| Line Number |
../DebugInfoTest/example_mips_dbg.ll
|
Hit count |
Line Number |
../DebugInfoTest/example_mips.ll
|
Hit count |
| 1 |
//===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===// |
--- |
1 |
//===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===// |
--- |
| 2 |
// |
--- |
2 |
// |
--- |
| 3 |
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
--- |
3 |
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
--- |
| 4 |
// See https://llvm.org/LICENSE.txt for license information. |
--- |
4 |
// See https://llvm.org/LICENSE.txt for license information. |
--- |
| 5 |
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
--- |
5 |
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
--- |
| 6 |
// |
--- |
6 |
// |
--- |
| 7 |
//===----------------------------------------------------------------------===// |
--- |
7 |
//===----------------------------------------------------------------------===// |
--- |
| 8 |
// |
--- |
8 |
// |
--- |
| 9 |
// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run |
--- |
9 |
// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run |
--- |
| 10 |
// both before and after the DAG is legalized. |
--- |
10 |
// both before and after the DAG is legalized. |
--- |
| 11 |
// |
--- |
11 |
// |
--- |
| 12 |
// This pass is not a substitute for the LLVM IR instcombine pass. This pass is |
--- |
12 |
// This pass is not a substitute for the LLVM IR instcombine pass. This pass is |
--- |
| 13 |
// primarily intended to handle simplification opportunities that are implicit |
--- |
13 |
// primarily intended to handle simplification opportunities that are implicit |
--- |
| 14 |
// in the LLVM IR and exposed by the various codegen lowering phases. |
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14 |
// in the LLVM IR and exposed by the various codegen lowering phases. |
--- |
| 15 |
// |
--- |
15 |
// |
--- |
| 16 |
//===----------------------------------------------------------------------===// |
--- |
16 |
//===----------------------------------------------------------------------===// |
--- |
| 17 |
|
--- |
17 |
|
--- |
| 18 |
#include "llvm/ADT/APFloat.h" |
--- |
18 |
#include "llvm/ADT/APFloat.h" |
--- |
| 19 |
#include "llvm/ADT/APInt.h" |
--- |
19 |
#include "llvm/ADT/APInt.h" |
--- |
| 20 |
#include "llvm/ADT/ArrayRef.h" |
--- |
20 |
#include "llvm/ADT/ArrayRef.h" |
--- |
| 21 |
#include "llvm/ADT/DenseMap.h" |
--- |
21 |
#include "llvm/ADT/DenseMap.h" |
--- |
| 22 |
#include "llvm/ADT/IntervalMap.h" |
--- |
22 |
#include "llvm/ADT/IntervalMap.h" |
--- |
| 23 |
#include "llvm/ADT/STLExtras.h" |
--- |
23 |
#include "llvm/ADT/STLExtras.h" |
--- |
| 24 |
#include "llvm/ADT/SetVector.h" |
--- |
24 |
#include "llvm/ADT/SetVector.h" |
--- |
| 25 |
#include "llvm/ADT/SmallBitVector.h" |
--- |
25 |
#include "llvm/ADT/SmallBitVector.h" |
--- |
| 26 |
#include "llvm/ADT/SmallPtrSet.h" |
--- |
26 |
#include "llvm/ADT/SmallPtrSet.h" |
--- |
| 27 |
#include "llvm/ADT/SmallSet.h" |
--- |
27 |
#include "llvm/ADT/SmallSet.h" |
--- |
| 28 |
#include "llvm/ADT/SmallVector.h" |
--- |
28 |
#include "llvm/ADT/SmallVector.h" |
--- |
| 29 |
#include "llvm/ADT/Statistic.h" |
--- |
29 |
#include "llvm/ADT/Statistic.h" |
--- |
| 30 |
#include "llvm/Analysis/AliasAnalysis.h" |
--- |
30 |
#include "llvm/Analysis/AliasAnalysis.h" |
--- |
| 31 |
#include "llvm/Analysis/MemoryLocation.h" |
--- |
31 |
#include "llvm/Analysis/MemoryLocation.h" |
--- |
| 32 |
#include "llvm/Analysis/TargetLibraryInfo.h" |
--- |
32 |
#include "llvm/Analysis/TargetLibraryInfo.h" |
--- |
| 33 |
#include "llvm/Analysis/ValueTracking.h" |
--- |
33 |
#include "llvm/Analysis/ValueTracking.h" |
--- |
| 34 |
#include "llvm/Analysis/VectorUtils.h" |
--- |
34 |
#include "llvm/Analysis/VectorUtils.h" |
--- |
| 35 |
#include "llvm/CodeGen/ByteProvider.h" |
--- |
35 |
#include "llvm/CodeGen/ByteProvider.h" |
--- |
| 36 |
#include "llvm/CodeGen/DAGCombine.h" |
--- |
36 |
#include "llvm/CodeGen/DAGCombine.h" |
--- |
| 37 |
#include "llvm/CodeGen/ISDOpcodes.h" |
--- |
37 |
#include "llvm/CodeGen/ISDOpcodes.h" |
--- |
| 38 |
#include "llvm/CodeGen/MachineFunction.h" |
--- |
38 |
#include "llvm/CodeGen/MachineFunction.h" |
--- |
| 39 |
#include "llvm/CodeGen/MachineMemOperand.h" |
--- |
39 |
#include "llvm/CodeGen/MachineMemOperand.h" |
--- |
| 40 |
#include "llvm/CodeGen/MachineValueType.h" |
--- |
40 |
#include "llvm/CodeGen/MachineValueType.h" |
--- |
| 41 |
#include "llvm/CodeGen/RuntimeLibcalls.h" |
--- |
41 |
#include "llvm/CodeGen/RuntimeLibcalls.h" |
--- |
| 42 |
#include "llvm/CodeGen/SelectionDAG.h" |
--- |
42 |
#include "llvm/CodeGen/SelectionDAG.h" |
--- |
| 43 |
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h" |
--- |
43 |
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h" |
--- |
| 44 |
#include "llvm/CodeGen/SelectionDAGNodes.h" |
--- |
44 |
#include "llvm/CodeGen/SelectionDAGNodes.h" |
--- |
| 45 |
#include "llvm/CodeGen/SelectionDAGTargetInfo.h" |
--- |
45 |
#include "llvm/CodeGen/SelectionDAGTargetInfo.h" |
--- |
| 46 |
#include "llvm/CodeGen/TargetLowering.h" |
--- |
46 |
#include "llvm/CodeGen/TargetLowering.h" |
--- |
| 47 |
#include "llvm/CodeGen/TargetRegisterInfo.h" |
--- |
47 |
#include "llvm/CodeGen/TargetRegisterInfo.h" |
--- |
| 48 |
#include "llvm/CodeGen/TargetSubtargetInfo.h" |
--- |
48 |
#include "llvm/CodeGen/TargetSubtargetInfo.h" |
--- |
| 49 |
#include "llvm/CodeGen/ValueTypes.h" |
--- |
49 |
#include "llvm/CodeGen/ValueTypes.h" |
--- |
| 50 |
#include "llvm/IR/Attributes.h" |
--- |
50 |
#include "llvm/IR/Attributes.h" |
--- |
| 51 |
#include "llvm/IR/Constant.h" |
--- |
51 |
#include "llvm/IR/Constant.h" |
--- |
| 52 |
#include "llvm/IR/DataLayout.h" |
--- |
52 |
#include "llvm/IR/DataLayout.h" |
--- |
| 53 |
#include "llvm/IR/DerivedTypes.h" |
--- |
53 |
#include "llvm/IR/DerivedTypes.h" |
--- |
| 54 |
#include "llvm/IR/Function.h" |
--- |
54 |
#include "llvm/IR/Function.h" |
--- |
| 55 |
#include "llvm/IR/Metadata.h" |
--- |
55 |
#include "llvm/IR/Metadata.h" |
--- |
| 56 |
#include "llvm/Support/Casting.h" |
--- |
56 |
#include "llvm/Support/Casting.h" |
--- |
| 57 |
#include "llvm/Support/CodeGen.h" |
--- |
57 |
#include "llvm/Support/CodeGen.h" |
--- |
| 58 |
#include "llvm/Support/CommandLine.h" |
--- |
58 |
#include "llvm/Support/CommandLine.h" |
--- |
| 59 |
#include "llvm/Support/Compiler.h" |
--- |
59 |
#include "llvm/Support/Compiler.h" |
--- |
| 60 |
#include "llvm/Support/Debug.h" |
--- |
60 |
#include "llvm/Support/Debug.h" |
--- |
| 61 |
#include "llvm/Support/ErrorHandling.h" |
--- |
61 |
#include "llvm/Support/ErrorHandling.h" |
--- |
| 62 |
#include "llvm/Support/KnownBits.h" |
--- |
62 |
#include "llvm/Support/KnownBits.h" |
--- |
| 63 |
#include "llvm/Support/MathExtras.h" |
--- |
63 |
#include "llvm/Support/MathExtras.h" |
--- |
| 64 |
#include "llvm/Support/raw_ostream.h" |
--- |
64 |
#include "llvm/Support/raw_ostream.h" |
--- |
| 65 |
#include "llvm/Target/TargetMachine.h" |
--- |
65 |
#include "llvm/Target/TargetMachine.h" |
--- |
| 66 |
#include "llvm/Target/TargetOptions.h" |
--- |
66 |
#include "llvm/Target/TargetOptions.h" |
--- |
| 67 |
#include |
--- |
67 |
#include |
--- |
| 68 |
#include |
--- |
68 |
#include |
--- |
| 69 |
#include |
--- |
69 |
#include |
--- |
| 70 |
#include |
--- |
70 |
#include |
--- |
| 71 |
#include |
--- |
71 |
#include |
--- |
| 72 |
#include |
--- |
72 |
#include |
--- |
| 73 |
#include |
--- |
73 |
#include |
--- |
| 74 |
#include |
--- |
74 |
#include |
--- |
| 75 |
#include |
--- |
75 |
#include |
--- |
| 76 |
#include |
--- |
76 |
#include |
--- |
| 77 |
|
--- |
77 |
|
--- |
| 78 |
using namespace llvm; |
--- |
78 |
using namespace llvm; |
--- |
| 79 |
|
--- |
79 |
|
--- |
| 80 |
#define DEBUG_TYPE "dagcombine" |
--- |
80 |
#define DEBUG_TYPE "dagcombine" |
--- |
| 81 |
|
--- |
81 |
|
--- |
| 82 |
STATISTIC(NodesCombined , "Number of dag nodes combined"); |
--- |
82 |
STATISTIC(NodesCombined , "Number of dag nodes combined"); |
--- |
| 83 |
STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); |
--- |
83 |
STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); |
--- |
| 84 |
STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); |
--- |
84 |
STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); |
--- |
| 85 |
STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); |
--- |
85 |
STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); |
--- |
| 86 |
STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); |
--- |
86 |
STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); |
--- |
| 87 |
STATISTIC(SlicedLoads, "Number of load sliced"); |
--- |
87 |
STATISTIC(SlicedLoads, "Number of load sliced"); |
--- |
| 88 |
STATISTIC(NumFPLogicOpsConv, "Number of logic ops converted to fp ops"); |
--- |
88 |
STATISTIC(NumFPLogicOpsConv, "Number of logic ops converted to fp ops"); |
--- |
| 89 |
|
--- |
89 |
|
--- |
| 90 |
static cl::opt |
--- |
90 |
static cl::opt |
--- |
| 91 |
CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, |
--- |
91 |
CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, |
--- |
| 92 |
cl::desc("Enable DAG combiner's use of IR alias analysis")); |
--- |
92 |
cl::desc("Enable DAG combiner's use of IR alias analysis")); |
--- |
| 93 |
|
--- |
93 |
|
--- |
| 94 |
static cl::opt |
--- |
94 |
static cl::opt |
--- |
| 95 |
UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true), |
--- |
95 |
UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true), |
--- |
| 96 |
cl::desc("Enable DAG combiner's use of TBAA")); |
--- |
96 |
cl::desc("Enable DAG combiner's use of TBAA")); |
--- |
| 97 |
|
--- |
97 |
|
--- |
| 98 |
#ifndef NDEBUG |
--- |
98 |
#ifndef NDEBUG |
--- |
| 99 |
static cl::opt |
--- |
99 |
static cl::opt |
--- |
| 100 |
CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden, |
--- |
100 |
CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden, |
--- |
| 101 |
cl::desc("Only use DAG-combiner alias analysis in this" |
--- |
101 |
cl::desc("Only use DAG-combiner alias analysis in this" |
--- |
| 102 |
" function")); |
--- |
102 |
" function")); |
--- |
| 103 |
#endif |
--- |
103 |
#endif |
--- |
| 104 |
|
--- |
104 |
|
--- |
| 105 |
/// Hidden option to stress test load slicing, i.e., when this option |
--- |
105 |
/// Hidden option to stress test load slicing, i.e., when this option |
--- |
| 106 |
/// is enabled, load slicing bypasses most of its profitability guards. |
--- |
106 |
/// is enabled, load slicing bypasses most of its profitability guards. |
--- |
| 107 |
static cl::opt |
--- |
107 |
static cl::opt |
--- |
| 108 |
StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden, |
--- |
108 |
StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden, |
--- |
| 109 |
cl::desc("Bypass the profitability model of load slicing"), |
--- |
109 |
cl::desc("Bypass the profitability model of load slicing"), |
--- |
| 110 |
cl::init(false)); |
--- |
110 |
cl::init(false)); |
--- |
| 111 |
|
--- |
111 |
|
--- |
| 112 |
static cl::opt |
--- |
112 |
static cl::opt |
--- |
| 113 |
MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true), |
--- |
113 |
MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true), |
--- |
| 114 |
cl::desc("DAG combiner may split indexing from loads")); |
--- |
114 |
cl::desc("DAG combiner may split indexing from loads")); |
--- |
| 115 |
|
--- |
115 |
|
--- |
| 116 |
static cl::opt |
--- |
116 |
static cl::opt |
--- |
| 117 |
EnableStoreMerging("combiner-store-merging", cl::Hidden, cl::init(true), |
--- |
117 |
EnableStoreMerging("combiner-store-merging", cl::Hidden, cl::init(true), |
--- |
| 118 |
cl::desc("DAG combiner enable merging multiple stores " |
--- |
118 |
cl::desc("DAG combiner enable merging multiple stores " |
--- |
| 119 |
"into a wider store")); |
--- |
119 |
"into a wider store")); |
--- |
| 120 |
|
--- |
120 |
|
--- |
| 121 |
static cl::opt TokenFactorInlineLimit( |
--- |
121 |
static cl::opt TokenFactorInlineLimit( |
--- |
| 122 |
"combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048), |
--- |
122 |
"combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048), |
--- |
| 123 |
cl::desc("Limit the number of operands to inline for Token Factors")); |
--- |
123 |
cl::desc("Limit the number of operands to inline for Token Factors")); |
--- |
| 124 |
|
--- |
124 |
|
--- |
| 125 |
static cl::opt StoreMergeDependenceLimit( |
--- |
125 |
static cl::opt StoreMergeDependenceLimit( |
--- |
| 126 |
"combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10), |
--- |
126 |
"combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10), |
--- |
| 127 |
cl::desc("Limit the number of times for the same StoreNode and RootNode " |
--- |
127 |
cl::desc("Limit the number of times for the same StoreNode and RootNode " |
--- |
| 128 |
"to bail out in store merging dependence check")); |
--- |
128 |
"to bail out in store merging dependence check")); |
--- |
| 129 |
|
--- |
129 |
|
--- |
| 130 |
static cl::opt EnableReduceLoadOpStoreWidth( |
--- |
130 |
static cl::opt EnableReduceLoadOpStoreWidth( |
--- |
| 131 |
"combiner-reduce-load-op-store-width", cl::Hidden, cl::init(true), |
--- |
131 |
"combiner-reduce-load-op-store-width", cl::Hidden, cl::init(true), |
--- |
| 132 |
cl::desc("DAG combiner enable reducing the width of load/op/store " |
--- |
132 |
cl::desc("DAG combiner enable reducing the width of load/op/store " |
--- |
| 133 |
"sequence")); |
--- |
133 |
"sequence")); |
--- |
| 134 |
|
--- |
134 |
|
--- |
| 135 |
static cl::opt EnableShrinkLoadReplaceStoreWithStore( |
--- |
135 |
static cl::opt EnableShrinkLoadReplaceStoreWithStore( |
--- |
| 136 |
"combiner-shrink-load-replace-store-with-store", cl::Hidden, cl::init(true), |
--- |
136 |
"combiner-shrink-load-replace-store-with-store", cl::Hidden, cl::init(true), |
--- |
| 137 |
cl::desc("DAG combiner enable load//store with " |
--- |
137 |
cl::desc("DAG combiner enable load//store with " |
--- |
| 138 |
"a narrower store")); |
--- |
138 |
"a narrower store")); |
--- |
| 139 |
|
--- |
139 |
|
--- |
| 140 |
static cl::opt EnableVectorFCopySignExtendRound( |
--- |
140 |
static cl::opt EnableVectorFCopySignExtendRound( |
--- |
| 141 |
"combiner-vector-fcopysign-extend-round", cl::Hidden, cl::init(false), |
--- |
141 |
"combiner-vector-fcopysign-extend-round", cl::Hidden, cl::init(false), |
--- |
| 142 |
cl::desc( |
--- |
142 |
cl::desc( |
--- |
| 143 |
"Enable merging extends and rounds into FCOPYSIGN on vector types")); |
--- |
143 |
"Enable merging extends and rounds into FCOPYSIGN on vector types")); |
--- |
| 144 |
|
--- |
144 |
|
--- |
| 145 |
namespace { |
--- |
145 |
namespace { |
--- |
| 146 |
|
--- |
146 |
|
--- |
| 147 |
class DAGCombiner { |
--- |
147 |
class DAGCombiner { |
--- |
| 148 |
SelectionDAG &DAG; |
--- |
148 |
SelectionDAG &DAG; |
--- |
| 149 |
const TargetLowering &TLI; |
--- |
149 |
const TargetLowering &TLI; |
--- |
| 150 |
const SelectionDAGTargetInfo *STI; |
--- |
150 |
const SelectionDAGTargetInfo *STI; |
--- |
| 151 |
CombineLevel Level = BeforeLegalizeTypes; |
--- |
151 |
CombineLevel Level = BeforeLegalizeTypes; |
--- |
| 152 |
CodeGenOpt::Level OptLevel; |
--- |
152 |
CodeGenOpt::Level OptLevel; |
--- |
| 153 |
bool LegalDAG = false; |
--- |
153 |
bool LegalDAG = false; |
--- |
| 154 |
bool LegalOperations = false; |
--- |
154 |
bool LegalOperations = false; |
--- |
| 155 |
bool LegalTypes = false; |
--- |
155 |
bool LegalTypes = false; |
--- |
| 156 |
bool ForCodeSize; |
--- |
156 |
bool ForCodeSize; |
--- |
| 157 |
bool DisableGenericCombines; |
--- |
157 |
bool DisableGenericCombines; |
--- |
| 158 |
|
--- |
158 |
|
--- |
| 159 |
/// Worklist of all of the nodes that need to be simplified. |
--- |
159 |
/// Worklist of all of the nodes that need to be simplified. |
--- |
| 160 |
/// |
--- |
160 |
/// |
--- |
| 161 |
/// This must behave as a stack -- new nodes to process are pushed onto the |
--- |
161 |
/// This must behave as a stack -- new nodes to process are pushed onto the |
--- |
| 162 |
/// back and when processing we pop off of the back. |
--- |
162 |
/// back and when processing we pop off of the back. |
--- |
| 163 |
/// |
--- |
163 |
/// |
--- |
| 164 |
/// The worklist will not contain duplicates but may contain null entries |
--- |
164 |
/// The worklist will not contain duplicates but may contain null entries |
--- |
| 165 |
/// due to nodes being deleted from the underlying DAG. |
--- |
165 |
/// due to nodes being deleted from the underlying DAG. |
--- |
| 166 |
SmallVector Worklist; |
--- |
166 |
SmallVector Worklist; |
--- |
| 167 |
|
--- |
167 |
|
--- |
| 168 |
/// Mapping from an SDNode to its position on the worklist. |
--- |
168 |
/// Mapping from an SDNode to its position on the worklist. |
--- |
| 169 |
/// |
--- |
169 |
/// |
--- |
| 170 |
/// This is used to find and remove nodes from the worklist (by nulling |
--- |
170 |
/// This is used to find and remove nodes from the worklist (by nulling |
--- |
| 171 |
/// them) when they are deleted from the underlying DAG. It relies on |
--- |
171 |
/// them) when they are deleted from the underlying DAG. It relies on |
--- |
| 172 |
/// stable indices of nodes within the worklist. |
--- |
172 |
/// stable indices of nodes within the worklist. |
--- |
| 173 |
DenseMap WorklistMap; |
--- |
173 |
DenseMap WorklistMap; |
--- |
| 174 |
|
--- |
174 |
|
--- |
| 175 |
/// This records all nodes attempted to be added to the worklist since we |
--- |
175 |
/// This records all nodes attempted to be added to the worklist since we |
--- |
| 176 |
/// considered a new worklist entry. As we keep do not add duplicate nodes |
--- |
176 |
/// considered a new worklist entry. As we keep do not add duplicate nodes |
--- |
| 177 |
/// in the worklist, this is different from the tail of the worklist. |
--- |
177 |
/// in the worklist, this is different from the tail of the worklist. |
--- |
| 178 |
SmallSetVector PruningList; |
--- |
178 |
SmallSetVector PruningList; |
--- |
| 179 |
|
--- |
179 |
|
--- |
| 180 |
/// Set of nodes which have been combined (at least once). |
--- |
180 |
/// Set of nodes which have been combined (at least once). |
--- |
| 181 |
/// |
--- |
181 |
/// |
--- |
| 182 |
/// This is used to allow us to reliably add any operands of a DAG node |
--- |
182 |
/// This is used to allow us to reliably add any operands of a DAG node |
--- |
| 183 |
/// which have not yet been combined to the worklist. |
--- |
183 |
/// which have not yet been combined to the worklist. |
--- |
| 184 |
SmallPtrSet CombinedNodes; |
--- |
184 |
SmallPtrSet CombinedNodes; |
--- |
| 185 |
|
--- |
185 |
|
--- |
| 186 |
/// Map from candidate StoreNode to the pair of RootNode and count. |
--- |
186 |
/// Map from candidate StoreNode to the pair of RootNode and count. |
--- |
| 187 |
/// The count is used to track how many times we have seen the StoreNode |
--- |
187 |
/// The count is used to track how many times we have seen the StoreNode |
--- |
| 188 |
/// with the same RootNode bail out in dependence check. If we have seen |
--- |
188 |
/// with the same RootNode bail out in dependence check. If we have seen |
--- |
| 189 |
/// the bail out for the same pair many times over a limit, we won't |
--- |
189 |
/// the bail out for the same pair many times over a limit, we won't |
--- |
| 190 |
/// consider the StoreNode with the same RootNode as store merging |
--- |
190 |
/// consider the StoreNode with the same RootNode as store merging |
--- |
| 191 |
/// candidate again. |
--- |
191 |
/// candidate again. |
--- |
| 192 |
DenseMap> StoreRootCountMap; |
--- |
192 |
DenseMap> StoreRootCountMap; |
--- |
| 193 |
|
--- |
193 |
|
--- |
| 194 |
// AA - Used for DAG load/store alias analysis. |
--- |
194 |
// AA - Used for DAG load/store alias analysis. |
--- |
| 195 |
AliasAnalysis *AA; |
--- |
195 |
AliasAnalysis *AA; |
--- |
| 196 |
|
--- |
196 |
|
--- |
| 197 |
/// When an instruction is simplified, add all users of the instruction to |
--- |
197 |
/// When an instruction is simplified, add all users of the instruction to |
--- |
| 198 |
/// the work lists because they might get more simplified now. |
--- |
198 |
/// the work lists because they might get more simplified now. |
--- |
| 199 |
void AddUsersToWorklist(SDNode *N) { |
2 |
199 |
void AddUsersToWorklist(SDNode *N) { |
2 |
| 200 |
for (SDNode *Node : N->uses()) |
5 |
200 |
for (SDNode *Node : N->uses()) |
5 |
| 201 |
AddToWorklist(Node); |
3 |
201 |
AddToWorklist(Node); |
3 |
| 202 |
} |
2 |
202 |
} |
2 |
| 203 |
|
--- |
203 |
|
--- |
| 204 |
/// Convenient shorthand to add a node and all of its user to the worklist. |
--- |
204 |
/// Convenient shorthand to add a node and all of its user to the worklist. |
--- |
| 205 |
void AddToWorklistWithUsers(SDNode *N) { |
2 |
205 |
void AddToWorklistWithUsers(SDNode *N) { |
2 |
| 206 |
AddUsersToWorklist(N); |
2 |
206 |
AddUsersToWorklist(N); |
2 |
| 207 |
AddToWorklist(N); |
2 |
207 |
AddToWorklist(N); |
2 |
| 208 |
} |
2 |
208 |
} |
2 |
| 209 |
|
--- |
209 |
|
--- |
| 210 |
// Prune potentially dangling nodes. This is called after |
--- |
210 |
// Prune potentially dangling nodes. This is called after |
--- |
| 211 |
// any visit to a node, but should also be called during a visit after any |
--- |
211 |
// any visit to a node, but should also be called during a visit after any |
--- |
| 212 |
// failed combine which may have created a DAG node. |
--- |
212 |
// failed combine which may have created a DAG node. |
--- |
| 213 |
void clearAddedDanglingWorklistEntries() { |
112 |
213 |
void clearAddedDanglingWorklistEntries() { |
112 |
| 214 |
// Check any nodes added to the worklist to see if they are prunable. |
--- |
214 |
// Check any nodes added to the worklist to see if they are prunable. |
--- |
| 215 |
while (!PruningList.empty()) { |
259 |
215 |
while (!PruningList.empty()) { |
259 |
| 216 |
auto *N = PruningList.pop_back_val(); |
147 |
216 |
auto *N = PruningList.pop_back_val(); |
147 |
| 217 |
if (N->use_empty()) |
147 |
217 |
if (N->use_empty()) |
147 |
| 218 |
recursivelyDeleteUnusedNodes(N); |
4 |
218 |
recursivelyDeleteUnusedNodes(N); |
4 |
| 219 |
} |
--- |
219 |
} |
--- |
| 220 |
} |
112 |
220 |
} |
112 |
| 221 |
|
--- |
221 |
|
--- |
| 222 |
SDNode *getNextWorklistEntry() { |
112 |
222 |
SDNode *getNextWorklistEntry() { |
112 |
| 223 |
// Before we do any work, remove nodes that are not in use. |
--- |
223 |
// Before we do any work, remove nodes that are not in use. |
--- |
| 224 |
clearAddedDanglingWorklistEntries(); |
112 |
224 |
clearAddedDanglingWorklistEntries(); |
112 |
| 225 |
SDNode *N = nullptr; |
112 |
225 |
SDNode *N = nullptr; |
112 |
| 226 |
// The Worklist holds the SDNodes in order, but it may contain null |
--- |
226 |
// The Worklist holds the SDNodes in order, but it may contain null |
--- |
| 227 |
// entries. |
--- |
227 |
// entries. |
--- |
| 228 |
while (!N && !Worklist.empty()) { |
225 |
228 |
while (!N && !Worklist.empty()) { |
225 |
| 229 |
N = Worklist.pop_back_val(); |
113 |
229 |
N = Worklist.pop_back_val(); |
113 |
| 230 |
} |
--- |
230 |
} |
--- |
| 231 |
|
--- |
231 |
|
--- |
| 232 |
if (N) { |
112 |
232 |
if (N) { |
112 |
| 233 |
bool GoodWorklistEntry = WorklistMap.erase(N); |
103 |
233 |
bool GoodWorklistEntry = WorklistMap.erase(N); |
103 |
| 234 |
(void)GoodWorklistEntry; |
--- |
234 |
(void)GoodWorklistEntry; |
--- |
| 235 |
assert(GoodWorklistEntry && |
103 |
235 |
assert(GoodWorklistEntry && |
103 |
| 236 |
"Found a worklist entry without a corresponding map entry!"); |
--- |
236 |
"Found a worklist entry without a corresponding map entry!"); |
--- |
| 237 |
} |
--- |
237 |
} |
--- |
| 238 |
return N; |
112 |
238 |
return N; |
112 |
| 239 |
} |
--- |
239 |
} |
--- |
| 240 |
|
--- |
240 |
|
--- |
| 241 |
/// Call the node-specific routine that folds each particular type of node. |
--- |
241 |
/// Call the node-specific routine that folds each particular type of node. |
--- |
| 242 |
SDValue visit(SDNode *N); |
--- |
242 |
SDValue visit(SDNode *N); |
--- |
| 243 |
|
--- |
243 |
|
--- |
| 244 |
public: |
--- |
244 |
public: |
--- |
| 245 |
DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL) |
9 |
245 |
DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL) |
9 |
| 246 |
: DAG(D), TLI(D.getTargetLoweringInfo()), |
9 |
246 |
: DAG(D), TLI(D.getTargetLoweringInfo()), |
9 |
| 247 |
STI(D.getSubtarget().getSelectionDAGInfo()), OptLevel(OL), AA(AA) { |
9 |
247 |
STI(D.getSubtarget().getSelectionDAGInfo()), OptLevel(OL), AA(AA) { |
9 |
| 248 |
ForCodeSize = DAG.shouldOptForSize(); |
9 |
248 |
ForCodeSize = DAG.shouldOptForSize(); |
9 |
| 249 |
DisableGenericCombines = STI && STI->disableGenericCombines(OptLevel); |
9 |
249 |
DisableGenericCombines = STI && STI->disableGenericCombines(OptLevel); |
9 |
| 250 |
|
--- |
250 |
|
--- |
| 251 |
MaximumLegalStoreInBits = 0; |
9 |
251 |
MaximumLegalStoreInBits = 0; |
9 |
| 252 |
// We use the minimum store size here, since that's all we can guarantee |
--- |
252 |
// We use the minimum store size here, since that's all we can guarantee |
--- |
| 253 |
// for the scalable vector types. |
--- |
253 |
// for the scalable vector types. |
--- |
| 254 |
for (MVT VT : MVT::all_valuetypes()) |
1782 |
254 |
for (MVT VT : MVT::all_valuetypes()) |
1782 |
| 255 |
if (EVT(VT).isSimple() && VT != MVT::Other && |
5310 |
255 |
if (EVT(VT).isSimple() && VT != MVT::Other && |
5310 |
| 256 |
TLI.isTypeLegal(EVT(VT)) && |
5310 |
256 |
TLI.isTypeLegal(EVT(VT)) && |
5310 |
| 257 |
VT.getSizeInBits().getKnownMinValue() >= MaximumLegalStoreInBits) |
1800 |
257 |
VT.getSizeInBits().getKnownMinValue() >= MaximumLegalStoreInBits) |
1800 |
| 258 |
MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinValue(); |
27 |
258 |
MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinValue(); |
27 |
| 259 |
} |
9 |
259 |
} |
9 |
| 260 |
|
--- |
260 |
|
--- |
| 261 |
void ConsiderForPruning(SDNode *N) { |
162 |
261 |
void ConsiderForPruning(SDNode *N) { |
162 |
| 262 |
// Mark this for potential pruning. |
--- |
262 |
// Mark this for potential pruning. |
--- |
| 263 |
PruningList.insert(N); |
162 |
263 |
PruningList.insert(N); |
162 |
| 264 |
} |
162 |
264 |
} |
162 |
| 265 |
|
--- |
265 |
|
--- |
| 266 |
/// Add to the worklist making sure its instance is at the back (next to be |
--- |
266 |
/// Add to the worklist making sure its instance is at the back (next to be |
--- |
| 267 |
/// processed.) |
--- |
267 |
/// processed.) |
--- |
| 268 |
void AddToWorklist(SDNode *N, bool IsCandidateForPruning = true) { |
254 |
268 |
void AddToWorklist(SDNode *N, bool IsCandidateForPruning = true) { |
254 |
| 269 |
assert(N->getOpcode() != ISD::DELETED_NODE && |
254 |
269 |
assert(N->getOpcode() != ISD::DELETED_NODE && |
254 |
| 270 |
"Deleted Node added to Worklist"); |
--- |
270 |
"Deleted Node added to Worklist"); |
--- |
| 271 |
|
--- |
271 |
|
--- |
| 272 |
// Skip handle nodes as they can't usefully be combined and confuse the |
--- |
272 |
// Skip handle nodes as they can't usefully be combined and confuse the |
--- |
| 273 |
// zero-use deletion strategy. |
--- |
273 |
// zero-use deletion strategy. |
--- |
| 274 |
if (N->getOpcode() == ISD::HANDLENODE) |
254 |
274 |
if (N->getOpcode() == ISD::HANDLENODE) |
254 |
| 275 |
return; |
0 |
275 |
return; |
0 |
| 276 |
|
--- |
276 |
|
--- |
| 277 |
if (IsCandidateForPruning) |
254 |
277 |
if (IsCandidateForPruning) |
254 |
| 278 |
ConsiderForPruning(N); |
159 |
278 |
ConsiderForPruning(N); |
159 |
| 279 |
|
--- |
279 |
|
--- |
| 280 |
if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second) |
254 |
280 |
if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second) |
254 |
| 281 |
Worklist.push_back(N); |
113 |
281 |
Worklist.push_back(N); |
113 |
| 282 |
} |
--- |
282 |
} |
--- |
| 283 |
|
--- |
283 |
|
--- |
| 284 |
/// Remove all instances of N from the worklist. |
--- |
284 |
/// Remove all instances of N from the worklist. |
--- |
| 285 |
void removeFromWorklist(SDNode *N) { |
11 |
285 |
void removeFromWorklist(SDNode *N) { |
11 |
| 286 |
CombinedNodes.erase(N); |
11 |
286 |
CombinedNodes.erase(N); |
11 |
| 287 |
PruningList.remove(N); |
11 |
287 |
PruningList.remove(N); |
11 |
| 288 |
StoreRootCountMap.erase(N); |
11 |
288 |
StoreRootCountMap.erase(N); |
11 |
| 289 |
|
--- |
289 |
|
--- |
| 290 |
auto It = WorklistMap.find(N); |
11 |
290 |
auto It = WorklistMap.find(N); |
11 |
| 291 |
if (It == WorklistMap.end()) |
11 |
291 |
if (It == WorklistMap.end()) |
11 |
| 292 |
return; // Not in the worklist. |
1 |
292 |
return; // Not in the worklist. |
1 |
| 293 |
|
--- |
293 |
|
--- |
| 294 |
// Null out the entry rather than erasing it to avoid a linear operation. |
--- |
294 |
// Null out the entry rather than erasing it to avoid a linear operation. |
--- |
| 295 |
Worklist[It->second] = nullptr; |
10 |
295 |
Worklist[It->second] = nullptr; |
10 |
| 296 |
WorklistMap.erase(It); |
10 |
296 |
WorklistMap.erase(It); |
10 |
| 297 |
} |
--- |
297 |
} |
--- |
| 298 |
|
--- |
298 |
|
--- |
| 299 |
void deleteAndRecombine(SDNode *N); |
--- |
299 |
void deleteAndRecombine(SDNode *N); |
--- |
| 300 |
bool recursivelyDeleteUnusedNodes(SDNode *N); |
--- |
300 |
bool recursivelyDeleteUnusedNodes(SDNode *N); |
--- |
| 301 |
|
--- |
301 |
|
--- |
| 302 |
/// Replaces all uses of the results of one DAG node with new values. |
--- |
302 |
/// Replaces all uses of the results of one DAG node with new values. |
--- |
| 303 |
SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, |
--- |
303 |
SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, |
--- |
| 304 |
bool AddTo = true); |
--- |
304 |
bool AddTo = true); |
--- |
| 305 |
|
--- |
305 |
|
--- |
| 306 |
/// Replaces all uses of the results of one DAG node with new values. |
--- |
306 |
/// Replaces all uses of the results of one DAG node with new values. |
--- |
| 307 |
SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { |
0 |
307 |
SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { |
0 |
| 308 |
return CombineTo(N, &Res, 1, AddTo); |
0 |
308 |
return CombineTo(N, &Res, 1, AddTo); |
0 |
| 309 |
} |
--- |
309 |
} |
--- |
| 310 |
|
--- |
310 |
|
--- |
| 311 |
/// Replaces all uses of the results of one DAG node with new values. |
--- |
311 |
/// Replaces all uses of the results of one DAG node with new values. |
--- |
| 312 |
SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, |
0 |
312 |
SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, |
0 |
| 313 |
bool AddTo = true) { |
--- |
313 |
bool AddTo = true) { |
--- |
| 314 |
SDValue To[] = { Res0, Res1 }; |
0 |
314 |
SDValue To[] = { Res0, Res1 }; |
0 |
| 315 |
return CombineTo(N, To, 2, AddTo); |
0 |
315 |
return CombineTo(N, To, 2, AddTo); |
0 |
| 316 |
} |
--- |
316 |
} |
--- |
| 317 |
|
--- |
317 |
|
--- |
| 318 |
void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); |
--- |
318 |
void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); |
--- |
| 319 |
|
--- |
319 |
|
--- |
| 320 |
private: |
--- |
320 |
private: |
--- |
| 321 |
unsigned MaximumLegalStoreInBits; |
--- |
321 |
unsigned MaximumLegalStoreInBits; |
--- |
| 322 |
|
--- |
322 |
|
--- |
| 323 |
/// Check the specified integer node value to see if it can be simplified or |
--- |
323 |
/// Check the specified integer node value to see if it can be simplified or |
--- |
| 324 |
/// if things it uses can be simplified by bit propagation. |
--- |
324 |
/// if things it uses can be simplified by bit propagation. |
--- |
| 325 |
/// If so, return true. |
--- |
325 |
/// If so, return true. |
--- |
| 326 |
bool SimplifyDemandedBits(SDValue Op) { |
2 |
326 |
bool SimplifyDemandedBits(SDValue Op) { |
2 |
| 327 |
unsigned BitWidth = Op.getScalarValueSizeInBits(); |
2 |
327 |
unsigned BitWidth = Op.getScalarValueSizeInBits(); |
2 |
| 328 |
APInt DemandedBits = APInt::getAllOnes(BitWidth); |
2 |
328 |
APInt DemandedBits = APInt::getAllOnes(BitWidth); |
2 |
| 329 |
return SimplifyDemandedBits(Op, DemandedBits); |
2 |
329 |
return SimplifyDemandedBits(Op, DemandedBits); |
2 |
| 330 |
} |
2 |
330 |
} |
2 |
| 331 |
|
--- |
331 |
|
--- |
| 332 |
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits) { |
2 |
332 |
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits) { |
2 |
| 333 |
TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); |
2 |
333 |
TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); |
2 |
| 334 |
KnownBits Known; |
2 |
334 |
KnownBits Known; |
2 |
| 335 |
if (!TLI.SimplifyDemandedBits(Op, DemandedBits, Known, TLO, 0, false)) |
2 |
335 |
if (!TLI.SimplifyDemandedBits(Op, DemandedBits, Known, TLO, 0, false)) |
2 |
| 336 |
return false; |
1 |
336 |
return false; |
1 |
| 337 |
|
--- |
337 |
|
--- |
| 338 |
// Revisit the node. |
--- |
338 |
// Revisit the node. |
--- |
| 339 |
AddToWorklist(Op.getNode()); |
1 |
339 |
AddToWorklist(Op.getNode()); |
1 |
| 340 |
|
--- |
340 |
|
--- |
| 341 |
CommitTargetLoweringOpt(TLO); |
1 |
341 |
CommitTargetLoweringOpt(TLO); |
1 |
| 342 |
return true; |
1 |
342 |
return true; |
1 |
| 343 |
} |
2 |
343 |
} |
2 |
| 344 |
|
--- |
344 |
|
--- |
| 345 |
/// Check the specified vector node value to see if it can be simplified or |
--- |
345 |
/// Check the specified vector node value to see if it can be simplified or |
--- |
| 346 |
/// if things it uses can be simplified as it only uses some of the |
--- |
346 |
/// if things it uses can be simplified as it only uses some of the |
--- |
| 347 |
/// elements. If so, return true. |
--- |
347 |
/// elements. If so, return true. |
--- |
| 348 |
bool SimplifyDemandedVectorElts(SDValue Op) { |
0 |
348 |
bool SimplifyDemandedVectorElts(SDValue Op) { |
0 |
| 349 |
// TODO: For now just pretend it cannot be simplified. |
--- |
349 |
// TODO: For now just pretend it cannot be simplified. |
--- |
| 350 |
if (Op.getValueType().isScalableVector()) |
0 |
350 |
if (Op.getValueType().isScalableVector()) |
0 |
| 351 |
return false; |
0 |
351 |
return false; |
0 |
| 352 |
|
--- |
352 |
|
--- |
| 353 |
unsigned NumElts = Op.getValueType().getVectorNumElements(); |
0 |
353 |
unsigned NumElts = Op.getValueType().getVectorNumElements(); |
0 |
| 354 |
APInt DemandedElts = APInt::getAllOnes(NumElts); |
0 |
354 |
APInt DemandedElts = APInt::getAllOnes(NumElts); |
0 |
| 355 |
return SimplifyDemandedVectorElts(Op, DemandedElts); |
0 |
355 |
return SimplifyDemandedVectorElts(Op, DemandedElts); |
0 |
| 356 |
} |
0 |
356 |
} |
0 |
| 357 |
|
--- |
357 |
|
--- |
| 358 |
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, |
--- |
358 |
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, |
--- |
| 359 |
const APInt &DemandedElts, |
--- |
359 |
const APInt &DemandedElts, |
--- |
| 360 |
bool AssumeSingleUse = false); |
--- |
360 |
bool AssumeSingleUse = false); |
--- |
| 361 |
bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts, |
--- |
361 |
bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts, |
--- |
| 362 |
bool AssumeSingleUse = false); |
--- |
362 |
bool AssumeSingleUse = false); |
--- |
| 363 |
|
--- |
363 |
|
--- |
| 364 |
bool CombineToPreIndexedLoadStore(SDNode *N); |
--- |
364 |
bool CombineToPreIndexedLoadStore(SDNode *N); |
--- |
| 365 |
bool CombineToPostIndexedLoadStore(SDNode *N); |
--- |
365 |
bool CombineToPostIndexedLoadStore(SDNode *N); |
--- |
| 366 |
SDValue SplitIndexingFromLoad(LoadSDNode *LD); |
--- |
366 |
SDValue SplitIndexingFromLoad(LoadSDNode *LD); |
--- |
| 367 |
bool SliceUpLoad(SDNode *N); |
--- |
367 |
bool SliceUpLoad(SDNode *N); |
--- |
| 368 |
|
--- |
368 |
|
--- |
| 369 |
// Looks up the chain to find a unique (unaliased) store feeding the passed |
--- |
369 |
// Looks up the chain to find a unique (unaliased) store feeding the passed |
--- |
| 370 |
// load. If no such store is found, returns a nullptr. |
--- |
370 |
// load. If no such store is found, returns a nullptr. |
--- |
| 371 |
// Note: This will look past a CALLSEQ_START if the load is chained to it so |
--- |
371 |
// Note: This will look past a CALLSEQ_START if the load is chained to it so |
--- |
| 372 |
// so that it can find stack stores for byval params. |
--- |
372 |
// so that it can find stack stores for byval params. |
--- |
| 373 |
StoreSDNode *getUniqueStoreFeeding(LoadSDNode *LD, int64_t &Offset); |
--- |
373 |
StoreSDNode *getUniqueStoreFeeding(LoadSDNode *LD, int64_t &Offset); |
--- |
| 374 |
// Scalars have size 0 to distinguish from singleton vectors. |
--- |
374 |
// Scalars have size 0 to distinguish from singleton vectors. |
--- |
| 375 |
SDValue ForwardStoreValueToDirectLoad(LoadSDNode *LD); |
--- |
375 |
SDValue ForwardStoreValueToDirectLoad(LoadSDNode *LD); |
--- |
| 376 |
bool getTruncatedStoreValue(StoreSDNode *ST, SDValue &Val); |
--- |
376 |
bool getTruncatedStoreValue(StoreSDNode *ST, SDValue &Val); |
--- |
| 377 |
bool extendLoadedValueToExtension(LoadSDNode *LD, SDValue &Val); |
--- |
377 |
bool extendLoadedValueToExtension(LoadSDNode *LD, SDValue &Val); |
--- |
| 378 |
|
--- |
378 |
|
--- |
| 379 |
/// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed |
--- |
379 |
/// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed |
--- |
| 380 |
/// load. |
--- |
380 |
/// load. |
--- |
| 381 |
/// |
--- |
381 |
/// |
--- |
| 382 |
/// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced. |
--- |
382 |
/// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced. |
--- |
| 383 |
/// \param InVecVT type of the input vector to EVE with bitcasts resolved. |
--- |
383 |
/// \param InVecVT type of the input vector to EVE with bitcasts resolved. |
--- |
| 384 |
/// \param EltNo index of the vector element to load. |
--- |
384 |
/// \param EltNo index of the vector element to load. |
--- |
| 385 |
/// \param OriginalLoad load that EVE came from to be replaced. |
--- |
385 |
/// \param OriginalLoad load that EVE came from to be replaced. |
--- |
| 386 |
/// \returns EVE on success SDValue() on failure. |
--- |
386 |
/// \returns EVE on success SDValue() on failure. |
--- |
| 387 |
SDValue scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT, |
--- |
387 |
SDValue scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT, |
--- |
| 388 |
SDValue EltNo, |
--- |
388 |
SDValue EltNo, |
--- |
| 389 |
LoadSDNode *OriginalLoad); |
--- |
389 |
LoadSDNode *OriginalLoad); |
--- |
| 390 |
void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); |
--- |
390 |
void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); |
--- |
| 391 |
SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); |
--- |
391 |
SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); |
--- |
| 392 |
SDValue SExtPromoteOperand(SDValue Op, EVT PVT); |
--- |
392 |
SDValue SExtPromoteOperand(SDValue Op, EVT PVT); |
--- |
| 393 |
SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); |
--- |
393 |
SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); |
--- |
| 394 |
SDValue PromoteIntBinOp(SDValue Op); |
--- |
394 |
SDValue PromoteIntBinOp(SDValue Op); |
--- |
| 395 |
SDValue PromoteIntShiftOp(SDValue Op); |
--- |
395 |
SDValue PromoteIntShiftOp(SDValue Op); |
--- |
| 396 |
SDValue PromoteExtend(SDValue Op); |
--- |
396 |
SDValue PromoteExtend(SDValue Op); |
--- |
| 397 |
bool PromoteLoad(SDValue Op); |
--- |
397 |
bool PromoteLoad(SDValue Op); |
--- |
| 398 |
|
--- |
398 |
|
--- |
| 399 |
SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS, |
--- |
399 |
SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS, |
--- |
| 400 |
SDValue RHS, SDValue True, SDValue False, |
--- |
400 |
SDValue RHS, SDValue True, SDValue False, |
--- |
| 401 |
ISD::CondCode CC); |
--- |
401 |
ISD::CondCode CC); |
--- |
| 402 |
|
--- |
402 |
|
--- |
| 403 |
/// Call the node-specific routine that knows how to fold each |
--- |
403 |
/// Call the node-specific routine that knows how to fold each |
--- |
| 404 |
/// particular type of node. If that doesn't do anything, try the |
--- |
404 |
/// particular type of node. If that doesn't do anything, try the |
--- |
| 405 |
/// target-specific DAG combines. |
--- |
405 |
/// target-specific DAG combines. |
--- |
| 406 |
SDValue combine(SDNode *N); |
--- |
406 |
SDValue combine(SDNode *N); |
--- |
| 407 |
|
--- |
407 |
|
--- |
| 408 |
// Visitation implementation - Implement dag node combining for different |
--- |
408 |
// Visitation implementation - Implement dag node combining for different |
--- |
| 409 |
// node types. The semantics are as follows: |
--- |
409 |
// node types. The semantics are as follows: |
--- |
| 410 |
// Return Value: |
--- |
410 |
// Return Value: |
--- |
| 411 |
// SDValue.getNode() == 0 - No change was made |
--- |
411 |
// SDValue.getNode() == 0 - No change was made |
--- |
| 412 |
// SDValue.getNode() == N - N was replaced, is dead and has been handled. |
--- |
412 |
// SDValue.getNode() == N - N was replaced, is dead and has been handled. |
--- |
| 413 |
// otherwise - N should be replaced by the returned Operand. |
--- |
413 |
// otherwise - N should be replaced by the returned Operand. |
--- |
| 414 |
// |
--- |
414 |
// |
--- |
| 415 |
SDValue visitTokenFactor(SDNode *N); |
--- |
415 |
SDValue visitTokenFactor(SDNode *N); |
--- |
| 416 |
SDValue visitMERGE_VALUES(SDNode *N); |
--- |
416 |
SDValue visitMERGE_VALUES(SDNode *N); |
--- |
| 417 |
SDValue visitADD(SDNode *N); |
--- |
417 |
SDValue visitADD(SDNode *N); |
--- |
| 418 |
SDValue visitADDLike(SDNode *N); |
--- |
418 |
SDValue visitADDLike(SDNode *N); |
--- |
| 419 |
SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference); |
--- |
419 |
SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference); |
--- |
| 420 |
SDValue visitSUB(SDNode *N); |
--- |
420 |
SDValue visitSUB(SDNode *N); |
--- |
| 421 |
SDValue visitADDSAT(SDNode *N); |
--- |
421 |
SDValue visitADDSAT(SDNode *N); |
--- |
| 422 |
SDValue visitSUBSAT(SDNode *N); |
--- |
422 |
SDValue visitSUBSAT(SDNode *N); |
--- |
| 423 |
SDValue visitADDC(SDNode *N); |
--- |
423 |
SDValue visitADDC(SDNode *N); |
--- |
| 424 |
SDValue visitADDO(SDNode *N); |
--- |
424 |
SDValue visitADDO(SDNode *N); |
--- |
| 425 |
SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N); |
--- |
425 |
SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N); |
--- |
| 426 |
SDValue visitSUBC(SDNode *N); |
--- |
426 |
SDValue visitSUBC(SDNode *N); |
--- |
| 427 |
SDValue visitSUBO(SDNode *N); |
--- |
427 |
SDValue visitSUBO(SDNode *N); |
--- |
| 428 |
SDValue visitADDE(SDNode *N); |
--- |
428 |
SDValue visitADDE(SDNode *N); |
--- |
| 429 |
SDValue visitUADDO_CARRY(SDNode *N); |
--- |
429 |
SDValue visitUADDO_CARRY(SDNode *N); |
--- |
| 430 |
SDValue visitSADDO_CARRY(SDNode *N); |
--- |
430 |
SDValue visitSADDO_CARRY(SDNode *N); |
--- |
| 431 |
SDValue visitUADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, |
--- |
431 |
SDValue visitUADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, |
--- |
| 432 |
SDNode *N); |
--- |
432 |
SDNode *N); |
--- |
| 433 |
SDValue visitSUBE(SDNode *N); |
--- |
433 |
SDValue visitSUBE(SDNode *N); |
--- |
| 434 |
SDValue visitUSUBO_CARRY(SDNode *N); |
--- |
434 |
SDValue visitUSUBO_CARRY(SDNode *N); |
--- |
| 435 |
SDValue visitSSUBO_CARRY(SDNode *N); |
--- |
435 |
SDValue visitSSUBO_CARRY(SDNode *N); |
--- |
| 436 |
SDValue visitMUL(SDNode *N); |
--- |
436 |
SDValue visitMUL(SDNode *N); |
--- |
| 437 |
SDValue visitMULFIX(SDNode *N); |
--- |
437 |
SDValue visitMULFIX(SDNode *N); |
--- |
| 438 |
SDValue useDivRem(SDNode *N); |
--- |
438 |
SDValue useDivRem(SDNode *N); |
--- |
| 439 |
SDValue visitSDIV(SDNode *N); |
--- |
439 |
SDValue visitSDIV(SDNode *N); |
--- |
| 440 |
SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N); |
--- |
440 |
SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N); |
--- |
| 441 |
SDValue visitUDIV(SDNode *N); |
--- |
441 |
SDValue visitUDIV(SDNode *N); |
--- |
| 442 |
SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N); |
--- |
442 |
SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N); |
--- |
| 443 |
SDValue visitREM(SDNode *N); |
--- |
443 |
SDValue visitREM(SDNode *N); |
--- |
| 444 |
SDValue visitMULHU(SDNode *N); |
--- |
444 |
SDValue visitMULHU(SDNode *N); |
--- |
| 445 |
SDValue visitMULHS(SDNode *N); |
--- |
445 |
SDValue visitMULHS(SDNode *N); |
--- |
| 446 |
SDValue visitAVG(SDNode *N); |
--- |
446 |
SDValue visitAVG(SDNode *N); |
--- |
| 447 |
SDValue visitABD(SDNode *N); |
--- |
447 |
SDValue visitABD(SDNode *N); |
--- |
| 448 |
SDValue visitSMUL_LOHI(SDNode *N); |
--- |
448 |
SDValue visitSMUL_LOHI(SDNode *N); |
--- |
| 449 |
SDValue visitUMUL_LOHI(SDNode *N); |
--- |
449 |
SDValue visitUMUL_LOHI(SDNode *N); |
--- |
| 450 |
SDValue visitMULO(SDNode *N); |
--- |
450 |
SDValue visitMULO(SDNode *N); |
--- |
| 451 |
SDValue visitIMINMAX(SDNode *N); |
--- |
451 |
SDValue visitIMINMAX(SDNode *N); |
--- |
| 452 |
SDValue visitAND(SDNode *N); |
--- |
452 |
SDValue visitAND(SDNode *N); |
--- |
| 453 |
SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N); |
--- |
453 |
SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N); |
--- |
| 454 |
SDValue visitOR(SDNode *N); |
--- |
454 |
SDValue visitOR(SDNode *N); |
--- |
| 455 |
SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N); |
--- |
455 |
SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N); |
--- |
| 456 |
SDValue visitXOR(SDNode *N); |
--- |
456 |
SDValue visitXOR(SDNode *N); |
--- |
| 457 |
SDValue SimplifyVCastOp(SDNode *N, const SDLoc &DL); |
--- |
457 |
SDValue SimplifyVCastOp(SDNode *N, const SDLoc &DL); |
--- |
| 458 |
SDValue SimplifyVBinOp(SDNode *N, const SDLoc &DL); |
--- |
458 |
SDValue SimplifyVBinOp(SDNode *N, const SDLoc &DL); |
--- |
| 459 |
SDValue visitSHL(SDNode *N); |
--- |
459 |
SDValue visitSHL(SDNode *N); |
--- |
| 460 |
SDValue visitSRA(SDNode *N); |
--- |
460 |
SDValue visitSRA(SDNode *N); |
--- |
| 461 |
SDValue visitSRL(SDNode *N); |
--- |
461 |
SDValue visitSRL(SDNode *N); |
--- |
| 462 |
SDValue visitFunnelShift(SDNode *N); |
--- |
462 |
SDValue visitFunnelShift(SDNode *N); |
--- |
| 463 |
SDValue visitSHLSAT(SDNode *N); |
--- |
463 |
SDValue visitSHLSAT(SDNode *N); |
--- |
| 464 |
SDValue visitRotate(SDNode *N); |
--- |
464 |
SDValue visitRotate(SDNode *N); |
--- |
| 465 |
SDValue visitABS(SDNode *N); |
--- |
465 |
SDValue visitABS(SDNode *N); |
--- |
| 466 |
SDValue visitBSWAP(SDNode *N); |
--- |
466 |
SDValue visitBSWAP(SDNode *N); |
--- |
| 467 |
SDValue visitBITREVERSE(SDNode *N); |
--- |
467 |
SDValue visitBITREVERSE(SDNode *N); |
--- |
| 468 |
SDValue visitCTLZ(SDNode *N); |
--- |
468 |
SDValue visitCTLZ(SDNode *N); |
--- |
| 469 |
SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); |
--- |
469 |
SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); |
--- |
| 470 |
SDValue visitCTTZ(SDNode *N); |
--- |
470 |
SDValue visitCTTZ(SDNode *N); |
--- |
| 471 |
SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); |
--- |
471 |
SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); |
--- |
| 472 |
SDValue visitCTPOP(SDNode *N); |
--- |
472 |
SDValue visitCTPOP(SDNode *N); |
--- |
| 473 |
SDValue visitSELECT(SDNode *N); |
--- |
473 |
SDValue visitSELECT(SDNode *N); |
--- |
| 474 |
SDValue visitVSELECT(SDNode *N); |
--- |
474 |
SDValue visitVSELECT(SDNode *N); |
--- |
| 475 |
SDValue visitSELECT_CC(SDNode *N); |
--- |
475 |
SDValue visitSELECT_CC(SDNode *N); |
--- |
| 476 |
SDValue visitSETCC(SDNode *N); |
--- |
476 |
SDValue visitSETCC(SDNode *N); |
--- |
| 477 |
SDValue visitSETCCCARRY(SDNode *N); |
--- |
477 |
SDValue visitSETCCCARRY(SDNode *N); |
--- |
| 478 |
SDValue visitSIGN_EXTEND(SDNode *N); |
--- |
478 |
SDValue visitSIGN_EXTEND(SDNode *N); |
--- |
| 479 |
SDValue visitZERO_EXTEND(SDNode *N); |
--- |
479 |
SDValue visitZERO_EXTEND(SDNode *N); |
--- |
| 480 |
SDValue visitANY_EXTEND(SDNode *N); |
--- |
480 |
SDValue visitANY_EXTEND(SDNode *N); |
--- |
| 481 |
SDValue visitAssertExt(SDNode *N); |
--- |
481 |
SDValue visitAssertExt(SDNode *N); |
--- |
| 482 |
SDValue visitAssertAlign(SDNode *N); |
--- |
482 |
SDValue visitAssertAlign(SDNode *N); |
--- |
| 483 |
SDValue visitSIGN_EXTEND_INREG(SDNode *N); |
--- |
483 |
SDValue visitSIGN_EXTEND_INREG(SDNode *N); |
--- |
| 484 |
SDValue visitEXTEND_VECTOR_INREG(SDNode *N); |
--- |
484 |
SDValue visitEXTEND_VECTOR_INREG(SDNode *N); |
--- |
| 485 |
SDValue visitTRUNCATE(SDNode *N); |
--- |
485 |
SDValue visitTRUNCATE(SDNode *N); |
--- |
| 486 |
SDValue visitBITCAST(SDNode *N); |
--- |
486 |
SDValue visitBITCAST(SDNode *N); |
--- |
| 487 |
SDValue visitFREEZE(SDNode *N); |
--- |
487 |
SDValue visitFREEZE(SDNode *N); |
--- |
| 488 |
SDValue visitBUILD_PAIR(SDNode *N); |
--- |
488 |
SDValue visitBUILD_PAIR(SDNode *N); |
--- |
| 489 |
SDValue visitFADD(SDNode *N); |
--- |
489 |
SDValue visitFADD(SDNode *N); |
--- |
| 490 |
SDValue visitVP_FADD(SDNode *N); |
--- |
490 |
SDValue visitVP_FADD(SDNode *N); |
--- |
| 491 |
SDValue visitVP_FSUB(SDNode *N); |
--- |
491 |
SDValue visitVP_FSUB(SDNode *N); |
--- |
| 492 |
SDValue visitSTRICT_FADD(SDNode *N); |
--- |
492 |
SDValue visitSTRICT_FADD(SDNode *N); |
--- |
| 493 |
SDValue visitFSUB(SDNode *N); |
--- |
493 |
SDValue visitFSUB(SDNode *N); |
--- |
| 494 |
SDValue visitFMUL(SDNode *N); |
--- |
494 |
SDValue visitFMUL(SDNode *N); |
--- |
| 495 |
template SDValue visitFMA(SDNode *N); |
--- |
495 |
template SDValue visitFMA(SDNode *N); |
--- |
| 496 |
SDValue visitFDIV(SDNode *N); |
--- |
496 |
SDValue visitFDIV(SDNode *N); |
--- |
| 497 |
SDValue visitFREM(SDNode *N); |
--- |
497 |
SDValue visitFREM(SDNode *N); |
--- |
| 498 |
SDValue visitFSQRT(SDNode *N); |
--- |
498 |
SDValue visitFSQRT(SDNode *N); |
--- |
| 499 |
SDValue visitFCOPYSIGN(SDNode *N); |
--- |
499 |
SDValue visitFCOPYSIGN(SDNode *N); |
--- |
| 500 |
SDValue visitFPOW(SDNode *N); |
--- |
500 |
SDValue visitFPOW(SDNode *N); |
--- |
| 501 |
SDValue visitSINT_TO_FP(SDNode *N); |
--- |
501 |
SDValue visitSINT_TO_FP(SDNode *N); |
--- |
| 502 |
SDValue visitUINT_TO_FP(SDNode *N); |
--- |
502 |
SDValue visitUINT_TO_FP(SDNode *N); |
--- |
| 503 |
SDValue visitFP_TO_SINT(SDNode *N); |
--- |
503 |
SDValue visitFP_TO_SINT(SDNode *N); |
--- |
| 504 |
SDValue visitFP_TO_UINT(SDNode *N); |
--- |
504 |
SDValue visitFP_TO_UINT(SDNode *N); |
--- |
| 505 |
SDValue visitFP_ROUND(SDNode *N); |
--- |
505 |
SDValue visitFP_ROUND(SDNode *N); |
--- |
| 506 |
SDValue visitFP_EXTEND(SDNode *N); |
--- |
506 |
SDValue visitFP_EXTEND(SDNode *N); |
--- |
| 507 |
SDValue visitFNEG(SDNode *N); |
--- |
507 |
SDValue visitFNEG(SDNode *N); |
--- |
| 508 |
SDValue visitFABS(SDNode *N); |
--- |
508 |
SDValue visitFABS(SDNode *N); |
--- |
| 509 |
SDValue visitFCEIL(SDNode *N); |
--- |
509 |
SDValue visitFCEIL(SDNode *N); |
--- |
| 510 |
SDValue visitFTRUNC(SDNode *N); |
--- |
510 |
SDValue visitFTRUNC(SDNode *N); |
--- |
| 511 |
SDValue visitFFREXP(SDNode *N); |
--- |
511 |
SDValue visitFFREXP(SDNode *N); |
--- |
| 512 |
SDValue visitFFLOOR(SDNode *N); |
--- |
512 |
SDValue visitFFLOOR(SDNode *N); |
--- |
| 513 |
SDValue visitFMinMax(SDNode *N); |
--- |
513 |
SDValue visitFMinMax(SDNode *N); |
--- |
| 514 |
SDValue visitBRCOND(SDNode *N); |
--- |
514 |
SDValue visitBRCOND(SDNode *N); |
--- |
| 515 |
SDValue visitBR_CC(SDNode *N); |
--- |
515 |
SDValue visitBR_CC(SDNode *N); |
--- |
| 516 |
SDValue visitLOAD(SDNode *N); |
--- |
516 |
SDValue visitLOAD(SDNode *N); |
--- |
| 517 |
|
--- |
517 |
|
--- |
| 518 |
SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain); |
--- |
518 |
SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain); |
--- |
| 519 |
SDValue replaceStoreOfFPConstant(StoreSDNode *ST); |
--- |
519 |
SDValue replaceStoreOfFPConstant(StoreSDNode *ST); |
--- |
| 520 |
SDValue replaceStoreOfInsertLoad(StoreSDNode *ST); |
--- |
520 |
SDValue replaceStoreOfInsertLoad(StoreSDNode *ST); |
--- |
| 521 |
|
--- |
521 |
|
--- |
| 522 |
bool refineExtractVectorEltIntoMultipleNarrowExtractVectorElts(SDNode *N); |
--- |
522 |
bool refineExtractVectorEltIntoMultipleNarrowExtractVectorElts(SDNode *N); |
--- |
| 523 |
|
--- |
523 |
|
--- |
| 524 |
SDValue visitSTORE(SDNode *N); |
--- |
524 |
SDValue visitSTORE(SDNode *N); |
--- |
| 525 |
SDValue visitLIFETIME_END(SDNode *N); |
--- |
525 |
SDValue visitLIFETIME_END(SDNode *N); |
--- |
| 526 |
SDValue visitINSERT_VECTOR_ELT(SDNode *N); |
--- |
526 |
SDValue visitINSERT_VECTOR_ELT(SDNode *N); |
--- |
| 527 |
SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); |
--- |
527 |
SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); |
--- |
| 528 |
SDValue visitBUILD_VECTOR(SDNode *N); |
--- |
528 |
SDValue visitBUILD_VECTOR(SDNode *N); |
--- |
| 529 |
SDValue visitCONCAT_VECTORS(SDNode *N); |
--- |
529 |
SDValue visitCONCAT_VECTORS(SDNode *N); |
--- |
| 530 |
SDValue visitEXTRACT_SUBVECTOR(SDNode *N); |
--- |
530 |
SDValue visitEXTRACT_SUBVECTOR(SDNode *N); |
--- |
| 531 |
SDValue visitVECTOR_SHUFFLE(SDNode *N); |
--- |
531 |
SDValue visitVECTOR_SHUFFLE(SDNode *N); |
--- |
| 532 |
SDValue visitSCALAR_TO_VECTOR(SDNode *N); |
--- |
532 |
SDValue visitSCALAR_TO_VECTOR(SDNode *N); |
--- |
| 533 |
SDValue visitINSERT_SUBVECTOR(SDNode *N); |
--- |
533 |
SDValue visitINSERT_SUBVECTOR(SDNode *N); |
--- |
| 534 |
SDValue visitMLOAD(SDNode *N); |
--- |
534 |
SDValue visitMLOAD(SDNode *N); |
--- |
| 535 |
SDValue visitMSTORE(SDNode *N); |
--- |
535 |
SDValue visitMSTORE(SDNode *N); |
--- |
| 536 |
SDValue visitMGATHER(SDNode *N); |
--- |
536 |
SDValue visitMGATHER(SDNode *N); |
--- |
| 537 |
SDValue visitMSCATTER(SDNode *N); |
--- |
537 |
SDValue visitMSCATTER(SDNode *N); |
--- |
| 538 |
SDValue visitVPGATHER(SDNode *N); |
--- |
538 |
SDValue visitVPGATHER(SDNode *N); |
--- |
| 539 |
SDValue visitVPSCATTER(SDNode *N); |
--- |
539 |
SDValue visitVPSCATTER(SDNode *N); |
--- |
| 540 |
SDValue visitFP_TO_FP16(SDNode *N); |
--- |
540 |
SDValue visitFP_TO_FP16(SDNode *N); |
--- |
| 541 |
SDValue visitFP16_TO_FP(SDNode *N); |
--- |
541 |
SDValue visitFP16_TO_FP(SDNode *N); |
--- |
| 542 |
SDValue visitFP_TO_BF16(SDNode *N); |
--- |
542 |
SDValue visitFP_TO_BF16(SDNode *N); |
--- |
| 543 |
SDValue visitVECREDUCE(SDNode *N); |
--- |
543 |
SDValue visitVECREDUCE(SDNode *N); |
--- |
| 544 |
SDValue visitVPOp(SDNode *N); |
--- |
544 |
SDValue visitVPOp(SDNode *N); |
--- |
| 545 |
SDValue visitGET_FPENV_MEM(SDNode *N); |
--- |
545 |
SDValue visitGET_FPENV_MEM(SDNode *N); |
--- |
| 546 |
SDValue visitSET_FPENV_MEM(SDNode *N); |
--- |
546 |
SDValue visitSET_FPENV_MEM(SDNode *N); |
--- |
| 547 |
|
--- |
547 |
|
--- |
| 548 |
template |
--- |
548 |
template |
--- |
| 549 |
SDValue visitFADDForFMACombine(SDNode *N); |
--- |
549 |
SDValue visitFADDForFMACombine(SDNode *N); |
--- |
| 550 |
template |
--- |
550 |
template |
--- |
| 551 |
SDValue visitFSUBForFMACombine(SDNode *N); |
--- |
551 |
SDValue visitFSUBForFMACombine(SDNode *N); |
--- |
| 552 |
SDValue visitFMULForFMADistributiveCombine(SDNode *N); |
--- |
552 |
SDValue visitFMULForFMADistributiveCombine(SDNode *N); |
--- |
| 553 |
|
--- |
553 |
|
--- |
| 554 |
SDValue XformToShuffleWithZero(SDNode *N); |
--- |
554 |
SDValue XformToShuffleWithZero(SDNode *N); |
--- |
| 555 |
bool reassociationCanBreakAddressingModePattern(unsigned Opc, |
--- |
555 |
bool reassociationCanBreakAddressingModePattern(unsigned Opc, |
--- |
| 556 |
const SDLoc &DL, |
--- |
556 |
const SDLoc &DL, |
--- |
| 557 |
SDNode *N, |
--- |
557 |
SDNode *N, |
--- |
| 558 |
SDValue N0, |
--- |
558 |
SDValue N0, |
--- |
| 559 |
SDValue N1); |
--- |
559 |
SDValue N1); |
--- |
| 560 |
SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0, |
--- |
560 |
SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0, |
--- |
| 561 |
SDValue N1, SDNodeFlags Flags); |
--- |
561 |
SDValue N1, SDNodeFlags Flags); |
--- |
| 562 |
SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0, |
--- |
562 |
SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0, |
--- |
| 563 |
SDValue N1, SDNodeFlags Flags); |
--- |
563 |
SDValue N1, SDNodeFlags Flags); |
--- |
| 564 |
SDValue reassociateReduction(unsigned ResOpc, unsigned Opc, const SDLoc &DL, |
--- |
564 |
SDValue reassociateReduction(unsigned ResOpc, unsigned Opc, const SDLoc &DL, |
--- |
| 565 |
EVT VT, SDValue N0, SDValue N1, |
--- |
565 |
EVT VT, SDValue N0, SDValue N1, |
--- |
| 566 |
SDNodeFlags Flags = SDNodeFlags()); |
--- |
566 |
SDNodeFlags Flags = SDNodeFlags()); |
--- |
| 567 |
|
--- |
567 |
|
--- |
| 568 |
SDValue visitShiftByConstant(SDNode *N); |
--- |
568 |
SDValue visitShiftByConstant(SDNode *N); |
--- |
| 569 |
|
--- |
569 |
|
--- |
| 570 |
SDValue foldSelectOfConstants(SDNode *N); |
--- |
570 |
SDValue foldSelectOfConstants(SDNode *N); |
--- |
| 571 |
SDValue foldVSelectOfConstants(SDNode *N); |
--- |
571 |
SDValue foldVSelectOfConstants(SDNode *N); |
--- |
| 572 |
SDValue foldBinOpIntoSelect(SDNode *BO); |
--- |
572 |
SDValue foldBinOpIntoSelect(SDNode *BO); |
--- |
| 573 |
bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); |
--- |
573 |
bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); |
--- |
| 574 |
SDValue hoistLogicOpWithSameOpcodeHands(SDNode *N); |
--- |
574 |
SDValue hoistLogicOpWithSameOpcodeHands(SDNode *N); |
--- |
| 575 |
SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2); |
--- |
575 |
SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2); |
--- |
| 576 |
SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1, |
--- |
576 |
SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1, |
--- |
| 577 |
SDValue N2, SDValue N3, ISD::CondCode CC, |
--- |
577 |
SDValue N2, SDValue N3, ISD::CondCode CC, |
--- |
| 578 |
bool NotExtCompare = false); |
--- |
578 |
bool NotExtCompare = false); |
--- |
| 579 |
SDValue convertSelectOfFPConstantsToLoadOffset( |
--- |
579 |
SDValue convertSelectOfFPConstantsToLoadOffset( |
--- |
| 580 |
const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, |
--- |
580 |
const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, |
--- |
| 581 |
ISD::CondCode CC); |
--- |
581 |
ISD::CondCode CC); |
--- |
| 582 |
SDValue foldSignChangeInBitcast(SDNode *N); |
--- |
582 |
SDValue foldSignChangeInBitcast(SDNode *N); |
--- |
| 583 |
SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1, |
--- |
583 |
SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1, |
--- |
| 584 |
SDValue N2, SDValue N3, ISD::CondCode CC); |
--- |
584 |
SDValue N2, SDValue N3, ISD::CondCode CC); |
--- |
| 585 |
SDValue foldSelectOfBinops(SDNode *N); |
--- |
585 |
SDValue foldSelectOfBinops(SDNode *N); |
--- |
| 586 |
SDValue foldSextSetcc(SDNode *N); |
--- |
586 |
SDValue foldSextSetcc(SDNode *N); |
--- |
| 587 |
SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1, |
--- |
587 |
SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1, |
--- |
| 588 |
const SDLoc &DL); |
--- |
588 |
const SDLoc &DL); |
--- |
| 589 |
SDValue foldSubToUSubSat(EVT DstVT, SDNode *N); |
--- |
589 |
SDValue foldSubToUSubSat(EVT DstVT, SDNode *N); |
--- |
| 590 |
SDValue foldABSToABD(SDNode *N); |
--- |
590 |
SDValue foldABSToABD(SDNode *N); |
--- |
| 591 |
SDValue unfoldMaskedMerge(SDNode *N); |
--- |
591 |
SDValue unfoldMaskedMerge(SDNode *N); |
--- |
| 592 |
SDValue unfoldExtremeBitClearingToShifts(SDNode *N); |
--- |
592 |
SDValue unfoldExtremeBitClearingToShifts(SDNode *N); |
--- |
| 593 |
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, |
--- |
593 |
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, |
--- |
| 594 |
const SDLoc &DL, bool foldBooleans); |
--- |
594 |
const SDLoc &DL, bool foldBooleans); |
--- |
| 595 |
SDValue rebuildSetCC(SDValue N); |
--- |
595 |
SDValue rebuildSetCC(SDValue N); |
--- |
| 596 |
|
--- |
596 |
|
--- |
| 597 |
bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, |
--- |
597 |
bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, |
--- |
| 598 |
SDValue &CC, bool MatchStrict = false) const; |
--- |
598 |
SDValue &CC, bool MatchStrict = false) const; |
--- |
| 599 |
bool isOneUseSetCC(SDValue N) const; |
--- |
599 |
bool isOneUseSetCC(SDValue N) const; |
--- |
| 600 |
|
--- |
600 |
|
--- |
| 601 |
SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, |
--- |
601 |
SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, |
--- |
| 602 |
unsigned HiOp); |
--- |
602 |
unsigned HiOp); |
--- |
| 603 |
SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); |
--- |
603 |
SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); |
--- |
| 604 |
SDValue foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG, |
--- |
604 |
SDValue foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG, |
--- |
| 605 |
const TargetLowering &TLI); |
--- |
605 |
const TargetLowering &TLI); |
--- |
| 606 |
|
--- |
606 |
|
--- |
| 607 |
SDValue CombineExtLoad(SDNode *N); |
--- |
607 |
SDValue CombineExtLoad(SDNode *N); |
--- |
| 608 |
SDValue CombineZExtLogicopShiftLoad(SDNode *N); |
--- |
608 |
SDValue CombineZExtLogicopShiftLoad(SDNode *N); |
--- |
| 609 |
SDValue combineRepeatedFPDivisors(SDNode *N); |
--- |
609 |
SDValue combineRepeatedFPDivisors(SDNode *N); |
--- |
| 610 |
SDValue mergeInsertEltWithShuffle(SDNode *N, unsigned InsIndex); |
--- |
610 |
SDValue mergeInsertEltWithShuffle(SDNode *N, unsigned InsIndex); |
--- |
| 611 |
SDValue combineInsertEltToShuffle(SDNode *N, unsigned InsIndex); |
--- |
611 |
SDValue combineInsertEltToShuffle(SDNode *N, unsigned InsIndex); |
--- |
| 612 |
SDValue combineInsertEltToLoad(SDNode *N, unsigned InsIndex); |
--- |
612 |
SDValue combineInsertEltToLoad(SDNode *N, unsigned InsIndex); |
--- |
| 613 |
SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); |
--- |
613 |
SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); |
--- |
| 614 |
SDValue BuildSDIV(SDNode *N); |
--- |
614 |
SDValue BuildSDIV(SDNode *N); |
--- |
| 615 |
SDValue BuildSDIVPow2(SDNode *N); |
--- |
615 |
SDValue BuildSDIVPow2(SDNode *N); |
--- |
| 616 |
SDValue BuildUDIV(SDNode *N); |
--- |
616 |
SDValue BuildUDIV(SDNode *N); |
--- |
| 617 |
SDValue BuildSREMPow2(SDNode *N); |
--- |
617 |
SDValue BuildSREMPow2(SDNode *N); |
--- |
| 618 |
SDValue buildOptimizedSREM(SDValue N0, SDValue N1, SDNode *N); |
--- |
618 |
SDValue buildOptimizedSREM(SDValue N0, SDValue N1, SDNode *N); |
--- |
| 619 |
SDValue BuildLogBase2(SDValue V, const SDLoc &DL); |
--- |
619 |
SDValue BuildLogBase2(SDValue V, const SDLoc &DL); |
--- |
| 620 |
SDValue BuildDivEstimate(SDValue N, SDValue Op, SDNodeFlags Flags); |
--- |
620 |
SDValue BuildDivEstimate(SDValue N, SDValue Op, SDNodeFlags Flags); |
--- |
| 621 |
SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags); |
--- |
621 |
SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags); |
--- |
| 622 |
SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags); |
--- |
622 |
SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags); |
--- |
| 623 |
SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip); |
--- |
623 |
SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip); |
--- |
| 624 |
SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations, |
--- |
624 |
SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations, |
--- |
| 625 |
SDNodeFlags Flags, bool Reciprocal); |
--- |
625 |
SDNodeFlags Flags, bool Reciprocal); |
--- |
| 626 |
SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations, |
--- |
626 |
SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations, |
--- |
| 627 |
SDNodeFlags Flags, bool Reciprocal); |
--- |
627 |
SDNodeFlags Flags, bool Reciprocal); |
--- |
| 628 |
SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, |
--- |
628 |
SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, |
--- |
| 629 |
bool DemandHighBits = true); |
--- |
629 |
bool DemandHighBits = true); |
--- |
| 630 |
SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); |
--- |
630 |
SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); |
--- |
| 631 |
SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg, |
--- |
631 |
SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg, |
--- |
| 632 |
SDValue InnerPos, SDValue InnerNeg, bool HasPos, |
--- |
632 |
SDValue InnerPos, SDValue InnerNeg, bool HasPos, |
--- |
| 633 |
unsigned PosOpcode, unsigned NegOpcode, |
--- |
633 |
unsigned PosOpcode, unsigned NegOpcode, |
--- |
| 634 |
const SDLoc &DL); |
--- |
634 |
const SDLoc &DL); |
--- |
| 635 |
SDValue MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos, SDValue Neg, |
--- |
635 |
SDValue MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos, SDValue Neg, |
--- |
| 636 |
SDValue InnerPos, SDValue InnerNeg, bool HasPos, |
--- |
636 |
SDValue InnerPos, SDValue InnerNeg, bool HasPos, |
--- |
| 637 |
unsigned PosOpcode, unsigned NegOpcode, |
--- |
637 |
unsigned PosOpcode, unsigned NegOpcode, |
--- |
| 638 |
const SDLoc &DL); |
--- |
638 |
const SDLoc &DL); |
--- |
| 639 |
SDValue MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL); |
--- |
639 |
SDValue MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL); |
--- |
| 640 |
SDValue MatchLoadCombine(SDNode *N); |
--- |
640 |
SDValue MatchLoadCombine(SDNode *N); |
--- |
| 641 |
SDValue mergeTruncStores(StoreSDNode *N); |
--- |
641 |
SDValue mergeTruncStores(StoreSDNode *N); |
--- |
| 642 |
SDValue reduceLoadWidth(SDNode *N); |
--- |
642 |
SDValue reduceLoadWidth(SDNode *N); |
--- |
| 643 |
SDValue ReduceLoadOpStoreWidth(SDNode *N); |
--- |
643 |
SDValue ReduceLoadOpStoreWidth(SDNode *N); |
--- |
| 644 |
SDValue splitMergedValStore(StoreSDNode *ST); |
--- |
644 |
SDValue splitMergedValStore(StoreSDNode *ST); |
--- |
| 645 |
SDValue TransformFPLoadStorePair(SDNode *N); |
--- |
645 |
SDValue TransformFPLoadStorePair(SDNode *N); |
--- |
| 646 |
SDValue convertBuildVecZextToZext(SDNode *N); |
--- |
646 |
SDValue convertBuildVecZextToZext(SDNode *N); |
--- |
| 647 |
SDValue convertBuildVecZextToBuildVecWithZeros(SDNode *N); |
--- |
647 |
SDValue convertBuildVecZextToBuildVecWithZeros(SDNode *N); |
--- |
| 648 |
SDValue reduceBuildVecExtToExtBuildVec(SDNode *N); |
--- |
648 |
SDValue reduceBuildVecExtToExtBuildVec(SDNode *N); |
--- |
| 649 |
SDValue reduceBuildVecTruncToBitCast(SDNode *N); |
--- |
649 |
SDValue reduceBuildVecTruncToBitCast(SDNode *N); |
--- |
| 650 |
SDValue reduceBuildVecToShuffle(SDNode *N); |
--- |
650 |
SDValue reduceBuildVecToShuffle(SDNode *N); |
--- |
| 651 |
SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N, |
--- |
651 |
SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N, |
--- |
| 652 |
ArrayRef VectorMask, SDValue VecIn1, |
--- |
652 |
ArrayRef VectorMask, SDValue VecIn1, |
--- |
| 653 |
SDValue VecIn2, unsigned LeftIdx, |
--- |
653 |
SDValue VecIn2, unsigned LeftIdx, |
--- |
| 654 |
bool DidSplitVec); |
--- |
654 |
bool DidSplitVec); |
--- |
| 655 |
SDValue matchVSelectOpSizesWithSetCC(SDNode *Cast); |
--- |
655 |
SDValue matchVSelectOpSizesWithSetCC(SDNode *Cast); |
--- |
| 656 |
|
--- |
656 |
|
--- |
| 657 |
/// Walk up chain skipping non-aliasing memory nodes, |
--- |
657 |
/// Walk up chain skipping non-aliasing memory nodes, |
--- |
| 658 |
/// looking for aliasing nodes and adding them to the Aliases vector. |
--- |
658 |
/// looking for aliasing nodes and adding them to the Aliases vector. |
--- |
| 659 |
void GatherAllAliases(SDNode *N, SDValue OriginalChain, |
--- |
659 |
void GatherAllAliases(SDNode *N, SDValue OriginalChain, |
--- |
| 660 |
SmallVectorImpl &Aliases); |
--- |
660 |
SmallVectorImpl &Aliases); |
--- |
| 661 |
|
--- |
661 |
|
--- |
| 662 |
/// Return true if there is any possibility that the two addresses overlap. |
--- |
662 |
/// Return true if there is any possibility that the two addresses overlap. |
--- |
| 663 |
bool mayAlias(SDNode *Op0, SDNode *Op1) const; |
--- |
663 |
bool mayAlias(SDNode *Op0, SDNode *Op1) const; |
--- |
| 664 |
|
--- |
664 |
|
--- |
| 665 |
/// Walk up chain skipping non-aliasing memory nodes, looking for a better |
--- |
665 |
/// Walk up chain skipping non-aliasing memory nodes, looking for a better |
--- |
| 666 |
/// chain (aliasing node.) |
--- |
666 |
/// chain (aliasing node.) |
--- |
| 667 |
SDValue FindBetterChain(SDNode *N, SDValue Chain); |
--- |
667 |
SDValue FindBetterChain(SDNode *N, SDValue Chain); |
--- |
| 668 |
|
--- |
668 |
|
--- |
| 669 |
/// Try to replace a store and any possibly adjacent stores on |
--- |
669 |
/// Try to replace a store and any possibly adjacent stores on |
--- |
| 670 |
/// consecutive chains with better chains. Return true only if St is |
--- |
670 |
/// consecutive chains with better chains. Return true only if St is |
--- |
| 671 |
/// replaced. |
--- |
671 |
/// replaced. |
--- |
| 672 |
/// |
--- |
672 |
/// |
--- |
| 673 |
/// Notice that other chains may still be replaced even if the function |
--- |
673 |
/// Notice that other chains may still be replaced even if the function |
--- |
| 674 |
/// returns false. |
--- |
674 |
/// returns false. |
--- |
| 675 |
bool findBetterNeighborChains(StoreSDNode *St); |
--- |
675 |
bool findBetterNeighborChains(StoreSDNode *St); |
--- |
| 676 |
|
--- |
676 |
|
--- |
| 677 |
// Helper for findBetterNeighborChains. Walk up store chain add additional |
--- |
677 |
// Helper for findBetterNeighborChains. Walk up store chain add additional |
--- |
| 678 |
// chained stores that do not overlap and can be parallelized. |
--- |
678 |
// chained stores that do not overlap and can be parallelized. |
--- |
| 679 |
bool parallelizeChainedStores(StoreSDNode *St); |
--- |
679 |
bool parallelizeChainedStores(StoreSDNode *St); |
--- |
| 680 |
|
--- |
680 |
|
--- |
| 681 |
/// Holds a pointer to an LSBaseSDNode as well as information on where it |
--- |
681 |
/// Holds a pointer to an LSBaseSDNode as well as information on where it |
--- |
| 682 |
/// is located in a sequence of memory operations connected by a chain. |
--- |
682 |
/// is located in a sequence of memory operations connected by a chain. |
--- |
| 683 |
struct MemOpLink { |
--- |
683 |
struct MemOpLink { |
--- |
| 684 |
// Ptr to the mem node. |
--- |
684 |
// Ptr to the mem node. |
--- |
| 685 |
LSBaseSDNode *MemNode; |
--- |
685 |
LSBaseSDNode *MemNode; |
--- |
| 686 |
|
--- |
686 |
|
--- |
| 687 |
// Offset from the base ptr. |
--- |
687 |
// Offset from the base ptr. |
--- |
| 688 |
int64_t OffsetFromBase; |
--- |
688 |
int64_t OffsetFromBase; |
--- |
| 689 |
|
--- |
689 |
|
--- |
| 690 |
MemOpLink(LSBaseSDNode *N, int64_t Offset) |
0 |
690 |
MemOpLink(LSBaseSDNode *N, int64_t Offset) |
0 |
| 691 |
: MemNode(N), OffsetFromBase(Offset) {} |
0 |
691 |
: MemNode(N), OffsetFromBase(Offset) {} |
0 |
| 692 |
}; |
--- |
692 |
}; |
--- |
| 693 |
|
--- |
693 |
|
--- |
| 694 |
// Classify the origin of a stored value. |
--- |
694 |
// Classify the origin of a stored value. |
--- |
| 695 |
enum class StoreSource { Unknown, Constant, Extract, Load }; |
--- |
695 |
enum class StoreSource { Unknown, Constant, Extract, Load }; |
--- |
| 696 |
StoreSource getStoreSource(SDValue StoreVal) { |
0 |
696 |
StoreSource getStoreSource(SDValue StoreVal) { |
0 |
| 697 |
switch (StoreVal.getOpcode()) { |
0 |
697 |
switch (StoreVal.getOpcode()) { |
0 |
| 698 |
case ISD::Constant: |
0 |
698 |
case ISD::Constant: |
0 |
| 699 |
case ISD::ConstantFP: |
--- |
699 |
case ISD::ConstantFP: |
--- |
| 700 |
return StoreSource::Constant; |
0 |
700 |
return StoreSource::Constant; |
0 |
| 701 |
case ISD::EXTRACT_VECTOR_ELT: |
0 |
701 |
case ISD::EXTRACT_VECTOR_ELT: |
0 |
| 702 |
case ISD::EXTRACT_SUBVECTOR: |
--- |
702 |
case ISD::EXTRACT_SUBVECTOR: |
--- |
| 703 |
return StoreSource::Extract; |
0 |
703 |
return StoreSource::Extract; |
0 |
| 704 |
case ISD::LOAD: |
0 |
704 |
case ISD::LOAD: |
0 |
| 705 |
return StoreSource::Load; |
0 |
705 |
return StoreSource::Load; |
0 |
| 706 |
default: |
0 |
706 |
default: |
0 |
| 707 |
return StoreSource::Unknown; |
0 |
707 |
return StoreSource::Unknown; |
0 |
| 708 |
} |
--- |
708 |
} |
--- |
| 709 |
} |
--- |
709 |
} |
--- |
| 710 |
|
--- |
710 |
|
--- |
| 711 |
/// This is a helper function for visitMUL to check the profitability |
--- |
711 |
/// This is a helper function for visitMUL to check the profitability |
--- |
| 712 |
/// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2). |
--- |
712 |
/// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2). |
--- |
| 713 |
/// MulNode is the original multiply, AddNode is (add x, c1), |
--- |
713 |
/// MulNode is the original multiply, AddNode is (add x, c1), |
--- |
| 714 |
/// and ConstNode is c2. |
--- |
714 |
/// and ConstNode is c2. |
--- |
| 715 |
bool isMulAddWithConstProfitable(SDNode *MulNode, SDValue AddNode, |
--- |
715 |
bool isMulAddWithConstProfitable(SDNode *MulNode, SDValue AddNode, |
--- |
| 716 |
SDValue ConstNode); |
--- |
716 |
SDValue ConstNode); |
--- |
| 717 |
|
--- |
717 |
|
--- |
| 718 |
/// This is a helper function for visitAND and visitZERO_EXTEND. Returns |
--- |
718 |
/// This is a helper function for visitAND and visitZERO_EXTEND. Returns |
--- |
| 719 |
/// true if the (and (load x) c) pattern matches an extload. ExtVT returns |
--- |
719 |
/// true if the (and (load x) c) pattern matches an extload. ExtVT returns |
--- |
| 720 |
/// the type of the loaded value to be extended. |
--- |
720 |
/// the type of the loaded value to be extended. |
--- |
| 721 |
bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN, |
--- |
721 |
bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN, |
--- |
| 722 |
EVT LoadResultTy, EVT &ExtVT); |
--- |
722 |
EVT LoadResultTy, EVT &ExtVT); |
--- |
| 723 |
|
--- |
723 |
|
--- |
| 724 |
/// Helper function to calculate whether the given Load/Store can have its |
--- |
724 |
/// Helper function to calculate whether the given Load/Store can have its |
--- |
| 725 |
/// width reduced to ExtVT. |
--- |
725 |
/// width reduced to ExtVT. |
--- |
| 726 |
bool isLegalNarrowLdSt(LSBaseSDNode *LDSTN, ISD::LoadExtType ExtType, |
--- |
726 |
bool isLegalNarrowLdSt(LSBaseSDNode *LDSTN, ISD::LoadExtType ExtType, |
--- |
| 727 |
EVT &MemVT, unsigned ShAmt = 0); |
--- |
727 |
EVT &MemVT, unsigned ShAmt = 0); |
--- |
| 728 |
|
--- |
728 |
|
--- |
| 729 |
/// Used by BackwardsPropagateMask to find suitable loads. |
--- |
729 |
/// Used by BackwardsPropagateMask to find suitable loads. |
--- |
| 730 |
bool SearchForAndLoads(SDNode *N, SmallVectorImpl &Loads, |
--- |
730 |
bool SearchForAndLoads(SDNode *N, SmallVectorImpl &Loads, |
--- |
| 731 |
SmallPtrSetImpl &NodesWithConsts, |
--- |
731 |
SmallPtrSetImpl &NodesWithConsts, |
--- |
| 732 |
ConstantSDNode *Mask, SDNode *&NodeToMask); |
--- |
732 |
ConstantSDNode *Mask, SDNode *&NodeToMask); |
--- |
| 733 |
/// Attempt to propagate a given AND node back to load leaves so that they |
--- |
733 |
/// Attempt to propagate a given AND node back to load leaves so that they |
--- |
| 734 |
/// can be combined into narrow loads. |
--- |
734 |
/// can be combined into narrow loads. |
--- |
| 735 |
bool BackwardsPropagateMask(SDNode *N); |
--- |
735 |
bool BackwardsPropagateMask(SDNode *N); |
--- |
| 736 |
|
--- |
736 |
|
--- |
| 737 |
/// Helper function for mergeConsecutiveStores which merges the component |
--- |
737 |
/// Helper function for mergeConsecutiveStores which merges the component |
--- |
| 738 |
/// store chains. |
--- |
738 |
/// store chains. |
--- |
| 739 |
SDValue getMergeStoreChains(SmallVectorImpl &StoreNodes, |
--- |
739 |
SDValue getMergeStoreChains(SmallVectorImpl &StoreNodes, |
--- |
| 740 |
unsigned NumStores); |
--- |
740 |
unsigned NumStores); |
--- |
| 741 |
|
--- |
741 |
|
--- |
| 742 |
/// Helper function for mergeConsecutiveStores which checks if all the store |
--- |
742 |
/// Helper function for mergeConsecutiveStores which checks if all the store |
--- |
| 743 |
/// nodes have the same underlying object. We can still reuse the first |
--- |
743 |
/// nodes have the same underlying object. We can still reuse the first |
--- |
| 744 |
/// store's pointer info if all the stores are from the same object. |
--- |
744 |
/// store's pointer info if all the stores are from the same object. |
--- |
| 745 |
bool hasSameUnderlyingObj(ArrayRef StoreNodes); |
--- |
745 |
bool hasSameUnderlyingObj(ArrayRef StoreNodes); |
--- |
| 746 |
|
--- |
746 |
|
--- |
| 747 |
/// This is a helper function for mergeConsecutiveStores. When the source |
--- |
747 |
/// This is a helper function for mergeConsecutiveStores. When the source |
--- |
| 748 |
/// elements of the consecutive stores are all constants or all extracted |
--- |
748 |
/// elements of the consecutive stores are all constants or all extracted |
--- |
| 749 |
/// vector elements, try to merge them into one larger store introducing |
--- |
749 |
/// vector elements, try to merge them into one larger store introducing |
--- |
| 750 |
/// bitcasts if necessary. \return True if a merged store was created. |
--- |
750 |
/// bitcasts if necessary. \return True if a merged store was created. |
--- |
| 751 |
bool mergeStoresOfConstantsOrVecElts(SmallVectorImpl &StoreNodes, |
--- |
751 |
bool mergeStoresOfConstantsOrVecElts(SmallVectorImpl &StoreNodes, |
--- |
| 752 |
EVT MemVT, unsigned NumStores, |
--- |
752 |
EVT MemVT, unsigned NumStores, |
--- |
| 753 |
bool IsConstantSrc, bool UseVector, |
--- |
753 |
bool IsConstantSrc, bool UseVector, |
--- |
| 754 |
bool UseTrunc); |
--- |
754 |
bool UseTrunc); |
--- |
| 755 |
|
--- |
755 |
|
--- |
| 756 |
/// This is a helper function for mergeConsecutiveStores. Stores that |
--- |
756 |
/// This is a helper function for mergeConsecutiveStores. Stores that |
--- |
| 757 |
/// potentially may be merged with St are placed in StoreNodes. RootNode is |
--- |
757 |
/// potentially may be merged with St are placed in StoreNodes. RootNode is |
--- |
| 758 |
/// a chain predecessor to all store candidates. |
--- |
758 |
/// a chain predecessor to all store candidates. |
--- |
| 759 |
void getStoreMergeCandidates(StoreSDNode *St, |
--- |
759 |
void getStoreMergeCandidates(StoreSDNode *St, |
--- |
| 760 |
SmallVectorImpl &StoreNodes, |
--- |
760 |
SmallVectorImpl &StoreNodes, |
--- |
| 761 |
SDNode *&Root); |
--- |
761 |
SDNode *&Root); |
--- |
| 762 |
|
--- |
762 |
|
--- |
| 763 |
/// Helper function for mergeConsecutiveStores. Checks if candidate stores |
--- |
763 |
/// Helper function for mergeConsecutiveStores. Checks if candidate stores |
--- |
| 764 |
/// have indirect dependency through their operands. RootNode is the |
--- |
764 |
/// have indirect dependency through their operands. RootNode is the |
--- |
| 765 |
/// predecessor to all stores calculated by getStoreMergeCandidates and is |
--- |
765 |
/// predecessor to all stores calculated by getStoreMergeCandidates and is |
--- |
| 766 |
/// used to prune the dependency check. \return True if safe to merge. |
--- |
766 |
/// used to prune the dependency check. \return True if safe to merge. |
--- |
| 767 |
bool checkMergeStoreCandidatesForDependencies( |
--- |
767 |
bool checkMergeStoreCandidatesForDependencies( |
--- |
| 768 |
SmallVectorImpl &StoreNodes, unsigned NumStores, |
--- |
768 |
SmallVectorImpl &StoreNodes, unsigned NumStores, |
--- |
| 769 |
SDNode *RootNode); |
--- |
769 |
SDNode *RootNode); |
--- |
| 770 |
|
--- |
770 |
|
--- |
| 771 |
/// This is a helper function for mergeConsecutiveStores. Given a list of |
--- |
771 |
/// This is a helper function for mergeConsecutiveStores. Given a list of |
--- |
| 772 |
/// store candidates, find the first N that are consecutive in memory. |
--- |
772 |
/// store candidates, find the first N that are consecutive in memory. |
--- |
| 773 |
/// Returns 0 if there are not at least 2 consecutive stores to try merging. |
--- |
773 |
/// Returns 0 if there are not at least 2 consecutive stores to try merging. |
--- |
| 774 |
unsigned getConsecutiveStores(SmallVectorImpl &StoreNodes, |
--- |
774 |
unsigned getConsecutiveStores(SmallVectorImpl &StoreNodes, |
--- |
| 775 |
int64_t ElementSizeBytes) const; |
--- |
775 |
int64_t ElementSizeBytes) const; |
--- |
| 776 |
|
--- |
776 |
|
--- |
| 777 |
/// This is a helper function for mergeConsecutiveStores. It is used for |
--- |
777 |
/// This is a helper function for mergeConsecutiveStores. It is used for |
--- |
| 778 |
/// store chains that are composed entirely of constant values. |
--- |
778 |
/// store chains that are composed entirely of constant values. |
--- |
| 779 |
bool tryStoreMergeOfConstants(SmallVectorImpl &StoreNodes, |
--- |
779 |
bool tryStoreMergeOfConstants(SmallVectorImpl &StoreNodes, |
--- |
| 780 |
unsigned NumConsecutiveStores, |
--- |
780 |
unsigned NumConsecutiveStores, |
--- |
| 781 |
EVT MemVT, SDNode *Root, bool AllowVectors); |
--- |
781 |
EVT MemVT, SDNode *Root, bool AllowVectors); |
--- |
| 782 |
|
--- |
782 |
|
--- |
| 783 |
/// This is a helper function for mergeConsecutiveStores. It is used for |
--- |
783 |
/// This is a helper function for mergeConsecutiveStores. It is used for |
--- |
| 784 |
/// store chains that are composed entirely of extracted vector elements. |
--- |
784 |
/// store chains that are composed entirely of extracted vector elements. |
--- |
| 785 |
/// When extracting multiple vector elements, try to store them in one |
--- |
785 |
/// When extracting multiple vector elements, try to store them in one |
--- |
| 786 |
/// vector store rather than a sequence of scalar stores. |
--- |
786 |
/// vector store rather than a sequence of scalar stores. |
--- |
| 787 |
bool tryStoreMergeOfExtracts(SmallVectorImpl &StoreNodes, |
--- |
787 |
bool tryStoreMergeOfExtracts(SmallVectorImpl &StoreNodes, |
--- |
| 788 |
unsigned NumConsecutiveStores, EVT MemVT, |
--- |
788 |
unsigned NumConsecutiveStores, EVT MemVT, |
--- |
| 789 |
SDNode *Root); |
--- |
789 |
SDNode *Root); |
--- |
| 790 |
|
--- |
790 |
|
--- |
| 791 |
/// This is a helper function for mergeConsecutiveStores. It is used for |
--- |
791 |
/// This is a helper function for mergeConsecutiveStores. It is used for |
--- |
| 792 |
/// store chains that are composed entirely of loaded values. |
--- |
792 |
/// store chains that are composed entirely of loaded values. |
--- |
| 793 |
bool tryStoreMergeOfLoads(SmallVectorImpl &StoreNodes, |
--- |
793 |
bool tryStoreMergeOfLoads(SmallVectorImpl &StoreNodes, |
--- |
| 794 |
unsigned NumConsecutiveStores, EVT MemVT, |
--- |
794 |
unsigned NumConsecutiveStores, EVT MemVT, |
--- |
| 795 |
SDNode *Root, bool AllowVectors, |
--- |
795 |
SDNode *Root, bool AllowVectors, |
--- |
| 796 |
bool IsNonTemporalStore, bool IsNonTemporalLoad); |
--- |
796 |
bool IsNonTemporalStore, bool IsNonTemporalLoad); |
--- |
| 797 |
|
--- |
797 |
|
--- |
| 798 |
/// Merge consecutive store operations into a wide store. |
--- |
798 |
/// Merge consecutive store operations into a wide store. |
--- |
| 799 |
/// This optimization uses wide integers or vectors when possible. |
--- |
799 |
/// This optimization uses wide integers or vectors when possible. |
--- |
| 800 |
/// \return true if stores were merged. |
--- |
800 |
/// \return true if stores were merged. |
--- |
| 801 |
bool mergeConsecutiveStores(StoreSDNode *St); |
--- |
801 |
bool mergeConsecutiveStores(StoreSDNode *St); |
--- |
| 802 |
|
--- |
802 |
|
--- |
| 803 |
/// Try to transform a truncation where C is a constant: |
--- |
803 |
/// Try to transform a truncation where C is a constant: |
--- |
| 804 |
/// (trunc (and X, C)) -> (and (trunc X), (trunc C)) |
--- |
804 |
/// (trunc (and X, C)) -> (and (trunc X), (trunc C)) |
--- |
| 805 |
/// |
--- |
805 |
/// |
--- |
| 806 |
/// \p N needs to be a truncation and its first operand an AND. Other |
--- |
806 |
/// \p N needs to be a truncation and its first operand an AND. Other |
--- |
| 807 |
/// requirements are checked by the function (e.g. that trunc is |
--- |
807 |
/// requirements are checked by the function (e.g. that trunc is |
--- |
| 808 |
/// single-use) and if missed an empty SDValue is returned. |
--- |
808 |
/// single-use) and if missed an empty SDValue is returned. |
--- |
| 809 |
SDValue distributeTruncateThroughAnd(SDNode *N); |
--- |
809 |
SDValue distributeTruncateThroughAnd(SDNode *N); |
--- |
| 810 |
|
--- |
810 |
|
--- |
| 811 |
/// Helper function to determine whether the target supports operation |
--- |
811 |
/// Helper function to determine whether the target supports operation |
--- |
| 812 |
/// given by \p Opcode for type \p VT, that is, whether the operation |
--- |
812 |
/// given by \p Opcode for type \p VT, that is, whether the operation |
--- |
| 813 |
/// is legal or custom before legalizing operations, and whether is |
--- |
813 |
/// is legal or custom before legalizing operations, and whether is |
--- |
| 814 |
/// legal (but not custom) after legalization. |
--- |
814 |
/// legal (but not custom) after legalization. |
--- |
| 815 |
bool hasOperation(unsigned Opcode, EVT VT) { |
0 |
815 |
bool hasOperation(unsigned Opcode, EVT VT) { |
0 |
| 816 |
return TLI.isOperationLegalOrCustom(Opcode, VT, LegalOperations); |
0 |
816 |
return TLI.isOperationLegalOrCustom(Opcode, VT, LegalOperations); |
0 |
| 817 |
} |
--- |
817 |
} |
--- |
| 818 |
|
--- |
818 |
|
--- |
| 819 |
public: |
--- |
819 |
public: |
--- |
| 820 |
/// Runs the dag combiner on all nodes in the work list |
--- |
820 |
/// Runs the dag combiner on all nodes in the work list |
--- |
| 821 |
void Run(CombineLevel AtLevel); |
--- |
821 |
void Run(CombineLevel AtLevel); |
--- |
| 822 |
|
--- |
822 |
|
--- |
| 823 |
SelectionDAG &getDAG() const { return DAG; } |
112 |
823 |
SelectionDAG &getDAG() const { return DAG; } |
112 |
| 824 |
|
--- |
824 |
|
--- |
| 825 |
/// Returns a type large enough to hold any valid shift amount - before type |
--- |
825 |
/// Returns a type large enough to hold any valid shift amount - before type |
--- |
| 826 |
/// legalization these can be huge. |
--- |
826 |
/// legalization these can be huge. |
--- |
| 827 |
EVT getShiftAmountTy(EVT LHSTy) { |
0 |
827 |
EVT getShiftAmountTy(EVT LHSTy) { |
0 |
| 828 |
assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); |
0 |
828 |
assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); |
0 |
| 829 |
return TLI.getShiftAmountTy(LHSTy, DAG.getDataLayout(), LegalTypes); |
0 |
829 |
return TLI.getShiftAmountTy(LHSTy, DAG.getDataLayout(), LegalTypes); |
0 |
| 830 |
} |
--- |
830 |
} |
--- |
| 831 |
|
--- |
831 |
|
--- |
| 832 |
/// This method returns true if we are running before type legalization or |
--- |
832 |
/// This method returns true if we are running before type legalization or |
--- |
| 833 |
/// if the specified VT is legal. |
--- |
833 |
/// if the specified VT is legal. |
--- |
| 834 |
bool isTypeLegal(const EVT &VT) { |
0 |
834 |
bool isTypeLegal(const EVT &VT) { |
0 |
| 835 |
if (!LegalTypes) return true; |
0 |
835 |
if (!LegalTypes) return true; |
0 |
| 836 |
return TLI.isTypeLegal(VT); |
0 |
836 |
return TLI.isTypeLegal(VT); |
0 |
| 837 |
} |
--- |
837 |
} |
--- |
| 838 |
|
--- |
838 |
|
--- |
| 839 |
/// Convenience wrapper around TargetLowering::getSetCCResultType |
--- |
839 |
/// Convenience wrapper around TargetLowering::getSetCCResultType |
--- |
| 840 |
EVT getSetCCResultType(EVT VT) const { |
0 |
840 |
EVT getSetCCResultType(EVT VT) const { |
0 |
| 841 |
return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); |
0 |
841 |
return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); |
0 |
| 842 |
} |
--- |
842 |
} |
--- |
| 843 |
|
--- |
843 |
|
--- |
| 844 |
void ExtendSetCCUses(const SmallVectorImpl &SetCCs, |
--- |
844 |
void ExtendSetCCUses(const SmallVectorImpl &SetCCs, |
--- |
| 845 |
SDValue OrigLoad, SDValue ExtLoad, |
--- |
845 |
SDValue OrigLoad, SDValue ExtLoad, |
--- |
| 846 |
ISD::NodeType ExtType); |
--- |
846 |
ISD::NodeType ExtType); |
--- |
| 847 |
}; |
--- |
847 |
}; |
--- |
| 848 |
|
--- |
848 |
|
--- |
| 849 |
/// This class is a DAGUpdateListener that removes any deleted |
--- |
849 |
/// This class is a DAGUpdateListener that removes any deleted |
--- |
| 850 |
/// nodes from the worklist. |
--- |
850 |
/// nodes from the worklist. |
--- |
| 851 |
class WorklistRemover : public SelectionDAG::DAGUpdateListener { |
--- |
851 |
class WorklistRemover : public SelectionDAG::DAGUpdateListener { |
--- |
| 852 |
DAGCombiner &DC; |
--- |
852 |
DAGCombiner &DC; |
--- |
| 853 |
|
--- |
853 |
|
--- |
| 854 |
public: |
--- |
854 |
public: |
--- |
| 855 |
explicit WorklistRemover(DAGCombiner &dc) |
103 |
855 |
explicit WorklistRemover(DAGCombiner &dc) |
103 |
| 856 |
: SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} |
103 |
856 |
: SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} |
103 |
| 857 |
|
--- |
857 |
|
--- |
| 858 |
void NodeDeleted(SDNode *N, SDNode *E) override { |
0 |
858 |
void NodeDeleted(SDNode *N, SDNode *E) override { |
0 |
| 859 |
DC.removeFromWorklist(N); |
0 |
859 |
DC.removeFromWorklist(N); |
0 |
| 860 |
} |
0 |
860 |
} |
0 |
| 861 |
}; |
--- |
861 |
}; |
--- |
| 862 |
|
--- |
862 |
|
--- |
| 863 |
class WorklistInserter : public SelectionDAG::DAGUpdateListener { |
--- |
863 |
class WorklistInserter : public SelectionDAG::DAGUpdateListener { |
--- |
| 864 |
DAGCombiner &DC; |
--- |
864 |
DAGCombiner &DC; |
--- |
| 865 |
|
--- |
865 |
|
--- |
| 866 |
public: |
--- |
866 |
public: |
--- |
| 867 |
explicit WorklistInserter(DAGCombiner &dc) |
9 |
867 |
explicit WorklistInserter(DAGCombiner &dc) |
9 |
| 868 |
: SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} |
9 |
868 |
: SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} |
9 |
| 869 |
|
--- |
869 |
|
--- |
| 870 |
// FIXME: Ideally we could add N to the worklist, but this causes exponential |
--- |
870 |
// FIXME: Ideally we could add N to the worklist, but this causes exponential |
--- |
| 871 |
// compile time costs in large DAGs, e.g. Halide. |
--- |
871 |
// compile time costs in large DAGs, e.g. Halide. |
--- |
| 872 |
void NodeInserted(SDNode *N) override { DC.ConsiderForPruning(N); } |
3 |
872 |
void NodeInserted(SDNode *N) override { DC.ConsiderForPruning(N); } |
3 |
| 873 |
}; |
--- |
873 |
}; |
--- |
| 874 |
|
--- |
874 |
|
--- |
| 875 |
class EmptyMatchContext { |
--- |
875 |
class EmptyMatchContext { |
--- |
| 876 |
SelectionDAG &DAG; |
--- |
876 |
SelectionDAG &DAG; |
--- |
| 877 |
const TargetLowering &TLI; |
--- |
877 |
const TargetLowering &TLI; |
--- |
| 878 |
|
--- |
878 |
|
--- |
| 879 |
public: |
--- |
879 |
public: |
--- |
| 880 |
EmptyMatchContext(SelectionDAG &DAG, const TargetLowering &TLI, SDNode *Root) |
0 |
880 |
EmptyMatchContext(SelectionDAG &DAG, const TargetLowering &TLI, SDNode *Root) |
0 |
| 881 |
: DAG(DAG), TLI(TLI) {} |
0 |
881 |
: DAG(DAG), TLI(TLI) {} |
0 |
| 882 |
|
--- |
882 |
|
--- |
| 883 |
bool match(SDValue OpN, unsigned Opcode) const { |
0 |
883 |
bool match(SDValue OpN, unsigned Opcode) const { |
0 |
| 884 |
return Opcode == OpN->getOpcode(); |
0 |
884 |
return Opcode == OpN->getOpcode(); |
0 |
| 885 |
} |
--- |
885 |
} |
--- |
| 886 |
|
--- |
886 |
|
--- |
| 887 |
// Same as SelectionDAG::getNode(). |
--- |
887 |
// Same as SelectionDAG::getNode(). |
--- |
| 888 |
template SDValue getNode(ArgT &&...Args) { |
0 |
888 |
template SDValue getNode(ArgT &&...Args) { |
0 |
| 889 |
return DAG.getNode(std::forward(Args)...); |
0 |
889 |
return DAG.getNode(std::forward(Args)...); |
0 |
| 890 |
} |
--- |
890 |
} |
--- |
| 891 |
|
--- |
891 |
|
--- |
| 892 |
bool isOperationLegalOrCustom(unsigned Op, EVT VT, |
0 |
892 |
bool isOperationLegalOrCustom(unsigned Op, EVT VT, |
0 |
| 893 |
bool LegalOnly = false) const { |
--- |
893 |
bool LegalOnly = false) const { |
--- |
| 894 |
return TLI.isOperationLegalOrCustom(Op, VT, LegalOnly); |
0 |
894 |
return TLI.isOperationLegalOrCustom(Op, VT, LegalOnly); |
0 |
| 895 |
} |
--- |
895 |
} |
--- |
| 896 |
}; |
--- |
896 |
}; |
--- |
| 897 |
|
--- |
897 |
|
--- |
| 898 |
class VPMatchContext { |
--- |
898 |
class VPMatchContext { |
--- |
| 899 |
SelectionDAG &DAG; |
--- |
899 |
SelectionDAG &DAG; |
--- |
| 900 |
const TargetLowering &TLI; |
--- |
900 |
const TargetLowering &TLI; |
--- |
| 901 |
SDValue RootMaskOp; |
--- |
901 |
SDValue RootMaskOp; |
--- |
| 902 |
SDValue RootVectorLenOp; |
--- |
902 |
SDValue RootVectorLenOp; |
--- |
| 903 |
|
--- |
903 |
|
--- |
| 904 |
public: |
--- |
904 |
public: |
--- |
| 905 |
VPMatchContext(SelectionDAG &DAG, const TargetLowering &TLI, SDNode *Root) |
0 |
905 |
VPMatchContext(SelectionDAG &DAG, const TargetLowering &TLI, SDNode *Root) |
0 |
| 906 |
: DAG(DAG), TLI(TLI), RootMaskOp(), RootVectorLenOp() { |
0 |
906 |
: DAG(DAG), TLI(TLI), RootMaskOp(), RootVectorLenOp() { |
0 |
| 907 |
assert(Root->isVPOpcode()); |
0 |
907 |
assert(Root->isVPOpcode()); |
0 |
| 908 |
if (auto RootMaskPos = ISD::getVPMaskIdx(Root->getOpcode())) |
0 |
908 |
if (auto RootMaskPos = ISD::getVPMaskIdx(Root->getOpcode())) |
0 |
| 909 |
RootMaskOp = Root->getOperand(*RootMaskPos); |
0 |
909 |
RootMaskOp = Root->getOperand(*RootMaskPos); |
0 |
| 910 |
|
--- |
910 |
|
--- |
| 911 |
if (auto RootVLenPos = |
0 |
911 |
if (auto RootVLenPos = |
0 |
| 912 |
ISD::getVPExplicitVectorLengthIdx(Root->getOpcode())) |
0 |
912 |
ISD::getVPExplicitVectorLengthIdx(Root->getOpcode())) |
0 |
| 913 |
RootVectorLenOp = Root->getOperand(*RootVLenPos); |
0 |
913 |
RootVectorLenOp = Root->getOperand(*RootVLenPos); |
0 |
| 914 |
} |
0 |
914 |
} |
0 |
| 915 |
|
--- |
915 |
|
--- |
| 916 |
/// whether \p OpVal is a node that is functionally compatible with the |
--- |
916 |
/// whether \p OpVal is a node that is functionally compatible with the |
--- |
| 917 |
/// NodeType \p Opc |
--- |
917 |
/// NodeType \p Opc |
--- |
| 918 |
bool match(SDValue OpVal, unsigned Opc) const { |
0 |
918 |
bool match(SDValue OpVal, unsigned Opc) const { |
0 |
| 919 |
if (!OpVal->isVPOpcode()) |
0 |
919 |
if (!OpVal->isVPOpcode()) |
0 |
| 920 |
return OpVal->getOpcode() == Opc; |
0 |
920 |
return OpVal->getOpcode() == Opc; |
0 |
| 921 |
|
--- |
921 |
|
--- |
| 922 |
auto BaseOpc = ISD::getBaseOpcodeForVP(OpVal->getOpcode(), |
0 |
922 |
auto BaseOpc = ISD::getBaseOpcodeForVP(OpVal->getOpcode(), |
0 |
| 923 |
!OpVal->getFlags().hasNoFPExcept()); |
0 |
923 |
!OpVal->getFlags().hasNoFPExcept()); |
0 |
| 924 |
if (BaseOpc != Opc) |
0 |
924 |
if (BaseOpc != Opc) |
0 |
| 925 |
return false; |
0 |
925 |
return false; |
0 |
| 926 |
|
--- |
926 |
|
--- |
| 927 |
// Make sure the mask of OpVal is true mask or is same as Root's. |
--- |
927 |
// Make sure the mask of OpVal is true mask or is same as Root's. |
--- |
| 928 |
unsigned VPOpcode = OpVal->getOpcode(); |
0 |
928 |
unsigned VPOpcode = OpVal->getOpcode(); |
0 |
| 929 |
if (auto MaskPos = ISD::getVPMaskIdx(VPOpcode)) { |
0 |
929 |
if (auto MaskPos = ISD::getVPMaskIdx(VPOpcode)) { |
0 |
| 930 |
SDValue MaskOp = OpVal.getOperand(*MaskPos); |
0 |
930 |
SDValue MaskOp = OpVal.getOperand(*MaskPos); |
0 |
| 931 |
if (RootMaskOp != MaskOp && |
0 |
931 |
if (RootMaskOp != MaskOp && |
0 |
| 932 |
!ISD::isConstantSplatVectorAllOnes(MaskOp.getNode())) |
0 |
932 |
!ISD::isConstantSplatVectorAllOnes(MaskOp.getNode())) |
0 |
| 933 |
return false; |
0 |
933 |
return false; |
0 |
| 934 |
} |
--- |
934 |
} |
--- |
| 935 |
|
--- |
935 |
|
--- |
| 936 |
// Make sure the EVL of OpVal is same as Root's. |
--- |
936 |
// Make sure the EVL of OpVal is same as Root's. |
--- |
| 937 |
if (auto VLenPos = ISD::getVPExplicitVectorLengthIdx(VPOpcode)) |
0 |
937 |
if (auto VLenPos = ISD::getVPExplicitVectorLengthIdx(VPOpcode)) |
0 |
| 938 |
if (RootVectorLenOp != OpVal.getOperand(*VLenPos)) |
0 |
938 |
if (RootVectorLenOp != OpVal.getOperand(*VLenPos)) |
0 |
| 939 |
return false; |
0 |
939 |
return false; |
0 |
| 940 |
return true; |
0 |
940 |
return true; |
0 |
| 941 |
} |
--- |
941 |
} |
--- |
| 942 |
|
--- |
942 |
|
--- |
| 943 |
// Specialize based on number of operands. |
--- |
943 |
// Specialize based on number of operands. |
--- |
| 944 |
// TODO emit VP intrinsics where MaskOp/VectorLenOp != null |
--- |
944 |
// TODO emit VP intrinsics where MaskOp/VectorLenOp != null |
--- |
| 945 |
// SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT) { return |
--- |
945 |
// SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT) { return |
--- |
| 946 |
// DAG.getNode(Opcode, DL, VT); } |
--- |
946 |
// DAG.getNode(Opcode, DL, VT); } |
--- |
| 947 |
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) { |
0 |
947 |
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) { |
0 |
| 948 |
unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); |
0 |
948 |
unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); |
0 |
| 949 |
assert(ISD::getVPMaskIdx(VPOpcode) == 1 && |
0 |
949 |
assert(ISD::getVPMaskIdx(VPOpcode) == 1 && |
0 |
| 950 |
ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 2); |
--- |
950 |
ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 2); |
--- |
| 951 |
return DAG.getNode(VPOpcode, DL, VT, |
0 |
951 |
return DAG.getNode(VPOpcode, DL, VT, |
0 |
| 952 |
{Operand, RootMaskOp, RootVectorLenOp}); |
0 |
952 |
{Operand, RootMaskOp, RootVectorLenOp}); |
0 |
| 953 |
} |
--- |
953 |
} |
--- |
| 954 |
|
--- |
954 |
|
--- |
| 955 |
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
0 |
955 |
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
0 |
| 956 |
SDValue N2) { |
--- |
956 |
SDValue N2) { |
--- |
| 957 |
unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); |
0 |
957 |
unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); |
0 |
| 958 |
assert(ISD::getVPMaskIdx(VPOpcode) == 2 && |
0 |
958 |
assert(ISD::getVPMaskIdx(VPOpcode) == 2 && |
0 |
| 959 |
ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 3); |
--- |
959 |
ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 3); |
--- |
| 960 |
return DAG.getNode(VPOpcode, DL, VT, |
0 |
960 |
return DAG.getNode(VPOpcode, DL, VT, |
0 |
| 961 |
{N1, N2, RootMaskOp, RootVectorLenOp}); |
0 |
961 |
{N1, N2, RootMaskOp, RootVectorLenOp}); |
0 |
| 962 |
} |
--- |
962 |
} |
--- |
| 963 |
|
--- |
963 |
|
--- |
| 964 |
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
0 |
964 |
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
0 |
| 965 |
SDValue N2, SDValue N3) { |
--- |
965 |
SDValue N2, SDValue N3) { |
--- |
| 966 |
unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); |
0 |
966 |
unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); |
0 |
| 967 |
assert(ISD::getVPMaskIdx(VPOpcode) == 3 && |
0 |
967 |
assert(ISD::getVPMaskIdx(VPOpcode) == 3 && |
0 |
| 968 |
ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 4); |
--- |
968 |
ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 4); |
--- |
| 969 |
return DAG.getNode(VPOpcode, DL, VT, |
0 |
969 |
return DAG.getNode(VPOpcode, DL, VT, |
0 |
| 970 |
{N1, N2, N3, RootMaskOp, RootVectorLenOp}); |
0 |
970 |
{N1, N2, N3, RootMaskOp, RootVectorLenOp}); |
0 |
| 971 |
} |
--- |
971 |
} |
--- |
| 972 |
|
--- |
972 |
|
--- |
| 973 |
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand, |
--- |
973 |
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand, |
--- |
| 974 |
SDNodeFlags Flags) { |
--- |
974 |
SDNodeFlags Flags) { |
--- |
| 975 |
unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); |
--- |
975 |
unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); |
--- |
| 976 |
assert(ISD::getVPMaskIdx(VPOpcode) == 1 && |
--- |
976 |
assert(ISD::getVPMaskIdx(VPOpcode) == 1 && |
--- |
| 977 |
ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 2); |
--- |
977 |
ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 2); |
--- |
| 978 |
return DAG.getNode(VPOpcode, DL, VT, {Operand, RootMaskOp, RootVectorLenOp}, |
--- |
978 |
return DAG.getNode(VPOpcode, DL, VT, {Operand, RootMaskOp, RootVectorLenOp}, |
--- |
| 979 |
Flags); |
--- |
979 |
Flags); |
--- |
| 980 |
} |
--- |
980 |
} |
--- |
| 981 |
|
--- |
981 |
|
--- |
| 982 |
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
--- |
982 |
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
--- |
| 983 |
SDValue N2, SDNodeFlags Flags) { |
--- |
983 |
SDValue N2, SDNodeFlags Flags) { |
--- |
| 984 |
unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); |
--- |
984 |
unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); |
--- |
| 985 |
assert(ISD::getVPMaskIdx(VPOpcode) == 2 && |
--- |
985 |
assert(ISD::getVPMaskIdx(VPOpcode) == 2 && |
--- |
| 986 |
ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 3); |
--- |
986 |
ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 3); |
--- |
| 987 |
return DAG.getNode(VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp}, |
--- |
987 |
return DAG.getNode(VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp}, |
--- |
| 988 |
Flags); |
--- |
988 |
Flags); |
--- |
| 989 |
} |
--- |
989 |
} |
--- |
| 990 |
|
--- |
990 |
|
--- |
| 991 |
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
--- |
991 |
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, |
--- |
| 992 |
SDValue N2, SDValue N3, SDNodeFlags Flags) { |
--- |
992 |
SDValue N2, SDValue N3, SDNodeFlags Flags) { |
--- |
| 993 |
unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); |
--- |
993 |
unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); |
--- |
| 994 |
assert(ISD::getVPMaskIdx(VPOpcode) == 3 && |
--- |
994 |
assert(ISD::getVPMaskIdx(VPOpcode) == 3 && |
--- |
| 995 |
ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 4); |
--- |
995 |
ISD::getVPExplicitVectorLengthIdx(VPOpcode) == 4); |
--- |
| 996 |
return DAG.getNode(VPOpcode, DL, VT, |
--- |
996 |
return DAG.getNode(VPOpcode, DL, VT, |
--- |
| 997 |
{N1, N2, N3, RootMaskOp, RootVectorLenOp}, Flags); |
--- |
997 |
{N1, N2, N3, RootMaskOp, RootVectorLenOp}, Flags); |
--- |
| 998 |
} |
--- |
998 |
} |
--- |
| 999 |
|
--- |
999 |
|
--- |
| 1000 |
bool isOperationLegalOrCustom(unsigned Op, EVT VT, |
0 |
1000 |
bool isOperationLegalOrCustom(unsigned Op, EVT VT, |
0 |
| 1001 |
bool LegalOnly = false) const { |
--- |
1001 |
bool LegalOnly = false) const { |
--- |
| 1002 |
unsigned VPOp = ISD::getVPForBaseOpcode(Op); |
0 |
1002 |
unsigned VPOp = ISD::getVPForBaseOpcode(Op); |
0 |
| 1003 |
return TLI.isOperationLegalOrCustom(VPOp, VT, LegalOnly); |
0 |
1003 |
return TLI.isOperationLegalOrCustom(VPOp, VT, LegalOnly); |
0 |
| 1004 |
} |
--- |
1004 |
} |
--- |
| 1005 |
}; |
--- |
1005 |
}; |
--- |
| 1006 |
|
--- |
1006 |
|
--- |
| 1007 |
} // end anonymous namespace |
--- |
1007 |
} // end anonymous namespace |
--- |
| 1008 |
|
--- |
1008 |
|
--- |
| 1009 |
//===----------------------------------------------------------------------===// |
--- |
1009 |
//===----------------------------------------------------------------------===// |
--- |
| 1010 |
// TargetLowering::DAGCombinerInfo implementation |
--- |
1010 |
// TargetLowering::DAGCombinerInfo implementation |
--- |
| 1011 |
//===----------------------------------------------------------------------===// |
--- |
1011 |
//===----------------------------------------------------------------------===// |
--- |
| 1012 |
|
--- |
1012 |
|
--- |
| 1013 |
void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { |
0 |
1013 |
void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { |
0 |
| 1014 |
((DAGCombiner*)DC)->AddToWorklist(N); |
0 |
1014 |
((DAGCombiner*)DC)->AddToWorklist(N); |
0 |
| 1015 |
} |
0 |
1015 |
} |
0 |
| 1016 |
|
--- |
1016 |
|
--- |
| 1017 |
SDValue TargetLowering::DAGCombinerInfo:: |
0 |
1017 |
SDValue TargetLowering::DAGCombinerInfo:: |
0 |
| 1018 |
CombineTo(SDNode *N, ArrayRef To, bool AddTo) { |
--- |
1018 |
CombineTo(SDNode *N, ArrayRef To, bool AddTo) { |
--- |
| 1019 |
return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); |
0 |
1019 |
return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); |
0 |
| 1020 |
} |
--- |
1020 |
} |
--- |
| 1021 |
|
--- |
1021 |
|
--- |
| 1022 |
SDValue TargetLowering::DAGCombinerInfo:: |
0 |
1022 |
SDValue TargetLowering::DAGCombinerInfo:: |
0 |
| 1023 |
CombineTo(SDNode *N, SDValue Res, bool AddTo) { |
--- |
1023 |
CombineTo(SDNode *N, SDValue Res, bool AddTo) { |
--- |
| 1024 |
return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); |
0 |
1024 |
return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); |
0 |
| 1025 |
} |
--- |
1025 |
} |
--- |
| 1026 |
|
--- |
1026 |
|
--- |
| 1027 |
SDValue TargetLowering::DAGCombinerInfo:: |
0 |
1027 |
SDValue TargetLowering::DAGCombinerInfo:: |
0 |
| 1028 |
CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { |
--- |
1028 |
CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { |
--- |
| 1029 |
return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); |
0 |
1029 |
return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); |
0 |
| 1030 |
} |
--- |
1030 |
} |
--- |
| 1031 |
|
--- |
1031 |
|
--- |
| 1032 |
bool TargetLowering::DAGCombinerInfo:: |
0 |
1032 |
bool TargetLowering::DAGCombinerInfo:: |
0 |
| 1033 |
recursivelyDeleteUnusedNodes(SDNode *N) { |
--- |
1033 |
recursivelyDeleteUnusedNodes(SDNode *N) { |
--- |
| 1034 |
return ((DAGCombiner*)DC)->recursivelyDeleteUnusedNodes(N); |
0 |
1034 |
return ((DAGCombiner*)DC)->recursivelyDeleteUnusedNodes(N); |
0 |
| 1035 |
} |
--- |
1035 |
} |
--- |
| 1036 |
|
--- |
1036 |
|
--- |
| 1037 |
void TargetLowering::DAGCombinerInfo:: |
0 |
1037 |
void TargetLowering::DAGCombinerInfo:: |
0 |
| 1038 |
CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { |
--- |
1038 |
CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { |
--- |
| 1039 |
return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); |
0 |
1039 |
return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); |
0 |
| 1040 |
} |
--- |
1040 |
} |
--- |
| 1041 |
|
--- |
1041 |
|
--- |
| 1042 |
//===----------------------------------------------------------------------===// |
--- |
1042 |
//===----------------------------------------------------------------------===// |
--- |
| 1043 |
// Helper Functions |
--- |
1043 |
// Helper Functions |
--- |
| 1044 |
//===----------------------------------------------------------------------===// |
--- |
1044 |
//===----------------------------------------------------------------------===// |
--- |
| 1045 |
|
--- |
1045 |
|
--- |
| 1046 |
void DAGCombiner::deleteAndRecombine(SDNode *N) { |
0 |
1046 |
void DAGCombiner::deleteAndRecombine(SDNode *N) { |
0 |
| 1047 |
removeFromWorklist(N); |
0 |
1047 |
removeFromWorklist(N); |
0 |
| 1048 |
|
--- |
1048 |
|
--- |
| 1049 |
// If the operands of this node are only used by the node, they will now be |
--- |
1049 |
// If the operands of this node are only used by the node, they will now be |
--- |
| 1050 |
// dead. Make sure to re-visit them and recursively delete dead nodes. |
--- |
1050 |
// dead. Make sure to re-visit them and recursively delete dead nodes. |
--- |
| 1051 |
for (const SDValue &Op : N->ops()) |
0 |
1051 |
for (const SDValue &Op : N->ops()) |
0 |
| 1052 |
// For an operand generating multiple values, one of the values may |
--- |
1052 |
// For an operand generating multiple values, one of the values may |
--- |
| 1053 |
// become dead allowing further simplification (e.g. split index |
--- |
1053 |
// become dead allowing further simplification (e.g. split index |
--- |
| 1054 |
// arithmetic from an indexed load). |
--- |
1054 |
// arithmetic from an indexed load). |
--- |
| 1055 |
if (Op->hasOneUse() || Op->getNumValues() > 1) |
0 |
1055 |
if (Op->hasOneUse() || Op->getNumValues() > 1) |
0 |
| 1056 |
AddToWorklist(Op.getNode()); |
0 |
1056 |
AddToWorklist(Op.getNode()); |
0 |
| 1057 |
|
--- |
1057 |
|
--- |
| 1058 |
DAG.DeleteNode(N); |
0 |
1058 |
DAG.DeleteNode(N); |
0 |
| 1059 |
} |
0 |
1059 |
} |
0 |
| 1060 |
|
--- |
1060 |
|
--- |
| 1061 |
// APInts must be the same size for most operations, this helper |
--- |
1061 |
// APInts must be the same size for most operations, this helper |
--- |
| 1062 |
// function zero extends the shorter of the pair so that they match. |
--- |
1062 |
// function zero extends the shorter of the pair so that they match. |
--- |
| 1063 |
// We provide an Offset so that we can create bitwidths that won't overflow. |
--- |
1063 |
// We provide an Offset so that we can create bitwidths that won't overflow. |
--- |
| 1064 |
static void zeroExtendToMatch(APInt &LHS, APInt &RHS, unsigned Offset = 0) { |
0 |
1064 |
static void zeroExtendToMatch(APInt &LHS, APInt &RHS, unsigned Offset = 0) { |
0 |
| 1065 |
unsigned Bits = Offset + std::max(LHS.getBitWidth(), RHS.getBitWidth()); |
0 |
1065 |
unsigned Bits = Offset + std::max(LHS.getBitWidth(), RHS.getBitWidth()); |
0 |
| 1066 |
LHS = LHS.zext(Bits); |
0 |
1066 |
LHS = LHS.zext(Bits); |
0 |
| 1067 |
RHS = RHS.zext(Bits); |
0 |
1067 |
RHS = RHS.zext(Bits); |
0 |
| 1068 |
} |
0 |
1068 |
} |
0 |
| 1069 |
|
--- |
1069 |
|
--- |
| 1070 |
// Return true if this node is a setcc, or is a select_cc |
--- |
1070 |
// Return true if this node is a setcc, or is a select_cc |
--- |
| 1071 |
// that selects between the target values used for true and false, making it |
--- |
1071 |
// that selects between the target values used for true and false, making it |
--- |
| 1072 |
// equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to |
--- |
1072 |
// equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to |
--- |
| 1073 |
// the appropriate nodes based on the type of node we are checking. This |
--- |
1073 |
// the appropriate nodes based on the type of node we are checking. This |
--- |
| 1074 |
// simplifies life a bit for the callers. |
--- |
1074 |
// simplifies life a bit for the callers. |
--- |
| 1075 |
bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, |
3 |
1075 |
bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, |
3 |
| 1076 |
SDValue &CC, bool MatchStrict) const { |
--- |
1076 |
SDValue &CC, bool MatchStrict) const { |
--- |
| 1077 |
if (N.getOpcode() == ISD::SETCC) { |
3 |
1077 |
if (N.getOpcode() == ISD::SETCC) { |
3 |
| 1078 |
LHS = N.getOperand(0); |
2 |
1078 |
LHS = N.getOperand(0); |
2 |
| 1079 |
RHS = N.getOperand(1); |
2 |
1079 |
RHS = N.getOperand(1); |
2 |
| 1080 |
CC = N.getOperand(2); |
2 |
1080 |
CC = N.getOperand(2); |
2 |
| 1081 |
return true; |
2 |
1081 |
return true; |
2 |
| 1082 |
} |
--- |
1082 |
} |
--- |
| 1083 |
|
--- |
1083 |
|
--- |
| 1084 |
if (MatchStrict && |
1 |
1084 |
if (MatchStrict && |
1 |
| 1085 |
(N.getOpcode() == ISD::STRICT_FSETCC || |
0 |
1085 |
(N.getOpcode() == ISD::STRICT_FSETCC || |
0 |
| 1086 |
N.getOpcode() == ISD::STRICT_FSETCCS)) { |
0 |
1086 |
N.getOpcode() == ISD::STRICT_FSETCCS)) { |
0 |
| 1087 |
LHS = N.getOperand(1); |
0 |
1087 |
LHS = N.getOperand(1); |
0 |
| 1088 |
RHS = N.getOperand(2); |
0 |
1088 |
RHS = N.getOperand(2); |
0 |
| 1089 |
CC = N.getOperand(3); |
0 |
1089 |
CC = N.getOperand(3); |
0 |
| 1090 |
return true; |
0 |
1090 |
return true; |
0 |
| 1091 |
} |
--- |
1091 |
} |
--- |
| 1092 |
|
--- |
1092 |
|
--- |
| 1093 |
if (N.getOpcode() != ISD::SELECT_CC || !TLI.isConstTrueVal(N.getOperand(2)) || |
1 |
1093 |
if (N.getOpcode() != ISD::SELECT_CC || !TLI.isConstTrueVal(N.getOperand(2)) || |
1 |
| 1094 |
!TLI.isConstFalseVal(N.getOperand(3))) |
0 |
1094 |
!TLI.isConstFalseVal(N.getOperand(3))) |
0 |
| 1095 |
return false; |
1 |
1095 |
return false; |
1 |
| 1096 |
|
--- |
1096 |
|
--- |
| 1097 |
if (TLI.getBooleanContents(N.getValueType()) == |
0 |
1097 |
if (TLI.getBooleanContents(N.getValueType()) == |
0 |
| 1098 |
TargetLowering::UndefinedBooleanContent) |
--- |
1098 |
TargetLowering::UndefinedBooleanContent) |
--- |
| 1099 |
return false; |
0 |
1099 |
return false; |
0 |
| 1100 |
|
--- |
1100 |
|
--- |
| 1101 |
LHS = N.getOperand(0); |
0 |
1101 |
LHS = N.getOperand(0); |
0 |
| 1102 |
RHS = N.getOperand(1); |
0 |
1102 |
RHS = N.getOperand(1); |
0 |
| 1103 |
CC = N.getOperand(4); |
0 |
1103 |
CC = N.getOperand(4); |
0 |
| 1104 |
return true; |
0 |
1104 |
return true; |
0 |
| 1105 |
} |
--- |
1105 |
} |
--- |
| 1106 |
|
--- |
1106 |
|
--- |
| 1107 |
/// Return true if this is a SetCC-equivalent operation with only one use. |
--- |
1107 |
/// Return true if this is a SetCC-equivalent operation with only one use. |
--- |
| 1108 |
/// If this is true, it allows the users to invert the operation for free when |
--- |
1108 |
/// If this is true, it allows the users to invert the operation for free when |
--- |
| 1109 |
/// it is profitable to do so. |
--- |
1109 |
/// it is profitable to do so. |
--- |
| 1110 |
bool DAGCombiner::isOneUseSetCC(SDValue N) const { |
0 |
1110 |
bool DAGCombiner::isOneUseSetCC(SDValue N) const { |
0 |
| 1111 |
SDValue N0, N1, N2; |
0 |
1111 |
SDValue N0, N1, N2; |
0 |
| 1112 |
if (isSetCCEquivalent(N, N0, N1, N2) && N->hasOneUse()) |
0 |
1112 |
if (isSetCCEquivalent(N, N0, N1, N2) && N->hasOneUse()) |
0 |
| 1113 |
return true; |
0 |
1113 |
return true; |
0 |
| 1114 |
return false; |
0 |
1114 |
return false; |
0 |
| 1115 |
} |
--- |
1115 |
} |
--- |
| 1116 |
|
--- |
1116 |
|
--- |
| 1117 |
static bool isConstantSplatVectorMaskForType(SDNode *N, EVT ScalarTy) { |
0 |
1117 |
static bool isConstantSplatVectorMaskForType(SDNode *N, EVT ScalarTy) { |
0 |
| 1118 |
if (!ScalarTy.isSimple()) |
0 |
1118 |
if (!ScalarTy.isSimple()) |
0 |
| 1119 |
return false; |
0 |
1119 |
return false; |
0 |
| 1120 |
|
--- |
1120 |
|
--- |
| 1121 |
uint64_t MaskForTy = 0ULL; |
0 |
1121 |
uint64_t MaskForTy = 0ULL; |
0 |
| 1122 |
switch (ScalarTy.getSimpleVT().SimpleTy) { |
0 |
1122 |
switch (ScalarTy.getSimpleVT().SimpleTy) { |
0 |
| 1123 |
case MVT::i8: |
0 |
1123 |
case MVT::i8: |
0 |
| 1124 |
MaskForTy = 0xFFULL; |
0 |
1124 |
MaskForTy = 0xFFULL; |
0 |
| 1125 |
break; |
0 |
1125 |
break; |
0 |
| 1126 |
case MVT::i16: |
0 |
1126 |
case MVT::i16: |
0 |
| 1127 |
MaskForTy = 0xFFFFULL; |
0 |
1127 |
MaskForTy = 0xFFFFULL; |
0 |
| 1128 |
break; |
0 |
1128 |
break; |
0 |
| 1129 |
case MVT::i32: |
0 |
1129 |
case MVT::i32: |
0 |
| 1130 |
MaskForTy = 0xFFFFFFFFULL; |
0 |
1130 |
MaskForTy = 0xFFFFFFFFULL; |
0 |
| 1131 |
break; |
0 |
1131 |
break; |
0 |
| 1132 |
default: |
0 |
1132 |
default: |
0 |
| 1133 |
return false; |
0 |
1133 |
return false; |
0 |
| 1134 |
break; |
--- |
1134 |
break; |
--- |
| 1135 |
} |
--- |
1135 |
} |
--- |
| 1136 |
|
--- |
1136 |
|
--- |
| 1137 |
APInt Val; |
0 |
1137 |
APInt Val; |
0 |
| 1138 |
if (ISD::isConstantSplatVector(N, Val)) |
0 |
1138 |
if (ISD::isConstantSplatVector(N, Val)) |
0 |
| 1139 |
return Val.getLimitedValue() == MaskForTy; |
0 |
1139 |
return Val.getLimitedValue() == MaskForTy; |
0 |
| 1140 |
|
--- |
1140 |
|
--- |
| 1141 |
return false; |
0 |
1141 |
return false; |
0 |
| 1142 |
} |
--- |
1142 |
} |
--- |
| 1143 |
|
--- |
1143 |
|
--- |
| 1144 |
// Determines if it is a constant integer or a splat/build vector of constant |
--- |
1144 |
// Determines if it is a constant integer or a splat/build vector of constant |
--- |
| 1145 |
// integers (and undefs). |
--- |
1145 |
// integers (and undefs). |
--- |
| 1146 |
// Do not permit build vector implicit truncation. |
--- |
1146 |
// Do not permit build vector implicit truncation. |
--- |
| 1147 |
static bool isConstantOrConstantVector(SDValue N, bool NoOpaques = false) { |
0 |
1147 |
static bool isConstantOrConstantVector(SDValue N, bool NoOpaques = false) { |
0 |
| 1148 |
if (ConstantSDNode *Const = dyn_cast(N)) |
0 |
1148 |
if (ConstantSDNode *Const = dyn_cast(N)) |
0 |
| 1149 |
return !(Const->isOpaque() && NoOpaques); |
0 |
1149 |
return !(Const->isOpaque() && NoOpaques); |
0 |
| 1150 |
if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) |
0 |
1150 |
if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) |
0 |
| 1151 |
return false; |
0 |
1151 |
return false; |
0 |
| 1152 |
unsigned BitWidth = N.getScalarValueSizeInBits(); |
0 |
1152 |
unsigned BitWidth = N.getScalarValueSizeInBits(); |
0 |
| 1153 |
for (const SDValue &Op : N->op_values()) { |
0 |
1153 |
for (const SDValue &Op : N->op_values()) { |
0 |
| 1154 |
if (Op.isUndef()) |
0 |
1154 |
if (Op.isUndef()) |
0 |
| 1155 |
continue; |
0 |
1155 |
continue; |
0 |
| 1156 |
ConstantSDNode *Const = dyn_cast(Op); |
0 |
1156 |
ConstantSDNode *Const = dyn_cast(Op); |
0 |
| 1157 |
if (!Const || Const->getAPIntValue().getBitWidth() != BitWidth || |
0 |
1157 |
if (!Const || Const->getAPIntValue().getBitWidth() != BitWidth || |
0 |
| 1158 |
(Const->isOpaque() && NoOpaques)) |
0 |
1158 |
(Const->isOpaque() && NoOpaques)) |
0 |
| 1159 |
return false; |
0 |
1159 |
return false; |
0 |
| 1160 |
} |
--- |
1160 |
} |
--- |
| 1161 |
return true; |
0 |
1161 |
return true; |
0 |
| 1162 |
} |
--- |
1162 |
} |
--- |
| 1163 |
|
--- |
1163 |
|
--- |
| 1164 |
// Determines if a BUILD_VECTOR is composed of all-constants possibly mixed with |
--- |
1164 |
// Determines if a BUILD_VECTOR is composed of all-constants possibly mixed with |
--- |
| 1165 |
// undef's. |
--- |
1165 |
// undef's. |
--- |
| 1166 |
static bool isAnyConstantBuildVector(SDValue V, bool NoOpaques = false) { |
0 |
1166 |
static bool isAnyConstantBuildVector(SDValue V, bool NoOpaques = false) { |
0 |
| 1167 |
if (V.getOpcode() != ISD::BUILD_VECTOR) |
0 |
1167 |
if (V.getOpcode() != ISD::BUILD_VECTOR) |
0 |
| 1168 |
return false; |
0 |
1168 |
return false; |
0 |
| 1169 |
return isConstantOrConstantVector(V, NoOpaques) || |
0 |
1169 |
return isConstantOrConstantVector(V, NoOpaques) || |
0 |
| 1170 |
ISD::isBuildVectorOfConstantFPSDNodes(V.getNode()); |
0 |
1170 |
ISD::isBuildVectorOfConstantFPSDNodes(V.getNode()); |
0 |
| 1171 |
} |
--- |
1171 |
} |
--- |
| 1172 |
|
--- |
1172 |
|
--- |
| 1173 |
// Determine if this an indexed load with an opaque target constant index. |
--- |
1173 |
// Determine if this an indexed load with an opaque target constant index. |
--- |
| 1174 |
static bool canSplitIdx(LoadSDNode *LD) { |
0 |
1174 |
static bool canSplitIdx(LoadSDNode *LD) { |
0 |
| 1175 |
return MaySplitLoadIndex && |
0 |
1175 |
return MaySplitLoadIndex && |
0 |
| 1176 |
(LD->getOperand(2).getOpcode() != ISD::TargetConstant || |
0 |
1176 |
(LD->getOperand(2).getOpcode() != ISD::TargetConstant || |
0 |
| 1177 |
!cast(LD->getOperand(2))->isOpaque()); |
0 |
1177 |
!cast(LD->getOperand(2))->isOpaque()); |
0 |
| 1178 |
} |
--- |
1178 |
} |
--- |
| 1179 |
|
--- |
1179 |
|
--- |
| 1180 |
bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc, |
1 |
1180 |
bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc, |
1 |
| 1181 |
const SDLoc &DL, |
--- |
1181 |
const SDLoc &DL, |
--- |
| 1182 |
SDNode *N, |
--- |
1182 |
SDNode *N, |
--- |
| 1183 |
SDValue N0, |
--- |
1183 |
SDValue N0, |
--- |
| 1184 |
SDValue N1) { |
--- |
1184 |
SDValue N1) { |
--- |
| 1185 |
// Currently this only tries to ensure we don't undo the GEP splits done by |
--- |
1185 |
// Currently this only tries to ensure we don't undo the GEP splits done by |
--- |
| 1186 |
// CodeGenPrepare when shouldConsiderGEPOffsetSplit is true. To ensure this, |
--- |
1186 |
// CodeGenPrepare when shouldConsiderGEPOffsetSplit is true. To ensure this, |
--- |
| 1187 |
// we check if the following transformation would be problematic: |
--- |
1187 |
// we check if the following transformation would be problematic: |
--- |
| 1188 |
// (load/store (add, (add, x, offset1), offset2)) -> |
--- |
1188 |
// (load/store (add, (add, x, offset1), offset2)) -> |
--- |
| 1189 |
// (load/store (add, x, offset1+offset2)). |
--- |
1189 |
// (load/store (add, x, offset1+offset2)). |
--- |
| 1190 |
|
--- |
1190 |
|
--- |
| 1191 |
// (load/store (add, (add, x, y), offset2)) -> |
--- |
1191 |
// (load/store (add, (add, x, y), offset2)) -> |
--- |
| 1192 |
// (load/store (add, (add, x, offset2), y)). |
--- |
1192 |
// (load/store (add, (add, x, offset2), y)). |
--- |
| 1193 |
|
--- |
1193 |
|
--- |
| 1194 |
if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD) |
1 |
1194 |
if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD) |
1 |
| 1195 |
return false; |
1 |
1195 |
return false; |
1 |
| 1196 |
|
--- |
1196 |
|
--- |
| 1197 |
auto *C2 = dyn_cast(N1); |
0 |
1197 |
auto *C2 = dyn_cast(N1); |
0 |
| 1198 |
if (!C2) |
0 |
1198 |
if (!C2) |
0 |
| 1199 |
return false; |
0 |
1199 |
return false; |
0 |
| 1200 |
|
--- |
1200 |
|
--- |
| 1201 |
const APInt &C2APIntVal = C2->getAPIntValue(); |
0 |
1201 |
const APInt &C2APIntVal = C2->getAPIntValue(); |
0 |
| 1202 |
if (C2APIntVal.getSignificantBits() > 64) |
0 |
1202 |
if (C2APIntVal.getSignificantBits() > 64) |
0 |
| 1203 |
return false; |
0 |
1203 |
return false; |
0 |
| 1204 |
|
--- |
1204 |
|
--- |
| 1205 |
if (auto *C1 = dyn_cast(N0.getOperand(1))) { |
0 |
1205 |
if (auto *C1 = dyn_cast(N0.getOperand(1))) { |
0 |
| 1206 |
if (N0.hasOneUse()) |
0 |
1206 |
if (N0.hasOneUse()) |
0 |
| 1207 |
return false; |
0 |
1207 |
return false; |
0 |
| 1208 |
|
--- |
1208 |
|
--- |
| 1209 |
const APInt &C1APIntVal = C1->getAPIntValue(); |
0 |
1209 |
const APInt &C1APIntVal = C1->getAPIntValue(); |
0 |
| 1210 |
const APInt CombinedValueIntVal = C1APIntVal + C2APIntVal; |
0 |
1210 |
const APInt CombinedValueIntVal = C1APIntVal + C2APIntVal; |
0 |
| 1211 |
if (CombinedValueIntVal.getSignificantBits() > 64) |
0 |
1211 |
if (CombinedValueIntVal.getSignificantBits() > 64) |
0 |
| 1212 |
return false; |
0 |
1212 |
return false; |
0 |
| 1213 |
const int64_t CombinedValue = CombinedValueIntVal.getSExtValue(); |
0 |
1213 |
const int64_t CombinedValue = CombinedValueIntVal.getSExtValue(); |
0 |
| 1214 |
|
--- |
1214 |
|
--- |
| 1215 |
for (SDNode *Node : N->uses()) { |
0 |
1215 |
for (SDNode *Node : N->uses()) { |
0 |
| 1216 |
if (auto *LoadStore = dyn_cast(Node)) { |
0 |
1216 |
if (auto *LoadStore = dyn_cast(Node)) { |
0 |
| 1217 |
// Is x[offset2] already not a legal addressing mode? If so then |
--- |
1217 |
// Is x[offset2] already not a legal addressing mode? If so then |
--- |
| 1218 |
// reassociating the constants breaks nothing (we test offset2 because |
--- |
1218 |
// reassociating the constants breaks nothing (we test offset2 because |
--- |
| 1219 |
// that's the one we hope to fold into the load or store). |
--- |
1219 |
// that's the one we hope to fold into the load or store). |
--- |
| 1220 |
TargetLoweringBase::AddrMode AM; |
0 |
1220 |
TargetLoweringBase::AddrMode AM; |
0 |
| 1221 |
AM.HasBaseReg = true; |
0 |
1221 |
AM.HasBaseReg = true; |
0 |
| 1222 |
AM.BaseOffs = C2APIntVal.getSExtValue(); |
0 |
1222 |
AM.BaseOffs = C2APIntVal.getSExtValue(); |
0 |
| 1223 |
EVT VT = LoadStore->getMemoryVT(); |
0 |
1223 |
EVT VT = LoadStore->getMemoryVT(); |
0 |
| 1224 |
unsigned AS = LoadStore->getAddressSpace(); |
0 |
1224 |
unsigned AS = LoadStore->getAddressSpace(); |
0 |
| 1225 |
Type *AccessTy = VT.getTypeForEVT(*DAG.getContext()); |
0 |
1225 |
Type *AccessTy = VT.getTypeForEVT(*DAG.getContext()); |
0 |
| 1226 |
if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS)) |
0 |
1226 |
if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS)) |
0 |
| 1227 |
continue; |
0 |
1227 |
continue; |
0 |
| 1228 |
|
--- |
1228 |
|
--- |
| 1229 |
// Would x[offset1+offset2] still be a legal addressing mode? |
--- |
1229 |
// Would x[offset1+offset2] still be a legal addressing mode? |
--- |
| 1230 |
AM.BaseOffs = CombinedValue; |
0 |
1230 |
AM.BaseOffs = CombinedValue; |
0 |
| 1231 |
if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS)) |
0 |
1231 |
if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS)) |
0 |
| 1232 |
return true; |
0 |
1232 |
return true; |
0 |
| 1233 |
} |
--- |
1233 |
} |
--- |
| 1234 |
} |
--- |
1234 |
} |
--- |
| 1235 |
} else { |
0 |
1235 |
} else { |
0 |
| 1236 |
if (auto *GA = dyn_cast(N0.getOperand(1))) |
0 |
1236 |
if (auto *GA = dyn_cast(N0.getOperand(1))) |
0 |
| 1237 |
if (GA->getOpcode() == ISD::GlobalAddress && TLI.isOffsetFoldingLegal(GA)) |
0 |
1237 |
if (GA->getOpcode() == ISD::GlobalAddress && TLI.isOffsetFoldingLegal(GA)) |
0 |
| 1238 |
return false; |
0 |
1238 |
return false; |
0 |
| 1239 |
|
--- |
1239 |
|
--- |
| 1240 |
for (SDNode *Node : N->uses()) { |
0 |
1240 |
for (SDNode *Node : N->uses()) { |
0 |
| 1241 |
auto *LoadStore = dyn_cast(Node); |
0 |
1241 |
auto *LoadStore = dyn_cast(Node); |
0 |
| 1242 |
if (!LoadStore) |
0 |
1242 |
if (!LoadStore) |
0 |
| 1243 |
return false; |
0 |
1243 |
return false; |
0 |
| 1244 |
|
--- |
1244 |
|
--- |
| 1245 |
// Is x[offset2] a legal addressing mode? If so then |
--- |
1245 |
// Is x[offset2] a legal addressing mode? If so then |
--- |
| 1246 |
// reassociating the constants breaks address pattern |
--- |
1246 |
// reassociating the constants breaks address pattern |
--- |
| 1247 |
TargetLoweringBase::AddrMode AM; |
0 |
1247 |
TargetLoweringBase::AddrMode AM; |
0 |
| 1248 |
AM.HasBaseReg = true; |
0 |
1248 |
AM.HasBaseReg = true; |
0 |
| 1249 |
AM.BaseOffs = C2APIntVal.getSExtValue(); |
0 |
1249 |
AM.BaseOffs = C2APIntVal.getSExtValue(); |
0 |
| 1250 |
EVT VT = LoadStore->getMemoryVT(); |
0 |
1250 |
EVT VT = LoadStore->getMemoryVT(); |
0 |
| 1251 |
unsigned AS = LoadStore->getAddressSpace(); |
0 |
1251 |
unsigned AS = LoadStore->getAddressSpace(); |
0 |
| 1252 |
Type *AccessTy = VT.getTypeForEVT(*DAG.getContext()); |
0 |
1252 |
Type *AccessTy = VT.getTypeForEVT(*DAG.getContext()); |
0 |
| 1253 |
if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS)) |
0 |
1253 |
if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS)) |
0 |
| 1254 |
return false; |
0 |
1254 |
return false; |
0 |
| 1255 |
} |
--- |
1255 |
} |
--- |
| 1256 |
return true; |
0 |
1256 |
return true; |
0 |
| 1257 |
} |
--- |
1257 |
} |
--- |
| 1258 |
|
--- |
1258 |
|
--- |
| 1259 |
return false; |
0 |
1259 |
return false; |
0 |
| 1260 |
} |
--- |
1260 |
} |
--- |
| 1261 |
|
--- |
1261 |
|
--- |
| 1262 |
// Helper for DAGCombiner::reassociateOps. Try to reassociate an expression |
--- |
1262 |
// Helper for DAGCombiner::reassociateOps. Try to reassociate an expression |
--- |
| 1263 |
// such as (Opc N0, N1), if \p N0 is the same kind of operation as \p Opc. |
--- |
1263 |
// such as (Opc N0, N1), if \p N0 is the same kind of operation as \p Opc. |
--- |
| 1264 |
SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, |
6 |
1264 |
SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, |
6 |
| 1265 |
SDValue N0, SDValue N1, |
--- |
1265 |
SDValue N0, SDValue N1, |
--- |
| 1266 |
SDNodeFlags Flags) { |
--- |
1266 |
SDNodeFlags Flags) { |
--- |
| 1267 |
EVT VT = N0.getValueType(); |
6 |
1267 |
EVT VT = N0.getValueType(); |
6 |
| 1268 |
|
--- |
1268 |
|
--- |
| 1269 |
if (N0.getOpcode() != Opc) |
6 |
1269 |
if (N0.getOpcode() != Opc) |
6 |
| 1270 |
return SDValue(); |
6 |
1270 |
return SDValue(); |
6 |
| 1271 |
|
--- |
1271 |
|
--- |
| 1272 |
SDValue N00 = N0.getOperand(0); |
0 |
1272 |
SDValue N00 = N0.getOperand(0); |
0 |
| 1273 |
SDValue N01 = N0.getOperand(1); |
0 |
1273 |
SDValue N01 = N0.getOperand(1); |
0 |
| 1274 |
|
--- |
1274 |
|
--- |
| 1275 |
if (DAG.isConstantIntBuildVectorOrConstantInt(peekThroughBitcasts(N01))) { |
0 |
1275 |
if (DAG.isConstantIntBuildVectorOrConstantInt(peekThroughBitcasts(N01))) { |
0 |
| 1276 |
if (DAG.isConstantIntBuildVectorOrConstantInt(peekThroughBitcasts(N1))) { |
0 |
1276 |
if (DAG.isConstantIntBuildVectorOrConstantInt(peekThroughBitcasts(N1))) { |
0 |
| 1277 |
// Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2)) |
--- |
1277 |
// Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2)) |
--- |
| 1278 |
if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, {N01, N1})) |
0 |
1278 |
if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, {N01, N1})) |
0 |
| 1279 |
return DAG.getNode(Opc, DL, VT, N00, OpNode); |
0 |
1279 |
return DAG.getNode(Opc, DL, VT, N00, OpNode); |
0 |
| 1280 |
return SDValue(); |
0 |
1280 |
return SDValue(); |
0 |
| 1281 |
} |
--- |
1281 |
} |
--- |
| 1282 |
if (TLI.isReassocProfitable(DAG, N0, N1)) { |
0 |
1282 |
if (TLI.isReassocProfitable(DAG, N0, N1)) { |
0 |
| 1283 |
// Reassociate: (op (op x, c1), y) -> (op (op x, y), c1) |
--- |
1283 |
// Reassociate: (op (op x, c1), y) -> (op (op x, y), c1) |
--- |
| 1284 |
// iff (op x, c1) has one use |
--- |
1284 |
// iff (op x, c1) has one use |
--- |
| 1285 |
SDNodeFlags NewFlags; |
0 |
1285 |
SDNodeFlags NewFlags; |
0 |
| 1286 |
if (N0.getOpcode() == ISD::ADD && N0->getFlags().hasNoUnsignedWrap() && |
0 |
1286 |
if (N0.getOpcode() == ISD::ADD && N0->getFlags().hasNoUnsignedWrap() && |
0 |
| 1287 |
Flags.hasNoUnsignedWrap()) |
0 |
1287 |
Flags.hasNoUnsignedWrap()) |
0 |
| 1288 |
NewFlags.setNoUnsignedWrap(true); |
0 |
1288 |
NewFlags.setNoUnsignedWrap(true); |
0 |
| 1289 |
SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, NewFlags); |
0 |
1289 |
SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, NewFlags); |
0 |
| 1290 |
return DAG.getNode(Opc, DL, VT, OpNode, N01, NewFlags); |
0 |
1290 |
return DAG.getNode(Opc, DL, VT, OpNode, N01, NewFlags); |
0 |
| 1291 |
} |
--- |
1291 |
} |
--- |
| 1292 |
} |
--- |
1292 |
} |
--- |
| 1293 |
|
--- |
1293 |
|
--- |
| 1294 |
// Check for repeated operand logic simplifications. |
--- |
1294 |
// Check for repeated operand logic simplifications. |
--- |
| 1295 |
if (Opc == ISD::AND || Opc == ISD::OR) { |
0 |
1295 |
if (Opc == ISD::AND || Opc == ISD::OR) { |
0 |
| 1296 |
// (N00 & N01) & N00 --> N00 & N01 |
--- |
1296 |
// (N00 & N01) & N00 --> N00 & N01 |
--- |
| 1297 |
// (N00 & N01) & N01 --> N00 & N01 |
--- |
1297 |
// (N00 & N01) & N01 --> N00 & N01 |
--- |
| 1298 |
// (N00 | N01) | N00 --> N00 | N01 |
--- |
1298 |
// (N00 | N01) | N00 --> N00 | N01 |
--- |
| 1299 |
// (N00 | N01) | N01 --> N00 | N01 |
--- |
1299 |
// (N00 | N01) | N01 --> N00 | N01 |
--- |
| 1300 |
if (N1 == N00 || N1 == N01) |
0 |
1300 |
if (N1 == N00 || N1 == N01) |
0 |
| 1301 |
return N0; |
0 |
1301 |
return N0; |
0 |
| 1302 |
} |
--- |
1302 |
} |
--- |
| 1303 |
if (Opc == ISD::XOR) { |
0 |
1303 |
if (Opc == ISD::XOR) { |
0 |
| 1304 |
// (N00 ^ N01) ^ N00 --> N01 |
--- |
1304 |
// (N00 ^ N01) ^ N00 --> N01 |
--- |
| 1305 |
if (N1 == N00) |
0 |
1305 |
if (N1 == N00) |
0 |
| 1306 |
return N01; |
0 |
1306 |
return N01; |
0 |
| 1307 |
// (N00 ^ N01) ^ N01 --> N00 |
--- |
1307 |
// (N00 ^ N01) ^ N01 --> N00 |
--- |
| 1308 |
if (N1 == N01) |
0 |
1308 |
if (N1 == N01) |
0 |
| 1309 |
return N00; |
0 |
1309 |
return N00; |
0 |
| 1310 |
} |
--- |
1310 |
} |
--- |
| 1311 |
|
--- |
1311 |
|
--- |
| 1312 |
if (TLI.isReassocProfitable(DAG, N0, N1)) { |
0 |
1312 |
if (TLI.isReassocProfitable(DAG, N0, N1)) { |
0 |
| 1313 |
if (N1 != N01) { |
0 |
1313 |
if (N1 != N01) { |
0 |
| 1314 |
// Reassociate if (op N00, N1) already exist |
--- |
1314 |
// Reassociate if (op N00, N1) already exist |
--- |
| 1315 |
if (SDNode *NE = DAG.getNodeIfExists(Opc, DAG.getVTList(VT), {N00, N1})) { |
0 |
1315 |
if (SDNode *NE = DAG.getNodeIfExists(Opc, DAG.getVTList(VT), {N00, N1})) { |
0 |
| 1316 |
// if Op (Op N00, N1), N01 already exist |
--- |
1316 |
// if Op (Op N00, N1), N01 already exist |
--- |
| 1317 |
// we need to stop reassciate to avoid dead loop |
--- |
1317 |
// we need to stop reassciate to avoid dead loop |
--- |
| 1318 |
if (!DAG.doesNodeExist(Opc, DAG.getVTList(VT), {SDValue(NE, 0), N01})) |
0 |
1318 |
if (!DAG.doesNodeExist(Opc, DAG.getVTList(VT), {SDValue(NE, 0), N01})) |
0 |
| 1319 |
return DAG.getNode(Opc, DL, VT, SDValue(NE, 0), N01); |
0 |
1319 |
return DAG.getNode(Opc, DL, VT, SDValue(NE, 0), N01); |
0 |
| 1320 |
} |
--- |
1320 |
} |
--- |
| 1321 |
} |
--- |
1321 |
} |
--- |
| 1322 |
|
--- |
1322 |
|
--- |
| 1323 |
if (N1 != N00) { |
0 |
1323 |
if (N1 != N00) { |
0 |
| 1324 |
// Reassociate if (op N01, N1) already exist |
--- |
1324 |
// Reassociate if (op N01, N1) already exist |
--- |
| 1325 |
if (SDNode *NE = DAG.getNodeIfExists(Opc, DAG.getVTList(VT), {N01, N1})) { |
0 |
1325 |
if (SDNode *NE = DAG.getNodeIfExists(Opc, DAG.getVTList(VT), {N01, N1})) { |
0 |
| 1326 |
// if Op (Op N01, N1), N00 already exist |
--- |
1326 |
// if Op (Op N01, N1), N00 already exist |
--- |
| 1327 |
// we need to stop reassciate to avoid dead loop |
--- |
1327 |
// we need to stop reassciate to avoid dead loop |
--- |
| 1328 |
if (!DAG.doesNodeExist(Opc, DAG.getVTList(VT), {SDValue(NE, 0), N00})) |
0 |
1328 |
if (!DAG.doesNodeExist(Opc, DAG.getVTList(VT), {SDValue(NE, 0), N00})) |
0 |
| 1329 |
return DAG.getNode(Opc, DL, VT, SDValue(NE, 0), N00); |
0 |
1329 |
return DAG.getNode(Opc, DL, VT, SDValue(NE, 0), N00); |
0 |
| 1330 |
} |
--- |
1330 |
} |
--- |
| 1331 |
} |
--- |
1331 |
} |
--- |
| 1332 |
} |
--- |
1332 |
} |
--- |
| 1333 |
|
--- |
1333 |
|
--- |
| 1334 |
return SDValue(); |
0 |
1334 |
return SDValue(); |
0 |
| 1335 |
} |
--- |
1335 |
} |
--- |
| 1336 |
|
--- |
1336 |
|
--- |
| 1337 |
// Try to reassociate commutative binops. |
--- |
1337 |
// Try to reassociate commutative binops. |
--- |
| 1338 |
SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0, |
3 |
1338 |
SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0, |
3 |
| 1339 |
SDValue N1, SDNodeFlags Flags) { |
--- |
1339 |
SDValue N1, SDNodeFlags Flags) { |
--- |
| 1340 |
assert(TLI.isCommutativeBinOp(Opc) && "Operation not commutative."); |
3 |
1340 |
assert(TLI.isCommutativeBinOp(Opc) && "Operation not commutative."); |
3 |
| 1341 |
|
--- |
1341 |
|
--- |
| 1342 |
// Floating-point reassociation is not allowed without loose FP math. |
--- |
1342 |
// Floating-point reassociation is not allowed without loose FP math. |
--- |
| 1343 |
if (N0.getValueType().isFloatingPoint() || |
6 |
1343 |
if (N0.getValueType().isFloatingPoint() || |
6 |
| 1344 |
N1.getValueType().isFloatingPoint()) |
6 |
1344 |
N1.getValueType().isFloatingPoint()) |
6 |
| 1345 |
if (!Flags.hasAllowReassociation() || !Flags.hasNoSignedZeros()) |
0 |
1345 |
if (!Flags.hasAllowReassociation() || !Flags.hasNoSignedZeros()) |
0 |
| 1346 |
return SDValue(); |
0 |
1346 |
return SDValue(); |
0 |
| 1347 |
|
--- |
1347 |
|
--- |
| 1348 |
if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N0, N1, Flags)) |
3 |
1348 |
if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N0, N1, Flags)) |
3 |
| 1349 |
return Combined; |
0 |
1349 |
return Combined; |
0 |
| 1350 |
if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N1, N0, Flags)) |
3 |
1350 |
if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N1, N0, Flags)) |
3 |
| 1351 |
return Combined; |
0 |
1351 |
return Combined; |
0 |
| 1352 |
return SDValue(); |
3 |
1352 |
return SDValue(); |
3 |
| 1353 |
} |
--- |
1353 |
} |
--- |
| 1354 |
|
--- |
1354 |
|
--- |
| 1355 |
// Try to fold Opc(vecreduce(x), vecreduce(y)) -> vecreduce(Opc(x, y)) |
--- |
1355 |
// Try to fold Opc(vecreduce(x), vecreduce(y)) -> vecreduce(Opc(x, y)) |
--- |
| 1356 |
// Note that we only expect Flags to be passed from FP operations. For integer |
--- |
1356 |
// Note that we only expect Flags to be passed from FP operations. For integer |
--- |
| 1357 |
// operations they need to be dropped. |
--- |
1357 |
// operations they need to be dropped. |
--- |
| 1358 |
SDValue DAGCombiner::reassociateReduction(unsigned RedOpc, unsigned Opc, |
3 |
1358 |
SDValue DAGCombiner::reassociateReduction(unsigned RedOpc, unsigned Opc, |
3 |
| 1359 |
const SDLoc &DL, EVT VT, SDValue N0, |
--- |
1359 |
const SDLoc &DL, EVT VT, SDValue N0, |
--- |
| 1360 |
SDValue N1, SDNodeFlags Flags) { |
--- |
1360 |
SDValue N1, SDNodeFlags Flags) { |
--- |
| 1361 |
if (N0.getOpcode() == RedOpc && N1.getOpcode() == RedOpc && |
3 |
1361 |
if (N0.getOpcode() == RedOpc && N1.getOpcode() == RedOpc && |
3 |
| 1362 |
N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() && |
0 |
1362 |
N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() && |
0 |
| 1363 |
N0->hasOneUse() && N1->hasOneUse() && |
0 |
1363 |
N0->hasOneUse() && N1->hasOneUse() && |
0 |
| 1364 |
TLI.isOperationLegalOrCustom(Opc, N0.getOperand(0).getValueType()) && |
3 |
1364 |
TLI.isOperationLegalOrCustom(Opc, N0.getOperand(0).getValueType()) && |
3 |
| 1365 |
TLI.shouldReassociateReduction(RedOpc, N0.getOperand(0).getValueType())) { |
0 |
1365 |
TLI.shouldReassociateReduction(RedOpc, N0.getOperand(0).getValueType())) { |
0 |
| 1366 |
SelectionDAG::FlagInserter FlagsInserter(DAG, Flags); |
0 |
1366 |
SelectionDAG::FlagInserter FlagsInserter(DAG, Flags); |
0 |
| 1367 |
return DAG.getNode(RedOpc, DL, VT, |
0 |
1367 |
return DAG.getNode(RedOpc, DL, VT, |
0 |
| 1368 |
DAG.getNode(Opc, DL, N0.getOperand(0).getValueType(), |
0 |
1368 |
DAG.getNode(Opc, DL, N0.getOperand(0).getValueType(), |
0 |
| 1369 |
N0.getOperand(0), N1.getOperand(0))); |
0 |
1369 |
N0.getOperand(0), N1.getOperand(0))); |
0 |
| 1370 |
} |
0 |
1370 |
} |
0 |
| 1371 |
return SDValue(); |
3 |
1371 |
return SDValue(); |
3 |
| 1372 |
} |
--- |
1372 |
} |
--- |
| 1373 |
|
--- |
1373 |
|
--- |
| 1374 |
SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, |
0 |
1374 |
SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, |
0 |
| 1375 |
bool AddTo) { |
--- |
1375 |
bool AddTo) { |
--- |
| 1376 |
assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); |
0 |
1376 |
assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); |
0 |
| 1377 |
++NodesCombined; |
0 |
1377 |
++NodesCombined; |
0 |
| 1378 |
LLVM_DEBUG(dbgs() << "\nReplacing.1 "; N->dump(&DAG); dbgs() << "\nWith: "; |
0 |
1378 |
LLVM_DEBUG(dbgs() << "\nReplacing.1 "; N->dump(&DAG); dbgs() << "\nWith: "; |
0 |
| 1379 |
To[0].dump(&DAG); |
--- |
1379 |
To[0].dump(&DAG); |
--- |
| 1380 |
dbgs() << " and " << NumTo - 1 << " other values\n"); |
--- |
1380 |
dbgs() << " and " << NumTo - 1 << " other values\n"); |
--- |
| 1381 |
for (unsigned i = 0, e = NumTo; i != e; ++i) |
0 |
1381 |
for (unsigned i = 0, e = NumTo; i != e; ++i) |
0 |
| 1382 |
assert((!To[i].getNode() || |
0 |
1382 |
assert((!To[i].getNode() || |
0 |
| 1383 |
N->getValueType(i) == To[i].getValueType()) && |
--- |
1383 |
N->getValueType(i) == To[i].getValueType()) && |
--- |
| 1384 |
"Cannot combine value to value of different type!"); |
--- |
1384 |
"Cannot combine value to value of different type!"); |
--- |
| 1385 |
|
--- |
1385 |
|
--- |
| 1386 |
WorklistRemover DeadNodes(*this); |
0 |
1386 |
WorklistRemover DeadNodes(*this); |
0 |
| 1387 |
DAG.ReplaceAllUsesWith(N, To); |
0 |
1387 |
DAG.ReplaceAllUsesWith(N, To); |
0 |
| 1388 |
if (AddTo) { |
0 |
1388 |
if (AddTo) { |
0 |
| 1389 |
// Push the new nodes and any users onto the worklist |
--- |
1389 |
// Push the new nodes and any users onto the worklist |
--- |
| 1390 |
for (unsigned i = 0, e = NumTo; i != e; ++i) { |
0 |
1390 |
for (unsigned i = 0, e = NumTo; i != e; ++i) { |
0 |
| 1391 |
if (To[i].getNode()) |
0 |
1391 |
if (To[i].getNode()) |
0 |
| 1392 |
AddToWorklistWithUsers(To[i].getNode()); |
0 |
1392 |
AddToWorklistWithUsers(To[i].getNode()); |
0 |
| 1393 |
} |
--- |
1393 |
} |
--- |
| 1394 |
} |
--- |
1394 |
} |
--- |
| 1395 |
|
--- |
1395 |
|
--- |
| 1396 |
// Finally, if the node is now dead, remove it from the graph. The node |
--- |
1396 |
// Finally, if the node is now dead, remove it from the graph. The node |
--- |
| 1397 |
// may not be dead if the replacement process recursively simplified to |
--- |
1397 |
// may not be dead if the replacement process recursively simplified to |
--- |
| 1398 |
// something else needing this node. |
--- |
1398 |
// something else needing this node. |
--- |
| 1399 |
if (N->use_empty()) |
0 |
1399 |
if (N->use_empty()) |
0 |
| 1400 |
deleteAndRecombine(N); |
0 |
1400 |
deleteAndRecombine(N); |
0 |
| 1401 |
return SDValue(N, 0); |
0 |
1401 |
return SDValue(N, 0); |
0 |
| 1402 |
} |
0 |
1402 |
} |
0 |
| 1403 |
|
--- |
1403 |
|
--- |
| 1404 |
void DAGCombiner:: |
1 |
1404 |
void DAGCombiner:: |
1 |
| 1405 |
CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { |
--- |
1405 |
CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { |
--- |
| 1406 |
// Replace the old value with the new one. |
--- |
1406 |
// Replace the old value with the new one. |
--- |
| 1407 |
++NodesCombined; |
1 |
1407 |
++NodesCombined; |
1 |
| 1408 |
LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.dump(&DAG); |
1 |
1408 |
LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.dump(&DAG); |
1 |
| 1409 |
dbgs() << "\nWith: "; TLO.New.dump(&DAG); dbgs() << '\n'); |
--- |
1409 |
dbgs() << "\nWith: "; TLO.New.dump(&DAG); dbgs() << '\n'); |
--- |
| 1410 |
|
--- |
1410 |
|
--- |
| 1411 |
// Replace all uses. |
--- |
1411 |
// Replace all uses. |
--- |
| 1412 |
DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); |
1 |
1412 |
DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); |
1 |
| 1413 |
|
--- |
1413 |
|
--- |
| 1414 |
// Push the new node and any (possibly new) users onto the worklist. |
--- |
1414 |
// Push the new node and any (possibly new) users onto the worklist. |
--- |
| 1415 |
AddToWorklistWithUsers(TLO.New.getNode()); |
1 |
1415 |
AddToWorklistWithUsers(TLO.New.getNode()); |
1 |
| 1416 |
|
--- |
1416 |
|
--- |
| 1417 |
// Finally, if the node is now dead, remove it from the graph. |
--- |
1417 |
// Finally, if the node is now dead, remove it from the graph. |
--- |
| 1418 |
recursivelyDeleteUnusedNodes(TLO.Old.getNode()); |
1 |
1418 |
recursivelyDeleteUnusedNodes(TLO.Old.getNode()); |
1 |
| 1419 |
} |
1 |
1419 |
} |
1 |
| 1420 |
|
--- |
1420 |
|
--- |
| 1421 |
/// Check the specified integer node value to see if it can be simplified or if |
--- |
1421 |
/// Check the specified integer node value to see if it can be simplified or if |
--- |
| 1422 |
/// things it uses can be simplified by bit propagation. If so, return true. |
--- |
1422 |
/// things it uses can be simplified by bit propagation. If so, return true. |
--- |
| 1423 |
bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, |
0 |
1423 |
bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, |
0 |
| 1424 |
const APInt &DemandedElts, |
--- |
1424 |
const APInt &DemandedElts, |
--- |
| 1425 |
bool AssumeSingleUse) { |
--- |
1425 |
bool AssumeSingleUse) { |
--- |
| 1426 |
TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); |
0 |
1426 |
TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); |
0 |
| 1427 |
KnownBits Known; |
0 |
1427 |
KnownBits Known; |
0 |
| 1428 |
if (!TLI.SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, 0, |
0 |
1428 |
if (!TLI.SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, 0, |
0 |
| 1429 |
AssumeSingleUse)) |
--- |
1429 |
AssumeSingleUse)) |
--- |
| 1430 |
return false; |
0 |
1430 |
return false; |
0 |
| 1431 |
|
--- |
1431 |
|
--- |
| 1432 |
// Revisit the node. |
--- |
1432 |
// Revisit the node. |
--- |
| 1433 |
AddToWorklist(Op.getNode()); |
0 |
1433 |
AddToWorklist(Op.getNode()); |
0 |
| 1434 |
|
--- |
1434 |
|
--- |
| 1435 |
CommitTargetLoweringOpt(TLO); |
0 |
1435 |
CommitTargetLoweringOpt(TLO); |
0 |
| 1436 |
return true; |
0 |
1436 |
return true; |
0 |
| 1437 |
} |
0 |
1437 |
} |
0 |
| 1438 |
|
--- |
1438 |
|
--- |
| 1439 |
/// Check the specified vector node value to see if it can be simplified or |
--- |
1439 |
/// Check the specified vector node value to see if it can be simplified or |
--- |
| 1440 |
/// if things it uses can be simplified as it only uses some of the elements. |
--- |
1440 |
/// if things it uses can be simplified as it only uses some of the elements. |
--- |
| 1441 |
/// If so, return true. |
--- |
1441 |
/// If so, return true. |
--- |
| 1442 |
bool DAGCombiner::SimplifyDemandedVectorElts(SDValue Op, |
0 |
1442 |
bool DAGCombiner::SimplifyDemandedVectorElts(SDValue Op, |
0 |
| 1443 |
const APInt &DemandedElts, |
--- |
1443 |
const APInt &DemandedElts, |
--- |
| 1444 |
bool AssumeSingleUse) { |
--- |
1444 |
bool AssumeSingleUse) { |
--- |
| 1445 |
TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); |
0 |
1445 |
TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); |
0 |
| 1446 |
APInt KnownUndef, KnownZero; |
0 |
1446 |
APInt KnownUndef, KnownZero; |
0 |
| 1447 |
if (!TLI.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, |
0 |
1447 |
if (!TLI.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, |
0 |
| 1448 |
TLO, 0, AssumeSingleUse)) |
--- |
1448 |
TLO, 0, AssumeSingleUse)) |
--- |
| 1449 |
return false; |
0 |
1449 |
return false; |
0 |
| 1450 |
|
--- |
1450 |
|
--- |
| 1451 |
// Revisit the node. |
--- |
1451 |
// Revisit the node. |
--- |
| 1452 |
AddToWorklist(Op.getNode()); |
0 |
1452 |
AddToWorklist(Op.getNode()); |
0 |
| 1453 |
|
--- |
1453 |
|
--- |
| 1454 |
CommitTargetLoweringOpt(TLO); |
0 |
1454 |
CommitTargetLoweringOpt(TLO); |
0 |
| 1455 |
return true; |
0 |
1455 |
return true; |
0 |
| 1456 |
} |
0 |
1456 |
} |
0 |
| 1457 |
|
--- |
1457 |
|
--- |
| 1458 |
void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { |
0 |
1458 |
void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { |
0 |
| 1459 |
SDLoc DL(Load); |
0 |
1459 |
SDLoc DL(Load); |
0 |
| 1460 |
EVT VT = Load->getValueType(0); |
0 |
1460 |
EVT VT = Load->getValueType(0); |
0 |
| 1461 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0)); |
0 |
1461 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0)); |
0 |
| 1462 |
|
--- |
1462 |
|
--- |
| 1463 |
LLVM_DEBUG(dbgs() << "\nReplacing.9 "; Load->dump(&DAG); dbgs() << "\nWith: "; |
0 |
1463 |
LLVM_DEBUG(dbgs() << "\nReplacing.9 "; Load->dump(&DAG); dbgs() << "\nWith: "; |
0 |
| 1464 |
Trunc.dump(&DAG); dbgs() << '\n'); |
--- |
1464 |
Trunc.dump(&DAG); dbgs() << '\n'); |
--- |
| 1465 |
|
--- |
1465 |
|
--- |
| 1466 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); |
0 |
1466 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); |
0 |
| 1467 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); |
0 |
1467 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); |
0 |
| 1468 |
|
--- |
1468 |
|
--- |
| 1469 |
AddToWorklist(Trunc.getNode()); |
0 |
1469 |
AddToWorklist(Trunc.getNode()); |
0 |
| 1470 |
recursivelyDeleteUnusedNodes(Load); |
0 |
1470 |
recursivelyDeleteUnusedNodes(Load); |
0 |
| 1471 |
} |
0 |
1471 |
} |
0 |
| 1472 |
|
--- |
1472 |
|
--- |
| 1473 |
SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { |
0 |
1473 |
SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { |
0 |
| 1474 |
Replace = false; |
0 |
1474 |
Replace = false; |
0 |
| 1475 |
SDLoc DL(Op); |
0 |
1475 |
SDLoc DL(Op); |
0 |
| 1476 |
if (ISD::isUNINDEXEDLoad(Op.getNode())) { |
0 |
1476 |
if (ISD::isUNINDEXEDLoad(Op.getNode())) { |
0 |
| 1477 |
LoadSDNode *LD = cast(Op); |
0 |
1477 |
LoadSDNode *LD = cast(Op); |
0 |
| 1478 |
EVT MemVT = LD->getMemoryVT(); |
0 |
1478 |
EVT MemVT = LD->getMemoryVT(); |
0 |
| 1479 |
ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD |
0 |
1479 |
ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD |
0 |
| 1480 |
: LD->getExtensionType(); |
0 |
1480 |
: LD->getExtensionType(); |
0 |
| 1481 |
Replace = true; |
0 |
1481 |
Replace = true; |
0 |
| 1482 |
return DAG.getExtLoad(ExtType, DL, PVT, |
0 |
1482 |
return DAG.getExtLoad(ExtType, DL, PVT, |
0 |
| 1483 |
LD->getChain(), LD->getBasePtr(), |
0 |
1483 |
LD->getChain(), LD->getBasePtr(), |
0 |
| 1484 |
MemVT, LD->getMemOperand()); |
0 |
1484 |
MemVT, LD->getMemOperand()); |
0 |
| 1485 |
} |
--- |
1485 |
} |
--- |
| 1486 |
|
--- |
1486 |
|
--- |
| 1487 |
unsigned Opc = Op.getOpcode(); |
0 |
1487 |
unsigned Opc = Op.getOpcode(); |
0 |
| 1488 |
switch (Opc) { |
0 |
1488 |
switch (Opc) { |
0 |
| 1489 |
default: break; |
0 |
1489 |
default: break; |
0 |
| 1490 |
case ISD::AssertSext: |
0 |
1490 |
case ISD::AssertSext: |
0 |
| 1491 |
if (SDValue Op0 = SExtPromoteOperand(Op.getOperand(0), PVT)) |
0 |
1491 |
if (SDValue Op0 = SExtPromoteOperand(Op.getOperand(0), PVT)) |
0 |
| 1492 |
return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1)); |
0 |
1492 |
return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1)); |
0 |
| 1493 |
break; |
0 |
1493 |
break; |
0 |
| 1494 |
case ISD::AssertZext: |
0 |
1494 |
case ISD::AssertZext: |
0 |
| 1495 |
if (SDValue Op0 = ZExtPromoteOperand(Op.getOperand(0), PVT)) |
0 |
1495 |
if (SDValue Op0 = ZExtPromoteOperand(Op.getOperand(0), PVT)) |
0 |
| 1496 |
return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1)); |
0 |
1496 |
return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1)); |
0 |
| 1497 |
break; |
0 |
1497 |
break; |
0 |
| 1498 |
case ISD::Constant: { |
0 |
1498 |
case ISD::Constant: { |
0 |
| 1499 |
unsigned ExtOpc = |
--- |
1499 |
unsigned ExtOpc = |
--- |
| 1500 |
Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; |
0 |
1500 |
Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; |
0 |
| 1501 |
return DAG.getNode(ExtOpc, DL, PVT, Op); |
0 |
1501 |
return DAG.getNode(ExtOpc, DL, PVT, Op); |
0 |
| 1502 |
} |
--- |
1502 |
} |
--- |
| 1503 |
} |
--- |
1503 |
} |
--- |
| 1504 |
|
--- |
1504 |
|
--- |
| 1505 |
if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) |
0 |
1505 |
if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) |
0 |
| 1506 |
return SDValue(); |
0 |
1506 |
return SDValue(); |
0 |
| 1507 |
return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op); |
0 |
1507 |
return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op); |
0 |
| 1508 |
} |
0 |
1508 |
} |
0 |
| 1509 |
|
--- |
1509 |
|
--- |
| 1510 |
SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { |
0 |
1510 |
SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { |
0 |
| 1511 |
if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) |
0 |
1511 |
if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) |
0 |
| 1512 |
return SDValue(); |
0 |
1512 |
return SDValue(); |
0 |
| 1513 |
EVT OldVT = Op.getValueType(); |
0 |
1513 |
EVT OldVT = Op.getValueType(); |
0 |
| 1514 |
SDLoc DL(Op); |
0 |
1514 |
SDLoc DL(Op); |
0 |
| 1515 |
bool Replace = false; |
0 |
1515 |
bool Replace = false; |
0 |
| 1516 |
SDValue NewOp = PromoteOperand(Op, PVT, Replace); |
0 |
1516 |
SDValue NewOp = PromoteOperand(Op, PVT, Replace); |
0 |
| 1517 |
if (!NewOp.getNode()) |
0 |
1517 |
if (!NewOp.getNode()) |
0 |
| 1518 |
return SDValue(); |
0 |
1518 |
return SDValue(); |
0 |
| 1519 |
AddToWorklist(NewOp.getNode()); |
0 |
1519 |
AddToWorklist(NewOp.getNode()); |
0 |
| 1520 |
|
--- |
1520 |
|
--- |
| 1521 |
if (Replace) |
0 |
1521 |
if (Replace) |
0 |
| 1522 |
ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); |
0 |
1522 |
ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); |
0 |
| 1523 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp, |
0 |
1523 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp, |
0 |
| 1524 |
DAG.getValueType(OldVT)); |
0 |
1524 |
DAG.getValueType(OldVT)); |
0 |
| 1525 |
} |
0 |
1525 |
} |
0 |
| 1526 |
|
--- |
1526 |
|
--- |
| 1527 |
SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { |
0 |
1527 |
SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { |
0 |
| 1528 |
EVT OldVT = Op.getValueType(); |
0 |
1528 |
EVT OldVT = Op.getValueType(); |
0 |
| 1529 |
SDLoc DL(Op); |
0 |
1529 |
SDLoc DL(Op); |
0 |
| 1530 |
bool Replace = false; |
0 |
1530 |
bool Replace = false; |
0 |
| 1531 |
SDValue NewOp = PromoteOperand(Op, PVT, Replace); |
0 |
1531 |
SDValue NewOp = PromoteOperand(Op, PVT, Replace); |
0 |
| 1532 |
if (!NewOp.getNode()) |
0 |
1532 |
if (!NewOp.getNode()) |
0 |
| 1533 |
return SDValue(); |
0 |
1533 |
return SDValue(); |
0 |
| 1534 |
AddToWorklist(NewOp.getNode()); |
0 |
1534 |
AddToWorklist(NewOp.getNode()); |
0 |
| 1535 |
|
--- |
1535 |
|
--- |
| 1536 |
if (Replace) |
0 |
1536 |
if (Replace) |
0 |
| 1537 |
ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); |
0 |
1537 |
ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); |
0 |
| 1538 |
return DAG.getZeroExtendInReg(NewOp, DL, OldVT); |
0 |
1538 |
return DAG.getZeroExtendInReg(NewOp, DL, OldVT); |
0 |
| 1539 |
} |
0 |
1539 |
} |
0 |
| 1540 |
|
--- |
1540 |
|
--- |
| 1541 |
/// Promote the specified integer binary operation if the target indicates it is |
--- |
1541 |
/// Promote the specified integer binary operation if the target indicates it is |
--- |
| 1542 |
/// beneficial. e.g. On x86, it's usually better to promote i16 operations to |
--- |
1542 |
/// beneficial. e.g. On x86, it's usually better to promote i16 operations to |
--- |
| 1543 |
/// i32 since i16 instructions are longer. |
--- |
1543 |
/// i32 since i16 instructions are longer. |
--- |
| 1544 |
SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { |
0 |
1544 |
SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { |
0 |
| 1545 |
if (!LegalOperations) |
0 |
1545 |
if (!LegalOperations) |
0 |
| 1546 |
return SDValue(); |
0 |
1546 |
return SDValue(); |
0 |
| 1547 |
|
--- |
1547 |
|
--- |
| 1548 |
EVT VT = Op.getValueType(); |
0 |
1548 |
EVT VT = Op.getValueType(); |
0 |
| 1549 |
if (VT.isVector() || !VT.isInteger()) |
0 |
1549 |
if (VT.isVector() || !VT.isInteger()) |
0 |
| 1550 |
return SDValue(); |
0 |
1550 |
return SDValue(); |
0 |
| 1551 |
|
--- |
1551 |
|
--- |
| 1552 |
// If operation type is 'undesirable', e.g. i16 on x86, consider |
--- |
1552 |
// If operation type is 'undesirable', e.g. i16 on x86, consider |
--- |
| 1553 |
// promoting it. |
--- |
1553 |
// promoting it. |
--- |
| 1554 |
unsigned Opc = Op.getOpcode(); |
0 |
1554 |
unsigned Opc = Op.getOpcode(); |
0 |
| 1555 |
if (TLI.isTypeDesirableForOp(Opc, VT)) |
0 |
1555 |
if (TLI.isTypeDesirableForOp(Opc, VT)) |
0 |
| 1556 |
return SDValue(); |
0 |
1556 |
return SDValue(); |
0 |
| 1557 |
|
--- |
1557 |
|
--- |
| 1558 |
EVT PVT = VT; |
0 |
1558 |
EVT PVT = VT; |
0 |
| 1559 |
// Consult target whether it is a good idea to promote this operation and |
--- |
1559 |
// Consult target whether it is a good idea to promote this operation and |
--- |
| 1560 |
// what's the right type to promote it to. |
--- |
1560 |
// what's the right type to promote it to. |
--- |
| 1561 |
if (TLI.IsDesirableToPromoteOp(Op, PVT)) { |
0 |
1561 |
if (TLI.IsDesirableToPromoteOp(Op, PVT)) { |
0 |
| 1562 |
assert(PVT != VT && "Don't know what type to promote to!"); |
0 |
1562 |
assert(PVT != VT && "Don't know what type to promote to!"); |
0 |
| 1563 |
|
--- |
1563 |
|
--- |
| 1564 |
LLVM_DEBUG(dbgs() << "\nPromoting "; Op.dump(&DAG)); |
0 |
1564 |
LLVM_DEBUG(dbgs() << "\nPromoting "; Op.dump(&DAG)); |
0 |
| 1565 |
|
--- |
1565 |
|
--- |
| 1566 |
bool Replace0 = false; |
0 |
1566 |
bool Replace0 = false; |
0 |
| 1567 |
SDValue N0 = Op.getOperand(0); |
0 |
1567 |
SDValue N0 = Op.getOperand(0); |
0 |
| 1568 |
SDValue NN0 = PromoteOperand(N0, PVT, Replace0); |
0 |
1568 |
SDValue NN0 = PromoteOperand(N0, PVT, Replace0); |
0 |
| 1569 |
|
--- |
1569 |
|
--- |
| 1570 |
bool Replace1 = false; |
0 |
1570 |
bool Replace1 = false; |
0 |
| 1571 |
SDValue N1 = Op.getOperand(1); |
0 |
1571 |
SDValue N1 = Op.getOperand(1); |
0 |
| 1572 |
SDValue NN1 = PromoteOperand(N1, PVT, Replace1); |
0 |
1572 |
SDValue NN1 = PromoteOperand(N1, PVT, Replace1); |
0 |
| 1573 |
SDLoc DL(Op); |
0 |
1573 |
SDLoc DL(Op); |
0 |
| 1574 |
|
--- |
1574 |
|
--- |
| 1575 |
SDValue RV = |
--- |
1575 |
SDValue RV = |
--- |
| 1576 |
DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1)); |
0 |
1576 |
DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1)); |
0 |
| 1577 |
|
--- |
1577 |
|
--- |
| 1578 |
// We are always replacing N0/N1's use in N and only need additional |
--- |
1578 |
// We are always replacing N0/N1's use in N and only need additional |
--- |
| 1579 |
// replacements if there are additional uses. |
--- |
1579 |
// replacements if there are additional uses. |
--- |
| 1580 |
// Note: We are checking uses of the *nodes* (SDNode) rather than values |
--- |
1580 |
// Note: We are checking uses of the *nodes* (SDNode) rather than values |
--- |
| 1581 |
// (SDValue) here because the node may reference multiple values |
--- |
1581 |
// (SDValue) here because the node may reference multiple values |
--- |
| 1582 |
// (for example, the chain value of a load node). |
--- |
1582 |
// (for example, the chain value of a load node). |
--- |
| 1583 |
Replace0 &= !N0->hasOneUse(); |
0 |
1583 |
Replace0 &= !N0->hasOneUse(); |
0 |
| 1584 |
Replace1 &= (N0 != N1) && !N1->hasOneUse(); |
0 |
1584 |
Replace1 &= (N0 != N1) && !N1->hasOneUse(); |
0 |
| 1585 |
|
--- |
1585 |
|
--- |
| 1586 |
// Combine Op here so it is preserved past replacements. |
--- |
1586 |
// Combine Op here so it is preserved past replacements. |
--- |
| 1587 |
CombineTo(Op.getNode(), RV); |
0 |
1587 |
CombineTo(Op.getNode(), RV); |
0 |
| 1588 |
|
--- |
1588 |
|
--- |
| 1589 |
// If operands have a use ordering, make sure we deal with |
--- |
1589 |
// If operands have a use ordering, make sure we deal with |
--- |
| 1590 |
// predecessor first. |
--- |
1590 |
// predecessor first. |
--- |
| 1591 |
if (Replace0 && Replace1 && N0->isPredecessorOf(N1.getNode())) { |
0 |
1591 |
if (Replace0 && Replace1 && N0->isPredecessorOf(N1.getNode())) { |
0 |
| 1592 |
std::swap(N0, N1); |
0 |
1592 |
std::swap(N0, N1); |
0 |
| 1593 |
std::swap(NN0, NN1); |
0 |
1593 |
std::swap(NN0, NN1); |
0 |
| 1594 |
} |
--- |
1594 |
} |
--- |
| 1595 |
|
--- |
1595 |
|
--- |
| 1596 |
if (Replace0) { |
0 |
1596 |
if (Replace0) { |
0 |
| 1597 |
AddToWorklist(NN0.getNode()); |
0 |
1597 |
AddToWorklist(NN0.getNode()); |
0 |
| 1598 |
ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); |
0 |
1598 |
ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); |
0 |
| 1599 |
} |
--- |
1599 |
} |
--- |
| 1600 |
if (Replace1) { |
0 |
1600 |
if (Replace1) { |
0 |
| 1601 |
AddToWorklist(NN1.getNode()); |
0 |
1601 |
AddToWorklist(NN1.getNode()); |
0 |
| 1602 |
ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); |
0 |
1602 |
ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); |
0 |
| 1603 |
} |
--- |
1603 |
} |
--- |
| 1604 |
return Op; |
0 |
1604 |
return Op; |
0 |
| 1605 |
} |
0 |
1605 |
} |
0 |
| 1606 |
return SDValue(); |
0 |
1606 |
return SDValue(); |
0 |
| 1607 |
} |
--- |
1607 |
} |
--- |
| 1608 |
|
--- |
1608 |
|
--- |
| 1609 |
/// Promote the specified integer shift operation if the target indicates it is |
--- |
1609 |
/// Promote the specified integer shift operation if the target indicates it is |
--- |
| 1610 |
/// beneficial. e.g. On x86, it's usually better to promote i16 operations to |
--- |
1610 |
/// beneficial. e.g. On x86, it's usually better to promote i16 operations to |
--- |
| 1611 |
/// i32 since i16 instructions are longer. |
--- |
1611 |
/// i32 since i16 instructions are longer. |
--- |
| 1612 |
SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { |
0 |
1612 |
SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { |
0 |
| 1613 |
if (!LegalOperations) |
0 |
1613 |
if (!LegalOperations) |
0 |
| 1614 |
return SDValue(); |
0 |
1614 |
return SDValue(); |
0 |
| 1615 |
|
--- |
1615 |
|
--- |
| 1616 |
EVT VT = Op.getValueType(); |
0 |
1616 |
EVT VT = Op.getValueType(); |
0 |
| 1617 |
if (VT.isVector() || !VT.isInteger()) |
0 |
1617 |
if (VT.isVector() || !VT.isInteger()) |
0 |
| 1618 |
return SDValue(); |
0 |
1618 |
return SDValue(); |
0 |
| 1619 |
|
--- |
1619 |
|
--- |
| 1620 |
// If operation type is 'undesirable', e.g. i16 on x86, consider |
--- |
1620 |
// If operation type is 'undesirable', e.g. i16 on x86, consider |
--- |
| 1621 |
// promoting it. |
--- |
1621 |
// promoting it. |
--- |
| 1622 |
unsigned Opc = Op.getOpcode(); |
0 |
1622 |
unsigned Opc = Op.getOpcode(); |
0 |
| 1623 |
if (TLI.isTypeDesirableForOp(Opc, VT)) |
0 |
1623 |
if (TLI.isTypeDesirableForOp(Opc, VT)) |
0 |
| 1624 |
return SDValue(); |
0 |
1624 |
return SDValue(); |
0 |
| 1625 |
|
--- |
1625 |
|
--- |
| 1626 |
EVT PVT = VT; |
0 |
1626 |
EVT PVT = VT; |
0 |
| 1627 |
// Consult target whether it is a good idea to promote this operation and |
--- |
1627 |
// Consult target whether it is a good idea to promote this operation and |
--- |
| 1628 |
// what's the right type to promote it to. |
--- |
1628 |
// what's the right type to promote it to. |
--- |
| 1629 |
if (TLI.IsDesirableToPromoteOp(Op, PVT)) { |
0 |
1629 |
if (TLI.IsDesirableToPromoteOp(Op, PVT)) { |
0 |
| 1630 |
assert(PVT != VT && "Don't know what type to promote to!"); |
0 |
1630 |
assert(PVT != VT && "Don't know what type to promote to!"); |
0 |
| 1631 |
|
--- |
1631 |
|
--- |
| 1632 |
LLVM_DEBUG(dbgs() << "\nPromoting "; Op.dump(&DAG)); |
0 |
1632 |
LLVM_DEBUG(dbgs() << "\nPromoting "; Op.dump(&DAG)); |
0 |
| 1633 |
|
--- |
1633 |
|
--- |
| 1634 |
bool Replace = false; |
0 |
1634 |
bool Replace = false; |
0 |
| 1635 |
SDValue N0 = Op.getOperand(0); |
0 |
1635 |
SDValue N0 = Op.getOperand(0); |
0 |
| 1636 |
if (Opc == ISD::SRA) |
0 |
1636 |
if (Opc == ISD::SRA) |
0 |
| 1637 |
N0 = SExtPromoteOperand(N0, PVT); |
0 |
1637 |
N0 = SExtPromoteOperand(N0, PVT); |
0 |
| 1638 |
else if (Opc == ISD::SRL) |
0 |
1638 |
else if (Opc == ISD::SRL) |
0 |
| 1639 |
N0 = ZExtPromoteOperand(N0, PVT); |
0 |
1639 |
N0 = ZExtPromoteOperand(N0, PVT); |
0 |
| 1640 |
else |
--- |
1640 |
else |
--- |
| 1641 |
N0 = PromoteOperand(N0, PVT, Replace); |
0 |
1641 |
N0 = PromoteOperand(N0, PVT, Replace); |
0 |
| 1642 |
|
--- |
1642 |
|
--- |
| 1643 |
if (!N0.getNode()) |
0 |
1643 |
if (!N0.getNode()) |
0 |
| 1644 |
return SDValue(); |
0 |
1644 |
return SDValue(); |
0 |
| 1645 |
|
--- |
1645 |
|
--- |
| 1646 |
SDLoc DL(Op); |
0 |
1646 |
SDLoc DL(Op); |
0 |
| 1647 |
SDValue N1 = Op.getOperand(1); |
0 |
1647 |
SDValue N1 = Op.getOperand(1); |
0 |
| 1648 |
SDValue RV = |
--- |
1648 |
SDValue RV = |
--- |
| 1649 |
DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1)); |
0 |
1649 |
DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1)); |
0 |
| 1650 |
|
--- |
1650 |
|
--- |
| 1651 |
if (Replace) |
0 |
1651 |
if (Replace) |
0 |
| 1652 |
ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); |
0 |
1652 |
ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); |
0 |
| 1653 |
|
--- |
1653 |
|
--- |
| 1654 |
// Deal with Op being deleted. |
--- |
1654 |
// Deal with Op being deleted. |
--- |
| 1655 |
if (Op && Op.getOpcode() != ISD::DELETED_NODE) |
0 |
1655 |
if (Op && Op.getOpcode() != ISD::DELETED_NODE) |
0 |
| 1656 |
return RV; |
0 |
1656 |
return RV; |
0 |
| 1657 |
} |
0 |
1657 |
} |
0 |
| 1658 |
return SDValue(); |
0 |
1658 |
return SDValue(); |
0 |
| 1659 |
} |
--- |
1659 |
} |
--- |
| 1660 |
|
--- |
1660 |
|
--- |
| 1661 |
SDValue DAGCombiner::PromoteExtend(SDValue Op) { |
0 |
1661 |
SDValue DAGCombiner::PromoteExtend(SDValue Op) { |
0 |
| 1662 |
if (!LegalOperations) |
0 |
1662 |
if (!LegalOperations) |
0 |
| 1663 |
return SDValue(); |
0 |
1663 |
return SDValue(); |
0 |
| 1664 |
|
--- |
1664 |
|
--- |
| 1665 |
EVT VT = Op.getValueType(); |
0 |
1665 |
EVT VT = Op.getValueType(); |
0 |
| 1666 |
if (VT.isVector() || !VT.isInteger()) |
0 |
1666 |
if (VT.isVector() || !VT.isInteger()) |
0 |
| 1667 |
return SDValue(); |
0 |
1667 |
return SDValue(); |
0 |
| 1668 |
|
--- |
1668 |
|
--- |
| 1669 |
// If operation type is 'undesirable', e.g. i16 on x86, consider |
--- |
1669 |
// If operation type is 'undesirable', e.g. i16 on x86, consider |
--- |
| 1670 |
// promoting it. |
--- |
1670 |
// promoting it. |
--- |
| 1671 |
unsigned Opc = Op.getOpcode(); |
0 |
1671 |
unsigned Opc = Op.getOpcode(); |
0 |
| 1672 |
if (TLI.isTypeDesirableForOp(Opc, VT)) |
0 |
1672 |
if (TLI.isTypeDesirableForOp(Opc, VT)) |
0 |
| 1673 |
return SDValue(); |
0 |
1673 |
return SDValue(); |
0 |
| 1674 |
|
--- |
1674 |
|
--- |
| 1675 |
EVT PVT = VT; |
0 |
1675 |
EVT PVT = VT; |
0 |
| 1676 |
// Consult target whether it is a good idea to promote this operation and |
--- |
1676 |
// Consult target whether it is a good idea to promote this operation and |
--- |
| 1677 |
// what's the right type to promote it to. |
--- |
1677 |
// what's the right type to promote it to. |
--- |
| 1678 |
if (TLI.IsDesirableToPromoteOp(Op, PVT)) { |
0 |
1678 |
if (TLI.IsDesirableToPromoteOp(Op, PVT)) { |
0 |
| 1679 |
assert(PVT != VT && "Don't know what type to promote to!"); |
0 |
1679 |
assert(PVT != VT && "Don't know what type to promote to!"); |
0 |
| 1680 |
// fold (aext (aext x)) -> (aext x) |
--- |
1680 |
// fold (aext (aext x)) -> (aext x) |
--- |
| 1681 |
// fold (aext (zext x)) -> (zext x) |
--- |
1681 |
// fold (aext (zext x)) -> (zext x) |
--- |
| 1682 |
// fold (aext (sext x)) -> (sext x) |
--- |
1682 |
// fold (aext (sext x)) -> (sext x) |
--- |
| 1683 |
LLVM_DEBUG(dbgs() << "\nPromoting "; Op.dump(&DAG)); |
0 |
1683 |
LLVM_DEBUG(dbgs() << "\nPromoting "; Op.dump(&DAG)); |
0 |
| 1684 |
return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0)); |
0 |
1684 |
return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0)); |
0 |
| 1685 |
} |
--- |
1685 |
} |
--- |
| 1686 |
return SDValue(); |
0 |
1686 |
return SDValue(); |
0 |
| 1687 |
} |
--- |
1687 |
} |
--- |
| 1688 |
|
--- |
1688 |
|
--- |
| 1689 |
bool DAGCombiner::PromoteLoad(SDValue Op) { |
12 |
1689 |
bool DAGCombiner::PromoteLoad(SDValue Op) { |
12 |
| 1690 |
if (!LegalOperations) |
12 |
1690 |
if (!LegalOperations) |
12 |
| 1691 |
return false; |
7 |
1691 |
return false; |
7 |
| 1692 |
|
--- |
1692 |
|
--- |
| 1693 |
if (!ISD::isUNINDEXEDLoad(Op.getNode())) |
5 |
1693 |
if (!ISD::isUNINDEXEDLoad(Op.getNode())) |
5 |
| 1694 |
return false; |
0 |
1694 |
return false; |
0 |
| 1695 |
|
--- |
1695 |
|
--- |
| 1696 |
EVT VT = Op.getValueType(); |
5 |
1696 |
EVT VT = Op.getValueType(); |
5 |
| 1697 |
if (VT.isVector() || !VT.isInteger()) |
5 |
1697 |
if (VT.isVector() || !VT.isInteger()) |
5 |
| 1698 |
return false; |
0 |
1698 |
return false; |
0 |
| 1699 |
|
--- |
1699 |
|
--- |
| 1700 |
// If operation type is 'undesirable', e.g. i16 on x86, consider |
--- |
1700 |
// If operation type is 'undesirable', e.g. i16 on x86, consider |
--- |
| 1701 |
// promoting it. |
--- |
1701 |
// promoting it. |
--- |
| 1702 |
unsigned Opc = Op.getOpcode(); |
5 |
1702 |
unsigned Opc = Op.getOpcode(); |
5 |
| 1703 |
if (TLI.isTypeDesirableForOp(Opc, VT)) |
5 |
1703 |
if (TLI.isTypeDesirableForOp(Opc, VT)) |
5 |
| 1704 |
return false; |
5 |
1704 |
return false; |
5 |
| 1705 |
|
--- |
1705 |
|
--- |
| 1706 |
EVT PVT = VT; |
0 |
1706 |
EVT PVT = VT; |
0 |
| 1707 |
// Consult target whether it is a good idea to promote this operation and |
--- |
1707 |
// Consult target whether it is a good idea to promote this operation and |
--- |
| 1708 |
// what's the right type to promote it to. |
--- |
1708 |
// what's the right type to promote it to. |
--- |
| 1709 |
if (TLI.IsDesirableToPromoteOp(Op, PVT)) { |
0 |
1709 |
if (TLI.IsDesirableToPromoteOp(Op, PVT)) { |
0 |
| 1710 |
assert(PVT != VT && "Don't know what type to promote to!"); |
0 |
1710 |
assert(PVT != VT && "Don't know what type to promote to!"); |
0 |
| 1711 |
|
--- |
1711 |
|
--- |
| 1712 |
SDLoc DL(Op); |
0 |
1712 |
SDLoc DL(Op); |
0 |
| 1713 |
SDNode *N = Op.getNode(); |
0 |
1713 |
SDNode *N = Op.getNode(); |
0 |
| 1714 |
LoadSDNode *LD = cast(N); |
0 |
1714 |
LoadSDNode *LD = cast(N); |
0 |
| 1715 |
EVT MemVT = LD->getMemoryVT(); |
0 |
1715 |
EVT MemVT = LD->getMemoryVT(); |
0 |
| 1716 |
ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD |
0 |
1716 |
ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD |
0 |
| 1717 |
: LD->getExtensionType(); |
0 |
1717 |
: LD->getExtensionType(); |
0 |
| 1718 |
SDValue NewLD = DAG.getExtLoad(ExtType, DL, PVT, |
0 |
1718 |
SDValue NewLD = DAG.getExtLoad(ExtType, DL, PVT, |
0 |
| 1719 |
LD->getChain(), LD->getBasePtr(), |
0 |
1719 |
LD->getChain(), LD->getBasePtr(), |
0 |
| 1720 |
MemVT, LD->getMemOperand()); |
--- |
1720 |
MemVT, LD->getMemOperand()); |
--- |
| 1721 |
SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD); |
0 |
1721 |
SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD); |
0 |
| 1722 |
|
--- |
1722 |
|
--- |
| 1723 |
LLVM_DEBUG(dbgs() << "\nPromoting "; N->dump(&DAG); dbgs() << "\nTo: "; |
0 |
1723 |
LLVM_DEBUG(dbgs() << "\nPromoting "; N->dump(&DAG); dbgs() << "\nTo: "; |
0 |
| 1724 |
Result.dump(&DAG); dbgs() << '\n'); |
--- |
1724 |
Result.dump(&DAG); dbgs() << '\n'); |
--- |
| 1725 |
|
--- |
1725 |
|
--- |
| 1726 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); |
0 |
1726 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); |
0 |
| 1727 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); |
0 |
1727 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); |
0 |
| 1728 |
|
--- |
1728 |
|
--- |
| 1729 |
AddToWorklist(Result.getNode()); |
0 |
1729 |
AddToWorklist(Result.getNode()); |
0 |
| 1730 |
recursivelyDeleteUnusedNodes(N); |
0 |
1730 |
recursivelyDeleteUnusedNodes(N); |
0 |
| 1731 |
return true; |
0 |
1731 |
return true; |
0 |
| 1732 |
} |
0 |
1732 |
} |
0 |
| 1733 |
|
--- |
1733 |
|
--- |
| 1734 |
return false; |
0 |
1734 |
return false; |
0 |
| 1735 |
} |
--- |
1735 |
} |
--- |
| 1736 |
|
--- |
1736 |
|
--- |
| 1737 |
/// Recursively delete a node which has no uses and any operands for |
--- |
1737 |
/// Recursively delete a node which has no uses and any operands for |
--- |
| 1738 |
/// which it is the only use. |
--- |
1738 |
/// which it is the only use. |
--- |
| 1739 |
/// |
--- |
1739 |
/// |
--- |
| 1740 |
/// Note that this both deletes the nodes and removes them from the worklist. |
--- |
1740 |
/// Note that this both deletes the nodes and removes them from the worklist. |
--- |
| 1741 |
/// It also adds any nodes who have had a user deleted to the worklist as they |
--- |
1741 |
/// It also adds any nodes who have had a user deleted to the worklist as they |
--- |
| 1742 |
/// may now have only one use and subject to other combines. |
--- |
1742 |
/// may now have only one use and subject to other combines. |
--- |
| 1743 |
bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) { |
109 |
1743 |
bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) { |
109 |
| 1744 |
if (!N->use_empty()) |
109 |
1744 |
if (!N->use_empty()) |
109 |
| 1745 |
return false; |
103 |
1745 |
return false; |
103 |
| 1746 |
|
--- |
1746 |
|
--- |
| 1747 |
SmallSetVector Nodes; |
6 |
1747 |
SmallSetVector Nodes; |
6 |
| 1748 |
Nodes.insert(N); |
6 |
1748 |
Nodes.insert(N); |
6 |
| 1749 |
do { |
--- |
1749 |
do { |
--- |
| 1750 |
N = Nodes.pop_back_val(); |
16 |
1750 |
N = Nodes.pop_back_val(); |
16 |
| 1751 |
if (!N) |
16 |
1751 |
if (!N) |
16 |
| 1752 |
continue; |
0 |
1752 |
continue; |
0 |
| 1753 |
|
--- |
1753 |
|
--- |
| 1754 |
if (N->use_empty()) { |
16 |
1754 |
if (N->use_empty()) { |
16 |
| 1755 |
for (const SDValue &ChildN : N->op_values()) |
21 |
1755 |
for (const SDValue &ChildN : N->op_values()) |
21 |
| 1756 |
Nodes.insert(ChildN.getNode()); |
10 |
1756 |
Nodes.insert(ChildN.getNode()); |
10 |
| 1757 |
|
--- |
1757 |
|
--- |
| 1758 |
removeFromWorklist(N); |
11 |
1758 |
removeFromWorklist(N); |
11 |
| 1759 |
DAG.DeleteNode(N); |
11 |
1759 |
DAG.DeleteNode(N); |
11 |
| 1760 |
} else { |
--- |
1760 |
} else { |
--- |
| 1761 |
AddToWorklist(N); |
5 |
1761 |
AddToWorklist(N); |
5 |
| 1762 |
} |
--- |
1762 |
} |
--- |
| 1763 |
} while (!Nodes.empty()); |
16 |
1763 |
} while (!Nodes.empty()); |
16 |
| 1764 |
return true; |
6 |
1764 |
return true; |
6 |
| 1765 |
} |
6 |
1765 |
} |
6 |
| 1766 |
|
--- |
1766 |
|
--- |
| 1767 |
//===----------------------------------------------------------------------===// |
--- |
1767 |
//===----------------------------------------------------------------------===// |
--- |
| 1768 |
// Main DAG Combiner implementation |
--- |
1768 |
// Main DAG Combiner implementation |
--- |
| 1769 |
//===----------------------------------------------------------------------===// |
--- |
1769 |
//===----------------------------------------------------------------------===// |
--- |
| 1770 |
|
--- |
1770 |
|
--- |
| 1771 |
void DAGCombiner::Run(CombineLevel AtLevel) { |
9 |
1771 |
void DAGCombiner::Run(CombineLevel AtLevel) { |
9 |
| 1772 |
// set the instance variables, so that the various visit routines may use it. |
--- |
1772 |
// set the instance variables, so that the various visit routines may use it. |
--- |
| 1773 |
Level = AtLevel; |
9 |
1773 |
Level = AtLevel; |
9 |
| 1774 |
LegalDAG = Level >= AfterLegalizeDAG; |
9 |
1774 |
LegalDAG = Level >= AfterLegalizeDAG; |
9 |
| 1775 |
LegalOperations = Level >= AfterLegalizeVectorOps; |
9 |
1775 |
LegalOperations = Level >= AfterLegalizeVectorOps; |
9 |
| 1776 |
LegalTypes = Level >= AfterLegalizeTypes; |
9 |
1776 |
LegalTypes = Level >= AfterLegalizeTypes; |
9 |
| 1777 |
|
--- |
1777 |
|
--- |
| 1778 |
WorklistInserter AddNodes(*this); |
9 |
1778 |
WorklistInserter AddNodes(*this); |
9 |
| 1779 |
|
--- |
1779 |
|
--- |
| 1780 |
// Add all the dag nodes to the worklist. |
--- |
1780 |
// Add all the dag nodes to the worklist. |
--- |
| 1781 |
// |
--- |
1781 |
// |
--- |
| 1782 |
// Note: All nodes are not added to PruningList here, this is because the only |
--- |
1782 |
// Note: All nodes are not added to PruningList here, this is because the only |
--- |
| 1783 |
// nodes which can be deleted are those which have no uses and all other nodes |
--- |
1783 |
// nodes which can be deleted are those which have no uses and all other nodes |
--- |
| 1784 |
// which would otherwise be added to the worklist by the first call to |
--- |
1784 |
// which would otherwise be added to the worklist by the first call to |
--- |
| 1785 |
// getNextWorklistEntry are already present in it. |
--- |
1785 |
// getNextWorklistEntry are already present in it. |
--- |
| 1786 |
for (SDNode &Node : DAG.allnodes()) |
117 |
1786 |
for (SDNode &Node : DAG.allnodes()) |
117 |
| 1787 |
AddToWorklist(&Node, /* IsCandidateForPruning */ Node.use_empty()); |
108 |
1787 |
AddToWorklist(&Node, /* IsCandidateForPruning */ Node.use_empty()); |
108 |
| 1788 |
|
--- |
1788 |
|
--- |
| 1789 |
// Create a dummy node (which is not added to allnodes), that adds a reference |
--- |
1789 |
// Create a dummy node (which is not added to allnodes), that adds a reference |
--- |
| 1790 |
// to the root node, preventing it from being deleted, and tracking any |
--- |
1790 |
// to the root node, preventing it from being deleted, and tracking any |
--- |
| 1791 |
// changes of the root. |
--- |
1791 |
// changes of the root. |
--- |
| 1792 |
HandleSDNode Dummy(DAG.getRoot()); |
9 |
1792 |
HandleSDNode Dummy(DAG.getRoot()); |
9 |
| 1793 |
|
--- |
1793 |
|
--- |
| 1794 |
// While we have a valid worklist entry node, try to combine it. |
--- |
1794 |
// While we have a valid worklist entry node, try to combine it. |
--- |
| 1795 |
while (SDNode *N = getNextWorklistEntry()) { |
112 |
1795 |
while (SDNode *N = getNextWorklistEntry()) { |
112 |
| 1796 |
// If N has no uses, it is dead. Make sure to revisit all N's operands once |
--- |
1796 |
// If N has no uses, it is dead. Make sure to revisit all N's operands once |
--- |
| 1797 |
// N is deleted from the DAG, since they too may now be dead or may have a |
--- |
1797 |
// N is deleted from the DAG, since they too may now be dead or may have a |
--- |
| 1798 |
// reduced number of uses, allowing other xforms. |
--- |
1798 |
// reduced number of uses, allowing other xforms. |
--- |
| 1799 |
if (recursivelyDeleteUnusedNodes(N)) |
103 |
1799 |
if (recursivelyDeleteUnusedNodes(N)) |
103 |
| 1800 |
continue; |
102 |
1800 |
continue; |
102 |
| 1801 |
|
--- |
1801 |
|
--- |
| 1802 |
WorklistRemover DeadNodes(*this); |
103 |
1802 |
WorklistRemover DeadNodes(*this); |
103 |
| 1803 |
|
--- |
1803 |
|
--- |
| 1804 |
// If this combine is running after legalizing the DAG, re-legalize any |
--- |
1804 |
// If this combine is running after legalizing the DAG, re-legalize any |
--- |
| 1805 |
// nodes pulled off the worklist. |
--- |
1805 |
// nodes pulled off the worklist. |
--- |
| 1806 |
if (LegalDAG) { |
103 |
1806 |
if (LegalDAG) { |
103 |
| 1807 |
SmallSetVector UpdatedNodes; |
41 |
1807 |
SmallSetVector UpdatedNodes; |
41 |
| 1808 |
bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes); |
41 |
1808 |
bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes); |
41 |
| 1809 |
|
--- |
1809 |
|
--- |
| 1810 |
for (SDNode *LN : UpdatedNodes) |
41 |
1810 |
for (SDNode *LN : UpdatedNodes) |
41 |
| 1811 |
AddToWorklistWithUsers(LN); |
0 |
1811 |
AddToWorklistWithUsers(LN); |
0 |
| 1812 |
|
--- |
1812 |
|
--- |
| 1813 |
if (!NIsValid) |
41 |
1813 |
if (!NIsValid) |
41 |
| 1814 |
continue; |
0 |
1814 |
continue; |
0 |
| 1815 |
} |
41 |
1815 |
} |
41 |
| 1816 |
|
--- |
1816 |
|
--- |
| 1817 |
LLVM_DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG)); |
103 |
1817 |
LLVM_DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG)); |
103 |
| 1818 |
|
--- |
1818 |
|
--- |
| 1819 |
// Add any operands of the new node which have not yet been combined to the |
--- |
1819 |
// Add any operands of the new node which have not yet been combined to the |
--- |
| 1820 |
// worklist as well. Because the worklist uniques things already, this |
--- |
1820 |
// worklist as well. Because the worklist uniques things already, this |
--- |
| 1821 |
// won't repeatedly process the same operand. |
--- |
1821 |
// won't repeatedly process the same operand. |
--- |
| 1822 |
for (const SDValue &ChildN : N->op_values()) |
242 |
1822 |
for (const SDValue &ChildN : N->op_values()) |
242 |
| 1823 |
if (!CombinedNodes.count(ChildN.getNode())) |
139 |
1823 |
if (!CombinedNodes.count(ChildN.getNode())) |
139 |
| 1824 |
AddToWorklist(ChildN.getNode()); |
135 |
1824 |
AddToWorklist(ChildN.getNode()); |
135 |
| 1825 |
|
--- |
1825 |
|
--- |
| 1826 |
CombinedNodes.insert(N); |
103 |
1826 |
CombinedNodes.insert(N); |
103 |
| 1827 |
SDValue RV = combine(N); |
103 |
1827 |
SDValue RV = combine(N); |
103 |
| 1828 |
|
--- |
1828 |
|
--- |
| 1829 |
if (!RV.getNode()) |
103 |
1829 |
if (!RV.getNode()) |
103 |
| 1830 |
continue; |
101 |
1830 |
continue; |
101 |
| 1831 |
|
--- |
1831 |
|
--- |
| 1832 |
++NodesCombined; |
2 |
1832 |
++NodesCombined; |
2 |
| 1833 |
|
--- |
1833 |
|
--- |
| 1834 |
// If we get back the same node we passed in, rather than a new node or |
--- |
1834 |
// If we get back the same node we passed in, rather than a new node or |
--- |
| 1835 |
// zero, we know that the node must have defined multiple values and |
--- |
1835 |
// zero, we know that the node must have defined multiple values and |
--- |
| 1836 |
// CombineTo was used. Since CombineTo takes care of the worklist |
--- |
1836 |
// CombineTo was used. Since CombineTo takes care of the worklist |
--- |
| 1837 |
// mechanics for us, we have no work to do in this case. |
--- |
1837 |
// mechanics for us, we have no work to do in this case. |
--- |
| 1838 |
if (RV.getNode() == N) |
2 |
1838 |
if (RV.getNode() == N) |
2 |
| 1839 |
continue; |
1 |
1839 |
continue; |
1 |
| 1840 |
|
--- |
1840 |
|
--- |
| 1841 |
assert(N->getOpcode() != ISD::DELETED_NODE && |
1 |
1841 |
assert(N->getOpcode() != ISD::DELETED_NODE && |
1 |
| 1842 |
RV.getOpcode() != ISD::DELETED_NODE && |
--- |
1842 |
RV.getOpcode() != ISD::DELETED_NODE && |
--- |
| 1843 |
"Node was deleted but visit returned new node!"); |
--- |
1843 |
"Node was deleted but visit returned new node!"); |
--- |
| 1844 |
|
--- |
1844 |
|
--- |
| 1845 |
LLVM_DEBUG(dbgs() << " ... into: "; RV.dump(&DAG)); |
1 |
1845 |
LLVM_DEBUG(dbgs() << " ... into: "; RV.dump(&DAG)); |
1 |
| 1846 |
|
--- |
1846 |
|
--- |
| 1847 |
if (N->getNumValues() == RV->getNumValues()) |
1 |
1847 |
if (N->getNumValues() == RV->getNumValues()) |
1 |
| 1848 |
DAG.ReplaceAllUsesWith(N, RV.getNode()); |
1 |
1848 |
DAG.ReplaceAllUsesWith(N, RV.getNode()); |
1 |
| 1849 |
else { |
--- |
1849 |
else { |
--- |
| 1850 |
assert(N->getValueType(0) == RV.getValueType() && |
0 |
1850 |
assert(N->getValueType(0) == RV.getValueType() && |
0 |
| 1851 |
N->getNumValues() == 1 && "Type mismatch"); |
--- |
1851 |
N->getNumValues() == 1 && "Type mismatch"); |
--- |
| 1852 |
DAG.ReplaceAllUsesWith(N, &RV); |
0 |
1852 |
DAG.ReplaceAllUsesWith(N, &RV); |
0 |
| 1853 |
} |
--- |
1853 |
} |
--- |
| 1854 |
|
--- |
1854 |
|
--- |
| 1855 |
// Push the new node and any users onto the worklist. Omit this if the |
--- |
1855 |
// Push the new node and any users onto the worklist. Omit this if the |
--- |
| 1856 |
// new node is the EntryToken (e.g. if a store managed to get optimized |
--- |
1856 |
// new node is the EntryToken (e.g. if a store managed to get optimized |
--- |
| 1857 |
// out), because re-visiting the EntryToken and its users will not uncover |
--- |
1857 |
// out), because re-visiting the EntryToken and its users will not uncover |
--- |
| 1858 |
// any additional opportunities, but there may be a large number of such |
--- |
1858 |
// any additional opportunities, but there may be a large number of such |
--- |
| 1859 |
// users, potentially causing compile time explosion. |
--- |
1859 |
// users, potentially causing compile time explosion. |
--- |
| 1860 |
if (RV.getOpcode() != ISD::EntryToken) |
1 |
1860 |
if (RV.getOpcode() != ISD::EntryToken) |
1 |
| 1861 |
AddToWorklistWithUsers(RV.getNode()); |
1 |
1861 |
AddToWorklistWithUsers(RV.getNode()); |
1 |
| 1862 |
|
--- |
1862 |
|
--- |
| 1863 |
// Finally, if the node is now dead, remove it from the graph. The node |
--- |
1863 |
// Finally, if the node is now dead, remove it from the graph. The node |
--- |
| 1864 |
// may not be dead if the replacement process recursively simplified to |
--- |
1864 |
// may not be dead if the replacement process recursively simplified to |
--- |
| 1865 |
// something else needing this node. This will also take care of adding any |
--- |
1865 |
// something else needing this node. This will also take care of adding any |
--- |
| 1866 |
// operands which have lost a user to the worklist. |
--- |
1866 |
// operands which have lost a user to the worklist. |
--- |
| 1867 |
recursivelyDeleteUnusedNodes(N); |
1 |
1867 |
recursivelyDeleteUnusedNodes(N); |
1 |
| 1868 |
} |
103 |
1868 |
} |
103 |
| 1869 |
|
--- |
1869 |
|
--- |
| 1870 |
// If the root changed (e.g. it was a dead load, update the root). |
--- |
1870 |
// If the root changed (e.g. it was a dead load, update the root). |
--- |
| 1871 |
DAG.setRoot(Dummy.getValue()); |
9 |
1871 |
DAG.setRoot(Dummy.getValue()); |
9 |
| 1872 |
DAG.RemoveDeadNodes(); |
9 |
1872 |
DAG.RemoveDeadNodes(); |
9 |
| 1873 |
} |
9 |
1873 |
} |
9 |
| 1874 |
|
--- |
1874 |
|
--- |
| 1875 |
SDValue DAGCombiner::visit(SDNode *N) { |
103 |
1875 |
SDValue DAGCombiner::visit(SDNode *N) { |
103 |
| 1876 |
switch (N->getOpcode()) { |
103 |
1876 |
switch (N->getOpcode()) { |
103 |
| 1877 |
default: break; |
73 |
1877 |
default: break; |
73 |
| 1878 |
case ISD::TokenFactor: return visitTokenFactor(N); |
0 |
1878 |
case ISD::TokenFactor: return visitTokenFactor(N); |
0 |
| 1879 |
case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); |
0 |
1879 |
case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); |
0 |
| 1880 |
case ISD::ADD: return visitADD(N); |
0 |
1880 |
case ISD::ADD: return visitADD(N); |
0 |
| 1881 |
case ISD::SUB: return visitSUB(N); |
0 |
1881 |
case ISD::SUB: return visitSUB(N); |
0 |
| 1882 |
case ISD::SADDSAT: |
0 |
1882 |
case ISD::SADDSAT: |
0 |
| 1883 |
case ISD::UADDSAT: return visitADDSAT(N); |
0 |
1883 |
case ISD::UADDSAT: return visitADDSAT(N); |
0 |
| 1884 |
case ISD::SSUBSAT: |
0 |
1884 |
case ISD::SSUBSAT: |
0 |
| 1885 |
case ISD::USUBSAT: return visitSUBSAT(N); |
0 |
1885 |
case ISD::USUBSAT: return visitSUBSAT(N); |
0 |
| 1886 |
case ISD::ADDC: return visitADDC(N); |
0 |
1886 |
case ISD::ADDC: return visitADDC(N); |
0 |
| 1887 |
case ISD::SADDO: |
0 |
1887 |
case ISD::SADDO: |
0 |
| 1888 |
case ISD::UADDO: return visitADDO(N); |
0 |
1888 |
case ISD::UADDO: return visitADDO(N); |
0 |
| 1889 |
case ISD::SUBC: return visitSUBC(N); |
0 |
1889 |
case ISD::SUBC: return visitSUBC(N); |
0 |
| 1890 |
case ISD::SSUBO: |
0 |
1890 |
case ISD::SSUBO: |
0 |
| 1891 |
case ISD::USUBO: return visitSUBO(N); |
0 |
1891 |
case ISD::USUBO: return visitSUBO(N); |
0 |
| 1892 |
case ISD::ADDE: return visitADDE(N); |
0 |
1892 |
case ISD::ADDE: return visitADDE(N); |
0 |
| 1893 |
case ISD::UADDO_CARRY: return visitUADDO_CARRY(N); |
0 |
1893 |
case ISD::UADDO_CARRY: return visitUADDO_CARRY(N); |
0 |
| 1894 |
case ISD::SADDO_CARRY: return visitSADDO_CARRY(N); |
0 |
1894 |
case ISD::SADDO_CARRY: return visitSADDO_CARRY(N); |
0 |
| 1895 |
case ISD::SUBE: return visitSUBE(N); |
0 |
1895 |
case ISD::SUBE: return visitSUBE(N); |
0 |
| 1896 |
case ISD::USUBO_CARRY: return visitUSUBO_CARRY(N); |
0 |
1896 |
case ISD::USUBO_CARRY: return visitUSUBO_CARRY(N); |
0 |
| 1897 |
case ISD::SSUBO_CARRY: return visitSSUBO_CARRY(N); |
0 |
1897 |
case ISD::SSUBO_CARRY: return visitSSUBO_CARRY(N); |
0 |
| 1898 |
case ISD::SMULFIX: |
0 |
1898 |
case ISD::SMULFIX: |
0 |
| 1899 |
case ISD::SMULFIXSAT: |
--- |
1899 |
case ISD::SMULFIXSAT: |
--- |
| 1900 |
case ISD::UMULFIX: |
--- |
1900 |
case ISD::UMULFIX: |
--- |
| 1901 |
case ISD::UMULFIXSAT: return visitMULFIX(N); |
0 |
1901 |
case ISD::UMULFIXSAT: return visitMULFIX(N); |
0 |
| 1902 |
case ISD::MUL: return visitMUL(N); |
0 |
1902 |
case ISD::MUL: return visitMUL(N); |
0 |
| 1903 |
case ISD::SDIV: return visitSDIV(N); |
0 |
1903 |
case ISD::SDIV: return visitSDIV(N); |
0 |
| 1904 |
case ISD::UDIV: return visitUDIV(N); |
0 |
1904 |
case ISD::UDIV: return visitUDIV(N); |
0 |
| 1905 |
case ISD::SREM: |
0 |
1905 |
case ISD::SREM: |
0 |
| 1906 |
case ISD::UREM: return visitREM(N); |
0 |
1906 |
case ISD::UREM: return visitREM(N); |
0 |
| 1907 |
case ISD::MULHU: return visitMULHU(N); |
0 |
1907 |
case ISD::MULHU: return visitMULHU(N); |
0 |
| 1908 |
case ISD::MULHS: return visitMULHS(N); |
0 |
1908 |
case ISD::MULHS: return visitMULHS(N); |
0 |
| 1909 |
case ISD::AVGFLOORS: |
0 |
1909 |
case ISD::AVGFLOORS: |
0 |
| 1910 |
case ISD::AVGFLOORU: |
--- |
1910 |
case ISD::AVGFLOORU: |
--- |
| 1911 |
case ISD::AVGCEILS: |
--- |
1911 |
case ISD::AVGCEILS: |
--- |
| 1912 |
case ISD::AVGCEILU: return visitAVG(N); |
0 |
1912 |
case ISD::AVGCEILU: return visitAVG(N); |
0 |
| 1913 |
case ISD::ABDS: |
0 |
1913 |
case ISD::ABDS: |
0 |
| 1914 |
case ISD::ABDU: return visitABD(N); |
0 |
1914 |
case ISD::ABDU: return visitABD(N); |
0 |
| 1915 |
case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); |
0 |
1915 |
case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); |
0 |
| 1916 |
case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); |
0 |
1916 |
case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); |
0 |
| 1917 |
case ISD::SMULO: |
0 |
1917 |
case ISD::SMULO: |
0 |
| 1918 |
case ISD::UMULO: return visitMULO(N); |
0 |
1918 |
case ISD::UMULO: return visitMULO(N); |
0 |
| 1919 |
case ISD::SMIN: |
0 |
1919 |
case ISD::SMIN: |
0 |
| 1920 |
case ISD::SMAX: |
--- |
1920 |
case ISD::SMAX: |
--- |
| 1921 |
case ISD::UMIN: |
--- |
1921 |
case ISD::UMIN: |
--- |
| 1922 |
case ISD::UMAX: return visitIMINMAX(N); |
0 |
1922 |
case ISD::UMAX: return visitIMINMAX(N); |
0 |
| 1923 |
case ISD::AND: return visitAND(N); |
1 |
1923 |
case ISD::AND: return visitAND(N); |
1 |
| 1924 |
case ISD::OR: return visitOR(N); |
0 |
1924 |
case ISD::OR: return visitOR(N); |
0 |
| 1925 |
case ISD::XOR: return visitXOR(N); |
0 |
1925 |
case ISD::XOR: return visitXOR(N); |
0 |
| 1926 |
case ISD::SHL: return visitSHL(N); |
0 |
1926 |
case ISD::SHL: return visitSHL(N); |
0 |
| 1927 |
case ISD::SRA: return visitSRA(N); |
0 |
1927 |
case ISD::SRA: return visitSRA(N); |
0 |
| 1928 |
case ISD::SRL: return visitSRL(N); |
0 |
1928 |
case ISD::SRL: return visitSRL(N); |
0 |
| 1929 |
case ISD::ROTR: |
0 |
1929 |
case ISD::ROTR: |
0 |
| 1930 |
case ISD::ROTL: return visitRotate(N); |
0 |
1930 |
case ISD::ROTL: return visitRotate(N); |
0 |
| 1931 |
case ISD::FSHL: |
0 |
1931 |
case ISD::FSHL: |
0 |
| 1932 |
case ISD::FSHR: return visitFunnelShift(N); |
0 |
1932 |
case ISD::FSHR: return visitFunnelShift(N); |
0 |
| 1933 |
case ISD::SSHLSAT: |
0 |
1933 |
case ISD::SSHLSAT: |
0 |
| 1934 |
case ISD::USHLSAT: return visitSHLSAT(N); |
0 |
1934 |
case ISD::USHLSAT: return visitSHLSAT(N); |
0 |
| 1935 |
case ISD::ABS: return visitABS(N); |
0 |
1935 |
case ISD::ABS: return visitABS(N); |
0 |
| 1936 |
case ISD::BSWAP: return visitBSWAP(N); |
0 |
1936 |
case ISD::BSWAP: return visitBSWAP(N); |
0 |
| 1937 |
case ISD::BITREVERSE: return visitBITREVERSE(N); |
0 |
1937 |
case ISD::BITREVERSE: return visitBITREVERSE(N); |
0 |
| 1938 |
case ISD::CTLZ: return visitCTLZ(N); |
0 |
1938 |
case ISD::CTLZ: return visitCTLZ(N); |
0 |
| 1939 |
case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); |
0 |
1939 |
case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); |
0 |
| 1940 |
case ISD::CTTZ: return visitCTTZ(N); |
0 |
1940 |
case ISD::CTTZ: return visitCTTZ(N); |
0 |
| 1941 |
case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); |
0 |
1941 |
case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); |
0 |
| 1942 |
case ISD::CTPOP: return visitCTPOP(N); |
0 |
1942 |
case ISD::CTPOP: return visitCTPOP(N); |
0 |
| 1943 |
case ISD::SELECT: return visitSELECT(N); |
0 |
1943 |
case ISD::SELECT: return visitSELECT(N); |
0 |
| 1944 |
case ISD::VSELECT: return visitVSELECT(N); |
0 |
1944 |
case ISD::VSELECT: return visitVSELECT(N); |
0 |
| 1945 |
case ISD::SELECT_CC: return visitSELECT_CC(N); |
0 |
1945 |
case ISD::SELECT_CC: return visitSELECT_CC(N); |
0 |
| 1946 |
case ISD::SETCC: return visitSETCC(N); |
3 |
1946 |
case ISD::SETCC: return visitSETCC(N); |
3 |
| 1947 |
case ISD::SETCCCARRY: return visitSETCCCARRY(N); |
0 |
1947 |
case ISD::SETCCCARRY: return visitSETCCCARRY(N); |
0 |
| 1948 |
case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); |
0 |
1948 |
case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); |
0 |
| 1949 |
case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); |
0 |
1949 |
case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); |
0 |
| 1950 |
case ISD::ANY_EXTEND: return visitANY_EXTEND(N); |
0 |
1950 |
case ISD::ANY_EXTEND: return visitANY_EXTEND(N); |
0 |
| 1951 |
case ISD::AssertSext: |
0 |
1951 |
case ISD::AssertSext: |
0 |
| 1952 |
case ISD::AssertZext: return visitAssertExt(N); |
0 |
1952 |
case ISD::AssertZext: return visitAssertExt(N); |
0 |
| 1953 |
case ISD::AssertAlign: return visitAssertAlign(N); |
0 |
1953 |
case ISD::AssertAlign: return visitAssertAlign(N); |
0 |
| 1954 |
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); |
0 |
1954 |
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); |
0 |
| 1955 |
case ISD::SIGN_EXTEND_VECTOR_INREG: |
0 |
1955 |
case ISD::SIGN_EXTEND_VECTOR_INREG: |
0 |
| 1956 |
case ISD::ZERO_EXTEND_VECTOR_INREG: |
--- |
1956 |
case ISD::ZERO_EXTEND_VECTOR_INREG: |
--- |
| 1957 |
case ISD::ANY_EXTEND_VECTOR_INREG: return visitEXTEND_VECTOR_INREG(N); |
0 |
1957 |
case ISD::ANY_EXTEND_VECTOR_INREG: return visitEXTEND_VECTOR_INREG(N); |
0 |
| 1958 |
case ISD::TRUNCATE: return visitTRUNCATE(N); |
0 |
1958 |
case ISD::TRUNCATE: return visitTRUNCATE(N); |
0 |
| 1959 |
case ISD::BITCAST: return visitBITCAST(N); |
0 |
1959 |
case ISD::BITCAST: return visitBITCAST(N); |
0 |
| 1960 |
case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); |
0 |
1960 |
case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); |
0 |
| 1961 |
case ISD::FADD: return visitFADD(N); |
0 |
1961 |
case ISD::FADD: return visitFADD(N); |
0 |
| 1962 |
case ISD::STRICT_FADD: return visitSTRICT_FADD(N); |
0 |
1962 |
case ISD::STRICT_FADD: return visitSTRICT_FADD(N); |
0 |
| 1963 |
case ISD::FSUB: return visitFSUB(N); |
0 |
1963 |
case ISD::FSUB: return visitFSUB(N); |
0 |
| 1964 |
case ISD::FMUL: return visitFMUL(N); |
0 |
1964 |
case ISD::FMUL: return visitFMUL(N); |
0 |
| 1965 |
case ISD::FMA: return visitFMA(N); |
0 |
1965 |
case ISD::FMA: return visitFMA(N); |
0 |
| 1966 |
case ISD::FDIV: return visitFDIV(N); |
0 |
1966 |
case ISD::FDIV: return visitFDIV(N); |
0 |
| 1967 |
case ISD::FREM: return visitFREM(N); |
0 |
1967 |
case ISD::FREM: return visitFREM(N); |
0 |
| 1968 |
case ISD::FSQRT: return visitFSQRT(N); |
0 |
1968 |
case ISD::FSQRT: return visitFSQRT(N); |
0 |
| 1969 |
case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); |
0 |
1969 |
case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); |
0 |
| 1970 |
case ISD::FPOW: return visitFPOW(N); |
0 |
1970 |
case ISD::FPOW: return visitFPOW(N); |
0 |
| 1971 |
case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); |
0 |
1971 |
case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); |
0 |
| 1972 |
case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); |
0 |
1972 |
case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); |
0 |
| 1973 |
case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); |
0 |
1973 |
case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); |
0 |
| 1974 |
case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); |
0 |
1974 |
case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); |
0 |
| 1975 |
case ISD::FP_ROUND: return visitFP_ROUND(N); |
0 |
1975 |
case ISD::FP_ROUND: return visitFP_ROUND(N); |
0 |
| 1976 |
case ISD::FP_EXTEND: return visitFP_EXTEND(N); |
0 |
1976 |
case ISD::FP_EXTEND: return visitFP_EXTEND(N); |
0 |
| 1977 |
case ISD::FNEG: return visitFNEG(N); |
0 |
1977 |
case ISD::FNEG: return visitFNEG(N); |
0 |
| 1978 |
case ISD::FABS: return visitFABS(N); |
0 |
1978 |
case ISD::FABS: return visitFABS(N); |
0 |
| 1979 |
case ISD::FFLOOR: return visitFFLOOR(N); |
0 |
1979 |
case ISD::FFLOOR: return visitFFLOOR(N); |
0 |
| 1980 |
case ISD::FMINNUM: |
0 |
1980 |
case ISD::FMINNUM: |
0 |
| 1981 |
case ISD::FMAXNUM: |
--- |
1981 |
case ISD::FMAXNUM: |
--- |
| 1982 |
case ISD::FMINIMUM: |
--- |
1982 |
case ISD::FMINIMUM: |
--- |
| 1983 |
case ISD::FMAXIMUM: return visitFMinMax(N); |
0 |
1983 |
case ISD::FMAXIMUM: return visitFMinMax(N); |
0 |
| 1984 |
case ISD::FCEIL: return visitFCEIL(N); |
0 |
1984 |
case ISD::FCEIL: return visitFCEIL(N); |
0 |
| 1985 |
case ISD::FTRUNC: return visitFTRUNC(N); |
0 |
1985 |
case ISD::FTRUNC: return visitFTRUNC(N); |
0 |
| 1986 |
case ISD::FFREXP: return visitFFREXP(N); |
0 |
1986 |
case ISD::FFREXP: return visitFFREXP(N); |
0 |
| 1987 |
case ISD::BRCOND: return visitBRCOND(N); |
4 |
1987 |
case ISD::BRCOND: return visitBRCOND(N); |
4 |
| 1988 |
case ISD::BR_CC: return visitBR_CC(N); |
0 |
1988 |
case ISD::BR_CC: return visitBR_CC(N); |
0 |
| 1989 |
case ISD::LOAD: return visitLOAD(N); |
12 |
1989 |
case ISD::LOAD: return visitLOAD(N); |
12 |
| 1990 |
case ISD::STORE: return visitSTORE(N); |
10 |
1990 |
case ISD::STORE: return visitSTORE(N); |
10 |
| 1991 |
case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); |
0 |
1991 |
case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); |
0 |
| 1992 |
case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); |
0 |
1992 |
case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); |
0 |
| 1993 |
case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); |
0 |
1993 |
case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); |
0 |
| 1994 |
case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); |
0 |
1994 |
case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); |
0 |
| 1995 |
case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); |
0 |
1995 |
case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); |
0 |
| 1996 |
case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); |
0 |
1996 |
case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); |
0 |
| 1997 |
case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N); |
0 |
1997 |
case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N); |
0 |
| 1998 |
case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N); |
0 |
1998 |
case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N); |
0 |
| 1999 |
case ISD::MGATHER: return visitMGATHER(N); |
0 |
1999 |
case ISD::MGATHER: return visitMGATHER(N); |
0 |
| 2000 |
case ISD::MLOAD: return visitMLOAD(N); |
0 |
2000 |
case ISD::MLOAD: return visitMLOAD(N); |
0 |
| 2001 |
case ISD::MSCATTER: return visitMSCATTER(N); |
0 |
2001 |
case ISD::MSCATTER: return visitMSCATTER(N); |
0 |
| 2002 |
case ISD::MSTORE: return visitMSTORE(N); |
0 |
2002 |
case ISD::MSTORE: return visitMSTORE(N); |
0 |
| 2003 |
case ISD::LIFETIME_END: return visitLIFETIME_END(N); |
0 |
2003 |
case ISD::LIFETIME_END: return visitLIFETIME_END(N); |
0 |
| 2004 |
case ISD::FP_TO_FP16: return visitFP_TO_FP16(N); |
0 |
2004 |
case ISD::FP_TO_FP16: return visitFP_TO_FP16(N); |
0 |
| 2005 |
case ISD::FP16_TO_FP: return visitFP16_TO_FP(N); |
0 |
2005 |
case ISD::FP16_TO_FP: return visitFP16_TO_FP(N); |
0 |
| 2006 |
case ISD::FP_TO_BF16: return visitFP_TO_BF16(N); |
0 |
2006 |
case ISD::FP_TO_BF16: return visitFP_TO_BF16(N); |
0 |
| 2007 |
case ISD::FREEZE: return visitFREEZE(N); |
0 |
2007 |
case ISD::FREEZE: return visitFREEZE(N); |
0 |
| 2008 |
case ISD::GET_FPENV_MEM: return visitGET_FPENV_MEM(N); |
0 |
2008 |
case ISD::GET_FPENV_MEM: return visitGET_FPENV_MEM(N); |
0 |
| 2009 |
case ISD::SET_FPENV_MEM: return visitSET_FPENV_MEM(N); |
0 |
2009 |
case ISD::SET_FPENV_MEM: return visitSET_FPENV_MEM(N); |
0 |
| 2010 |
case ISD::VECREDUCE_FADD: |
0 |
2010 |
case ISD::VECREDUCE_FADD: |
0 |
| 2011 |
case ISD::VECREDUCE_FMUL: |
--- |
2011 |
case ISD::VECREDUCE_FMUL: |
--- |
| 2012 |
case ISD::VECREDUCE_ADD: |
--- |
2012 |
case ISD::VECREDUCE_ADD: |
--- |
| 2013 |
case ISD::VECREDUCE_MUL: |
--- |
2013 |
case ISD::VECREDUCE_MUL: |
--- |
| 2014 |
case ISD::VECREDUCE_AND: |
--- |
2014 |
case ISD::VECREDUCE_AND: |
--- |
| 2015 |
case ISD::VECREDUCE_OR: |
--- |
2015 |
case ISD::VECREDUCE_OR: |
--- |
| 2016 |
case ISD::VECREDUCE_XOR: |
--- |
2016 |
case ISD::VECREDUCE_XOR: |
--- |
| 2017 |
case ISD::VECREDUCE_SMAX: |
--- |
2017 |
case ISD::VECREDUCE_SMAX: |
--- |
| 2018 |
case ISD::VECREDUCE_SMIN: |
--- |
2018 |
case ISD::VECREDUCE_SMIN: |
--- |
| 2019 |
case ISD::VECREDUCE_UMAX: |
--- |
2019 |
case ISD::VECREDUCE_UMAX: |
--- |
| 2020 |
case ISD::VECREDUCE_UMIN: |
--- |
2020 |
case ISD::VECREDUCE_UMIN: |
--- |
| 2021 |
case ISD::VECREDUCE_FMAX: |
--- |
2021 |
case ISD::VECREDUCE_FMAX: |
--- |
| 2022 |
case ISD::VECREDUCE_FMIN: |
--- |
2022 |
case ISD::VECREDUCE_FMIN: |
--- |
| 2023 |
case ISD::VECREDUCE_FMAXIMUM: |
--- |
2023 |
case ISD::VECREDUCE_FMAXIMUM: |
--- |
| 2024 |
case ISD::VECREDUCE_FMINIMUM: return visitVECREDUCE(N); |
0 |
2024 |
case ISD::VECREDUCE_FMINIMUM: return visitVECREDUCE(N); |
0 |
| 2025 |
#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) case ISD::SDOPC: |
--- |
2025 |
#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) case ISD::SDOPC: |
--- |
| 2026 |
#include "llvm/IR/VPIntrinsics.def" |
--- |
2026 |
#include "llvm/IR/VPIntrinsics.def" |
--- |
| 2027 |
return visitVPOp(N); |
0 |
2027 |
return visitVPOp(N); |
0 |
| 2028 |
} |
--- |
2028 |
} |
--- |
| 2029 |
return SDValue(); |
73 |
2029 |
return SDValue(); |
73 |
| 2030 |
} |
--- |
2030 |
} |
--- |
| 2031 |
|
--- |
2031 |
|
--- |
| 2032 |
SDValue DAGCombiner::combine(SDNode *N) { |
103 |
2032 |
SDValue DAGCombiner::combine(SDNode *N) { |
103 |
| 2033 |
SDValue RV; |
103 |
2033 |
SDValue RV; |
103 |
| 2034 |
if (!DisableGenericCombines) |
103 |
2034 |
if (!DisableGenericCombines) |
103 |
| 2035 |
RV = visit(N); |
103 |
2035 |
RV = visit(N); |
103 |
| 2036 |
|
--- |
2036 |
|
--- |
| 2037 |
// If nothing happened, try a target-specific DAG combine. |
--- |
2037 |
// If nothing happened, try a target-specific DAG combine. |
--- |
| 2038 |
if (!RV.getNode()) { |
103 |
2038 |
if (!RV.getNode()) { |
103 |
| 2039 |
assert(N->getOpcode() != ISD::DELETED_NODE && |
101 |
2039 |
assert(N->getOpcode() != ISD::DELETED_NODE && |
101 |
| 2040 |
"Node was deleted but visit returned NULL!"); |
--- |
2040 |
"Node was deleted but visit returned NULL!"); |
--- |
| 2041 |
|
--- |
2041 |
|
--- |
| 2042 |
if (N->getOpcode() >= ISD::BUILTIN_OP_END || |
200 |
2042 |
if (N->getOpcode() >= ISD::BUILTIN_OP_END || |
200 |
| 2043 |
TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { |
99 |
2043 |
TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { |
99 |
| 2044 |
|
--- |
2044 |
|
--- |
| 2045 |
// Expose the DAG combiner to the target combiner impls. |
--- |
2045 |
// Expose the DAG combiner to the target combiner impls. |
--- |
| 2046 |
TargetLowering::DAGCombinerInfo |
--- |
2046 |
TargetLowering::DAGCombinerInfo |
--- |
| 2047 |
DagCombineInfo(DAG, Level, false, this); |
2 |
2047 |
DagCombineInfo(DAG, Level, false, this); |
2 |
| 2048 |
|
--- |
2048 |
|
--- |
| 2049 |
RV = TLI.PerformDAGCombine(N, DagCombineInfo); |
2 |
2049 |
RV = TLI.PerformDAGCombine(N, DagCombineInfo); |
2 |
| 2050 |
} |
--- |
2050 |
} |
--- |
| 2051 |
} |
--- |
2051 |
} |
--- |
| 2052 |
|
--- |
2052 |
|
--- |
| 2053 |
// If nothing happened still, try promoting the operation. |
--- |
2053 |
// If nothing happened still, try promoting the operation. |
--- |
| 2054 |
if (!RV.getNode()) { |
103 |
2054 |
if (!RV.getNode()) { |
103 |
| 2055 |
switch (N->getOpcode()) { |
101 |
2055 |
switch (N->getOpcode()) { |
101 |
| 2056 |
default: break; |
89 |
2056 |
default: break; |
89 |
| 2057 |
case ISD::ADD: |
0 |
2057 |
case ISD::ADD: |
0 |
| 2058 |
case ISD::SUB: |
--- |
2058 |
case ISD::SUB: |
--- |
| 2059 |
case ISD::MUL: |
--- |
2059 |
case ISD::MUL: |
--- |
| 2060 |
case ISD::AND: |
--- |
2060 |
case ISD::AND: |
--- |
| 2061 |
case ISD::OR: |
--- |
2061 |
case ISD::OR: |
--- |
| 2062 |
case ISD::XOR: |
--- |
2062 |
case ISD::XOR: |
--- |
| 2063 |
RV = PromoteIntBinOp(SDValue(N, 0)); |
0 |
2063 |
RV = PromoteIntBinOp(SDValue(N, 0)); |
0 |
| 2064 |
break; |
0 |
2064 |
break; |
0 |
| 2065 |
case ISD::SHL: |
0 |
2065 |
case ISD::SHL: |
0 |
| 2066 |
case ISD::SRA: |
--- |
2066 |
case ISD::SRA: |
--- |
| 2067 |
case ISD::SRL: |
--- |
2067 |
case ISD::SRL: |
--- |
| 2068 |
RV = PromoteIntShiftOp(SDValue(N, 0)); |
0 |
2068 |
RV = PromoteIntShiftOp(SDValue(N, 0)); |
0 |
| 2069 |
break; |
0 |
2069 |
break; |
0 |
| 2070 |
case ISD::SIGN_EXTEND: |
0 |
2070 |
case ISD::SIGN_EXTEND: |
0 |
| 2071 |
case ISD::ZERO_EXTEND: |
--- |
2071 |
case ISD::ZERO_EXTEND: |
--- |
| 2072 |
case ISD::ANY_EXTEND: |
--- |
2072 |
case ISD::ANY_EXTEND: |
--- |
| 2073 |
RV = PromoteExtend(SDValue(N, 0)); |
0 |
2073 |
RV = PromoteExtend(SDValue(N, 0)); |
0 |
| 2074 |
break; |
0 |
2074 |
break; |
0 |
| 2075 |
case ISD::LOAD: |
12 |
2075 |
case ISD::LOAD: |
12 |
| 2076 |
if (PromoteLoad(SDValue(N, 0))) |
12 |
2076 |
if (PromoteLoad(SDValue(N, 0))) |
12 |
| 2077 |
RV = SDValue(N, 0); |
0 |
2077 |
RV = SDValue(N, 0); |
0 |
| 2078 |
break; |
12 |
2078 |
break; |
12 |
| 2079 |
} |
--- |
2079 |
} |
--- |
| 2080 |
} |
--- |
2080 |
} |
--- |
| 2081 |
|
--- |
2081 |
|
--- |
| 2082 |
// If N is a commutative binary node, try to eliminate it if the commuted |
--- |
2082 |
// If N is a commutative binary node, try to eliminate it if the commuted |
--- |
| 2083 |
// version is already present in the DAG. |
--- |
2083 |
// version is already present in the DAG. |
--- |
| 2084 |
if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode())) { |
103 |
2084 |
if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode())) { |
103 |
| 2085 |
SDValue N0 = N->getOperand(0); |
0 |
2085 |
SDValue N0 = N->getOperand(0); |
0 |
| 2086 |
SDValue N1 = N->getOperand(1); |
0 |
2086 |
SDValue N1 = N->getOperand(1); |
0 |
| 2087 |
|
--- |
2087 |
|
--- |
| 2088 |
// Constant operands are canonicalized to RHS. |
--- |
2088 |
// Constant operands are canonicalized to RHS. |
--- |
| 2089 |
if (N0 != N1 && (isa(N0) || !isa(N1))) { |
0 |
2089 |
if (N0 != N1 && (isa(N0) || !isa(N1))) { |
0 |
| 2090 |
SDValue Ops[] = {N1, N0}; |
0 |
2090 |
SDValue Ops[] = {N1, N0}; |
0 |
| 2091 |
SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops, |
0 |
2091 |
SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops, |
0 |
| 2092 |
N->getFlags()); |
--- |
2092 |
N->getFlags()); |
--- |
| 2093 |
if (CSENode) |
0 |
2093 |
if (CSENode) |
0 |
| 2094 |
return SDValue(CSENode, 0); |
0 |
2094 |
return SDValue(CSENode, 0); |
0 |
| 2095 |
} |
--- |
2095 |
} |
--- |
| 2096 |
} |
--- |
2096 |
} |
--- |
| 2097 |
|
--- |
2097 |
|
--- |
| 2098 |
return RV; |
103 |
2098 |
return RV; |
103 |
| 2099 |
} |
--- |
2099 |
} |
--- |
| 2100 |
|
--- |
2100 |
|
--- |
| 2101 |
/// Given a node, return its input chain if it has one, otherwise return a null |
--- |
2101 |
/// Given a node, return its input chain if it has one, otherwise return a null |
--- |
| 2102 |
/// sd operand. |
--- |
2102 |
/// sd operand. |
--- |
| 2103 |
static SDValue getInputChainForNode(SDNode *N) { |
0 |
2103 |
static SDValue getInputChainForNode(SDNode *N) { |
0 |
| 2104 |
if (unsigned NumOps = N->getNumOperands()) { |
0 |
2104 |
if (unsigned NumOps = N->getNumOperands()) { |
0 |
| 2105 |
if (N->getOperand(0).getValueType() == MVT::Other) |
0 |
2105 |
if (N->getOperand(0).getValueType() == MVT::Other) |
0 |
| 2106 |
return N->getOperand(0); |
0 |
2106 |
return N->getOperand(0); |
0 |
| 2107 |
if (N->getOperand(NumOps-1).getValueType() == MVT::Other) |
0 |
2107 |
if (N->getOperand(NumOps-1).getValueType() == MVT::Other) |
0 |
| 2108 |
return N->getOperand(NumOps-1); |
0 |
2108 |
return N->getOperand(NumOps-1); |
0 |
| 2109 |
for (unsigned i = 1; i < NumOps-1; ++i) |
0 |
2109 |
for (unsigned i = 1; i < NumOps-1; ++i) |
0 |
| 2110 |
if (N->getOperand(i).getValueType() == MVT::Other) |
0 |
2110 |
if (N->getOperand(i).getValueType() == MVT::Other) |
0 |
| 2111 |
return N->getOperand(i); |
0 |
2111 |
return N->getOperand(i); |
0 |
| 2112 |
} |
--- |
2112 |
} |
--- |
| 2113 |
return SDValue(); |
0 |
2113 |
return SDValue(); |
0 |
| 2114 |
} |
--- |
2114 |
} |
--- |
| 2115 |
|
--- |
2115 |
|
--- |
| 2116 |
SDValue DAGCombiner::visitTokenFactor(SDNode *N) { |
0 |
2116 |
SDValue DAGCombiner::visitTokenFactor(SDNode *N) { |
0 |
| 2117 |
// If N has two operands, where one has an input chain equal to the other, |
--- |
2117 |
// If N has two operands, where one has an input chain equal to the other, |
--- |
| 2118 |
// the 'other' chain is redundant. |
--- |
2118 |
// the 'other' chain is redundant. |
--- |
| 2119 |
if (N->getNumOperands() == 2) { |
0 |
2119 |
if (N->getNumOperands() == 2) { |
0 |
| 2120 |
if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) |
0 |
2120 |
if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) |
0 |
| 2121 |
return N->getOperand(0); |
0 |
2121 |
return N->getOperand(0); |
0 |
| 2122 |
if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) |
0 |
2122 |
if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) |
0 |
| 2123 |
return N->getOperand(1); |
0 |
2123 |
return N->getOperand(1); |
0 |
| 2124 |
} |
--- |
2124 |
} |
--- |
| 2125 |
|
--- |
2125 |
|
--- |
| 2126 |
// Don't simplify token factors if optnone. |
--- |
2126 |
// Don't simplify token factors if optnone. |
--- |
| 2127 |
if (OptLevel == CodeGenOpt::None) |
0 |
2127 |
if (OptLevel == CodeGenOpt::None) |
0 |
| 2128 |
return SDValue(); |
0 |
2128 |
return SDValue(); |
0 |
| 2129 |
|
--- |
2129 |
|
--- |
| 2130 |
// Don't simplify the token factor if the node itself has too many operands. |
--- |
2130 |
// Don't simplify the token factor if the node itself has too many operands. |
--- |
| 2131 |
if (N->getNumOperands() > TokenFactorInlineLimit) |
0 |
2131 |
if (N->getNumOperands() > TokenFactorInlineLimit) |
0 |
| 2132 |
return SDValue(); |
0 |
2132 |
return SDValue(); |
0 |
| 2133 |
|
--- |
2133 |
|
--- |
| 2134 |
// If the sole user is a token factor, we should make sure we have a |
--- |
2134 |
// If the sole user is a token factor, we should make sure we have a |
--- |
| 2135 |
// chance to merge them together. This prevents TF chains from inhibiting |
--- |
2135 |
// chance to merge them together. This prevents TF chains from inhibiting |
--- |
| 2136 |
// optimizations. |
--- |
2136 |
// optimizations. |
--- |
| 2137 |
if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor) |
0 |
2137 |
if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor) |
0 |
| 2138 |
AddToWorklist(*(N->use_begin())); |
0 |
2138 |
AddToWorklist(*(N->use_begin())); |
0 |
| 2139 |
|
--- |
2139 |
|
--- |
| 2140 |
SmallVector TFs; // List of token factors to visit. |
0 |
2140 |
SmallVector TFs; // List of token factors to visit. |
0 |
| 2141 |
SmallVector Ops; // Ops for replacing token factor. |
0 |
2141 |
SmallVector Ops; // Ops for replacing token factor. |
0 |
| 2142 |
SmallPtrSet SeenOps; |
0 |
2142 |
SmallPtrSet SeenOps; |
0 |
| 2143 |
bool Changed = false; // If we should replace this token factor. |
0 |
2143 |
bool Changed = false; // If we should replace this token factor. |
0 |
| 2144 |
|
--- |
2144 |
|
--- |
| 2145 |
// Start out with this token factor. |
--- |
2145 |
// Start out with this token factor. |
--- |
| 2146 |
TFs.push_back(N); |
0 |
2146 |
TFs.push_back(N); |
0 |
| 2147 |
|
--- |
2147 |
|
--- |
| 2148 |
// Iterate through token factors. The TFs grows when new token factors are |
--- |
2148 |
// Iterate through token factors. The TFs grows when new token factors are |
--- |
| 2149 |
// encountered. |
--- |
2149 |
// encountered. |
--- |
| 2150 |
for (unsigned i = 0; i < TFs.size(); ++i) { |
0 |
2150 |
for (unsigned i = 0; i < TFs.size(); ++i) { |
0 |
| 2151 |
// Limit number of nodes to inline, to avoid quadratic compile times. |
--- |
2151 |
// Limit number of nodes to inline, to avoid quadratic compile times. |
--- |
| 2152 |
// We have to add the outstanding Token Factors to Ops, otherwise we might |
--- |
2152 |
// We have to add the outstanding Token Factors to Ops, otherwise we might |
--- |
| 2153 |
// drop Ops from the resulting Token Factors. |
--- |
2153 |
// drop Ops from the resulting Token Factors. |
--- |
| 2154 |
if (Ops.size() > TokenFactorInlineLimit) { |
0 |
2154 |
if (Ops.size() > TokenFactorInlineLimit) { |
0 |
| 2155 |
for (unsigned j = i; j < TFs.size(); j++) |
0 |
2155 |
for (unsigned j = i; j < TFs.size(); j++) |
0 |
| 2156 |
Ops.emplace_back(TFs[j], 0); |
0 |
2156 |
Ops.emplace_back(TFs[j], 0); |
0 |
| 2157 |
// Drop unprocessed Token Factors from TFs, so we do not add them to the |
--- |
2157 |
// Drop unprocessed Token Factors from TFs, so we do not add them to the |
--- |
| 2158 |
// combiner worklist later. |
--- |
2158 |
// combiner worklist later. |
--- |
| 2159 |
TFs.resize(i); |
0 |
2159 |
TFs.resize(i); |
0 |
| 2160 |
break; |
0 |
2160 |
break; |
0 |
| 2161 |
} |
--- |
2161 |
} |
--- |
| 2162 |
|
--- |
2162 |
|
--- |
| 2163 |
SDNode *TF = TFs[i]; |
0 |
2163 |
SDNode *TF = TFs[i]; |
0 |
| 2164 |
// Check each of the operands. |
--- |
2164 |
// Check each of the operands. |
--- |
| 2165 |
for (const SDValue &Op : TF->op_values()) { |
0 |
2165 |
for (const SDValue &Op : TF->op_values()) { |
0 |
| 2166 |
switch (Op.getOpcode()) { |
0 |
2166 |
switch (Op.getOpcode()) { |
0 |
| 2167 |
case ISD::EntryToken: |
0 |
2167 |
case ISD::EntryToken: |
0 |
| 2168 |
// Entry tokens don't need to be added to the list. They are |
--- |
2168 |
// Entry tokens don't need to be added to the list. They are |
--- |
| 2169 |
// redundant. |
--- |
2169 |
// redundant. |
--- |
| 2170 |
Changed = true; |
0 |
2170 |
Changed = true; |
0 |
| 2171 |
break; |
0 |
2171 |
break; |
0 |
| 2172 |
|
--- |
2172 |
|
--- |
| 2173 |
case ISD::TokenFactor: |
0 |
2173 |
case ISD::TokenFactor: |
0 |
| 2174 |
if (Op.hasOneUse() && !is_contained(TFs, Op.getNode())) { |
0 |
2174 |
if (Op.hasOneUse() && !is_contained(TFs, Op.getNode())) { |
0 |
| 2175 |
// Queue up for processing. |
--- |
2175 |
// Queue up for processing. |
--- |
| 2176 |
TFs.push_back(Op.getNode()); |
0 |
2176 |
TFs.push_back(Op.getNode()); |
0 |
| 2177 |
Changed = true; |
0 |
2177 |
Changed = true; |
0 |
| 2178 |
break; |
0 |
2178 |
break; |
0 |
| 2179 |
} |
--- |
2179 |
} |
--- |
| 2180 |
[[fallthrough]]; |
--- |
2180 |
[[fallthrough]]; |
--- |
| 2181 |
|
--- |
2181 |
|
--- |
| 2182 |
default: |
--- |
2182 |
default: |
--- |
| 2183 |
// Only add if it isn't already in the list. |
--- |
2183 |
// Only add if it isn't already in the list. |
--- |
| 2184 |
if (SeenOps.insert(Op.getNode()).second) |
0 |
2184 |
if (SeenOps.insert(Op.getNode()).second) |
0 |
| 2185 |
Ops.push_back(Op); |
0 |
2185 |
Ops.push_back(Op); |
0 |
| 2186 |
else |
--- |
2186 |
else |
--- |
| 2187 |
Changed = true; |
0 |
2187 |
Changed = true; |
0 |
| 2188 |
break; |
0 |
2188 |
break; |
0 |
| 2189 |
} |
--- |
2189 |
} |
--- |
| 2190 |
} |
--- |
2190 |
} |
--- |
| 2191 |
} |
--- |
2191 |
} |
--- |
| 2192 |
|
--- |
2192 |
|
--- |
| 2193 |
// Re-visit inlined Token Factors, to clean them up in case they have been |
--- |
2193 |
// Re-visit inlined Token Factors, to clean them up in case they have been |
--- |
| 2194 |
// removed. Skip the first Token Factor, as this is the current node. |
--- |
2194 |
// removed. Skip the first Token Factor, as this is the current node. |
--- |
| 2195 |
for (unsigned i = 1, e = TFs.size(); i < e; i++) |
0 |
2195 |
for (unsigned i = 1, e = TFs.size(); i < e; i++) |
0 |
| 2196 |
AddToWorklist(TFs[i]); |
0 |
2196 |
AddToWorklist(TFs[i]); |
0 |
| 2197 |
|
--- |
2197 |
|
--- |
| 2198 |
// Remove Nodes that are chained to another node in the list. Do so |
--- |
2198 |
// Remove Nodes that are chained to another node in the list. Do so |
--- |
| 2199 |
// by walking up chains breath-first stopping when we've seen |
--- |
2199 |
// by walking up chains breath-first stopping when we've seen |
--- |
| 2200 |
// another operand. In general we must climb to the EntryNode, but we can exit |
--- |
2200 |
// another operand. In general we must climb to the EntryNode, but we can exit |
--- |
| 2201 |
// early if we find all remaining work is associated with just one operand as |
--- |
2201 |
// early if we find all remaining work is associated with just one operand as |
--- |
| 2202 |
// no further pruning is possible. |
--- |
2202 |
// no further pruning is possible. |
--- |
| 2203 |
|
--- |
2203 |
|
--- |
| 2204 |
// List of nodes to search through and original Ops from which they originate. |
--- |
2204 |
// List of nodes to search through and original Ops from which they originate. |
--- |
| 2205 |
SmallVector, 8> Worklist; |
0 |
2205 |
SmallVector, 8> Worklist; |
0 |
| 2206 |
SmallVector OpWorkCount; // Count of work for each Op. |
0 |
2206 |
SmallVector OpWorkCount; // Count of work for each Op. |
0 |
| 2207 |
SmallPtrSet SeenChains; |
0 |
2207 |
SmallPtrSet SeenChains; |
0 |
| 2208 |
bool DidPruneOps = false; |
0 |
2208 |
bool DidPruneOps = false; |
0 |
| 2209 |
|
--- |
2209 |
|
--- |
| 2210 |
unsigned NumLeftToConsider = 0; |
0 |
2210 |
unsigned NumLeftToConsider = 0; |
0 |
| 2211 |
for (const SDValue &Op : Ops) { |
0 |
2211 |
for (const SDValue &Op : Ops) { |
0 |
| 2212 |
Worklist.push_back(std::make_pair(Op.getNode(), NumLeftToConsider++)); |
0 |
2212 |
Worklist.push_back(std::make_pair(Op.getNode(), NumLeftToConsider++)); |
0 |
| 2213 |
OpWorkCount.push_back(1); |
0 |
2213 |
OpWorkCount.push_back(1); |
0 |
| 2214 |
} |
--- |
2214 |
} |
--- |
| 2215 |
|
--- |
2215 |
|
--- |
| 2216 |
auto AddToWorklist = [&](unsigned CurIdx, SDNode *Op, unsigned OpNumber) { |
0 |
2216 |
auto AddToWorklist = [&](unsigned CurIdx, SDNode *Op, unsigned OpNumber) { |
0 |
| 2217 |
// If this is an Op, we can remove the op from the list. Remark any |
--- |
2217 |
// If this is an Op, we can remove the op from the list. Remark any |
--- |
| 2218 |
// search associated with it as from the current OpNumber. |
--- |
2218 |
// search associated with it as from the current OpNumber. |
--- |
| 2219 |
if (SeenOps.contains(Op)) { |
0 |
2219 |
if (SeenOps.contains(Op)) { |
0 |
| 2220 |
Changed = true; |
0 |
2220 |
Changed = true; |
0 |
| 2221 |
DidPruneOps = true; |
0 |
2221 |
DidPruneOps = true; |
0 |
| 2222 |
unsigned OrigOpNumber = 0; |
0 |
2222 |
unsigned OrigOpNumber = 0; |
0 |
| 2223 |
while (OrigOpNumber < Ops.size() && Ops[OrigOpNumber].getNode() != Op) |
0 |
2223 |
while (OrigOpNumber < Ops.size() && Ops[OrigOpNumber].getNode() != Op) |
0 |
| 2224 |
OrigOpNumber++; |
0 |
2224 |
OrigOpNumber++; |
0 |
| 2225 |
assert((OrigOpNumber != Ops.size()) && |
0 |
2225 |
assert((OrigOpNumber != Ops.size()) && |
0 |
| 2226 |
"expected to find TokenFactor Operand"); |
--- |
2226 |
"expected to find TokenFactor Operand"); |
--- |
| 2227 |
// Re-mark worklist from OrigOpNumber to OpNumber |
--- |
2227 |
// Re-mark worklist from OrigOpNumber to OpNumber |
--- |
| 2228 |
for (unsigned i = CurIdx + 1; i < Worklist.size(); ++i) { |
0 |
2228 |
for (unsigned i = CurIdx + 1; i < Worklist.size(); ++i) { |
0 |
| 2229 |
if (Worklist[i].second == OrigOpNumber) { |
0 |
2229 |
if (Worklist[i].second == OrigOpNumber) { |
0 |
| 2230 |
Worklist[i].second = OpNumber; |
0 |
2230 |
Worklist[i].second = OpNumber; |
0 |
| 2231 |
} |
--- |
2231 |
} |
--- |
| 2232 |
} |
--- |
2232 |
} |
--- |
| 2233 |
OpWorkCount[OpNumber] += OpWorkCount[OrigOpNumber]; |
0 |
2233 |
OpWorkCount[OpNumber] += OpWorkCount[OrigOpNumber]; |
0 |
| 2234 |
OpWorkCount[OrigOpNumber] = 0; |
0 |
2234 |
OpWorkCount[OrigOpNumber] = 0; |
0 |
| 2235 |
NumLeftToConsider--; |
0 |
2235 |
NumLeftToConsider--; |
0 |
| 2236 |
} |
--- |
2236 |
} |
--- |
| 2237 |
// Add if it's a new chain |
--- |
2237 |
// Add if it's a new chain |
--- |
| 2238 |
if (SeenChains.insert(Op).second) { |
0 |
2238 |
if (SeenChains.insert(Op).second) { |
0 |
| 2239 |
OpWorkCount[OpNumber]++; |
0 |
2239 |
OpWorkCount[OpNumber]++; |
0 |
| 2240 |
Worklist.push_back(std::make_pair(Op, OpNumber)); |
0 |
2240 |
Worklist.push_back(std::make_pair(Op, OpNumber)); |
0 |
| 2241 |
} |
--- |
2241 |
} |
--- |
| 2242 |
}; |
0 |
2242 |
}; |
0 |
| 2243 |
|
--- |
2243 |
|
--- |
| 2244 |
for (unsigned i = 0; i < Worklist.size() && i < 1024; ++i) { |
0 |
2244 |
for (unsigned i = 0; i < Worklist.size() && i < 1024; ++i) { |
0 |
| 2245 |
// We need at least be consider at least 2 Ops to prune. |
--- |
2245 |
// We need at least be consider at least 2 Ops to prune. |
--- |
| 2246 |
if (NumLeftToConsider <= 1) |
0 |
2246 |
if (NumLeftToConsider <= 1) |
0 |
| 2247 |
break; |
0 |
2247 |
break; |
0 |
| 2248 |
auto CurNode = Worklist[i].first; |
0 |
2248 |
auto CurNode = Worklist[i].first; |
0 |
| 2249 |
auto CurOpNumber = Worklist[i].second; |
0 |
2249 |
auto CurOpNumber = Worklist[i].second; |
0 |
| 2250 |
assert((OpWorkCount[CurOpNumber] > 0) && |
0 |
2250 |
assert((OpWorkCount[CurOpNumber] > 0) && |
0 |
| 2251 |
"Node should not appear in worklist"); |
--- |
2251 |
"Node should not appear in worklist"); |
--- |
| 2252 |
switch (CurNode->getOpcode()) { |
0 |
2252 |
switch (CurNode->getOpcode()) { |
0 |
| 2253 |
case ISD::EntryToken: |
0 |
2253 |
case ISD::EntryToken: |
0 |
| 2254 |
// Hitting EntryToken is the only way for the search to terminate without |
--- |
2254 |
// Hitting EntryToken is the only way for the search to terminate without |
--- |
| 2255 |
// hitting |
--- |
2255 |
// hitting |
--- |
| 2256 |
// another operand's search. Prevent us from marking this operand |
--- |
2256 |
// another operand's search. Prevent us from marking this operand |
--- |
| 2257 |
// considered. |
--- |
2257 |
// considered. |
--- |
| 2258 |
NumLeftToConsider++; |
0 |
2258 |
NumLeftToConsider++; |
0 |
| 2259 |
break; |
0 |
2259 |
break; |
0 |
| 2260 |
case ISD::TokenFactor: |
0 |
2260 |
case ISD::TokenFactor: |
0 |
| 2261 |
for (const SDValue &Op : CurNode->op_values()) |
0 |
2261 |
for (const SDValue &Op : CurNode->op_values()) |
0 |
| 2262 |
AddToWorklist(i, Op.getNode(), CurOpNumber); |
0 |
2262 |
AddToWorklist(i, Op.getNode(), CurOpNumber); |
0 |
| 2263 |
break; |
0 |
2263 |
break; |
0 |
| 2264 |
case ISD::LIFETIME_START: |
0 |
2264 |
case ISD::LIFETIME_START: |
0 |
| 2265 |
case ISD::LIFETIME_END: |
--- |
2265 |
case ISD::LIFETIME_END: |
--- |
| 2266 |
case ISD::CopyFromReg: |
--- |
2266 |
case ISD::CopyFromReg: |
--- |
| 2267 |
case ISD::CopyToReg: |
--- |
2267 |
case ISD::CopyToReg: |
--- |
| 2268 |
AddToWorklist(i, CurNode->getOperand(0).getNode(), CurOpNumber); |
0 |
2268 |
AddToWorklist(i, CurNode->getOperand(0).getNode(), CurOpNumber); |
0 |
| 2269 |
break; |
0 |
2269 |
break; |
0 |
| 2270 |
default: |
0 |
2270 |
default: |
0 |
| 2271 |
if (auto *MemNode = dyn_cast(CurNode)) |
0 |
2271 |
if (auto *MemNode = dyn_cast(CurNode)) |
0 |
| 2272 |
AddToWorklist(i, MemNode->getChain().getNode(), CurOpNumber); |
0 |
2272 |
AddToWorklist(i, MemNode->getChain().getNode(), CurOpNumber); |
0 |
| 2273 |
break; |
0 |
2273 |
break; |
0 |
| 2274 |
} |
--- |
2274 |
} |
--- |
| 2275 |
OpWorkCount[CurOpNumber]--; |
0 |
2275 |
OpWorkCount[CurOpNumber]--; |
0 |
| 2276 |
if (OpWorkCount[CurOpNumber] == 0) |
0 |
2276 |
if (OpWorkCount[CurOpNumber] == 0) |
0 |
| 2277 |
NumLeftToConsider--; |
0 |
2277 |
NumLeftToConsider--; |
0 |
| 2278 |
} |
--- |
2278 |
} |
--- |
| 2279 |
|
--- |
2279 |
|
--- |
| 2280 |
// If we've changed things around then replace token factor. |
--- |
2280 |
// If we've changed things around then replace token factor. |
--- |
| 2281 |
if (Changed) { |
0 |
2281 |
if (Changed) { |
0 |
| 2282 |
SDValue Result; |
0 |
2282 |
SDValue Result; |
0 |
| 2283 |
if (Ops.empty()) { |
0 |
2283 |
if (Ops.empty()) { |
0 |
| 2284 |
// The entry token is the only possible outcome. |
--- |
2284 |
// The entry token is the only possible outcome. |
--- |
| 2285 |
Result = DAG.getEntryNode(); |
0 |
2285 |
Result = DAG.getEntryNode(); |
0 |
| 2286 |
} else { |
--- |
2286 |
} else { |
--- |
| 2287 |
if (DidPruneOps) { |
0 |
2287 |
if (DidPruneOps) { |
0 |
| 2288 |
SmallVector PrunedOps; |
0 |
2288 |
SmallVector PrunedOps; |
0 |
| 2289 |
// |
--- |
2289 |
// |
--- |
| 2290 |
for (const SDValue &Op : Ops) { |
0 |
2290 |
for (const SDValue &Op : Ops) { |
0 |
| 2291 |
if (SeenChains.count(Op.getNode()) == 0) |
0 |
2291 |
if (SeenChains.count(Op.getNode()) == 0) |
0 |
| 2292 |
PrunedOps.push_back(Op); |
0 |
2292 |
PrunedOps.push_back(Op); |
0 |
| 2293 |
} |
--- |
2293 |
} |
--- |
| 2294 |
Result = DAG.getTokenFactor(SDLoc(N), PrunedOps); |
0 |
2294 |
Result = DAG.getTokenFactor(SDLoc(N), PrunedOps); |
0 |
| 2295 |
} else { |
0 |
2295 |
} else { |
0 |
| 2296 |
Result = DAG.getTokenFactor(SDLoc(N), Ops); |
0 |
2296 |
Result = DAG.getTokenFactor(SDLoc(N), Ops); |
0 |
| 2297 |
} |
--- |
2297 |
} |
--- |
| 2298 |
} |
--- |
2298 |
} |
--- |
| 2299 |
return Result; |
0 |
2299 |
return Result; |
0 |
| 2300 |
} |
--- |
2300 |
} |
--- |
| 2301 |
return SDValue(); |
0 |
2301 |
return SDValue(); |
0 |
| 2302 |
} |
0 |
2302 |
} |
0 |
| 2303 |
|
--- |
2303 |
|
--- |
| 2304 |
/// MERGE_VALUES can always be eliminated. |
--- |
2304 |
/// MERGE_VALUES can always be eliminated. |
--- |
| 2305 |
SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { |
0 |
2305 |
SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { |
0 |
| 2306 |
WorklistRemover DeadNodes(*this); |
0 |
2306 |
WorklistRemover DeadNodes(*this); |
0 |
| 2307 |
// Replacing results may cause a different MERGE_VALUES to suddenly |
--- |
2307 |
// Replacing results may cause a different MERGE_VALUES to suddenly |
--- |
| 2308 |
// be CSE'd with N, and carry its uses with it. Iterate until no |
--- |
2308 |
// be CSE'd with N, and carry its uses with it. Iterate until no |
--- |
| 2309 |
// uses remain, to ensure that the node can be safely deleted. |
--- |
2309 |
// uses remain, to ensure that the node can be safely deleted. |
--- |
| 2310 |
// First add the users of this node to the work list so that they |
--- |
2310 |
// First add the users of this node to the work list so that they |
--- |
| 2311 |
// can be tried again once they have new operands. |
--- |
2311 |
// can be tried again once they have new operands. |
--- |
| 2312 |
AddUsersToWorklist(N); |
0 |
2312 |
AddUsersToWorklist(N); |
0 |
| 2313 |
do { |
--- |
2313 |
do { |
--- |
| 2314 |
// Do as a single replacement to avoid rewalking use lists. |
--- |
2314 |
// Do as a single replacement to avoid rewalking use lists. |
--- |
| 2315 |
SmallVector Ops; |
0 |
2315 |
SmallVector Ops; |
0 |
| 2316 |
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) |
0 |
2316 |
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) |
0 |
| 2317 |
Ops.push_back(N->getOperand(i)); |
0 |
2317 |
Ops.push_back(N->getOperand(i)); |
0 |
| 2318 |
DAG.ReplaceAllUsesWith(N, Ops.data()); |
0 |
2318 |
DAG.ReplaceAllUsesWith(N, Ops.data()); |
0 |
| 2319 |
} while (!N->use_empty()); |
0 |
2319 |
} while (!N->use_empty()); |
0 |
| 2320 |
deleteAndRecombine(N); |
0 |
2320 |
deleteAndRecombine(N); |
0 |
| 2321 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
2321 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 2322 |
} |
0 |
2322 |
} |
0 |
| 2323 |
|
--- |
2323 |
|
--- |
| 2324 |
/// If \p N is a ConstantSDNode with isOpaque() == false return it casted to a |
--- |
2324 |
/// If \p N is a ConstantSDNode with isOpaque() == false return it casted to a |
--- |
| 2325 |
/// ConstantSDNode pointer else nullptr. |
--- |
2325 |
/// ConstantSDNode pointer else nullptr. |
--- |
| 2326 |
static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) { |
0 |
2326 |
static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) { |
0 |
| 2327 |
ConstantSDNode *Const = dyn_cast(N); |
0 |
2327 |
ConstantSDNode *Const = dyn_cast(N); |
0 |
| 2328 |
return Const != nullptr && !Const->isOpaque() ? Const : nullptr; |
0 |
2328 |
return Const != nullptr && !Const->isOpaque() ? Const : nullptr; |
0 |
| 2329 |
} |
--- |
2329 |
} |
--- |
| 2330 |
|
--- |
2330 |
|
--- |
| 2331 |
// isTruncateOf - If N is a truncate of some other value, return true, record |
--- |
2331 |
// isTruncateOf - If N is a truncate of some other value, return true, record |
--- |
| 2332 |
// the value being truncated in Op and which of Op's bits are zero/one in Known. |
--- |
2332 |
// the value being truncated in Op and which of Op's bits are zero/one in Known. |
--- |
| 2333 |
// This function computes KnownBits to avoid a duplicated call to |
--- |
2333 |
// This function computes KnownBits to avoid a duplicated call to |
--- |
| 2334 |
// computeKnownBits in the caller. |
--- |
2334 |
// computeKnownBits in the caller. |
--- |
| 2335 |
static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, |
0 |
2335 |
static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, |
0 |
| 2336 |
KnownBits &Known) { |
--- |
2336 |
KnownBits &Known) { |
--- |
| 2337 |
if (N->getOpcode() == ISD::TRUNCATE) { |
0 |
2337 |
if (N->getOpcode() == ISD::TRUNCATE) { |
0 |
| 2338 |
Op = N->getOperand(0); |
0 |
2338 |
Op = N->getOperand(0); |
0 |
| 2339 |
Known = DAG.computeKnownBits(Op); |
0 |
2339 |
Known = DAG.computeKnownBits(Op); |
0 |
| 2340 |
return true; |
0 |
2340 |
return true; |
0 |
| 2341 |
} |
--- |
2341 |
} |
--- |
| 2342 |
|
--- |
2342 |
|
--- |
| 2343 |
if (N.getOpcode() != ISD::SETCC || |
0 |
2343 |
if (N.getOpcode() != ISD::SETCC || |
0 |
| 2344 |
N.getValueType().getScalarType() != MVT::i1 || |
0 |
2344 |
N.getValueType().getScalarType() != MVT::i1 || |
0 |
| 2345 |
cast(N.getOperand(2))->get() != ISD::SETNE) |
0 |
2345 |
cast(N.getOperand(2))->get() != ISD::SETNE) |
0 |
| 2346 |
return false; |
0 |
2346 |
return false; |
0 |
| 2347 |
|
--- |
2347 |
|
--- |
| 2348 |
SDValue Op0 = N->getOperand(0); |
0 |
2348 |
SDValue Op0 = N->getOperand(0); |
0 |
| 2349 |
SDValue Op1 = N->getOperand(1); |
0 |
2349 |
SDValue Op1 = N->getOperand(1); |
0 |
| 2350 |
assert(Op0.getValueType() == Op1.getValueType()); |
0 |
2350 |
assert(Op0.getValueType() == Op1.getValueType()); |
0 |
| 2351 |
|
--- |
2351 |
|
--- |
| 2352 |
if (isNullOrNullSplat(Op0)) |
0 |
2352 |
if (isNullOrNullSplat(Op0)) |
0 |
| 2353 |
Op = Op1; |
0 |
2353 |
Op = Op1; |
0 |
| 2354 |
else if (isNullOrNullSplat(Op1)) |
0 |
2354 |
else if (isNullOrNullSplat(Op1)) |
0 |
| 2355 |
Op = Op0; |
0 |
2355 |
Op = Op0; |
0 |
| 2356 |
else |
--- |
2356 |
else |
--- |
| 2357 |
return false; |
0 |
2357 |
return false; |
0 |
| 2358 |
|
--- |
2358 |
|
--- |
| 2359 |
Known = DAG.computeKnownBits(Op); |
0 |
2359 |
Known = DAG.computeKnownBits(Op); |
0 |
| 2360 |
|
--- |
2360 |
|
--- |
| 2361 |
return (Known.Zero | 1).isAllOnes(); |
0 |
2361 |
return (Known.Zero | 1).isAllOnes(); |
0 |
| 2362 |
} |
--- |
2362 |
} |
--- |
| 2363 |
|
--- |
2363 |
|
--- |
| 2364 |
/// Return true if 'Use' is a load or a store that uses N as its base pointer |
--- |
2364 |
/// Return true if 'Use' is a load or a store that uses N as its base pointer |
--- |
| 2365 |
/// and that N may be folded in the load / store addressing mode. |
--- |
2365 |
/// and that N may be folded in the load / store addressing mode. |
--- |
| 2366 |
static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, SelectionDAG &DAG, |
0 |
2366 |
static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, SelectionDAG &DAG, |
0 |
| 2367 |
const TargetLowering &TLI) { |
--- |
2367 |
const TargetLowering &TLI) { |
--- |
| 2368 |
EVT VT; |
0 |
2368 |
EVT VT; |
0 |
| 2369 |
unsigned AS; |
--- |
2369 |
unsigned AS; |
--- |
| 2370 |
|
--- |
2370 |
|
--- |
| 2371 |
if (LoadSDNode *LD = dyn_cast(Use)) { |
0 |
2371 |
if (LoadSDNode *LD = dyn_cast(Use)) { |
0 |
| 2372 |
if (LD->isIndexed() || LD->getBasePtr().getNode() != N) |
0 |
2372 |
if (LD->isIndexed() || LD->getBasePtr().getNode() != N) |
0 |
| 2373 |
return false; |
0 |
2373 |
return false; |
0 |
| 2374 |
VT = LD->getMemoryVT(); |
0 |
2374 |
VT = LD->getMemoryVT(); |
0 |
| 2375 |
AS = LD->getAddressSpace(); |
0 |
2375 |
AS = LD->getAddressSpace(); |
0 |
| 2376 |
} else if (StoreSDNode *ST = dyn_cast(Use)) { |
0 |
2376 |
} else if (StoreSDNode *ST = dyn_cast(Use)) { |
0 |
| 2377 |
if (ST->isIndexed() || ST->getBasePtr().getNode() != N) |
0 |
2377 |
if (ST->isIndexed() || ST->getBasePtr().getNode() != N) |
0 |
| 2378 |
return false; |
0 |
2378 |
return false; |
0 |
| 2379 |
VT = ST->getMemoryVT(); |
0 |
2379 |
VT = ST->getMemoryVT(); |
0 |
| 2380 |
AS = ST->getAddressSpace(); |
0 |
2380 |
AS = ST->getAddressSpace(); |
0 |
| 2381 |
} else if (MaskedLoadSDNode *LD = dyn_cast(Use)) { |
0 |
2381 |
} else if (MaskedLoadSDNode *LD = dyn_cast(Use)) { |
0 |
| 2382 |
if (LD->isIndexed() || LD->getBasePtr().getNode() != N) |
0 |
2382 |
if (LD->isIndexed() || LD->getBasePtr().getNode() != N) |
0 |
| 2383 |
return false; |
0 |
2383 |
return false; |
0 |
| 2384 |
VT = LD->getMemoryVT(); |
0 |
2384 |
VT = LD->getMemoryVT(); |
0 |
| 2385 |
AS = LD->getAddressSpace(); |
0 |
2385 |
AS = LD->getAddressSpace(); |
0 |
| 2386 |
} else if (MaskedStoreSDNode *ST = dyn_cast(Use)) { |
0 |
2386 |
} else if (MaskedStoreSDNode *ST = dyn_cast(Use)) { |
0 |
| 2387 |
if (ST->isIndexed() || ST->getBasePtr().getNode() != N) |
0 |
2387 |
if (ST->isIndexed() || ST->getBasePtr().getNode() != N) |
0 |
| 2388 |
return false; |
0 |
2388 |
return false; |
0 |
| 2389 |
VT = ST->getMemoryVT(); |
0 |
2389 |
VT = ST->getMemoryVT(); |
0 |
| 2390 |
AS = ST->getAddressSpace(); |
0 |
2390 |
AS = ST->getAddressSpace(); |
0 |
| 2391 |
} else { |
--- |
2391 |
} else { |
--- |
| 2392 |
return false; |
0 |
2392 |
return false; |
0 |
| 2393 |
} |
--- |
2393 |
} |
--- |
| 2394 |
|
--- |
2394 |
|
--- |
| 2395 |
TargetLowering::AddrMode AM; |
0 |
2395 |
TargetLowering::AddrMode AM; |
0 |
| 2396 |
if (N->getOpcode() == ISD::ADD) { |
0 |
2396 |
if (N->getOpcode() == ISD::ADD) { |
0 |
| 2397 |
AM.HasBaseReg = true; |
0 |
2397 |
AM.HasBaseReg = true; |
0 |
| 2398 |
ConstantSDNode *Offset = dyn_cast(N->getOperand(1)); |
0 |
2398 |
ConstantSDNode *Offset = dyn_cast(N->getOperand(1)); |
0 |
| 2399 |
if (Offset) |
0 |
2399 |
if (Offset) |
0 |
| 2400 |
// [reg +/- imm] |
--- |
2400 |
// [reg +/- imm] |
--- |
| 2401 |
AM.BaseOffs = Offset->getSExtValue(); |
0 |
2401 |
AM.BaseOffs = Offset->getSExtValue(); |
0 |
| 2402 |
else |
--- |
2402 |
else |
--- |
| 2403 |
// [reg +/- reg] |
--- |
2403 |
// [reg +/- reg] |
--- |
| 2404 |
AM.Scale = 1; |
0 |
2404 |
AM.Scale = 1; |
0 |
| 2405 |
} else if (N->getOpcode() == ISD::SUB) { |
0 |
2405 |
} else if (N->getOpcode() == ISD::SUB) { |
0 |
| 2406 |
AM.HasBaseReg = true; |
0 |
2406 |
AM.HasBaseReg = true; |
0 |
| 2407 |
ConstantSDNode *Offset = dyn_cast(N->getOperand(1)); |
0 |
2407 |
ConstantSDNode *Offset = dyn_cast(N->getOperand(1)); |
0 |
| 2408 |
if (Offset) |
0 |
2408 |
if (Offset) |
0 |
| 2409 |
// [reg +/- imm] |
--- |
2409 |
// [reg +/- imm] |
--- |
| 2410 |
AM.BaseOffs = -Offset->getSExtValue(); |
0 |
2410 |
AM.BaseOffs = -Offset->getSExtValue(); |
0 |
| 2411 |
else |
--- |
2411 |
else |
--- |
| 2412 |
// [reg +/- reg] |
--- |
2412 |
// [reg +/- reg] |
--- |
| 2413 |
AM.Scale = 1; |
0 |
2413 |
AM.Scale = 1; |
0 |
| 2414 |
} else { |
--- |
2414 |
} else { |
--- |
| 2415 |
return false; |
0 |
2415 |
return false; |
0 |
| 2416 |
} |
--- |
2416 |
} |
--- |
| 2417 |
|
--- |
2417 |
|
--- |
| 2418 |
return TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, |
0 |
2418 |
return TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, |
0 |
| 2419 |
VT.getTypeForEVT(*DAG.getContext()), AS); |
0 |
2419 |
VT.getTypeForEVT(*DAG.getContext()), AS); |
0 |
| 2420 |
} |
--- |
2420 |
} |
--- |
| 2421 |
|
--- |
2421 |
|
--- |
| 2422 |
/// This inverts a canonicalization in IR that replaces a variable select arm |
--- |
2422 |
/// This inverts a canonicalization in IR that replaces a variable select arm |
--- |
| 2423 |
/// with an identity constant. Codegen improves if we re-use the variable |
--- |
2423 |
/// with an identity constant. Codegen improves if we re-use the variable |
--- |
| 2424 |
/// operand rather than load a constant. This can also be converted into a |
--- |
2424 |
/// operand rather than load a constant. This can also be converted into a |
--- |
| 2425 |
/// masked vector operation if the target supports it. |
--- |
2425 |
/// masked vector operation if the target supports it. |
--- |
| 2426 |
static SDValue foldSelectWithIdentityConstant(SDNode *N, SelectionDAG &DAG, |
0 |
2426 |
static SDValue foldSelectWithIdentityConstant(SDNode *N, SelectionDAG &DAG, |
0 |
| 2427 |
bool ShouldCommuteOperands) { |
--- |
2427 |
bool ShouldCommuteOperands) { |
--- |
| 2428 |
// Match a select as operand 1. The identity constant that we are looking for |
--- |
2428 |
// Match a select as operand 1. The identity constant that we are looking for |
--- |
| 2429 |
// is only valid as operand 1 of a non-commutative binop. |
--- |
2429 |
// is only valid as operand 1 of a non-commutative binop. |
--- |
| 2430 |
SDValue N0 = N->getOperand(0); |
0 |
2430 |
SDValue N0 = N->getOperand(0); |
0 |
| 2431 |
SDValue N1 = N->getOperand(1); |
0 |
2431 |
SDValue N1 = N->getOperand(1); |
0 |
| 2432 |
if (ShouldCommuteOperands) |
0 |
2432 |
if (ShouldCommuteOperands) |
0 |
| 2433 |
std::swap(N0, N1); |
0 |
2433 |
std::swap(N0, N1); |
0 |
| 2434 |
|
--- |
2434 |
|
--- |
| 2435 |
// TODO: Should this apply to scalar select too? |
--- |
2435 |
// TODO: Should this apply to scalar select too? |
--- |
| 2436 |
if (N1.getOpcode() != ISD::VSELECT || !N1.hasOneUse()) |
0 |
2436 |
if (N1.getOpcode() != ISD::VSELECT || !N1.hasOneUse()) |
0 |
| 2437 |
return SDValue(); |
0 |
2437 |
return SDValue(); |
0 |
| 2438 |
|
--- |
2438 |
|
--- |
| 2439 |
// We can't hoist all instructions because of immediate UB (not speculatable). |
--- |
2439 |
// We can't hoist all instructions because of immediate UB (not speculatable). |
--- |
| 2440 |
// For example div/rem by zero. |
--- |
2440 |
// For example div/rem by zero. |
--- |
| 2441 |
if (!DAG.isSafeToSpeculativelyExecuteNode(N)) |
0 |
2441 |
if (!DAG.isSafeToSpeculativelyExecuteNode(N)) |
0 |
| 2442 |
return SDValue(); |
0 |
2442 |
return SDValue(); |
0 |
| 2443 |
|
--- |
2443 |
|
--- |
| 2444 |
unsigned Opcode = N->getOpcode(); |
0 |
2444 |
unsigned Opcode = N->getOpcode(); |
0 |
| 2445 |
EVT VT = N->getValueType(0); |
0 |
2445 |
EVT VT = N->getValueType(0); |
0 |
| 2446 |
SDValue Cond = N1.getOperand(0); |
0 |
2446 |
SDValue Cond = N1.getOperand(0); |
0 |
| 2447 |
SDValue TVal = N1.getOperand(1); |
0 |
2447 |
SDValue TVal = N1.getOperand(1); |
0 |
| 2448 |
SDValue FVal = N1.getOperand(2); |
0 |
2448 |
SDValue FVal = N1.getOperand(2); |
0 |
| 2449 |
|
--- |
2449 |
|
--- |
| 2450 |
// This transform increases uses of N0, so freeze it to be safe. |
--- |
2450 |
// This transform increases uses of N0, so freeze it to be safe. |
--- |
| 2451 |
// binop N0, (vselect Cond, IDC, FVal) --> vselect Cond, N0, (binop N0, FVal) |
--- |
2451 |
// binop N0, (vselect Cond, IDC, FVal) --> vselect Cond, N0, (binop N0, FVal) |
--- |
| 2452 |
unsigned OpNo = ShouldCommuteOperands ? 0 : 1; |
0 |
2452 |
unsigned OpNo = ShouldCommuteOperands ? 0 : 1; |
0 |
| 2453 |
if (isNeutralConstant(Opcode, N->getFlags(), TVal, OpNo)) { |
0 |
2453 |
if (isNeutralConstant(Opcode, N->getFlags(), TVal, OpNo)) { |
0 |
| 2454 |
SDValue F0 = DAG.getFreeze(N0); |
0 |
2454 |
SDValue F0 = DAG.getFreeze(N0); |
0 |
| 2455 |
SDValue NewBO = DAG.getNode(Opcode, SDLoc(N), VT, F0, FVal, N->getFlags()); |
0 |
2455 |
SDValue NewBO = DAG.getNode(Opcode, SDLoc(N), VT, F0, FVal, N->getFlags()); |
0 |
| 2456 |
return DAG.getSelect(SDLoc(N), VT, Cond, F0, NewBO); |
0 |
2456 |
return DAG.getSelect(SDLoc(N), VT, Cond, F0, NewBO); |
0 |
| 2457 |
} |
--- |
2457 |
} |
--- |
| 2458 |
// binop N0, (vselect Cond, TVal, IDC) --> vselect Cond, (binop N0, TVal), N0 |
--- |
2458 |
// binop N0, (vselect Cond, TVal, IDC) --> vselect Cond, (binop N0, TVal), N0 |
--- |
| 2459 |
if (isNeutralConstant(Opcode, N->getFlags(), FVal, OpNo)) { |
0 |
2459 |
if (isNeutralConstant(Opcode, N->getFlags(), FVal, OpNo)) { |
0 |
| 2460 |
SDValue F0 = DAG.getFreeze(N0); |
0 |
2460 |
SDValue F0 = DAG.getFreeze(N0); |
0 |
| 2461 |
SDValue NewBO = DAG.getNode(Opcode, SDLoc(N), VT, F0, TVal, N->getFlags()); |
0 |
2461 |
SDValue NewBO = DAG.getNode(Opcode, SDLoc(N), VT, F0, TVal, N->getFlags()); |
0 |
| 2462 |
return DAG.getSelect(SDLoc(N), VT, Cond, NewBO, F0); |
0 |
2462 |
return DAG.getSelect(SDLoc(N), VT, Cond, NewBO, F0); |
0 |
| 2463 |
} |
--- |
2463 |
} |
--- |
| 2464 |
|
--- |
2464 |
|
--- |
| 2465 |
return SDValue(); |
0 |
2465 |
return SDValue(); |
0 |
| 2466 |
} |
--- |
2466 |
} |
--- |
| 2467 |
|
--- |
2467 |
|
--- |
| 2468 |
SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) { |
3 |
2468 |
SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) { |
3 |
| 2469 |
assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && |
3 |
2469 |
assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && |
3 |
| 2470 |
"Unexpected binary operator"); |
--- |
2470 |
"Unexpected binary operator"); |
--- |
| 2471 |
|
--- |
2471 |
|
--- |
| 2472 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
3 |
2472 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
3 |
| 2473 |
auto BinOpcode = BO->getOpcode(); |
3 |
2473 |
auto BinOpcode = BO->getOpcode(); |
3 |
| 2474 |
EVT VT = BO->getValueType(0); |
3 |
2474 |
EVT VT = BO->getValueType(0); |
3 |
| 2475 |
if (TLI.shouldFoldSelectWithIdentityConstant(BinOpcode, VT)) { |
3 |
2475 |
if (TLI.shouldFoldSelectWithIdentityConstant(BinOpcode, VT)) { |
3 |
| 2476 |
if (SDValue Sel = foldSelectWithIdentityConstant(BO, DAG, false)) |
0 |
2476 |
if (SDValue Sel = foldSelectWithIdentityConstant(BO, DAG, false)) |
0 |
| 2477 |
return Sel; |
0 |
2477 |
return Sel; |
0 |
| 2478 |
|
--- |
2478 |
|
--- |
| 2479 |
if (TLI.isCommutativeBinOp(BO->getOpcode())) |
0 |
2479 |
if (TLI.isCommutativeBinOp(BO->getOpcode())) |
0 |
| 2480 |
if (SDValue Sel = foldSelectWithIdentityConstant(BO, DAG, true)) |
0 |
2480 |
if (SDValue Sel = foldSelectWithIdentityConstant(BO, DAG, true)) |
0 |
| 2481 |
return Sel; |
0 |
2481 |
return Sel; |
0 |
| 2482 |
} |
--- |
2482 |
} |
--- |
| 2483 |
|
--- |
2483 |
|
--- |
| 2484 |
// Don't do this unless the old select is going away. We want to eliminate the |
--- |
2484 |
// Don't do this unless the old select is going away. We want to eliminate the |
--- |
| 2485 |
// binary operator, not replace a binop with a select. |
--- |
2485 |
// binary operator, not replace a binop with a select. |
--- |
| 2486 |
// TODO: Handle ISD::SELECT_CC. |
--- |
2486 |
// TODO: Handle ISD::SELECT_CC. |
--- |
| 2487 |
unsigned SelOpNo = 0; |
3 |
2487 |
unsigned SelOpNo = 0; |
3 |
| 2488 |
SDValue Sel = BO->getOperand(0); |
3 |
2488 |
SDValue Sel = BO->getOperand(0); |
3 |
| 2489 |
if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) { |
3 |
2489 |
if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) { |
3 |
| 2490 |
SelOpNo = 1; |
3 |
2490 |
SelOpNo = 1; |
3 |
| 2491 |
Sel = BO->getOperand(1); |
3 |
2491 |
Sel = BO->getOperand(1); |
3 |
| 2492 |
|
--- |
2492 |
|
--- |
| 2493 |
// Peek through trunc to shift amount type. |
--- |
2493 |
// Peek through trunc to shift amount type. |
--- |
| 2494 |
if ((BinOpcode == ISD::SHL || BinOpcode == ISD::SRA || |
3 |
2494 |
if ((BinOpcode == ISD::SHL || BinOpcode == ISD::SRA || |
3 |
| 2495 |
BinOpcode == ISD::SRL) && Sel.hasOneUse()) { |
6 |
2495 |
BinOpcode == ISD::SRL) && Sel.hasOneUse()) { |
6 |
| 2496 |
// This is valid when the truncated bits of x are already zero. |
--- |
2496 |
// This is valid when the truncated bits of x are already zero. |
--- |
| 2497 |
SDValue Op; |
0 |
2497 |
SDValue Op; |
0 |
| 2498 |
KnownBits Known; |
0 |
2498 |
KnownBits Known; |
0 |
| 2499 |
if (isTruncateOf(DAG, Sel, Op, Known) && |
0 |
2499 |
if (isTruncateOf(DAG, Sel, Op, Known) && |
0 |
| 2500 |
Known.countMaxActiveBits() < Sel.getScalarValueSizeInBits()) |
0 |
2500 |
Known.countMaxActiveBits() < Sel.getScalarValueSizeInBits()) |
0 |
| 2501 |
Sel = Op; |
0 |
2501 |
Sel = Op; |
0 |
| 2502 |
} |
0 |
2502 |
} |
0 |
| 2503 |
} |
--- |
2503 |
} |
--- |
| 2504 |
|
--- |
2504 |
|
--- |
| 2505 |
if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) |
3 |
2505 |
if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) |
3 |
| 2506 |
return SDValue(); |
3 |
2506 |
return SDValue(); |
3 |
| 2507 |
|
--- |
2507 |
|
--- |
| 2508 |
SDValue CT = Sel.getOperand(1); |
0 |
2508 |
SDValue CT = Sel.getOperand(1); |
0 |
| 2509 |
if (!isConstantOrConstantVector(CT, true) && |
0 |
2509 |
if (!isConstantOrConstantVector(CT, true) && |
0 |
| 2510 |
!DAG.isConstantFPBuildVectorOrConstantFP(CT)) |
0 |
2510 |
!DAG.isConstantFPBuildVectorOrConstantFP(CT)) |
0 |
| 2511 |
return SDValue(); |
0 |
2511 |
return SDValue(); |
0 |
| 2512 |
|
--- |
2512 |
|
--- |
| 2513 |
SDValue CF = Sel.getOperand(2); |
0 |
2513 |
SDValue CF = Sel.getOperand(2); |
0 |
| 2514 |
if (!isConstantOrConstantVector(CF, true) && |
0 |
2514 |
if (!isConstantOrConstantVector(CF, true) && |
0 |
| 2515 |
!DAG.isConstantFPBuildVectorOrConstantFP(CF)) |
0 |
2515 |
!DAG.isConstantFPBuildVectorOrConstantFP(CF)) |
0 |
| 2516 |
return SDValue(); |
0 |
2516 |
return SDValue(); |
0 |
| 2517 |
|
--- |
2517 |
|
--- |
| 2518 |
// Bail out if any constants are opaque because we can't constant fold those. |
--- |
2518 |
// Bail out if any constants are opaque because we can't constant fold those. |
--- |
| 2519 |
// The exception is "and" and "or" with either 0 or -1 in which case we can |
--- |
2519 |
// The exception is "and" and "or" with either 0 or -1 in which case we can |
--- |
| 2520 |
// propagate non constant operands into select. I.e.: |
--- |
2520 |
// propagate non constant operands into select. I.e.: |
--- |
| 2521 |
// and (select Cond, 0, -1), X --> select Cond, 0, X |
--- |
2521 |
// and (select Cond, 0, -1), X --> select Cond, 0, X |
--- |
| 2522 |
// or X, (select Cond, -1, 0) --> select Cond, -1, X |
--- |
2522 |
// or X, (select Cond, -1, 0) --> select Cond, -1, X |
--- |
| 2523 |
bool CanFoldNonConst = |
--- |
2523 |
bool CanFoldNonConst = |
--- |
| 2524 |
(BinOpcode == ISD::AND || BinOpcode == ISD::OR) && |
0 |
2524 |
(BinOpcode == ISD::AND || BinOpcode == ISD::OR) && |
0 |
| 2525 |
((isNullOrNullSplat(CT) && isAllOnesOrAllOnesSplat(CF)) || |
0 |
2525 |
((isNullOrNullSplat(CT) && isAllOnesOrAllOnesSplat(CF)) || |
0 |
| 2526 |
(isNullOrNullSplat(CF) && isAllOnesOrAllOnesSplat(CT))); |
0 |
2526 |
(isNullOrNullSplat(CF) && isAllOnesOrAllOnesSplat(CT))); |
0 |
| 2527 |
|
--- |
2527 |
|
--- |
| 2528 |
SDValue CBO = BO->getOperand(SelOpNo ^ 1); |
0 |
2528 |
SDValue CBO = BO->getOperand(SelOpNo ^ 1); |
0 |
| 2529 |
if (!CanFoldNonConst && |
0 |
2529 |
if (!CanFoldNonConst && |
0 |
| 2530 |
!isConstantOrConstantVector(CBO, true) && |
0 |
2530 |
!isConstantOrConstantVector(CBO, true) && |
0 |
| 2531 |
!DAG.isConstantFPBuildVectorOrConstantFP(CBO)) |
0 |
2531 |
!DAG.isConstantFPBuildVectorOrConstantFP(CBO)) |
0 |
| 2532 |
return SDValue(); |
0 |
2532 |
return SDValue(); |
0 |
| 2533 |
|
--- |
2533 |
|
--- |
| 2534 |
SDLoc DL(Sel); |
0 |
2534 |
SDLoc DL(Sel); |
0 |
| 2535 |
SDValue NewCT, NewCF; |
0 |
2535 |
SDValue NewCT, NewCF; |
0 |
| 2536 |
|
--- |
2536 |
|
--- |
| 2537 |
if (CanFoldNonConst) { |
0 |
2537 |
if (CanFoldNonConst) { |
0 |
| 2538 |
// If CBO is an opaque constant, we can't rely on getNode to constant fold. |
--- |
2538 |
// If CBO is an opaque constant, we can't rely on getNode to constant fold. |
--- |
| 2539 |
if ((BinOpcode == ISD::AND && isNullOrNullSplat(CT)) || |
0 |
2539 |
if ((BinOpcode == ISD::AND && isNullOrNullSplat(CT)) || |
0 |
| 2540 |
(BinOpcode == ISD::OR && isAllOnesOrAllOnesSplat(CT))) |
0 |
2540 |
(BinOpcode == ISD::OR && isAllOnesOrAllOnesSplat(CT))) |
0 |
| 2541 |
NewCT = CT; |
0 |
2541 |
NewCT = CT; |
0 |
| 2542 |
else |
--- |
2542 |
else |
--- |
| 2543 |
NewCT = CBO; |
0 |
2543 |
NewCT = CBO; |
0 |
| 2544 |
|
--- |
2544 |
|
--- |
| 2545 |
if ((BinOpcode == ISD::AND && isNullOrNullSplat(CF)) || |
0 |
2545 |
if ((BinOpcode == ISD::AND && isNullOrNullSplat(CF)) || |
0 |
| 2546 |
(BinOpcode == ISD::OR && isAllOnesOrAllOnesSplat(CF))) |
0 |
2546 |
(BinOpcode == ISD::OR && isAllOnesOrAllOnesSplat(CF))) |
0 |
| 2547 |
NewCF = CF; |
0 |
2547 |
NewCF = CF; |
0 |
| 2548 |
else |
--- |
2548 |
else |
--- |
| 2549 |
NewCF = CBO; |
0 |
2549 |
NewCF = CBO; |
0 |
| 2550 |
} else { |
--- |
2550 |
} else { |
--- |
| 2551 |
// We have a select-of-constants followed by a binary operator with a |
--- |
2551 |
// We have a select-of-constants followed by a binary operator with a |
--- |
| 2552 |
// constant. Eliminate the binop by pulling the constant math into the |
--- |
2552 |
// constant. Eliminate the binop by pulling the constant math into the |
--- |
| 2553 |
// select. Example: add (select Cond, CT, CF), CBO --> select Cond, CT + |
--- |
2553 |
// select. Example: add (select Cond, CT, CF), CBO --> select Cond, CT + |
--- |
| 2554 |
// CBO, CF + CBO |
--- |
2554 |
// CBO, CF + CBO |
--- |
| 2555 |
NewCT = SelOpNo ? DAG.FoldConstantArithmetic(BinOpcode, DL, VT, {CBO, CT}) |
0 |
2555 |
NewCT = SelOpNo ? DAG.FoldConstantArithmetic(BinOpcode, DL, VT, {CBO, CT}) |
0 |
| 2556 |
: DAG.FoldConstantArithmetic(BinOpcode, DL, VT, {CT, CBO}); |
0 |
2556 |
: DAG.FoldConstantArithmetic(BinOpcode, DL, VT, {CT, CBO}); |
0 |
| 2557 |
if (!NewCT) |
0 |
2557 |
if (!NewCT) |
0 |
| 2558 |
return SDValue(); |
0 |
2558 |
return SDValue(); |
0 |
| 2559 |
|
--- |
2559 |
|
--- |
| 2560 |
NewCF = SelOpNo ? DAG.FoldConstantArithmetic(BinOpcode, DL, VT, {CBO, CF}) |
0 |
2560 |
NewCF = SelOpNo ? DAG.FoldConstantArithmetic(BinOpcode, DL, VT, {CBO, CF}) |
0 |
| 2561 |
: DAG.FoldConstantArithmetic(BinOpcode, DL, VT, {CF, CBO}); |
0 |
2561 |
: DAG.FoldConstantArithmetic(BinOpcode, DL, VT, {CF, CBO}); |
0 |
| 2562 |
if (!NewCF) |
0 |
2562 |
if (!NewCF) |
0 |
| 2563 |
return SDValue(); |
0 |
2563 |
return SDValue(); |
0 |
| 2564 |
} |
--- |
2564 |
} |
--- |
| 2565 |
|
--- |
2565 |
|
--- |
| 2566 |
SDValue SelectOp = DAG.getSelect(DL, VT, Sel.getOperand(0), NewCT, NewCF); |
0 |
2566 |
SDValue SelectOp = DAG.getSelect(DL, VT, Sel.getOperand(0), NewCT, NewCF); |
0 |
| 2567 |
SelectOp->setFlags(BO->getFlags()); |
0 |
2567 |
SelectOp->setFlags(BO->getFlags()); |
0 |
| 2568 |
return SelectOp; |
0 |
2568 |
return SelectOp; |
0 |
| 2569 |
} |
0 |
2569 |
} |
0 |
| 2570 |
|
--- |
2570 |
|
--- |
| 2571 |
static SDValue foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) { |
0 |
2571 |
static SDValue foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) { |
0 |
| 2572 |
assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && |
0 |
2572 |
assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && |
0 |
| 2573 |
"Expecting add or sub"); |
--- |
2573 |
"Expecting add or sub"); |
--- |
| 2574 |
|
--- |
2574 |
|
--- |
| 2575 |
// Match a constant operand and a zext operand for the math instruction: |
--- |
2575 |
// Match a constant operand and a zext operand for the math instruction: |
--- |
| 2576 |
// add Z, C |
--- |
2576 |
// add Z, C |
--- |
| 2577 |
// sub C, Z |
--- |
2577 |
// sub C, Z |
--- |
| 2578 |
bool IsAdd = N->getOpcode() == ISD::ADD; |
0 |
2578 |
bool IsAdd = N->getOpcode() == ISD::ADD; |
0 |
| 2579 |
SDValue C = IsAdd ? N->getOperand(1) : N->getOperand(0); |
0 |
2579 |
SDValue C = IsAdd ? N->getOperand(1) : N->getOperand(0); |
0 |
| 2580 |
SDValue Z = IsAdd ? N->getOperand(0) : N->getOperand(1); |
0 |
2580 |
SDValue Z = IsAdd ? N->getOperand(0) : N->getOperand(1); |
0 |
| 2581 |
auto *CN = dyn_cast(C); |
0 |
2581 |
auto *CN = dyn_cast(C); |
0 |
| 2582 |
if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND) |
0 |
2582 |
if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND) |
0 |
| 2583 |
return SDValue(); |
0 |
2583 |
return SDValue(); |
0 |
| 2584 |
|
--- |
2584 |
|
--- |
| 2585 |
// Match the zext operand as a setcc of a boolean. |
--- |
2585 |
// Match the zext operand as a setcc of a boolean. |
--- |
| 2586 |
if (Z.getOperand(0).getOpcode() != ISD::SETCC || |
0 |
2586 |
if (Z.getOperand(0).getOpcode() != ISD::SETCC || |
0 |
| 2587 |
Z.getOperand(0).getValueType() != MVT::i1) |
0 |
2587 |
Z.getOperand(0).getValueType() != MVT::i1) |
0 |
| 2588 |
return SDValue(); |
0 |
2588 |
return SDValue(); |
0 |
| 2589 |
|
--- |
2589 |
|
--- |
| 2590 |
// Match the compare as: setcc (X & 1), 0, eq. |
--- |
2590 |
// Match the compare as: setcc (X & 1), 0, eq. |
--- |
| 2591 |
SDValue SetCC = Z.getOperand(0); |
0 |
2591 |
SDValue SetCC = Z.getOperand(0); |
0 |
| 2592 |
ISD::CondCode CC = cast(SetCC->getOperand(2))->get(); |
0 |
2592 |
ISD::CondCode CC = cast(SetCC->getOperand(2))->get(); |
0 |
| 2593 |
if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) || |
0 |
2593 |
if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) || |
0 |
| 2594 |
SetCC.getOperand(0).getOpcode() != ISD::AND || |
0 |
2594 |
SetCC.getOperand(0).getOpcode() != ISD::AND || |
0 |
| 2595 |
!isOneConstant(SetCC.getOperand(0).getOperand(1))) |
0 |
2595 |
!isOneConstant(SetCC.getOperand(0).getOperand(1))) |
0 |
| 2596 |
return SDValue(); |
0 |
2596 |
return SDValue(); |
0 |
| 2597 |
|
--- |
2597 |
|
--- |
| 2598 |
// We are adding/subtracting a constant and an inverted low bit. Turn that |
--- |
2598 |
// We are adding/subtracting a constant and an inverted low bit. Turn that |
--- |
| 2599 |
// into a subtract/add of the low bit with incremented/decremented constant: |
--- |
2599 |
// into a subtract/add of the low bit with incremented/decremented constant: |
--- |
| 2600 |
// add (zext i1 (seteq (X & 1), 0)), C --> sub C+1, (zext (X & 1)) |
--- |
2600 |
// add (zext i1 (seteq (X & 1), 0)), C --> sub C+1, (zext (X & 1)) |
--- |
| 2601 |
// sub C, (zext i1 (seteq (X & 1), 0)) --> add C-1, (zext (X & 1)) |
--- |
2601 |
// sub C, (zext i1 (seteq (X & 1), 0)) --> add C-1, (zext (X & 1)) |
--- |
| 2602 |
EVT VT = C.getValueType(); |
0 |
2602 |
EVT VT = C.getValueType(); |
0 |
| 2603 |
SDLoc DL(N); |
0 |
2603 |
SDLoc DL(N); |
0 |
| 2604 |
SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT); |
0 |
2604 |
SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT); |
0 |
| 2605 |
SDValue C1 = IsAdd ? DAG.getConstant(CN->getAPIntValue() + 1, DL, VT) : |
0 |
2605 |
SDValue C1 = IsAdd ? DAG.getConstant(CN->getAPIntValue() + 1, DL, VT) : |
0 |
| 2606 |
DAG.getConstant(CN->getAPIntValue() - 1, DL, VT); |
0 |
2606 |
DAG.getConstant(CN->getAPIntValue() - 1, DL, VT); |
0 |
| 2607 |
return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit); |
0 |
2607 |
return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit); |
0 |
| 2608 |
} |
0 |
2608 |
} |
0 |
| 2609 |
|
--- |
2609 |
|
--- |
| 2610 |
/// Try to fold a 'not' shifted sign-bit with add/sub with constant operand into |
--- |
2610 |
/// Try to fold a 'not' shifted sign-bit with add/sub with constant operand into |
--- |
| 2611 |
/// a shift and add with a different constant. |
--- |
2611 |
/// a shift and add with a different constant. |
--- |
| 2612 |
static SDValue foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) { |
0 |
2612 |
static SDValue foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) { |
0 |
| 2613 |
assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && |
0 |
2613 |
assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && |
0 |
| 2614 |
"Expecting add or sub"); |
--- |
2614 |
"Expecting add or sub"); |
--- |
| 2615 |
|
--- |
2615 |
|
--- |
| 2616 |
// We need a constant operand for the add/sub, and the other operand is a |
--- |
2616 |
// We need a constant operand for the add/sub, and the other operand is a |
--- |
| 2617 |
// logical shift right: add (srl), C or sub C, (srl). |
--- |
2617 |
// logical shift right: add (srl), C or sub C, (srl). |
--- |
| 2618 |
bool IsAdd = N->getOpcode() == ISD::ADD; |
0 |
2618 |
bool IsAdd = N->getOpcode() == ISD::ADD; |
0 |
| 2619 |
SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0); |
0 |
2619 |
SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0); |
0 |
| 2620 |
SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1); |
0 |
2620 |
SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1); |
0 |
| 2621 |
if (!DAG.isConstantIntBuildVectorOrConstantInt(ConstantOp) || |
0 |
2621 |
if (!DAG.isConstantIntBuildVectorOrConstantInt(ConstantOp) || |
0 |
| 2622 |
ShiftOp.getOpcode() != ISD::SRL) |
0 |
2622 |
ShiftOp.getOpcode() != ISD::SRL) |
0 |
| 2623 |
return SDValue(); |
0 |
2623 |
return SDValue(); |
0 |
| 2624 |
|
--- |
2624 |
|
--- |
| 2625 |
// The shift must be of a 'not' value. |
--- |
2625 |
// The shift must be of a 'not' value. |
--- |
| 2626 |
SDValue Not = ShiftOp.getOperand(0); |
0 |
2626 |
SDValue Not = ShiftOp.getOperand(0); |
0 |
| 2627 |
if (!Not.hasOneUse() || !isBitwiseNot(Not)) |
0 |
2627 |
if (!Not.hasOneUse() || !isBitwiseNot(Not)) |
0 |
| 2628 |
return SDValue(); |
0 |
2628 |
return SDValue(); |
0 |
| 2629 |
|
--- |
2629 |
|
--- |
| 2630 |
// The shift must be moving the sign bit to the least-significant-bit. |
--- |
2630 |
// The shift must be moving the sign bit to the least-significant-bit. |
--- |
| 2631 |
EVT VT = ShiftOp.getValueType(); |
0 |
2631 |
EVT VT = ShiftOp.getValueType(); |
0 |
| 2632 |
SDValue ShAmt = ShiftOp.getOperand(1); |
0 |
2632 |
SDValue ShAmt = ShiftOp.getOperand(1); |
0 |
| 2633 |
ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt); |
0 |
2633 |
ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt); |
0 |
| 2634 |
if (!ShAmtC || ShAmtC->getAPIntValue() != (VT.getScalarSizeInBits() - 1)) |
0 |
2634 |
if (!ShAmtC || ShAmtC->getAPIntValue() != (VT.getScalarSizeInBits() - 1)) |
0 |
| 2635 |
return SDValue(); |
0 |
2635 |
return SDValue(); |
0 |
| 2636 |
|
--- |
2636 |
|
--- |
| 2637 |
// Eliminate the 'not' by adjusting the shift and add/sub constant: |
--- |
2637 |
// Eliminate the 'not' by adjusting the shift and add/sub constant: |
--- |
| 2638 |
// add (srl (not X), 31), C --> add (sra X, 31), (C + 1) |
--- |
2638 |
// add (srl (not X), 31), C --> add (sra X, 31), (C + 1) |
--- |
| 2639 |
// sub C, (srl (not X), 31) --> add (srl X, 31), (C - 1) |
--- |
2639 |
// sub C, (srl (not X), 31) --> add (srl X, 31), (C - 1) |
--- |
| 2640 |
SDLoc DL(N); |
0 |
2640 |
SDLoc DL(N); |
0 |
| 2641 |
if (SDValue NewC = DAG.FoldConstantArithmetic( |
0 |
2641 |
if (SDValue NewC = DAG.FoldConstantArithmetic( |
0 |
| 2642 |
IsAdd ? ISD::ADD : ISD::SUB, DL, VT, |
--- |
2642 |
IsAdd ? ISD::ADD : ISD::SUB, DL, VT, |
--- |
| 2643 |
{ConstantOp, DAG.getConstant(1, DL, VT)})) { |
0 |
2643 |
{ConstantOp, DAG.getConstant(1, DL, VT)})) { |
0 |
| 2644 |
SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, |
0 |
2644 |
SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, |
0 |
| 2645 |
Not.getOperand(0), ShAmt); |
0 |
2645 |
Not.getOperand(0), ShAmt); |
0 |
| 2646 |
return DAG.getNode(ISD::ADD, DL, VT, NewShift, NewC); |
0 |
2646 |
return DAG.getNode(ISD::ADD, DL, VT, NewShift, NewC); |
0 |
| 2647 |
} |
--- |
2647 |
} |
--- |
| 2648 |
|
--- |
2648 |
|
--- |
| 2649 |
return SDValue(); |
0 |
2649 |
return SDValue(); |
0 |
| 2650 |
} |
0 |
2650 |
} |
0 |
| 2651 |
|
--- |
2651 |
|
--- |
| 2652 |
static bool isADDLike(SDValue V, const SelectionDAG &DAG) { |
3 |
2652 |
static bool isADDLike(SDValue V, const SelectionDAG &DAG) { |
3 |
| 2653 |
unsigned Opcode = V.getOpcode(); |
3 |
2653 |
unsigned Opcode = V.getOpcode(); |
3 |
| 2654 |
if (Opcode == ISD::OR) |
3 |
2654 |
if (Opcode == ISD::OR) |
3 |
| 2655 |
return DAG.haveNoCommonBitsSet(V.getOperand(0), V.getOperand(1)); |
0 |
2655 |
return DAG.haveNoCommonBitsSet(V.getOperand(0), V.getOperand(1)); |
0 |
| 2656 |
if (Opcode == ISD::XOR) |
3 |
2656 |
if (Opcode == ISD::XOR) |
3 |
| 2657 |
return isMinSignedConstant(V.getOperand(1)); |
0 |
2657 |
return isMinSignedConstant(V.getOperand(1)); |
0 |
| 2658 |
return false; |
3 |
2658 |
return false; |
3 |
| 2659 |
} |
--- |
2659 |
} |
--- |
| 2660 |
|
--- |
2660 |
|
--- |
| 2661 |
static bool |
--- |
2661 |
static bool |
--- |
| 2662 |
areBitwiseNotOfEachother(SDValue Op0, SDValue Op1) { |
2 |
2662 |
areBitwiseNotOfEachother(SDValue Op0, SDValue Op1) { |
2 |
| 2663 |
return (isBitwiseNot(Op0) && Op0.getOperand(0) == Op1) || |
4 |
2663 |
return (isBitwiseNot(Op0) && Op0.getOperand(0) == Op1) || |
4 |
| 2664 |
(isBitwiseNot(Op1) && Op1.getOperand(0) == Op0); |
4 |
2664 |
(isBitwiseNot(Op1) && Op1.getOperand(0) == Op0); |
4 |
| 2665 |
} |
--- |
2665 |
} |
--- |
| 2666 |
|
--- |
2666 |
|
--- |
| 2667 |
/// Try to fold a node that behaves like an ADD (note that N isn't necessarily |
--- |
2667 |
/// Try to fold a node that behaves like an ADD (note that N isn't necessarily |
--- |
| 2668 |
/// an ISD::ADD here, it could for example be an ISD::OR if we know that there |
--- |
2668 |
/// an ISD::ADD here, it could for example be an ISD::OR if we know that there |
--- |
| 2669 |
/// are no common bits set in the operands). |
--- |
2669 |
/// are no common bits set in the operands). |
--- |
| 2670 |
SDValue DAGCombiner::visitADDLike(SDNode *N) { |
1 |
2670 |
SDValue DAGCombiner::visitADDLike(SDNode *N) { |
1 |
| 2671 |
SDValue N0 = N->getOperand(0); |
1 |
2671 |
SDValue N0 = N->getOperand(0); |
1 |
| 2672 |
SDValue N1 = N->getOperand(1); |
1 |
2672 |
SDValue N1 = N->getOperand(1); |
1 |
| 2673 |
EVT VT = N0.getValueType(); |
1 |
2673 |
EVT VT = N0.getValueType(); |
1 |
| 2674 |
SDLoc DL(N); |
1 |
2674 |
SDLoc DL(N); |
1 |
| 2675 |
|
--- |
2675 |
|
--- |
| 2676 |
// fold (add x, undef) -> undef |
--- |
2676 |
// fold (add x, undef) -> undef |
--- |
| 2677 |
if (N0.isUndef()) |
1 |
2677 |
if (N0.isUndef()) |
1 |
| 2678 |
return N0; |
0 |
2678 |
return N0; |
0 |
| 2679 |
if (N1.isUndef()) |
1 |
2679 |
if (N1.isUndef()) |
1 |
| 2680 |
return N1; |
0 |
2680 |
return N1; |
0 |
| 2681 |
|
--- |
2681 |
|
--- |
| 2682 |
// fold (add c1, c2) -> c1+c2 |
--- |
2682 |
// fold (add c1, c2) -> c1+c2 |
--- |
| 2683 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0, N1})) |
1 |
2683 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0, N1})) |
1 |
| 2684 |
return C; |
0 |
2684 |
return C; |
0 |
| 2685 |
|
--- |
2685 |
|
--- |
| 2686 |
// canonicalize constant to RHS |
--- |
2686 |
// canonicalize constant to RHS |
--- |
| 2687 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
1 |
2687 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
1 |
| 2688 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
2688 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 2689 |
return DAG.getNode(ISD::ADD, DL, VT, N1, N0); |
0 |
2689 |
return DAG.getNode(ISD::ADD, DL, VT, N1, N0); |
0 |
| 2690 |
|
--- |
2690 |
|
--- |
| 2691 |
if (areBitwiseNotOfEachother(N0, N1)) |
1 |
2691 |
if (areBitwiseNotOfEachother(N0, N1)) |
1 |
| 2692 |
return DAG.getConstant(APInt::getAllOnes(VT.getScalarSizeInBits()), |
0 |
2692 |
return DAG.getConstant(APInt::getAllOnes(VT.getScalarSizeInBits()), |
0 |
| 2693 |
SDLoc(N), VT); |
0 |
2693 |
SDLoc(N), VT); |
0 |
| 2694 |
|
--- |
2694 |
|
--- |
| 2695 |
// fold vector ops |
--- |
2695 |
// fold vector ops |
--- |
| 2696 |
if (VT.isVector()) { |
1 |
2696 |
if (VT.isVector()) { |
1 |
| 2697 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
2697 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 2698 |
return FoldedVOp; |
0 |
2698 |
return FoldedVOp; |
0 |
| 2699 |
|
--- |
2699 |
|
--- |
| 2700 |
// fold (add x, 0) -> x, vector edition |
--- |
2700 |
// fold (add x, 0) -> x, vector edition |
--- |
| 2701 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
2701 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
| 2702 |
return N0; |
0 |
2702 |
return N0; |
0 |
| 2703 |
} |
--- |
2703 |
} |
--- |
| 2704 |
|
--- |
2704 |
|
--- |
| 2705 |
// fold (add x, 0) -> x |
--- |
2705 |
// fold (add x, 0) -> x |
--- |
| 2706 |
if (isNullConstant(N1)) |
1 |
2706 |
if (isNullConstant(N1)) |
1 |
| 2707 |
return N0; |
0 |
2707 |
return N0; |
0 |
| 2708 |
|
--- |
2708 |
|
--- |
| 2709 |
if (N0.getOpcode() == ISD::SUB) { |
1 |
2709 |
if (N0.getOpcode() == ISD::SUB) { |
1 |
| 2710 |
SDValue N00 = N0.getOperand(0); |
0 |
2710 |
SDValue N00 = N0.getOperand(0); |
0 |
| 2711 |
SDValue N01 = N0.getOperand(1); |
0 |
2711 |
SDValue N01 = N0.getOperand(1); |
0 |
| 2712 |
|
--- |
2712 |
|
--- |
| 2713 |
// fold ((A-c1)+c2) -> (A+(c2-c1)) |
--- |
2713 |
// fold ((A-c1)+c2) -> (A+(c2-c1)) |
--- |
| 2714 |
if (SDValue Sub = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N1, N01})) |
0 |
2714 |
if (SDValue Sub = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N1, N01})) |
0 |
| 2715 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Sub); |
0 |
2715 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Sub); |
0 |
| 2716 |
|
--- |
2716 |
|
--- |
| 2717 |
// fold ((c1-A)+c2) -> (c1+c2)-A |
--- |
2717 |
// fold ((c1-A)+c2) -> (c1+c2)-A |
--- |
| 2718 |
if (SDValue Add = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N1, N00})) |
0 |
2718 |
if (SDValue Add = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N1, N00})) |
0 |
| 2719 |
return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1)); |
0 |
2719 |
return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1)); |
0 |
| 2720 |
} |
--- |
2720 |
} |
--- |
| 2721 |
|
--- |
2721 |
|
--- |
| 2722 |
// add (sext i1 X), 1 -> zext (not i1 X) |
--- |
2722 |
// add (sext i1 X), 1 -> zext (not i1 X) |
--- |
| 2723 |
// We don't transform this pattern: |
--- |
2723 |
// We don't transform this pattern: |
--- |
| 2724 |
// add (zext i1 X), -1 -> sext (not i1 X) |
--- |
2724 |
// add (zext i1 X), -1 -> sext (not i1 X) |
--- |
| 2725 |
// because most (?) targets generate better code for the zext form. |
--- |
2725 |
// because most (?) targets generate better code for the zext form. |
--- |
| 2726 |
if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() && |
1 |
2726 |
if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() && |
1 |
| 2727 |
isOneOrOneSplat(N1)) { |
0 |
2727 |
isOneOrOneSplat(N1)) { |
0 |
| 2728 |
SDValue X = N0.getOperand(0); |
0 |
2728 |
SDValue X = N0.getOperand(0); |
0 |
| 2729 |
if ((!LegalOperations || |
0 |
2729 |
if ((!LegalOperations || |
0 |
| 2730 |
(TLI.isOperationLegal(ISD::XOR, X.getValueType()) && |
0 |
2730 |
(TLI.isOperationLegal(ISD::XOR, X.getValueType()) && |
0 |
| 2731 |
TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) && |
0 |
2731 |
TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) && |
0 |
| 2732 |
X.getScalarValueSizeInBits() == 1) { |
0 |
2732 |
X.getScalarValueSizeInBits() == 1) { |
0 |
| 2733 |
SDValue Not = DAG.getNOT(DL, X, X.getValueType()); |
0 |
2733 |
SDValue Not = DAG.getNOT(DL, X, X.getValueType()); |
0 |
| 2734 |
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not); |
0 |
2734 |
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not); |
0 |
| 2735 |
} |
--- |
2735 |
} |
--- |
| 2736 |
} |
--- |
2736 |
} |
--- |
| 2737 |
|
--- |
2737 |
|
--- |
| 2738 |
// Fold (add (or x, c0), c1) -> (add x, (c0 + c1)) |
--- |
2738 |
// Fold (add (or x, c0), c1) -> (add x, (c0 + c1)) |
--- |
| 2739 |
// iff (or x, c0) is equivalent to (add x, c0). |
--- |
2739 |
// iff (or x, c0) is equivalent to (add x, c0). |
--- |
| 2740 |
// Fold (add (xor x, c0), c1) -> (add x, (c0 + c1)) |
--- |
2740 |
// Fold (add (xor x, c0), c1) -> (add x, (c0 + c1)) |
--- |
| 2741 |
// iff (xor x, c0) is equivalent to (add x, c0). |
--- |
2741 |
// iff (xor x, c0) is equivalent to (add x, c0). |
--- |
| 2742 |
if (isADDLike(N0, DAG)) { |
1 |
2742 |
if (isADDLike(N0, DAG)) { |
1 |
| 2743 |
SDValue N01 = N0.getOperand(1); |
0 |
2743 |
SDValue N01 = N0.getOperand(1); |
0 |
| 2744 |
if (SDValue Add = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N1, N01})) |
0 |
2744 |
if (SDValue Add = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N1, N01})) |
0 |
| 2745 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add); |
0 |
2745 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add); |
0 |
| 2746 |
} |
--- |
2746 |
} |
--- |
| 2747 |
|
--- |
2747 |
|
--- |
| 2748 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
1 |
2748 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
1 |
| 2749 |
return NewSel; |
0 |
2749 |
return NewSel; |
0 |
| 2750 |
|
--- |
2750 |
|
--- |
| 2751 |
// reassociate add |
--- |
2751 |
// reassociate add |
--- |
| 2752 |
if (!reassociationCanBreakAddressingModePattern(ISD::ADD, DL, N, N0, N1)) { |
1 |
2752 |
if (!reassociationCanBreakAddressingModePattern(ISD::ADD, DL, N, N0, N1)) { |
1 |
| 2753 |
if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags())) |
1 |
2753 |
if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags())) |
1 |
| 2754 |
return RADD; |
0 |
2754 |
return RADD; |
0 |
| 2755 |
|
--- |
2755 |
|
--- |
| 2756 |
// Reassociate (add (or x, c), y) -> (add add(x, y), c)) if (or x, c) is |
--- |
2756 |
// Reassociate (add (or x, c), y) -> (add add(x, y), c)) if (or x, c) is |
--- |
| 2757 |
// equivalent to (add x, c). |
--- |
2757 |
// equivalent to (add x, c). |
--- |
| 2758 |
// Reassociate (add (xor x, c), y) -> (add add(x, y), c)) if (xor x, c) is |
--- |
2758 |
// Reassociate (add (xor x, c), y) -> (add add(x, y), c)) if (xor x, c) is |
--- |
| 2759 |
// equivalent to (add x, c). |
--- |
2759 |
// equivalent to (add x, c). |
--- |
| 2760 |
// Do this optimization only when adding c does not introduce instructions |
--- |
2760 |
// Do this optimization only when adding c does not introduce instructions |
--- |
| 2761 |
// for adding carries. |
--- |
2761 |
// for adding carries. |
--- |
| 2762 |
auto ReassociateAddOr = [&](SDValue N0, SDValue N1) { |
2 |
2762 |
auto ReassociateAddOr = [&](SDValue N0, SDValue N1) { |
2 |
| 2763 |
if (isADDLike(N0, DAG) && N0.hasOneUse() && |
2 |
2763 |
if (isADDLike(N0, DAG) && N0.hasOneUse() && |
2 |
| 2764 |
isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true)) { |
0 |
2764 |
isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true)) { |
0 |
| 2765 |
// If N0's type does not split or is a sign mask, it does not introduce |
--- |
2765 |
// If N0's type does not split or is a sign mask, it does not introduce |
--- |
| 2766 |
// add carry. |
--- |
2766 |
// add carry. |
--- |
| 2767 |
auto TyActn = TLI.getTypeAction(*DAG.getContext(), N0.getValueType()); |
0 |
2767 |
auto TyActn = TLI.getTypeAction(*DAG.getContext(), N0.getValueType()); |
0 |
| 2768 |
bool NoAddCarry = TyActn == TargetLoweringBase::TypeLegal || |
0 |
2768 |
bool NoAddCarry = TyActn == TargetLoweringBase::TypeLegal || |
0 |
| 2769 |
TyActn == TargetLoweringBase::TypePromoteInteger || |
0 |
2769 |
TyActn == TargetLoweringBase::TypePromoteInteger || |
0 |
| 2770 |
isMinSignedConstant(N0.getOperand(1)); |
0 |
2770 |
isMinSignedConstant(N0.getOperand(1)); |
0 |
| 2771 |
if (NoAddCarry) |
0 |
2771 |
if (NoAddCarry) |
0 |
| 2772 |
return DAG.getNode( |
0 |
2772 |
return DAG.getNode( |
0 |
| 2773 |
ISD::ADD, DL, VT, |
0 |
2773 |
ISD::ADD, DL, VT, |
0 |
| 2774 |
DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(0)), |
0 |
2774 |
DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(0)), |
0 |
| 2775 |
N0.getOperand(1)); |
0 |
2775 |
N0.getOperand(1)); |
0 |
| 2776 |
} |
--- |
2776 |
} |
--- |
| 2777 |
return SDValue(); |
2 |
2777 |
return SDValue(); |
2 |
| 2778 |
}; |
1 |
2778 |
}; |
1 |
| 2779 |
if (SDValue Add = ReassociateAddOr(N0, N1)) |
1 |
2779 |
if (SDValue Add = ReassociateAddOr(N0, N1)) |
1 |
| 2780 |
return Add; |
0 |
2780 |
return Add; |
0 |
| 2781 |
if (SDValue Add = ReassociateAddOr(N1, N0)) |
1 |
2781 |
if (SDValue Add = ReassociateAddOr(N1, N0)) |
1 |
| 2782 |
return Add; |
0 |
2782 |
return Add; |
0 |
| 2783 |
|
--- |
2783 |
|
--- |
| 2784 |
// Fold add(vecreduce(x), vecreduce(y)) -> vecreduce(add(x, y)) |
--- |
2784 |
// Fold add(vecreduce(x), vecreduce(y)) -> vecreduce(add(x, y)) |
--- |
| 2785 |
if (SDValue SD = |
1 |
2785 |
if (SDValue SD = |
1 |
| 2786 |
reassociateReduction(ISD::VECREDUCE_ADD, ISD::ADD, DL, VT, N0, N1)) |
1 |
2786 |
reassociateReduction(ISD::VECREDUCE_ADD, ISD::ADD, DL, VT, N0, N1)) |
1 |
| 2787 |
return SD; |
0 |
2787 |
return SD; |
0 |
| 2788 |
} |
--- |
2788 |
} |
--- |
| 2789 |
// fold ((0-A) + B) -> B-A |
--- |
2789 |
// fold ((0-A) + B) -> B-A |
--- |
| 2790 |
if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0))) |
1 |
2790 |
if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0))) |
1 |
| 2791 |
return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1)); |
0 |
2791 |
return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1)); |
0 |
| 2792 |
|
--- |
2792 |
|
--- |
| 2793 |
// fold (A + (0-B)) -> A-B |
--- |
2793 |
// fold (A + (0-B)) -> A-B |
--- |
| 2794 |
if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) |
1 |
2794 |
if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) |
1 |
| 2795 |
return DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(1)); |
0 |
2795 |
return DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(1)); |
0 |
| 2796 |
|
--- |
2796 |
|
--- |
| 2797 |
// fold (A+(B-A)) -> B |
--- |
2797 |
// fold (A+(B-A)) -> B |
--- |
| 2798 |
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) |
1 |
2798 |
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) |
1 |
| 2799 |
return N1.getOperand(0); |
0 |
2799 |
return N1.getOperand(0); |
0 |
| 2800 |
|
--- |
2800 |
|
--- |
| 2801 |
// fold ((B-A)+A) -> B |
--- |
2801 |
// fold ((B-A)+A) -> B |
--- |
| 2802 |
if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) |
1 |
2802 |
if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) |
1 |
| 2803 |
return N0.getOperand(0); |
0 |
2803 |
return N0.getOperand(0); |
0 |
| 2804 |
|
--- |
2804 |
|
--- |
| 2805 |
// fold ((A-B)+(C-A)) -> (C-B) |
--- |
2805 |
// fold ((A-B)+(C-A)) -> (C-B) |
--- |
| 2806 |
if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && |
1 |
2806 |
if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && |
1 |
| 2807 |
N0.getOperand(0) == N1.getOperand(1)) |
0 |
2807 |
N0.getOperand(0) == N1.getOperand(1)) |
0 |
| 2808 |
return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0), |
0 |
2808 |
return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0), |
0 |
| 2809 |
N0.getOperand(1)); |
0 |
2809 |
N0.getOperand(1)); |
0 |
| 2810 |
|
--- |
2810 |
|
--- |
| 2811 |
// fold ((A-B)+(B-C)) -> (A-C) |
--- |
2811 |
// fold ((A-B)+(B-C)) -> (A-C) |
--- |
| 2812 |
if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && |
1 |
2812 |
if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && |
1 |
| 2813 |
N0.getOperand(1) == N1.getOperand(0)) |
0 |
2813 |
N0.getOperand(1) == N1.getOperand(0)) |
0 |
| 2814 |
return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), |
0 |
2814 |
return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), |
0 |
| 2815 |
N1.getOperand(1)); |
0 |
2815 |
N1.getOperand(1)); |
0 |
| 2816 |
|
--- |
2816 |
|
--- |
| 2817 |
// fold (A+(B-(A+C))) to (B-C) |
--- |
2817 |
// fold (A+(B-(A+C))) to (B-C) |
--- |
| 2818 |
if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && |
1 |
2818 |
if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && |
1 |
| 2819 |
N0 == N1.getOperand(1).getOperand(0)) |
0 |
2819 |
N0 == N1.getOperand(1).getOperand(0)) |
0 |
| 2820 |
return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0), |
0 |
2820 |
return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0), |
0 |
| 2821 |
N1.getOperand(1).getOperand(1)); |
0 |
2821 |
N1.getOperand(1).getOperand(1)); |
0 |
| 2822 |
|
--- |
2822 |
|
--- |
| 2823 |
// fold (A+(B-(C+A))) to (B-C) |
--- |
2823 |
// fold (A+(B-(C+A))) to (B-C) |
--- |
| 2824 |
if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && |
1 |
2824 |
if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && |
1 |
| 2825 |
N0 == N1.getOperand(1).getOperand(1)) |
0 |
2825 |
N0 == N1.getOperand(1).getOperand(1)) |
0 |
| 2826 |
return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0), |
0 |
2826 |
return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0), |
0 |
| 2827 |
N1.getOperand(1).getOperand(0)); |
0 |
2827 |
N1.getOperand(1).getOperand(0)); |
0 |
| 2828 |
|
--- |
2828 |
|
--- |
| 2829 |
// fold (A+((B-A)+or-C)) to (B+or-C) |
--- |
2829 |
// fold (A+((B-A)+or-C)) to (B+or-C) |
--- |
| 2830 |
if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && |
2 |
2830 |
if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && |
2 |
| 2831 |
N1.getOperand(0).getOpcode() == ISD::SUB && |
2 |
2831 |
N1.getOperand(0).getOpcode() == ISD::SUB && |
2 |
| 2832 |
N0 == N1.getOperand(0).getOperand(1)) |
0 |
2832 |
N0 == N1.getOperand(0).getOperand(1)) |
0 |
| 2833 |
return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0), |
0 |
2833 |
return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0), |
0 |
| 2834 |
N1.getOperand(1)); |
0 |
2834 |
N1.getOperand(1)); |
0 |
| 2835 |
|
--- |
2835 |
|
--- |
| 2836 |
// fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant |
--- |
2836 |
// fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant |
--- |
| 2837 |
if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && |
1 |
2837 |
if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB && |
1 |
| 2838 |
N0->hasOneUse() && N1->hasOneUse()) { |
1 |
2838 |
N0->hasOneUse() && N1->hasOneUse()) { |
1 |
| 2839 |
SDValue N00 = N0.getOperand(0); |
0 |
2839 |
SDValue N00 = N0.getOperand(0); |
0 |
| 2840 |
SDValue N01 = N0.getOperand(1); |
0 |
2840 |
SDValue N01 = N0.getOperand(1); |
0 |
| 2841 |
SDValue N10 = N1.getOperand(0); |
0 |
2841 |
SDValue N10 = N1.getOperand(0); |
0 |
| 2842 |
SDValue N11 = N1.getOperand(1); |
0 |
2842 |
SDValue N11 = N1.getOperand(1); |
0 |
| 2843 |
|
--- |
2843 |
|
--- |
| 2844 |
if (isConstantOrConstantVector(N00) || isConstantOrConstantVector(N10)) |
0 |
2844 |
if (isConstantOrConstantVector(N00) || isConstantOrConstantVector(N10)) |
0 |
| 2845 |
return DAG.getNode(ISD::SUB, DL, VT, |
0 |
2845 |
return DAG.getNode(ISD::SUB, DL, VT, |
0 |
| 2846 |
DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10), |
0 |
2846 |
DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10), |
0 |
| 2847 |
DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11)); |
0 |
2847 |
DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11)); |
0 |
| 2848 |
} |
--- |
2848 |
} |
--- |
| 2849 |
|
--- |
2849 |
|
--- |
| 2850 |
// fold (add (umax X, C), -C) --> (usubsat X, C) |
--- |
2850 |
// fold (add (umax X, C), -C) --> (usubsat X, C) |
--- |
| 2851 |
if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) { |
1 |
2851 |
if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) { |
1 |
| 2852 |
auto MatchUSUBSAT = [](ConstantSDNode *Max, ConstantSDNode *Op) { |
0 |
2852 |
auto MatchUSUBSAT = [](ConstantSDNode *Max, ConstantSDNode *Op) { |
0 |
| 2853 |
return (!Max && !Op) || |
0 |
2853 |
return (!Max && !Op) || |
0 |
| 2854 |
(Max && Op && Max->getAPIntValue() == (-Op->getAPIntValue())); |
0 |
2854 |
(Max && Op && Max->getAPIntValue() == (-Op->getAPIntValue())); |
0 |
| 2855 |
}; |
--- |
2855 |
}; |
--- |
| 2856 |
if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchUSUBSAT, |
0 |
2856 |
if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchUSUBSAT, |
0 |
| 2857 |
/*AllowUndefs*/ true)) |
--- |
2857 |
/*AllowUndefs*/ true)) |
--- |
| 2858 |
return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0), |
0 |
2858 |
return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0), |
0 |
| 2859 |
N0.getOperand(1)); |
0 |
2859 |
N0.getOperand(1)); |
0 |
| 2860 |
} |
--- |
2860 |
} |
--- |
| 2861 |
|
--- |
2861 |
|
--- |
| 2862 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
1 |
2862 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
1 |
| 2863 |
return SDValue(N, 0); |
0 |
2863 |
return SDValue(N, 0); |
0 |
| 2864 |
|
--- |
2864 |
|
--- |
| 2865 |
if (isOneOrOneSplat(N1)) { |
1 |
2865 |
if (isOneOrOneSplat(N1)) { |
1 |
| 2866 |
// fold (add (xor a, -1), 1) -> (sub 0, a) |
--- |
2866 |
// fold (add (xor a, -1), 1) -> (sub 0, a) |
--- |
| 2867 |
if (isBitwiseNot(N0)) |
1 |
2867 |
if (isBitwiseNot(N0)) |
1 |
| 2868 |
return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), |
0 |
2868 |
return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), |
0 |
| 2869 |
N0.getOperand(0)); |
0 |
2869 |
N0.getOperand(0)); |
0 |
| 2870 |
|
--- |
2870 |
|
--- |
| 2871 |
// fold (add (add (xor a, -1), b), 1) -> (sub b, a) |
--- |
2871 |
// fold (add (add (xor a, -1), b), 1) -> (sub b, a) |
--- |
| 2872 |
if (N0.getOpcode() == ISD::ADD) { |
1 |
2872 |
if (N0.getOpcode() == ISD::ADD) { |
1 |
| 2873 |
SDValue A, Xor; |
0 |
2873 |
SDValue A, Xor; |
0 |
| 2874 |
|
--- |
2874 |
|
--- |
| 2875 |
if (isBitwiseNot(N0.getOperand(0))) { |
0 |
2875 |
if (isBitwiseNot(N0.getOperand(0))) { |
0 |
| 2876 |
A = N0.getOperand(1); |
0 |
2876 |
A = N0.getOperand(1); |
0 |
| 2877 |
Xor = N0.getOperand(0); |
0 |
2877 |
Xor = N0.getOperand(0); |
0 |
| 2878 |
} else if (isBitwiseNot(N0.getOperand(1))) { |
0 |
2878 |
} else if (isBitwiseNot(N0.getOperand(1))) { |
0 |
| 2879 |
A = N0.getOperand(0); |
0 |
2879 |
A = N0.getOperand(0); |
0 |
| 2880 |
Xor = N0.getOperand(1); |
0 |
2880 |
Xor = N0.getOperand(1); |
0 |
| 2881 |
} |
--- |
2881 |
} |
--- |
| 2882 |
|
--- |
2882 |
|
--- |
| 2883 |
if (Xor) |
0 |
2883 |
if (Xor) |
0 |
| 2884 |
return DAG.getNode(ISD::SUB, DL, VT, A, Xor.getOperand(0)); |
0 |
2884 |
return DAG.getNode(ISD::SUB, DL, VT, A, Xor.getOperand(0)); |
0 |
| 2885 |
} |
--- |
2885 |
} |
--- |
| 2886 |
|
--- |
2886 |
|
--- |
| 2887 |
// Look for: |
--- |
2887 |
// Look for: |
--- |
| 2888 |
// add (add x, y), 1 |
--- |
2888 |
// add (add x, y), 1 |
--- |
| 2889 |
// And if the target does not like this form then turn into: |
--- |
2889 |
// And if the target does not like this form then turn into: |
--- |
| 2890 |
// sub y, (xor x, -1) |
--- |
2890 |
// sub y, (xor x, -1) |
--- |
| 2891 |
if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD && |
1 |
2891 |
if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD && |
1 |
| 2892 |
N0.hasOneUse() && |
1 |
2892 |
N0.hasOneUse() && |
1 |
| 2893 |
// Limit this to after legalization if the add has wrap flags |
--- |
2893 |
// Limit this to after legalization if the add has wrap flags |
--- |
| 2894 |
(Level >= AfterLegalizeDAG || (!N->getFlags().hasNoUnsignedWrap() && |
0 |
2894 |
(Level >= AfterLegalizeDAG || (!N->getFlags().hasNoUnsignedWrap() && |
0 |
| 2895 |
!N->getFlags().hasNoSignedWrap()))) { |
1 |
2895 |
!N->getFlags().hasNoSignedWrap()))) { |
1 |
| 2896 |
SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0), |
0 |
2896 |
SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0), |
0 |
| 2897 |
DAG.getAllOnesConstant(DL, VT)); |
0 |
2897 |
DAG.getAllOnesConstant(DL, VT)); |
0 |
| 2898 |
return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(1), Not); |
0 |
2898 |
return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(1), Not); |
0 |
| 2899 |
} |
--- |
2899 |
} |
--- |
| 2900 |
} |
--- |
2900 |
} |
--- |
| 2901 |
|
--- |
2901 |
|
--- |
| 2902 |
// (x - y) + -1 -> add (xor y, -1), x |
--- |
2902 |
// (x - y) + -1 -> add (xor y, -1), x |
--- |
| 2903 |
if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && |
1 |
2903 |
if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && |
1 |
| 2904 |
isAllOnesOrAllOnesSplat(N1)) { |
0 |
2904 |
isAllOnesOrAllOnesSplat(N1)) { |
0 |
| 2905 |
SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1), N1); |
0 |
2905 |
SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1), N1); |
0 |
| 2906 |
return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0)); |
0 |
2906 |
return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0)); |
0 |
| 2907 |
} |
--- |
2907 |
} |
--- |
| 2908 |
|
--- |
2908 |
|
--- |
| 2909 |
if (SDValue Combined = visitADDLikeCommutative(N0, N1, N)) |
1 |
2909 |
if (SDValue Combined = visitADDLikeCommutative(N0, N1, N)) |
1 |
| 2910 |
return Combined; |
0 |
2910 |
return Combined; |
0 |
| 2911 |
|
--- |
2911 |
|
--- |
| 2912 |
if (SDValue Combined = visitADDLikeCommutative(N1, N0, N)) |
1 |
2912 |
if (SDValue Combined = visitADDLikeCommutative(N1, N0, N)) |
1 |
| 2913 |
return Combined; |
0 |
2913 |
return Combined; |
0 |
| 2914 |
|
--- |
2914 |
|
--- |
| 2915 |
return SDValue(); |
1 |
2915 |
return SDValue(); |
1 |
| 2916 |
} |
1 |
2916 |
} |
1 |
| 2917 |
|
--- |
2917 |
|
--- |
| 2918 |
SDValue DAGCombiner::visitADD(SDNode *N) { |
0 |
2918 |
SDValue DAGCombiner::visitADD(SDNode *N) { |
0 |
| 2919 |
SDValue N0 = N->getOperand(0); |
0 |
2919 |
SDValue N0 = N->getOperand(0); |
0 |
| 2920 |
SDValue N1 = N->getOperand(1); |
0 |
2920 |
SDValue N1 = N->getOperand(1); |
0 |
| 2921 |
EVT VT = N0.getValueType(); |
0 |
2921 |
EVT VT = N0.getValueType(); |
0 |
| 2922 |
SDLoc DL(N); |
0 |
2922 |
SDLoc DL(N); |
0 |
| 2923 |
|
--- |
2923 |
|
--- |
| 2924 |
if (SDValue Combined = visitADDLike(N)) |
0 |
2924 |
if (SDValue Combined = visitADDLike(N)) |
0 |
| 2925 |
return Combined; |
0 |
2925 |
return Combined; |
0 |
| 2926 |
|
--- |
2926 |
|
--- |
| 2927 |
if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG)) |
0 |
2927 |
if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG)) |
0 |
| 2928 |
return V; |
0 |
2928 |
return V; |
0 |
| 2929 |
|
--- |
2929 |
|
--- |
| 2930 |
if (SDValue V = foldAddSubOfSignBit(N, DAG)) |
0 |
2930 |
if (SDValue V = foldAddSubOfSignBit(N, DAG)) |
0 |
| 2931 |
return V; |
0 |
2931 |
return V; |
0 |
| 2932 |
|
--- |
2932 |
|
--- |
| 2933 |
// fold (a+b) -> (a|b) iff a and b share no bits. |
--- |
2933 |
// fold (a+b) -> (a|b) iff a and b share no bits. |
--- |
| 2934 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && |
0 |
2934 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && |
0 |
| 2935 |
DAG.haveNoCommonBitsSet(N0, N1)) |
0 |
2935 |
DAG.haveNoCommonBitsSet(N0, N1)) |
0 |
| 2936 |
return DAG.getNode(ISD::OR, DL, VT, N0, N1); |
0 |
2936 |
return DAG.getNode(ISD::OR, DL, VT, N0, N1); |
0 |
| 2937 |
|
--- |
2937 |
|
--- |
| 2938 |
// Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)). |
--- |
2938 |
// Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)). |
--- |
| 2939 |
if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { |
0 |
2939 |
if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { |
0 |
| 2940 |
const APInt &C0 = N0->getConstantOperandAPInt(0); |
0 |
2940 |
const APInt &C0 = N0->getConstantOperandAPInt(0); |
0 |
| 2941 |
const APInt &C1 = N1->getConstantOperandAPInt(0); |
0 |
2941 |
const APInt &C1 = N1->getConstantOperandAPInt(0); |
0 |
| 2942 |
return DAG.getVScale(DL, VT, C0 + C1); |
0 |
2942 |
return DAG.getVScale(DL, VT, C0 + C1); |
0 |
| 2943 |
} |
--- |
2943 |
} |
--- |
| 2944 |
|
--- |
2944 |
|
--- |
| 2945 |
// fold a+vscale(c1)+vscale(c2) -> a+vscale(c1+c2) |
--- |
2945 |
// fold a+vscale(c1)+vscale(c2) -> a+vscale(c1+c2) |
--- |
| 2946 |
if (N0.getOpcode() == ISD::ADD && |
0 |
2946 |
if (N0.getOpcode() == ISD::ADD && |
0 |
| 2947 |
N0.getOperand(1).getOpcode() == ISD::VSCALE && |
0 |
2947 |
N0.getOperand(1).getOpcode() == ISD::VSCALE && |
0 |
| 2948 |
N1.getOpcode() == ISD::VSCALE) { |
0 |
2948 |
N1.getOpcode() == ISD::VSCALE) { |
0 |
| 2949 |
const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0); |
0 |
2949 |
const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0); |
0 |
| 2950 |
const APInt &VS1 = N1->getConstantOperandAPInt(0); |
0 |
2950 |
const APInt &VS1 = N1->getConstantOperandAPInt(0); |
0 |
| 2951 |
SDValue VS = DAG.getVScale(DL, VT, VS0 + VS1); |
0 |
2951 |
SDValue VS = DAG.getVScale(DL, VT, VS0 + VS1); |
0 |
| 2952 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), VS); |
0 |
2952 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), VS); |
0 |
| 2953 |
} |
--- |
2953 |
} |
--- |
| 2954 |
|
--- |
2954 |
|
--- |
| 2955 |
// Fold (add step_vector(c1), step_vector(c2) to step_vector(c1+c2)) |
--- |
2955 |
// Fold (add step_vector(c1), step_vector(c2) to step_vector(c1+c2)) |
--- |
| 2956 |
if (N0.getOpcode() == ISD::STEP_VECTOR && |
0 |
2956 |
if (N0.getOpcode() == ISD::STEP_VECTOR && |
0 |
| 2957 |
N1.getOpcode() == ISD::STEP_VECTOR) { |
0 |
2957 |
N1.getOpcode() == ISD::STEP_VECTOR) { |
0 |
| 2958 |
const APInt &C0 = N0->getConstantOperandAPInt(0); |
0 |
2958 |
const APInt &C0 = N0->getConstantOperandAPInt(0); |
0 |
| 2959 |
const APInt &C1 = N1->getConstantOperandAPInt(0); |
0 |
2959 |
const APInt &C1 = N1->getConstantOperandAPInt(0); |
0 |
| 2960 |
APInt NewStep = C0 + C1; |
0 |
2960 |
APInt NewStep = C0 + C1; |
0 |
| 2961 |
return DAG.getStepVector(DL, VT, NewStep); |
0 |
2961 |
return DAG.getStepVector(DL, VT, NewStep); |
0 |
| 2962 |
} |
0 |
2962 |
} |
0 |
| 2963 |
|
--- |
2963 |
|
--- |
| 2964 |
// Fold a + step_vector(c1) + step_vector(c2) to a + step_vector(c1+c2) |
--- |
2964 |
// Fold a + step_vector(c1) + step_vector(c2) to a + step_vector(c1+c2) |
--- |
| 2965 |
if (N0.getOpcode() == ISD::ADD && |
0 |
2965 |
if (N0.getOpcode() == ISD::ADD && |
0 |
| 2966 |
N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR && |
0 |
2966 |
N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR && |
0 |
| 2967 |
N1.getOpcode() == ISD::STEP_VECTOR) { |
0 |
2967 |
N1.getOpcode() == ISD::STEP_VECTOR) { |
0 |
| 2968 |
const APInt &SV0 = N0.getOperand(1)->getConstantOperandAPInt(0); |
0 |
2968 |
const APInt &SV0 = N0.getOperand(1)->getConstantOperandAPInt(0); |
0 |
| 2969 |
const APInt &SV1 = N1->getConstantOperandAPInt(0); |
0 |
2969 |
const APInt &SV1 = N1->getConstantOperandAPInt(0); |
0 |
| 2970 |
APInt NewStep = SV0 + SV1; |
0 |
2970 |
APInt NewStep = SV0 + SV1; |
0 |
| 2971 |
SDValue SV = DAG.getStepVector(DL, VT, NewStep); |
0 |
2971 |
SDValue SV = DAG.getStepVector(DL, VT, NewStep); |
0 |
| 2972 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), SV); |
0 |
2972 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), SV); |
0 |
| 2973 |
} |
0 |
2973 |
} |
0 |
| 2974 |
|
--- |
2974 |
|
--- |
| 2975 |
return SDValue(); |
0 |
2975 |
return SDValue(); |
0 |
| 2976 |
} |
0 |
2976 |
} |
0 |
| 2977 |
|
--- |
2977 |
|
--- |
| 2978 |
SDValue DAGCombiner::visitADDSAT(SDNode *N) { |
0 |
2978 |
SDValue DAGCombiner::visitADDSAT(SDNode *N) { |
0 |
| 2979 |
unsigned Opcode = N->getOpcode(); |
0 |
2979 |
unsigned Opcode = N->getOpcode(); |
0 |
| 2980 |
SDValue N0 = N->getOperand(0); |
0 |
2980 |
SDValue N0 = N->getOperand(0); |
0 |
| 2981 |
SDValue N1 = N->getOperand(1); |
0 |
2981 |
SDValue N1 = N->getOperand(1); |
0 |
| 2982 |
EVT VT = N0.getValueType(); |
0 |
2982 |
EVT VT = N0.getValueType(); |
0 |
| 2983 |
bool IsSigned = Opcode == ISD::SADDSAT; |
0 |
2983 |
bool IsSigned = Opcode == ISD::SADDSAT; |
0 |
| 2984 |
SDLoc DL(N); |
0 |
2984 |
SDLoc DL(N); |
0 |
| 2985 |
|
--- |
2985 |
|
--- |
| 2986 |
// fold (add_sat x, undef) -> -1 |
--- |
2986 |
// fold (add_sat x, undef) -> -1 |
--- |
| 2987 |
if (N0.isUndef() || N1.isUndef()) |
0 |
2987 |
if (N0.isUndef() || N1.isUndef()) |
0 |
| 2988 |
return DAG.getAllOnesConstant(DL, VT); |
0 |
2988 |
return DAG.getAllOnesConstant(DL, VT); |
0 |
| 2989 |
|
--- |
2989 |
|
--- |
| 2990 |
// fold (add_sat c1, c2) -> c3 |
--- |
2990 |
// fold (add_sat c1, c2) -> c3 |
--- |
| 2991 |
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1})) |
0 |
2991 |
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1})) |
0 |
| 2992 |
return C; |
0 |
2992 |
return C; |
0 |
| 2993 |
|
--- |
2993 |
|
--- |
| 2994 |
// canonicalize constant to RHS |
--- |
2994 |
// canonicalize constant to RHS |
--- |
| 2995 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
2995 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 2996 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
2996 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 2997 |
return DAG.getNode(Opcode, DL, VT, N1, N0); |
0 |
2997 |
return DAG.getNode(Opcode, DL, VT, N1, N0); |
0 |
| 2998 |
|
--- |
2998 |
|
--- |
| 2999 |
// fold vector ops |
--- |
2999 |
// fold vector ops |
--- |
| 3000 |
if (VT.isVector()) { |
0 |
3000 |
if (VT.isVector()) { |
0 |
| 3001 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
3001 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 3002 |
return FoldedVOp; |
0 |
3002 |
return FoldedVOp; |
0 |
| 3003 |
|
--- |
3003 |
|
--- |
| 3004 |
// fold (add_sat x, 0) -> x, vector edition |
--- |
3004 |
// fold (add_sat x, 0) -> x, vector edition |
--- |
| 3005 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
3005 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
| 3006 |
return N0; |
0 |
3006 |
return N0; |
0 |
| 3007 |
} |
--- |
3007 |
} |
--- |
| 3008 |
|
--- |
3008 |
|
--- |
| 3009 |
// fold (add_sat x, 0) -> x |
--- |
3009 |
// fold (add_sat x, 0) -> x |
--- |
| 3010 |
if (isNullConstant(N1)) |
0 |
3010 |
if (isNullConstant(N1)) |
0 |
| 3011 |
return N0; |
0 |
3011 |
return N0; |
0 |
| 3012 |
|
--- |
3012 |
|
--- |
| 3013 |
// If it cannot overflow, transform into an add. |
--- |
3013 |
// If it cannot overflow, transform into an add. |
--- |
| 3014 |
if (DAG.computeOverflowForAdd(IsSigned, N0, N1) == SelectionDAG::OFK_Never) |
0 |
3014 |
if (DAG.computeOverflowForAdd(IsSigned, N0, N1) == SelectionDAG::OFK_Never) |
0 |
| 3015 |
return DAG.getNode(ISD::ADD, DL, VT, N0, N1); |
0 |
3015 |
return DAG.getNode(ISD::ADD, DL, VT, N0, N1); |
0 |
| 3016 |
|
--- |
3016 |
|
--- |
| 3017 |
return SDValue(); |
0 |
3017 |
return SDValue(); |
0 |
| 3018 |
} |
0 |
3018 |
} |
0 |
| 3019 |
|
--- |
3019 |
|
--- |
| 3020 |
static SDValue getAsCarry(const TargetLowering &TLI, SDValue V, |
1 |
3020 |
static SDValue getAsCarry(const TargetLowering &TLI, SDValue V, |
1 |
| 3021 |
bool ForceCarryReconstruction = false) { |
--- |
3021 |
bool ForceCarryReconstruction = false) { |
--- |
| 3022 |
bool Masked = false; |
1 |
3022 |
bool Masked = false; |
1 |
| 3023 |
|
--- |
3023 |
|
--- |
| 3024 |
// First, peel away TRUNCATE/ZERO_EXTEND/AND nodes due to legalization. |
--- |
3024 |
// First, peel away TRUNCATE/ZERO_EXTEND/AND nodes due to legalization. |
--- |
| 3025 |
while (true) { |
--- |
3025 |
while (true) { |
--- |
| 3026 |
if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) { |
1 |
3026 |
if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) { |
1 |
| 3027 |
V = V.getOperand(0); |
0 |
3027 |
V = V.getOperand(0); |
0 |
| 3028 |
continue; |
0 |
3028 |
continue; |
0 |
| 3029 |
} |
--- |
3029 |
} |
--- |
| 3030 |
|
--- |
3030 |
|
--- |
| 3031 |
if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) { |
1 |
3031 |
if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) { |
1 |
| 3032 |
if (ForceCarryReconstruction) |
0 |
3032 |
if (ForceCarryReconstruction) |
0 |
| 3033 |
return V; |
0 |
3033 |
return V; |
0 |
| 3034 |
|
--- |
3034 |
|
--- |
| 3035 |
Masked = true; |
0 |
3035 |
Masked = true; |
0 |
| 3036 |
V = V.getOperand(0); |
0 |
3036 |
V = V.getOperand(0); |
0 |
| 3037 |
continue; |
0 |
3037 |
continue; |
0 |
| 3038 |
} |
--- |
3038 |
} |
--- |
| 3039 |
|
--- |
3039 |
|
--- |
| 3040 |
if (ForceCarryReconstruction && V.getValueType() == MVT::i1) |
1 |
3040 |
if (ForceCarryReconstruction && V.getValueType() == MVT::i1) |
1 |
| 3041 |
return V; |
0 |
3041 |
return V; |
0 |
| 3042 |
|
--- |
3042 |
|
--- |
| 3043 |
break; |
1 |
3043 |
break; |
1 |
| 3044 |
} |
--- |
3044 |
} |
--- |
| 3045 |
|
--- |
3045 |
|
--- |
| 3046 |
// If this is not a carry, return. |
--- |
3046 |
// If this is not a carry, return. |
--- |
| 3047 |
if (V.getResNo() != 1) |
1 |
3047 |
if (V.getResNo() != 1) |
1 |
| 3048 |
return SDValue(); |
1 |
3048 |
return SDValue(); |
1 |
| 3049 |
|
--- |
3049 |
|
--- |
| 3050 |
if (V.getOpcode() != ISD::UADDO_CARRY && V.getOpcode() != ISD::USUBO_CARRY && |
0 |
3050 |
if (V.getOpcode() != ISD::UADDO_CARRY && V.getOpcode() != ISD::USUBO_CARRY && |
0 |
| 3051 |
V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO) |
0 |
3051 |
V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO) |
0 |
| 3052 |
return SDValue(); |
0 |
3052 |
return SDValue(); |
0 |
| 3053 |
|
--- |
3053 |
|
--- |
| 3054 |
EVT VT = V->getValueType(0); |
0 |
3054 |
EVT VT = V->getValueType(0); |
0 |
| 3055 |
if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT)) |
0 |
3055 |
if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT)) |
0 |
| 3056 |
return SDValue(); |
0 |
3056 |
return SDValue(); |
0 |
| 3057 |
|
--- |
3057 |
|
--- |
| 3058 |
// If the result is masked, then no matter what kind of bool it is we can |
--- |
3058 |
// If the result is masked, then no matter what kind of bool it is we can |
--- |
| 3059 |
// return. If it isn't, then we need to make sure the bool type is either 0 or |
--- |
3059 |
// return. If it isn't, then we need to make sure the bool type is either 0 or |
--- |
| 3060 |
// 1 and not other values. |
--- |
3060 |
// 1 and not other values. |
--- |
| 3061 |
if (Masked || |
0 |
3061 |
if (Masked || |
0 |
| 3062 |
TLI.getBooleanContents(V.getValueType()) == |
0 |
3062 |
TLI.getBooleanContents(V.getValueType()) == |
0 |
| 3063 |
TargetLoweringBase::ZeroOrOneBooleanContent) |
--- |
3063 |
TargetLoweringBase::ZeroOrOneBooleanContent) |
--- |
| 3064 |
return V; |
0 |
3064 |
return V; |
0 |
| 3065 |
|
--- |
3065 |
|
--- |
| 3066 |
return SDValue(); |
0 |
3066 |
return SDValue(); |
0 |
| 3067 |
} |
--- |
3067 |
} |
--- |
| 3068 |
|
--- |
3068 |
|
--- |
| 3069 |
/// Given the operands of an add/sub operation, see if the 2nd operand is a |
--- |
3069 |
/// Given the operands of an add/sub operation, see if the 2nd operand is a |
--- |
| 3070 |
/// masked 0/1 whose source operand is actually known to be 0/-1. If so, invert |
--- |
3070 |
/// masked 0/1 whose source operand is actually known to be 0/-1. If so, invert |
--- |
| 3071 |
/// the opcode and bypass the mask operation. |
--- |
3071 |
/// the opcode and bypass the mask operation. |
--- |
| 3072 |
static SDValue foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1, |
2 |
3072 |
static SDValue foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1, |
2 |
| 3073 |
SelectionDAG &DAG, const SDLoc &DL) { |
--- |
3073 |
SelectionDAG &DAG, const SDLoc &DL) { |
--- |
| 3074 |
if (N1.getOpcode() == ISD::ZERO_EXTEND) |
2 |
3074 |
if (N1.getOpcode() == ISD::ZERO_EXTEND) |
2 |
| 3075 |
N1 = N1.getOperand(0); |
0 |
3075 |
N1 = N1.getOperand(0); |
0 |
| 3076 |
|
--- |
3076 |
|
--- |
| 3077 |
if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1))) |
2 |
3077 |
if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1))) |
2 |
| 3078 |
return SDValue(); |
2 |
3078 |
return SDValue(); |
2 |
| 3079 |
|
--- |
3079 |
|
--- |
| 3080 |
EVT VT = N0.getValueType(); |
0 |
3080 |
EVT VT = N0.getValueType(); |
0 |
| 3081 |
SDValue N10 = N1.getOperand(0); |
0 |
3081 |
SDValue N10 = N1.getOperand(0); |
0 |
| 3082 |
if (N10.getValueType() != VT && N10.getOpcode() == ISD::TRUNCATE) |
0 |
3082 |
if (N10.getValueType() != VT && N10.getOpcode() == ISD::TRUNCATE) |
0 |
| 3083 |
N10 = N10.getOperand(0); |
0 |
3083 |
N10 = N10.getOperand(0); |
0 |
| 3084 |
|
--- |
3084 |
|
--- |
| 3085 |
if (N10.getValueType() != VT) |
0 |
3085 |
if (N10.getValueType() != VT) |
0 |
| 3086 |
return SDValue(); |
0 |
3086 |
return SDValue(); |
0 |
| 3087 |
|
--- |
3087 |
|
--- |
| 3088 |
if (DAG.ComputeNumSignBits(N10) != VT.getScalarSizeInBits()) |
0 |
3088 |
if (DAG.ComputeNumSignBits(N10) != VT.getScalarSizeInBits()) |
0 |
| 3089 |
return SDValue(); |
0 |
3089 |
return SDValue(); |
0 |
| 3090 |
|
--- |
3090 |
|
--- |
| 3091 |
// add N0, (and (AssertSext X, i1), 1) --> sub N0, X |
--- |
3091 |
// add N0, (and (AssertSext X, i1), 1) --> sub N0, X |
--- |
| 3092 |
// sub N0, (and (AssertSext X, i1), 1) --> add N0, X |
--- |
3092 |
// sub N0, (and (AssertSext X, i1), 1) --> add N0, X |
--- |
| 3093 |
return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N10); |
0 |
3093 |
return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N10); |
0 |
| 3094 |
} |
--- |
3094 |
} |
--- |
| 3095 |
|
--- |
3095 |
|
--- |
| 3096 |
/// Helper for doing combines based on N0 and N1 being added to each other. |
--- |
3096 |
/// Helper for doing combines based on N0 and N1 being added to each other. |
--- |
| 3097 |
SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1, |
2 |
3097 |
SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1, |
2 |
| 3098 |
SDNode *LocReference) { |
--- |
3098 |
SDNode *LocReference) { |
--- |
| 3099 |
EVT VT = N0.getValueType(); |
2 |
3099 |
EVT VT = N0.getValueType(); |
2 |
| 3100 |
SDLoc DL(LocReference); |
2 |
3100 |
SDLoc DL(LocReference); |
2 |
| 3101 |
|
--- |
3101 |
|
--- |
| 3102 |
// fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) |
--- |
3102 |
// fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) |
--- |
| 3103 |
if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB && |
2 |
3103 |
if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB && |
2 |
| 3104 |
isNullOrNullSplat(N1.getOperand(0).getOperand(0))) |
0 |
3104 |
isNullOrNullSplat(N1.getOperand(0).getOperand(0))) |
0 |
| 3105 |
return DAG.getNode(ISD::SUB, DL, VT, N0, |
0 |
3105 |
return DAG.getNode(ISD::SUB, DL, VT, N0, |
0 |
| 3106 |
DAG.getNode(ISD::SHL, DL, VT, |
0 |
3106 |
DAG.getNode(ISD::SHL, DL, VT, |
0 |
| 3107 |
N1.getOperand(0).getOperand(1), |
0 |
3107 |
N1.getOperand(0).getOperand(1), |
0 |
| 3108 |
N1.getOperand(1))); |
0 |
3108 |
N1.getOperand(1))); |
0 |
| 3109 |
|
--- |
3109 |
|
--- |
| 3110 |
if (SDValue V = foldAddSubMasked1(true, N0, N1, DAG, DL)) |
2 |
3110 |
if (SDValue V = foldAddSubMasked1(true, N0, N1, DAG, DL)) |
2 |
| 3111 |
return V; |
0 |
3111 |
return V; |
0 |
| 3112 |
|
--- |
3112 |
|
--- |
| 3113 |
// Look for: |
--- |
3113 |
// Look for: |
--- |
| 3114 |
// add (add x, 1), y |
--- |
3114 |
// add (add x, 1), y |
--- |
| 3115 |
// And if the target does not like this form then turn into: |
--- |
3115 |
// And if the target does not like this form then turn into: |
--- |
| 3116 |
// sub y, (xor x, -1) |
--- |
3116 |
// sub y, (xor x, -1) |
--- |
| 3117 |
if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD && |
2 |
3117 |
if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD && |
2 |
| 3118 |
N0.hasOneUse() && isOneOrOneSplat(N0.getOperand(1)) && |
2 |
3118 |
N0.hasOneUse() && isOneOrOneSplat(N0.getOperand(1)) && |
2 |
| 3119 |
// Limit this to after legalization if the add has wrap flags |
--- |
3119 |
// Limit this to after legalization if the add has wrap flags |
--- |
| 3120 |
(Level >= AfterLegalizeDAG || (!N0->getFlags().hasNoUnsignedWrap() && |
0 |
3120 |
(Level >= AfterLegalizeDAG || (!N0->getFlags().hasNoUnsignedWrap() && |
0 |
| 3121 |
!N0->getFlags().hasNoSignedWrap()))) { |
2 |
3121 |
!N0->getFlags().hasNoSignedWrap()))) { |
2 |
| 3122 |
SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0), |
0 |
3122 |
SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0), |
0 |
| 3123 |
DAG.getAllOnesConstant(DL, VT)); |
0 |
3123 |
DAG.getAllOnesConstant(DL, VT)); |
0 |
| 3124 |
return DAG.getNode(ISD::SUB, DL, VT, N1, Not); |
0 |
3124 |
return DAG.getNode(ISD::SUB, DL, VT, N1, Not); |
0 |
| 3125 |
} |
--- |
3125 |
} |
--- |
| 3126 |
|
--- |
3126 |
|
--- |
| 3127 |
if (N0.getOpcode() == ISD::SUB && N0.hasOneUse()) { |
2 |
3127 |
if (N0.getOpcode() == ISD::SUB && N0.hasOneUse()) { |
2 |
| 3128 |
// Hoist one-use subtraction by non-opaque constant: |
--- |
3128 |
// Hoist one-use subtraction by non-opaque constant: |
--- |
| 3129 |
// (x - C) + y -> (x + y) - C |
--- |
3129 |
// (x - C) + y -> (x + y) - C |
--- |
| 3130 |
// This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors. |
--- |
3130 |
// This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors. |
--- |
| 3131 |
if (isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) { |
0 |
3131 |
if (isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) { |
0 |
| 3132 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), N1); |
0 |
3132 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), N1); |
0 |
| 3133 |
return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1)); |
0 |
3133 |
return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1)); |
0 |
| 3134 |
} |
--- |
3134 |
} |
--- |
| 3135 |
// Hoist one-use subtraction from non-opaque constant: |
--- |
3135 |
// Hoist one-use subtraction from non-opaque constant: |
--- |
| 3136 |
// (C - x) + y -> (y - x) + C |
--- |
3136 |
// (C - x) + y -> (y - x) + C |
--- |
| 3137 |
if (isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) { |
0 |
3137 |
if (isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) { |
0 |
| 3138 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1)); |
0 |
3138 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1)); |
0 |
| 3139 |
return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(0)); |
0 |
3139 |
return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(0)); |
0 |
| 3140 |
} |
--- |
3140 |
} |
--- |
| 3141 |
} |
--- |
3141 |
} |
--- |
| 3142 |
|
--- |
3142 |
|
--- |
| 3143 |
// add (mul x, C), x -> mul x, C+1 |
--- |
3143 |
// add (mul x, C), x -> mul x, C+1 |
--- |
| 3144 |
if (N0.getOpcode() == ISD::MUL && N0.getOperand(0) == N1 && |
2 |
3144 |
if (N0.getOpcode() == ISD::MUL && N0.getOperand(0) == N1 && |
2 |
| 3145 |
isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true) && |
2 |
3145 |
isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true) && |
2 |
| 3146 |
N0.hasOneUse()) { |
0 |
3146 |
N0.hasOneUse()) { |
0 |
| 3147 |
SDValue NewC = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), |
0 |
3147 |
SDValue NewC = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), |
0 |
| 3148 |
DAG.getConstant(1, DL, VT)); |
0 |
3148 |
DAG.getConstant(1, DL, VT)); |
0 |
| 3149 |
return DAG.getNode(ISD::MUL, DL, VT, N0.getOperand(0), NewC); |
0 |
3149 |
return DAG.getNode(ISD::MUL, DL, VT, N0.getOperand(0), NewC); |
0 |
| 3150 |
} |
--- |
3150 |
} |
--- |
| 3151 |
|
--- |
3151 |
|
--- |
| 3152 |
// If the target's bool is represented as 0/1, prefer to make this 'sub 0/1' |
--- |
3152 |
// If the target's bool is represented as 0/1, prefer to make this 'sub 0/1' |
--- |
| 3153 |
// rather than 'add 0/-1' (the zext should get folded). |
--- |
3153 |
// rather than 'add 0/-1' (the zext should get folded). |
--- |
| 3154 |
// add (sext i1 Y), X --> sub X, (zext i1 Y) |
--- |
3154 |
// add (sext i1 Y), X --> sub X, (zext i1 Y) |
--- |
| 3155 |
if (N0.getOpcode() == ISD::SIGN_EXTEND && |
2 |
3155 |
if (N0.getOpcode() == ISD::SIGN_EXTEND && |
2 |
| 3156 |
N0.getOperand(0).getScalarValueSizeInBits() == 1 && |
2 |
3156 |
N0.getOperand(0).getScalarValueSizeInBits() == 1 && |
2 |
| 3157 |
TLI.getBooleanContents(VT) == TargetLowering::ZeroOrOneBooleanContent) { |
0 |
3157 |
TLI.getBooleanContents(VT) == TargetLowering::ZeroOrOneBooleanContent) { |
0 |
| 3158 |
SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); |
0 |
3158 |
SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); |
0 |
| 3159 |
return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); |
0 |
3159 |
return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); |
0 |
| 3160 |
} |
--- |
3160 |
} |
--- |
| 3161 |
|
--- |
3161 |
|
--- |
| 3162 |
// add X, (sextinreg Y i1) -> sub X, (and Y 1) |
--- |
3162 |
// add X, (sextinreg Y i1) -> sub X, (and Y 1) |
--- |
| 3163 |
if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { |
2 |
3163 |
if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { |
2 |
| 3164 |
VTSDNode *TN = cast(N1.getOperand(1)); |
0 |
3164 |
VTSDNode *TN = cast(N1.getOperand(1)); |
0 |
| 3165 |
if (TN->getVT() == MVT::i1) { |
0 |
3165 |
if (TN->getVT() == MVT::i1) { |
0 |
| 3166 |
SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0), |
0 |
3166 |
SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0), |
0 |
| 3167 |
DAG.getConstant(1, DL, VT)); |
0 |
3167 |
DAG.getConstant(1, DL, VT)); |
0 |
| 3168 |
return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt); |
0 |
3168 |
return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt); |
0 |
| 3169 |
} |
--- |
3169 |
} |
--- |
| 3170 |
} |
--- |
3170 |
} |
--- |
| 3171 |
|
--- |
3171 |
|
--- |
| 3172 |
// (add X, (uaddo_carry Y, 0, Carry)) -> (uaddo_carry X, Y, Carry) |
--- |
3172 |
// (add X, (uaddo_carry Y, 0, Carry)) -> (uaddo_carry X, Y, Carry) |
--- |
| 3173 |
if (N1.getOpcode() == ISD::UADDO_CARRY && isNullConstant(N1.getOperand(1)) && |
2 |
3173 |
if (N1.getOpcode() == ISD::UADDO_CARRY && isNullConstant(N1.getOperand(1)) && |
2 |
| 3174 |
N1.getResNo() == 0) |
0 |
3174 |
N1.getResNo() == 0) |
0 |
| 3175 |
return DAG.getNode(ISD::UADDO_CARRY, DL, N1->getVTList(), |
0 |
3175 |
return DAG.getNode(ISD::UADDO_CARRY, DL, N1->getVTList(), |
0 |
| 3176 |
N0, N1.getOperand(0), N1.getOperand(2)); |
0 |
3176 |
N0, N1.getOperand(0), N1.getOperand(2)); |
0 |
| 3177 |
|
--- |
3177 |
|
--- |
| 3178 |
// (add X, Carry) -> (uaddo_carry X, 0, Carry) |
--- |
3178 |
// (add X, Carry) -> (uaddo_carry X, 0, Carry) |
--- |
| 3179 |
if (TLI.isOperationLegalOrCustom(ISD::UADDO_CARRY, VT)) |
2 |
3179 |
if (TLI.isOperationLegalOrCustom(ISD::UADDO_CARRY, VT)) |
2 |
| 3180 |
if (SDValue Carry = getAsCarry(TLI, N1)) |
0 |
3180 |
if (SDValue Carry = getAsCarry(TLI, N1)) |
0 |
| 3181 |
return DAG.getNode(ISD::UADDO_CARRY, DL, |
0 |
3181 |
return DAG.getNode(ISD::UADDO_CARRY, DL, |
0 |
| 3182 |
DAG.getVTList(VT, Carry.getValueType()), N0, |
0 |
3182 |
DAG.getVTList(VT, Carry.getValueType()), N0, |
0 |
| 3183 |
DAG.getConstant(0, DL, VT), Carry); |
0 |
3183 |
DAG.getConstant(0, DL, VT), Carry); |
0 |
| 3184 |
|
--- |
3184 |
|
--- |
| 3185 |
return SDValue(); |
2 |
3185 |
return SDValue(); |
2 |
| 3186 |
} |
2 |
3186 |
} |
2 |
| 3187 |
|
--- |
3187 |
|
--- |
| 3188 |
SDValue DAGCombiner::visitADDC(SDNode *N) { |
0 |
3188 |
SDValue DAGCombiner::visitADDC(SDNode *N) { |
0 |
| 3189 |
SDValue N0 = N->getOperand(0); |
0 |
3189 |
SDValue N0 = N->getOperand(0); |
0 |
| 3190 |
SDValue N1 = N->getOperand(1); |
0 |
3190 |
SDValue N1 = N->getOperand(1); |
0 |
| 3191 |
EVT VT = N0.getValueType(); |
0 |
3191 |
EVT VT = N0.getValueType(); |
0 |
| 3192 |
SDLoc DL(N); |
0 |
3192 |
SDLoc DL(N); |
0 |
| 3193 |
|
--- |
3193 |
|
--- |
| 3194 |
// If the flag result is dead, turn this into an ADD. |
--- |
3194 |
// If the flag result is dead, turn this into an ADD. |
--- |
| 3195 |
if (!N->hasAnyUseOfValue(1)) |
0 |
3195 |
if (!N->hasAnyUseOfValue(1)) |
0 |
| 3196 |
return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1), |
0 |
3196 |
return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1), |
0 |
| 3197 |
DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue)); |
0 |
3197 |
DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue)); |
0 |
| 3198 |
|
--- |
3198 |
|
--- |
| 3199 |
// canonicalize constant to RHS. |
--- |
3199 |
// canonicalize constant to RHS. |
--- |
| 3200 |
ConstantSDNode *N0C = dyn_cast(N0); |
0 |
3200 |
ConstantSDNode *N0C = dyn_cast(N0); |
0 |
| 3201 |
ConstantSDNode *N1C = dyn_cast(N1); |
0 |
3201 |
ConstantSDNode *N1C = dyn_cast(N1); |
0 |
| 3202 |
if (N0C && !N1C) |
0 |
3202 |
if (N0C && !N1C) |
0 |
| 3203 |
return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0); |
0 |
3203 |
return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0); |
0 |
| 3204 |
|
--- |
3204 |
|
--- |
| 3205 |
// fold (addc x, 0) -> x + no carry out |
--- |
3205 |
// fold (addc x, 0) -> x + no carry out |
--- |
| 3206 |
if (isNullConstant(N1)) |
0 |
3206 |
if (isNullConstant(N1)) |
0 |
| 3207 |
return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, |
0 |
3207 |
return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, |
0 |
| 3208 |
DL, MVT::Glue)); |
0 |
3208 |
DL, MVT::Glue)); |
0 |
| 3209 |
|
--- |
3209 |
|
--- |
| 3210 |
// If it cannot overflow, transform into an add. |
--- |
3210 |
// If it cannot overflow, transform into an add. |
--- |
| 3211 |
if (DAG.computeOverflowForUnsignedAdd(N0, N1) == SelectionDAG::OFK_Never) |
0 |
3211 |
if (DAG.computeOverflowForUnsignedAdd(N0, N1) == SelectionDAG::OFK_Never) |
0 |
| 3212 |
return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1), |
0 |
3212 |
return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1), |
0 |
| 3213 |
DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue)); |
0 |
3213 |
DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue)); |
0 |
| 3214 |
|
--- |
3214 |
|
--- |
| 3215 |
return SDValue(); |
0 |
3215 |
return SDValue(); |
0 |
| 3216 |
} |
0 |
3216 |
} |
0 |
| 3217 |
|
--- |
3217 |
|
--- |
| 3218 |
/** |
--- |
3218 |
/** |
--- |
| 3219 |
* Flips a boolean if it is cheaper to compute. If the Force parameters is set, |
--- |
3219 |
* Flips a boolean if it is cheaper to compute. If the Force parameters is set, |
--- |
| 3220 |
* then the flip also occurs if computing the inverse is the same cost. |
--- |
3220 |
* then the flip also occurs if computing the inverse is the same cost. |
--- |
| 3221 |
* This function returns an empty SDValue in case it cannot flip the boolean |
--- |
3221 |
* This function returns an empty SDValue in case it cannot flip the boolean |
--- |
| 3222 |
* without increasing the cost of the computation. If you want to flip a boolean |
--- |
3222 |
* without increasing the cost of the computation. If you want to flip a boolean |
--- |
| 3223 |
* no matter what, use DAG.getLogicalNOT. |
--- |
3223 |
* no matter what, use DAG.getLogicalNOT. |
--- |
| 3224 |
*/ |
--- |
3224 |
*/ |
--- |
| 3225 |
static SDValue extractBooleanFlip(SDValue V, SelectionDAG &DAG, |
0 |
3225 |
static SDValue extractBooleanFlip(SDValue V, SelectionDAG &DAG, |
0 |
| 3226 |
const TargetLowering &TLI, |
--- |
3226 |
const TargetLowering &TLI, |
--- |
| 3227 |
bool Force) { |
--- |
3227 |
bool Force) { |
--- |
| 3228 |
if (Force && isa(V)) |
0 |
3228 |
if (Force && isa(V)) |
0 |
| 3229 |
return DAG.getLogicalNOT(SDLoc(V), V, V.getValueType()); |
0 |
3229 |
return DAG.getLogicalNOT(SDLoc(V), V, V.getValueType()); |
0 |
| 3230 |
|
--- |
3230 |
|
--- |
| 3231 |
if (V.getOpcode() != ISD::XOR) |
0 |
3231 |
if (V.getOpcode() != ISD::XOR) |
0 |
| 3232 |
return SDValue(); |
0 |
3232 |
return SDValue(); |
0 |
| 3233 |
|
--- |
3233 |
|
--- |
| 3234 |
ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false); |
0 |
3234 |
ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false); |
0 |
| 3235 |
if (!Const) |
0 |
3235 |
if (!Const) |
0 |
| 3236 |
return SDValue(); |
0 |
3236 |
return SDValue(); |
0 |
| 3237 |
|
--- |
3237 |
|
--- |
| 3238 |
EVT VT = V.getValueType(); |
0 |
3238 |
EVT VT = V.getValueType(); |
0 |
| 3239 |
|
--- |
3239 |
|
--- |
| 3240 |
bool IsFlip = false; |
0 |
3240 |
bool IsFlip = false; |
0 |
| 3241 |
switch(TLI.getBooleanContents(VT)) { |
0 |
3241 |
switch(TLI.getBooleanContents(VT)) { |
0 |
| 3242 |
case TargetLowering::ZeroOrOneBooleanContent: |
0 |
3242 |
case TargetLowering::ZeroOrOneBooleanContent: |
0 |
| 3243 |
IsFlip = Const->isOne(); |
0 |
3243 |
IsFlip = Const->isOne(); |
0 |
| 3244 |
break; |
0 |
3244 |
break; |
0 |
| 3245 |
case TargetLowering::ZeroOrNegativeOneBooleanContent: |
0 |
3245 |
case TargetLowering::ZeroOrNegativeOneBooleanContent: |
0 |
| 3246 |
IsFlip = Const->isAllOnes(); |
0 |
3246 |
IsFlip = Const->isAllOnes(); |
0 |
| 3247 |
break; |
0 |
3247 |
break; |
0 |
| 3248 |
case TargetLowering::UndefinedBooleanContent: |
0 |
3248 |
case TargetLowering::UndefinedBooleanContent: |
0 |
| 3249 |
IsFlip = (Const->getAPIntValue() & 0x01) == 1; |
0 |
3249 |
IsFlip = (Const->getAPIntValue() & 0x01) == 1; |
0 |
| 3250 |
break; |
0 |
3250 |
break; |
0 |
| 3251 |
} |
--- |
3251 |
} |
--- |
| 3252 |
|
--- |
3252 |
|
--- |
| 3253 |
if (IsFlip) |
0 |
3253 |
if (IsFlip) |
0 |
| 3254 |
return V.getOperand(0); |
0 |
3254 |
return V.getOperand(0); |
0 |
| 3255 |
if (Force) |
0 |
3255 |
if (Force) |
0 |
| 3256 |
return DAG.getLogicalNOT(SDLoc(V), V, V.getValueType()); |
0 |
3256 |
return DAG.getLogicalNOT(SDLoc(V), V, V.getValueType()); |
0 |
| 3257 |
return SDValue(); |
0 |
3257 |
return SDValue(); |
0 |
| 3258 |
} |
--- |
3258 |
} |
--- |
| 3259 |
|
--- |
3259 |
|
--- |
| 3260 |
SDValue DAGCombiner::visitADDO(SDNode *N) { |
0 |
3260 |
SDValue DAGCombiner::visitADDO(SDNode *N) { |
0 |
| 3261 |
SDValue N0 = N->getOperand(0); |
0 |
3261 |
SDValue N0 = N->getOperand(0); |
0 |
| 3262 |
SDValue N1 = N->getOperand(1); |
0 |
3262 |
SDValue N1 = N->getOperand(1); |
0 |
| 3263 |
EVT VT = N0.getValueType(); |
0 |
3263 |
EVT VT = N0.getValueType(); |
0 |
| 3264 |
bool IsSigned = (ISD::SADDO == N->getOpcode()); |
0 |
3264 |
bool IsSigned = (ISD::SADDO == N->getOpcode()); |
0 |
| 3265 |
|
--- |
3265 |
|
--- |
| 3266 |
EVT CarryVT = N->getValueType(1); |
0 |
3266 |
EVT CarryVT = N->getValueType(1); |
0 |
| 3267 |
SDLoc DL(N); |
0 |
3267 |
SDLoc DL(N); |
0 |
| 3268 |
|
--- |
3268 |
|
--- |
| 3269 |
// If the flag result is dead, turn this into an ADD. |
--- |
3269 |
// If the flag result is dead, turn this into an ADD. |
--- |
| 3270 |
if (!N->hasAnyUseOfValue(1)) |
0 |
3270 |
if (!N->hasAnyUseOfValue(1)) |
0 |
| 3271 |
return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1), |
0 |
3271 |
return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1), |
0 |
| 3272 |
DAG.getUNDEF(CarryVT)); |
0 |
3272 |
DAG.getUNDEF(CarryVT)); |
0 |
| 3273 |
|
--- |
3273 |
|
--- |
| 3274 |
// canonicalize constant to RHS. |
--- |
3274 |
// canonicalize constant to RHS. |
--- |
| 3275 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
3275 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 3276 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
3276 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 3277 |
return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); |
0 |
3277 |
return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); |
0 |
| 3278 |
|
--- |
3278 |
|
--- |
| 3279 |
// fold (addo x, 0) -> x + no carry out |
--- |
3279 |
// fold (addo x, 0) -> x + no carry out |
--- |
| 3280 |
if (isNullOrNullSplat(N1)) |
0 |
3280 |
if (isNullOrNullSplat(N1)) |
0 |
| 3281 |
return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT)); |
0 |
3281 |
return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT)); |
0 |
| 3282 |
|
--- |
3282 |
|
--- |
| 3283 |
// If it cannot overflow, transform into an add. |
--- |
3283 |
// If it cannot overflow, transform into an add. |
--- |
| 3284 |
if (DAG.computeOverflowForAdd(IsSigned, N0, N1) == SelectionDAG::OFK_Never) |
0 |
3284 |
if (DAG.computeOverflowForAdd(IsSigned, N0, N1) == SelectionDAG::OFK_Never) |
0 |
| 3285 |
return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1), |
0 |
3285 |
return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1), |
0 |
| 3286 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
3286 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
| 3287 |
|
--- |
3287 |
|
--- |
| 3288 |
if (!IsSigned) { |
0 |
3288 |
if (!IsSigned) { |
0 |
| 3289 |
// fold (uaddo (xor a, -1), 1) -> (usub 0, a) and flip carry. |
--- |
3289 |
// fold (uaddo (xor a, -1), 1) -> (usub 0, a) and flip carry. |
--- |
| 3290 |
if (isBitwiseNot(N0) && isOneOrOneSplat(N1)) { |
0 |
3290 |
if (isBitwiseNot(N0) && isOneOrOneSplat(N1)) { |
0 |
| 3291 |
SDValue Sub = DAG.getNode(ISD::USUBO, DL, N->getVTList(), |
0 |
3291 |
SDValue Sub = DAG.getNode(ISD::USUBO, DL, N->getVTList(), |
0 |
| 3292 |
DAG.getConstant(0, DL, VT), N0.getOperand(0)); |
0 |
3292 |
DAG.getConstant(0, DL, VT), N0.getOperand(0)); |
0 |
| 3293 |
return CombineTo( |
0 |
3293 |
return CombineTo( |
0 |
| 3294 |
N, Sub, DAG.getLogicalNOT(DL, Sub.getValue(1), Sub->getValueType(1))); |
0 |
3294 |
N, Sub, DAG.getLogicalNOT(DL, Sub.getValue(1), Sub->getValueType(1))); |
0 |
| 3295 |
} |
--- |
3295 |
} |
--- |
| 3296 |
|
--- |
3296 |
|
--- |
| 3297 |
if (SDValue Combined = visitUADDOLike(N0, N1, N)) |
0 |
3297 |
if (SDValue Combined = visitUADDOLike(N0, N1, N)) |
0 |
| 3298 |
return Combined; |
0 |
3298 |
return Combined; |
0 |
| 3299 |
|
--- |
3299 |
|
--- |
| 3300 |
if (SDValue Combined = visitUADDOLike(N1, N0, N)) |
0 |
3300 |
if (SDValue Combined = visitUADDOLike(N1, N0, N)) |
0 |
| 3301 |
return Combined; |
0 |
3301 |
return Combined; |
0 |
| 3302 |
} |
--- |
3302 |
} |
--- |
| 3303 |
|
--- |
3303 |
|
--- |
| 3304 |
return SDValue(); |
0 |
3304 |
return SDValue(); |
0 |
| 3305 |
} |
0 |
3305 |
} |
0 |
| 3306 |
|
--- |
3306 |
|
--- |
| 3307 |
SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) { |
0 |
3307 |
SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) { |
0 |
| 3308 |
EVT VT = N0.getValueType(); |
0 |
3308 |
EVT VT = N0.getValueType(); |
0 |
| 3309 |
if (VT.isVector()) |
0 |
3309 |
if (VT.isVector()) |
0 |
| 3310 |
return SDValue(); |
0 |
3310 |
return SDValue(); |
0 |
| 3311 |
|
--- |
3311 |
|
--- |
| 3312 |
// (uaddo X, (uaddo_carry Y, 0, Carry)) -> (uaddo_carry X, Y, Carry) |
--- |
3312 |
// (uaddo X, (uaddo_carry Y, 0, Carry)) -> (uaddo_carry X, Y, Carry) |
--- |
| 3313 |
// If Y + 1 cannot overflow. |
--- |
3313 |
// If Y + 1 cannot overflow. |
--- |
| 3314 |
if (N1.getOpcode() == ISD::UADDO_CARRY && isNullConstant(N1.getOperand(1))) { |
0 |
3314 |
if (N1.getOpcode() == ISD::UADDO_CARRY && isNullConstant(N1.getOperand(1))) { |
0 |
| 3315 |
SDValue Y = N1.getOperand(0); |
0 |
3315 |
SDValue Y = N1.getOperand(0); |
0 |
| 3316 |
SDValue One = DAG.getConstant(1, SDLoc(N), Y.getValueType()); |
0 |
3316 |
SDValue One = DAG.getConstant(1, SDLoc(N), Y.getValueType()); |
0 |
| 3317 |
if (DAG.computeOverflowForUnsignedAdd(Y, One) == SelectionDAG::OFK_Never) |
0 |
3317 |
if (DAG.computeOverflowForUnsignedAdd(Y, One) == SelectionDAG::OFK_Never) |
0 |
| 3318 |
return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(), N0, Y, |
0 |
3318 |
return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(), N0, Y, |
0 |
| 3319 |
N1.getOperand(2)); |
0 |
3319 |
N1.getOperand(2)); |
0 |
| 3320 |
} |
--- |
3320 |
} |
--- |
| 3321 |
|
--- |
3321 |
|
--- |
| 3322 |
// (uaddo X, Carry) -> (uaddo_carry X, 0, Carry) |
--- |
3322 |
// (uaddo X, Carry) -> (uaddo_carry X, 0, Carry) |
--- |
| 3323 |
if (TLI.isOperationLegalOrCustom(ISD::UADDO_CARRY, VT)) |
0 |
3323 |
if (TLI.isOperationLegalOrCustom(ISD::UADDO_CARRY, VT)) |
0 |
| 3324 |
if (SDValue Carry = getAsCarry(TLI, N1)) |
0 |
3324 |
if (SDValue Carry = getAsCarry(TLI, N1)) |
0 |
| 3325 |
return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(), N0, |
0 |
3325 |
return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(), N0, |
0 |
| 3326 |
DAG.getConstant(0, SDLoc(N), VT), Carry); |
0 |
3326 |
DAG.getConstant(0, SDLoc(N), VT), Carry); |
0 |
| 3327 |
|
--- |
3327 |
|
--- |
| 3328 |
return SDValue(); |
0 |
3328 |
return SDValue(); |
0 |
| 3329 |
} |
--- |
3329 |
} |
--- |
| 3330 |
|
--- |
3330 |
|
--- |
| 3331 |
SDValue DAGCombiner::visitADDE(SDNode *N) { |
0 |
3331 |
SDValue DAGCombiner::visitADDE(SDNode *N) { |
0 |
| 3332 |
SDValue N0 = N->getOperand(0); |
0 |
3332 |
SDValue N0 = N->getOperand(0); |
0 |
| 3333 |
SDValue N1 = N->getOperand(1); |
0 |
3333 |
SDValue N1 = N->getOperand(1); |
0 |
| 3334 |
SDValue CarryIn = N->getOperand(2); |
0 |
3334 |
SDValue CarryIn = N->getOperand(2); |
0 |
| 3335 |
|
--- |
3335 |
|
--- |
| 3336 |
// canonicalize constant to RHS |
--- |
3336 |
// canonicalize constant to RHS |
--- |
| 3337 |
ConstantSDNode *N0C = dyn_cast(N0); |
0 |
3337 |
ConstantSDNode *N0C = dyn_cast(N0); |
0 |
| 3338 |
ConstantSDNode *N1C = dyn_cast(N1); |
0 |
3338 |
ConstantSDNode *N1C = dyn_cast(N1); |
0 |
| 3339 |
if (N0C && !N1C) |
0 |
3339 |
if (N0C && !N1C) |
0 |
| 3340 |
return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(), |
0 |
3340 |
return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(), |
0 |
| 3341 |
N1, N0, CarryIn); |
0 |
3341 |
N1, N0, CarryIn); |
0 |
| 3342 |
|
--- |
3342 |
|
--- |
| 3343 |
// fold (adde x, y, false) -> (addc x, y) |
--- |
3343 |
// fold (adde x, y, false) -> (addc x, y) |
--- |
| 3344 |
if (CarryIn.getOpcode() == ISD::CARRY_FALSE) |
0 |
3344 |
if (CarryIn.getOpcode() == ISD::CARRY_FALSE) |
0 |
| 3345 |
return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1); |
0 |
3345 |
return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1); |
0 |
| 3346 |
|
--- |
3346 |
|
--- |
| 3347 |
return SDValue(); |
0 |
3347 |
return SDValue(); |
0 |
| 3348 |
} |
--- |
3348 |
} |
--- |
| 3349 |
|
--- |
3349 |
|
--- |
| 3350 |
SDValue DAGCombiner::visitUADDO_CARRY(SDNode *N) { |
0 |
3350 |
SDValue DAGCombiner::visitUADDO_CARRY(SDNode *N) { |
0 |
| 3351 |
SDValue N0 = N->getOperand(0); |
0 |
3351 |
SDValue N0 = N->getOperand(0); |
0 |
| 3352 |
SDValue N1 = N->getOperand(1); |
0 |
3352 |
SDValue N1 = N->getOperand(1); |
0 |
| 3353 |
SDValue CarryIn = N->getOperand(2); |
0 |
3353 |
SDValue CarryIn = N->getOperand(2); |
0 |
| 3354 |
SDLoc DL(N); |
0 |
3354 |
SDLoc DL(N); |
0 |
| 3355 |
|
--- |
3355 |
|
--- |
| 3356 |
// canonicalize constant to RHS |
--- |
3356 |
// canonicalize constant to RHS |
--- |
| 3357 |
ConstantSDNode *N0C = dyn_cast(N0); |
0 |
3357 |
ConstantSDNode *N0C = dyn_cast(N0); |
0 |
| 3358 |
ConstantSDNode *N1C = dyn_cast(N1); |
0 |
3358 |
ConstantSDNode *N1C = dyn_cast(N1); |
0 |
| 3359 |
if (N0C && !N1C) |
0 |
3359 |
if (N0C && !N1C) |
0 |
| 3360 |
return DAG.getNode(ISD::UADDO_CARRY, DL, N->getVTList(), N1, N0, CarryIn); |
0 |
3360 |
return DAG.getNode(ISD::UADDO_CARRY, DL, N->getVTList(), N1, N0, CarryIn); |
0 |
| 3361 |
|
--- |
3361 |
|
--- |
| 3362 |
// fold (uaddo_carry x, y, false) -> (uaddo x, y) |
--- |
3362 |
// fold (uaddo_carry x, y, false) -> (uaddo x, y) |
--- |
| 3363 |
if (isNullConstant(CarryIn)) { |
0 |
3363 |
if (isNullConstant(CarryIn)) { |
0 |
| 3364 |
if (!LegalOperations || |
0 |
3364 |
if (!LegalOperations || |
0 |
| 3365 |
TLI.isOperationLegalOrCustom(ISD::UADDO, N->getValueType(0))) |
0 |
3365 |
TLI.isOperationLegalOrCustom(ISD::UADDO, N->getValueType(0))) |
0 |
| 3366 |
return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1); |
0 |
3366 |
return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1); |
0 |
| 3367 |
} |
--- |
3367 |
} |
--- |
| 3368 |
|
--- |
3368 |
|
--- |
| 3369 |
// fold (uaddo_carry 0, 0, X) -> (and (ext/trunc X), 1) and no carry. |
--- |
3369 |
// fold (uaddo_carry 0, 0, X) -> (and (ext/trunc X), 1) and no carry. |
--- |
| 3370 |
if (isNullConstant(N0) && isNullConstant(N1)) { |
0 |
3370 |
if (isNullConstant(N0) && isNullConstant(N1)) { |
0 |
| 3371 |
EVT VT = N0.getValueType(); |
0 |
3371 |
EVT VT = N0.getValueType(); |
0 |
| 3372 |
EVT CarryVT = CarryIn.getValueType(); |
0 |
3372 |
EVT CarryVT = CarryIn.getValueType(); |
0 |
| 3373 |
SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT); |
0 |
3373 |
SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT); |
0 |
| 3374 |
AddToWorklist(CarryExt.getNode()); |
0 |
3374 |
AddToWorklist(CarryExt.getNode()); |
0 |
| 3375 |
return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt, |
0 |
3375 |
return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt, |
0 |
| 3376 |
DAG.getConstant(1, DL, VT)), |
0 |
3376 |
DAG.getConstant(1, DL, VT)), |
0 |
| 3377 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
3377 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
| 3378 |
} |
--- |
3378 |
} |
--- |
| 3379 |
|
--- |
3379 |
|
--- |
| 3380 |
if (SDValue Combined = visitUADDO_CARRYLike(N0, N1, CarryIn, N)) |
0 |
3380 |
if (SDValue Combined = visitUADDO_CARRYLike(N0, N1, CarryIn, N)) |
0 |
| 3381 |
return Combined; |
0 |
3381 |
return Combined; |
0 |
| 3382 |
|
--- |
3382 |
|
--- |
| 3383 |
if (SDValue Combined = visitUADDO_CARRYLike(N1, N0, CarryIn, N)) |
0 |
3383 |
if (SDValue Combined = visitUADDO_CARRYLike(N1, N0, CarryIn, N)) |
0 |
| 3384 |
return Combined; |
0 |
3384 |
return Combined; |
0 |
| 3385 |
|
--- |
3385 |
|
--- |
| 3386 |
// We want to avoid useless duplication. |
--- |
3386 |
// We want to avoid useless duplication. |
--- |
| 3387 |
// TODO: This is done automatically for binary operations. As UADDO_CARRY is |
--- |
3387 |
// TODO: This is done automatically for binary operations. As UADDO_CARRY is |
--- |
| 3388 |
// not a binary operation, this is not really possible to leverage this |
--- |
3388 |
// not a binary operation, this is not really possible to leverage this |
--- |
| 3389 |
// existing mechanism for it. However, if more operations require the same |
--- |
3389 |
// existing mechanism for it. However, if more operations require the same |
--- |
| 3390 |
// deduplication logic, then it may be worth generalize. |
--- |
3390 |
// deduplication logic, then it may be worth generalize. |
--- |
| 3391 |
SDValue Ops[] = {N1, N0, CarryIn}; |
0 |
3391 |
SDValue Ops[] = {N1, N0, CarryIn}; |
0 |
| 3392 |
SDNode *CSENode = |
--- |
3392 |
SDNode *CSENode = |
--- |
| 3393 |
DAG.getNodeIfExists(ISD::UADDO_CARRY, N->getVTList(), Ops, N->getFlags()); |
0 |
3393 |
DAG.getNodeIfExists(ISD::UADDO_CARRY, N->getVTList(), Ops, N->getFlags()); |
0 |
| 3394 |
if (CSENode) |
0 |
3394 |
if (CSENode) |
0 |
| 3395 |
return SDValue(CSENode, 0); |
0 |
3395 |
return SDValue(CSENode, 0); |
0 |
| 3396 |
|
--- |
3396 |
|
--- |
| 3397 |
return SDValue(); |
0 |
3397 |
return SDValue(); |
0 |
| 3398 |
} |
0 |
3398 |
} |
0 |
| 3399 |
|
--- |
3399 |
|
--- |
| 3400 |
/** |
--- |
3400 |
/** |
--- |
| 3401 |
* If we are facing some sort of diamond carry propapagtion pattern try to |
--- |
3401 |
* If we are facing some sort of diamond carry propapagtion pattern try to |
--- |
| 3402 |
* break it up to generate something like: |
--- |
3402 |
* break it up to generate something like: |
--- |
| 3403 |
* (uaddo_carry X, 0, (uaddo_carry A, B, Z):Carry) |
--- |
3403 |
* (uaddo_carry X, 0, (uaddo_carry A, B, Z):Carry) |
--- |
| 3404 |
* |
--- |
3404 |
* |
--- |
| 3405 |
* The end result is usually an increase in operation required, but because the |
--- |
3405 |
* The end result is usually an increase in operation required, but because the |
--- |
| 3406 |
* carry is now linearized, other transforms can kick in and optimize the DAG. |
--- |
3406 |
* carry is now linearized, other transforms can kick in and optimize the DAG. |
--- |
| 3407 |
* |
--- |
3407 |
* |
--- |
| 3408 |
* Patterns typically look something like |
--- |
3408 |
* Patterns typically look something like |
--- |
| 3409 |
* (uaddo A, B) |
--- |
3409 |
* (uaddo A, B) |
--- |
| 3410 |
* / \ |
--- |
3410 |
* / \ |
--- |
| 3411 |
* Carry Sum |
--- |
3411 |
* Carry Sum |
--- |
| 3412 |
* | \ |
--- |
3412 |
* | \ |
--- |
| 3413 |
* | (uaddo_carry *, 0, Z) |
--- |
3413 |
* | (uaddo_carry *, 0, Z) |
--- |
| 3414 |
* | / |
--- |
3414 |
* | / |
--- |
| 3415 |
* \ Carry |
--- |
3415 |
* \ Carry |
--- |
| 3416 |
* | / |
--- |
3416 |
* | / |
--- |
| 3417 |
* (uaddo_carry X, *, *) |
--- |
3417 |
* (uaddo_carry X, *, *) |
--- |
| 3418 |
* |
--- |
3418 |
* |
--- |
| 3419 |
* But numerous variation exist. Our goal is to identify A, B, X and Z and |
--- |
3419 |
* But numerous variation exist. Our goal is to identify A, B, X and Z and |
--- |
| 3420 |
* produce a combine with a single path for carry propagation. |
--- |
3420 |
* produce a combine with a single path for carry propagation. |
--- |
| 3421 |
*/ |
--- |
3421 |
*/ |
--- |
| 3422 |
static SDValue combineUADDO_CARRYDiamond(DAGCombiner &Combiner, |
0 |
3422 |
static SDValue combineUADDO_CARRYDiamond(DAGCombiner &Combiner, |
0 |
| 3423 |
SelectionDAG &DAG, SDValue X, |
--- |
3423 |
SelectionDAG &DAG, SDValue X, |
--- |
| 3424 |
SDValue Carry0, SDValue Carry1, |
--- |
3424 |
SDValue Carry0, SDValue Carry1, |
--- |
| 3425 |
SDNode *N) { |
--- |
3425 |
SDNode *N) { |
--- |
| 3426 |
if (Carry1.getResNo() != 1 || Carry0.getResNo() != 1) |
0 |
3426 |
if (Carry1.getResNo() != 1 || Carry0.getResNo() != 1) |
0 |
| 3427 |
return SDValue(); |
0 |
3427 |
return SDValue(); |
0 |
| 3428 |
if (Carry1.getOpcode() != ISD::UADDO) |
0 |
3428 |
if (Carry1.getOpcode() != ISD::UADDO) |
0 |
| 3429 |
return SDValue(); |
0 |
3429 |
return SDValue(); |
0 |
| 3430 |
|
--- |
3430 |
|
--- |
| 3431 |
SDValue Z; |
0 |
3431 |
SDValue Z; |
0 |
| 3432 |
|
--- |
3432 |
|
--- |
| 3433 |
/** |
--- |
3433 |
/** |
--- |
| 3434 |
* First look for a suitable Z. It will present itself in the form of |
--- |
3434 |
* First look for a suitable Z. It will present itself in the form of |
--- |
| 3435 |
* (uaddo_carry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true |
--- |
3435 |
* (uaddo_carry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true |
--- |
| 3436 |
*/ |
--- |
3436 |
*/ |
--- |
| 3437 |
if (Carry0.getOpcode() == ISD::UADDO_CARRY && |
0 |
3437 |
if (Carry0.getOpcode() == ISD::UADDO_CARRY && |
0 |
| 3438 |
isNullConstant(Carry0.getOperand(1))) { |
0 |
3438 |
isNullConstant(Carry0.getOperand(1))) { |
0 |
| 3439 |
Z = Carry0.getOperand(2); |
0 |
3439 |
Z = Carry0.getOperand(2); |
0 |
| 3440 |
} else if (Carry0.getOpcode() == ISD::UADDO && |
0 |
3440 |
} else if (Carry0.getOpcode() == ISD::UADDO && |
0 |
| 3441 |
isOneConstant(Carry0.getOperand(1))) { |
0 |
3441 |
isOneConstant(Carry0.getOperand(1))) { |
0 |
| 3442 |
EVT VT = Combiner.getSetCCResultType(Carry0.getValueType()); |
0 |
3442 |
EVT VT = Combiner.getSetCCResultType(Carry0.getValueType()); |
0 |
| 3443 |
Z = DAG.getConstant(1, SDLoc(Carry0.getOperand(1)), VT); |
0 |
3443 |
Z = DAG.getConstant(1, SDLoc(Carry0.getOperand(1)), VT); |
0 |
| 3444 |
} else { |
--- |
3444 |
} else { |
--- |
| 3445 |
// We couldn't find a suitable Z. |
--- |
3445 |
// We couldn't find a suitable Z. |
--- |
| 3446 |
return SDValue(); |
0 |
3446 |
return SDValue(); |
0 |
| 3447 |
} |
--- |
3447 |
} |
--- |
| 3448 |
|
--- |
3448 |
|
--- |
| 3449 |
|
--- |
3449 |
|
--- |
| 3450 |
auto cancelDiamond = [&](SDValue A,SDValue B) { |
0 |
3450 |
auto cancelDiamond = [&](SDValue A,SDValue B) { |
0 |
| 3451 |
SDLoc DL(N); |
0 |
3451 |
SDLoc DL(N); |
0 |
| 3452 |
SDValue NewY = |
--- |
3452 |
SDValue NewY = |
--- |
| 3453 |
DAG.getNode(ISD::UADDO_CARRY, DL, Carry0->getVTList(), A, B, Z); |
0 |
3453 |
DAG.getNode(ISD::UADDO_CARRY, DL, Carry0->getVTList(), A, B, Z); |
0 |
| 3454 |
Combiner.AddToWorklist(NewY.getNode()); |
0 |
3454 |
Combiner.AddToWorklist(NewY.getNode()); |
0 |
| 3455 |
return DAG.getNode(ISD::UADDO_CARRY, DL, N->getVTList(), X, |
0 |
3455 |
return DAG.getNode(ISD::UADDO_CARRY, DL, N->getVTList(), X, |
0 |
| 3456 |
DAG.getConstant(0, DL, X.getValueType()), |
--- |
3456 |
DAG.getConstant(0, DL, X.getValueType()), |
--- |
| 3457 |
NewY.getValue(1)); |
0 |
3457 |
NewY.getValue(1)); |
0 |
| 3458 |
}; |
0 |
3458 |
}; |
0 |
| 3459 |
|
--- |
3459 |
|
--- |
| 3460 |
/** |
--- |
3460 |
/** |
--- |
| 3461 |
* (uaddo A, B) |
--- |
3461 |
* (uaddo A, B) |
--- |
| 3462 |
* | |
--- |
3462 |
* | |
--- |
| 3463 |
* Sum |
--- |
3463 |
* Sum |
--- |
| 3464 |
* | |
--- |
3464 |
* | |
--- |
| 3465 |
* (uaddo_carry *, 0, Z) |
--- |
3465 |
* (uaddo_carry *, 0, Z) |
--- |
| 3466 |
*/ |
--- |
3466 |
*/ |
--- |
| 3467 |
if (Carry0.getOperand(0) == Carry1.getValue(0)) { |
0 |
3467 |
if (Carry0.getOperand(0) == Carry1.getValue(0)) { |
0 |
| 3468 |
return cancelDiamond(Carry1.getOperand(0), Carry1.getOperand(1)); |
0 |
3468 |
return cancelDiamond(Carry1.getOperand(0), Carry1.getOperand(1)); |
0 |
| 3469 |
} |
--- |
3469 |
} |
--- |
| 3470 |
|
--- |
3470 |
|
--- |
| 3471 |
/** |
--- |
3471 |
/** |
--- |
| 3472 |
* (uaddo_carry A, 0, Z) |
--- |
3472 |
* (uaddo_carry A, 0, Z) |
--- |
| 3473 |
* | |
--- |
3473 |
* | |
--- |
| 3474 |
* Sum |
--- |
3474 |
* Sum |
--- |
| 3475 |
* | |
--- |
3475 |
* | |
--- |
| 3476 |
* (uaddo *, B) |
--- |
3476 |
* (uaddo *, B) |
--- |
| 3477 |
*/ |
--- |
3477 |
*/ |
--- |
| 3478 |
if (Carry1.getOperand(0) == Carry0.getValue(0)) { |
0 |
3478 |
if (Carry1.getOperand(0) == Carry0.getValue(0)) { |
0 |
| 3479 |
return cancelDiamond(Carry0.getOperand(0), Carry1.getOperand(1)); |
0 |
3479 |
return cancelDiamond(Carry0.getOperand(0), Carry1.getOperand(1)); |
0 |
| 3480 |
} |
--- |
3480 |
} |
--- |
| 3481 |
|
--- |
3481 |
|
--- |
| 3482 |
if (Carry1.getOperand(1) == Carry0.getValue(0)) { |
0 |
3482 |
if (Carry1.getOperand(1) == Carry0.getValue(0)) { |
0 |
| 3483 |
return cancelDiamond(Carry1.getOperand(0), Carry0.getOperand(0)); |
0 |
3483 |
return cancelDiamond(Carry1.getOperand(0), Carry0.getOperand(0)); |
0 |
| 3484 |
} |
--- |
3484 |
} |
--- |
| 3485 |
|
--- |
3485 |
|
--- |
| 3486 |
return SDValue(); |
0 |
3486 |
return SDValue(); |
0 |
| 3487 |
} |
--- |
3487 |
} |
--- |
| 3488 |
|
--- |
3488 |
|
--- |
| 3489 |
// If we are facing some sort of diamond carry/borrow in/out pattern try to |
--- |
3489 |
// If we are facing some sort of diamond carry/borrow in/out pattern try to |
--- |
| 3490 |
// match patterns like: |
--- |
3490 |
// match patterns like: |
--- |
| 3491 |
// |
--- |
3491 |
// |
--- |
| 3492 |
// (uaddo A, B) CarryIn |
--- |
3492 |
// (uaddo A, B) CarryIn |
--- |
| 3493 |
// | \ | |
--- |
3493 |
// | \ | |
--- |
| 3494 |
// | \ | |
--- |
3494 |
// | \ | |
--- |
| 3495 |
// PartialSum PartialCarryOutX / |
--- |
3495 |
// PartialSum PartialCarryOutX / |
--- |
| 3496 |
// | | / |
--- |
3496 |
// | | / |
--- |
| 3497 |
// | ____|____________/ |
--- |
3497 |
// | ____|____________/ |
--- |
| 3498 |
// | / | |
--- |
3498 |
// | / | |
--- |
| 3499 |
// (uaddo *, *) \________ |
--- |
3499 |
// (uaddo *, *) \________ |
--- |
| 3500 |
// | \ \ |
--- |
3500 |
// | \ \ |
--- |
| 3501 |
// | \ | |
--- |
3501 |
// | \ | |
--- |
| 3502 |
// | PartialCarryOutY | |
--- |
3502 |
// | PartialCarryOutY | |
--- |
| 3503 |
// | \ | |
--- |
3503 |
// | \ | |
--- |
| 3504 |
// | \ / |
--- |
3504 |
// | \ / |
--- |
| 3505 |
// AddCarrySum | ______/ |
--- |
3505 |
// AddCarrySum | ______/ |
--- |
| 3506 |
// | / |
--- |
3506 |
// | / |
--- |
| 3507 |
// CarryOut = (or *, *) |
--- |
3507 |
// CarryOut = (or *, *) |
--- |
| 3508 |
// |
--- |
3508 |
// |
--- |
| 3509 |
// And generate UADDO_CARRY (or USUBO_CARRY) with two result values: |
--- |
3509 |
// And generate UADDO_CARRY (or USUBO_CARRY) with two result values: |
--- |
| 3510 |
// |
--- |
3510 |
// |
--- |
| 3511 |
// {AddCarrySum, CarryOut} = (uaddo_carry A, B, CarryIn) |
--- |
3511 |
// {AddCarrySum, CarryOut} = (uaddo_carry A, B, CarryIn) |
--- |
| 3512 |
// |
--- |
3512 |
// |
--- |
| 3513 |
// Our goal is to identify A, B, and CarryIn and produce UADDO_CARRY/USUBO_CARRY |
--- |
3513 |
// Our goal is to identify A, B, and CarryIn and produce UADDO_CARRY/USUBO_CARRY |
--- |
| 3514 |
// with a single path for carry/borrow out propagation. |
--- |
3514 |
// with a single path for carry/borrow out propagation. |
--- |
| 3515 |
static SDValue combineCarryDiamond(SelectionDAG &DAG, const TargetLowering &TLI, |
1 |
3515 |
static SDValue combineCarryDiamond(SelectionDAG &DAG, const TargetLowering &TLI, |
1 |
| 3516 |
SDValue N0, SDValue N1, SDNode *N) { |
--- |
3516 |
SDValue N0, SDValue N1, SDNode *N) { |
--- |
| 3517 |
SDValue Carry0 = getAsCarry(TLI, N0); |
1 |
3517 |
SDValue Carry0 = getAsCarry(TLI, N0); |
1 |
| 3518 |
if (!Carry0) |
1 |
3518 |
if (!Carry0) |
1 |
| 3519 |
return SDValue(); |
1 |
3519 |
return SDValue(); |
1 |
| 3520 |
SDValue Carry1 = getAsCarry(TLI, N1); |
0 |
3520 |
SDValue Carry1 = getAsCarry(TLI, N1); |
0 |
| 3521 |
if (!Carry1) |
0 |
3521 |
if (!Carry1) |
0 |
| 3522 |
return SDValue(); |
0 |
3522 |
return SDValue(); |
0 |
| 3523 |
|
--- |
3523 |
|
--- |
| 3524 |
unsigned Opcode = Carry0.getOpcode(); |
0 |
3524 |
unsigned Opcode = Carry0.getOpcode(); |
0 |
| 3525 |
if (Opcode != Carry1.getOpcode()) |
0 |
3525 |
if (Opcode != Carry1.getOpcode()) |
0 |
| 3526 |
return SDValue(); |
0 |
3526 |
return SDValue(); |
0 |
| 3527 |
if (Opcode != ISD::UADDO && Opcode != ISD::USUBO) |
0 |
3527 |
if (Opcode != ISD::UADDO && Opcode != ISD::USUBO) |
0 |
| 3528 |
return SDValue(); |
0 |
3528 |
return SDValue(); |
0 |
| 3529 |
|
--- |
3529 |
|
--- |
| 3530 |
// Canonicalize the add/sub of A and B (the top node in the above ASCII art) |
--- |
3530 |
// Canonicalize the add/sub of A and B (the top node in the above ASCII art) |
--- |
| 3531 |
// as Carry0 and the add/sub of the carry in as Carry1 (the middle node). |
--- |
3531 |
// as Carry0 and the add/sub of the carry in as Carry1 (the middle node). |
--- |
| 3532 |
if (Carry1.getNode()->isOperandOf(Carry0.getNode())) |
0 |
3532 |
if (Carry1.getNode()->isOperandOf(Carry0.getNode())) |
0 |
| 3533 |
std::swap(Carry0, Carry1); |
0 |
3533 |
std::swap(Carry0, Carry1); |
0 |
| 3534 |
|
--- |
3534 |
|
--- |
| 3535 |
// Check if nodes are connected in expected way. |
--- |
3535 |
// Check if nodes are connected in expected way. |
--- |
| 3536 |
if (Carry1.getOperand(0) != Carry0.getValue(0) && |
0 |
3536 |
if (Carry1.getOperand(0) != Carry0.getValue(0) && |
0 |
| 3537 |
Carry1.getOperand(1) != Carry0.getValue(0)) |
0 |
3537 |
Carry1.getOperand(1) != Carry0.getValue(0)) |
0 |
| 3538 |
return SDValue(); |
0 |
3538 |
return SDValue(); |
0 |
| 3539 |
|
--- |
3539 |
|
--- |
| 3540 |
// The carry in value must be on the righthand side for subtraction. |
--- |
3540 |
// The carry in value must be on the righthand side for subtraction. |
--- |
| 3541 |
unsigned CarryInOperandNum = |
--- |
3541 |
unsigned CarryInOperandNum = |
--- |
| 3542 |
Carry1.getOperand(0) == Carry0.getValue(0) ? 1 : 0; |
0 |
3542 |
Carry1.getOperand(0) == Carry0.getValue(0) ? 1 : 0; |
0 |
| 3543 |
if (Opcode == ISD::USUBO && CarryInOperandNum != 1) |
0 |
3543 |
if (Opcode == ISD::USUBO && CarryInOperandNum != 1) |
0 |
| 3544 |
return SDValue(); |
0 |
3544 |
return SDValue(); |
0 |
| 3545 |
SDValue CarryIn = Carry1.getOperand(CarryInOperandNum); |
0 |
3545 |
SDValue CarryIn = Carry1.getOperand(CarryInOperandNum); |
0 |
| 3546 |
|
--- |
3546 |
|
--- |
| 3547 |
unsigned NewOp = Opcode == ISD::UADDO ? ISD::UADDO_CARRY : ISD::USUBO_CARRY; |
0 |
3547 |
unsigned NewOp = Opcode == ISD::UADDO ? ISD::UADDO_CARRY : ISD::USUBO_CARRY; |
0 |
| 3548 |
if (!TLI.isOperationLegalOrCustom(NewOp, Carry0.getValue(0).getValueType())) |
0 |
3548 |
if (!TLI.isOperationLegalOrCustom(NewOp, Carry0.getValue(0).getValueType())) |
0 |
| 3549 |
return SDValue(); |
0 |
3549 |
return SDValue(); |
0 |
| 3550 |
|
--- |
3550 |
|
--- |
| 3551 |
// Verify that the carry/borrow in is plausibly a carry/borrow bit. |
--- |
3551 |
// Verify that the carry/borrow in is plausibly a carry/borrow bit. |
--- |
| 3552 |
CarryIn = getAsCarry(TLI, CarryIn, true); |
0 |
3552 |
CarryIn = getAsCarry(TLI, CarryIn, true); |
0 |
| 3553 |
if (!CarryIn) |
0 |
3553 |
if (!CarryIn) |
0 |
| 3554 |
return SDValue(); |
0 |
3554 |
return SDValue(); |
0 |
| 3555 |
|
--- |
3555 |
|
--- |
| 3556 |
SDLoc DL(N); |
0 |
3556 |
SDLoc DL(N); |
0 |
| 3557 |
SDValue Merged = |
--- |
3557 |
SDValue Merged = |
--- |
| 3558 |
DAG.getNode(NewOp, DL, Carry1->getVTList(), Carry0.getOperand(0), |
0 |
3558 |
DAG.getNode(NewOp, DL, Carry1->getVTList(), Carry0.getOperand(0), |
0 |
| 3559 |
Carry0.getOperand(1), CarryIn); |
0 |
3559 |
Carry0.getOperand(1), CarryIn); |
0 |
| 3560 |
|
--- |
3560 |
|
--- |
| 3561 |
// Please note that because we have proven that the result of the UADDO/USUBO |
--- |
3561 |
// Please note that because we have proven that the result of the UADDO/USUBO |
--- |
| 3562 |
// of A and B feeds into the UADDO/USUBO that does the carry/borrow in, we can |
--- |
3562 |
// of A and B feeds into the UADDO/USUBO that does the carry/borrow in, we can |
--- |
| 3563 |
// therefore prove that if the first UADDO/USUBO overflows, the second |
--- |
3563 |
// therefore prove that if the first UADDO/USUBO overflows, the second |
--- |
| 3564 |
// UADDO/USUBO cannot. For example consider 8-bit numbers where 0xFF is the |
--- |
3564 |
// UADDO/USUBO cannot. For example consider 8-bit numbers where 0xFF is the |
--- |
| 3565 |
// maximum value. |
--- |
3565 |
// maximum value. |
--- |
| 3566 |
// |
--- |
3566 |
// |
--- |
| 3567 |
// 0xFF + 0xFF == 0xFE with carry but 0xFE + 1 does not carry |
--- |
3567 |
// 0xFF + 0xFF == 0xFE with carry but 0xFE + 1 does not carry |
--- |
| 3568 |
// 0x00 - 0xFF == 1 with a carry/borrow but 1 - 1 == 0 (no carry/borrow) |
--- |
3568 |
// 0x00 - 0xFF == 1 with a carry/borrow but 1 - 1 == 0 (no carry/borrow) |
--- |
| 3569 |
// |
--- |
3569 |
// |
--- |
| 3570 |
// This is important because it means that OR and XOR can be used to merge |
--- |
3570 |
// This is important because it means that OR and XOR can be used to merge |
--- |
| 3571 |
// carry flags; and that AND can return a constant zero. |
--- |
3571 |
// carry flags; and that AND can return a constant zero. |
--- |
| 3572 |
// |
--- |
3572 |
// |
--- |
| 3573 |
// TODO: match other operations that can merge flags (ADD, etc) |
--- |
3573 |
// TODO: match other operations that can merge flags (ADD, etc) |
--- |
| 3574 |
DAG.ReplaceAllUsesOfValueWith(Carry1.getValue(0), Merged.getValue(0)); |
0 |
3574 |
DAG.ReplaceAllUsesOfValueWith(Carry1.getValue(0), Merged.getValue(0)); |
0 |
| 3575 |
if (N->getOpcode() == ISD::AND) |
0 |
3575 |
if (N->getOpcode() == ISD::AND) |
0 |
| 3576 |
return DAG.getConstant(0, DL, MVT::i1); |
0 |
3576 |
return DAG.getConstant(0, DL, MVT::i1); |
0 |
| 3577 |
return Merged.getValue(1); |
0 |
3577 |
return Merged.getValue(1); |
0 |
| 3578 |
} |
0 |
3578 |
} |
0 |
| 3579 |
|
--- |
3579 |
|
--- |
| 3580 |
SDValue DAGCombiner::visitUADDO_CARRYLike(SDValue N0, SDValue N1, |
0 |
3580 |
SDValue DAGCombiner::visitUADDO_CARRYLike(SDValue N0, SDValue N1, |
0 |
| 3581 |
SDValue CarryIn, SDNode *N) { |
--- |
3581 |
SDValue CarryIn, SDNode *N) { |
--- |
| 3582 |
// fold (uaddo_carry (xor a, -1), b, c) -> (usubo_carry b, a, !c) and flip |
--- |
3582 |
// fold (uaddo_carry (xor a, -1), b, c) -> (usubo_carry b, a, !c) and flip |
--- |
| 3583 |
// carry. |
--- |
3583 |
// carry. |
--- |
| 3584 |
if (isBitwiseNot(N0)) |
0 |
3584 |
if (isBitwiseNot(N0)) |
0 |
| 3585 |
if (SDValue NotC = extractBooleanFlip(CarryIn, DAG, TLI, true)) { |
0 |
3585 |
if (SDValue NotC = extractBooleanFlip(CarryIn, DAG, TLI, true)) { |
0 |
| 3586 |
SDLoc DL(N); |
0 |
3586 |
SDLoc DL(N); |
0 |
| 3587 |
SDValue Sub = DAG.getNode(ISD::USUBO_CARRY, DL, N->getVTList(), N1, |
0 |
3587 |
SDValue Sub = DAG.getNode(ISD::USUBO_CARRY, DL, N->getVTList(), N1, |
0 |
| 3588 |
N0.getOperand(0), NotC); |
0 |
3588 |
N0.getOperand(0), NotC); |
0 |
| 3589 |
return CombineTo( |
0 |
3589 |
return CombineTo( |
0 |
| 3590 |
N, Sub, DAG.getLogicalNOT(DL, Sub.getValue(1), Sub->getValueType(1))); |
0 |
3590 |
N, Sub, DAG.getLogicalNOT(DL, Sub.getValue(1), Sub->getValueType(1))); |
0 |
| 3591 |
} |
0 |
3591 |
} |
0 |
| 3592 |
|
--- |
3592 |
|
--- |
| 3593 |
// Iff the flag result is dead: |
--- |
3593 |
// Iff the flag result is dead: |
--- |
| 3594 |
// (uaddo_carry (add|uaddo X, Y), 0, Carry) -> (uaddo_carry X, Y, Carry) |
--- |
3594 |
// (uaddo_carry (add|uaddo X, Y), 0, Carry) -> (uaddo_carry X, Y, Carry) |
--- |
| 3595 |
// Don't do this if the Carry comes from the uaddo. It won't remove the uaddo |
--- |
3595 |
// Don't do this if the Carry comes from the uaddo. It won't remove the uaddo |
--- |
| 3596 |
// or the dependency between the instructions. |
--- |
3596 |
// or the dependency between the instructions. |
--- |
| 3597 |
if ((N0.getOpcode() == ISD::ADD || |
0 |
3597 |
if ((N0.getOpcode() == ISD::ADD || |
0 |
| 3598 |
(N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 && |
0 |
3598 |
(N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 && |
0 |
| 3599 |
N0.getValue(1) != CarryIn)) && |
0 |
3599 |
N0.getValue(1) != CarryIn)) && |
0 |
| 3600 |
isNullConstant(N1) && !N->hasAnyUseOfValue(1)) |
0 |
3600 |
isNullConstant(N1) && !N->hasAnyUseOfValue(1)) |
0 |
| 3601 |
return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(), |
0 |
3601 |
return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(), |
0 |
| 3602 |
N0.getOperand(0), N0.getOperand(1), CarryIn); |
0 |
3602 |
N0.getOperand(0), N0.getOperand(1), CarryIn); |
0 |
| 3603 |
|
--- |
3603 |
|
--- |
| 3604 |
/** |
--- |
3604 |
/** |
--- |
| 3605 |
* When one of the uaddo_carry argument is itself a carry, we may be facing |
--- |
3605 |
* When one of the uaddo_carry argument is itself a carry, we may be facing |
--- |
| 3606 |
* a diamond carry propagation. In which case we try to transform the DAG |
--- |
3606 |
* a diamond carry propagation. In which case we try to transform the DAG |
--- |
| 3607 |
* to ensure linear carry propagation if that is possible. |
--- |
3607 |
* to ensure linear carry propagation if that is possible. |
--- |
| 3608 |
*/ |
--- |
3608 |
*/ |
--- |
| 3609 |
if (auto Y = getAsCarry(TLI, N1)) { |
0 |
3609 |
if (auto Y = getAsCarry(TLI, N1)) { |
0 |
| 3610 |
// Because both are carries, Y and Z can be swapped. |
--- |
3610 |
// Because both are carries, Y and Z can be swapped. |
--- |
| 3611 |
if (auto R = combineUADDO_CARRYDiamond(*this, DAG, N0, Y, CarryIn, N)) |
0 |
3611 |
if (auto R = combineUADDO_CARRYDiamond(*this, DAG, N0, Y, CarryIn, N)) |
0 |
| 3612 |
return R; |
0 |
3612 |
return R; |
0 |
| 3613 |
if (auto R = combineUADDO_CARRYDiamond(*this, DAG, N0, CarryIn, Y, N)) |
0 |
3613 |
if (auto R = combineUADDO_CARRYDiamond(*this, DAG, N0, CarryIn, Y, N)) |
0 |
| 3614 |
return R; |
0 |
3614 |
return R; |
0 |
| 3615 |
} |
--- |
3615 |
} |
--- |
| 3616 |
|
--- |
3616 |
|
--- |
| 3617 |
return SDValue(); |
0 |
3617 |
return SDValue(); |
0 |
| 3618 |
} |
--- |
3618 |
} |
--- |
| 3619 |
|
--- |
3619 |
|
--- |
| 3620 |
SDValue DAGCombiner::visitSADDO_CARRY(SDNode *N) { |
0 |
3620 |
SDValue DAGCombiner::visitSADDO_CARRY(SDNode *N) { |
0 |
| 3621 |
SDValue N0 = N->getOperand(0); |
0 |
3621 |
SDValue N0 = N->getOperand(0); |
0 |
| 3622 |
SDValue N1 = N->getOperand(1); |
0 |
3622 |
SDValue N1 = N->getOperand(1); |
0 |
| 3623 |
SDValue CarryIn = N->getOperand(2); |
0 |
3623 |
SDValue CarryIn = N->getOperand(2); |
0 |
| 3624 |
SDLoc DL(N); |
0 |
3624 |
SDLoc DL(N); |
0 |
| 3625 |
|
--- |
3625 |
|
--- |
| 3626 |
// canonicalize constant to RHS |
--- |
3626 |
// canonicalize constant to RHS |
--- |
| 3627 |
ConstantSDNode *N0C = dyn_cast(N0); |
0 |
3627 |
ConstantSDNode *N0C = dyn_cast(N0); |
0 |
| 3628 |
ConstantSDNode *N1C = dyn_cast(N1); |
0 |
3628 |
ConstantSDNode *N1C = dyn_cast(N1); |
0 |
| 3629 |
if (N0C && !N1C) |
0 |
3629 |
if (N0C && !N1C) |
0 |
| 3630 |
return DAG.getNode(ISD::SADDO_CARRY, DL, N->getVTList(), N1, N0, CarryIn); |
0 |
3630 |
return DAG.getNode(ISD::SADDO_CARRY, DL, N->getVTList(), N1, N0, CarryIn); |
0 |
| 3631 |
|
--- |
3631 |
|
--- |
| 3632 |
// fold (saddo_carry x, y, false) -> (saddo x, y) |
--- |
3632 |
// fold (saddo_carry x, y, false) -> (saddo x, y) |
--- |
| 3633 |
if (isNullConstant(CarryIn)) { |
0 |
3633 |
if (isNullConstant(CarryIn)) { |
0 |
| 3634 |
if (!LegalOperations || |
0 |
3634 |
if (!LegalOperations || |
0 |
| 3635 |
TLI.isOperationLegalOrCustom(ISD::SADDO, N->getValueType(0))) |
0 |
3635 |
TLI.isOperationLegalOrCustom(ISD::SADDO, N->getValueType(0))) |
0 |
| 3636 |
return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0, N1); |
0 |
3636 |
return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0, N1); |
0 |
| 3637 |
} |
--- |
3637 |
} |
--- |
| 3638 |
|
--- |
3638 |
|
--- |
| 3639 |
return SDValue(); |
0 |
3639 |
return SDValue(); |
0 |
| 3640 |
} |
0 |
3640 |
} |
0 |
| 3641 |
|
--- |
3641 |
|
--- |
| 3642 |
// Attempt to create a USUBSAT(LHS, RHS) node with DstVT, performing a |
--- |
3642 |
// Attempt to create a USUBSAT(LHS, RHS) node with DstVT, performing a |
--- |
| 3643 |
// clamp/truncation if necessary. |
--- |
3643 |
// clamp/truncation if necessary. |
--- |
| 3644 |
static SDValue getTruncatedUSUBSAT(EVT DstVT, EVT SrcVT, SDValue LHS, |
0 |
3644 |
static SDValue getTruncatedUSUBSAT(EVT DstVT, EVT SrcVT, SDValue LHS, |
0 |
| 3645 |
SDValue RHS, SelectionDAG &DAG, |
--- |
3645 |
SDValue RHS, SelectionDAG &DAG, |
--- |
| 3646 |
const SDLoc &DL) { |
--- |
3646 |
const SDLoc &DL) { |
--- |
| 3647 |
assert(DstVT.getScalarSizeInBits() <= SrcVT.getScalarSizeInBits() && |
0 |
3647 |
assert(DstVT.getScalarSizeInBits() <= SrcVT.getScalarSizeInBits() && |
0 |
| 3648 |
"Illegal truncation"); |
--- |
3648 |
"Illegal truncation"); |
--- |
| 3649 |
|
--- |
3649 |
|
--- |
| 3650 |
if (DstVT == SrcVT) |
0 |
3650 |
if (DstVT == SrcVT) |
0 |
| 3651 |
return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS); |
0 |
3651 |
return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS); |
0 |
| 3652 |
|
--- |
3652 |
|
--- |
| 3653 |
// If the LHS is zero-extended then we can perform the USUBSAT as DstVT by |
--- |
3653 |
// If the LHS is zero-extended then we can perform the USUBSAT as DstVT by |
--- |
| 3654 |
// clamping RHS. |
--- |
3654 |
// clamping RHS. |
--- |
| 3655 |
APInt UpperBits = APInt::getBitsSetFrom(SrcVT.getScalarSizeInBits(), |
0 |
3655 |
APInt UpperBits = APInt::getBitsSetFrom(SrcVT.getScalarSizeInBits(), |
0 |
| 3656 |
DstVT.getScalarSizeInBits()); |
0 |
3656 |
DstVT.getScalarSizeInBits()); |
0 |
| 3657 |
if (!DAG.MaskedValueIsZero(LHS, UpperBits)) |
0 |
3657 |
if (!DAG.MaskedValueIsZero(LHS, UpperBits)) |
0 |
| 3658 |
return SDValue(); |
0 |
3658 |
return SDValue(); |
0 |
| 3659 |
|
--- |
3659 |
|
--- |
| 3660 |
SDValue SatLimit = |
--- |
3660 |
SDValue SatLimit = |
--- |
| 3661 |
DAG.getConstant(APInt::getLowBitsSet(SrcVT.getScalarSizeInBits(), |
0 |
3661 |
DAG.getConstant(APInt::getLowBitsSet(SrcVT.getScalarSizeInBits(), |
0 |
| 3662 |
DstVT.getScalarSizeInBits()), |
0 |
3662 |
DstVT.getScalarSizeInBits()), |
0 |
| 3663 |
DL, SrcVT); |
--- |
3663 |
DL, SrcVT); |
--- |
| 3664 |
RHS = DAG.getNode(ISD::UMIN, DL, SrcVT, RHS, SatLimit); |
0 |
3664 |
RHS = DAG.getNode(ISD::UMIN, DL, SrcVT, RHS, SatLimit); |
0 |
| 3665 |
RHS = DAG.getNode(ISD::TRUNCATE, DL, DstVT, RHS); |
0 |
3665 |
RHS = DAG.getNode(ISD::TRUNCATE, DL, DstVT, RHS); |
0 |
| 3666 |
LHS = DAG.getNode(ISD::TRUNCATE, DL, DstVT, LHS); |
0 |
3666 |
LHS = DAG.getNode(ISD::TRUNCATE, DL, DstVT, LHS); |
0 |
| 3667 |
return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS); |
0 |
3667 |
return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS); |
0 |
| 3668 |
} |
0 |
3668 |
} |
0 |
| 3669 |
|
--- |
3669 |
|
--- |
| 3670 |
// Try to find umax(a,b) - b or a - umin(a,b) patterns that may be converted to |
--- |
3670 |
// Try to find umax(a,b) - b or a - umin(a,b) patterns that may be converted to |
--- |
| 3671 |
// usubsat(a,b), optionally as a truncated type. |
--- |
3671 |
// usubsat(a,b), optionally as a truncated type. |
--- |
| 3672 |
SDValue DAGCombiner::foldSubToUSubSat(EVT DstVT, SDNode *N) { |
0 |
3672 |
SDValue DAGCombiner::foldSubToUSubSat(EVT DstVT, SDNode *N) { |
0 |
| 3673 |
if (N->getOpcode() != ISD::SUB || |
0 |
3673 |
if (N->getOpcode() != ISD::SUB || |
0 |
| 3674 |
!(!LegalOperations || hasOperation(ISD::USUBSAT, DstVT))) |
0 |
3674 |
!(!LegalOperations || hasOperation(ISD::USUBSAT, DstVT))) |
0 |
| 3675 |
return SDValue(); |
0 |
3675 |
return SDValue(); |
0 |
| 3676 |
|
--- |
3676 |
|
--- |
| 3677 |
EVT SubVT = N->getValueType(0); |
0 |
3677 |
EVT SubVT = N->getValueType(0); |
0 |
| 3678 |
SDValue Op0 = N->getOperand(0); |
0 |
3678 |
SDValue Op0 = N->getOperand(0); |
0 |
| 3679 |
SDValue Op1 = N->getOperand(1); |
0 |
3679 |
SDValue Op1 = N->getOperand(1); |
0 |
| 3680 |
|
--- |
3680 |
|
--- |
| 3681 |
// Try to find umax(a,b) - b or a - umin(a,b) patterns |
--- |
3681 |
// Try to find umax(a,b) - b or a - umin(a,b) patterns |
--- |
| 3682 |
// they may be converted to usubsat(a,b). |
--- |
3682 |
// they may be converted to usubsat(a,b). |
--- |
| 3683 |
if (Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { |
0 |
3683 |
if (Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { |
0 |
| 3684 |
SDValue MaxLHS = Op0.getOperand(0); |
0 |
3684 |
SDValue MaxLHS = Op0.getOperand(0); |
0 |
| 3685 |
SDValue MaxRHS = Op0.getOperand(1); |
0 |
3685 |
SDValue MaxRHS = Op0.getOperand(1); |
0 |
| 3686 |
if (MaxLHS == Op1) |
0 |
3686 |
if (MaxLHS == Op1) |
0 |
| 3687 |
return getTruncatedUSUBSAT(DstVT, SubVT, MaxRHS, Op1, DAG, SDLoc(N)); |
0 |
3687 |
return getTruncatedUSUBSAT(DstVT, SubVT, MaxRHS, Op1, DAG, SDLoc(N)); |
0 |
| 3688 |
if (MaxRHS == Op1) |
0 |
3688 |
if (MaxRHS == Op1) |
0 |
| 3689 |
return getTruncatedUSUBSAT(DstVT, SubVT, MaxLHS, Op1, DAG, SDLoc(N)); |
0 |
3689 |
return getTruncatedUSUBSAT(DstVT, SubVT, MaxLHS, Op1, DAG, SDLoc(N)); |
0 |
| 3690 |
} |
--- |
3690 |
} |
--- |
| 3691 |
|
--- |
3691 |
|
--- |
| 3692 |
if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) { |
0 |
3692 |
if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) { |
0 |
| 3693 |
SDValue MinLHS = Op1.getOperand(0); |
0 |
3693 |
SDValue MinLHS = Op1.getOperand(0); |
0 |
| 3694 |
SDValue MinRHS = Op1.getOperand(1); |
0 |
3694 |
SDValue MinRHS = Op1.getOperand(1); |
0 |
| 3695 |
if (MinLHS == Op0) |
0 |
3695 |
if (MinLHS == Op0) |
0 |
| 3696 |
return getTruncatedUSUBSAT(DstVT, SubVT, Op0, MinRHS, DAG, SDLoc(N)); |
0 |
3696 |
return getTruncatedUSUBSAT(DstVT, SubVT, Op0, MinRHS, DAG, SDLoc(N)); |
0 |
| 3697 |
if (MinRHS == Op0) |
0 |
3697 |
if (MinRHS == Op0) |
0 |
| 3698 |
return getTruncatedUSUBSAT(DstVT, SubVT, Op0, MinLHS, DAG, SDLoc(N)); |
0 |
3698 |
return getTruncatedUSUBSAT(DstVT, SubVT, Op0, MinLHS, DAG, SDLoc(N)); |
0 |
| 3699 |
} |
--- |
3699 |
} |
--- |
| 3700 |
|
--- |
3700 |
|
--- |
| 3701 |
// sub(a,trunc(umin(zext(a),b))) -> usubsat(a,trunc(umin(b,SatLimit))) |
--- |
3701 |
// sub(a,trunc(umin(zext(a),b))) -> usubsat(a,trunc(umin(b,SatLimit))) |
--- |
| 3702 |
if (Op1.getOpcode() == ISD::TRUNCATE && |
0 |
3702 |
if (Op1.getOpcode() == ISD::TRUNCATE && |
0 |
| 3703 |
Op1.getOperand(0).getOpcode() == ISD::UMIN && |
0 |
3703 |
Op1.getOperand(0).getOpcode() == ISD::UMIN && |
0 |
| 3704 |
Op1.getOperand(0).hasOneUse()) { |
0 |
3704 |
Op1.getOperand(0).hasOneUse()) { |
0 |
| 3705 |
SDValue MinLHS = Op1.getOperand(0).getOperand(0); |
0 |
3705 |
SDValue MinLHS = Op1.getOperand(0).getOperand(0); |
0 |
| 3706 |
SDValue MinRHS = Op1.getOperand(0).getOperand(1); |
0 |
3706 |
SDValue MinRHS = Op1.getOperand(0).getOperand(1); |
0 |
| 3707 |
if (MinLHS.getOpcode() == ISD::ZERO_EXTEND && MinLHS.getOperand(0) == Op0) |
0 |
3707 |
if (MinLHS.getOpcode() == ISD::ZERO_EXTEND && MinLHS.getOperand(0) == Op0) |
0 |
| 3708 |
return getTruncatedUSUBSAT(DstVT, MinLHS.getValueType(), MinLHS, MinRHS, |
0 |
3708 |
return getTruncatedUSUBSAT(DstVT, MinLHS.getValueType(), MinLHS, MinRHS, |
0 |
| 3709 |
DAG, SDLoc(N)); |
0 |
3709 |
DAG, SDLoc(N)); |
0 |
| 3710 |
if (MinRHS.getOpcode() == ISD::ZERO_EXTEND && MinRHS.getOperand(0) == Op0) |
0 |
3710 |
if (MinRHS.getOpcode() == ISD::ZERO_EXTEND && MinRHS.getOperand(0) == Op0) |
0 |
| 3711 |
return getTruncatedUSUBSAT(DstVT, MinLHS.getValueType(), MinRHS, MinLHS, |
0 |
3711 |
return getTruncatedUSUBSAT(DstVT, MinLHS.getValueType(), MinRHS, MinLHS, |
0 |
| 3712 |
DAG, SDLoc(N)); |
0 |
3712 |
DAG, SDLoc(N)); |
0 |
| 3713 |
} |
--- |
3713 |
} |
--- |
| 3714 |
|
--- |
3714 |
|
--- |
| 3715 |
return SDValue(); |
0 |
3715 |
return SDValue(); |
0 |
| 3716 |
} |
--- |
3716 |
} |
--- |
| 3717 |
|
--- |
3717 |
|
--- |
| 3718 |
// Since it may not be valid to emit a fold to zero for vector initializers |
--- |
3718 |
// Since it may not be valid to emit a fold to zero for vector initializers |
--- |
| 3719 |
// check if we can before folding. |
--- |
3719 |
// check if we can before folding. |
--- |
| 3720 |
static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT, |
0 |
3720 |
static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT, |
0 |
| 3721 |
SelectionDAG &DAG, bool LegalOperations) { |
--- |
3721 |
SelectionDAG &DAG, bool LegalOperations) { |
--- |
| 3722 |
if (!VT.isVector()) |
0 |
3722 |
if (!VT.isVector()) |
0 |
| 3723 |
return DAG.getConstant(0, DL, VT); |
0 |
3723 |
return DAG.getConstant(0, DL, VT); |
0 |
| 3724 |
if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) |
0 |
3724 |
if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) |
0 |
| 3725 |
return DAG.getConstant(0, DL, VT); |
0 |
3725 |
return DAG.getConstant(0, DL, VT); |
0 |
| 3726 |
return SDValue(); |
0 |
3726 |
return SDValue(); |
0 |
| 3727 |
} |
--- |
3727 |
} |
--- |
| 3728 |
|
--- |
3728 |
|
--- |
| 3729 |
SDValue DAGCombiner::visitSUB(SDNode *N) { |
0 |
3729 |
SDValue DAGCombiner::visitSUB(SDNode *N) { |
0 |
| 3730 |
SDValue N0 = N->getOperand(0); |
0 |
3730 |
SDValue N0 = N->getOperand(0); |
0 |
| 3731 |
SDValue N1 = N->getOperand(1); |
0 |
3731 |
SDValue N1 = N->getOperand(1); |
0 |
| 3732 |
EVT VT = N0.getValueType(); |
0 |
3732 |
EVT VT = N0.getValueType(); |
0 |
| 3733 |
SDLoc DL(N); |
0 |
3733 |
SDLoc DL(N); |
0 |
| 3734 |
|
--- |
3734 |
|
--- |
| 3735 |
auto PeekThroughFreeze = [](SDValue N) { |
0 |
3735 |
auto PeekThroughFreeze = [](SDValue N) { |
0 |
| 3736 |
if (N->getOpcode() == ISD::FREEZE && N.hasOneUse()) |
0 |
3736 |
if (N->getOpcode() == ISD::FREEZE && N.hasOneUse()) |
0 |
| 3737 |
return N->getOperand(0); |
0 |
3737 |
return N->getOperand(0); |
0 |
| 3738 |
return N; |
0 |
3738 |
return N; |
0 |
| 3739 |
}; |
--- |
3739 |
}; |
--- |
| 3740 |
|
--- |
3740 |
|
--- |
| 3741 |
// fold (sub x, x) -> 0 |
--- |
3741 |
// fold (sub x, x) -> 0 |
--- |
| 3742 |
// FIXME: Refactor this and xor and other similar operations together. |
--- |
3742 |
// FIXME: Refactor this and xor and other similar operations together. |
--- |
| 3743 |
if (PeekThroughFreeze(N0) == PeekThroughFreeze(N1)) |
0 |
3743 |
if (PeekThroughFreeze(N0) == PeekThroughFreeze(N1)) |
0 |
| 3744 |
return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); |
0 |
3744 |
return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); |
0 |
| 3745 |
|
--- |
3745 |
|
--- |
| 3746 |
// fold (sub c1, c2) -> c3 |
--- |
3746 |
// fold (sub c1, c2) -> c3 |
--- |
| 3747 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N1})) |
0 |
3747 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N1})) |
0 |
| 3748 |
return C; |
0 |
3748 |
return C; |
0 |
| 3749 |
|
--- |
3749 |
|
--- |
| 3750 |
// fold vector ops |
--- |
3750 |
// fold vector ops |
--- |
| 3751 |
if (VT.isVector()) { |
0 |
3751 |
if (VT.isVector()) { |
0 |
| 3752 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
3752 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 3753 |
return FoldedVOp; |
0 |
3753 |
return FoldedVOp; |
0 |
| 3754 |
|
--- |
3754 |
|
--- |
| 3755 |
// fold (sub x, 0) -> x, vector edition |
--- |
3755 |
// fold (sub x, 0) -> x, vector edition |
--- |
| 3756 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
3756 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
| 3757 |
return N0; |
0 |
3757 |
return N0; |
0 |
| 3758 |
} |
--- |
3758 |
} |
--- |
| 3759 |
|
--- |
3759 |
|
--- |
| 3760 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
3760 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 3761 |
return NewSel; |
0 |
3761 |
return NewSel; |
0 |
| 3762 |
|
--- |
3762 |
|
--- |
| 3763 |
ConstantSDNode *N1C = getAsNonOpaqueConstant(N1); |
0 |
3763 |
ConstantSDNode *N1C = getAsNonOpaqueConstant(N1); |
0 |
| 3764 |
|
--- |
3764 |
|
--- |
| 3765 |
// fold (sub x, c) -> (add x, -c) |
--- |
3765 |
// fold (sub x, c) -> (add x, -c) |
--- |
| 3766 |
if (N1C) { |
0 |
3766 |
if (N1C) { |
0 |
| 3767 |
return DAG.getNode(ISD::ADD, DL, VT, N0, |
0 |
3767 |
return DAG.getNode(ISD::ADD, DL, VT, N0, |
0 |
| 3768 |
DAG.getConstant(-N1C->getAPIntValue(), DL, VT)); |
0 |
3768 |
DAG.getConstant(-N1C->getAPIntValue(), DL, VT)); |
0 |
| 3769 |
} |
--- |
3769 |
} |
--- |
| 3770 |
|
--- |
3770 |
|
--- |
| 3771 |
if (isNullOrNullSplat(N0)) { |
0 |
3771 |
if (isNullOrNullSplat(N0)) { |
0 |
| 3772 |
unsigned BitWidth = VT.getScalarSizeInBits(); |
0 |
3772 |
unsigned BitWidth = VT.getScalarSizeInBits(); |
0 |
| 3773 |
// Right-shifting everything out but the sign bit followed by negation is |
--- |
3773 |
// Right-shifting everything out but the sign bit followed by negation is |
--- |
| 3774 |
// the same as flipping arithmetic/logical shift type without the negation: |
--- |
3774 |
// the same as flipping arithmetic/logical shift type without the negation: |
--- |
| 3775 |
// -(X >>u 31) -> (X >>s 31) |
--- |
3775 |
// -(X >>u 31) -> (X >>s 31) |
--- |
| 3776 |
// -(X >>s 31) -> (X >>u 31) |
--- |
3776 |
// -(X >>s 31) -> (X >>u 31) |
--- |
| 3777 |
if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { |
0 |
3777 |
if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { |
0 |
| 3778 |
ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1)); |
0 |
3778 |
ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1)); |
0 |
| 3779 |
if (ShiftAmt && ShiftAmt->getAPIntValue() == (BitWidth - 1)) { |
0 |
3779 |
if (ShiftAmt && ShiftAmt->getAPIntValue() == (BitWidth - 1)) { |
0 |
| 3780 |
auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; |
0 |
3780 |
auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; |
0 |
| 3781 |
if (!LegalOperations || TLI.isOperationLegal(NewSh, VT)) |
0 |
3781 |
if (!LegalOperations || TLI.isOperationLegal(NewSh, VT)) |
0 |
| 3782 |
return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1)); |
0 |
3782 |
return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1)); |
0 |
| 3783 |
} |
--- |
3783 |
} |
--- |
| 3784 |
} |
--- |
3784 |
} |
--- |
| 3785 |
|
--- |
3785 |
|
--- |
| 3786 |
// 0 - X --> 0 if the sub is NUW. |
--- |
3786 |
// 0 - X --> 0 if the sub is NUW. |
--- |
| 3787 |
if (N->getFlags().hasNoUnsignedWrap()) |
0 |
3787 |
if (N->getFlags().hasNoUnsignedWrap()) |
0 |
| 3788 |
return N0; |
0 |
3788 |
return N0; |
0 |
| 3789 |
|
--- |
3789 |
|
--- |
| 3790 |
if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) { |
0 |
3790 |
if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) { |
0 |
| 3791 |
// N1 is either 0 or the minimum signed value. If the sub is NSW, then |
--- |
3791 |
// N1 is either 0 or the minimum signed value. If the sub is NSW, then |
--- |
| 3792 |
// N1 must be 0 because negating the minimum signed value is undefined. |
--- |
3792 |
// N1 must be 0 because negating the minimum signed value is undefined. |
--- |
| 3793 |
if (N->getFlags().hasNoSignedWrap()) |
0 |
3793 |
if (N->getFlags().hasNoSignedWrap()) |
0 |
| 3794 |
return N0; |
0 |
3794 |
return N0; |
0 |
| 3795 |
|
--- |
3795 |
|
--- |
| 3796 |
// 0 - X --> X if X is 0 or the minimum signed value. |
--- |
3796 |
// 0 - X --> X if X is 0 or the minimum signed value. |
--- |
| 3797 |
return N1; |
0 |
3797 |
return N1; |
0 |
| 3798 |
} |
--- |
3798 |
} |
--- |
| 3799 |
|
--- |
3799 |
|
--- |
| 3800 |
// Convert 0 - abs(x). |
--- |
3800 |
// Convert 0 - abs(x). |
--- |
| 3801 |
if (N1.getOpcode() == ISD::ABS && N1.hasOneUse() && |
0 |
3801 |
if (N1.getOpcode() == ISD::ABS && N1.hasOneUse() && |
0 |
| 3802 |
!TLI.isOperationLegalOrCustom(ISD::ABS, VT)) |
0 |
3802 |
!TLI.isOperationLegalOrCustom(ISD::ABS, VT)) |
0 |
| 3803 |
if (SDValue Result = TLI.expandABS(N1.getNode(), DAG, true)) |
0 |
3803 |
if (SDValue Result = TLI.expandABS(N1.getNode(), DAG, true)) |
0 |
| 3804 |
return Result; |
0 |
3804 |
return Result; |
0 |
| 3805 |
|
--- |
3805 |
|
--- |
| 3806 |
// Fold neg(splat(neg(x)) -> splat(x) |
--- |
3806 |
// Fold neg(splat(neg(x)) -> splat(x) |
--- |
| 3807 |
if (VT.isVector()) { |
0 |
3807 |
if (VT.isVector()) { |
0 |
| 3808 |
SDValue N1S = DAG.getSplatValue(N1, true); |
0 |
3808 |
SDValue N1S = DAG.getSplatValue(N1, true); |
0 |
| 3809 |
if (N1S && N1S.getOpcode() == ISD::SUB && |
0 |
3809 |
if (N1S && N1S.getOpcode() == ISD::SUB && |
0 |
| 3810 |
isNullConstant(N1S.getOperand(0))) |
0 |
3810 |
isNullConstant(N1S.getOperand(0))) |
0 |
| 3811 |
return DAG.getSplat(VT, DL, N1S.getOperand(1)); |
0 |
3811 |
return DAG.getSplat(VT, DL, N1S.getOperand(1)); |
0 |
| 3812 |
} |
--- |
3812 |
} |
--- |
| 3813 |
} |
--- |
3813 |
} |
--- |
| 3814 |
|
--- |
3814 |
|
--- |
| 3815 |
// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) |
--- |
3815 |
// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) |
--- |
| 3816 |
if (isAllOnesOrAllOnesSplat(N0)) |
0 |
3816 |
if (isAllOnesOrAllOnesSplat(N0)) |
0 |
| 3817 |
return DAG.getNode(ISD::XOR, DL, VT, N1, N0); |
0 |
3817 |
return DAG.getNode(ISD::XOR, DL, VT, N1, N0); |
0 |
| 3818 |
|
--- |
3818 |
|
--- |
| 3819 |
// fold (A - (0-B)) -> A+B |
--- |
3819 |
// fold (A - (0-B)) -> A+B |
--- |
| 3820 |
if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) |
0 |
3820 |
if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0))) |
0 |
| 3821 |
return DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(1)); |
0 |
3821 |
return DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(1)); |
0 |
| 3822 |
|
--- |
3822 |
|
--- |
| 3823 |
// fold A-(A-B) -> B |
--- |
3823 |
// fold A-(A-B) -> B |
--- |
| 3824 |
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) |
0 |
3824 |
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) |
0 |
| 3825 |
return N1.getOperand(1); |
0 |
3825 |
return N1.getOperand(1); |
0 |
| 3826 |
|
--- |
3826 |
|
--- |
| 3827 |
// fold (A+B)-A -> B |
--- |
3827 |
// fold (A+B)-A -> B |
--- |
| 3828 |
if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) |
0 |
3828 |
if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) |
0 |
| 3829 |
return N0.getOperand(1); |
0 |
3829 |
return N0.getOperand(1); |
0 |
| 3830 |
|
--- |
3830 |
|
--- |
| 3831 |
// fold (A+B)-B -> A |
--- |
3831 |
// fold (A+B)-B -> A |
--- |
| 3832 |
if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) |
0 |
3832 |
if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) |
0 |
| 3833 |
return N0.getOperand(0); |
0 |
3833 |
return N0.getOperand(0); |
0 |
| 3834 |
|
--- |
3834 |
|
--- |
| 3835 |
// fold (A+C1)-C2 -> A+(C1-C2) |
--- |
3835 |
// fold (A+C1)-C2 -> A+(C1-C2) |
--- |
| 3836 |
if (N0.getOpcode() == ISD::ADD) { |
0 |
3836 |
if (N0.getOpcode() == ISD::ADD) { |
0 |
| 3837 |
SDValue N01 = N0.getOperand(1); |
0 |
3837 |
SDValue N01 = N0.getOperand(1); |
0 |
| 3838 |
if (SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N01, N1})) |
0 |
3838 |
if (SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N01, N1})) |
0 |
| 3839 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC); |
0 |
3839 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC); |
0 |
| 3840 |
} |
--- |
3840 |
} |
--- |
| 3841 |
|
--- |
3841 |
|
--- |
| 3842 |
// fold C2-(A+C1) -> (C2-C1)-A |
--- |
3842 |
// fold C2-(A+C1) -> (C2-C1)-A |
--- |
| 3843 |
if (N1.getOpcode() == ISD::ADD) { |
0 |
3843 |
if (N1.getOpcode() == ISD::ADD) { |
0 |
| 3844 |
SDValue N11 = N1.getOperand(1); |
0 |
3844 |
SDValue N11 = N1.getOperand(1); |
0 |
| 3845 |
if (SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N11})) |
0 |
3845 |
if (SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N11})) |
0 |
| 3846 |
return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0)); |
0 |
3846 |
return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0)); |
0 |
| 3847 |
} |
--- |
3847 |
} |
--- |
| 3848 |
|
--- |
3848 |
|
--- |
| 3849 |
// fold (A-C1)-C2 -> A-(C1+C2) |
--- |
3849 |
// fold (A-C1)-C2 -> A-(C1+C2) |
--- |
| 3850 |
if (N0.getOpcode() == ISD::SUB) { |
0 |
3850 |
if (N0.getOpcode() == ISD::SUB) { |
0 |
| 3851 |
SDValue N01 = N0.getOperand(1); |
0 |
3851 |
SDValue N01 = N0.getOperand(1); |
0 |
| 3852 |
if (SDValue NewC = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N01, N1})) |
0 |
3852 |
if (SDValue NewC = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N01, N1})) |
0 |
| 3853 |
return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), NewC); |
0 |
3853 |
return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), NewC); |
0 |
| 3854 |
} |
--- |
3854 |
} |
--- |
| 3855 |
|
--- |
3855 |
|
--- |
| 3856 |
// fold (c1-A)-c2 -> (c1-c2)-A |
--- |
3856 |
// fold (c1-A)-c2 -> (c1-c2)-A |
--- |
| 3857 |
if (N0.getOpcode() == ISD::SUB) { |
0 |
3857 |
if (N0.getOpcode() == ISD::SUB) { |
0 |
| 3858 |
SDValue N00 = N0.getOperand(0); |
0 |
3858 |
SDValue N00 = N0.getOperand(0); |
0 |
| 3859 |
if (SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N00, N1})) |
0 |
3859 |
if (SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N00, N1})) |
0 |
| 3860 |
return DAG.getNode(ISD::SUB, DL, VT, NewC, N0.getOperand(1)); |
0 |
3860 |
return DAG.getNode(ISD::SUB, DL, VT, NewC, N0.getOperand(1)); |
0 |
| 3861 |
} |
--- |
3861 |
} |
--- |
| 3862 |
|
--- |
3862 |
|
--- |
| 3863 |
// fold ((A+(B+or-C))-B) -> A+or-C |
--- |
3863 |
// fold ((A+(B+or-C))-B) -> A+or-C |
--- |
| 3864 |
if (N0.getOpcode() == ISD::ADD && |
0 |
3864 |
if (N0.getOpcode() == ISD::ADD && |
0 |
| 3865 |
(N0.getOperand(1).getOpcode() == ISD::SUB || |
0 |
3865 |
(N0.getOperand(1).getOpcode() == ISD::SUB || |
0 |
| 3866 |
N0.getOperand(1).getOpcode() == ISD::ADD) && |
0 |
3866 |
N0.getOperand(1).getOpcode() == ISD::ADD) && |
0 |
| 3867 |
N0.getOperand(1).getOperand(0) == N1) |
0 |
3867 |
N0.getOperand(1).getOperand(0) == N1) |
0 |
| 3868 |
return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0), |
0 |
3868 |
return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0), |
0 |
| 3869 |
N0.getOperand(1).getOperand(1)); |
0 |
3869 |
N0.getOperand(1).getOperand(1)); |
0 |
| 3870 |
|
--- |
3870 |
|
--- |
| 3871 |
// fold ((A+(C+B))-B) -> A+C |
--- |
3871 |
// fold ((A+(C+B))-B) -> A+C |
--- |
| 3872 |
if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD && |
0 |
3872 |
if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD && |
0 |
| 3873 |
N0.getOperand(1).getOperand(1) == N1) |
0 |
3873 |
N0.getOperand(1).getOperand(1) == N1) |
0 |
| 3874 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), |
0 |
3874 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), |
0 |
| 3875 |
N0.getOperand(1).getOperand(0)); |
0 |
3875 |
N0.getOperand(1).getOperand(0)); |
0 |
| 3876 |
|
--- |
3876 |
|
--- |
| 3877 |
// fold ((A-(B-C))-C) -> A-B |
--- |
3877 |
// fold ((A-(B-C))-C) -> A-B |
--- |
| 3878 |
if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB && |
0 |
3878 |
if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB && |
0 |
| 3879 |
N0.getOperand(1).getOperand(1) == N1) |
0 |
3879 |
N0.getOperand(1).getOperand(1) == N1) |
0 |
| 3880 |
return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), |
0 |
3880 |
return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), |
0 |
| 3881 |
N0.getOperand(1).getOperand(0)); |
0 |
3881 |
N0.getOperand(1).getOperand(0)); |
0 |
| 3882 |
|
--- |
3882 |
|
--- |
| 3883 |
// fold (A-(B-C)) -> A+(C-B) |
--- |
3883 |
// fold (A-(B-C)) -> A+(C-B) |
--- |
| 3884 |
if (N1.getOpcode() == ISD::SUB && N1.hasOneUse()) |
0 |
3884 |
if (N1.getOpcode() == ISD::SUB && N1.hasOneUse()) |
0 |
| 3885 |
return DAG.getNode(ISD::ADD, DL, VT, N0, |
0 |
3885 |
return DAG.getNode(ISD::ADD, DL, VT, N0, |
0 |
| 3886 |
DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(1), |
0 |
3886 |
DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(1), |
0 |
| 3887 |
N1.getOperand(0))); |
0 |
3887 |
N1.getOperand(0))); |
0 |
| 3888 |
|
--- |
3888 |
|
--- |
| 3889 |
// A - (A & B) -> A & (~B) |
--- |
3889 |
// A - (A & B) -> A & (~B) |
--- |
| 3890 |
if (N1.getOpcode() == ISD::AND) { |
0 |
3890 |
if (N1.getOpcode() == ISD::AND) { |
0 |
| 3891 |
SDValue A = N1.getOperand(0); |
0 |
3891 |
SDValue A = N1.getOperand(0); |
0 |
| 3892 |
SDValue B = N1.getOperand(1); |
0 |
3892 |
SDValue B = N1.getOperand(1); |
0 |
| 3893 |
if (A != N0) |
0 |
3893 |
if (A != N0) |
0 |
| 3894 |
std::swap(A, B); |
0 |
3894 |
std::swap(A, B); |
0 |
| 3895 |
if (A == N0 && |
0 |
3895 |
if (A == N0 && |
0 |
| 3896 |
(N1.hasOneUse() || isConstantOrConstantVector(B, /*NoOpaques=*/true))) { |
0 |
3896 |
(N1.hasOneUse() || isConstantOrConstantVector(B, /*NoOpaques=*/true))) { |
0 |
| 3897 |
SDValue InvB = |
--- |
3897 |
SDValue InvB = |
--- |
| 3898 |
DAG.getNode(ISD::XOR, DL, VT, B, DAG.getAllOnesConstant(DL, VT)); |
0 |
3898 |
DAG.getNode(ISD::XOR, DL, VT, B, DAG.getAllOnesConstant(DL, VT)); |
0 |
| 3899 |
return DAG.getNode(ISD::AND, DL, VT, A, InvB); |
0 |
3899 |
return DAG.getNode(ISD::AND, DL, VT, A, InvB); |
0 |
| 3900 |
} |
--- |
3900 |
} |
--- |
| 3901 |
} |
--- |
3901 |
} |
--- |
| 3902 |
|
--- |
3902 |
|
--- |
| 3903 |
// fold (X - (-Y * Z)) -> (X + (Y * Z)) |
--- |
3903 |
// fold (X - (-Y * Z)) -> (X + (Y * Z)) |
--- |
| 3904 |
if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) { |
0 |
3904 |
if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) { |
0 |
| 3905 |
if (N1.getOperand(0).getOpcode() == ISD::SUB && |
0 |
3905 |
if (N1.getOperand(0).getOpcode() == ISD::SUB && |
0 |
| 3906 |
isNullOrNullSplat(N1.getOperand(0).getOperand(0))) { |
0 |
3906 |
isNullOrNullSplat(N1.getOperand(0).getOperand(0))) { |
0 |
| 3907 |
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, |
0 |
3907 |
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, |
0 |
| 3908 |
N1.getOperand(0).getOperand(1), |
0 |
3908 |
N1.getOperand(0).getOperand(1), |
0 |
| 3909 |
N1.getOperand(1)); |
0 |
3909 |
N1.getOperand(1)); |
0 |
| 3910 |
return DAG.getNode(ISD::ADD, DL, VT, N0, Mul); |
0 |
3910 |
return DAG.getNode(ISD::ADD, DL, VT, N0, Mul); |
0 |
| 3911 |
} |
--- |
3911 |
} |
--- |
| 3912 |
if (N1.getOperand(1).getOpcode() == ISD::SUB && |
0 |
3912 |
if (N1.getOperand(1).getOpcode() == ISD::SUB && |
0 |
| 3913 |
isNullOrNullSplat(N1.getOperand(1).getOperand(0))) { |
0 |
3913 |
isNullOrNullSplat(N1.getOperand(1).getOperand(0))) { |
0 |
| 3914 |
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, |
0 |
3914 |
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, |
0 |
| 3915 |
N1.getOperand(0), |
0 |
3915 |
N1.getOperand(0), |
0 |
| 3916 |
N1.getOperand(1).getOperand(1)); |
0 |
3916 |
N1.getOperand(1).getOperand(1)); |
0 |
| 3917 |
return DAG.getNode(ISD::ADD, DL, VT, N0, Mul); |
0 |
3917 |
return DAG.getNode(ISD::ADD, DL, VT, N0, Mul); |
0 |
| 3918 |
} |
--- |
3918 |
} |
--- |
| 3919 |
} |
--- |
3919 |
} |
--- |
| 3920 |
|
--- |
3920 |
|
--- |
| 3921 |
// If either operand of a sub is undef, the result is undef |
--- |
3921 |
// If either operand of a sub is undef, the result is undef |
--- |
| 3922 |
if (N0.isUndef()) |
0 |
3922 |
if (N0.isUndef()) |
0 |
| 3923 |
return N0; |
0 |
3923 |
return N0; |
0 |
| 3924 |
if (N1.isUndef()) |
0 |
3924 |
if (N1.isUndef()) |
0 |
| 3925 |
return N1; |
0 |
3925 |
return N1; |
0 |
| 3926 |
|
--- |
3926 |
|
--- |
| 3927 |
if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG)) |
0 |
3927 |
if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG)) |
0 |
| 3928 |
return V; |
0 |
3928 |
return V; |
0 |
| 3929 |
|
--- |
3929 |
|
--- |
| 3930 |
if (SDValue V = foldAddSubOfSignBit(N, DAG)) |
0 |
3930 |
if (SDValue V = foldAddSubOfSignBit(N, DAG)) |
0 |
| 3931 |
return V; |
0 |
3931 |
return V; |
0 |
| 3932 |
|
--- |
3932 |
|
--- |
| 3933 |
if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N))) |
0 |
3933 |
if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N))) |
0 |
| 3934 |
return V; |
0 |
3934 |
return V; |
0 |
| 3935 |
|
--- |
3935 |
|
--- |
| 3936 |
if (SDValue V = foldSubToUSubSat(VT, N)) |
0 |
3936 |
if (SDValue V = foldSubToUSubSat(VT, N)) |
0 |
| 3937 |
return V; |
0 |
3937 |
return V; |
0 |
| 3938 |
|
--- |
3938 |
|
--- |
| 3939 |
// (x - y) - 1 -> add (xor y, -1), x |
--- |
3939 |
// (x - y) - 1 -> add (xor y, -1), x |
--- |
| 3940 |
if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && isOneOrOneSplat(N1)) { |
0 |
3940 |
if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && isOneOrOneSplat(N1)) { |
0 |
| 3941 |
SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1), |
0 |
3941 |
SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1), |
0 |
| 3942 |
DAG.getAllOnesConstant(DL, VT)); |
0 |
3942 |
DAG.getAllOnesConstant(DL, VT)); |
0 |
| 3943 |
return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0)); |
0 |
3943 |
return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0)); |
0 |
| 3944 |
} |
--- |
3944 |
} |
--- |
| 3945 |
|
--- |
3945 |
|
--- |
| 3946 |
// Look for: |
--- |
3946 |
// Look for: |
--- |
| 3947 |
// sub y, (xor x, -1) |
--- |
3947 |
// sub y, (xor x, -1) |
--- |
| 3948 |
// And if the target does not like this form then turn into: |
--- |
3948 |
// And if the target does not like this form then turn into: |
--- |
| 3949 |
// add (add x, y), 1 |
--- |
3949 |
// add (add x, y), 1 |
--- |
| 3950 |
if (TLI.preferIncOfAddToSubOfNot(VT) && N1.hasOneUse() && isBitwiseNot(N1)) { |
0 |
3950 |
if (TLI.preferIncOfAddToSubOfNot(VT) && N1.hasOneUse() && isBitwiseNot(N1)) { |
0 |
| 3951 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(0)); |
0 |
3951 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(0)); |
0 |
| 3952 |
return DAG.getNode(ISD::ADD, DL, VT, Add, DAG.getConstant(1, DL, VT)); |
0 |
3952 |
return DAG.getNode(ISD::ADD, DL, VT, Add, DAG.getConstant(1, DL, VT)); |
0 |
| 3953 |
} |
--- |
3953 |
} |
--- |
| 3954 |
|
--- |
3954 |
|
--- |
| 3955 |
// Hoist one-use addition by non-opaque constant: |
--- |
3955 |
// Hoist one-use addition by non-opaque constant: |
--- |
| 3956 |
// (x + C) - y -> (x - y) + C |
--- |
3956 |
// (x + C) - y -> (x - y) + C |
--- |
| 3957 |
if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && |
0 |
3957 |
if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && |
0 |
| 3958 |
isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) { |
0 |
3958 |
isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) { |
0 |
| 3959 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1); |
0 |
3959 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1); |
0 |
| 3960 |
return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1)); |
0 |
3960 |
return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1)); |
0 |
| 3961 |
} |
--- |
3961 |
} |
--- |
| 3962 |
// y - (x + C) -> (y - x) - C |
--- |
3962 |
// y - (x + C) -> (y - x) - C |
--- |
| 3963 |
if (N1.getOpcode() == ISD::ADD && N1.hasOneUse() && |
0 |
3963 |
if (N1.getOpcode() == ISD::ADD && N1.hasOneUse() && |
0 |
| 3964 |
isConstantOrConstantVector(N1.getOperand(1), /*NoOpaques=*/true)) { |
0 |
3964 |
isConstantOrConstantVector(N1.getOperand(1), /*NoOpaques=*/true)) { |
0 |
| 3965 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0)); |
0 |
3965 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0)); |
0 |
| 3966 |
return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1)); |
0 |
3966 |
return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1)); |
0 |
| 3967 |
} |
--- |
3967 |
} |
--- |
| 3968 |
// (x - C) - y -> (x - y) - C |
--- |
3968 |
// (x - C) - y -> (x - y) - C |
--- |
| 3969 |
// This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors. |
--- |
3969 |
// This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors. |
--- |
| 3970 |
if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && |
0 |
3970 |
if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && |
0 |
| 3971 |
isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) { |
0 |
3971 |
isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) { |
0 |
| 3972 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1); |
0 |
3972 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1); |
0 |
| 3973 |
return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1)); |
0 |
3973 |
return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1)); |
0 |
| 3974 |
} |
--- |
3974 |
} |
--- |
| 3975 |
// (C - x) - y -> C - (x + y) |
--- |
3975 |
// (C - x) - y -> C - (x + y) |
--- |
| 3976 |
if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && |
0 |
3976 |
if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && |
0 |
| 3977 |
isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) { |
0 |
3977 |
isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) { |
0 |
| 3978 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), N1); |
0 |
3978 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), N1); |
0 |
| 3979 |
return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add); |
0 |
3979 |
return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add); |
0 |
| 3980 |
} |
--- |
3980 |
} |
--- |
| 3981 |
|
--- |
3981 |
|
--- |
| 3982 |
// If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1' |
--- |
3982 |
// If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1' |
--- |
| 3983 |
// rather than 'sub 0/1' (the sext should get folded). |
--- |
3983 |
// rather than 'sub 0/1' (the sext should get folded). |
--- |
| 3984 |
// sub X, (zext i1 Y) --> add X, (sext i1 Y) |
--- |
3984 |
// sub X, (zext i1 Y) --> add X, (sext i1 Y) |
--- |
| 3985 |
if (N1.getOpcode() == ISD::ZERO_EXTEND && |
0 |
3985 |
if (N1.getOpcode() == ISD::ZERO_EXTEND && |
0 |
| 3986 |
N1.getOperand(0).getScalarValueSizeInBits() == 1 && |
0 |
3986 |
N1.getOperand(0).getScalarValueSizeInBits() == 1 && |
0 |
| 3987 |
TLI.getBooleanContents(VT) == |
0 |
3987 |
TLI.getBooleanContents(VT) == |
0 |
| 3988 |
TargetLowering::ZeroOrNegativeOneBooleanContent) { |
--- |
3988 |
TargetLowering::ZeroOrNegativeOneBooleanContent) { |
--- |
| 3989 |
SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0)); |
0 |
3989 |
SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0)); |
0 |
| 3990 |
return DAG.getNode(ISD::ADD, DL, VT, N0, SExt); |
0 |
3990 |
return DAG.getNode(ISD::ADD, DL, VT, N0, SExt); |
0 |
| 3991 |
} |
--- |
3991 |
} |
--- |
| 3992 |
|
--- |
3992 |
|
--- |
| 3993 |
// fold Y = sra (X, size(X)-1); sub (xor (X, Y), Y) -> (abs X) |
--- |
3993 |
// fold Y = sra (X, size(X)-1); sub (xor (X, Y), Y) -> (abs X) |
--- |
| 3994 |
if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { |
0 |
3994 |
if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { |
0 |
| 3995 |
if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) { |
0 |
3995 |
if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) { |
0 |
| 3996 |
SDValue X0 = N0.getOperand(0), X1 = N0.getOperand(1); |
0 |
3996 |
SDValue X0 = N0.getOperand(0), X1 = N0.getOperand(1); |
0 |
| 3997 |
SDValue S0 = N1.getOperand(0); |
0 |
3997 |
SDValue S0 = N1.getOperand(0); |
0 |
| 3998 |
if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0)) |
0 |
3998 |
if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0)) |
0 |
| 3999 |
if (ConstantSDNode *C = isConstOrConstSplat(N1.getOperand(1))) |
0 |
3999 |
if (ConstantSDNode *C = isConstOrConstSplat(N1.getOperand(1))) |
0 |
| 4000 |
if (C->getAPIntValue() == (VT.getScalarSizeInBits() - 1)) |
0 |
4000 |
if (C->getAPIntValue() == (VT.getScalarSizeInBits() - 1)) |
0 |
| 4001 |
return DAG.getNode(ISD::ABS, SDLoc(N), VT, S0); |
0 |
4001 |
return DAG.getNode(ISD::ABS, SDLoc(N), VT, S0); |
0 |
| 4002 |
} |
--- |
4002 |
} |
--- |
| 4003 |
} |
--- |
4003 |
} |
--- |
| 4004 |
|
--- |
4004 |
|
--- |
| 4005 |
// If the relocation model supports it, consider symbol offsets. |
--- |
4005 |
// If the relocation model supports it, consider symbol offsets. |
--- |
| 4006 |
if (GlobalAddressSDNode *GA = dyn_cast(N0)) |
0 |
4006 |
if (GlobalAddressSDNode *GA = dyn_cast(N0)) |
0 |
| 4007 |
if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { |
0 |
4007 |
if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { |
0 |
| 4008 |
// fold (sub Sym+c1, Sym+c2) -> c1-c2 |
--- |
4008 |
// fold (sub Sym+c1, Sym+c2) -> c1-c2 |
--- |
| 4009 |
if (GlobalAddressSDNode *GB = dyn_cast(N1)) |
0 |
4009 |
if (GlobalAddressSDNode *GB = dyn_cast(N1)) |
0 |
| 4010 |
if (GA->getGlobal() == GB->getGlobal()) |
0 |
4010 |
if (GA->getGlobal() == GB->getGlobal()) |
0 |
| 4011 |
return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), |
0 |
4011 |
return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), |
0 |
| 4012 |
DL, VT); |
0 |
4012 |
DL, VT); |
0 |
| 4013 |
} |
--- |
4013 |
} |
--- |
| 4014 |
|
--- |
4014 |
|
--- |
| 4015 |
// sub X, (sextinreg Y i1) -> add X, (and Y 1) |
--- |
4015 |
// sub X, (sextinreg Y i1) -> add X, (and Y 1) |
--- |
| 4016 |
if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { |
0 |
4016 |
if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { |
0 |
| 4017 |
VTSDNode *TN = cast(N1.getOperand(1)); |
0 |
4017 |
VTSDNode *TN = cast(N1.getOperand(1)); |
0 |
| 4018 |
if (TN->getVT() == MVT::i1) { |
0 |
4018 |
if (TN->getVT() == MVT::i1) { |
0 |
| 4019 |
SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0), |
0 |
4019 |
SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0), |
0 |
| 4020 |
DAG.getConstant(1, DL, VT)); |
0 |
4020 |
DAG.getConstant(1, DL, VT)); |
0 |
| 4021 |
return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt); |
0 |
4021 |
return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt); |
0 |
| 4022 |
} |
--- |
4022 |
} |
--- |
| 4023 |
} |
--- |
4023 |
} |
--- |
| 4024 |
|
--- |
4024 |
|
--- |
| 4025 |
// canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C)) |
--- |
4025 |
// canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C)) |
--- |
| 4026 |
if (N1.getOpcode() == ISD::VSCALE && N1.hasOneUse()) { |
0 |
4026 |
if (N1.getOpcode() == ISD::VSCALE && N1.hasOneUse()) { |
0 |
| 4027 |
const APInt &IntVal = N1.getConstantOperandAPInt(0); |
0 |
4027 |
const APInt &IntVal = N1.getConstantOperandAPInt(0); |
0 |
| 4028 |
return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal)); |
0 |
4028 |
return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal)); |
0 |
| 4029 |
} |
--- |
4029 |
} |
--- |
| 4030 |
|
--- |
4030 |
|
--- |
| 4031 |
// canonicalize (sub X, step_vector(C)) to (add X, step_vector(-C)) |
--- |
4031 |
// canonicalize (sub X, step_vector(C)) to (add X, step_vector(-C)) |
--- |
| 4032 |
if (N1.getOpcode() == ISD::STEP_VECTOR && N1.hasOneUse()) { |
0 |
4032 |
if (N1.getOpcode() == ISD::STEP_VECTOR && N1.hasOneUse()) { |
0 |
| 4033 |
APInt NewStep = -N1.getConstantOperandAPInt(0); |
0 |
4033 |
APInt NewStep = -N1.getConstantOperandAPInt(0); |
0 |
| 4034 |
return DAG.getNode(ISD::ADD, DL, VT, N0, |
0 |
4034 |
return DAG.getNode(ISD::ADD, DL, VT, N0, |
0 |
| 4035 |
DAG.getStepVector(DL, VT, NewStep)); |
0 |
4035 |
DAG.getStepVector(DL, VT, NewStep)); |
0 |
| 4036 |
} |
0 |
4036 |
} |
0 |
| 4037 |
|
--- |
4037 |
|
--- |
| 4038 |
// Prefer an add for more folding potential and possibly better codegen: |
--- |
4038 |
// Prefer an add for more folding potential and possibly better codegen: |
--- |
| 4039 |
// sub N0, (lshr N10, width-1) --> add N0, (ashr N10, width-1) |
--- |
4039 |
// sub N0, (lshr N10, width-1) --> add N0, (ashr N10, width-1) |
--- |
| 4040 |
if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { |
0 |
4040 |
if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { |
0 |
| 4041 |
SDValue ShAmt = N1.getOperand(1); |
0 |
4041 |
SDValue ShAmt = N1.getOperand(1); |
0 |
| 4042 |
ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt); |
0 |
4042 |
ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt); |
0 |
| 4043 |
if (ShAmtC && |
0 |
4043 |
if (ShAmtC && |
0 |
| 4044 |
ShAmtC->getAPIntValue() == (N1.getScalarValueSizeInBits() - 1)) { |
0 |
4044 |
ShAmtC->getAPIntValue() == (N1.getScalarValueSizeInBits() - 1)) { |
0 |
| 4045 |
SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt); |
0 |
4045 |
SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt); |
0 |
| 4046 |
return DAG.getNode(ISD::ADD, DL, VT, N0, SRA); |
0 |
4046 |
return DAG.getNode(ISD::ADD, DL, VT, N0, SRA); |
0 |
| 4047 |
} |
--- |
4047 |
} |
--- |
| 4048 |
} |
--- |
4048 |
} |
--- |
| 4049 |
|
--- |
4049 |
|
--- |
| 4050 |
// As with the previous fold, prefer add for more folding potential. |
--- |
4050 |
// As with the previous fold, prefer add for more folding potential. |
--- |
| 4051 |
// Subtracting SMIN/0 is the same as adding SMIN/0: |
--- |
4051 |
// Subtracting SMIN/0 is the same as adding SMIN/0: |
--- |
| 4052 |
// N0 - (X << BW-1) --> N0 + (X << BW-1) |
--- |
4052 |
// N0 - (X << BW-1) --> N0 + (X << BW-1) |
--- |
| 4053 |
if (N1.getOpcode() == ISD::SHL) { |
0 |
4053 |
if (N1.getOpcode() == ISD::SHL) { |
0 |
| 4054 |
ConstantSDNode *ShlC = isConstOrConstSplat(N1.getOperand(1)); |
0 |
4054 |
ConstantSDNode *ShlC = isConstOrConstSplat(N1.getOperand(1)); |
0 |
| 4055 |
if (ShlC && ShlC->getAPIntValue() == VT.getScalarSizeInBits() - 1) |
0 |
4055 |
if (ShlC && ShlC->getAPIntValue() == VT.getScalarSizeInBits() - 1) |
0 |
| 4056 |
return DAG.getNode(ISD::ADD, DL, VT, N1, N0); |
0 |
4056 |
return DAG.getNode(ISD::ADD, DL, VT, N1, N0); |
0 |
| 4057 |
} |
--- |
4057 |
} |
--- |
| 4058 |
|
--- |
4058 |
|
--- |
| 4059 |
// (sub (usubo_carry X, 0, Carry), Y) -> (usubo_carry X, Y, Carry) |
--- |
4059 |
// (sub (usubo_carry X, 0, Carry), Y) -> (usubo_carry X, Y, Carry) |
--- |
| 4060 |
if (N0.getOpcode() == ISD::USUBO_CARRY && isNullConstant(N0.getOperand(1)) && |
0 |
4060 |
if (N0.getOpcode() == ISD::USUBO_CARRY && isNullConstant(N0.getOperand(1)) && |
0 |
| 4061 |
N0.getResNo() == 0 && N0.hasOneUse()) |
0 |
4061 |
N0.getResNo() == 0 && N0.hasOneUse()) |
0 |
| 4062 |
return DAG.getNode(ISD::USUBO_CARRY, DL, N0->getVTList(), |
0 |
4062 |
return DAG.getNode(ISD::USUBO_CARRY, DL, N0->getVTList(), |
0 |
| 4063 |
N0.getOperand(0), N1, N0.getOperand(2)); |
0 |
4063 |
N0.getOperand(0), N1, N0.getOperand(2)); |
0 |
| 4064 |
|
--- |
4064 |
|
--- |
| 4065 |
if (TLI.isOperationLegalOrCustom(ISD::UADDO_CARRY, VT)) { |
0 |
4065 |
if (TLI.isOperationLegalOrCustom(ISD::UADDO_CARRY, VT)) { |
0 |
| 4066 |
// (sub Carry, X) -> (uaddo_carry (sub 0, X), 0, Carry) |
--- |
4066 |
// (sub Carry, X) -> (uaddo_carry (sub 0, X), 0, Carry) |
--- |
| 4067 |
if (SDValue Carry = getAsCarry(TLI, N0)) { |
0 |
4067 |
if (SDValue Carry = getAsCarry(TLI, N0)) { |
0 |
| 4068 |
SDValue X = N1; |
0 |
4068 |
SDValue X = N1; |
0 |
| 4069 |
SDValue Zero = DAG.getConstant(0, DL, VT); |
0 |
4069 |
SDValue Zero = DAG.getConstant(0, DL, VT); |
0 |
| 4070 |
SDValue NegX = DAG.getNode(ISD::SUB, DL, VT, Zero, X); |
0 |
4070 |
SDValue NegX = DAG.getNode(ISD::SUB, DL, VT, Zero, X); |
0 |
| 4071 |
return DAG.getNode(ISD::UADDO_CARRY, DL, |
0 |
4071 |
return DAG.getNode(ISD::UADDO_CARRY, DL, |
0 |
| 4072 |
DAG.getVTList(VT, Carry.getValueType()), NegX, Zero, |
0 |
4072 |
DAG.getVTList(VT, Carry.getValueType()), NegX, Zero, |
0 |
| 4073 |
Carry); |
0 |
4073 |
Carry); |
0 |
| 4074 |
} |
--- |
4074 |
} |
--- |
| 4075 |
} |
--- |
4075 |
} |
--- |
| 4076 |
|
--- |
4076 |
|
--- |
| 4077 |
// If there's no chance of borrowing from adjacent bits, then sub is xor: |
--- |
4077 |
// If there's no chance of borrowing from adjacent bits, then sub is xor: |
--- |
| 4078 |
// sub C0, X --> xor X, C0 |
--- |
4078 |
// sub C0, X --> xor X, C0 |
--- |
| 4079 |
if (ConstantSDNode *C0 = isConstOrConstSplat(N0)) { |
0 |
4079 |
if (ConstantSDNode *C0 = isConstOrConstSplat(N0)) { |
0 |
| 4080 |
if (!C0->isOpaque()) { |
0 |
4080 |
if (!C0->isOpaque()) { |
0 |
| 4081 |
const APInt &C0Val = C0->getAPIntValue(); |
0 |
4081 |
const APInt &C0Val = C0->getAPIntValue(); |
0 |
| 4082 |
const APInt &MaybeOnes = ~DAG.computeKnownBits(N1).Zero; |
0 |
4082 |
const APInt &MaybeOnes = ~DAG.computeKnownBits(N1).Zero; |
0 |
| 4083 |
if ((C0Val - MaybeOnes) == (C0Val ^ MaybeOnes)) |
0 |
4083 |
if ((C0Val - MaybeOnes) == (C0Val ^ MaybeOnes)) |
0 |
| 4084 |
return DAG.getNode(ISD::XOR, DL, VT, N1, N0); |
0 |
4084 |
return DAG.getNode(ISD::XOR, DL, VT, N1, N0); |
0 |
| 4085 |
} |
0 |
4085 |
} |
0 |
| 4086 |
} |
--- |
4086 |
} |
--- |
| 4087 |
|
--- |
4087 |
|
--- |
| 4088 |
// max(a,b) - min(a,b) --> abd(a,b) |
--- |
4088 |
// max(a,b) - min(a,b) --> abd(a,b) |
--- |
| 4089 |
auto MatchSubMaxMin = [&](unsigned Max, unsigned Min, unsigned Abd) { |
0 |
4089 |
auto MatchSubMaxMin = [&](unsigned Max, unsigned Min, unsigned Abd) { |
0 |
| 4090 |
if (N0.getOpcode() != Max || N1.getOpcode() != Min) |
0 |
4090 |
if (N0.getOpcode() != Max || N1.getOpcode() != Min) |
0 |
| 4091 |
return SDValue(); |
0 |
4091 |
return SDValue(); |
0 |
| 4092 |
if ((N0.getOperand(0) != N1.getOperand(0) || |
0 |
4092 |
if ((N0.getOperand(0) != N1.getOperand(0) || |
0 |
| 4093 |
N0.getOperand(1) != N1.getOperand(1)) && |
0 |
4093 |
N0.getOperand(1) != N1.getOperand(1)) && |
0 |
| 4094 |
(N0.getOperand(0) != N1.getOperand(1) || |
0 |
4094 |
(N0.getOperand(0) != N1.getOperand(1) || |
0 |
| 4095 |
N0.getOperand(1) != N1.getOperand(0))) |
0 |
4095 |
N0.getOperand(1) != N1.getOperand(0))) |
0 |
| 4096 |
return SDValue(); |
0 |
4096 |
return SDValue(); |
0 |
| 4097 |
if (!hasOperation(Abd, VT)) |
0 |
4097 |
if (!hasOperation(Abd, VT)) |
0 |
| 4098 |
return SDValue(); |
0 |
4098 |
return SDValue(); |
0 |
| 4099 |
return DAG.getNode(Abd, DL, VT, N0.getOperand(0), N0.getOperand(1)); |
0 |
4099 |
return DAG.getNode(Abd, DL, VT, N0.getOperand(0), N0.getOperand(1)); |
0 |
| 4100 |
}; |
0 |
4100 |
}; |
0 |
| 4101 |
if (SDValue R = MatchSubMaxMin(ISD::SMAX, ISD::SMIN, ISD::ABDS)) |
0 |
4101 |
if (SDValue R = MatchSubMaxMin(ISD::SMAX, ISD::SMIN, ISD::ABDS)) |
0 |
| 4102 |
return R; |
0 |
4102 |
return R; |
0 |
| 4103 |
if (SDValue R = MatchSubMaxMin(ISD::UMAX, ISD::UMIN, ISD::ABDU)) |
0 |
4103 |
if (SDValue R = MatchSubMaxMin(ISD::UMAX, ISD::UMIN, ISD::ABDU)) |
0 |
| 4104 |
return R; |
0 |
4104 |
return R; |
0 |
| 4105 |
|
--- |
4105 |
|
--- |
| 4106 |
return SDValue(); |
0 |
4106 |
return SDValue(); |
0 |
| 4107 |
} |
0 |
4107 |
} |
0 |
| 4108 |
|
--- |
4108 |
|
--- |
| 4109 |
SDValue DAGCombiner::visitSUBSAT(SDNode *N) { |
0 |
4109 |
SDValue DAGCombiner::visitSUBSAT(SDNode *N) { |
0 |
| 4110 |
unsigned Opcode = N->getOpcode(); |
0 |
4110 |
unsigned Opcode = N->getOpcode(); |
0 |
| 4111 |
SDValue N0 = N->getOperand(0); |
0 |
4111 |
SDValue N0 = N->getOperand(0); |
0 |
| 4112 |
SDValue N1 = N->getOperand(1); |
0 |
4112 |
SDValue N1 = N->getOperand(1); |
0 |
| 4113 |
EVT VT = N0.getValueType(); |
0 |
4113 |
EVT VT = N0.getValueType(); |
0 |
| 4114 |
bool IsSigned = Opcode == ISD::SSUBSAT; |
0 |
4114 |
bool IsSigned = Opcode == ISD::SSUBSAT; |
0 |
| 4115 |
SDLoc DL(N); |
0 |
4115 |
SDLoc DL(N); |
0 |
| 4116 |
|
--- |
4116 |
|
--- |
| 4117 |
// fold (sub_sat x, undef) -> 0 |
--- |
4117 |
// fold (sub_sat x, undef) -> 0 |
--- |
| 4118 |
if (N0.isUndef() || N1.isUndef()) |
0 |
4118 |
if (N0.isUndef() || N1.isUndef()) |
0 |
| 4119 |
return DAG.getConstant(0, DL, VT); |
0 |
4119 |
return DAG.getConstant(0, DL, VT); |
0 |
| 4120 |
|
--- |
4120 |
|
--- |
| 4121 |
// fold (sub_sat x, x) -> 0 |
--- |
4121 |
// fold (sub_sat x, x) -> 0 |
--- |
| 4122 |
if (N0 == N1) |
0 |
4122 |
if (N0 == N1) |
0 |
| 4123 |
return DAG.getConstant(0, DL, VT); |
0 |
4123 |
return DAG.getConstant(0, DL, VT); |
0 |
| 4124 |
|
--- |
4124 |
|
--- |
| 4125 |
// fold (sub_sat c1, c2) -> c3 |
--- |
4125 |
// fold (sub_sat c1, c2) -> c3 |
--- |
| 4126 |
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1})) |
0 |
4126 |
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1})) |
0 |
| 4127 |
return C; |
0 |
4127 |
return C; |
0 |
| 4128 |
|
--- |
4128 |
|
--- |
| 4129 |
// fold vector ops |
--- |
4129 |
// fold vector ops |
--- |
| 4130 |
if (VT.isVector()) { |
0 |
4130 |
if (VT.isVector()) { |
0 |
| 4131 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
4131 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 4132 |
return FoldedVOp; |
0 |
4132 |
return FoldedVOp; |
0 |
| 4133 |
|
--- |
4133 |
|
--- |
| 4134 |
// fold (sub_sat x, 0) -> x, vector edition |
--- |
4134 |
// fold (sub_sat x, 0) -> x, vector edition |
--- |
| 4135 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
4135 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
| 4136 |
return N0; |
0 |
4136 |
return N0; |
0 |
| 4137 |
} |
--- |
4137 |
} |
--- |
| 4138 |
|
--- |
4138 |
|
--- |
| 4139 |
// fold (sub_sat x, 0) -> x |
--- |
4139 |
// fold (sub_sat x, 0) -> x |
--- |
| 4140 |
if (isNullConstant(N1)) |
0 |
4140 |
if (isNullConstant(N1)) |
0 |
| 4141 |
return N0; |
0 |
4141 |
return N0; |
0 |
| 4142 |
|
--- |
4142 |
|
--- |
| 4143 |
// If it cannot overflow, transform into an sub. |
--- |
4143 |
// If it cannot overflow, transform into an sub. |
--- |
| 4144 |
if (DAG.computeOverflowForSub(IsSigned, N0, N1) == SelectionDAG::OFK_Never) |
0 |
4144 |
if (DAG.computeOverflowForSub(IsSigned, N0, N1) == SelectionDAG::OFK_Never) |
0 |
| 4145 |
return DAG.getNode(ISD::SUB, DL, VT, N0, N1); |
0 |
4145 |
return DAG.getNode(ISD::SUB, DL, VT, N0, N1); |
0 |
| 4146 |
|
--- |
4146 |
|
--- |
| 4147 |
return SDValue(); |
0 |
4147 |
return SDValue(); |
0 |
| 4148 |
} |
0 |
4148 |
} |
0 |
| 4149 |
|
--- |
4149 |
|
--- |
| 4150 |
SDValue DAGCombiner::visitSUBC(SDNode *N) { |
0 |
4150 |
SDValue DAGCombiner::visitSUBC(SDNode *N) { |
0 |
| 4151 |
SDValue N0 = N->getOperand(0); |
0 |
4151 |
SDValue N0 = N->getOperand(0); |
0 |
| 4152 |
SDValue N1 = N->getOperand(1); |
0 |
4152 |
SDValue N1 = N->getOperand(1); |
0 |
| 4153 |
EVT VT = N0.getValueType(); |
0 |
4153 |
EVT VT = N0.getValueType(); |
0 |
| 4154 |
SDLoc DL(N); |
0 |
4154 |
SDLoc DL(N); |
0 |
| 4155 |
|
--- |
4155 |
|
--- |
| 4156 |
// If the flag result is dead, turn this into an SUB. |
--- |
4156 |
// If the flag result is dead, turn this into an SUB. |
--- |
| 4157 |
if (!N->hasAnyUseOfValue(1)) |
0 |
4157 |
if (!N->hasAnyUseOfValue(1)) |
0 |
| 4158 |
return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1), |
0 |
4158 |
return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1), |
0 |
| 4159 |
DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue)); |
0 |
4159 |
DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue)); |
0 |
| 4160 |
|
--- |
4160 |
|
--- |
| 4161 |
// fold (subc x, x) -> 0 + no borrow |
--- |
4161 |
// fold (subc x, x) -> 0 + no borrow |
--- |
| 4162 |
if (N0 == N1) |
0 |
4162 |
if (N0 == N1) |
0 |
| 4163 |
return CombineTo(N, DAG.getConstant(0, DL, VT), |
0 |
4163 |
return CombineTo(N, DAG.getConstant(0, DL, VT), |
0 |
| 4164 |
DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue)); |
0 |
4164 |
DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue)); |
0 |
| 4165 |
|
--- |
4165 |
|
--- |
| 4166 |
// fold (subc x, 0) -> x + no borrow |
--- |
4166 |
// fold (subc x, 0) -> x + no borrow |
--- |
| 4167 |
if (isNullConstant(N1)) |
0 |
4167 |
if (isNullConstant(N1)) |
0 |
| 4168 |
return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue)); |
0 |
4168 |
return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue)); |
0 |
| 4169 |
|
--- |
4169 |
|
--- |
| 4170 |
// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow |
--- |
4170 |
// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow |
--- |
| 4171 |
if (isAllOnesConstant(N0)) |
0 |
4171 |
if (isAllOnesConstant(N0)) |
0 |
| 4172 |
return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0), |
0 |
4172 |
return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0), |
0 |
| 4173 |
DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue)); |
0 |
4173 |
DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue)); |
0 |
| 4174 |
|
--- |
4174 |
|
--- |
| 4175 |
return SDValue(); |
0 |
4175 |
return SDValue(); |
0 |
| 4176 |
} |
0 |
4176 |
} |
0 |
| 4177 |
|
--- |
4177 |
|
--- |
| 4178 |
SDValue DAGCombiner::visitSUBO(SDNode *N) { |
0 |
4178 |
SDValue DAGCombiner::visitSUBO(SDNode *N) { |
0 |
| 4179 |
SDValue N0 = N->getOperand(0); |
0 |
4179 |
SDValue N0 = N->getOperand(0); |
0 |
| 4180 |
SDValue N1 = N->getOperand(1); |
0 |
4180 |
SDValue N1 = N->getOperand(1); |
0 |
| 4181 |
EVT VT = N0.getValueType(); |
0 |
4181 |
EVT VT = N0.getValueType(); |
0 |
| 4182 |
bool IsSigned = (ISD::SSUBO == N->getOpcode()); |
0 |
4182 |
bool IsSigned = (ISD::SSUBO == N->getOpcode()); |
0 |
| 4183 |
|
--- |
4183 |
|
--- |
| 4184 |
EVT CarryVT = N->getValueType(1); |
0 |
4184 |
EVT CarryVT = N->getValueType(1); |
0 |
| 4185 |
SDLoc DL(N); |
0 |
4185 |
SDLoc DL(N); |
0 |
| 4186 |
|
--- |
4186 |
|
--- |
| 4187 |
// If the flag result is dead, turn this into an SUB. |
--- |
4187 |
// If the flag result is dead, turn this into an SUB. |
--- |
| 4188 |
if (!N->hasAnyUseOfValue(1)) |
0 |
4188 |
if (!N->hasAnyUseOfValue(1)) |
0 |
| 4189 |
return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1), |
0 |
4189 |
return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1), |
0 |
| 4190 |
DAG.getUNDEF(CarryVT)); |
0 |
4190 |
DAG.getUNDEF(CarryVT)); |
0 |
| 4191 |
|
--- |
4191 |
|
--- |
| 4192 |
// fold (subo x, x) -> 0 + no borrow |
--- |
4192 |
// fold (subo x, x) -> 0 + no borrow |
--- |
| 4193 |
if (N0 == N1) |
0 |
4193 |
if (N0 == N1) |
0 |
| 4194 |
return CombineTo(N, DAG.getConstant(0, DL, VT), |
0 |
4194 |
return CombineTo(N, DAG.getConstant(0, DL, VT), |
0 |
| 4195 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
4195 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
| 4196 |
|
--- |
4196 |
|
--- |
| 4197 |
ConstantSDNode *N1C = getAsNonOpaqueConstant(N1); |
0 |
4197 |
ConstantSDNode *N1C = getAsNonOpaqueConstant(N1); |
0 |
| 4198 |
|
--- |
4198 |
|
--- |
| 4199 |
// fold (subox, c) -> (addo x, -c) |
--- |
4199 |
// fold (subox, c) -> (addo x, -c) |
--- |
| 4200 |
if (IsSigned && N1C && !N1C->isMinSignedValue()) { |
0 |
4200 |
if (IsSigned && N1C && !N1C->isMinSignedValue()) { |
0 |
| 4201 |
return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0, |
0 |
4201 |
return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0, |
0 |
| 4202 |
DAG.getConstant(-N1C->getAPIntValue(), DL, VT)); |
0 |
4202 |
DAG.getConstant(-N1C->getAPIntValue(), DL, VT)); |
0 |
| 4203 |
} |
--- |
4203 |
} |
--- |
| 4204 |
|
--- |
4204 |
|
--- |
| 4205 |
// fold (subo x, 0) -> x + no borrow |
--- |
4205 |
// fold (subo x, 0) -> x + no borrow |
--- |
| 4206 |
if (isNullOrNullSplat(N1)) |
0 |
4206 |
if (isNullOrNullSplat(N1)) |
0 |
| 4207 |
return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT)); |
0 |
4207 |
return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT)); |
0 |
| 4208 |
|
--- |
4208 |
|
--- |
| 4209 |
// If it cannot overflow, transform into an sub. |
--- |
4209 |
// If it cannot overflow, transform into an sub. |
--- |
| 4210 |
if (DAG.computeOverflowForSub(IsSigned, N0, N1) == SelectionDAG::OFK_Never) |
0 |
4210 |
if (DAG.computeOverflowForSub(IsSigned, N0, N1) == SelectionDAG::OFK_Never) |
0 |
| 4211 |
return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1), |
0 |
4211 |
return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1), |
0 |
| 4212 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
4212 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
| 4213 |
|
--- |
4213 |
|
--- |
| 4214 |
// Canonicalize (usubo -1, x) -> ~x, i.e. (xor x, -1) + no borrow |
--- |
4214 |
// Canonicalize (usubo -1, x) -> ~x, i.e. (xor x, -1) + no borrow |
--- |
| 4215 |
if (!IsSigned && isAllOnesOrAllOnesSplat(N0)) |
0 |
4215 |
if (!IsSigned && isAllOnesOrAllOnesSplat(N0)) |
0 |
| 4216 |
return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0), |
0 |
4216 |
return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0), |
0 |
| 4217 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
4217 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
| 4218 |
|
--- |
4218 |
|
--- |
| 4219 |
return SDValue(); |
0 |
4219 |
return SDValue(); |
0 |
| 4220 |
} |
0 |
4220 |
} |
0 |
| 4221 |
|
--- |
4221 |
|
--- |
| 4222 |
SDValue DAGCombiner::visitSUBE(SDNode *N) { |
0 |
4222 |
SDValue DAGCombiner::visitSUBE(SDNode *N) { |
0 |
| 4223 |
SDValue N0 = N->getOperand(0); |
0 |
4223 |
SDValue N0 = N->getOperand(0); |
0 |
| 4224 |
SDValue N1 = N->getOperand(1); |
0 |
4224 |
SDValue N1 = N->getOperand(1); |
0 |
| 4225 |
SDValue CarryIn = N->getOperand(2); |
0 |
4225 |
SDValue CarryIn = N->getOperand(2); |
0 |
| 4226 |
|
--- |
4226 |
|
--- |
| 4227 |
// fold (sube x, y, false) -> (subc x, y) |
--- |
4227 |
// fold (sube x, y, false) -> (subc x, y) |
--- |
| 4228 |
if (CarryIn.getOpcode() == ISD::CARRY_FALSE) |
0 |
4228 |
if (CarryIn.getOpcode() == ISD::CARRY_FALSE) |
0 |
| 4229 |
return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1); |
0 |
4229 |
return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1); |
0 |
| 4230 |
|
--- |
4230 |
|
--- |
| 4231 |
return SDValue(); |
0 |
4231 |
return SDValue(); |
0 |
| 4232 |
} |
--- |
4232 |
} |
--- |
| 4233 |
|
--- |
4233 |
|
--- |
| 4234 |
SDValue DAGCombiner::visitUSUBO_CARRY(SDNode *N) { |
0 |
4234 |
SDValue DAGCombiner::visitUSUBO_CARRY(SDNode *N) { |
0 |
| 4235 |
SDValue N0 = N->getOperand(0); |
0 |
4235 |
SDValue N0 = N->getOperand(0); |
0 |
| 4236 |
SDValue N1 = N->getOperand(1); |
0 |
4236 |
SDValue N1 = N->getOperand(1); |
0 |
| 4237 |
SDValue CarryIn = N->getOperand(2); |
0 |
4237 |
SDValue CarryIn = N->getOperand(2); |
0 |
| 4238 |
|
--- |
4238 |
|
--- |
| 4239 |
// fold (usubo_carry x, y, false) -> (usubo x, y) |
--- |
4239 |
// fold (usubo_carry x, y, false) -> (usubo x, y) |
--- |
| 4240 |
if (isNullConstant(CarryIn)) { |
0 |
4240 |
if (isNullConstant(CarryIn)) { |
0 |
| 4241 |
if (!LegalOperations || |
0 |
4241 |
if (!LegalOperations || |
0 |
| 4242 |
TLI.isOperationLegalOrCustom(ISD::USUBO, N->getValueType(0))) |
0 |
4242 |
TLI.isOperationLegalOrCustom(ISD::USUBO, N->getValueType(0))) |
0 |
| 4243 |
return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1); |
0 |
4243 |
return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1); |
0 |
| 4244 |
} |
--- |
4244 |
} |
--- |
| 4245 |
|
--- |
4245 |
|
--- |
| 4246 |
return SDValue(); |
0 |
4246 |
return SDValue(); |
0 |
| 4247 |
} |
--- |
4247 |
} |
--- |
| 4248 |
|
--- |
4248 |
|
--- |
| 4249 |
SDValue DAGCombiner::visitSSUBO_CARRY(SDNode *N) { |
0 |
4249 |
SDValue DAGCombiner::visitSSUBO_CARRY(SDNode *N) { |
0 |
| 4250 |
SDValue N0 = N->getOperand(0); |
0 |
4250 |
SDValue N0 = N->getOperand(0); |
0 |
| 4251 |
SDValue N1 = N->getOperand(1); |
0 |
4251 |
SDValue N1 = N->getOperand(1); |
0 |
| 4252 |
SDValue CarryIn = N->getOperand(2); |
0 |
4252 |
SDValue CarryIn = N->getOperand(2); |
0 |
| 4253 |
|
--- |
4253 |
|
--- |
| 4254 |
// fold (ssubo_carry x, y, false) -> (ssubo x, y) |
--- |
4254 |
// fold (ssubo_carry x, y, false) -> (ssubo x, y) |
--- |
| 4255 |
if (isNullConstant(CarryIn)) { |
0 |
4255 |
if (isNullConstant(CarryIn)) { |
0 |
| 4256 |
if (!LegalOperations || |
0 |
4256 |
if (!LegalOperations || |
0 |
| 4257 |
TLI.isOperationLegalOrCustom(ISD::SSUBO, N->getValueType(0))) |
0 |
4257 |
TLI.isOperationLegalOrCustom(ISD::SSUBO, N->getValueType(0))) |
0 |
| 4258 |
return DAG.getNode(ISD::SSUBO, SDLoc(N), N->getVTList(), N0, N1); |
0 |
4258 |
return DAG.getNode(ISD::SSUBO, SDLoc(N), N->getVTList(), N0, N1); |
0 |
| 4259 |
} |
--- |
4259 |
} |
--- |
| 4260 |
|
--- |
4260 |
|
--- |
| 4261 |
return SDValue(); |
0 |
4261 |
return SDValue(); |
0 |
| 4262 |
} |
--- |
4262 |
} |
--- |
| 4263 |
|
--- |
4263 |
|
--- |
| 4264 |
// Notice that "mulfix" can be any of SMULFIX, SMULFIXSAT, UMULFIX and |
--- |
4264 |
// Notice that "mulfix" can be any of SMULFIX, SMULFIXSAT, UMULFIX and |
--- |
| 4265 |
// UMULFIXSAT here. |
--- |
4265 |
// UMULFIXSAT here. |
--- |
| 4266 |
SDValue DAGCombiner::visitMULFIX(SDNode *N) { |
0 |
4266 |
SDValue DAGCombiner::visitMULFIX(SDNode *N) { |
0 |
| 4267 |
SDValue N0 = N->getOperand(0); |
0 |
4267 |
SDValue N0 = N->getOperand(0); |
0 |
| 4268 |
SDValue N1 = N->getOperand(1); |
0 |
4268 |
SDValue N1 = N->getOperand(1); |
0 |
| 4269 |
SDValue Scale = N->getOperand(2); |
0 |
4269 |
SDValue Scale = N->getOperand(2); |
0 |
| 4270 |
EVT VT = N0.getValueType(); |
0 |
4270 |
EVT VT = N0.getValueType(); |
0 |
| 4271 |
|
--- |
4271 |
|
--- |
| 4272 |
// fold (mulfix x, undef, scale) -> 0 |
--- |
4272 |
// fold (mulfix x, undef, scale) -> 0 |
--- |
| 4273 |
if (N0.isUndef() || N1.isUndef()) |
0 |
4273 |
if (N0.isUndef() || N1.isUndef()) |
0 |
| 4274 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
4274 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
| 4275 |
|
--- |
4275 |
|
--- |
| 4276 |
// Canonicalize constant to RHS (vector doesn't have to splat) |
--- |
4276 |
// Canonicalize constant to RHS (vector doesn't have to splat) |
--- |
| 4277 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
4277 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 4278 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
4278 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 4279 |
return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale); |
0 |
4279 |
return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale); |
0 |
| 4280 |
|
--- |
4280 |
|
--- |
| 4281 |
// fold (mulfix x, 0, scale) -> 0 |
--- |
4281 |
// fold (mulfix x, 0, scale) -> 0 |
--- |
| 4282 |
if (isNullConstant(N1)) |
0 |
4282 |
if (isNullConstant(N1)) |
0 |
| 4283 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
4283 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
| 4284 |
|
--- |
4284 |
|
--- |
| 4285 |
return SDValue(); |
0 |
4285 |
return SDValue(); |
0 |
| 4286 |
} |
--- |
4286 |
} |
--- |
| 4287 |
|
--- |
4287 |
|
--- |
| 4288 |
SDValue DAGCombiner::visitMUL(SDNode *N) { |
0 |
4288 |
SDValue DAGCombiner::visitMUL(SDNode *N) { |
0 |
| 4289 |
SDValue N0 = N->getOperand(0); |
0 |
4289 |
SDValue N0 = N->getOperand(0); |
0 |
| 4290 |
SDValue N1 = N->getOperand(1); |
0 |
4290 |
SDValue N1 = N->getOperand(1); |
0 |
| 4291 |
EVT VT = N0.getValueType(); |
0 |
4291 |
EVT VT = N0.getValueType(); |
0 |
| 4292 |
SDLoc DL(N); |
0 |
4292 |
SDLoc DL(N); |
0 |
| 4293 |
|
--- |
4293 |
|
--- |
| 4294 |
// fold (mul x, undef) -> 0 |
--- |
4294 |
// fold (mul x, undef) -> 0 |
--- |
| 4295 |
if (N0.isUndef() || N1.isUndef()) |
0 |
4295 |
if (N0.isUndef() || N1.isUndef()) |
0 |
| 4296 |
return DAG.getConstant(0, DL, VT); |
0 |
4296 |
return DAG.getConstant(0, DL, VT); |
0 |
| 4297 |
|
--- |
4297 |
|
--- |
| 4298 |
// fold (mul c1, c2) -> c1*c2 |
--- |
4298 |
// fold (mul c1, c2) -> c1*c2 |
--- |
| 4299 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::MUL, DL, VT, {N0, N1})) |
0 |
4299 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::MUL, DL, VT, {N0, N1})) |
0 |
| 4300 |
return C; |
0 |
4300 |
return C; |
0 |
| 4301 |
|
--- |
4301 |
|
--- |
| 4302 |
// canonicalize constant to RHS (vector doesn't have to splat) |
--- |
4302 |
// canonicalize constant to RHS (vector doesn't have to splat) |
--- |
| 4303 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
4303 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 4304 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
4304 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 4305 |
return DAG.getNode(ISD::MUL, DL, VT, N1, N0); |
0 |
4305 |
return DAG.getNode(ISD::MUL, DL, VT, N1, N0); |
0 |
| 4306 |
|
--- |
4306 |
|
--- |
| 4307 |
bool N1IsConst = false; |
0 |
4307 |
bool N1IsConst = false; |
0 |
| 4308 |
bool N1IsOpaqueConst = false; |
0 |
4308 |
bool N1IsOpaqueConst = false; |
0 |
| 4309 |
APInt ConstValue1; |
0 |
4309 |
APInt ConstValue1; |
0 |
| 4310 |
|
--- |
4310 |
|
--- |
| 4311 |
// fold vector ops |
--- |
4311 |
// fold vector ops |
--- |
| 4312 |
if (VT.isVector()) { |
0 |
4312 |
if (VT.isVector()) { |
0 |
| 4313 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
4313 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 4314 |
return FoldedVOp; |
0 |
4314 |
return FoldedVOp; |
0 |
| 4315 |
|
--- |
4315 |
|
--- |
| 4316 |
N1IsConst = ISD::isConstantSplatVector(N1.getNode(), ConstValue1); |
0 |
4316 |
N1IsConst = ISD::isConstantSplatVector(N1.getNode(), ConstValue1); |
0 |
| 4317 |
assert((!N1IsConst || |
0 |
4317 |
assert((!N1IsConst || |
0 |
| 4318 |
ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && |
--- |
4318 |
ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && |
--- |
| 4319 |
"Splat APInt should be element width"); |
--- |
4319 |
"Splat APInt should be element width"); |
--- |
| 4320 |
} else { |
--- |
4320 |
} else { |
--- |
| 4321 |
N1IsConst = isa(N1); |
0 |
4321 |
N1IsConst = isa(N1); |
0 |
| 4322 |
if (N1IsConst) { |
0 |
4322 |
if (N1IsConst) { |
0 |
| 4323 |
ConstValue1 = cast(N1)->getAPIntValue(); |
0 |
4323 |
ConstValue1 = cast(N1)->getAPIntValue(); |
0 |
| 4324 |
N1IsOpaqueConst = cast(N1)->isOpaque(); |
0 |
4324 |
N1IsOpaqueConst = cast(N1)->isOpaque(); |
0 |
| 4325 |
} |
--- |
4325 |
} |
--- |
| 4326 |
} |
--- |
4326 |
} |
--- |
| 4327 |
|
--- |
4327 |
|
--- |
| 4328 |
// fold (mul x, 0) -> 0 |
--- |
4328 |
// fold (mul x, 0) -> 0 |
--- |
| 4329 |
if (N1IsConst && ConstValue1.isZero()) |
0 |
4329 |
if (N1IsConst && ConstValue1.isZero()) |
0 |
| 4330 |
return N1; |
0 |
4330 |
return N1; |
0 |
| 4331 |
|
--- |
4331 |
|
--- |
| 4332 |
// fold (mul x, 1) -> x |
--- |
4332 |
// fold (mul x, 1) -> x |
--- |
| 4333 |
if (N1IsConst && ConstValue1.isOne()) |
0 |
4333 |
if (N1IsConst && ConstValue1.isOne()) |
0 |
| 4334 |
return N0; |
0 |
4334 |
return N0; |
0 |
| 4335 |
|
--- |
4335 |
|
--- |
| 4336 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
4336 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 4337 |
return NewSel; |
0 |
4337 |
return NewSel; |
0 |
| 4338 |
|
--- |
4338 |
|
--- |
| 4339 |
// fold (mul x, -1) -> 0-x |
--- |
4339 |
// fold (mul x, -1) -> 0-x |
--- |
| 4340 |
if (N1IsConst && ConstValue1.isAllOnes()) |
0 |
4340 |
if (N1IsConst && ConstValue1.isAllOnes()) |
0 |
| 4341 |
return DAG.getNegative(N0, DL, VT); |
0 |
4341 |
return DAG.getNegative(N0, DL, VT); |
0 |
| 4342 |
|
--- |
4342 |
|
--- |
| 4343 |
// fold (mul x, (1 << c)) -> x << c |
--- |
4343 |
// fold (mul x, (1 << c)) -> x << c |
--- |
| 4344 |
if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) && |
0 |
4344 |
if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) && |
0 |
| 4345 |
DAG.isKnownToBeAPowerOfTwo(N1) && |
0 |
4345 |
DAG.isKnownToBeAPowerOfTwo(N1) && |
0 |
| 4346 |
(!VT.isVector() || Level <= AfterLegalizeVectorOps)) { |
0 |
4346 |
(!VT.isVector() || Level <= AfterLegalizeVectorOps)) { |
0 |
| 4347 |
SDValue LogBase2 = BuildLogBase2(N1, DL); |
0 |
4347 |
SDValue LogBase2 = BuildLogBase2(N1, DL); |
0 |
| 4348 |
EVT ShiftVT = getShiftAmountTy(N0.getValueType()); |
0 |
4348 |
EVT ShiftVT = getShiftAmountTy(N0.getValueType()); |
0 |
| 4349 |
SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT); |
0 |
4349 |
SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT); |
0 |
| 4350 |
return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc); |
0 |
4350 |
return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc); |
0 |
| 4351 |
} |
--- |
4351 |
} |
--- |
| 4352 |
|
--- |
4352 |
|
--- |
| 4353 |
// fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c |
--- |
4353 |
// fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c |
--- |
| 4354 |
if (N1IsConst && !N1IsOpaqueConst && ConstValue1.isNegatedPowerOf2()) { |
0 |
4354 |
if (N1IsConst && !N1IsOpaqueConst && ConstValue1.isNegatedPowerOf2()) { |
0 |
| 4355 |
unsigned Log2Val = (-ConstValue1).logBase2(); |
0 |
4355 |
unsigned Log2Val = (-ConstValue1).logBase2(); |
0 |
| 4356 |
EVT ShiftVT = getShiftAmountTy(N0.getValueType()); |
0 |
4356 |
EVT ShiftVT = getShiftAmountTy(N0.getValueType()); |
0 |
| 4357 |
|
--- |
4357 |
|
--- |
| 4358 |
// FIXME: If the input is something that is easily negated (e.g. a |
--- |
4358 |
// FIXME: If the input is something that is easily negated (e.g. a |
--- |
| 4359 |
// single-use add), we should put the negate there. |
--- |
4359 |
// single-use add), we should put the negate there. |
--- |
| 4360 |
return DAG.getNode(ISD::SUB, DL, VT, |
0 |
4360 |
return DAG.getNode(ISD::SUB, DL, VT, |
0 |
| 4361 |
DAG.getConstant(0, DL, VT), |
0 |
4361 |
DAG.getConstant(0, DL, VT), |
0 |
| 4362 |
DAG.getNode(ISD::SHL, DL, VT, N0, |
0 |
4362 |
DAG.getNode(ISD::SHL, DL, VT, N0, |
0 |
| 4363 |
DAG.getConstant(Log2Val, DL, ShiftVT))); |
0 |
4363 |
DAG.getConstant(Log2Val, DL, ShiftVT))); |
0 |
| 4364 |
} |
--- |
4364 |
} |
--- |
| 4365 |
|
--- |
4365 |
|
--- |
| 4366 |
// Attempt to reuse an existing umul_lohi/smul_lohi node, but only if the |
--- |
4366 |
// Attempt to reuse an existing umul_lohi/smul_lohi node, but only if the |
--- |
| 4367 |
// hi result is in use in case we hit this mid-legalization. |
--- |
4367 |
// hi result is in use in case we hit this mid-legalization. |
--- |
| 4368 |
for (unsigned LoHiOpc : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { |
0 |
4368 |
for (unsigned LoHiOpc : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { |
0 |
| 4369 |
if (!LegalOperations || TLI.isOperationLegalOrCustom(LoHiOpc, VT)) { |
0 |
4369 |
if (!LegalOperations || TLI.isOperationLegalOrCustom(LoHiOpc, VT)) { |
0 |
| 4370 |
SDVTList LoHiVT = DAG.getVTList(VT, VT); |
0 |
4370 |
SDVTList LoHiVT = DAG.getVTList(VT, VT); |
0 |
| 4371 |
// TODO: Can we match commutable operands with getNodeIfExists? |
--- |
4371 |
// TODO: Can we match commutable operands with getNodeIfExists? |
--- |
| 4372 |
if (SDNode *LoHi = DAG.getNodeIfExists(LoHiOpc, LoHiVT, {N0, N1})) |
0 |
4372 |
if (SDNode *LoHi = DAG.getNodeIfExists(LoHiOpc, LoHiVT, {N0, N1})) |
0 |
| 4373 |
if (LoHi->hasAnyUseOfValue(1)) |
0 |
4373 |
if (LoHi->hasAnyUseOfValue(1)) |
0 |
| 4374 |
return SDValue(LoHi, 0); |
0 |
4374 |
return SDValue(LoHi, 0); |
0 |
| 4375 |
if (SDNode *LoHi = DAG.getNodeIfExists(LoHiOpc, LoHiVT, {N1, N0})) |
0 |
4375 |
if (SDNode *LoHi = DAG.getNodeIfExists(LoHiOpc, LoHiVT, {N1, N0})) |
0 |
| 4376 |
if (LoHi->hasAnyUseOfValue(1)) |
0 |
4376 |
if (LoHi->hasAnyUseOfValue(1)) |
0 |
| 4377 |
return SDValue(LoHi, 0); |
0 |
4377 |
return SDValue(LoHi, 0); |
0 |
| 4378 |
} |
--- |
4378 |
} |
--- |
| 4379 |
} |
--- |
4379 |
} |
--- |
| 4380 |
|
--- |
4380 |
|
--- |
| 4381 |
// Try to transform: |
--- |
4381 |
// Try to transform: |
--- |
| 4382 |
// (1) multiply-by-(power-of-2 +/- 1) into shift and add/sub. |
--- |
4382 |
// (1) multiply-by-(power-of-2 +/- 1) into shift and add/sub. |
--- |
| 4383 |
// mul x, (2^N + 1) --> add (shl x, N), x |
--- |
4383 |
// mul x, (2^N + 1) --> add (shl x, N), x |
--- |
| 4384 |
// mul x, (2^N - 1) --> sub (shl x, N), x |
--- |
4384 |
// mul x, (2^N - 1) --> sub (shl x, N), x |
--- |
| 4385 |
// Examples: x * 33 --> (x << 5) + x |
--- |
4385 |
// Examples: x * 33 --> (x << 5) + x |
--- |
| 4386 |
// x * 15 --> (x << 4) - x |
--- |
4386 |
// x * 15 --> (x << 4) - x |
--- |
| 4387 |
// x * -33 --> -((x << 5) + x) |
--- |
4387 |
// x * -33 --> -((x << 5) + x) |
--- |
| 4388 |
// x * -15 --> -((x << 4) - x) ; this reduces --> x - (x << 4) |
--- |
4388 |
// x * -15 --> -((x << 4) - x) ; this reduces --> x - (x << 4) |
--- |
| 4389 |
// (2) multiply-by-(power-of-2 +/- power-of-2) into shifts and add/sub. |
--- |
4389 |
// (2) multiply-by-(power-of-2 +/- power-of-2) into shifts and add/sub. |
--- |
| 4390 |
// mul x, (2^N + 2^M) --> (add (shl x, N), (shl x, M)) |
--- |
4390 |
// mul x, (2^N + 2^M) --> (add (shl x, N), (shl x, M)) |
--- |
| 4391 |
// mul x, (2^N - 2^M) --> (sub (shl x, N), (shl x, M)) |
--- |
4391 |
// mul x, (2^N - 2^M) --> (sub (shl x, N), (shl x, M)) |
--- |
| 4392 |
// Examples: x * 0x8800 --> (x << 15) + (x << 11) |
--- |
4392 |
// Examples: x * 0x8800 --> (x << 15) + (x << 11) |
--- |
| 4393 |
// x * 0xf800 --> (x << 16) - (x << 11) |
--- |
4393 |
// x * 0xf800 --> (x << 16) - (x << 11) |
--- |
| 4394 |
// x * -0x8800 --> -((x << 15) + (x << 11)) |
--- |
4394 |
// x * -0x8800 --> -((x << 15) + (x << 11)) |
--- |
| 4395 |
// x * -0xf800 --> -((x << 16) - (x << 11)) ; (x << 11) - (x << 16) |
--- |
4395 |
// x * -0xf800 --> -((x << 16) - (x << 11)) ; (x << 11) - (x << 16) |
--- |
| 4396 |
if (N1IsConst && TLI.decomposeMulByConstant(*DAG.getContext(), VT, N1)) { |
0 |
4396 |
if (N1IsConst && TLI.decomposeMulByConstant(*DAG.getContext(), VT, N1)) { |
0 |
| 4397 |
// TODO: We could handle more general decomposition of any constant by |
--- |
4397 |
// TODO: We could handle more general decomposition of any constant by |
--- |
| 4398 |
// having the target set a limit on number of ops and making a |
--- |
4398 |
// having the target set a limit on number of ops and making a |
--- |
| 4399 |
// callback to determine that sequence (similar to sqrt expansion). |
--- |
4399 |
// callback to determine that sequence (similar to sqrt expansion). |
--- |
| 4400 |
unsigned MathOp = ISD::DELETED_NODE; |
0 |
4400 |
unsigned MathOp = ISD::DELETED_NODE; |
0 |
| 4401 |
APInt MulC = ConstValue1.abs(); |
0 |
4401 |
APInt MulC = ConstValue1.abs(); |
0 |
| 4402 |
// The constant `2` should be treated as (2^0 + 1). |
--- |
4402 |
// The constant `2` should be treated as (2^0 + 1). |
--- |
| 4403 |
unsigned TZeros = MulC == 2 ? 0 : MulC.countr_zero(); |
0 |
4403 |
unsigned TZeros = MulC == 2 ? 0 : MulC.countr_zero(); |
0 |
| 4404 |
MulC.lshrInPlace(TZeros); |
0 |
4404 |
MulC.lshrInPlace(TZeros); |
0 |
| 4405 |
if ((MulC - 1).isPowerOf2()) |
0 |
4405 |
if ((MulC - 1).isPowerOf2()) |
0 |
| 4406 |
MathOp = ISD::ADD; |
0 |
4406 |
MathOp = ISD::ADD; |
0 |
| 4407 |
else if ((MulC + 1).isPowerOf2()) |
0 |
4407 |
else if ((MulC + 1).isPowerOf2()) |
0 |
| 4408 |
MathOp = ISD::SUB; |
0 |
4408 |
MathOp = ISD::SUB; |
0 |
| 4409 |
|
--- |
4409 |
|
--- |
| 4410 |
if (MathOp != ISD::DELETED_NODE) { |
0 |
4410 |
if (MathOp != ISD::DELETED_NODE) { |
0 |
| 4411 |
unsigned ShAmt = |
--- |
4411 |
unsigned ShAmt = |
--- |
| 4412 |
MathOp == ISD::ADD ? (MulC - 1).logBase2() : (MulC + 1).logBase2(); |
0 |
4412 |
MathOp == ISD::ADD ? (MulC - 1).logBase2() : (MulC + 1).logBase2(); |
0 |
| 4413 |
ShAmt += TZeros; |
0 |
4413 |
ShAmt += TZeros; |
0 |
| 4414 |
assert(ShAmt < VT.getScalarSizeInBits() && |
0 |
4414 |
assert(ShAmt < VT.getScalarSizeInBits() && |
0 |
| 4415 |
"multiply-by-constant generated out of bounds shift"); |
--- |
4415 |
"multiply-by-constant generated out of bounds shift"); |
--- |
| 4416 |
SDValue Shl = |
--- |
4416 |
SDValue Shl = |
--- |
| 4417 |
DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT)); |
0 |
4417 |
DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT)); |
0 |
| 4418 |
SDValue R = |
--- |
4418 |
SDValue R = |
--- |
| 4419 |
TZeros ? DAG.getNode(MathOp, DL, VT, Shl, |
0 |
4419 |
TZeros ? DAG.getNode(MathOp, DL, VT, Shl, |
0 |
| 4420 |
DAG.getNode(ISD::SHL, DL, VT, N0, |
0 |
4420 |
DAG.getNode(ISD::SHL, DL, VT, N0, |
0 |
| 4421 |
DAG.getConstant(TZeros, DL, VT))) |
0 |
4421 |
DAG.getConstant(TZeros, DL, VT))) |
0 |
| 4422 |
: DAG.getNode(MathOp, DL, VT, Shl, N0); |
0 |
4422 |
: DAG.getNode(MathOp, DL, VT, Shl, N0); |
0 |
| 4423 |
if (ConstValue1.isNegative()) |
0 |
4423 |
if (ConstValue1.isNegative()) |
0 |
| 4424 |
R = DAG.getNegative(R, DL, VT); |
0 |
4424 |
R = DAG.getNegative(R, DL, VT); |
0 |
| 4425 |
return R; |
0 |
4425 |
return R; |
0 |
| 4426 |
} |
--- |
4426 |
} |
--- |
| 4427 |
} |
0 |
4427 |
} |
0 |
| 4428 |
|
--- |
4428 |
|
--- |
| 4429 |
// (mul (shl X, c1), c2) -> (mul X, c2 << c1) |
--- |
4429 |
// (mul (shl X, c1), c2) -> (mul X, c2 << c1) |
--- |
| 4430 |
if (N0.getOpcode() == ISD::SHL) { |
0 |
4430 |
if (N0.getOpcode() == ISD::SHL) { |
0 |
| 4431 |
SDValue N01 = N0.getOperand(1); |
0 |
4431 |
SDValue N01 = N0.getOperand(1); |
0 |
| 4432 |
if (SDValue C3 = DAG.FoldConstantArithmetic(ISD::SHL, DL, VT, {N1, N01})) |
0 |
4432 |
if (SDValue C3 = DAG.FoldConstantArithmetic(ISD::SHL, DL, VT, {N1, N01})) |
0 |
| 4433 |
return DAG.getNode(ISD::MUL, DL, VT, N0.getOperand(0), C3); |
0 |
4433 |
return DAG.getNode(ISD::MUL, DL, VT, N0.getOperand(0), C3); |
0 |
| 4434 |
} |
--- |
4434 |
} |
--- |
| 4435 |
|
--- |
4435 |
|
--- |
| 4436 |
// Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one |
--- |
4436 |
// Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one |
--- |
| 4437 |
// use. |
--- |
4437 |
// use. |
--- |
| 4438 |
{ |
--- |
4438 |
{ |
--- |
| 4439 |
SDValue Sh, Y; |
0 |
4439 |
SDValue Sh, Y; |
0 |
| 4440 |
|
--- |
4440 |
|
--- |
| 4441 |
// Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). |
--- |
4441 |
// Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). |
--- |
| 4442 |
if (N0.getOpcode() == ISD::SHL && |
0 |
4442 |
if (N0.getOpcode() == ISD::SHL && |
0 |
| 4443 |
isConstantOrConstantVector(N0.getOperand(1)) && N0->hasOneUse()) { |
0 |
4443 |
isConstantOrConstantVector(N0.getOperand(1)) && N0->hasOneUse()) { |
0 |
| 4444 |
Sh = N0; Y = N1; |
0 |
4444 |
Sh = N0; Y = N1; |
0 |
| 4445 |
} else if (N1.getOpcode() == ISD::SHL && |
0 |
4445 |
} else if (N1.getOpcode() == ISD::SHL && |
0 |
| 4446 |
isConstantOrConstantVector(N1.getOperand(1)) && |
0 |
4446 |
isConstantOrConstantVector(N1.getOperand(1)) && |
0 |
| 4447 |
N1->hasOneUse()) { |
0 |
4447 |
N1->hasOneUse()) { |
0 |
| 4448 |
Sh = N1; Y = N0; |
0 |
4448 |
Sh = N1; Y = N0; |
0 |
| 4449 |
} |
--- |
4449 |
} |
--- |
| 4450 |
|
--- |
4450 |
|
--- |
| 4451 |
if (Sh.getNode()) { |
0 |
4451 |
if (Sh.getNode()) { |
0 |
| 4452 |
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, Sh.getOperand(0), Y); |
0 |
4452 |
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, Sh.getOperand(0), Y); |
0 |
| 4453 |
return DAG.getNode(ISD::SHL, DL, VT, Mul, Sh.getOperand(1)); |
0 |
4453 |
return DAG.getNode(ISD::SHL, DL, VT, Mul, Sh.getOperand(1)); |
0 |
| 4454 |
} |
--- |
4454 |
} |
--- |
| 4455 |
} |
--- |
4455 |
} |
--- |
| 4456 |
|
--- |
4456 |
|
--- |
| 4457 |
// fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) |
--- |
4457 |
// fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) |
--- |
| 4458 |
if (N0.getOpcode() == ISD::ADD && |
0 |
4458 |
if (N0.getOpcode() == ISD::ADD && |
0 |
| 4459 |
DAG.isConstantIntBuildVectorOrConstantInt(N1) && |
0 |
4459 |
DAG.isConstantIntBuildVectorOrConstantInt(N1) && |
0 |
| 4460 |
DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) && |
0 |
4460 |
DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) && |
0 |
| 4461 |
isMulAddWithConstProfitable(N, N0, N1)) |
0 |
4461 |
isMulAddWithConstProfitable(N, N0, N1)) |
0 |
| 4462 |
return DAG.getNode( |
0 |
4462 |
return DAG.getNode( |
0 |
| 4463 |
ISD::ADD, DL, VT, |
--- |
4463 |
ISD::ADD, DL, VT, |
--- |
| 4464 |
DAG.getNode(ISD::MUL, SDLoc(N0), VT, N0.getOperand(0), N1), |
0 |
4464 |
DAG.getNode(ISD::MUL, SDLoc(N0), VT, N0.getOperand(0), N1), |
0 |
| 4465 |
DAG.getNode(ISD::MUL, SDLoc(N1), VT, N0.getOperand(1), N1)); |
0 |
4465 |
DAG.getNode(ISD::MUL, SDLoc(N1), VT, N0.getOperand(1), N1)); |
0 |
| 4466 |
|
--- |
4466 |
|
--- |
| 4467 |
// Fold (mul (vscale * C0), C1) to (vscale * (C0 * C1)). |
--- |
4467 |
// Fold (mul (vscale * C0), C1) to (vscale * (C0 * C1)). |
--- |
| 4468 |
ConstantSDNode *NC1 = isConstOrConstSplat(N1); |
0 |
4468 |
ConstantSDNode *NC1 = isConstOrConstSplat(N1); |
0 |
| 4469 |
if (N0.getOpcode() == ISD::VSCALE && NC1) { |
0 |
4469 |
if (N0.getOpcode() == ISD::VSCALE && NC1) { |
0 |
| 4470 |
const APInt &C0 = N0.getConstantOperandAPInt(0); |
0 |
4470 |
const APInt &C0 = N0.getConstantOperandAPInt(0); |
0 |
| 4471 |
const APInt &C1 = NC1->getAPIntValue(); |
0 |
4471 |
const APInt &C1 = NC1->getAPIntValue(); |
0 |
| 4472 |
return DAG.getVScale(DL, VT, C0 * C1); |
0 |
4472 |
return DAG.getVScale(DL, VT, C0 * C1); |
0 |
| 4473 |
} |
--- |
4473 |
} |
--- |
| 4474 |
|
--- |
4474 |
|
--- |
| 4475 |
// Fold (mul step_vector(C0), C1) to (step_vector(C0 * C1)). |
--- |
4475 |
// Fold (mul step_vector(C0), C1) to (step_vector(C0 * C1)). |
--- |
| 4476 |
APInt MulVal; |
0 |
4476 |
APInt MulVal; |
0 |
| 4477 |
if (N0.getOpcode() == ISD::STEP_VECTOR && |
0 |
4477 |
if (N0.getOpcode() == ISD::STEP_VECTOR && |
0 |
| 4478 |
ISD::isConstantSplatVector(N1.getNode(), MulVal)) { |
0 |
4478 |
ISD::isConstantSplatVector(N1.getNode(), MulVal)) { |
0 |
| 4479 |
const APInt &C0 = N0.getConstantOperandAPInt(0); |
0 |
4479 |
const APInt &C0 = N0.getConstantOperandAPInt(0); |
0 |
| 4480 |
APInt NewStep = C0 * MulVal; |
0 |
4480 |
APInt NewStep = C0 * MulVal; |
0 |
| 4481 |
return DAG.getStepVector(DL, VT, NewStep); |
0 |
4481 |
return DAG.getStepVector(DL, VT, NewStep); |
0 |
| 4482 |
} |
0 |
4482 |
} |
0 |
| 4483 |
|
--- |
4483 |
|
--- |
| 4484 |
// Fold ((mul x, 0/undef) -> 0, |
--- |
4484 |
// Fold ((mul x, 0/undef) -> 0, |
--- |
| 4485 |
// (mul x, 1) -> x) -> x) |
--- |
4485 |
// (mul x, 1) -> x) -> x) |
--- |
| 4486 |
// -> and(x, mask) |
--- |
4486 |
// -> and(x, mask) |
--- |
| 4487 |
// We can replace vectors with '0' and '1' factors with a clearing mask. |
--- |
4487 |
// We can replace vectors with '0' and '1' factors with a clearing mask. |
--- |
| 4488 |
if (VT.isFixedLengthVector()) { |
0 |
4488 |
if (VT.isFixedLengthVector()) { |
0 |
| 4489 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
4489 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
| 4490 |
SmallBitVector ClearMask; |
0 |
4490 |
SmallBitVector ClearMask; |
0 |
| 4491 |
ClearMask.reserve(NumElts); |
0 |
4491 |
ClearMask.reserve(NumElts); |
0 |
| 4492 |
auto IsClearMask = [&ClearMask](ConstantSDNode *V) { |
0 |
4492 |
auto IsClearMask = [&ClearMask](ConstantSDNode *V) { |
0 |
| 4493 |
if (!V || V->isZero()) { |
0 |
4493 |
if (!V || V->isZero()) { |
0 |
| 4494 |
ClearMask.push_back(true); |
0 |
4494 |
ClearMask.push_back(true); |
0 |
| 4495 |
return true; |
0 |
4495 |
return true; |
0 |
| 4496 |
} |
--- |
4496 |
} |
--- |
| 4497 |
ClearMask.push_back(false); |
0 |
4497 |
ClearMask.push_back(false); |
0 |
| 4498 |
return V->isOne(); |
0 |
4498 |
return V->isOne(); |
0 |
| 4499 |
}; |
0 |
4499 |
}; |
0 |
| 4500 |
if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::AND, VT)) && |
0 |
4500 |
if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::AND, VT)) && |
0 |
| 4501 |
ISD::matchUnaryPredicate(N1, IsClearMask, /*AllowUndefs*/ true)) { |
0 |
4501 |
ISD::matchUnaryPredicate(N1, IsClearMask, /*AllowUndefs*/ true)) { |
0 |
| 4502 |
assert(N1.getOpcode() == ISD::BUILD_VECTOR && "Unknown constant vector"); |
0 |
4502 |
assert(N1.getOpcode() == ISD::BUILD_VECTOR && "Unknown constant vector"); |
0 |
| 4503 |
EVT LegalSVT = N1.getOperand(0).getValueType(); |
0 |
4503 |
EVT LegalSVT = N1.getOperand(0).getValueType(); |
0 |
| 4504 |
SDValue Zero = DAG.getConstant(0, DL, LegalSVT); |
0 |
4504 |
SDValue Zero = DAG.getConstant(0, DL, LegalSVT); |
0 |
| 4505 |
SDValue AllOnes = DAG.getAllOnesConstant(DL, LegalSVT); |
0 |
4505 |
SDValue AllOnes = DAG.getAllOnesConstant(DL, LegalSVT); |
0 |
| 4506 |
SmallVector Mask(NumElts, AllOnes); |
0 |
4506 |
SmallVector Mask(NumElts, AllOnes); |
0 |
| 4507 |
for (unsigned I = 0; I != NumElts; ++I) |
0 |
4507 |
for (unsigned I = 0; I != NumElts; ++I) |
0 |
| 4508 |
if (ClearMask[I]) |
0 |
4508 |
if (ClearMask[I]) |
0 |
| 4509 |
Mask[I] = Zero; |
0 |
4509 |
Mask[I] = Zero; |
0 |
| 4510 |
return DAG.getNode(ISD::AND, DL, VT, N0, DAG.getBuildVector(VT, DL, Mask)); |
0 |
4510 |
return DAG.getNode(ISD::AND, DL, VT, N0, DAG.getBuildVector(VT, DL, Mask)); |
0 |
| 4511 |
} |
0 |
4511 |
} |
0 |
| 4512 |
} |
0 |
4512 |
} |
0 |
| 4513 |
|
--- |
4513 |
|
--- |
| 4514 |
// reassociate mul |
--- |
4514 |
// reassociate mul |
--- |
| 4515 |
if (SDValue RMUL = reassociateOps(ISD::MUL, DL, N0, N1, N->getFlags())) |
0 |
4515 |
if (SDValue RMUL = reassociateOps(ISD::MUL, DL, N0, N1, N->getFlags())) |
0 |
| 4516 |
return RMUL; |
0 |
4516 |
return RMUL; |
0 |
| 4517 |
|
--- |
4517 |
|
--- |
| 4518 |
// Fold mul(vecreduce(x), vecreduce(y)) -> vecreduce(mul(x, y)) |
--- |
4518 |
// Fold mul(vecreduce(x), vecreduce(y)) -> vecreduce(mul(x, y)) |
--- |
| 4519 |
if (SDValue SD = |
0 |
4519 |
if (SDValue SD = |
0 |
| 4520 |
reassociateReduction(ISD::VECREDUCE_MUL, ISD::MUL, DL, VT, N0, N1)) |
0 |
4520 |
reassociateReduction(ISD::VECREDUCE_MUL, ISD::MUL, DL, VT, N0, N1)) |
0 |
| 4521 |
return SD; |
0 |
4521 |
return SD; |
0 |
| 4522 |
|
--- |
4522 |
|
--- |
| 4523 |
// Simplify the operands using demanded-bits information. |
--- |
4523 |
// Simplify the operands using demanded-bits information. |
--- |
| 4524 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
4524 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
| 4525 |
return SDValue(N, 0); |
0 |
4525 |
return SDValue(N, 0); |
0 |
| 4526 |
|
--- |
4526 |
|
--- |
| 4527 |
return SDValue(); |
0 |
4527 |
return SDValue(); |
0 |
| 4528 |
} |
0 |
4528 |
} |
0 |
| 4529 |
|
--- |
4529 |
|
--- |
| 4530 |
/// Return true if divmod libcall is available. |
--- |
4530 |
/// Return true if divmod libcall is available. |
--- |
| 4531 |
static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned, |
0 |
4531 |
static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned, |
0 |
| 4532 |
const TargetLowering &TLI) { |
--- |
4532 |
const TargetLowering &TLI) { |
--- |
| 4533 |
RTLIB::Libcall LC; |
--- |
4533 |
RTLIB::Libcall LC; |
--- |
| 4534 |
EVT NodeType = Node->getValueType(0); |
0 |
4534 |
EVT NodeType = Node->getValueType(0); |
0 |
| 4535 |
if (!NodeType.isSimple()) |
0 |
4535 |
if (!NodeType.isSimple()) |
0 |
| 4536 |
return false; |
0 |
4536 |
return false; |
0 |
| 4537 |
switch (NodeType.getSimpleVT().SimpleTy) { |
0 |
4537 |
switch (NodeType.getSimpleVT().SimpleTy) { |
0 |
| 4538 |
default: return false; // No libcall for vector types. |
0 |
4538 |
default: return false; // No libcall for vector types. |
0 |
| 4539 |
case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; |
0 |
4539 |
case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; |
0 |
| 4540 |
case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; |
0 |
4540 |
case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; |
0 |
| 4541 |
case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; |
0 |
4541 |
case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; |
0 |
| 4542 |
case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; |
0 |
4542 |
case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; |
0 |
| 4543 |
case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; |
0 |
4543 |
case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; |
0 |
| 4544 |
} |
--- |
4544 |
} |
--- |
| 4545 |
|
--- |
4545 |
|
--- |
| 4546 |
return TLI.getLibcallName(LC) != nullptr; |
0 |
4546 |
return TLI.getLibcallName(LC) != nullptr; |
0 |
| 4547 |
} |
--- |
4547 |
} |
--- |
| 4548 |
|
--- |
4548 |
|
--- |
| 4549 |
/// Issue divrem if both quotient and remainder are needed. |
--- |
4549 |
/// Issue divrem if both quotient and remainder are needed. |
--- |
| 4550 |
SDValue DAGCombiner::useDivRem(SDNode *Node) { |
0 |
4550 |
SDValue DAGCombiner::useDivRem(SDNode *Node) { |
0 |
| 4551 |
if (Node->use_empty()) |
0 |
4551 |
if (Node->use_empty()) |
0 |
| 4552 |
return SDValue(); // This is a dead node, leave it alone. |
0 |
4552 |
return SDValue(); // This is a dead node, leave it alone. |
0 |
| 4553 |
|
--- |
4553 |
|
--- |
| 4554 |
unsigned Opcode = Node->getOpcode(); |
0 |
4554 |
unsigned Opcode = Node->getOpcode(); |
0 |
| 4555 |
bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM); |
0 |
4555 |
bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM); |
0 |
| 4556 |
unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; |
0 |
4556 |
unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; |
0 |
| 4557 |
|
--- |
4557 |
|
--- |
| 4558 |
// DivMod lib calls can still work on non-legal types if using lib-calls. |
--- |
4558 |
// DivMod lib calls can still work on non-legal types if using lib-calls. |
--- |
| 4559 |
EVT VT = Node->getValueType(0); |
0 |
4559 |
EVT VT = Node->getValueType(0); |
0 |
| 4560 |
if (VT.isVector() || !VT.isInteger()) |
0 |
4560 |
if (VT.isVector() || !VT.isInteger()) |
0 |
| 4561 |
return SDValue(); |
0 |
4561 |
return SDValue(); |
0 |
| 4562 |
|
--- |
4562 |
|
--- |
| 4563 |
if (!TLI.isTypeLegal(VT) && !TLI.isOperationCustom(DivRemOpc, VT)) |
0 |
4563 |
if (!TLI.isTypeLegal(VT) && !TLI.isOperationCustom(DivRemOpc, VT)) |
0 |
| 4564 |
return SDValue(); |
0 |
4564 |
return SDValue(); |
0 |
| 4565 |
|
--- |
4565 |
|
--- |
| 4566 |
// If DIVREM is going to get expanded into a libcall, |
--- |
4566 |
// If DIVREM is going to get expanded into a libcall, |
--- |
| 4567 |
// but there is no libcall available, then don't combine. |
--- |
4567 |
// but there is no libcall available, then don't combine. |
--- |
| 4568 |
if (!TLI.isOperationLegalOrCustom(DivRemOpc, VT) && |
0 |
4568 |
if (!TLI.isOperationLegalOrCustom(DivRemOpc, VT) && |
0 |
| 4569 |
!isDivRemLibcallAvailable(Node, isSigned, TLI)) |
0 |
4569 |
!isDivRemLibcallAvailable(Node, isSigned, TLI)) |
0 |
| 4570 |
return SDValue(); |
0 |
4570 |
return SDValue(); |
0 |
| 4571 |
|
--- |
4571 |
|
--- |
| 4572 |
// If div is legal, it's better to do the normal expansion |
--- |
4572 |
// If div is legal, it's better to do the normal expansion |
--- |
| 4573 |
unsigned OtherOpcode = 0; |
0 |
4573 |
unsigned OtherOpcode = 0; |
0 |
| 4574 |
if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) { |
0 |
4574 |
if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) { |
0 |
| 4575 |
OtherOpcode = isSigned ? ISD::SREM : ISD::UREM; |
0 |
4575 |
OtherOpcode = isSigned ? ISD::SREM : ISD::UREM; |
0 |
| 4576 |
if (TLI.isOperationLegalOrCustom(Opcode, VT)) |
0 |
4576 |
if (TLI.isOperationLegalOrCustom(Opcode, VT)) |
0 |
| 4577 |
return SDValue(); |
0 |
4577 |
return SDValue(); |
0 |
| 4578 |
} else { |
--- |
4578 |
} else { |
--- |
| 4579 |
OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV; |
0 |
4579 |
OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV; |
0 |
| 4580 |
if (TLI.isOperationLegalOrCustom(OtherOpcode, VT)) |
0 |
4580 |
if (TLI.isOperationLegalOrCustom(OtherOpcode, VT)) |
0 |
| 4581 |
return SDValue(); |
0 |
4581 |
return SDValue(); |
0 |
| 4582 |
} |
--- |
4582 |
} |
--- |
| 4583 |
|
--- |
4583 |
|
--- |
| 4584 |
SDValue Op0 = Node->getOperand(0); |
0 |
4584 |
SDValue Op0 = Node->getOperand(0); |
0 |
| 4585 |
SDValue Op1 = Node->getOperand(1); |
0 |
4585 |
SDValue Op1 = Node->getOperand(1); |
0 |
| 4586 |
SDValue combined; |
0 |
4586 |
SDValue combined; |
0 |
| 4587 |
for (SDNode *User : Op0->uses()) { |
0 |
4587 |
for (SDNode *User : Op0->uses()) { |
0 |
| 4588 |
if (User == Node || User->getOpcode() == ISD::DELETED_NODE || |
0 |
4588 |
if (User == Node || User->getOpcode() == ISD::DELETED_NODE || |
0 |
| 4589 |
User->use_empty()) |
0 |
4589 |
User->use_empty()) |
0 |
| 4590 |
continue; |
0 |
4590 |
continue; |
0 |
| 4591 |
// Convert the other matching node(s), too; |
--- |
4591 |
// Convert the other matching node(s), too; |
--- |
| 4592 |
// otherwise, the DIVREM may get target-legalized into something |
--- |
4592 |
// otherwise, the DIVREM may get target-legalized into something |
--- |
| 4593 |
// target-specific that we won't be able to recognize. |
--- |
4593 |
// target-specific that we won't be able to recognize. |
--- |
| 4594 |
unsigned UserOpc = User->getOpcode(); |
0 |
4594 |
unsigned UserOpc = User->getOpcode(); |
0 |
| 4595 |
if ((UserOpc == Opcode || UserOpc == OtherOpcode || UserOpc == DivRemOpc) && |
0 |
4595 |
if ((UserOpc == Opcode || UserOpc == OtherOpcode || UserOpc == DivRemOpc) && |
0 |
| 4596 |
User->getOperand(0) == Op0 && |
0 |
4596 |
User->getOperand(0) == Op0 && |
0 |
| 4597 |
User->getOperand(1) == Op1) { |
0 |
4597 |
User->getOperand(1) == Op1) { |
0 |
| 4598 |
if (!combined) { |
0 |
4598 |
if (!combined) { |
0 |
| 4599 |
if (UserOpc == OtherOpcode) { |
0 |
4599 |
if (UserOpc == OtherOpcode) { |
0 |
| 4600 |
SDVTList VTs = DAG.getVTList(VT, VT); |
0 |
4600 |
SDVTList VTs = DAG.getVTList(VT, VT); |
0 |
| 4601 |
combined = DAG.getNode(DivRemOpc, SDLoc(Node), VTs, Op0, Op1); |
0 |
4601 |
combined = DAG.getNode(DivRemOpc, SDLoc(Node), VTs, Op0, Op1); |
0 |
| 4602 |
} else if (UserOpc == DivRemOpc) { |
0 |
4602 |
} else if (UserOpc == DivRemOpc) { |
0 |
| 4603 |
combined = SDValue(User, 0); |
0 |
4603 |
combined = SDValue(User, 0); |
0 |
| 4604 |
} else { |
--- |
4604 |
} else { |
--- |
| 4605 |
assert(UserOpc == Opcode); |
0 |
4605 |
assert(UserOpc == Opcode); |
0 |
| 4606 |
continue; |
0 |
4606 |
continue; |
0 |
| 4607 |
} |
--- |
4607 |
} |
--- |
| 4608 |
} |
--- |
4608 |
} |
--- |
| 4609 |
if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV) |
0 |
4609 |
if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV) |
0 |
| 4610 |
CombineTo(User, combined); |
0 |
4610 |
CombineTo(User, combined); |
0 |
| 4611 |
else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM) |
0 |
4611 |
else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM) |
0 |
| 4612 |
CombineTo(User, combined.getValue(1)); |
0 |
4612 |
CombineTo(User, combined.getValue(1)); |
0 |
| 4613 |
} |
--- |
4613 |
} |
--- |
| 4614 |
} |
--- |
4614 |
} |
--- |
| 4615 |
return combined; |
0 |
4615 |
return combined; |
0 |
| 4616 |
} |
--- |
4616 |
} |
--- |
| 4617 |
|
--- |
4617 |
|
--- |
| 4618 |
static SDValue simplifyDivRem(SDNode *N, SelectionDAG &DAG) { |
0 |
4618 |
static SDValue simplifyDivRem(SDNode *N, SelectionDAG &DAG) { |
0 |
| 4619 |
SDValue N0 = N->getOperand(0); |
0 |
4619 |
SDValue N0 = N->getOperand(0); |
0 |
| 4620 |
SDValue N1 = N->getOperand(1); |
0 |
4620 |
SDValue N1 = N->getOperand(1); |
0 |
| 4621 |
EVT VT = N->getValueType(0); |
0 |
4621 |
EVT VT = N->getValueType(0); |
0 |
| 4622 |
SDLoc DL(N); |
0 |
4622 |
SDLoc DL(N); |
0 |
| 4623 |
|
--- |
4623 |
|
--- |
| 4624 |
unsigned Opc = N->getOpcode(); |
0 |
4624 |
unsigned Opc = N->getOpcode(); |
0 |
| 4625 |
bool IsDiv = (ISD::SDIV == Opc) || (ISD::UDIV == Opc); |
0 |
4625 |
bool IsDiv = (ISD::SDIV == Opc) || (ISD::UDIV == Opc); |
0 |
| 4626 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
4626 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
| 4627 |
|
--- |
4627 |
|
--- |
| 4628 |
// X / undef -> undef |
--- |
4628 |
// X / undef -> undef |
--- |
| 4629 |
// X % undef -> undef |
--- |
4629 |
// X % undef -> undef |
--- |
| 4630 |
// X / 0 -> undef |
--- |
4630 |
// X / 0 -> undef |
--- |
| 4631 |
// X % 0 -> undef |
--- |
4631 |
// X % 0 -> undef |
--- |
| 4632 |
// NOTE: This includes vectors where any divisor element is zero/undef. |
--- |
4632 |
// NOTE: This includes vectors where any divisor element is zero/undef. |
--- |
| 4633 |
if (DAG.isUndef(Opc, {N0, N1})) |
0 |
4633 |
if (DAG.isUndef(Opc, {N0, N1})) |
0 |
| 4634 |
return DAG.getUNDEF(VT); |
0 |
4634 |
return DAG.getUNDEF(VT); |
0 |
| 4635 |
|
--- |
4635 |
|
--- |
| 4636 |
// undef / X -> 0 |
--- |
4636 |
// undef / X -> 0 |
--- |
| 4637 |
// undef % X -> 0 |
--- |
4637 |
// undef % X -> 0 |
--- |
| 4638 |
if (N0.isUndef()) |
0 |
4638 |
if (N0.isUndef()) |
0 |
| 4639 |
return DAG.getConstant(0, DL, VT); |
0 |
4639 |
return DAG.getConstant(0, DL, VT); |
0 |
| 4640 |
|
--- |
4640 |
|
--- |
| 4641 |
// 0 / X -> 0 |
--- |
4641 |
// 0 / X -> 0 |
--- |
| 4642 |
// 0 % X -> 0 |
--- |
4642 |
// 0 % X -> 0 |
--- |
| 4643 |
ConstantSDNode *N0C = isConstOrConstSplat(N0); |
0 |
4643 |
ConstantSDNode *N0C = isConstOrConstSplat(N0); |
0 |
| 4644 |
if (N0C && N0C->isZero()) |
0 |
4644 |
if (N0C && N0C->isZero()) |
0 |
| 4645 |
return N0; |
0 |
4645 |
return N0; |
0 |
| 4646 |
|
--- |
4646 |
|
--- |
| 4647 |
// X / X -> 1 |
--- |
4647 |
// X / X -> 1 |
--- |
| 4648 |
// X % X -> 0 |
--- |
4648 |
// X % X -> 0 |
--- |
| 4649 |
if (N0 == N1) |
0 |
4649 |
if (N0 == N1) |
0 |
| 4650 |
return DAG.getConstant(IsDiv ? 1 : 0, DL, VT); |
0 |
4650 |
return DAG.getConstant(IsDiv ? 1 : 0, DL, VT); |
0 |
| 4651 |
|
--- |
4651 |
|
--- |
| 4652 |
// X / 1 -> X |
--- |
4652 |
// X / 1 -> X |
--- |
| 4653 |
// X % 1 -> 0 |
--- |
4653 |
// X % 1 -> 0 |
--- |
| 4654 |
// If this is a boolean op (single-bit element type), we can't have |
--- |
4654 |
// If this is a boolean op (single-bit element type), we can't have |
--- |
| 4655 |
// division-by-zero or remainder-by-zero, so assume the divisor is 1. |
--- |
4655 |
// division-by-zero or remainder-by-zero, so assume the divisor is 1. |
--- |
| 4656 |
// TODO: Similarly, if we're zero-extending a boolean divisor, then assume |
--- |
4656 |
// TODO: Similarly, if we're zero-extending a boolean divisor, then assume |
--- |
| 4657 |
// it's a 1. |
--- |
4657 |
// it's a 1. |
--- |
| 4658 |
if ((N1C && N1C->isOne()) || (VT.getScalarType() == MVT::i1)) |
0 |
4658 |
if ((N1C && N1C->isOne()) || (VT.getScalarType() == MVT::i1)) |
0 |
| 4659 |
return IsDiv ? N0 : DAG.getConstant(0, DL, VT); |
0 |
4659 |
return IsDiv ? N0 : DAG.getConstant(0, DL, VT); |
0 |
| 4660 |
|
--- |
4660 |
|
--- |
| 4661 |
return SDValue(); |
0 |
4661 |
return SDValue(); |
0 |
| 4662 |
} |
0 |
4662 |
} |
0 |
| 4663 |
|
--- |
4663 |
|
--- |
| 4664 |
SDValue DAGCombiner::visitSDIV(SDNode *N) { |
0 |
4664 |
SDValue DAGCombiner::visitSDIV(SDNode *N) { |
0 |
| 4665 |
SDValue N0 = N->getOperand(0); |
0 |
4665 |
SDValue N0 = N->getOperand(0); |
0 |
| 4666 |
SDValue N1 = N->getOperand(1); |
0 |
4666 |
SDValue N1 = N->getOperand(1); |
0 |
| 4667 |
EVT VT = N->getValueType(0); |
0 |
4667 |
EVT VT = N->getValueType(0); |
0 |
| 4668 |
EVT CCVT = getSetCCResultType(VT); |
0 |
4668 |
EVT CCVT = getSetCCResultType(VT); |
0 |
| 4669 |
SDLoc DL(N); |
0 |
4669 |
SDLoc DL(N); |
0 |
| 4670 |
|
--- |
4670 |
|
--- |
| 4671 |
// fold (sdiv c1, c2) -> c1/c2 |
--- |
4671 |
// fold (sdiv c1, c2) -> c1/c2 |
--- |
| 4672 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, {N0, N1})) |
0 |
4672 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, {N0, N1})) |
0 |
| 4673 |
return C; |
0 |
4673 |
return C; |
0 |
| 4674 |
|
--- |
4674 |
|
--- |
| 4675 |
// fold vector ops |
--- |
4675 |
// fold vector ops |
--- |
| 4676 |
if (VT.isVector()) |
0 |
4676 |
if (VT.isVector()) |
0 |
| 4677 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
4677 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 4678 |
return FoldedVOp; |
0 |
4678 |
return FoldedVOp; |
0 |
| 4679 |
|
--- |
4679 |
|
--- |
| 4680 |
// fold (sdiv X, -1) -> 0-X |
--- |
4680 |
// fold (sdiv X, -1) -> 0-X |
--- |
| 4681 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
4681 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
| 4682 |
if (N1C && N1C->isAllOnes()) |
0 |
4682 |
if (N1C && N1C->isAllOnes()) |
0 |
| 4683 |
return DAG.getNegative(N0, DL, VT); |
0 |
4683 |
return DAG.getNegative(N0, DL, VT); |
0 |
| 4684 |
|
--- |
4684 |
|
--- |
| 4685 |
// fold (sdiv X, MIN_SIGNED) -> select(X == MIN_SIGNED, 1, 0) |
--- |
4685 |
// fold (sdiv X, MIN_SIGNED) -> select(X == MIN_SIGNED, 1, 0) |
--- |
| 4686 |
if (N1C && N1C->isMinSignedValue()) |
0 |
4686 |
if (N1C && N1C->isMinSignedValue()) |
0 |
| 4687 |
return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ), |
0 |
4687 |
return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ), |
0 |
| 4688 |
DAG.getConstant(1, DL, VT), |
0 |
4688 |
DAG.getConstant(1, DL, VT), |
0 |
| 4689 |
DAG.getConstant(0, DL, VT)); |
0 |
4689 |
DAG.getConstant(0, DL, VT)); |
0 |
| 4690 |
|
--- |
4690 |
|
--- |
| 4691 |
if (SDValue V = simplifyDivRem(N, DAG)) |
0 |
4691 |
if (SDValue V = simplifyDivRem(N, DAG)) |
0 |
| 4692 |
return V; |
0 |
4692 |
return V; |
0 |
| 4693 |
|
--- |
4693 |
|
--- |
| 4694 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
4694 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 4695 |
return NewSel; |
0 |
4695 |
return NewSel; |
0 |
| 4696 |
|
--- |
4696 |
|
--- |
| 4697 |
// If we know the sign bits of both operands are zero, strength reduce to a |
--- |
4697 |
// If we know the sign bits of both operands are zero, strength reduce to a |
--- |
| 4698 |
// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 |
--- |
4698 |
// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 |
--- |
| 4699 |
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) |
0 |
4699 |
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) |
0 |
| 4700 |
return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1); |
0 |
4700 |
return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1); |
0 |
| 4701 |
|
--- |
4701 |
|
--- |
| 4702 |
if (SDValue V = visitSDIVLike(N0, N1, N)) { |
0 |
4702 |
if (SDValue V = visitSDIVLike(N0, N1, N)) { |
0 |
| 4703 |
// If the corresponding remainder node exists, update its users with |
--- |
4703 |
// If the corresponding remainder node exists, update its users with |
--- |
| 4704 |
// (Dividend - (Quotient * Divisor). |
--- |
4704 |
// (Dividend - (Quotient * Divisor). |
--- |
| 4705 |
if (SDNode *RemNode = DAG.getNodeIfExists(ISD::SREM, N->getVTList(), |
0 |
4705 |
if (SDNode *RemNode = DAG.getNodeIfExists(ISD::SREM, N->getVTList(), |
0 |
| 4706 |
{ N0, N1 })) { |
--- |
4706 |
{ N0, N1 })) { |
--- |
| 4707 |
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1); |
0 |
4707 |
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1); |
0 |
| 4708 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul); |
0 |
4708 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul); |
0 |
| 4709 |
AddToWorklist(Mul.getNode()); |
0 |
4709 |
AddToWorklist(Mul.getNode()); |
0 |
| 4710 |
AddToWorklist(Sub.getNode()); |
0 |
4710 |
AddToWorklist(Sub.getNode()); |
0 |
| 4711 |
CombineTo(RemNode, Sub); |
0 |
4711 |
CombineTo(RemNode, Sub); |
0 |
| 4712 |
} |
--- |
4712 |
} |
--- |
| 4713 |
return V; |
0 |
4713 |
return V; |
0 |
| 4714 |
} |
--- |
4714 |
} |
--- |
| 4715 |
|
--- |
4715 |
|
--- |
| 4716 |
// sdiv, srem -> sdivrem |
--- |
4716 |
// sdiv, srem -> sdivrem |
--- |
| 4717 |
// If the divisor is constant, then return DIVREM only if isIntDivCheap() is |
--- |
4717 |
// If the divisor is constant, then return DIVREM only if isIntDivCheap() is |
--- |
| 4718 |
// true. Otherwise, we break the simplification logic in visitREM(). |
--- |
4718 |
// true. Otherwise, we break the simplification logic in visitREM(). |
--- |
| 4719 |
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); |
0 |
4719 |
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); |
0 |
| 4720 |
if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr)) |
0 |
4720 |
if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr)) |
0 |
| 4721 |
if (SDValue DivRem = useDivRem(N)) |
0 |
4721 |
if (SDValue DivRem = useDivRem(N)) |
0 |
| 4722 |
return DivRem; |
0 |
4722 |
return DivRem; |
0 |
| 4723 |
|
--- |
4723 |
|
--- |
| 4724 |
return SDValue(); |
0 |
4724 |
return SDValue(); |
0 |
| 4725 |
} |
0 |
4725 |
} |
0 |
| 4726 |
|
--- |
4726 |
|
--- |
| 4727 |
static bool isDivisorPowerOfTwo(SDValue Divisor) { |
0 |
4727 |
static bool isDivisorPowerOfTwo(SDValue Divisor) { |
0 |
| 4728 |
// Helper for determining whether a value is a power-2 constant scalar or a |
--- |
4728 |
// Helper for determining whether a value is a power-2 constant scalar or a |
--- |
| 4729 |
// vector of such elements. |
--- |
4729 |
// vector of such elements. |
--- |
| 4730 |
auto IsPowerOfTwo = [](ConstantSDNode *C) { |
0 |
4730 |
auto IsPowerOfTwo = [](ConstantSDNode *C) { |
0 |
| 4731 |
if (C->isZero() || C->isOpaque()) |
0 |
4731 |
if (C->isZero() || C->isOpaque()) |
0 |
| 4732 |
return false; |
0 |
4732 |
return false; |
0 |
| 4733 |
if (C->getAPIntValue().isPowerOf2()) |
0 |
4733 |
if (C->getAPIntValue().isPowerOf2()) |
0 |
| 4734 |
return true; |
0 |
4734 |
return true; |
0 |
| 4735 |
if (C->getAPIntValue().isNegatedPowerOf2()) |
0 |
4735 |
if (C->getAPIntValue().isNegatedPowerOf2()) |
0 |
| 4736 |
return true; |
0 |
4736 |
return true; |
0 |
| 4737 |
return false; |
0 |
4737 |
return false; |
0 |
| 4738 |
}; |
--- |
4738 |
}; |
--- |
| 4739 |
|
--- |
4739 |
|
--- |
| 4740 |
return ISD::matchUnaryPredicate(Divisor, IsPowerOfTwo); |
0 |
4740 |
return ISD::matchUnaryPredicate(Divisor, IsPowerOfTwo); |
0 |
| 4741 |
} |
--- |
4741 |
} |
--- |
| 4742 |
|
--- |
4742 |
|
--- |
| 4743 |
SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) { |
0 |
4743 |
SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) { |
0 |
| 4744 |
SDLoc DL(N); |
0 |
4744 |
SDLoc DL(N); |
0 |
| 4745 |
EVT VT = N->getValueType(0); |
0 |
4745 |
EVT VT = N->getValueType(0); |
0 |
| 4746 |
EVT CCVT = getSetCCResultType(VT); |
0 |
4746 |
EVT CCVT = getSetCCResultType(VT); |
0 |
| 4747 |
unsigned BitWidth = VT.getScalarSizeInBits(); |
0 |
4747 |
unsigned BitWidth = VT.getScalarSizeInBits(); |
0 |
| 4748 |
|
--- |
4748 |
|
--- |
| 4749 |
// fold (sdiv X, pow2) -> simple ops after legalize |
--- |
4749 |
// fold (sdiv X, pow2) -> simple ops after legalize |
--- |
| 4750 |
// FIXME: We check for the exact bit here because the generic lowering gives |
--- |
4750 |
// FIXME: We check for the exact bit here because the generic lowering gives |
--- |
| 4751 |
// better results in that case. The target-specific lowering should learn how |
--- |
4751 |
// better results in that case. The target-specific lowering should learn how |
--- |
| 4752 |
// to handle exact sdivs efficiently. |
--- |
4752 |
// to handle exact sdivs efficiently. |
--- |
| 4753 |
if (!N->getFlags().hasExact() && isDivisorPowerOfTwo(N1)) { |
0 |
4753 |
if (!N->getFlags().hasExact() && isDivisorPowerOfTwo(N1)) { |
0 |
| 4754 |
// Target-specific implementation of sdiv x, pow2. |
--- |
4754 |
// Target-specific implementation of sdiv x, pow2. |
--- |
| 4755 |
if (SDValue Res = BuildSDIVPow2(N)) |
0 |
4755 |
if (SDValue Res = BuildSDIVPow2(N)) |
0 |
| 4756 |
return Res; |
0 |
4756 |
return Res; |
0 |
| 4757 |
|
--- |
4757 |
|
--- |
| 4758 |
// Create constants that are functions of the shift amount value. |
--- |
4758 |
// Create constants that are functions of the shift amount value. |
--- |
| 4759 |
EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType()); |
0 |
4759 |
EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType()); |
0 |
| 4760 |
SDValue Bits = DAG.getConstant(BitWidth, DL, ShiftAmtTy); |
0 |
4760 |
SDValue Bits = DAG.getConstant(BitWidth, DL, ShiftAmtTy); |
0 |
| 4761 |
SDValue C1 = DAG.getNode(ISD::CTTZ, DL, VT, N1); |
0 |
4761 |
SDValue C1 = DAG.getNode(ISD::CTTZ, DL, VT, N1); |
0 |
| 4762 |
C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy); |
0 |
4762 |
C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy); |
0 |
| 4763 |
SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1); |
0 |
4763 |
SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1); |
0 |
| 4764 |
if (!isConstantOrConstantVector(Inexact)) |
0 |
4764 |
if (!isConstantOrConstantVector(Inexact)) |
0 |
| 4765 |
return SDValue(); |
0 |
4765 |
return SDValue(); |
0 |
| 4766 |
|
--- |
4766 |
|
--- |
| 4767 |
// Splat the sign bit into the register |
--- |
4767 |
// Splat the sign bit into the register |
--- |
| 4768 |
SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0, |
0 |
4768 |
SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0, |
0 |
| 4769 |
DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy)); |
0 |
4769 |
DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy)); |
0 |
| 4770 |
AddToWorklist(Sign.getNode()); |
0 |
4770 |
AddToWorklist(Sign.getNode()); |
0 |
| 4771 |
|
--- |
4771 |
|
--- |
| 4772 |
// Add (N0 < 0) ? abs2 - 1 : 0; |
--- |
4772 |
// Add (N0 < 0) ? abs2 - 1 : 0; |
--- |
| 4773 |
SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); |
0 |
4773 |
SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); |
0 |
| 4774 |
AddToWorklist(Srl.getNode()); |
0 |
4774 |
AddToWorklist(Srl.getNode()); |
0 |
| 4775 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl); |
0 |
4775 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl); |
0 |
| 4776 |
AddToWorklist(Add.getNode()); |
0 |
4776 |
AddToWorklist(Add.getNode()); |
0 |
| 4777 |
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1); |
0 |
4777 |
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1); |
0 |
| 4778 |
AddToWorklist(Sra.getNode()); |
0 |
4778 |
AddToWorklist(Sra.getNode()); |
0 |
| 4779 |
|
--- |
4779 |
|
--- |
| 4780 |
// Special case: (sdiv X, 1) -> X |
--- |
4780 |
// Special case: (sdiv X, 1) -> X |
--- |
| 4781 |
// Special Case: (sdiv X, -1) -> 0-X |
--- |
4781 |
// Special Case: (sdiv X, -1) -> 0-X |
--- |
| 4782 |
SDValue One = DAG.getConstant(1, DL, VT); |
0 |
4782 |
SDValue One = DAG.getConstant(1, DL, VT); |
0 |
| 4783 |
SDValue AllOnes = DAG.getAllOnesConstant(DL, VT); |
0 |
4783 |
SDValue AllOnes = DAG.getAllOnesConstant(DL, VT); |
0 |
| 4784 |
SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ); |
0 |
4784 |
SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ); |
0 |
| 4785 |
SDValue IsAllOnes = DAG.getSetCC(DL, CCVT, N1, AllOnes, ISD::SETEQ); |
0 |
4785 |
SDValue IsAllOnes = DAG.getSetCC(DL, CCVT, N1, AllOnes, ISD::SETEQ); |
0 |
| 4786 |
SDValue IsOneOrAllOnes = DAG.getNode(ISD::OR, DL, CCVT, IsOne, IsAllOnes); |
0 |
4786 |
SDValue IsOneOrAllOnes = DAG.getNode(ISD::OR, DL, CCVT, IsOne, IsAllOnes); |
0 |
| 4787 |
Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra); |
0 |
4787 |
Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra); |
0 |
| 4788 |
|
--- |
4788 |
|
--- |
| 4789 |
// If dividing by a positive value, we're done. Otherwise, the result must |
--- |
4789 |
// If dividing by a positive value, we're done. Otherwise, the result must |
--- |
| 4790 |
// be negated. |
--- |
4790 |
// be negated. |
--- |
| 4791 |
SDValue Zero = DAG.getConstant(0, DL, VT); |
0 |
4791 |
SDValue Zero = DAG.getConstant(0, DL, VT); |
0 |
| 4792 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra); |
0 |
4792 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra); |
0 |
| 4793 |
|
--- |
4793 |
|
--- |
| 4794 |
// FIXME: Use SELECT_CC once we improve SELECT_CC constant-folding. |
--- |
4794 |
// FIXME: Use SELECT_CC once we improve SELECT_CC constant-folding. |
--- |
| 4795 |
SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT); |
0 |
4795 |
SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT); |
0 |
| 4796 |
SDValue Res = DAG.getSelect(DL, VT, IsNeg, Sub, Sra); |
0 |
4796 |
SDValue Res = DAG.getSelect(DL, VT, IsNeg, Sub, Sra); |
0 |
| 4797 |
return Res; |
0 |
4797 |
return Res; |
0 |
| 4798 |
} |
--- |
4798 |
} |
--- |
| 4799 |
|
--- |
4799 |
|
--- |
| 4800 |
// If integer divide is expensive and we satisfy the requirements, emit an |
--- |
4800 |
// If integer divide is expensive and we satisfy the requirements, emit an |
--- |
| 4801 |
// alternate sequence. Targets may check function attributes for size/speed |
--- |
4801 |
// alternate sequence. Targets may check function attributes for size/speed |
--- |
| 4802 |
// trade-offs. |
--- |
4802 |
// trade-offs. |
--- |
| 4803 |
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); |
0 |
4803 |
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); |
0 |
| 4804 |
if (isConstantOrConstantVector(N1) && |
0 |
4804 |
if (isConstantOrConstantVector(N1) && |
0 |
| 4805 |
!TLI.isIntDivCheap(N->getValueType(0), Attr)) |
0 |
4805 |
!TLI.isIntDivCheap(N->getValueType(0), Attr)) |
0 |
| 4806 |
if (SDValue Op = BuildSDIV(N)) |
0 |
4806 |
if (SDValue Op = BuildSDIV(N)) |
0 |
| 4807 |
return Op; |
0 |
4807 |
return Op; |
0 |
| 4808 |
|
--- |
4808 |
|
--- |
| 4809 |
return SDValue(); |
0 |
4809 |
return SDValue(); |
0 |
| 4810 |
} |
0 |
4810 |
} |
0 |
| 4811 |
|
--- |
4811 |
|
--- |
| 4812 |
SDValue DAGCombiner::visitUDIV(SDNode *N) { |
0 |
4812 |
SDValue DAGCombiner::visitUDIV(SDNode *N) { |
0 |
| 4813 |
SDValue N0 = N->getOperand(0); |
0 |
4813 |
SDValue N0 = N->getOperand(0); |
0 |
| 4814 |
SDValue N1 = N->getOperand(1); |
0 |
4814 |
SDValue N1 = N->getOperand(1); |
0 |
| 4815 |
EVT VT = N->getValueType(0); |
0 |
4815 |
EVT VT = N->getValueType(0); |
0 |
| 4816 |
EVT CCVT = getSetCCResultType(VT); |
0 |
4816 |
EVT CCVT = getSetCCResultType(VT); |
0 |
| 4817 |
SDLoc DL(N); |
0 |
4817 |
SDLoc DL(N); |
0 |
| 4818 |
|
--- |
4818 |
|
--- |
| 4819 |
// fold (udiv c1, c2) -> c1/c2 |
--- |
4819 |
// fold (udiv c1, c2) -> c1/c2 |
--- |
| 4820 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT, {N0, N1})) |
0 |
4820 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT, {N0, N1})) |
0 |
| 4821 |
return C; |
0 |
4821 |
return C; |
0 |
| 4822 |
|
--- |
4822 |
|
--- |
| 4823 |
// fold vector ops |
--- |
4823 |
// fold vector ops |
--- |
| 4824 |
if (VT.isVector()) |
0 |
4824 |
if (VT.isVector()) |
0 |
| 4825 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
4825 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 4826 |
return FoldedVOp; |
0 |
4826 |
return FoldedVOp; |
0 |
| 4827 |
|
--- |
4827 |
|
--- |
| 4828 |
// fold (udiv X, -1) -> select(X == -1, 1, 0) |
--- |
4828 |
// fold (udiv X, -1) -> select(X == -1, 1, 0) |
--- |
| 4829 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
4829 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
| 4830 |
if (N1C && N1C->isAllOnes() && CCVT.isVector() == VT.isVector()) { |
0 |
4830 |
if (N1C && N1C->isAllOnes() && CCVT.isVector() == VT.isVector()) { |
0 |
| 4831 |
return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ), |
0 |
4831 |
return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ), |
0 |
| 4832 |
DAG.getConstant(1, DL, VT), |
0 |
4832 |
DAG.getConstant(1, DL, VT), |
0 |
| 4833 |
DAG.getConstant(0, DL, VT)); |
0 |
4833 |
DAG.getConstant(0, DL, VT)); |
0 |
| 4834 |
} |
--- |
4834 |
} |
--- |
| 4835 |
|
--- |
4835 |
|
--- |
| 4836 |
if (SDValue V = simplifyDivRem(N, DAG)) |
0 |
4836 |
if (SDValue V = simplifyDivRem(N, DAG)) |
0 |
| 4837 |
return V; |
0 |
4837 |
return V; |
0 |
| 4838 |
|
--- |
4838 |
|
--- |
| 4839 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
4839 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 4840 |
return NewSel; |
0 |
4840 |
return NewSel; |
0 |
| 4841 |
|
--- |
4841 |
|
--- |
| 4842 |
if (SDValue V = visitUDIVLike(N0, N1, N)) { |
0 |
4842 |
if (SDValue V = visitUDIVLike(N0, N1, N)) { |
0 |
| 4843 |
// If the corresponding remainder node exists, update its users with |
--- |
4843 |
// If the corresponding remainder node exists, update its users with |
--- |
| 4844 |
// (Dividend - (Quotient * Divisor). |
--- |
4844 |
// (Dividend - (Quotient * Divisor). |
--- |
| 4845 |
if (SDNode *RemNode = DAG.getNodeIfExists(ISD::UREM, N->getVTList(), |
0 |
4845 |
if (SDNode *RemNode = DAG.getNodeIfExists(ISD::UREM, N->getVTList(), |
0 |
| 4846 |
{ N0, N1 })) { |
--- |
4846 |
{ N0, N1 })) { |
--- |
| 4847 |
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1); |
0 |
4847 |
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1); |
0 |
| 4848 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul); |
0 |
4848 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul); |
0 |
| 4849 |
AddToWorklist(Mul.getNode()); |
0 |
4849 |
AddToWorklist(Mul.getNode()); |
0 |
| 4850 |
AddToWorklist(Sub.getNode()); |
0 |
4850 |
AddToWorklist(Sub.getNode()); |
0 |
| 4851 |
CombineTo(RemNode, Sub); |
0 |
4851 |
CombineTo(RemNode, Sub); |
0 |
| 4852 |
} |
--- |
4852 |
} |
--- |
| 4853 |
return V; |
0 |
4853 |
return V; |
0 |
| 4854 |
} |
--- |
4854 |
} |
--- |
| 4855 |
|
--- |
4855 |
|
--- |
| 4856 |
// sdiv, srem -> sdivrem |
--- |
4856 |
// sdiv, srem -> sdivrem |
--- |
| 4857 |
// If the divisor is constant, then return DIVREM only if isIntDivCheap() is |
--- |
4857 |
// If the divisor is constant, then return DIVREM only if isIntDivCheap() is |
--- |
| 4858 |
// true. Otherwise, we break the simplification logic in visitREM(). |
--- |
4858 |
// true. Otherwise, we break the simplification logic in visitREM(). |
--- |
| 4859 |
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); |
0 |
4859 |
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); |
0 |
| 4860 |
if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr)) |
0 |
4860 |
if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr)) |
0 |
| 4861 |
if (SDValue DivRem = useDivRem(N)) |
0 |
4861 |
if (SDValue DivRem = useDivRem(N)) |
0 |
| 4862 |
return DivRem; |
0 |
4862 |
return DivRem; |
0 |
| 4863 |
|
--- |
4863 |
|
--- |
| 4864 |
return SDValue(); |
0 |
4864 |
return SDValue(); |
0 |
| 4865 |
} |
0 |
4865 |
} |
0 |
| 4866 |
|
--- |
4866 |
|
--- |
| 4867 |
SDValue DAGCombiner::visitUDIVLike(SDValue N0, SDValue N1, SDNode *N) { |
0 |
4867 |
SDValue DAGCombiner::visitUDIVLike(SDValue N0, SDValue N1, SDNode *N) { |
0 |
| 4868 |
SDLoc DL(N); |
0 |
4868 |
SDLoc DL(N); |
0 |
| 4869 |
EVT VT = N->getValueType(0); |
0 |
4869 |
EVT VT = N->getValueType(0); |
0 |
| 4870 |
|
--- |
4870 |
|
--- |
| 4871 |
// fold (udiv x, (1 << c)) -> x >>u c |
--- |
4871 |
// fold (udiv x, (1 << c)) -> x >>u c |
--- |
| 4872 |
if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) && |
0 |
4872 |
if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) && |
0 |
| 4873 |
DAG.isKnownToBeAPowerOfTwo(N1)) { |
0 |
4873 |
DAG.isKnownToBeAPowerOfTwo(N1)) { |
0 |
| 4874 |
SDValue LogBase2 = BuildLogBase2(N1, DL); |
0 |
4874 |
SDValue LogBase2 = BuildLogBase2(N1, DL); |
0 |
| 4875 |
AddToWorklist(LogBase2.getNode()); |
0 |
4875 |
AddToWorklist(LogBase2.getNode()); |
0 |
| 4876 |
|
--- |
4876 |
|
--- |
| 4877 |
EVT ShiftVT = getShiftAmountTy(N0.getValueType()); |
0 |
4877 |
EVT ShiftVT = getShiftAmountTy(N0.getValueType()); |
0 |
| 4878 |
SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT); |
0 |
4878 |
SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT); |
0 |
| 4879 |
AddToWorklist(Trunc.getNode()); |
0 |
4879 |
AddToWorklist(Trunc.getNode()); |
0 |
| 4880 |
return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc); |
0 |
4880 |
return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc); |
0 |
| 4881 |
} |
--- |
4881 |
} |
--- |
| 4882 |
|
--- |
4882 |
|
--- |
| 4883 |
// fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 |
--- |
4883 |
// fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 |
--- |
| 4884 |
if (N1.getOpcode() == ISD::SHL) { |
0 |
4884 |
if (N1.getOpcode() == ISD::SHL) { |
0 |
| 4885 |
SDValue N10 = N1.getOperand(0); |
0 |
4885 |
SDValue N10 = N1.getOperand(0); |
0 |
| 4886 |
if (isConstantOrConstantVector(N10, /*NoOpaques*/ true) && |
0 |
4886 |
if (isConstantOrConstantVector(N10, /*NoOpaques*/ true) && |
0 |
| 4887 |
DAG.isKnownToBeAPowerOfTwo(N10)) { |
0 |
4887 |
DAG.isKnownToBeAPowerOfTwo(N10)) { |
0 |
| 4888 |
SDValue LogBase2 = BuildLogBase2(N10, DL); |
0 |
4888 |
SDValue LogBase2 = BuildLogBase2(N10, DL); |
0 |
| 4889 |
AddToWorklist(LogBase2.getNode()); |
0 |
4889 |
AddToWorklist(LogBase2.getNode()); |
0 |
| 4890 |
|
--- |
4890 |
|
--- |
| 4891 |
EVT ADDVT = N1.getOperand(1).getValueType(); |
0 |
4891 |
EVT ADDVT = N1.getOperand(1).getValueType(); |
0 |
| 4892 |
SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ADDVT); |
0 |
4892 |
SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ADDVT); |
0 |
| 4893 |
AddToWorklist(Trunc.getNode()); |
0 |
4893 |
AddToWorklist(Trunc.getNode()); |
0 |
| 4894 |
SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT, N1.getOperand(1), Trunc); |
0 |
4894 |
SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT, N1.getOperand(1), Trunc); |
0 |
| 4895 |
AddToWorklist(Add.getNode()); |
0 |
4895 |
AddToWorklist(Add.getNode()); |
0 |
| 4896 |
return DAG.getNode(ISD::SRL, DL, VT, N0, Add); |
0 |
4896 |
return DAG.getNode(ISD::SRL, DL, VT, N0, Add); |
0 |
| 4897 |
} |
--- |
4897 |
} |
--- |
| 4898 |
} |
--- |
4898 |
} |
--- |
| 4899 |
|
--- |
4899 |
|
--- |
| 4900 |
// fold (udiv x, c) -> alternate |
--- |
4900 |
// fold (udiv x, c) -> alternate |
--- |
| 4901 |
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); |
0 |
4901 |
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); |
0 |
| 4902 |
if (isConstantOrConstantVector(N1) && |
0 |
4902 |
if (isConstantOrConstantVector(N1) && |
0 |
| 4903 |
!TLI.isIntDivCheap(N->getValueType(0), Attr)) |
0 |
4903 |
!TLI.isIntDivCheap(N->getValueType(0), Attr)) |
0 |
| 4904 |
if (SDValue Op = BuildUDIV(N)) |
0 |
4904 |
if (SDValue Op = BuildUDIV(N)) |
0 |
| 4905 |
return Op; |
0 |
4905 |
return Op; |
0 |
| 4906 |
|
--- |
4906 |
|
--- |
| 4907 |
return SDValue(); |
0 |
4907 |
return SDValue(); |
0 |
| 4908 |
} |
0 |
4908 |
} |
0 |
| 4909 |
|
--- |
4909 |
|
--- |
| 4910 |
SDValue DAGCombiner::buildOptimizedSREM(SDValue N0, SDValue N1, SDNode *N) { |
0 |
4910 |
SDValue DAGCombiner::buildOptimizedSREM(SDValue N0, SDValue N1, SDNode *N) { |
0 |
| 4911 |
if (!N->getFlags().hasExact() && isDivisorPowerOfTwo(N1) && |
0 |
4911 |
if (!N->getFlags().hasExact() && isDivisorPowerOfTwo(N1) && |
0 |
| 4912 |
!DAG.doesNodeExist(ISD::SDIV, N->getVTList(), {N0, N1})) { |
0 |
4912 |
!DAG.doesNodeExist(ISD::SDIV, N->getVTList(), {N0, N1})) { |
0 |
| 4913 |
// Target-specific implementation of srem x, pow2. |
--- |
4913 |
// Target-specific implementation of srem x, pow2. |
--- |
| 4914 |
if (SDValue Res = BuildSREMPow2(N)) |
0 |
4914 |
if (SDValue Res = BuildSREMPow2(N)) |
0 |
| 4915 |
return Res; |
0 |
4915 |
return Res; |
0 |
| 4916 |
} |
--- |
4916 |
} |
--- |
| 4917 |
return SDValue(); |
0 |
4917 |
return SDValue(); |
0 |
| 4918 |
} |
--- |
4918 |
} |
--- |
| 4919 |
|
--- |
4919 |
|
--- |
| 4920 |
// handles ISD::SREM and ISD::UREM |
--- |
4920 |
// handles ISD::SREM and ISD::UREM |
--- |
| 4921 |
SDValue DAGCombiner::visitREM(SDNode *N) { |
0 |
4921 |
SDValue DAGCombiner::visitREM(SDNode *N) { |
0 |
| 4922 |
unsigned Opcode = N->getOpcode(); |
0 |
4922 |
unsigned Opcode = N->getOpcode(); |
0 |
| 4923 |
SDValue N0 = N->getOperand(0); |
0 |
4923 |
SDValue N0 = N->getOperand(0); |
0 |
| 4924 |
SDValue N1 = N->getOperand(1); |
0 |
4924 |
SDValue N1 = N->getOperand(1); |
0 |
| 4925 |
EVT VT = N->getValueType(0); |
0 |
4925 |
EVT VT = N->getValueType(0); |
0 |
| 4926 |
EVT CCVT = getSetCCResultType(VT); |
0 |
4926 |
EVT CCVT = getSetCCResultType(VT); |
0 |
| 4927 |
|
--- |
4927 |
|
--- |
| 4928 |
bool isSigned = (Opcode == ISD::SREM); |
0 |
4928 |
bool isSigned = (Opcode == ISD::SREM); |
0 |
| 4929 |
SDLoc DL(N); |
0 |
4929 |
SDLoc DL(N); |
0 |
| 4930 |
|
--- |
4930 |
|
--- |
| 4931 |
// fold (rem c1, c2) -> c1%c2 |
--- |
4931 |
// fold (rem c1, c2) -> c1%c2 |
--- |
| 4932 |
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1})) |
0 |
4932 |
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1})) |
0 |
| 4933 |
return C; |
0 |
4933 |
return C; |
0 |
| 4934 |
|
--- |
4934 |
|
--- |
| 4935 |
// fold (urem X, -1) -> select(FX == -1, 0, FX) |
--- |
4935 |
// fold (urem X, -1) -> select(FX == -1, 0, FX) |
--- |
| 4936 |
// Freeze the numerator to avoid a miscompile with an undefined value. |
--- |
4936 |
// Freeze the numerator to avoid a miscompile with an undefined value. |
--- |
| 4937 |
if (!isSigned && llvm::isAllOnesOrAllOnesSplat(N1, /*AllowUndefs*/ false) && |
0 |
4937 |
if (!isSigned && llvm::isAllOnesOrAllOnesSplat(N1, /*AllowUndefs*/ false) && |
0 |
| 4938 |
CCVT.isVector() == VT.isVector()) { |
0 |
4938 |
CCVT.isVector() == VT.isVector()) { |
0 |
| 4939 |
SDValue F0 = DAG.getFreeze(N0); |
0 |
4939 |
SDValue F0 = DAG.getFreeze(N0); |
0 |
| 4940 |
SDValue EqualsNeg1 = DAG.getSetCC(DL, CCVT, F0, N1, ISD::SETEQ); |
0 |
4940 |
SDValue EqualsNeg1 = DAG.getSetCC(DL, CCVT, F0, N1, ISD::SETEQ); |
0 |
| 4941 |
return DAG.getSelect(DL, VT, EqualsNeg1, DAG.getConstant(0, DL, VT), F0); |
0 |
4941 |
return DAG.getSelect(DL, VT, EqualsNeg1, DAG.getConstant(0, DL, VT), F0); |
0 |
| 4942 |
} |
--- |
4942 |
} |
--- |
| 4943 |
|
--- |
4943 |
|
--- |
| 4944 |
if (SDValue V = simplifyDivRem(N, DAG)) |
0 |
4944 |
if (SDValue V = simplifyDivRem(N, DAG)) |
0 |
| 4945 |
return V; |
0 |
4945 |
return V; |
0 |
| 4946 |
|
--- |
4946 |
|
--- |
| 4947 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
4947 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 4948 |
return NewSel; |
0 |
4948 |
return NewSel; |
0 |
| 4949 |
|
--- |
4949 |
|
--- |
| 4950 |
if (isSigned) { |
0 |
4950 |
if (isSigned) { |
0 |
| 4951 |
// If we know the sign bits of both operands are zero, strength reduce to a |
--- |
4951 |
// If we know the sign bits of both operands are zero, strength reduce to a |
--- |
| 4952 |
// urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 |
--- |
4952 |
// urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 |
--- |
| 4953 |
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) |
0 |
4953 |
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) |
0 |
| 4954 |
return DAG.getNode(ISD::UREM, DL, VT, N0, N1); |
0 |
4954 |
return DAG.getNode(ISD::UREM, DL, VT, N0, N1); |
0 |
| 4955 |
} else { |
--- |
4955 |
} else { |
--- |
| 4956 |
if (DAG.isKnownToBeAPowerOfTwo(N1)) { |
0 |
4956 |
if (DAG.isKnownToBeAPowerOfTwo(N1)) { |
0 |
| 4957 |
// fold (urem x, pow2) -> (and x, pow2-1) |
--- |
4957 |
// fold (urem x, pow2) -> (and x, pow2-1) |
--- |
| 4958 |
SDValue NegOne = DAG.getAllOnesConstant(DL, VT); |
0 |
4958 |
SDValue NegOne = DAG.getAllOnesConstant(DL, VT); |
0 |
| 4959 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne); |
0 |
4959 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne); |
0 |
| 4960 |
AddToWorklist(Add.getNode()); |
0 |
4960 |
AddToWorklist(Add.getNode()); |
0 |
| 4961 |
return DAG.getNode(ISD::AND, DL, VT, N0, Add); |
0 |
4961 |
return DAG.getNode(ISD::AND, DL, VT, N0, Add); |
0 |
| 4962 |
} |
--- |
4962 |
} |
--- |
| 4963 |
// fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) |
--- |
4963 |
// fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) |
--- |
| 4964 |
// fold (urem x, (lshr pow2, y)) -> (and x, (add (lshr pow2, y), -1)) |
--- |
4964 |
// fold (urem x, (lshr pow2, y)) -> (and x, (add (lshr pow2, y), -1)) |
--- |
| 4965 |
// TODO: We should sink the following into isKnownToBePowerOfTwo |
--- |
4965 |
// TODO: We should sink the following into isKnownToBePowerOfTwo |
--- |
| 4966 |
// using a OrZero parameter analogous to our handling in ValueTracking. |
--- |
4966 |
// using a OrZero parameter analogous to our handling in ValueTracking. |
--- |
| 4967 |
if ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) && |
0 |
4967 |
if ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) && |
0 |
| 4968 |
DAG.isKnownToBeAPowerOfTwo(N1.getOperand(0))) { |
0 |
4968 |
DAG.isKnownToBeAPowerOfTwo(N1.getOperand(0))) { |
0 |
| 4969 |
SDValue NegOne = DAG.getAllOnesConstant(DL, VT); |
0 |
4969 |
SDValue NegOne = DAG.getAllOnesConstant(DL, VT); |
0 |
| 4970 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne); |
0 |
4970 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne); |
0 |
| 4971 |
AddToWorklist(Add.getNode()); |
0 |
4971 |
AddToWorklist(Add.getNode()); |
0 |
| 4972 |
return DAG.getNode(ISD::AND, DL, VT, N0, Add); |
0 |
4972 |
return DAG.getNode(ISD::AND, DL, VT, N0, Add); |
0 |
| 4973 |
} |
--- |
4973 |
} |
--- |
| 4974 |
} |
--- |
4974 |
} |
--- |
| 4975 |
|
--- |
4975 |
|
--- |
| 4976 |
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); |
0 |
4976 |
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); |
0 |
| 4977 |
|
--- |
4977 |
|
--- |
| 4978 |
// If X/C can be simplified by the division-by-constant logic, lower |
--- |
4978 |
// If X/C can be simplified by the division-by-constant logic, lower |
--- |
| 4979 |
// X%C to the equivalent of X-X/C*C. |
--- |
4979 |
// X%C to the equivalent of X-X/C*C. |
--- |
| 4980 |
// Reuse the SDIVLike/UDIVLike combines - to avoid mangling nodes, the |
--- |
4980 |
// Reuse the SDIVLike/UDIVLike combines - to avoid mangling nodes, the |
--- |
| 4981 |
// speculative DIV must not cause a DIVREM conversion. We guard against this |
--- |
4981 |
// speculative DIV must not cause a DIVREM conversion. We guard against this |
--- |
| 4982 |
// by skipping the simplification if isIntDivCheap(). When div is not cheap, |
--- |
4982 |
// by skipping the simplification if isIntDivCheap(). When div is not cheap, |
--- |
| 4983 |
// combine will not return a DIVREM. Regardless, checking cheapness here |
--- |
4983 |
// combine will not return a DIVREM. Regardless, checking cheapness here |
--- |
| 4984 |
// makes sense since the simplification results in fatter code. |
--- |
4984 |
// makes sense since the simplification results in fatter code. |
--- |
| 4985 |
if (DAG.isKnownNeverZero(N1) && !TLI.isIntDivCheap(VT, Attr)) { |
0 |
4985 |
if (DAG.isKnownNeverZero(N1) && !TLI.isIntDivCheap(VT, Attr)) { |
0 |
| 4986 |
if (isSigned) { |
0 |
4986 |
if (isSigned) { |
0 |
| 4987 |
// check if we can build faster implementation for srem |
--- |
4987 |
// check if we can build faster implementation for srem |
--- |
| 4988 |
if (SDValue OptimizedRem = buildOptimizedSREM(N0, N1, N)) |
0 |
4988 |
if (SDValue OptimizedRem = buildOptimizedSREM(N0, N1, N)) |
0 |
| 4989 |
return OptimizedRem; |
0 |
4989 |
return OptimizedRem; |
0 |
| 4990 |
} |
--- |
4990 |
} |
--- |
| 4991 |
|
--- |
4991 |
|
--- |
| 4992 |
SDValue OptimizedDiv = |
--- |
4992 |
SDValue OptimizedDiv = |
--- |
| 4993 |
isSigned ? visitSDIVLike(N0, N1, N) : visitUDIVLike(N0, N1, N); |
0 |
4993 |
isSigned ? visitSDIVLike(N0, N1, N) : visitUDIVLike(N0, N1, N); |
0 |
| 4994 |
if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != N) { |
0 |
4994 |
if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != N) { |
0 |
| 4995 |
// If the equivalent Div node also exists, update its users. |
--- |
4995 |
// If the equivalent Div node also exists, update its users. |
--- |
| 4996 |
unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV; |
0 |
4996 |
unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV; |
0 |
| 4997 |
if (SDNode *DivNode = DAG.getNodeIfExists(DivOpcode, N->getVTList(), |
0 |
4997 |
if (SDNode *DivNode = DAG.getNodeIfExists(DivOpcode, N->getVTList(), |
0 |
| 4998 |
{ N0, N1 })) |
--- |
4998 |
{ N0, N1 })) |
--- |
| 4999 |
CombineTo(DivNode, OptimizedDiv); |
0 |
4999 |
CombineTo(DivNode, OptimizedDiv); |
0 |
| 5000 |
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, OptimizedDiv, N1); |
0 |
5000 |
SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, OptimizedDiv, N1); |
0 |
| 5001 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul); |
0 |
5001 |
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul); |
0 |
| 5002 |
AddToWorklist(OptimizedDiv.getNode()); |
0 |
5002 |
AddToWorklist(OptimizedDiv.getNode()); |
0 |
| 5003 |
AddToWorklist(Mul.getNode()); |
0 |
5003 |
AddToWorklist(Mul.getNode()); |
0 |
| 5004 |
return Sub; |
0 |
5004 |
return Sub; |
0 |
| 5005 |
} |
--- |
5005 |
} |
--- |
| 5006 |
} |
--- |
5006 |
} |
--- |
| 5007 |
|
--- |
5007 |
|
--- |
| 5008 |
// sdiv, srem -> sdivrem |
--- |
5008 |
// sdiv, srem -> sdivrem |
--- |
| 5009 |
if (SDValue DivRem = useDivRem(N)) |
0 |
5009 |
if (SDValue DivRem = useDivRem(N)) |
0 |
| 5010 |
return DivRem.getValue(1); |
0 |
5010 |
return DivRem.getValue(1); |
0 |
| 5011 |
|
--- |
5011 |
|
--- |
| 5012 |
return SDValue(); |
0 |
5012 |
return SDValue(); |
0 |
| 5013 |
} |
0 |
5013 |
} |
0 |
| 5014 |
|
--- |
5014 |
|
--- |
| 5015 |
SDValue DAGCombiner::visitMULHS(SDNode *N) { |
0 |
5015 |
SDValue DAGCombiner::visitMULHS(SDNode *N) { |
0 |
| 5016 |
SDValue N0 = N->getOperand(0); |
0 |
5016 |
SDValue N0 = N->getOperand(0); |
0 |
| 5017 |
SDValue N1 = N->getOperand(1); |
0 |
5017 |
SDValue N1 = N->getOperand(1); |
0 |
| 5018 |
EVT VT = N->getValueType(0); |
0 |
5018 |
EVT VT = N->getValueType(0); |
0 |
| 5019 |
SDLoc DL(N); |
0 |
5019 |
SDLoc DL(N); |
0 |
| 5020 |
|
--- |
5020 |
|
--- |
| 5021 |
// fold (mulhs c1, c2) |
--- |
5021 |
// fold (mulhs c1, c2) |
--- |
| 5022 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHS, DL, VT, {N0, N1})) |
0 |
5022 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHS, DL, VT, {N0, N1})) |
0 |
| 5023 |
return C; |
0 |
5023 |
return C; |
0 |
| 5024 |
|
--- |
5024 |
|
--- |
| 5025 |
// canonicalize constant to RHS. |
--- |
5025 |
// canonicalize constant to RHS. |
--- |
| 5026 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
5026 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 5027 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
5027 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 5028 |
return DAG.getNode(ISD::MULHS, DL, N->getVTList(), N1, N0); |
0 |
5028 |
return DAG.getNode(ISD::MULHS, DL, N->getVTList(), N1, N0); |
0 |
| 5029 |
|
--- |
5029 |
|
--- |
| 5030 |
if (VT.isVector()) { |
0 |
5030 |
if (VT.isVector()) { |
0 |
| 5031 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
5031 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 5032 |
return FoldedVOp; |
0 |
5032 |
return FoldedVOp; |
0 |
| 5033 |
|
--- |
5033 |
|
--- |
| 5034 |
// fold (mulhs x, 0) -> 0 |
--- |
5034 |
// fold (mulhs x, 0) -> 0 |
--- |
| 5035 |
// do not return N1, because undef node may exist. |
--- |
5035 |
// do not return N1, because undef node may exist. |
--- |
| 5036 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
5036 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
| 5037 |
return DAG.getConstant(0, DL, VT); |
0 |
5037 |
return DAG.getConstant(0, DL, VT); |
0 |
| 5038 |
} |
--- |
5038 |
} |
--- |
| 5039 |
|
--- |
5039 |
|
--- |
| 5040 |
// fold (mulhs x, 0) -> 0 |
--- |
5040 |
// fold (mulhs x, 0) -> 0 |
--- |
| 5041 |
if (isNullConstant(N1)) |
0 |
5041 |
if (isNullConstant(N1)) |
0 |
| 5042 |
return N1; |
0 |
5042 |
return N1; |
0 |
| 5043 |
|
--- |
5043 |
|
--- |
| 5044 |
// fold (mulhs x, 1) -> (sra x, size(x)-1) |
--- |
5044 |
// fold (mulhs x, 1) -> (sra x, size(x)-1) |
--- |
| 5045 |
if (isOneConstant(N1)) |
0 |
5045 |
if (isOneConstant(N1)) |
0 |
| 5046 |
return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0, |
0 |
5046 |
return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0, |
0 |
| 5047 |
DAG.getConstant(N0.getScalarValueSizeInBits() - 1, DL, |
0 |
5047 |
DAG.getConstant(N0.getScalarValueSizeInBits() - 1, DL, |
0 |
| 5048 |
getShiftAmountTy(N0.getValueType()))); |
0 |
5048 |
getShiftAmountTy(N0.getValueType()))); |
0 |
| 5049 |
|
--- |
5049 |
|
--- |
| 5050 |
// fold (mulhs x, undef) -> 0 |
--- |
5050 |
// fold (mulhs x, undef) -> 0 |
--- |
| 5051 |
if (N0.isUndef() || N1.isUndef()) |
0 |
5051 |
if (N0.isUndef() || N1.isUndef()) |
0 |
| 5052 |
return DAG.getConstant(0, DL, VT); |
0 |
5052 |
return DAG.getConstant(0, DL, VT); |
0 |
| 5053 |
|
--- |
5053 |
|
--- |
| 5054 |
// If the type twice as wide is legal, transform the mulhs to a wider multiply |
--- |
5054 |
// If the type twice as wide is legal, transform the mulhs to a wider multiply |
--- |
| 5055 |
// plus a shift. |
--- |
5055 |
// plus a shift. |
--- |
| 5056 |
if (!TLI.isOperationLegalOrCustom(ISD::MULHS, VT) && VT.isSimple() && |
0 |
5056 |
if (!TLI.isOperationLegalOrCustom(ISD::MULHS, VT) && VT.isSimple() && |
0 |
| 5057 |
!VT.isVector()) { |
0 |
5057 |
!VT.isVector()) { |
0 |
| 5058 |
MVT Simple = VT.getSimpleVT(); |
0 |
5058 |
MVT Simple = VT.getSimpleVT(); |
0 |
| 5059 |
unsigned SimpleSize = Simple.getSizeInBits(); |
0 |
5059 |
unsigned SimpleSize = Simple.getSizeInBits(); |
0 |
| 5060 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); |
0 |
5060 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); |
0 |
| 5061 |
if (TLI.isOperationLegal(ISD::MUL, NewVT)) { |
0 |
5061 |
if (TLI.isOperationLegal(ISD::MUL, NewVT)) { |
0 |
| 5062 |
N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); |
0 |
5062 |
N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); |
0 |
| 5063 |
N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); |
0 |
5063 |
N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); |
0 |
| 5064 |
N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); |
0 |
5064 |
N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); |
0 |
| 5065 |
N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, |
0 |
5065 |
N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, |
0 |
| 5066 |
DAG.getConstant(SimpleSize, DL, |
0 |
5066 |
DAG.getConstant(SimpleSize, DL, |
0 |
| 5067 |
getShiftAmountTy(N1.getValueType()))); |
--- |
5067 |
getShiftAmountTy(N1.getValueType()))); |
--- |
| 5068 |
return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); |
0 |
5068 |
return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); |
0 |
| 5069 |
} |
--- |
5069 |
} |
--- |
| 5070 |
} |
--- |
5070 |
} |
--- |
| 5071 |
|
--- |
5071 |
|
--- |
| 5072 |
return SDValue(); |
0 |
5072 |
return SDValue(); |
0 |
| 5073 |
} |
0 |
5073 |
} |
0 |
| 5074 |
|
--- |
5074 |
|
--- |
| 5075 |
SDValue DAGCombiner::visitMULHU(SDNode *N) { |
0 |
5075 |
SDValue DAGCombiner::visitMULHU(SDNode *N) { |
0 |
| 5076 |
SDValue N0 = N->getOperand(0); |
0 |
5076 |
SDValue N0 = N->getOperand(0); |
0 |
| 5077 |
SDValue N1 = N->getOperand(1); |
0 |
5077 |
SDValue N1 = N->getOperand(1); |
0 |
| 5078 |
EVT VT = N->getValueType(0); |
0 |
5078 |
EVT VT = N->getValueType(0); |
0 |
| 5079 |
SDLoc DL(N); |
0 |
5079 |
SDLoc DL(N); |
0 |
| 5080 |
|
--- |
5080 |
|
--- |
| 5081 |
// fold (mulhu c1, c2) |
--- |
5081 |
// fold (mulhu c1, c2) |
--- |
| 5082 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHU, DL, VT, {N0, N1})) |
0 |
5082 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHU, DL, VT, {N0, N1})) |
0 |
| 5083 |
return C; |
0 |
5083 |
return C; |
0 |
| 5084 |
|
--- |
5084 |
|
--- |
| 5085 |
// canonicalize constant to RHS. |
--- |
5085 |
// canonicalize constant to RHS. |
--- |
| 5086 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
5086 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 5087 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
5087 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 5088 |
return DAG.getNode(ISD::MULHU, DL, N->getVTList(), N1, N0); |
0 |
5088 |
return DAG.getNode(ISD::MULHU, DL, N->getVTList(), N1, N0); |
0 |
| 5089 |
|
--- |
5089 |
|
--- |
| 5090 |
if (VT.isVector()) { |
0 |
5090 |
if (VT.isVector()) { |
0 |
| 5091 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
5091 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 5092 |
return FoldedVOp; |
0 |
5092 |
return FoldedVOp; |
0 |
| 5093 |
|
--- |
5093 |
|
--- |
| 5094 |
// fold (mulhu x, 0) -> 0 |
--- |
5094 |
// fold (mulhu x, 0) -> 0 |
--- |
| 5095 |
// do not return N1, because undef node may exist. |
--- |
5095 |
// do not return N1, because undef node may exist. |
--- |
| 5096 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
5096 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
| 5097 |
return DAG.getConstant(0, DL, VT); |
0 |
5097 |
return DAG.getConstant(0, DL, VT); |
0 |
| 5098 |
} |
--- |
5098 |
} |
--- |
| 5099 |
|
--- |
5099 |
|
--- |
| 5100 |
// fold (mulhu x, 0) -> 0 |
--- |
5100 |
// fold (mulhu x, 0) -> 0 |
--- |
| 5101 |
if (isNullConstant(N1)) |
0 |
5101 |
if (isNullConstant(N1)) |
0 |
| 5102 |
return N1; |
0 |
5102 |
return N1; |
0 |
| 5103 |
|
--- |
5103 |
|
--- |
| 5104 |
// fold (mulhu x, 1) -> 0 |
--- |
5104 |
// fold (mulhu x, 1) -> 0 |
--- |
| 5105 |
if (isOneConstant(N1)) |
0 |
5105 |
if (isOneConstant(N1)) |
0 |
| 5106 |
return DAG.getConstant(0, DL, N0.getValueType()); |
0 |
5106 |
return DAG.getConstant(0, DL, N0.getValueType()); |
0 |
| 5107 |
|
--- |
5107 |
|
--- |
| 5108 |
// fold (mulhu x, undef) -> 0 |
--- |
5108 |
// fold (mulhu x, undef) -> 0 |
--- |
| 5109 |
if (N0.isUndef() || N1.isUndef()) |
0 |
5109 |
if (N0.isUndef() || N1.isUndef()) |
0 |
| 5110 |
return DAG.getConstant(0, DL, VT); |
0 |
5110 |
return DAG.getConstant(0, DL, VT); |
0 |
| 5111 |
|
--- |
5111 |
|
--- |
| 5112 |
// fold (mulhu x, (1 << c)) -> x >> (bitwidth - c) |
--- |
5112 |
// fold (mulhu x, (1 << c)) -> x >> (bitwidth - c) |
--- |
| 5113 |
if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) && |
0 |
5113 |
if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) && |
0 |
| 5114 |
DAG.isKnownToBeAPowerOfTwo(N1) && hasOperation(ISD::SRL, VT)) { |
0 |
5114 |
DAG.isKnownToBeAPowerOfTwo(N1) && hasOperation(ISD::SRL, VT)) { |
0 |
| 5115 |
unsigned NumEltBits = VT.getScalarSizeInBits(); |
0 |
5115 |
unsigned NumEltBits = VT.getScalarSizeInBits(); |
0 |
| 5116 |
SDValue LogBase2 = BuildLogBase2(N1, DL); |
0 |
5116 |
SDValue LogBase2 = BuildLogBase2(N1, DL); |
0 |
| 5117 |
SDValue SRLAmt = DAG.getNode( |
0 |
5117 |
SDValue SRLAmt = DAG.getNode( |
0 |
| 5118 |
ISD::SUB, DL, VT, DAG.getConstant(NumEltBits, DL, VT), LogBase2); |
0 |
5118 |
ISD::SUB, DL, VT, DAG.getConstant(NumEltBits, DL, VT), LogBase2); |
0 |
| 5119 |
EVT ShiftVT = getShiftAmountTy(N0.getValueType()); |
0 |
5119 |
EVT ShiftVT = getShiftAmountTy(N0.getValueType()); |
0 |
| 5120 |
SDValue Trunc = DAG.getZExtOrTrunc(SRLAmt, DL, ShiftVT); |
0 |
5120 |
SDValue Trunc = DAG.getZExtOrTrunc(SRLAmt, DL, ShiftVT); |
0 |
| 5121 |
return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc); |
0 |
5121 |
return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc); |
0 |
| 5122 |
} |
--- |
5122 |
} |
--- |
| 5123 |
|
--- |
5123 |
|
--- |
| 5124 |
// If the type twice as wide is legal, transform the mulhu to a wider multiply |
--- |
5124 |
// If the type twice as wide is legal, transform the mulhu to a wider multiply |
--- |
| 5125 |
// plus a shift. |
--- |
5125 |
// plus a shift. |
--- |
| 5126 |
if (!TLI.isOperationLegalOrCustom(ISD::MULHU, VT) && VT.isSimple() && |
0 |
5126 |
if (!TLI.isOperationLegalOrCustom(ISD::MULHU, VT) && VT.isSimple() && |
0 |
| 5127 |
!VT.isVector()) { |
0 |
5127 |
!VT.isVector()) { |
0 |
| 5128 |
MVT Simple = VT.getSimpleVT(); |
0 |
5128 |
MVT Simple = VT.getSimpleVT(); |
0 |
| 5129 |
unsigned SimpleSize = Simple.getSizeInBits(); |
0 |
5129 |
unsigned SimpleSize = Simple.getSizeInBits(); |
0 |
| 5130 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); |
0 |
5130 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); |
0 |
| 5131 |
if (TLI.isOperationLegal(ISD::MUL, NewVT)) { |
0 |
5131 |
if (TLI.isOperationLegal(ISD::MUL, NewVT)) { |
0 |
| 5132 |
N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); |
0 |
5132 |
N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); |
0 |
| 5133 |
N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); |
0 |
5133 |
N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); |
0 |
| 5134 |
N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); |
0 |
5134 |
N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); |
0 |
| 5135 |
N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, |
0 |
5135 |
N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, |
0 |
| 5136 |
DAG.getConstant(SimpleSize, DL, |
0 |
5136 |
DAG.getConstant(SimpleSize, DL, |
0 |
| 5137 |
getShiftAmountTy(N1.getValueType()))); |
--- |
5137 |
getShiftAmountTy(N1.getValueType()))); |
--- |
| 5138 |
return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); |
0 |
5138 |
return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); |
0 |
| 5139 |
} |
--- |
5139 |
} |
--- |
| 5140 |
} |
--- |
5140 |
} |
--- |
| 5141 |
|
--- |
5141 |
|
--- |
| 5142 |
// Simplify the operands using demanded-bits information. |
--- |
5142 |
// Simplify the operands using demanded-bits information. |
--- |
| 5143 |
// We don't have demanded bits support for MULHU so this just enables constant |
--- |
5143 |
// We don't have demanded bits support for MULHU so this just enables constant |
--- |
| 5144 |
// folding based on known bits. |
--- |
5144 |
// folding based on known bits. |
--- |
| 5145 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
5145 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
| 5146 |
return SDValue(N, 0); |
0 |
5146 |
return SDValue(N, 0); |
0 |
| 5147 |
|
--- |
5147 |
|
--- |
| 5148 |
return SDValue(); |
0 |
5148 |
return SDValue(); |
0 |
| 5149 |
} |
0 |
5149 |
} |
0 |
| 5150 |
|
--- |
5150 |
|
--- |
| 5151 |
SDValue DAGCombiner::visitAVG(SDNode *N) { |
0 |
5151 |
SDValue DAGCombiner::visitAVG(SDNode *N) { |
0 |
| 5152 |
unsigned Opcode = N->getOpcode(); |
0 |
5152 |
unsigned Opcode = N->getOpcode(); |
0 |
| 5153 |
SDValue N0 = N->getOperand(0); |
0 |
5153 |
SDValue N0 = N->getOperand(0); |
0 |
| 5154 |
SDValue N1 = N->getOperand(1); |
0 |
5154 |
SDValue N1 = N->getOperand(1); |
0 |
| 5155 |
EVT VT = N->getValueType(0); |
0 |
5155 |
EVT VT = N->getValueType(0); |
0 |
| 5156 |
SDLoc DL(N); |
0 |
5156 |
SDLoc DL(N); |
0 |
| 5157 |
|
--- |
5157 |
|
--- |
| 5158 |
// fold (avg c1, c2) |
--- |
5158 |
// fold (avg c1, c2) |
--- |
| 5159 |
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1})) |
0 |
5159 |
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1})) |
0 |
| 5160 |
return C; |
0 |
5160 |
return C; |
0 |
| 5161 |
|
--- |
5161 |
|
--- |
| 5162 |
// canonicalize constant to RHS. |
--- |
5162 |
// canonicalize constant to RHS. |
--- |
| 5163 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
5163 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 5164 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
5164 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 5165 |
return DAG.getNode(Opcode, DL, N->getVTList(), N1, N0); |
0 |
5165 |
return DAG.getNode(Opcode, DL, N->getVTList(), N1, N0); |
0 |
| 5166 |
|
--- |
5166 |
|
--- |
| 5167 |
if (VT.isVector()) { |
0 |
5167 |
if (VT.isVector()) { |
0 |
| 5168 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
5168 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 5169 |
return FoldedVOp; |
0 |
5169 |
return FoldedVOp; |
0 |
| 5170 |
|
--- |
5170 |
|
--- |
| 5171 |
// fold (avgfloor x, 0) -> x >> 1 |
--- |
5171 |
// fold (avgfloor x, 0) -> x >> 1 |
--- |
| 5172 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) { |
0 |
5172 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) { |
0 |
| 5173 |
if (Opcode == ISD::AVGFLOORS) |
0 |
5173 |
if (Opcode == ISD::AVGFLOORS) |
0 |
| 5174 |
return DAG.getNode(ISD::SRA, DL, VT, N0, DAG.getConstant(1, DL, VT)); |
0 |
5174 |
return DAG.getNode(ISD::SRA, DL, VT, N0, DAG.getConstant(1, DL, VT)); |
0 |
| 5175 |
if (Opcode == ISD::AVGFLOORU) |
0 |
5175 |
if (Opcode == ISD::AVGFLOORU) |
0 |
| 5176 |
return DAG.getNode(ISD::SRL, DL, VT, N0, DAG.getConstant(1, DL, VT)); |
0 |
5176 |
return DAG.getNode(ISD::SRL, DL, VT, N0, DAG.getConstant(1, DL, VT)); |
0 |
| 5177 |
} |
--- |
5177 |
} |
--- |
| 5178 |
} |
--- |
5178 |
} |
--- |
| 5179 |
|
--- |
5179 |
|
--- |
| 5180 |
// fold (avg x, undef) -> x |
--- |
5180 |
// fold (avg x, undef) -> x |
--- |
| 5181 |
if (N0.isUndef()) |
0 |
5181 |
if (N0.isUndef()) |
0 |
| 5182 |
return N1; |
0 |
5182 |
return N1; |
0 |
| 5183 |
if (N1.isUndef()) |
0 |
5183 |
if (N1.isUndef()) |
0 |
| 5184 |
return N0; |
0 |
5184 |
return N0; |
0 |
| 5185 |
|
--- |
5185 |
|
--- |
| 5186 |
// Fold (avg x, x) --> x |
--- |
5186 |
// Fold (avg x, x) --> x |
--- |
| 5187 |
if (N0 == N1 && Level >= AfterLegalizeTypes) |
0 |
5187 |
if (N0 == N1 && Level >= AfterLegalizeTypes) |
0 |
| 5188 |
return N0; |
0 |
5188 |
return N0; |
0 |
| 5189 |
|
--- |
5189 |
|
--- |
| 5190 |
// TODO If we use avg for scalars anywhere, we can add (avgfl x, 0) -> x >> 1 |
--- |
5190 |
// TODO If we use avg for scalars anywhere, we can add (avgfl x, 0) -> x >> 1 |
--- |
| 5191 |
|
--- |
5191 |
|
--- |
| 5192 |
return SDValue(); |
0 |
5192 |
return SDValue(); |
0 |
| 5193 |
} |
0 |
5193 |
} |
0 |
| 5194 |
|
--- |
5194 |
|
--- |
| 5195 |
SDValue DAGCombiner::visitABD(SDNode *N) { |
0 |
5195 |
SDValue DAGCombiner::visitABD(SDNode *N) { |
0 |
| 5196 |
unsigned Opcode = N->getOpcode(); |
0 |
5196 |
unsigned Opcode = N->getOpcode(); |
0 |
| 5197 |
SDValue N0 = N->getOperand(0); |
0 |
5197 |
SDValue N0 = N->getOperand(0); |
0 |
| 5198 |
SDValue N1 = N->getOperand(1); |
0 |
5198 |
SDValue N1 = N->getOperand(1); |
0 |
| 5199 |
EVT VT = N->getValueType(0); |
0 |
5199 |
EVT VT = N->getValueType(0); |
0 |
| 5200 |
SDLoc DL(N); |
0 |
5200 |
SDLoc DL(N); |
0 |
| 5201 |
|
--- |
5201 |
|
--- |
| 5202 |
// fold (abd c1, c2) |
--- |
5202 |
// fold (abd c1, c2) |
--- |
| 5203 |
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1})) |
0 |
5203 |
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1})) |
0 |
| 5204 |
return C; |
0 |
5204 |
return C; |
0 |
| 5205 |
|
--- |
5205 |
|
--- |
| 5206 |
// canonicalize constant to RHS. |
--- |
5206 |
// canonicalize constant to RHS. |
--- |
| 5207 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
5207 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 5208 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
5208 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 5209 |
return DAG.getNode(Opcode, DL, N->getVTList(), N1, N0); |
0 |
5209 |
return DAG.getNode(Opcode, DL, N->getVTList(), N1, N0); |
0 |
| 5210 |
|
--- |
5210 |
|
--- |
| 5211 |
if (VT.isVector()) { |
0 |
5211 |
if (VT.isVector()) { |
0 |
| 5212 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
5212 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 5213 |
return FoldedVOp; |
0 |
5213 |
return FoldedVOp; |
0 |
| 5214 |
|
--- |
5214 |
|
--- |
| 5215 |
// fold (abds x, 0) -> abs x |
--- |
5215 |
// fold (abds x, 0) -> abs x |
--- |
| 5216 |
// fold (abdu x, 0) -> x |
--- |
5216 |
// fold (abdu x, 0) -> x |
--- |
| 5217 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) { |
0 |
5217 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) { |
0 |
| 5218 |
if (Opcode == ISD::ABDS) |
0 |
5218 |
if (Opcode == ISD::ABDS) |
0 |
| 5219 |
return DAG.getNode(ISD::ABS, DL, VT, N0); |
0 |
5219 |
return DAG.getNode(ISD::ABS, DL, VT, N0); |
0 |
| 5220 |
if (Opcode == ISD::ABDU) |
0 |
5220 |
if (Opcode == ISD::ABDU) |
0 |
| 5221 |
return N0; |
0 |
5221 |
return N0; |
0 |
| 5222 |
} |
--- |
5222 |
} |
--- |
| 5223 |
} |
--- |
5223 |
} |
--- |
| 5224 |
|
--- |
5224 |
|
--- |
| 5225 |
// fold (abd x, undef) -> 0 |
--- |
5225 |
// fold (abd x, undef) -> 0 |
--- |
| 5226 |
if (N0.isUndef() || N1.isUndef()) |
0 |
5226 |
if (N0.isUndef() || N1.isUndef()) |
0 |
| 5227 |
return DAG.getConstant(0, DL, VT); |
0 |
5227 |
return DAG.getConstant(0, DL, VT); |
0 |
| 5228 |
|
--- |
5228 |
|
--- |
| 5229 |
// fold (abds x, y) -> (abdu x, y) iff both args are known positive |
--- |
5229 |
// fold (abds x, y) -> (abdu x, y) iff both args are known positive |
--- |
| 5230 |
if (Opcode == ISD::ABDS && hasOperation(ISD::ABDU, VT) && |
0 |
5230 |
if (Opcode == ISD::ABDS && hasOperation(ISD::ABDU, VT) && |
0 |
| 5231 |
DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1)) |
0 |
5231 |
DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1)) |
0 |
| 5232 |
return DAG.getNode(ISD::ABDU, DL, VT, N1, N0); |
0 |
5232 |
return DAG.getNode(ISD::ABDU, DL, VT, N1, N0); |
0 |
| 5233 |
|
--- |
5233 |
|
--- |
| 5234 |
return SDValue(); |
0 |
5234 |
return SDValue(); |
0 |
| 5235 |
} |
0 |
5235 |
} |
0 |
| 5236 |
|
--- |
5236 |
|
--- |
| 5237 |
/// Perform optimizations common to nodes that compute two values. LoOp and HiOp |
--- |
5237 |
/// Perform optimizations common to nodes that compute two values. LoOp and HiOp |
--- |
| 5238 |
/// give the opcodes for the two computations that are being performed. Return |
--- |
5238 |
/// give the opcodes for the two computations that are being performed. Return |
--- |
| 5239 |
/// true if a simplification was made. |
--- |
5239 |
/// true if a simplification was made. |
--- |
| 5240 |
SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, |
0 |
5240 |
SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, |
0 |
| 5241 |
unsigned HiOp) { |
--- |
5241 |
unsigned HiOp) { |
--- |
| 5242 |
// If the high half is not needed, just compute the low half. |
--- |
5242 |
// If the high half is not needed, just compute the low half. |
--- |
| 5243 |
bool HiExists = N->hasAnyUseOfValue(1); |
0 |
5243 |
bool HiExists = N->hasAnyUseOfValue(1); |
0 |
| 5244 |
if (!HiExists && (!LegalOperations || |
0 |
5244 |
if (!HiExists && (!LegalOperations || |
0 |
| 5245 |
TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) { |
0 |
5245 |
TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) { |
0 |
| 5246 |
SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops()); |
0 |
5246 |
SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops()); |
0 |
| 5247 |
return CombineTo(N, Res, Res); |
0 |
5247 |
return CombineTo(N, Res, Res); |
0 |
| 5248 |
} |
--- |
5248 |
} |
--- |
| 5249 |
|
--- |
5249 |
|
--- |
| 5250 |
// If the low half is not needed, just compute the high half. |
--- |
5250 |
// If the low half is not needed, just compute the high half. |
--- |
| 5251 |
bool LoExists = N->hasAnyUseOfValue(0); |
0 |
5251 |
bool LoExists = N->hasAnyUseOfValue(0); |
0 |
| 5252 |
if (!LoExists && (!LegalOperations || |
0 |
5252 |
if (!LoExists && (!LegalOperations || |
0 |
| 5253 |
TLI.isOperationLegalOrCustom(HiOp, N->getValueType(1)))) { |
0 |
5253 |
TLI.isOperationLegalOrCustom(HiOp, N->getValueType(1)))) { |
0 |
| 5254 |
SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops()); |
0 |
5254 |
SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops()); |
0 |
| 5255 |
return CombineTo(N, Res, Res); |
0 |
5255 |
return CombineTo(N, Res, Res); |
0 |
| 5256 |
} |
--- |
5256 |
} |
--- |
| 5257 |
|
--- |
5257 |
|
--- |
| 5258 |
// If both halves are used, return as it is. |
--- |
5258 |
// If both halves are used, return as it is. |
--- |
| 5259 |
if (LoExists && HiExists) |
0 |
5259 |
if (LoExists && HiExists) |
0 |
| 5260 |
return SDValue(); |
0 |
5260 |
return SDValue(); |
0 |
| 5261 |
|
--- |
5261 |
|
--- |
| 5262 |
// If the two computed results can be simplified separately, separate them. |
--- |
5262 |
// If the two computed results can be simplified separately, separate them. |
--- |
| 5263 |
if (LoExists) { |
0 |
5263 |
if (LoExists) { |
0 |
| 5264 |
SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops()); |
0 |
5264 |
SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops()); |
0 |
| 5265 |
AddToWorklist(Lo.getNode()); |
0 |
5265 |
AddToWorklist(Lo.getNode()); |
0 |
| 5266 |
SDValue LoOpt = combine(Lo.getNode()); |
0 |
5266 |
SDValue LoOpt = combine(Lo.getNode()); |
0 |
| 5267 |
if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && |
0 |
5267 |
if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && |
0 |
| 5268 |
(!LegalOperations || |
0 |
5268 |
(!LegalOperations || |
0 |
| 5269 |
TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType()))) |
0 |
5269 |
TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType()))) |
0 |
| 5270 |
return CombineTo(N, LoOpt, LoOpt); |
0 |
5270 |
return CombineTo(N, LoOpt, LoOpt); |
0 |
| 5271 |
} |
--- |
5271 |
} |
--- |
| 5272 |
|
--- |
5272 |
|
--- |
| 5273 |
if (HiExists) { |
0 |
5273 |
if (HiExists) { |
0 |
| 5274 |
SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops()); |
0 |
5274 |
SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops()); |
0 |
| 5275 |
AddToWorklist(Hi.getNode()); |
0 |
5275 |
AddToWorklist(Hi.getNode()); |
0 |
| 5276 |
SDValue HiOpt = combine(Hi.getNode()); |
0 |
5276 |
SDValue HiOpt = combine(Hi.getNode()); |
0 |
| 5277 |
if (HiOpt.getNode() && HiOpt != Hi && |
0 |
5277 |
if (HiOpt.getNode() && HiOpt != Hi && |
0 |
| 5278 |
(!LegalOperations || |
0 |
5278 |
(!LegalOperations || |
0 |
| 5279 |
TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType()))) |
0 |
5279 |
TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType()))) |
0 |
| 5280 |
return CombineTo(N, HiOpt, HiOpt); |
0 |
5280 |
return CombineTo(N, HiOpt, HiOpt); |
0 |
| 5281 |
} |
--- |
5281 |
} |
--- |
| 5282 |
|
--- |
5282 |
|
--- |
| 5283 |
return SDValue(); |
0 |
5283 |
return SDValue(); |
0 |
| 5284 |
} |
--- |
5284 |
} |
--- |
| 5285 |
|
--- |
5285 |
|
--- |
| 5286 |
SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { |
0 |
5286 |
SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { |
0 |
| 5287 |
if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS)) |
0 |
5287 |
if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS)) |
0 |
| 5288 |
return Res; |
0 |
5288 |
return Res; |
0 |
| 5289 |
|
--- |
5289 |
|
--- |
| 5290 |
SDValue N0 = N->getOperand(0); |
0 |
5290 |
SDValue N0 = N->getOperand(0); |
0 |
| 5291 |
SDValue N1 = N->getOperand(1); |
0 |
5291 |
SDValue N1 = N->getOperand(1); |
0 |
| 5292 |
EVT VT = N->getValueType(0); |
0 |
5292 |
EVT VT = N->getValueType(0); |
0 |
| 5293 |
SDLoc DL(N); |
0 |
5293 |
SDLoc DL(N); |
0 |
| 5294 |
|
--- |
5294 |
|
--- |
| 5295 |
// canonicalize constant to RHS (vector doesn't have to splat) |
--- |
5295 |
// canonicalize constant to RHS (vector doesn't have to splat) |
--- |
| 5296 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
5296 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 5297 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
5297 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 5298 |
return DAG.getNode(ISD::SMUL_LOHI, DL, N->getVTList(), N1, N0); |
0 |
5298 |
return DAG.getNode(ISD::SMUL_LOHI, DL, N->getVTList(), N1, N0); |
0 |
| 5299 |
|
--- |
5299 |
|
--- |
| 5300 |
// If the type is twice as wide is legal, transform the mulhu to a wider |
--- |
5300 |
// If the type is twice as wide is legal, transform the mulhu to a wider |
--- |
| 5301 |
// multiply plus a shift. |
--- |
5301 |
// multiply plus a shift. |
--- |
| 5302 |
if (VT.isSimple() && !VT.isVector()) { |
0 |
5302 |
if (VT.isSimple() && !VT.isVector()) { |
0 |
| 5303 |
MVT Simple = VT.getSimpleVT(); |
0 |
5303 |
MVT Simple = VT.getSimpleVT(); |
0 |
| 5304 |
unsigned SimpleSize = Simple.getSizeInBits(); |
0 |
5304 |
unsigned SimpleSize = Simple.getSizeInBits(); |
0 |
| 5305 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); |
0 |
5305 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); |
0 |
| 5306 |
if (TLI.isOperationLegal(ISD::MUL, NewVT)) { |
0 |
5306 |
if (TLI.isOperationLegal(ISD::MUL, NewVT)) { |
0 |
| 5307 |
SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); |
0 |
5307 |
SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); |
0 |
| 5308 |
SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); |
0 |
5308 |
SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); |
0 |
| 5309 |
Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); |
0 |
5309 |
Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); |
0 |
| 5310 |
// Compute the high part as N1. |
--- |
5310 |
// Compute the high part as N1. |
--- |
| 5311 |
Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, |
0 |
5311 |
Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, |
0 |
| 5312 |
DAG.getConstant(SimpleSize, DL, |
0 |
5312 |
DAG.getConstant(SimpleSize, DL, |
0 |
| 5313 |
getShiftAmountTy(Lo.getValueType()))); |
--- |
5313 |
getShiftAmountTy(Lo.getValueType()))); |
--- |
| 5314 |
Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); |
0 |
5314 |
Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); |
0 |
| 5315 |
// Compute the low part as N0. |
--- |
5315 |
// Compute the low part as N0. |
--- |
| 5316 |
Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); |
0 |
5316 |
Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); |
0 |
| 5317 |
return CombineTo(N, Lo, Hi); |
0 |
5317 |
return CombineTo(N, Lo, Hi); |
0 |
| 5318 |
} |
--- |
5318 |
} |
--- |
| 5319 |
} |
--- |
5319 |
} |
--- |
| 5320 |
|
--- |
5320 |
|
--- |
| 5321 |
return SDValue(); |
0 |
5321 |
return SDValue(); |
0 |
| 5322 |
} |
0 |
5322 |
} |
0 |
| 5323 |
|
--- |
5323 |
|
--- |
| 5324 |
SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { |
0 |
5324 |
SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { |
0 |
| 5325 |
if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU)) |
0 |
5325 |
if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU)) |
0 |
| 5326 |
return Res; |
0 |
5326 |
return Res; |
0 |
| 5327 |
|
--- |
5327 |
|
--- |
| 5328 |
SDValue N0 = N->getOperand(0); |
0 |
5328 |
SDValue N0 = N->getOperand(0); |
0 |
| 5329 |
SDValue N1 = N->getOperand(1); |
0 |
5329 |
SDValue N1 = N->getOperand(1); |
0 |
| 5330 |
EVT VT = N->getValueType(0); |
0 |
5330 |
EVT VT = N->getValueType(0); |
0 |
| 5331 |
SDLoc DL(N); |
0 |
5331 |
SDLoc DL(N); |
0 |
| 5332 |
|
--- |
5332 |
|
--- |
| 5333 |
// canonicalize constant to RHS (vector doesn't have to splat) |
--- |
5333 |
// canonicalize constant to RHS (vector doesn't have to splat) |
--- |
| 5334 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
5334 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 5335 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
5335 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 5336 |
return DAG.getNode(ISD::UMUL_LOHI, DL, N->getVTList(), N1, N0); |
0 |
5336 |
return DAG.getNode(ISD::UMUL_LOHI, DL, N->getVTList(), N1, N0); |
0 |
| 5337 |
|
--- |
5337 |
|
--- |
| 5338 |
// (umul_lohi N0, 0) -> (0, 0) |
--- |
5338 |
// (umul_lohi N0, 0) -> (0, 0) |
--- |
| 5339 |
if (isNullConstant(N1)) { |
0 |
5339 |
if (isNullConstant(N1)) { |
0 |
| 5340 |
SDValue Zero = DAG.getConstant(0, DL, VT); |
0 |
5340 |
SDValue Zero = DAG.getConstant(0, DL, VT); |
0 |
| 5341 |
return CombineTo(N, Zero, Zero); |
0 |
5341 |
return CombineTo(N, Zero, Zero); |
0 |
| 5342 |
} |
--- |
5342 |
} |
--- |
| 5343 |
|
--- |
5343 |
|
--- |
| 5344 |
// (umul_lohi N0, 1) -> (N0, 0) |
--- |
5344 |
// (umul_lohi N0, 1) -> (N0, 0) |
--- |
| 5345 |
if (isOneConstant(N1)) { |
0 |
5345 |
if (isOneConstant(N1)) { |
0 |
| 5346 |
SDValue Zero = DAG.getConstant(0, DL, VT); |
0 |
5346 |
SDValue Zero = DAG.getConstant(0, DL, VT); |
0 |
| 5347 |
return CombineTo(N, N0, Zero); |
0 |
5347 |
return CombineTo(N, N0, Zero); |
0 |
| 5348 |
} |
--- |
5348 |
} |
--- |
| 5349 |
|
--- |
5349 |
|
--- |
| 5350 |
// If the type is twice as wide is legal, transform the mulhu to a wider |
--- |
5350 |
// If the type is twice as wide is legal, transform the mulhu to a wider |
--- |
| 5351 |
// multiply plus a shift. |
--- |
5351 |
// multiply plus a shift. |
--- |
| 5352 |
if (VT.isSimple() && !VT.isVector()) { |
0 |
5352 |
if (VT.isSimple() && !VT.isVector()) { |
0 |
| 5353 |
MVT Simple = VT.getSimpleVT(); |
0 |
5353 |
MVT Simple = VT.getSimpleVT(); |
0 |
| 5354 |
unsigned SimpleSize = Simple.getSizeInBits(); |
0 |
5354 |
unsigned SimpleSize = Simple.getSizeInBits(); |
0 |
| 5355 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); |
0 |
5355 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); |
0 |
| 5356 |
if (TLI.isOperationLegal(ISD::MUL, NewVT)) { |
0 |
5356 |
if (TLI.isOperationLegal(ISD::MUL, NewVT)) { |
0 |
| 5357 |
SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); |
0 |
5357 |
SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); |
0 |
| 5358 |
SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); |
0 |
5358 |
SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); |
0 |
| 5359 |
Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); |
0 |
5359 |
Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); |
0 |
| 5360 |
// Compute the high part as N1. |
--- |
5360 |
// Compute the high part as N1. |
--- |
| 5361 |
Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, |
0 |
5361 |
Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, |
0 |
| 5362 |
DAG.getConstant(SimpleSize, DL, |
0 |
5362 |
DAG.getConstant(SimpleSize, DL, |
0 |
| 5363 |
getShiftAmountTy(Lo.getValueType()))); |
--- |
5363 |
getShiftAmountTy(Lo.getValueType()))); |
--- |
| 5364 |
Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); |
0 |
5364 |
Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); |
0 |
| 5365 |
// Compute the low part as N0. |
--- |
5365 |
// Compute the low part as N0. |
--- |
| 5366 |
Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); |
0 |
5366 |
Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); |
0 |
| 5367 |
return CombineTo(N, Lo, Hi); |
0 |
5367 |
return CombineTo(N, Lo, Hi); |
0 |
| 5368 |
} |
--- |
5368 |
} |
--- |
| 5369 |
} |
--- |
5369 |
} |
--- |
| 5370 |
|
--- |
5370 |
|
--- |
| 5371 |
return SDValue(); |
0 |
5371 |
return SDValue(); |
0 |
| 5372 |
} |
0 |
5372 |
} |
0 |
| 5373 |
|
--- |
5373 |
|
--- |
| 5374 |
SDValue DAGCombiner::visitMULO(SDNode *N) { |
0 |
5374 |
SDValue DAGCombiner::visitMULO(SDNode *N) { |
0 |
| 5375 |
SDValue N0 = N->getOperand(0); |
0 |
5375 |
SDValue N0 = N->getOperand(0); |
0 |
| 5376 |
SDValue N1 = N->getOperand(1); |
0 |
5376 |
SDValue N1 = N->getOperand(1); |
0 |
| 5377 |
EVT VT = N0.getValueType(); |
0 |
5377 |
EVT VT = N0.getValueType(); |
0 |
| 5378 |
bool IsSigned = (ISD::SMULO == N->getOpcode()); |
0 |
5378 |
bool IsSigned = (ISD::SMULO == N->getOpcode()); |
0 |
| 5379 |
|
--- |
5379 |
|
--- |
| 5380 |
EVT CarryVT = N->getValueType(1); |
0 |
5380 |
EVT CarryVT = N->getValueType(1); |
0 |
| 5381 |
SDLoc DL(N); |
0 |
5381 |
SDLoc DL(N); |
0 |
| 5382 |
|
--- |
5382 |
|
--- |
| 5383 |
ConstantSDNode *N0C = isConstOrConstSplat(N0); |
0 |
5383 |
ConstantSDNode *N0C = isConstOrConstSplat(N0); |
0 |
| 5384 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
5384 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
| 5385 |
|
--- |
5385 |
|
--- |
| 5386 |
// fold operation with constant operands. |
--- |
5386 |
// fold operation with constant operands. |
--- |
| 5387 |
// TODO: Move this to FoldConstantArithmetic when it supports nodes with |
--- |
5387 |
// TODO: Move this to FoldConstantArithmetic when it supports nodes with |
--- |
| 5388 |
// multiple results. |
--- |
5388 |
// multiple results. |
--- |
| 5389 |
if (N0C && N1C) { |
0 |
5389 |
if (N0C && N1C) { |
0 |
| 5390 |
bool Overflow; |
--- |
5390 |
bool Overflow; |
--- |
| 5391 |
APInt Result = |
--- |
5391 |
APInt Result = |
--- |
| 5392 |
IsSigned ? N0C->getAPIntValue().smul_ov(N1C->getAPIntValue(), Overflow) |
0 |
5392 |
IsSigned ? N0C->getAPIntValue().smul_ov(N1C->getAPIntValue(), Overflow) |
0 |
| 5393 |
: N0C->getAPIntValue().umul_ov(N1C->getAPIntValue(), Overflow); |
0 |
5393 |
: N0C->getAPIntValue().umul_ov(N1C->getAPIntValue(), Overflow); |
0 |
| 5394 |
return CombineTo(N, DAG.getConstant(Result, DL, VT), |
0 |
5394 |
return CombineTo(N, DAG.getConstant(Result, DL, VT), |
0 |
| 5395 |
DAG.getBoolConstant(Overflow, DL, CarryVT, CarryVT)); |
0 |
5395 |
DAG.getBoolConstant(Overflow, DL, CarryVT, CarryVT)); |
0 |
| 5396 |
} |
0 |
5396 |
} |
0 |
| 5397 |
|
--- |
5397 |
|
--- |
| 5398 |
// canonicalize constant to RHS. |
--- |
5398 |
// canonicalize constant to RHS. |
--- |
| 5399 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
5399 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 5400 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
5400 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 5401 |
return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); |
0 |
5401 |
return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0); |
0 |
| 5402 |
|
--- |
5402 |
|
--- |
| 5403 |
// fold (mulo x, 0) -> 0 + no carry out |
--- |
5403 |
// fold (mulo x, 0) -> 0 + no carry out |
--- |
| 5404 |
if (isNullOrNullSplat(N1)) |
0 |
5404 |
if (isNullOrNullSplat(N1)) |
0 |
| 5405 |
return CombineTo(N, DAG.getConstant(0, DL, VT), |
0 |
5405 |
return CombineTo(N, DAG.getConstant(0, DL, VT), |
0 |
| 5406 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
5406 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
| 5407 |
|
--- |
5407 |
|
--- |
| 5408 |
// (mulo x, 2) -> (addo x, x) |
--- |
5408 |
// (mulo x, 2) -> (addo x, x) |
--- |
| 5409 |
// FIXME: This needs a freeze. |
--- |
5409 |
// FIXME: This needs a freeze. |
--- |
| 5410 |
if (N1C && N1C->getAPIntValue() == 2 && |
0 |
5410 |
if (N1C && N1C->getAPIntValue() == 2 && |
0 |
| 5411 |
(!IsSigned || VT.getScalarSizeInBits() > 2)) |
0 |
5411 |
(!IsSigned || VT.getScalarSizeInBits() > 2)) |
0 |
| 5412 |
return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, DL, |
0 |
5412 |
return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, DL, |
0 |
| 5413 |
N->getVTList(), N0, N0); |
0 |
5413 |
N->getVTList(), N0, N0); |
0 |
| 5414 |
|
--- |
5414 |
|
--- |
| 5415 |
if (IsSigned) { |
0 |
5415 |
if (IsSigned) { |
0 |
| 5416 |
// A 1 bit SMULO overflows if both inputs are 1. |
--- |
5416 |
// A 1 bit SMULO overflows if both inputs are 1. |
--- |
| 5417 |
if (VT.getScalarSizeInBits() == 1) { |
0 |
5417 |
if (VT.getScalarSizeInBits() == 1) { |
0 |
| 5418 |
SDValue And = DAG.getNode(ISD::AND, DL, VT, N0, N1); |
0 |
5418 |
SDValue And = DAG.getNode(ISD::AND, DL, VT, N0, N1); |
0 |
| 5419 |
return CombineTo(N, And, |
0 |
5419 |
return CombineTo(N, And, |
0 |
| 5420 |
DAG.getSetCC(DL, CarryVT, And, |
0 |
5420 |
DAG.getSetCC(DL, CarryVT, And, |
0 |
| 5421 |
DAG.getConstant(0, DL, VT), ISD::SETNE)); |
0 |
5421 |
DAG.getConstant(0, DL, VT), ISD::SETNE)); |
0 |
| 5422 |
} |
--- |
5422 |
} |
--- |
| 5423 |
|
--- |
5423 |
|
--- |
| 5424 |
// Multiplying n * m significant bits yields a result of n + m significant |
--- |
5424 |
// Multiplying n * m significant bits yields a result of n + m significant |
--- |
| 5425 |
// bits. If the total number of significant bits does not exceed the |
--- |
5425 |
// bits. If the total number of significant bits does not exceed the |
--- |
| 5426 |
// result bit width (minus 1), there is no overflow. |
--- |
5426 |
// result bit width (minus 1), there is no overflow. |
--- |
| 5427 |
unsigned SignBits = DAG.ComputeNumSignBits(N0); |
0 |
5427 |
unsigned SignBits = DAG.ComputeNumSignBits(N0); |
0 |
| 5428 |
if (SignBits > 1) |
0 |
5428 |
if (SignBits > 1) |
0 |
| 5429 |
SignBits += DAG.ComputeNumSignBits(N1); |
0 |
5429 |
SignBits += DAG.ComputeNumSignBits(N1); |
0 |
| 5430 |
if (SignBits > VT.getScalarSizeInBits() + 1) |
0 |
5430 |
if (SignBits > VT.getScalarSizeInBits() + 1) |
0 |
| 5431 |
return CombineTo(N, DAG.getNode(ISD::MUL, DL, VT, N0, N1), |
0 |
5431 |
return CombineTo(N, DAG.getNode(ISD::MUL, DL, VT, N0, N1), |
0 |
| 5432 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
5432 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
| 5433 |
} else { |
--- |
5433 |
} else { |
--- |
| 5434 |
KnownBits N1Known = DAG.computeKnownBits(N1); |
0 |
5434 |
KnownBits N1Known = DAG.computeKnownBits(N1); |
0 |
| 5435 |
KnownBits N0Known = DAG.computeKnownBits(N0); |
0 |
5435 |
KnownBits N0Known = DAG.computeKnownBits(N0); |
0 |
| 5436 |
bool Overflow; |
--- |
5436 |
bool Overflow; |
--- |
| 5437 |
(void)N0Known.getMaxValue().umul_ov(N1Known.getMaxValue(), Overflow); |
0 |
5437 |
(void)N0Known.getMaxValue().umul_ov(N1Known.getMaxValue(), Overflow); |
0 |
| 5438 |
if (!Overflow) |
0 |
5438 |
if (!Overflow) |
0 |
| 5439 |
return CombineTo(N, DAG.getNode(ISD::MUL, DL, VT, N0, N1), |
0 |
5439 |
return CombineTo(N, DAG.getNode(ISD::MUL, DL, VT, N0, N1), |
0 |
| 5440 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
5440 |
DAG.getConstant(0, DL, CarryVT)); |
0 |
| 5441 |
} |
0 |
5441 |
} |
0 |
| 5442 |
|
--- |
5442 |
|
--- |
| 5443 |
return SDValue(); |
0 |
5443 |
return SDValue(); |
0 |
| 5444 |
} |
0 |
5444 |
} |
0 |
| 5445 |
|
--- |
5445 |
|
--- |
| 5446 |
// Function to calculate whether the Min/Max pair of SDNodes (potentially |
--- |
5446 |
// Function to calculate whether the Min/Max pair of SDNodes (potentially |
--- |
| 5447 |
// swapped around) make a signed saturate pattern, clamping to between a signed |
--- |
5447 |
// swapped around) make a signed saturate pattern, clamping to between a signed |
--- |
| 5448 |
// saturate of -2^(BW-1) and 2^(BW-1)-1, or an unsigned saturate of 0 and 2^BW. |
--- |
5448 |
// saturate of -2^(BW-1) and 2^(BW-1)-1, or an unsigned saturate of 0 and 2^BW. |
--- |
| 5449 |
// Returns the node being clamped and the bitwidth of the clamp in BW. Should |
--- |
5449 |
// Returns the node being clamped and the bitwidth of the clamp in BW. Should |
--- |
| 5450 |
// work with both SMIN/SMAX nodes and setcc/select combo. The operands are the |
--- |
5450 |
// work with both SMIN/SMAX nodes and setcc/select combo. The operands are the |
--- |
| 5451 |
// same as SimplifySelectCC. N0
| --- |
5451 |
// same as SimplifySelectCC. N0
| --- |
| |
| 5452 |
static SDValue isSaturatingMinMax(SDValue N0, SDValue N1, SDValue N2, |
0 |
5452 |
static SDValue isSaturatingMinMax(SDValue N0, SDValue N1, SDValue N2, |
0 |
| 5453 |
SDValue N3, ISD::CondCode CC, unsigned &BW, |
--- |
5453 |
SDValue N3, ISD::CondCode CC, unsigned &BW, |
--- |
| 5454 |
bool &Unsigned, SelectionDAG &DAG) { |
--- |
5454 |
bool &Unsigned, SelectionDAG &DAG) { |
--- |
| 5455 |
auto isSignedMinMax = [&](SDValue N0, SDValue N1, SDValue N2, SDValue N3, |
0 |
5455 |
auto isSignedMinMax = [&](SDValue N0, SDValue N1, SDValue N2, SDValue N3, |
0 |
| 5456 |
ISD::CondCode CC) { |
--- |
5456 |
ISD::CondCode CC) { |
--- |
| 5457 |
// The compare and select operand should be the same or the select operands |
--- |
5457 |
// The compare and select operand should be the same or the select operands |
--- |
| 5458 |
// should be truncated versions of the comparison. |
--- |
5458 |
// should be truncated versions of the comparison. |
--- |
| 5459 |
if (N0 != N2 && (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) |
0 |
5459 |
if (N0 != N2 && (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) |
0 |
| 5460 |
return 0; |
0 |
5460 |
return 0; |
0 |
| 5461 |
// The constants need to be the same or a truncated version of each other. |
--- |
5461 |
// The constants need to be the same or a truncated version of each other. |
--- |
| 5462 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
5462 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
| 5463 |
ConstantSDNode *N3C = isConstOrConstSplat(N3); |
0 |
5463 |
ConstantSDNode *N3C = isConstOrConstSplat(N3); |
0 |
| 5464 |
if (!N1C || !N3C) |
0 |
5464 |
if (!N1C || !N3C) |
0 |
| 5465 |
return 0; |
0 |
5465 |
return 0; |
0 |
| 5466 |
const APInt &C1 = N1C->getAPIntValue(); |
0 |
5466 |
const APInt &C1 = N1C->getAPIntValue(); |
0 |
| 5467 |
const APInt &C2 = N3C->getAPIntValue(); |
0 |
5467 |
const APInt &C2 = N3C->getAPIntValue(); |
0 |
| 5468 |
if (C1.getBitWidth() < C2.getBitWidth() || C1 != C2.sext(C1.getBitWidth())) |
0 |
5468 |
if (C1.getBitWidth() < C2.getBitWidth() || C1 != C2.sext(C1.getBitWidth())) |
0 |
| 5469 |
return 0; |
0 |
5469 |
return 0; |
0 |
| 5470 |
return CC == ISD::SETLT ? ISD::SMIN : (CC == ISD::SETGT ? ISD::SMAX : 0); |
0 |
5470 |
return CC == ISD::SETLT ? ISD::SMIN : (CC == ISD::SETGT ? ISD::SMAX : 0); |
0 |
| 5471 |
}; |
--- |
5471 |
}; |
--- |
| 5472 |
|
--- |
5472 |
|
--- |
| 5473 |
// Check the initial value is a SMIN/SMAX equivalent. |
--- |
5473 |
// Check the initial value is a SMIN/SMAX equivalent. |
--- |
| 5474 |
unsigned Opcode0 = isSignedMinMax(N0, N1, N2, N3, CC); |
0 |
5474 |
unsigned Opcode0 = isSignedMinMax(N0, N1, N2, N3, CC); |
0 |
| 5475 |
if (!Opcode0) |
0 |
5475 |
if (!Opcode0) |
0 |
| 5476 |
return SDValue(); |
0 |
5476 |
return SDValue(); |
0 |
| 5477 |
|
--- |
5477 |
|
--- |
| 5478 |
// We could only need one range check, if the fptosi could never produce |
--- |
5478 |
// We could only need one range check, if the fptosi could never produce |
--- |
| 5479 |
// the upper value. |
--- |
5479 |
// the upper value. |
--- |
| 5480 |
if (N0.getOpcode() == ISD::FP_TO_SINT && Opcode0 == ISD::SMAX) { |
0 |
5480 |
if (N0.getOpcode() == ISD::FP_TO_SINT && Opcode0 == ISD::SMAX) { |
0 |
| 5481 |
if (isNullOrNullSplat(N3)) { |
0 |
5481 |
if (isNullOrNullSplat(N3)) { |
0 |
| 5482 |
EVT IntVT = N0.getValueType().getScalarType(); |
0 |
5482 |
EVT IntVT = N0.getValueType().getScalarType(); |
0 |
| 5483 |
EVT FPVT = N0.getOperand(0).getValueType().getScalarType(); |
0 |
5483 |
EVT FPVT = N0.getOperand(0).getValueType().getScalarType(); |
0 |
| 5484 |
if (FPVT.isSimple()) { |
0 |
5484 |
if (FPVT.isSimple()) { |
0 |
| 5485 |
Type *InputTy = FPVT.getTypeForEVT(*DAG.getContext()); |
0 |
5485 |
Type *InputTy = FPVT.getTypeForEVT(*DAG.getContext()); |
0 |
| 5486 |
const fltSemantics &Semantics = InputTy->getFltSemantics(); |
0 |
5486 |
const fltSemantics &Semantics = InputTy->getFltSemantics(); |
0 |
| 5487 |
uint32_t MinBitWidth = |
--- |
5487 |
uint32_t MinBitWidth = |
--- |
| 5488 |
APFloatBase::semanticsIntSizeInBits(Semantics, /*isSigned*/ true); |
0 |
5488 |
APFloatBase::semanticsIntSizeInBits(Semantics, /*isSigned*/ true); |
0 |
| 5489 |
if (IntVT.getSizeInBits() >= MinBitWidth) { |
0 |
5489 |
if (IntVT.getSizeInBits() >= MinBitWidth) { |
0 |
| 5490 |
Unsigned = true; |
0 |
5490 |
Unsigned = true; |
0 |
| 5491 |
BW = PowerOf2Ceil(MinBitWidth); |
0 |
5491 |
BW = PowerOf2Ceil(MinBitWidth); |
0 |
| 5492 |
return N0; |
0 |
5492 |
return N0; |
0 |
| 5493 |
} |
--- |
5493 |
} |
--- |
| 5494 |
} |
--- |
5494 |
} |
--- |
| 5495 |
} |
--- |
5495 |
} |
--- |
| 5496 |
} |
--- |
5496 |
} |
--- |
| 5497 |
|
--- |
5497 |
|
--- |
| 5498 |
SDValue N00, N01, N02, N03; |
0 |
5498 |
SDValue N00, N01, N02, N03; |
0 |
| 5499 |
ISD::CondCode N0CC; |
--- |
5499 |
ISD::CondCode N0CC; |
--- |
| 5500 |
switch (N0.getOpcode()) { |
0 |
5500 |
switch (N0.getOpcode()) { |
0 |
| 5501 |
case ISD::SMIN: |
0 |
5501 |
case ISD::SMIN: |
0 |
| 5502 |
case ISD::SMAX: |
--- |
5502 |
case ISD::SMAX: |
--- |
| 5503 |
N00 = N02 = N0.getOperand(0); |
0 |
5503 |
N00 = N02 = N0.getOperand(0); |
0 |
| 5504 |
N01 = N03 = N0.getOperand(1); |
0 |
5504 |
N01 = N03 = N0.getOperand(1); |
0 |
| 5505 |
N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT; |
0 |
5505 |
N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT; |
0 |
| 5506 |
break; |
0 |
5506 |
break; |
0 |
| 5507 |
case ISD::SELECT_CC: |
0 |
5507 |
case ISD::SELECT_CC: |
0 |
| 5508 |
N00 = N0.getOperand(0); |
0 |
5508 |
N00 = N0.getOperand(0); |
0 |
| 5509 |
N01 = N0.getOperand(1); |
0 |
5509 |
N01 = N0.getOperand(1); |
0 |
| 5510 |
N02 = N0.getOperand(2); |
0 |
5510 |
N02 = N0.getOperand(2); |
0 |
| 5511 |
N03 = N0.getOperand(3); |
0 |
5511 |
N03 = N0.getOperand(3); |
0 |
| 5512 |
N0CC = cast(N0.getOperand(4))->get(); |
0 |
5512 |
N0CC = cast(N0.getOperand(4))->get(); |
0 |
| 5513 |
break; |
0 |
5513 |
break; |
0 |
| 5514 |
case ISD::SELECT: |
0 |
5514 |
case ISD::SELECT: |
0 |
| 5515 |
case ISD::VSELECT: |
--- |
5515 |
case ISD::VSELECT: |
--- |
| 5516 |
if (N0.getOperand(0).getOpcode() != ISD::SETCC) |
0 |
5516 |
if (N0.getOperand(0).getOpcode() != ISD::SETCC) |
0 |
| 5517 |
return SDValue(); |
0 |
5517 |
return SDValue(); |
0 |
| 5518 |
N00 = N0.getOperand(0).getOperand(0); |
0 |
5518 |
N00 = N0.getOperand(0).getOperand(0); |
0 |
| 5519 |
N01 = N0.getOperand(0).getOperand(1); |
0 |
5519 |
N01 = N0.getOperand(0).getOperand(1); |
0 |
| 5520 |
N02 = N0.getOperand(1); |
0 |
5520 |
N02 = N0.getOperand(1); |
0 |
| 5521 |
N03 = N0.getOperand(2); |
0 |
5521 |
N03 = N0.getOperand(2); |
0 |
| 5522 |
N0CC = cast(N0.getOperand(0).getOperand(2))->get(); |
0 |
5522 |
N0CC = cast(N0.getOperand(0).getOperand(2))->get(); |
0 |
| 5523 |
break; |
0 |
5523 |
break; |
0 |
| 5524 |
default: |
0 |
5524 |
default: |
0 |
| 5525 |
return SDValue(); |
0 |
5525 |
return SDValue(); |
0 |
| 5526 |
} |
--- |
5526 |
} |
--- |
| 5527 |
|
--- |
5527 |
|
--- |
| 5528 |
unsigned Opcode1 = isSignedMinMax(N00, N01, N02, N03, N0CC); |
0 |
5528 |
unsigned Opcode1 = isSignedMinMax(N00, N01, N02, N03, N0CC); |
0 |
| 5529 |
if (!Opcode1 || Opcode0 == Opcode1) |
0 |
5529 |
if (!Opcode1 || Opcode0 == Opcode1) |
0 |
| 5530 |
return SDValue(); |
0 |
5530 |
return SDValue(); |
0 |
| 5531 |
|
--- |
5531 |
|
--- |
| 5532 |
ConstantSDNode *MinCOp = isConstOrConstSplat(Opcode0 == ISD::SMIN ? N1 : N01); |
0 |
5532 |
ConstantSDNode *MinCOp = isConstOrConstSplat(Opcode0 == ISD::SMIN ? N1 : N01); |
0 |
| 5533 |
ConstantSDNode *MaxCOp = isConstOrConstSplat(Opcode0 == ISD::SMIN ? N01 : N1); |
0 |
5533 |
ConstantSDNode *MaxCOp = isConstOrConstSplat(Opcode0 == ISD::SMIN ? N01 : N1); |
0 |
| 5534 |
if (!MinCOp || !MaxCOp || MinCOp->getValueType(0) != MaxCOp->getValueType(0)) |
0 |
5534 |
if (!MinCOp || !MaxCOp || MinCOp->getValueType(0) != MaxCOp->getValueType(0)) |
0 |
| 5535 |
return SDValue(); |
0 |
5535 |
return SDValue(); |
0 |
| 5536 |
|
--- |
5536 |
|
--- |
| 5537 |
const APInt &MinC = MinCOp->getAPIntValue(); |
0 |
5537 |
const APInt &MinC = MinCOp->getAPIntValue(); |
0 |
| 5538 |
const APInt &MaxC = MaxCOp->getAPIntValue(); |
0 |
5538 |
const APInt &MaxC = MaxCOp->getAPIntValue(); |
0 |
| 5539 |
APInt MinCPlus1 = MinC + 1; |
0 |
5539 |
APInt MinCPlus1 = MinC + 1; |
0 |
| 5540 |
if (-MaxC == MinCPlus1 && MinCPlus1.isPowerOf2()) { |
0 |
5540 |
if (-MaxC == MinCPlus1 && MinCPlus1.isPowerOf2()) { |
0 |
| 5541 |
BW = MinCPlus1.exactLogBase2() + 1; |
0 |
5541 |
BW = MinCPlus1.exactLogBase2() + 1; |
0 |
| 5542 |
Unsigned = false; |
0 |
5542 |
Unsigned = false; |
0 |
| 5543 |
return N02; |
0 |
5543 |
return N02; |
0 |
| 5544 |
} |
--- |
5544 |
} |
--- |
| 5545 |
|
--- |
5545 |
|
--- |
| 5546 |
if (MaxC == 0 && MinCPlus1.isPowerOf2()) { |
0 |
5546 |
if (MaxC == 0 && MinCPlus1.isPowerOf2()) { |
0 |
| 5547 |
BW = MinCPlus1.exactLogBase2(); |
0 |
5547 |
BW = MinCPlus1.exactLogBase2(); |
0 |
| 5548 |
Unsigned = true; |
0 |
5548 |
Unsigned = true; |
0 |
| 5549 |
return N02; |
0 |
5549 |
return N02; |
0 |
| 5550 |
} |
--- |
5550 |
} |
--- |
| 5551 |
|
--- |
5551 |
|
--- |
| 5552 |
return SDValue(); |
0 |
5552 |
return SDValue(); |
0 |
| 5553 |
} |
--- |
5553 |
} |
--- |
| 5554 |
|
--- |
5554 |
|
--- |
| 5555 |
static SDValue PerformMinMaxFpToSatCombine(SDValue N0, SDValue N1, SDValue N2, |
0 |
5555 |
static SDValue PerformMinMaxFpToSatCombine(SDValue N0, SDValue N1, SDValue N2, |
0 |
| 5556 |
SDValue N3, ISD::CondCode CC, |
--- |
5556 |
SDValue N3, ISD::CondCode CC, |
--- |
| 5557 |
SelectionDAG &DAG) { |
--- |
5557 |
SelectionDAG &DAG) { |
--- |
| 5558 |
unsigned BW; |
--- |
5558 |
unsigned BW; |
--- |
| 5559 |
bool Unsigned; |
--- |
5559 |
bool Unsigned; |
--- |
| 5560 |
SDValue Fp = isSaturatingMinMax(N0, N1, N2, N3, CC, BW, Unsigned, DAG); |
0 |
5560 |
SDValue Fp = isSaturatingMinMax(N0, N1, N2, N3, CC, BW, Unsigned, DAG); |
0 |
| 5561 |
if (!Fp || Fp.getOpcode() != ISD::FP_TO_SINT) |
0 |
5561 |
if (!Fp || Fp.getOpcode() != ISD::FP_TO_SINT) |
0 |
| 5562 |
return SDValue(); |
0 |
5562 |
return SDValue(); |
0 |
| 5563 |
EVT FPVT = Fp.getOperand(0).getValueType(); |
0 |
5563 |
EVT FPVT = Fp.getOperand(0).getValueType(); |
0 |
| 5564 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), BW); |
0 |
5564 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), BW); |
0 |
| 5565 |
if (FPVT.isVector()) |
0 |
5565 |
if (FPVT.isVector()) |
0 |
| 5566 |
NewVT = EVT::getVectorVT(*DAG.getContext(), NewVT, |
0 |
5566 |
NewVT = EVT::getVectorVT(*DAG.getContext(), NewVT, |
0 |
| 5567 |
FPVT.getVectorElementCount()); |
--- |
5567 |
FPVT.getVectorElementCount()); |
--- |
| 5568 |
unsigned NewOpc = Unsigned ? ISD::FP_TO_UINT_SAT : ISD::FP_TO_SINT_SAT; |
0 |
5568 |
unsigned NewOpc = Unsigned ? ISD::FP_TO_UINT_SAT : ISD::FP_TO_SINT_SAT; |
0 |
| 5569 |
if (!DAG.getTargetLoweringInfo().shouldConvertFpToSat(NewOpc, FPVT, NewVT)) |
0 |
5569 |
if (!DAG.getTargetLoweringInfo().shouldConvertFpToSat(NewOpc, FPVT, NewVT)) |
0 |
| 5570 |
return SDValue(); |
0 |
5570 |
return SDValue(); |
0 |
| 5571 |
SDLoc DL(Fp); |
0 |
5571 |
SDLoc DL(Fp); |
0 |
| 5572 |
SDValue Sat = DAG.getNode(NewOpc, DL, NewVT, Fp.getOperand(0), |
0 |
5572 |
SDValue Sat = DAG.getNode(NewOpc, DL, NewVT, Fp.getOperand(0), |
0 |
| 5573 |
DAG.getValueType(NewVT.getScalarType())); |
--- |
5573 |
DAG.getValueType(NewVT.getScalarType())); |
--- |
| 5574 |
return DAG.getExtOrTrunc(!Unsigned, Sat, DL, N2->getValueType(0)); |
0 |
5574 |
return DAG.getExtOrTrunc(!Unsigned, Sat, DL, N2->getValueType(0)); |
0 |
| 5575 |
} |
0 |
5575 |
} |
0 |
| 5576 |
|
--- |
5576 |
|
--- |
| 5577 |
static SDValue PerformUMinFpToSatCombine(SDValue N0, SDValue N1, SDValue N2, |
0 |
5577 |
static SDValue PerformUMinFpToSatCombine(SDValue N0, SDValue N1, SDValue N2, |
0 |
| 5578 |
SDValue N3, ISD::CondCode CC, |
--- |
5578 |
SDValue N3, ISD::CondCode CC, |
--- |
| 5579 |
SelectionDAG &DAG) { |
--- |
5579 |
SelectionDAG &DAG) { |
--- |
| 5580 |
// We are looking for UMIN(FPTOUI(X), (2^n)-1), which may have come via a |
--- |
5580 |
// We are looking for UMIN(FPTOUI(X), (2^n)-1), which may have come via a |
--- |
| 5581 |
// select/vselect/select_cc. The two operands pairs for the select (N2/N3) may |
--- |
5581 |
// select/vselect/select_cc. The two operands pairs for the select (N2/N3) may |
--- |
| 5582 |
// be truncated versions of the the setcc (N0/N1). |
--- |
5582 |
// be truncated versions of the the setcc (N0/N1). |
--- |
| 5583 |
if ((N0 != N2 && |
0 |
5583 |
if ((N0 != N2 && |
0 |
| 5584 |
(N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) || |
0 |
5584 |
(N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) || |
0 |
| 5585 |
N0.getOpcode() != ISD::FP_TO_UINT || CC != ISD::SETULT) |
0 |
5585 |
N0.getOpcode() != ISD::FP_TO_UINT || CC != ISD::SETULT) |
0 |
| 5586 |
return SDValue(); |
0 |
5586 |
return SDValue(); |
0 |
| 5587 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
5587 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
| 5588 |
ConstantSDNode *N3C = isConstOrConstSplat(N3); |
0 |
5588 |
ConstantSDNode *N3C = isConstOrConstSplat(N3); |
0 |
| 5589 |
if (!N1C || !N3C) |
0 |
5589 |
if (!N1C || !N3C) |
0 |
| 5590 |
return SDValue(); |
0 |
5590 |
return SDValue(); |
0 |
| 5591 |
const APInt &C1 = N1C->getAPIntValue(); |
0 |
5591 |
const APInt &C1 = N1C->getAPIntValue(); |
0 |
| 5592 |
const APInt &C3 = N3C->getAPIntValue(); |
0 |
5592 |
const APInt &C3 = N3C->getAPIntValue(); |
0 |
| 5593 |
if (!(C1 + 1).isPowerOf2() || C1.getBitWidth() < C3.getBitWidth() || |
0 |
5593 |
if (!(C1 + 1).isPowerOf2() || C1.getBitWidth() < C3.getBitWidth() || |
0 |
| 5594 |
C1 != C3.zext(C1.getBitWidth())) |
0 |
5594 |
C1 != C3.zext(C1.getBitWidth())) |
0 |
| 5595 |
return SDValue(); |
0 |
5595 |
return SDValue(); |
0 |
| 5596 |
|
--- |
5596 |
|
--- |
| 5597 |
unsigned BW = (C1 + 1).exactLogBase2(); |
0 |
5597 |
unsigned BW = (C1 + 1).exactLogBase2(); |
0 |
| 5598 |
EVT FPVT = N0.getOperand(0).getValueType(); |
0 |
5598 |
EVT FPVT = N0.getOperand(0).getValueType(); |
0 |
| 5599 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), BW); |
0 |
5599 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), BW); |
0 |
| 5600 |
if (FPVT.isVector()) |
0 |
5600 |
if (FPVT.isVector()) |
0 |
| 5601 |
NewVT = EVT::getVectorVT(*DAG.getContext(), NewVT, |
0 |
5601 |
NewVT = EVT::getVectorVT(*DAG.getContext(), NewVT, |
0 |
| 5602 |
FPVT.getVectorElementCount()); |
--- |
5602 |
FPVT.getVectorElementCount()); |
--- |
| 5603 |
if (!DAG.getTargetLoweringInfo().shouldConvertFpToSat(ISD::FP_TO_UINT_SAT, |
0 |
5603 |
if (!DAG.getTargetLoweringInfo().shouldConvertFpToSat(ISD::FP_TO_UINT_SAT, |
0 |
| 5604 |
FPVT, NewVT)) |
--- |
5604 |
FPVT, NewVT)) |
--- |
| 5605 |
return SDValue(); |
0 |
5605 |
return SDValue(); |
0 |
| 5606 |
|
--- |
5606 |
|
--- |
| 5607 |
SDValue Sat = |
--- |
5607 |
SDValue Sat = |
--- |
| 5608 |
DAG.getNode(ISD::FP_TO_UINT_SAT, SDLoc(N0), NewVT, N0.getOperand(0), |
0 |
5608 |
DAG.getNode(ISD::FP_TO_UINT_SAT, SDLoc(N0), NewVT, N0.getOperand(0), |
0 |
| 5609 |
DAG.getValueType(NewVT.getScalarType())); |
--- |
5609 |
DAG.getValueType(NewVT.getScalarType())); |
--- |
| 5610 |
return DAG.getZExtOrTrunc(Sat, SDLoc(N0), N3.getValueType()); |
0 |
5610 |
return DAG.getZExtOrTrunc(Sat, SDLoc(N0), N3.getValueType()); |
0 |
| 5611 |
} |
--- |
5611 |
} |
--- |
| 5612 |
|
--- |
5612 |
|
--- |
| 5613 |
SDValue DAGCombiner::visitIMINMAX(SDNode *N) { |
0 |
5613 |
SDValue DAGCombiner::visitIMINMAX(SDNode *N) { |
0 |
| 5614 |
SDValue N0 = N->getOperand(0); |
0 |
5614 |
SDValue N0 = N->getOperand(0); |
0 |
| 5615 |
SDValue N1 = N->getOperand(1); |
0 |
5615 |
SDValue N1 = N->getOperand(1); |
0 |
| 5616 |
EVT VT = N0.getValueType(); |
0 |
5616 |
EVT VT = N0.getValueType(); |
0 |
| 5617 |
unsigned Opcode = N->getOpcode(); |
0 |
5617 |
unsigned Opcode = N->getOpcode(); |
0 |
| 5618 |
SDLoc DL(N); |
0 |
5618 |
SDLoc DL(N); |
0 |
| 5619 |
|
--- |
5619 |
|
--- |
| 5620 |
// fold operation with constant operands. |
--- |
5620 |
// fold operation with constant operands. |
--- |
| 5621 |
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1})) |
0 |
5621 |
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1})) |
0 |
| 5622 |
return C; |
0 |
5622 |
return C; |
0 |
| 5623 |
|
--- |
5623 |
|
--- |
| 5624 |
// If the operands are the same, this is a no-op. |
--- |
5624 |
// If the operands are the same, this is a no-op. |
--- |
| 5625 |
if (N0 == N1) |
0 |
5625 |
if (N0 == N1) |
0 |
| 5626 |
return N0; |
0 |
5626 |
return N0; |
0 |
| 5627 |
|
--- |
5627 |
|
--- |
| 5628 |
// canonicalize constant to RHS |
--- |
5628 |
// canonicalize constant to RHS |
--- |
| 5629 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
5629 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 5630 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
5630 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 5631 |
return DAG.getNode(Opcode, DL, VT, N1, N0); |
0 |
5631 |
return DAG.getNode(Opcode, DL, VT, N1, N0); |
0 |
| 5632 |
|
--- |
5632 |
|
--- |
| 5633 |
// fold vector ops |
--- |
5633 |
// fold vector ops |
--- |
| 5634 |
if (VT.isVector()) |
0 |
5634 |
if (VT.isVector()) |
0 |
| 5635 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
5635 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 5636 |
return FoldedVOp; |
0 |
5636 |
return FoldedVOp; |
0 |
| 5637 |
|
--- |
5637 |
|
--- |
| 5638 |
// Is sign bits are zero, flip between UMIN/UMAX and SMIN/SMAX. |
--- |
5638 |
// Is sign bits are zero, flip between UMIN/UMAX and SMIN/SMAX. |
--- |
| 5639 |
// Only do this if the current op isn't legal and the flipped is. |
--- |
5639 |
// Only do this if the current op isn't legal and the flipped is. |
--- |
| 5640 |
if (!TLI.isOperationLegal(Opcode, VT) && |
0 |
5640 |
if (!TLI.isOperationLegal(Opcode, VT) && |
0 |
| 5641 |
(N0.isUndef() || DAG.SignBitIsZero(N0)) && |
0 |
5641 |
(N0.isUndef() || DAG.SignBitIsZero(N0)) && |
0 |
| 5642 |
(N1.isUndef() || DAG.SignBitIsZero(N1))) { |
0 |
5642 |
(N1.isUndef() || DAG.SignBitIsZero(N1))) { |
0 |
| 5643 |
unsigned AltOpcode; |
--- |
5643 |
unsigned AltOpcode; |
--- |
| 5644 |
switch (Opcode) { |
0 |
5644 |
switch (Opcode) { |
0 |
| 5645 |
case ISD::SMIN: AltOpcode = ISD::UMIN; break; |
0 |
5645 |
case ISD::SMIN: AltOpcode = ISD::UMIN; break; |
0 |
| 5646 |
case ISD::SMAX: AltOpcode = ISD::UMAX; break; |
0 |
5646 |
case ISD::SMAX: AltOpcode = ISD::UMAX; break; |
0 |
| 5647 |
case ISD::UMIN: AltOpcode = ISD::SMIN; break; |
0 |
5647 |
case ISD::UMIN: AltOpcode = ISD::SMIN; break; |
0 |
| 5648 |
case ISD::UMAX: AltOpcode = ISD::SMAX; break; |
0 |
5648 |
case ISD::UMAX: AltOpcode = ISD::SMAX; break; |
0 |
| 5649 |
default: llvm_unreachable("Unknown MINMAX opcode"); |
0 |
5649 |
default: llvm_unreachable("Unknown MINMAX opcode"); |
0 |
| 5650 |
} |
--- |
5650 |
} |
--- |
| 5651 |
if (TLI.isOperationLegal(AltOpcode, VT)) |
0 |
5651 |
if (TLI.isOperationLegal(AltOpcode, VT)) |
0 |
| 5652 |
return DAG.getNode(AltOpcode, DL, VT, N0, N1); |
0 |
5652 |
return DAG.getNode(AltOpcode, DL, VT, N0, N1); |
0 |
| 5653 |
} |
--- |
5653 |
} |
--- |
| 5654 |
|
--- |
5654 |
|
--- |
| 5655 |
if (Opcode == ISD::SMIN || Opcode == ISD::SMAX) |
0 |
5655 |
if (Opcode == ISD::SMIN || Opcode == ISD::SMAX) |
0 |
| 5656 |
if (SDValue S = PerformMinMaxFpToSatCombine( |
0 |
5656 |
if (SDValue S = PerformMinMaxFpToSatCombine( |
0 |
| 5657 |
N0, N1, N0, N1, Opcode == ISD::SMIN ? ISD::SETLT : ISD::SETGT, DAG)) |
0 |
5657 |
N0, N1, N0, N1, Opcode == ISD::SMIN ? ISD::SETLT : ISD::SETGT, DAG)) |
0 |
| 5658 |
return S; |
0 |
5658 |
return S; |
0 |
| 5659 |
if (Opcode == ISD::UMIN) |
0 |
5659 |
if (Opcode == ISD::UMIN) |
0 |
| 5660 |
if (SDValue S = PerformUMinFpToSatCombine(N0, N1, N0, N1, ISD::SETULT, DAG)) |
0 |
5660 |
if (SDValue S = PerformUMinFpToSatCombine(N0, N1, N0, N1, ISD::SETULT, DAG)) |
0 |
| 5661 |
return S; |
0 |
5661 |
return S; |
0 |
| 5662 |
|
--- |
5662 |
|
--- |
| 5663 |
// Fold min/max(vecreduce(x), vecreduce(y)) -> vecreduce(min/max(x, y)) |
--- |
5663 |
// Fold min/max(vecreduce(x), vecreduce(y)) -> vecreduce(min/max(x, y)) |
--- |
| 5664 |
auto ReductionOpcode = [](unsigned Opcode) { |
0 |
5664 |
auto ReductionOpcode = [](unsigned Opcode) { |
0 |
| 5665 |
switch (Opcode) { |
0 |
5665 |
switch (Opcode) { |
0 |
| 5666 |
case ISD::SMIN: |
0 |
5666 |
case ISD::SMIN: |
0 |
| 5667 |
return ISD::VECREDUCE_SMIN; |
0 |
5667 |
return ISD::VECREDUCE_SMIN; |
0 |
| 5668 |
case ISD::SMAX: |
0 |
5668 |
case ISD::SMAX: |
0 |
| 5669 |
return ISD::VECREDUCE_SMAX; |
0 |
5669 |
return ISD::VECREDUCE_SMAX; |
0 |
| 5670 |
case ISD::UMIN: |
0 |
5670 |
case ISD::UMIN: |
0 |
| 5671 |
return ISD::VECREDUCE_UMIN; |
0 |
5671 |
return ISD::VECREDUCE_UMIN; |
0 |
| 5672 |
case ISD::UMAX: |
0 |
5672 |
case ISD::UMAX: |
0 |
| 5673 |
return ISD::VECREDUCE_UMAX; |
0 |
5673 |
return ISD::VECREDUCE_UMAX; |
0 |
| 5674 |
default: |
0 |
5674 |
default: |
0 |
| 5675 |
llvm_unreachable("Unexpected opcode"); |
0 |
5675 |
llvm_unreachable("Unexpected opcode"); |
0 |
| 5676 |
} |
--- |
5676 |
} |
--- |
| 5677 |
}; |
--- |
5677 |
}; |
--- |
| 5678 |
if (SDValue SD = reassociateReduction(ReductionOpcode(Opcode), Opcode, |
0 |
5678 |
if (SDValue SD = reassociateReduction(ReductionOpcode(Opcode), Opcode, |
0 |
| 5679 |
SDLoc(N), VT, N0, N1)) |
0 |
5679 |
SDLoc(N), VT, N0, N1)) |
0 |
| 5680 |
return SD; |
0 |
5680 |
return SD; |
0 |
| 5681 |
|
--- |
5681 |
|
--- |
| 5682 |
// Simplify the operands using demanded-bits information. |
--- |
5682 |
// Simplify the operands using demanded-bits information. |
--- |
| 5683 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
5683 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
| 5684 |
return SDValue(N, 0); |
0 |
5684 |
return SDValue(N, 0); |
0 |
| 5685 |
|
--- |
5685 |
|
--- |
| 5686 |
return SDValue(); |
0 |
5686 |
return SDValue(); |
0 |
| 5687 |
} |
0 |
5687 |
} |
0 |
| 5688 |
|
--- |
5688 |
|
--- |
| 5689 |
/// If this is a bitwise logic instruction and both operands have the same |
--- |
5689 |
/// If this is a bitwise logic instruction and both operands have the same |
--- |
| 5690 |
/// opcode, try to sink the other opcode after the logic instruction. |
--- |
5690 |
/// opcode, try to sink the other opcode after the logic instruction. |
--- |
| 5691 |
SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) { |
0 |
5691 |
SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) { |
0 |
| 5692 |
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); |
0 |
5692 |
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); |
0 |
| 5693 |
EVT VT = N0.getValueType(); |
0 |
5693 |
EVT VT = N0.getValueType(); |
0 |
| 5694 |
unsigned LogicOpcode = N->getOpcode(); |
0 |
5694 |
unsigned LogicOpcode = N->getOpcode(); |
0 |
| 5695 |
unsigned HandOpcode = N0.getOpcode(); |
0 |
5695 |
unsigned HandOpcode = N0.getOpcode(); |
0 |
| 5696 |
assert(ISD::isBitwiseLogicOp(LogicOpcode) && "Expected logic opcode"); |
0 |
5696 |
assert(ISD::isBitwiseLogicOp(LogicOpcode) && "Expected logic opcode"); |
0 |
| 5697 |
assert(HandOpcode == N1.getOpcode() && "Bad input!"); |
0 |
5697 |
assert(HandOpcode == N1.getOpcode() && "Bad input!"); |
0 |
| 5698 |
|
--- |
5698 |
|
--- |
| 5699 |
// Bail early if none of these transforms apply. |
--- |
5699 |
// Bail early if none of these transforms apply. |
--- |
| 5700 |
if (N0.getNumOperands() == 0) |
0 |
5700 |
if (N0.getNumOperands() == 0) |
0 |
| 5701 |
return SDValue(); |
0 |
5701 |
return SDValue(); |
0 |
| 5702 |
|
--- |
5702 |
|
--- |
| 5703 |
// FIXME: We should check number of uses of the operands to not increase |
--- |
5703 |
// FIXME: We should check number of uses of the operands to not increase |
--- |
| 5704 |
// the instruction count for all transforms. |
--- |
5704 |
// the instruction count for all transforms. |
--- |
| 5705 |
|
--- |
5705 |
|
--- |
| 5706 |
// Handle size-changing casts (or sign_extend_inreg). |
--- |
5706 |
// Handle size-changing casts (or sign_extend_inreg). |
--- |
| 5707 |
SDValue X = N0.getOperand(0); |
0 |
5707 |
SDValue X = N0.getOperand(0); |
0 |
| 5708 |
SDValue Y = N1.getOperand(0); |
0 |
5708 |
SDValue Y = N1.getOperand(0); |
0 |
| 5709 |
EVT XVT = X.getValueType(); |
0 |
5709 |
EVT XVT = X.getValueType(); |
0 |
| 5710 |
SDLoc DL(N); |
0 |
5710 |
SDLoc DL(N); |
0 |
| 5711 |
if (ISD::isExtOpcode(HandOpcode) || ISD::isExtVecInRegOpcode(HandOpcode) || |
0 |
5711 |
if (ISD::isExtOpcode(HandOpcode) || ISD::isExtVecInRegOpcode(HandOpcode) || |
0 |
| 5712 |
(HandOpcode == ISD::SIGN_EXTEND_INREG && |
0 |
5712 |
(HandOpcode == ISD::SIGN_EXTEND_INREG && |
0 |
| 5713 |
N0.getOperand(1) == N1.getOperand(1))) { |
0 |
5713 |
N0.getOperand(1) == N1.getOperand(1))) { |
0 |
| 5714 |
// If both operands have other uses, this transform would create extra |
--- |
5714 |
// If both operands have other uses, this transform would create extra |
--- |
| 5715 |
// instructions without eliminating anything. |
--- |
5715 |
// instructions without eliminating anything. |
--- |
| 5716 |
if (!N0.hasOneUse() && !N1.hasOneUse()) |
0 |
5716 |
if (!N0.hasOneUse() && !N1.hasOneUse()) |
0 |
| 5717 |
return SDValue(); |
0 |
5717 |
return SDValue(); |
0 |
| 5718 |
// We need matching integer source types. |
--- |
5718 |
// We need matching integer source types. |
--- |
| 5719 |
if (XVT != Y.getValueType()) |
0 |
5719 |
if (XVT != Y.getValueType()) |
0 |
| 5720 |
return SDValue(); |
0 |
5720 |
return SDValue(); |
0 |
| 5721 |
// Don't create an illegal op during or after legalization. Don't ever |
--- |
5721 |
// Don't create an illegal op during or after legalization. Don't ever |
--- |
| 5722 |
// create an unsupported vector op. |
--- |
5722 |
// create an unsupported vector op. |
--- |
| 5723 |
if ((VT.isVector() || LegalOperations) && |
0 |
5723 |
if ((VT.isVector() || LegalOperations) && |
0 |
| 5724 |
!TLI.isOperationLegalOrCustom(LogicOpcode, XVT)) |
0 |
5724 |
!TLI.isOperationLegalOrCustom(LogicOpcode, XVT)) |
0 |
| 5725 |
return SDValue(); |
0 |
5725 |
return SDValue(); |
0 |
| 5726 |
// Avoid infinite looping with PromoteIntBinOp. |
--- |
5726 |
// Avoid infinite looping with PromoteIntBinOp. |
--- |
| 5727 |
// TODO: Should we apply desirable/legal constraints to all opcodes? |
--- |
5727 |
// TODO: Should we apply desirable/legal constraints to all opcodes? |
--- |
| 5728 |
if ((HandOpcode == ISD::ANY_EXTEND || |
0 |
5728 |
if ((HandOpcode == ISD::ANY_EXTEND || |
0 |
| 5729 |
HandOpcode == ISD::ANY_EXTEND_VECTOR_INREG) && |
0 |
5729 |
HandOpcode == ISD::ANY_EXTEND_VECTOR_INREG) && |
0 |
| 5730 |
LegalTypes && !TLI.isTypeDesirableForOp(LogicOpcode, XVT)) |
0 |
5730 |
LegalTypes && !TLI.isTypeDesirableForOp(LogicOpcode, XVT)) |
0 |
| 5731 |
return SDValue(); |
0 |
5731 |
return SDValue(); |
0 |
| 5732 |
// logic_op (hand_op X), (hand_op Y) --> hand_op (logic_op X, Y) |
--- |
5732 |
// logic_op (hand_op X), (hand_op Y) --> hand_op (logic_op X, Y) |
--- |
| 5733 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); |
0 |
5733 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); |
0 |
| 5734 |
if (HandOpcode == ISD::SIGN_EXTEND_INREG) |
0 |
5734 |
if (HandOpcode == ISD::SIGN_EXTEND_INREG) |
0 |
| 5735 |
return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1)); |
0 |
5735 |
return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1)); |
0 |
| 5736 |
return DAG.getNode(HandOpcode, DL, VT, Logic); |
0 |
5736 |
return DAG.getNode(HandOpcode, DL, VT, Logic); |
0 |
| 5737 |
} |
--- |
5737 |
} |
--- |
| 5738 |
|
--- |
5738 |
|
--- |
| 5739 |
// logic_op (truncate x), (truncate y) --> truncate (logic_op x, y) |
--- |
5739 |
// logic_op (truncate x), (truncate y) --> truncate (logic_op x, y) |
--- |
| 5740 |
if (HandOpcode == ISD::TRUNCATE) { |
0 |
5740 |
if (HandOpcode == ISD::TRUNCATE) { |
0 |
| 5741 |
// If both operands have other uses, this transform would create extra |
--- |
5741 |
// If both operands have other uses, this transform would create extra |
--- |
| 5742 |
// instructions without eliminating anything. |
--- |
5742 |
// instructions without eliminating anything. |
--- |
| 5743 |
if (!N0.hasOneUse() && !N1.hasOneUse()) |
0 |
5743 |
if (!N0.hasOneUse() && !N1.hasOneUse()) |
0 |
| 5744 |
return SDValue(); |
0 |
5744 |
return SDValue(); |
0 |
| 5745 |
// We need matching source types. |
--- |
5745 |
// We need matching source types. |
--- |
| 5746 |
if (XVT != Y.getValueType()) |
0 |
5746 |
if (XVT != Y.getValueType()) |
0 |
| 5747 |
return SDValue(); |
0 |
5747 |
return SDValue(); |
0 |
| 5748 |
// Don't create an illegal op during or after legalization. |
--- |
5748 |
// Don't create an illegal op during or after legalization. |
--- |
| 5749 |
if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT)) |
0 |
5749 |
if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT)) |
0 |
| 5750 |
return SDValue(); |
0 |
5750 |
return SDValue(); |
0 |
| 5751 |
// Be extra careful sinking truncate. If it's free, there's no benefit in |
--- |
5751 |
// Be extra careful sinking truncate. If it's free, there's no benefit in |
--- |
| 5752 |
// widening a binop. Also, don't create a logic op on an illegal type. |
--- |
5752 |
// widening a binop. Also, don't create a logic op on an illegal type. |
--- |
| 5753 |
if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT)) |
0 |
5753 |
if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT)) |
0 |
| 5754 |
return SDValue(); |
0 |
5754 |
return SDValue(); |
0 |
| 5755 |
if (!TLI.isTypeLegal(XVT)) |
0 |
5755 |
if (!TLI.isTypeLegal(XVT)) |
0 |
| 5756 |
return SDValue(); |
0 |
5756 |
return SDValue(); |
0 |
| 5757 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); |
0 |
5757 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); |
0 |
| 5758 |
return DAG.getNode(HandOpcode, DL, VT, Logic); |
0 |
5758 |
return DAG.getNode(HandOpcode, DL, VT, Logic); |
0 |
| 5759 |
} |
--- |
5759 |
} |
--- |
| 5760 |
|
--- |
5760 |
|
--- |
| 5761 |
// For binops SHL/SRL/SRA/AND: |
--- |
5761 |
// For binops SHL/SRL/SRA/AND: |
--- |
| 5762 |
// logic_op (OP x, z), (OP y, z) --> OP (logic_op x, y), z |
--- |
5762 |
// logic_op (OP x, z), (OP y, z) --> OP (logic_op x, y), z |
--- |
| 5763 |
if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL || |
0 |
5763 |
if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL || |
0 |
| 5764 |
HandOpcode == ISD::SRA || HandOpcode == ISD::AND) && |
0 |
5764 |
HandOpcode == ISD::SRA || HandOpcode == ISD::AND) && |
0 |
| 5765 |
N0.getOperand(1) == N1.getOperand(1)) { |
0 |
5765 |
N0.getOperand(1) == N1.getOperand(1)) { |
0 |
| 5766 |
// If either operand has other uses, this transform is not an improvement. |
--- |
5766 |
// If either operand has other uses, this transform is not an improvement. |
--- |
| 5767 |
if (!N0.hasOneUse() || !N1.hasOneUse()) |
0 |
5767 |
if (!N0.hasOneUse() || !N1.hasOneUse()) |
0 |
| 5768 |
return SDValue(); |
0 |
5768 |
return SDValue(); |
0 |
| 5769 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); |
0 |
5769 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); |
0 |
| 5770 |
return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1)); |
0 |
5770 |
return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1)); |
0 |
| 5771 |
} |
--- |
5771 |
} |
--- |
| 5772 |
|
--- |
5772 |
|
--- |
| 5773 |
// Unary ops: logic_op (bswap x), (bswap y) --> bswap (logic_op x, y) |
--- |
5773 |
// Unary ops: logic_op (bswap x), (bswap y) --> bswap (logic_op x, y) |
--- |
| 5774 |
if (HandOpcode == ISD::BSWAP) { |
0 |
5774 |
if (HandOpcode == ISD::BSWAP) { |
0 |
| 5775 |
// If either operand has other uses, this transform is not an improvement. |
--- |
5775 |
// If either operand has other uses, this transform is not an improvement. |
--- |
| 5776 |
if (!N0.hasOneUse() || !N1.hasOneUse()) |
0 |
5776 |
if (!N0.hasOneUse() || !N1.hasOneUse()) |
0 |
| 5777 |
return SDValue(); |
0 |
5777 |
return SDValue(); |
0 |
| 5778 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); |
0 |
5778 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); |
0 |
| 5779 |
return DAG.getNode(HandOpcode, DL, VT, Logic); |
0 |
5779 |
return DAG.getNode(HandOpcode, DL, VT, Logic); |
0 |
| 5780 |
} |
--- |
5780 |
} |
--- |
| 5781 |
|
--- |
5781 |
|
--- |
| 5782 |
// For funnel shifts FSHL/FSHR: |
--- |
5782 |
// For funnel shifts FSHL/FSHR: |
--- |
| 5783 |
// logic_op (OP x, x1, s), (OP y, y1, s) --> |
--- |
5783 |
// logic_op (OP x, x1, s), (OP y, y1, s) --> |
--- |
| 5784 |
// --> OP (logic_op x, y), (logic_op, x1, y1), s |
--- |
5784 |
// --> OP (logic_op x, y), (logic_op, x1, y1), s |
--- |
| 5785 |
if ((HandOpcode == ISD::FSHL || HandOpcode == ISD::FSHR) && |
0 |
5785 |
if ((HandOpcode == ISD::FSHL || HandOpcode == ISD::FSHR) && |
0 |
| 5786 |
N0.getOperand(2) == N1.getOperand(2)) { |
0 |
5786 |
N0.getOperand(2) == N1.getOperand(2)) { |
0 |
| 5787 |
if (!N0.hasOneUse() || !N1.hasOneUse()) |
0 |
5787 |
if (!N0.hasOneUse() || !N1.hasOneUse()) |
0 |
| 5788 |
return SDValue(); |
0 |
5788 |
return SDValue(); |
0 |
| 5789 |
SDValue X1 = N0.getOperand(1); |
0 |
5789 |
SDValue X1 = N0.getOperand(1); |
0 |
| 5790 |
SDValue Y1 = N1.getOperand(1); |
0 |
5790 |
SDValue Y1 = N1.getOperand(1); |
0 |
| 5791 |
SDValue S = N0.getOperand(2); |
0 |
5791 |
SDValue S = N0.getOperand(2); |
0 |
| 5792 |
SDValue Logic0 = DAG.getNode(LogicOpcode, DL, VT, X, Y); |
0 |
5792 |
SDValue Logic0 = DAG.getNode(LogicOpcode, DL, VT, X, Y); |
0 |
| 5793 |
SDValue Logic1 = DAG.getNode(LogicOpcode, DL, VT, X1, Y1); |
0 |
5793 |
SDValue Logic1 = DAG.getNode(LogicOpcode, DL, VT, X1, Y1); |
0 |
| 5794 |
return DAG.getNode(HandOpcode, DL, VT, Logic0, Logic1, S); |
0 |
5794 |
return DAG.getNode(HandOpcode, DL, VT, Logic0, Logic1, S); |
0 |
| 5795 |
} |
--- |
5795 |
} |
--- |
| 5796 |
|
--- |
5796 |
|
--- |
| 5797 |
// Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) |
--- |
5797 |
// Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) |
--- |
| 5798 |
// Only perform this optimization up until type legalization, before |
--- |
5798 |
// Only perform this optimization up until type legalization, before |
--- |
| 5799 |
// LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by |
--- |
5799 |
// LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by |
--- |
| 5800 |
// adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and |
--- |
5800 |
// adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and |
--- |
| 5801 |
// we don't want to undo this promotion. |
--- |
5801 |
// we don't want to undo this promotion. |
--- |
| 5802 |
// We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper |
--- |
5802 |
// We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper |
--- |
| 5803 |
// on scalars. |
--- |
5803 |
// on scalars. |
--- |
| 5804 |
if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) && |
0 |
5804 |
if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) && |
0 |
| 5805 |
Level <= AfterLegalizeTypes) { |
0 |
5805 |
Level <= AfterLegalizeTypes) { |
0 |
| 5806 |
// Input types must be integer and the same. |
--- |
5806 |
// Input types must be integer and the same. |
--- |
| 5807 |
if (XVT.isInteger() && XVT == Y.getValueType() && |
0 |
5807 |
if (XVT.isInteger() && XVT == Y.getValueType() && |
0 |
| 5808 |
!(VT.isVector() && TLI.isTypeLegal(VT) && |
0 |
5808 |
!(VT.isVector() && TLI.isTypeLegal(VT) && |
0 |
| 5809 |
!XVT.isVector() && !TLI.isTypeLegal(XVT))) { |
0 |
5809 |
!XVT.isVector() && !TLI.isTypeLegal(XVT))) { |
0 |
| 5810 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); |
0 |
5810 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); |
0 |
| 5811 |
return DAG.getNode(HandOpcode, DL, VT, Logic); |
0 |
5811 |
return DAG.getNode(HandOpcode, DL, VT, Logic); |
0 |
| 5812 |
} |
--- |
5812 |
} |
--- |
| 5813 |
} |
--- |
5813 |
} |
--- |
| 5814 |
|
--- |
5814 |
|
--- |
| 5815 |
// Xor/and/or are indifferent to the swizzle operation (shuffle of one value). |
--- |
5815 |
// Xor/and/or are indifferent to the swizzle operation (shuffle of one value). |
--- |
| 5816 |
// Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) |
--- |
5816 |
// Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) |
--- |
| 5817 |
// If both shuffles use the same mask, and both shuffle within a single |
--- |
5817 |
// If both shuffles use the same mask, and both shuffle within a single |
--- |
| 5818 |
// vector, then it is worthwhile to move the swizzle after the operation. |
--- |
5818 |
// vector, then it is worthwhile to move the swizzle after the operation. |
--- |
| 5819 |
// The type-legalizer generates this pattern when loading illegal |
--- |
5819 |
// The type-legalizer generates this pattern when loading illegal |
--- |
| 5820 |
// vector types from memory. In many cases this allows additional shuffle |
--- |
5820 |
// vector types from memory. In many cases this allows additional shuffle |
--- |
| 5821 |
// optimizations. |
--- |
5821 |
// optimizations. |
--- |
| 5822 |
// There are other cases where moving the shuffle after the xor/and/or |
--- |
5822 |
// There are other cases where moving the shuffle after the xor/and/or |
--- |
| 5823 |
// is profitable even if shuffles don't perform a swizzle. |
--- |
5823 |
// is profitable even if shuffles don't perform a swizzle. |
--- |
| 5824 |
// If both shuffles use the same mask, and both shuffles have the same first |
--- |
5824 |
// If both shuffles use the same mask, and both shuffles have the same first |
--- |
| 5825 |
// or second operand, then it might still be profitable to move the shuffle |
--- |
5825 |
// or second operand, then it might still be profitable to move the shuffle |
--- |
| 5826 |
// after the xor/and/or operation. |
--- |
5826 |
// after the xor/and/or operation. |
--- |
| 5827 |
if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) { |
0 |
5827 |
if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) { |
0 |
| 5828 |
auto *SVN0 = cast(N0); |
0 |
5828 |
auto *SVN0 = cast(N0); |
0 |
| 5829 |
auto *SVN1 = cast(N1); |
0 |
5829 |
auto *SVN1 = cast(N1); |
0 |
| 5830 |
assert(X.getValueType() == Y.getValueType() && |
0 |
5830 |
assert(X.getValueType() == Y.getValueType() && |
0 |
| 5831 |
"Inputs to shuffles are not the same type"); |
--- |
5831 |
"Inputs to shuffles are not the same type"); |
--- |
| 5832 |
|
--- |
5832 |
|
--- |
| 5833 |
// Check that both shuffles use the same mask. The masks are known to be of |
--- |
5833 |
// Check that both shuffles use the same mask. The masks are known to be of |
--- |
| 5834 |
// the same length because the result vector type is the same. |
--- |
5834 |
// the same length because the result vector type is the same. |
--- |
| 5835 |
// Check also that shuffles have only one use to avoid introducing extra |
--- |
5835 |
// Check also that shuffles have only one use to avoid introducing extra |
--- |
| 5836 |
// instructions. |
--- |
5836 |
// instructions. |
--- |
| 5837 |
if (!SVN0->hasOneUse() || !SVN1->hasOneUse() || |
0 |
5837 |
if (!SVN0->hasOneUse() || !SVN1->hasOneUse() || |
0 |
| 5838 |
!SVN0->getMask().equals(SVN1->getMask())) |
0 |
5838 |
!SVN0->getMask().equals(SVN1->getMask())) |
0 |
| 5839 |
return SDValue(); |
0 |
5839 |
return SDValue(); |
0 |
| 5840 |
|
--- |
5840 |
|
--- |
| 5841 |
// Don't try to fold this node if it requires introducing a |
--- |
5841 |
// Don't try to fold this node if it requires introducing a |
--- |
| 5842 |
// build vector of all zeros that might be illegal at this stage. |
--- |
5842 |
// build vector of all zeros that might be illegal at this stage. |
--- |
| 5843 |
SDValue ShOp = N0.getOperand(1); |
0 |
5843 |
SDValue ShOp = N0.getOperand(1); |
0 |
| 5844 |
if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) |
0 |
5844 |
if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) |
0 |
| 5845 |
ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); |
0 |
5845 |
ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); |
0 |
| 5846 |
|
--- |
5846 |
|
--- |
| 5847 |
// (logic_op (shuf (A, C), shuf (B, C))) --> shuf (logic_op (A, B), C) |
--- |
5847 |
// (logic_op (shuf (A, C), shuf (B, C))) --> shuf (logic_op (A, B), C) |
--- |
| 5848 |
if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) { |
0 |
5848 |
if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) { |
0 |
| 5849 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, |
0 |
5849 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, |
0 |
| 5850 |
N0.getOperand(0), N1.getOperand(0)); |
0 |
5850 |
N0.getOperand(0), N1.getOperand(0)); |
0 |
| 5851 |
return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask()); |
0 |
5851 |
return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask()); |
0 |
| 5852 |
} |
--- |
5852 |
} |
--- |
| 5853 |
|
--- |
5853 |
|
--- |
| 5854 |
// Don't try to fold this node if it requires introducing a |
--- |
5854 |
// Don't try to fold this node if it requires introducing a |
--- |
| 5855 |
// build vector of all zeros that might be illegal at this stage. |
--- |
5855 |
// build vector of all zeros that might be illegal at this stage. |
--- |
| 5856 |
ShOp = N0.getOperand(0); |
0 |
5856 |
ShOp = N0.getOperand(0); |
0 |
| 5857 |
if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) |
0 |
5857 |
if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) |
0 |
| 5858 |
ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); |
0 |
5858 |
ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); |
0 |
| 5859 |
|
--- |
5859 |
|
--- |
| 5860 |
// (logic_op (shuf (C, A), shuf (C, B))) --> shuf (C, logic_op (A, B)) |
--- |
5860 |
// (logic_op (shuf (C, A), shuf (C, B))) --> shuf (C, logic_op (A, B)) |
--- |
| 5861 |
if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) { |
0 |
5861 |
if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) { |
0 |
| 5862 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1), |
0 |
5862 |
SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1), |
0 |
| 5863 |
N1.getOperand(1)); |
0 |
5863 |
N1.getOperand(1)); |
0 |
| 5864 |
return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask()); |
0 |
5864 |
return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask()); |
0 |
| 5865 |
} |
--- |
5865 |
} |
--- |
| 5866 |
} |
--- |
5866 |
} |
--- |
| 5867 |
|
--- |
5867 |
|
--- |
| 5868 |
return SDValue(); |
0 |
5868 |
return SDValue(); |
0 |
| 5869 |
} |
0 |
5869 |
} |
0 |
| 5870 |
|
--- |
5870 |
|
--- |
| 5871 |
/// Try to make (and/or setcc (LL, LR), setcc (RL, RR)) more efficient. |
--- |
5871 |
/// Try to make (and/or setcc (LL, LR), setcc (RL, RR)) more efficient. |
--- |
| 5872 |
SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1, |
1 |
5872 |
SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1, |
1 |
| 5873 |
const SDLoc &DL) { |
--- |
5873 |
const SDLoc &DL) { |
--- |
| 5874 |
SDValue LL, LR, RL, RR, N0CC, N1CC; |
1 |
5874 |
SDValue LL, LR, RL, RR, N0CC, N1CC; |
1 |
| 5875 |
if (!isSetCCEquivalent(N0, LL, LR, N0CC) || |
2 |
5875 |
if (!isSetCCEquivalent(N0, LL, LR, N0CC) || |
2 |
| 5876 |
!isSetCCEquivalent(N1, RL, RR, N1CC)) |
1 |
5876 |
!isSetCCEquivalent(N1, RL, RR, N1CC)) |
1 |
| 5877 |
return SDValue(); |
1 |
5877 |
return SDValue(); |
1 |
| 5878 |
|
--- |
5878 |
|
--- |
| 5879 |
assert(N0.getValueType() == N1.getValueType() && |
0 |
5879 |
assert(N0.getValueType() == N1.getValueType() && |
0 |
| 5880 |
"Unexpected operand types for bitwise logic op"); |
--- |
5880 |
"Unexpected operand types for bitwise logic op"); |
--- |
| 5881 |
assert(LL.getValueType() == LR.getValueType() && |
0 |
5881 |
assert(LL.getValueType() == LR.getValueType() && |
0 |
| 5882 |
RL.getValueType() == RR.getValueType() && |
--- |
5882 |
RL.getValueType() == RR.getValueType() && |
--- |
| 5883 |
"Unexpected operand types for setcc"); |
--- |
5883 |
"Unexpected operand types for setcc"); |
--- |
| 5884 |
|
--- |
5884 |
|
--- |
| 5885 |
// If we're here post-legalization or the logic op type is not i1, the logic |
--- |
5885 |
// If we're here post-legalization or the logic op type is not i1, the logic |
--- |
| 5886 |
// op type must match a setcc result type. Also, all folds require new |
--- |
5886 |
// op type must match a setcc result type. Also, all folds require new |
--- |
| 5887 |
// operations on the left and right operands, so those types must match. |
--- |
5887 |
// operations on the left and right operands, so those types must match. |
--- |
| 5888 |
EVT VT = N0.getValueType(); |
0 |
5888 |
EVT VT = N0.getValueType(); |
0 |
| 5889 |
EVT OpVT = LL.getValueType(); |
0 |
5889 |
EVT OpVT = LL.getValueType(); |
0 |
| 5890 |
if (LegalOperations || VT.getScalarType() != MVT::i1) |
0 |
5890 |
if (LegalOperations || VT.getScalarType() != MVT::i1) |
0 |
| 5891 |
if (VT != getSetCCResultType(OpVT)) |
0 |
5891 |
if (VT != getSetCCResultType(OpVT)) |
0 |
| 5892 |
return SDValue(); |
0 |
5892 |
return SDValue(); |
0 |
| 5893 |
if (OpVT != RL.getValueType()) |
0 |
5893 |
if (OpVT != RL.getValueType()) |
0 |
| 5894 |
return SDValue(); |
0 |
5894 |
return SDValue(); |
0 |
| 5895 |
|
--- |
5895 |
|
--- |
| 5896 |
ISD::CondCode CC0 = cast(N0CC)->get(); |
0 |
5896 |
ISD::CondCode CC0 = cast(N0CC)->get(); |
0 |
| 5897 |
ISD::CondCode CC1 = cast(N1CC)->get(); |
0 |
5897 |
ISD::CondCode CC1 = cast(N1CC)->get(); |
0 |
| 5898 |
bool IsInteger = OpVT.isInteger(); |
0 |
5898 |
bool IsInteger = OpVT.isInteger(); |
0 |
| 5899 |
if (LR == RR && CC0 == CC1 && IsInteger) { |
0 |
5899 |
if (LR == RR && CC0 == CC1 && IsInteger) { |
0 |
| 5900 |
bool IsZero = isNullOrNullSplat(LR); |
0 |
5900 |
bool IsZero = isNullOrNullSplat(LR); |
0 |
| 5901 |
bool IsNeg1 = isAllOnesOrAllOnesSplat(LR); |
0 |
5901 |
bool IsNeg1 = isAllOnesOrAllOnesSplat(LR); |
0 |
| 5902 |
|
--- |
5902 |
|
--- |
| 5903 |
// All bits clear? |
--- |
5903 |
// All bits clear? |
--- |
| 5904 |
bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero; |
0 |
5904 |
bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero; |
0 |
| 5905 |
// All sign bits clear? |
--- |
5905 |
// All sign bits clear? |
--- |
| 5906 |
bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1; |
0 |
5906 |
bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1; |
0 |
| 5907 |
// Any bits set? |
--- |
5907 |
// Any bits set? |
--- |
| 5908 |
bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero; |
0 |
5908 |
bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero; |
0 |
| 5909 |
// Any sign bits set? |
--- |
5909 |
// Any sign bits set? |
--- |
| 5910 |
bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero; |
0 |
5910 |
bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero; |
0 |
| 5911 |
|
--- |
5911 |
|
--- |
| 5912 |
// (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0) |
--- |
5912 |
// (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0) |
--- |
| 5913 |
// (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1) |
--- |
5913 |
// (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1) |
--- |
| 5914 |
// (or (setne X, 0), (setne Y, 0)) --> (setne (or X, Y), 0) |
--- |
5914 |
// (or (setne X, 0), (setne Y, 0)) --> (setne (or X, Y), 0) |
--- |
| 5915 |
// (or (setlt X, 0), (setlt Y, 0)) --> (setlt (or X, Y), 0) |
--- |
5915 |
// (or (setlt X, 0), (setlt Y, 0)) --> (setlt (or X, Y), 0) |
--- |
| 5916 |
if (AndEqZero || AndGtNeg1 || OrNeZero || OrLtZero) { |
0 |
5916 |
if (AndEqZero || AndGtNeg1 || OrNeZero || OrLtZero) { |
0 |
| 5917 |
SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL); |
0 |
5917 |
SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL); |
0 |
| 5918 |
AddToWorklist(Or.getNode()); |
0 |
5918 |
AddToWorklist(Or.getNode()); |
0 |
| 5919 |
return DAG.getSetCC(DL, VT, Or, LR, CC1); |
0 |
5919 |
return DAG.getSetCC(DL, VT, Or, LR, CC1); |
0 |
| 5920 |
} |
--- |
5920 |
} |
--- |
| 5921 |
|
--- |
5921 |
|
--- |
| 5922 |
// All bits set? |
--- |
5922 |
// All bits set? |
--- |
| 5923 |
bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1; |
0 |
5923 |
bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1; |
0 |
| 5924 |
// All sign bits set? |
--- |
5924 |
// All sign bits set? |
--- |
| 5925 |
bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero; |
0 |
5925 |
bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero; |
0 |
| 5926 |
// Any bits clear? |
--- |
5926 |
// Any bits clear? |
--- |
| 5927 |
bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1; |
0 |
5927 |
bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1; |
0 |
| 5928 |
// Any sign bits clear? |
--- |
5928 |
// Any sign bits clear? |
--- |
| 5929 |
bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1; |
0 |
5929 |
bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1; |
0 |
| 5930 |
|
--- |
5930 |
|
--- |
| 5931 |
// (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1) |
--- |
5931 |
// (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1) |
--- |
| 5932 |
// (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0) |
--- |
5932 |
// (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0) |
--- |
| 5933 |
// (or (setne X, -1), (setne Y, -1)) --> (setne (and X, Y), -1) |
--- |
5933 |
// (or (setne X, -1), (setne Y, -1)) --> (setne (and X, Y), -1) |
--- |
| 5934 |
// (or (setgt X, -1), (setgt Y -1)) --> (setgt (and X, Y), -1) |
--- |
5934 |
// (or (setgt X, -1), (setgt Y -1)) --> (setgt (and X, Y), -1) |
--- |
| 5935 |
if (AndEqNeg1 || AndLtZero || OrNeNeg1 || OrGtNeg1) { |
0 |
5935 |
if (AndEqNeg1 || AndLtZero || OrNeNeg1 || OrGtNeg1) { |
0 |
| 5936 |
SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL); |
0 |
5936 |
SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL); |
0 |
| 5937 |
AddToWorklist(And.getNode()); |
0 |
5937 |
AddToWorklist(And.getNode()); |
0 |
| 5938 |
return DAG.getSetCC(DL, VT, And, LR, CC1); |
0 |
5938 |
return DAG.getSetCC(DL, VT, And, LR, CC1); |
0 |
| 5939 |
} |
--- |
5939 |
} |
--- |
| 5940 |
} |
--- |
5940 |
} |
--- |
| 5941 |
|
--- |
5941 |
|
--- |
| 5942 |
// TODO: What is the 'or' equivalent of this fold? |
--- |
5942 |
// TODO: What is the 'or' equivalent of this fold? |
--- |
| 5943 |
// (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2) |
--- |
5943 |
// (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2) |
--- |
| 5944 |
if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 && |
0 |
5944 |
if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 && |
0 |
| 5945 |
IsInteger && CC0 == ISD::SETNE && |
0 |
5945 |
IsInteger && CC0 == ISD::SETNE && |
0 |
| 5946 |
((isNullConstant(LR) && isAllOnesConstant(RR)) || |
0 |
5946 |
((isNullConstant(LR) && isAllOnesConstant(RR)) || |
0 |
| 5947 |
(isAllOnesConstant(LR) && isNullConstant(RR)))) { |
0 |
5947 |
(isAllOnesConstant(LR) && isNullConstant(RR)))) { |
0 |
| 5948 |
SDValue One = DAG.getConstant(1, DL, OpVT); |
0 |
5948 |
SDValue One = DAG.getConstant(1, DL, OpVT); |
0 |
| 5949 |
SDValue Two = DAG.getConstant(2, DL, OpVT); |
0 |
5949 |
SDValue Two = DAG.getConstant(2, DL, OpVT); |
0 |
| 5950 |
SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One); |
0 |
5950 |
SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One); |
0 |
| 5951 |
AddToWorklist(Add.getNode()); |
0 |
5951 |
AddToWorklist(Add.getNode()); |
0 |
| 5952 |
return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE); |
0 |
5952 |
return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE); |
0 |
| 5953 |
} |
--- |
5953 |
} |
--- |
| 5954 |
|
--- |
5954 |
|
--- |
| 5955 |
// Try more general transforms if the predicates match and the only user of |
--- |
5955 |
// Try more general transforms if the predicates match and the only user of |
--- |
| 5956 |
// the compares is the 'and' or 'or'. |
--- |
5956 |
// the compares is the 'and' or 'or'. |
--- |
| 5957 |
if (IsInteger && TLI.convertSetCCLogicToBitwiseLogic(OpVT) && CC0 == CC1 && |
0 |
5957 |
if (IsInteger && TLI.convertSetCCLogicToBitwiseLogic(OpVT) && CC0 == CC1 && |
0 |
| 5958 |
N0.hasOneUse() && N1.hasOneUse()) { |
0 |
5958 |
N0.hasOneUse() && N1.hasOneUse()) { |
0 |
| 5959 |
// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0 |
--- |
5959 |
// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0 |
--- |
| 5960 |
// or (setne A, B), (setne C, D) --> setne (or (xor A, B), (xor C, D)), 0 |
--- |
5960 |
// or (setne A, B), (setne C, D) --> setne (or (xor A, B), (xor C, D)), 0 |
--- |
| 5961 |
if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) { |
0 |
5961 |
if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) { |
0 |
| 5962 |
SDValue XorL = DAG.getNode(ISD::XOR, SDLoc(N0), OpVT, LL, LR); |
0 |
5962 |
SDValue XorL = DAG.getNode(ISD::XOR, SDLoc(N0), OpVT, LL, LR); |
0 |
| 5963 |
SDValue XorR = DAG.getNode(ISD::XOR, SDLoc(N1), OpVT, RL, RR); |
0 |
5963 |
SDValue XorR = DAG.getNode(ISD::XOR, SDLoc(N1), OpVT, RL, RR); |
0 |
| 5964 |
SDValue Or = DAG.getNode(ISD::OR, DL, OpVT, XorL, XorR); |
0 |
5964 |
SDValue Or = DAG.getNode(ISD::OR, DL, OpVT, XorL, XorR); |
0 |
| 5965 |
SDValue Zero = DAG.getConstant(0, DL, OpVT); |
0 |
5965 |
SDValue Zero = DAG.getConstant(0, DL, OpVT); |
0 |
| 5966 |
return DAG.getSetCC(DL, VT, Or, Zero, CC1); |
0 |
5966 |
return DAG.getSetCC(DL, VT, Or, Zero, CC1); |
0 |
| 5967 |
} |
--- |
5967 |
} |
--- |
| 5968 |
|
--- |
5968 |
|
--- |
| 5969 |
// Turn compare of constants whose difference is 1 bit into add+and+setcc. |
--- |
5969 |
// Turn compare of constants whose difference is 1 bit into add+and+setcc. |
--- |
| 5970 |
if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) { |
0 |
5970 |
if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) { |
0 |
| 5971 |
// Match a shared variable operand and 2 non-opaque constant operands. |
--- |
5971 |
// Match a shared variable operand and 2 non-opaque constant operands. |
--- |
| 5972 |
auto MatchDiffPow2 = [&](ConstantSDNode *C0, ConstantSDNode *C1) { |
0 |
5972 |
auto MatchDiffPow2 = [&](ConstantSDNode *C0, ConstantSDNode *C1) { |
0 |
| 5973 |
// The difference of the constants must be a single bit. |
--- |
5973 |
// The difference of the constants must be a single bit. |
--- |
| 5974 |
const APInt &CMax = |
--- |
5974 |
const APInt &CMax = |
--- |
| 5975 |
APIntOps::umax(C0->getAPIntValue(), C1->getAPIntValue()); |
0 |
5975 |
APIntOps::umax(C0->getAPIntValue(), C1->getAPIntValue()); |
0 |
| 5976 |
const APInt &CMin = |
--- |
5976 |
const APInt &CMin = |
--- |
| 5977 |
APIntOps::umin(C0->getAPIntValue(), C1->getAPIntValue()); |
0 |
5977 |
APIntOps::umin(C0->getAPIntValue(), C1->getAPIntValue()); |
0 |
| 5978 |
return !C0->isOpaque() && !C1->isOpaque() && (CMax - CMin).isPowerOf2(); |
0 |
5978 |
return !C0->isOpaque() && !C1->isOpaque() && (CMax - CMin).isPowerOf2(); |
0 |
| 5979 |
}; |
--- |
5979 |
}; |
--- |
| 5980 |
if (LL == RL && ISD::matchBinaryPredicate(LR, RR, MatchDiffPow2)) { |
0 |
5980 |
if (LL == RL && ISD::matchBinaryPredicate(LR, RR, MatchDiffPow2)) { |
0 |
| 5981 |
// and/or (setcc X, CMax, ne), (setcc X, CMin, ne/eq) --> |
--- |
5981 |
// and/or (setcc X, CMax, ne), (setcc X, CMin, ne/eq) --> |
--- |
| 5982 |
// setcc ((sub X, CMin), ~(CMax - CMin)), 0, ne/eq |
--- |
5982 |
// setcc ((sub X, CMin), ~(CMax - CMin)), 0, ne/eq |
--- |
| 5983 |
SDValue Max = DAG.getNode(ISD::UMAX, DL, OpVT, LR, RR); |
0 |
5983 |
SDValue Max = DAG.getNode(ISD::UMAX, DL, OpVT, LR, RR); |
0 |
| 5984 |
SDValue Min = DAG.getNode(ISD::UMIN, DL, OpVT, LR, RR); |
0 |
5984 |
SDValue Min = DAG.getNode(ISD::UMIN, DL, OpVT, LR, RR); |
0 |
| 5985 |
SDValue Offset = DAG.getNode(ISD::SUB, DL, OpVT, LL, Min); |
0 |
5985 |
SDValue Offset = DAG.getNode(ISD::SUB, DL, OpVT, LL, Min); |
0 |
| 5986 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, OpVT, Max, Min); |
0 |
5986 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, OpVT, Max, Min); |
0 |
| 5987 |
SDValue Mask = DAG.getNOT(DL, Diff, OpVT); |
0 |
5987 |
SDValue Mask = DAG.getNOT(DL, Diff, OpVT); |
0 |
| 5988 |
SDValue And = DAG.getNode(ISD::AND, DL, OpVT, Offset, Mask); |
0 |
5988 |
SDValue And = DAG.getNode(ISD::AND, DL, OpVT, Offset, Mask); |
0 |
| 5989 |
SDValue Zero = DAG.getConstant(0, DL, OpVT); |
0 |
5989 |
SDValue Zero = DAG.getConstant(0, DL, OpVT); |
0 |
| 5990 |
return DAG.getSetCC(DL, VT, And, Zero, CC0); |
0 |
5990 |
return DAG.getSetCC(DL, VT, And, Zero, CC0); |
0 |
| 5991 |
} |
--- |
5991 |
} |
--- |
| 5992 |
} |
--- |
5992 |
} |
--- |
| 5993 |
} |
--- |
5993 |
} |
--- |
| 5994 |
|
--- |
5994 |
|
--- |
| 5995 |
// Canonicalize equivalent operands to LL == RL. |
--- |
5995 |
// Canonicalize equivalent operands to LL == RL. |
--- |
| 5996 |
if (LL == RR && LR == RL) { |
0 |
5996 |
if (LL == RR && LR == RL) { |
0 |
| 5997 |
CC1 = ISD::getSetCCSwappedOperands(CC1); |
0 |
5997 |
CC1 = ISD::getSetCCSwappedOperands(CC1); |
0 |
| 5998 |
std::swap(RL, RR); |
0 |
5998 |
std::swap(RL, RR); |
0 |
| 5999 |
} |
--- |
5999 |
} |
--- |
| 6000 |
|
--- |
6000 |
|
--- |
| 6001 |
// (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC) |
--- |
6001 |
// (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC) |
--- |
| 6002 |
// (or (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC) |
--- |
6002 |
// (or (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC) |
--- |
| 6003 |
if (LL == RL && LR == RR) { |
0 |
6003 |
if (LL == RL && LR == RR) { |
0 |
| 6004 |
ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, OpVT) |
0 |
6004 |
ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, OpVT) |
0 |
| 6005 |
: ISD::getSetCCOrOperation(CC0, CC1, OpVT); |
0 |
6005 |
: ISD::getSetCCOrOperation(CC0, CC1, OpVT); |
0 |
| 6006 |
if (NewCC != ISD::SETCC_INVALID && |
0 |
6006 |
if (NewCC != ISD::SETCC_INVALID && |
0 |
| 6007 |
(!LegalOperations || |
0 |
6007 |
(!LegalOperations || |
0 |
| 6008 |
(TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) && |
0 |
6008 |
(TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) && |
0 |
| 6009 |
TLI.isOperationLegal(ISD::SETCC, OpVT)))) |
0 |
6009 |
TLI.isOperationLegal(ISD::SETCC, OpVT)))) |
0 |
| 6010 |
return DAG.getSetCC(DL, VT, LL, LR, NewCC); |
0 |
6010 |
return DAG.getSetCC(DL, VT, LL, LR, NewCC); |
0 |
| 6011 |
} |
--- |
6011 |
} |
--- |
| 6012 |
|
--- |
6012 |
|
--- |
| 6013 |
return SDValue(); |
0 |
6013 |
return SDValue(); |
0 |
| 6014 |
} |
--- |
6014 |
} |
--- |
| 6015 |
|
--- |
6015 |
|
--- |
| 6016 |
static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) { |
1 |
6016 |
static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) { |
1 |
| 6017 |
using AndOrSETCCFoldKind = TargetLowering::AndOrSETCCFoldKind; |
--- |
6017 |
using AndOrSETCCFoldKind = TargetLowering::AndOrSETCCFoldKind; |
--- |
| 6018 |
assert( |
1 |
6018 |
assert( |
1 |
| 6019 |
(LogicOp->getOpcode() == ISD::AND || LogicOp->getOpcode() == ISD::OR) && |
--- |
6019 |
(LogicOp->getOpcode() == ISD::AND || LogicOp->getOpcode() == ISD::OR) && |
--- |
| 6020 |
"Invalid Op to combine SETCC with"); |
--- |
6020 |
"Invalid Op to combine SETCC with"); |
--- |
| 6021 |
|
--- |
6021 |
|
--- |
| 6022 |
// TODO: Search past casts/truncates. |
--- |
6022 |
// TODO: Search past casts/truncates. |
--- |
| 6023 |
SDValue LHS = LogicOp->getOperand(0); |
1 |
6023 |
SDValue LHS = LogicOp->getOperand(0); |
1 |
| 6024 |
SDValue RHS = LogicOp->getOperand(1); |
1 |
6024 |
SDValue RHS = LogicOp->getOperand(1); |
1 |
| 6025 |
if (LHS->getOpcode() != ISD::SETCC || RHS->getOpcode() != ISD::SETCC || |
2 |
6025 |
if (LHS->getOpcode() != ISD::SETCC || RHS->getOpcode() != ISD::SETCC || |
2 |
| 6026 |
!LHS->hasOneUse() || !RHS->hasOneUse()) |
2 |
6026 |
!LHS->hasOneUse() || !RHS->hasOneUse()) |
2 |
| 6027 |
return SDValue(); |
1 |
6027 |
return SDValue(); |
1 |
| 6028 |
|
--- |
6028 |
|
--- |
| 6029 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
6029 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 6030 |
AndOrSETCCFoldKind TargetPreference = TLI.isDesirableToCombineLogicOpOfSETCC( |
0 |
6030 |
AndOrSETCCFoldKind TargetPreference = TLI.isDesirableToCombineLogicOpOfSETCC( |
0 |
| 6031 |
LogicOp, LHS.getNode(), RHS.getNode()); |
0 |
6031 |
LogicOp, LHS.getNode(), RHS.getNode()); |
0 |
| 6032 |
|
--- |
6032 |
|
--- |
| 6033 |
SDValue LHS0 = LHS->getOperand(0); |
0 |
6033 |
SDValue LHS0 = LHS->getOperand(0); |
0 |
| 6034 |
SDValue RHS0 = RHS->getOperand(0); |
0 |
6034 |
SDValue RHS0 = RHS->getOperand(0); |
0 |
| 6035 |
SDValue LHS1 = LHS->getOperand(1); |
0 |
6035 |
SDValue LHS1 = LHS->getOperand(1); |
0 |
| 6036 |
SDValue RHS1 = RHS->getOperand(1); |
0 |
6036 |
SDValue RHS1 = RHS->getOperand(1); |
0 |
| 6037 |
// TODO: We don't actually need a splat here, for vectors we just need the |
--- |
6037 |
// TODO: We don't actually need a splat here, for vectors we just need the |
--- |
| 6038 |
// invariants to hold for each element. |
--- |
6038 |
// invariants to hold for each element. |
--- |
| 6039 |
auto *LHS1C = isConstOrConstSplat(LHS1); |
0 |
6039 |
auto *LHS1C = isConstOrConstSplat(LHS1); |
0 |
| 6040 |
auto *RHS1C = isConstOrConstSplat(RHS1); |
0 |
6040 |
auto *RHS1C = isConstOrConstSplat(RHS1); |
0 |
| 6041 |
ISD::CondCode CCL = cast(LHS.getOperand(2))->get(); |
0 |
6041 |
ISD::CondCode CCL = cast(LHS.getOperand(2))->get(); |
0 |
| 6042 |
ISD::CondCode CCR = cast(RHS.getOperand(2))->get(); |
0 |
6042 |
ISD::CondCode CCR = cast(RHS.getOperand(2))->get(); |
0 |
| 6043 |
EVT VT = LogicOp->getValueType(0); |
0 |
6043 |
EVT VT = LogicOp->getValueType(0); |
0 |
| 6044 |
EVT OpVT = LHS0.getValueType(); |
0 |
6044 |
EVT OpVT = LHS0.getValueType(); |
0 |
| 6045 |
SDLoc DL(LogicOp); |
0 |
6045 |
SDLoc DL(LogicOp); |
0 |
| 6046 |
|
--- |
6046 |
|
--- |
| 6047 |
// Check if the operands of an and/or operation are comparisons and if they |
--- |
6047 |
// Check if the operands of an and/or operation are comparisons and if they |
--- |
| 6048 |
// compare against the same value. Replace the and/or-cmp-cmp sequence with |
--- |
6048 |
// compare against the same value. Replace the and/or-cmp-cmp sequence with |
--- |
| 6049 |
// min/max cmp sequence. If LHS1 is equal to RHS1, then the or-cmp-cmp |
--- |
6049 |
// min/max cmp sequence. If LHS1 is equal to RHS1, then the or-cmp-cmp |
--- |
| 6050 |
// sequence will be replaced with min-cmp sequence: |
--- |
6050 |
// sequence will be replaced with min-cmp sequence: |
--- |
| 6051 |
// (LHS0 < LHS1) | (RHS0 < RHS1) -> min(LHS0, RHS0) < LHS1 |
--- |
6051 |
// (LHS0 < LHS1) | (RHS0 < RHS1) -> min(LHS0, RHS0) < LHS1 |
--- |
| 6052 |
// and and-cmp-cmp will be replaced with max-cmp sequence: |
--- |
6052 |
// and and-cmp-cmp will be replaced with max-cmp sequence: |
--- |
| 6053 |
// (LHS0 < LHS1) & (RHS0 < RHS1) -> max(LHS0, RHS0) < LHS1 |
--- |
6053 |
// (LHS0 < LHS1) & (RHS0 < RHS1) -> max(LHS0, RHS0) < LHS1 |
--- |
| 6054 |
// The optimization does not work for `==` or `!=` . |
--- |
6054 |
// The optimization does not work for `==` or `!=` . |
--- |
| 6055 |
// The two comparisons should have either the same predicate or the |
--- |
6055 |
// The two comparisons should have either the same predicate or the |
--- |
| 6056 |
// predicate of one of the comparisons is the opposite of the other one. |
--- |
6056 |
// predicate of one of the comparisons is the opposite of the other one. |
--- |
| 6057 |
if (OpVT.isInteger() && !ISD::isIntEqualitySetCC(CCL) && |
0 |
6057 |
if (OpVT.isInteger() && !ISD::isIntEqualitySetCC(CCL) && |
0 |
| 6058 |
(CCL == CCR || CCL == ISD::getSetCCSwappedOperands(CCR)) && |
0 |
6058 |
(CCL == CCR || CCL == ISD::getSetCCSwappedOperands(CCR)) && |
0 |
| 6059 |
TLI.isOperationLegal(ISD::UMAX, OpVT) && |
0 |
6059 |
TLI.isOperationLegal(ISD::UMAX, OpVT) && |
0 |
| 6060 |
TLI.isOperationLegal(ISD::SMAX, OpVT) && |
0 |
6060 |
TLI.isOperationLegal(ISD::SMAX, OpVT) && |
0 |
| 6061 |
TLI.isOperationLegal(ISD::UMIN, OpVT) && |
0 |
6061 |
TLI.isOperationLegal(ISD::UMIN, OpVT) && |
0 |
| 6062 |
TLI.isOperationLegal(ISD::SMIN, OpVT)) { |
0 |
6062 |
TLI.isOperationLegal(ISD::SMIN, OpVT)) { |
0 |
| 6063 |
SDValue CommonValue, Operand1, Operand2; |
0 |
6063 |
SDValue CommonValue, Operand1, Operand2; |
0 |
| 6064 |
ISD::CondCode CC = ISD::SETCC_INVALID; |
0 |
6064 |
ISD::CondCode CC = ISD::SETCC_INVALID; |
0 |
| 6065 |
if (CCL == CCR) { |
0 |
6065 |
if (CCL == CCR) { |
0 |
| 6066 |
if (LHS0 == RHS0) { |
0 |
6066 |
if (LHS0 == RHS0) { |
0 |
| 6067 |
CommonValue = LHS0; |
0 |
6067 |
CommonValue = LHS0; |
0 |
| 6068 |
Operand1 = LHS1; |
0 |
6068 |
Operand1 = LHS1; |
0 |
| 6069 |
Operand2 = RHS1; |
0 |
6069 |
Operand2 = RHS1; |
0 |
| 6070 |
CC = ISD::getSetCCSwappedOperands(CCL); |
0 |
6070 |
CC = ISD::getSetCCSwappedOperands(CCL); |
0 |
| 6071 |
} else if (LHS1 == RHS1) { |
0 |
6071 |
} else if (LHS1 == RHS1) { |
0 |
| 6072 |
CommonValue = LHS1; |
0 |
6072 |
CommonValue = LHS1; |
0 |
| 6073 |
Operand1 = LHS0; |
0 |
6073 |
Operand1 = LHS0; |
0 |
| 6074 |
Operand2 = RHS0; |
0 |
6074 |
Operand2 = RHS0; |
0 |
| 6075 |
CC = CCL; |
0 |
6075 |
CC = CCL; |
0 |
| 6076 |
} |
--- |
6076 |
} |
--- |
| 6077 |
} else { |
--- |
6077 |
} else { |
--- |
| 6078 |
assert(CCL == ISD::getSetCCSwappedOperands(CCR) && "Unexpected CC"); |
0 |
6078 |
assert(CCL == ISD::getSetCCSwappedOperands(CCR) && "Unexpected CC"); |
0 |
| 6079 |
if (LHS0 == RHS1) { |
0 |
6079 |
if (LHS0 == RHS1) { |
0 |
| 6080 |
CommonValue = LHS0; |
0 |
6080 |
CommonValue = LHS0; |
0 |
| 6081 |
Operand1 = LHS1; |
0 |
6081 |
Operand1 = LHS1; |
0 |
| 6082 |
Operand2 = RHS0; |
0 |
6082 |
Operand2 = RHS0; |
0 |
| 6083 |
CC = CCR; |
0 |
6083 |
CC = CCR; |
0 |
| 6084 |
} else if (RHS0 == LHS1) { |
0 |
6084 |
} else if (RHS0 == LHS1) { |
0 |
| 6085 |
CommonValue = LHS1; |
0 |
6085 |
CommonValue = LHS1; |
0 |
| 6086 |
Operand1 = LHS0; |
0 |
6086 |
Operand1 = LHS0; |
0 |
| 6087 |
Operand2 = RHS1; |
0 |
6087 |
Operand2 = RHS1; |
0 |
| 6088 |
CC = CCL; |
0 |
6088 |
CC = CCL; |
0 |
| 6089 |
} |
--- |
6089 |
} |
--- |
| 6090 |
} |
--- |
6090 |
} |
--- |
| 6091 |
|
--- |
6091 |
|
--- |
| 6092 |
if (CC != ISD::SETCC_INVALID) { |
0 |
6092 |
if (CC != ISD::SETCC_INVALID) { |
0 |
| 6093 |
unsigned NewOpcode; |
--- |
6093 |
unsigned NewOpcode; |
--- |
| 6094 |
bool IsSigned = isSignedIntSetCC(CC); |
0 |
6094 |
bool IsSigned = isSignedIntSetCC(CC); |
0 |
| 6095 |
bool IsLess = (CC == ISD::SETLE || CC == ISD::SETULE || |
0 |
6095 |
bool IsLess = (CC == ISD::SETLE || CC == ISD::SETULE || |
0 |
| 6096 |
CC == ISD::SETLT || CC == ISD::SETULT); |
0 |
6096 |
CC == ISD::SETLT || CC == ISD::SETULT); |
0 |
| 6097 |
bool IsOr = (LogicOp->getOpcode() == ISD::OR); |
0 |
6097 |
bool IsOr = (LogicOp->getOpcode() == ISD::OR); |
0 |
| 6098 |
if (IsLess == IsOr) |
0 |
6098 |
if (IsLess == IsOr) |
0 |
| 6099 |
NewOpcode = IsSigned ? ISD::SMIN : ISD::UMIN; |
0 |
6099 |
NewOpcode = IsSigned ? ISD::SMIN : ISD::UMIN; |
0 |
| 6100 |
else |
--- |
6100 |
else |
--- |
| 6101 |
NewOpcode = IsSigned ? ISD::SMAX : ISD::UMAX; |
0 |
6101 |
NewOpcode = IsSigned ? ISD::SMAX : ISD::UMAX; |
0 |
| 6102 |
|
--- |
6102 |
|
--- |
| 6103 |
SDValue MinMaxValue = |
--- |
6103 |
SDValue MinMaxValue = |
--- |
| 6104 |
DAG.getNode(NewOpcode, DL, OpVT, Operand1, Operand2); |
0 |
6104 |
DAG.getNode(NewOpcode, DL, OpVT, Operand1, Operand2); |
0 |
| 6105 |
return DAG.getSetCC(DL, VT, MinMaxValue, CommonValue, CC); |
0 |
6105 |
return DAG.getSetCC(DL, VT, MinMaxValue, CommonValue, CC); |
0 |
| 6106 |
} |
--- |
6106 |
} |
--- |
| 6107 |
} |
--- |
6107 |
} |
--- |
| 6108 |
|
--- |
6108 |
|
--- |
| 6109 |
if (TargetPreference == AndOrSETCCFoldKind::None) |
0 |
6109 |
if (TargetPreference == AndOrSETCCFoldKind::None) |
0 |
| 6110 |
return SDValue(); |
0 |
6110 |
return SDValue(); |
0 |
| 6111 |
|
--- |
6111 |
|
--- |
| 6112 |
if (CCL == CCR && |
0 |
6112 |
if (CCL == CCR && |
0 |
| 6113 |
CCL == (LogicOp->getOpcode() == ISD::AND ? ISD::SETNE : ISD::SETEQ) && |
0 |
6113 |
CCL == (LogicOp->getOpcode() == ISD::AND ? ISD::SETNE : ISD::SETEQ) && |
0 |
| 6114 |
LHS0 == RHS0 && LHS1C && RHS1C && OpVT.isInteger()) { |
0 |
6114 |
LHS0 == RHS0 && LHS1C && RHS1C && OpVT.isInteger()) { |
0 |
| 6115 |
const APInt &APLhs = LHS1C->getAPIntValue(); |
0 |
6115 |
const APInt &APLhs = LHS1C->getAPIntValue(); |
0 |
| 6116 |
const APInt &APRhs = RHS1C->getAPIntValue(); |
0 |
6116 |
const APInt &APRhs = RHS1C->getAPIntValue(); |
0 |
| 6117 |
|
--- |
6117 |
|
--- |
| 6118 |
// Preference is to use ISD::ABS or we already have an ISD::ABS (in which |
--- |
6118 |
// Preference is to use ISD::ABS or we already have an ISD::ABS (in which |
--- |
| 6119 |
// case this is just a compare). |
--- |
6119 |
// case this is just a compare). |
--- |
| 6120 |
if (APLhs == (-APRhs) && |
0 |
6120 |
if (APLhs == (-APRhs) && |
0 |
| 6121 |
((TargetPreference & AndOrSETCCFoldKind::ABS) || |
0 |
6121 |
((TargetPreference & AndOrSETCCFoldKind::ABS) || |
0 |
| 6122 |
DAG.doesNodeExist(ISD::ABS, DAG.getVTList(OpVT), {LHS0}))) { |
0 |
6122 |
DAG.doesNodeExist(ISD::ABS, DAG.getVTList(OpVT), {LHS0}))) { |
0 |
| 6123 |
const APInt &C = APLhs.isNegative() ? APRhs : APLhs; |
0 |
6123 |
const APInt &C = APLhs.isNegative() ? APRhs : APLhs; |
0 |
| 6124 |
// (icmp eq A, C) | (icmp eq A, -C) |
--- |
6124 |
// (icmp eq A, C) | (icmp eq A, -C) |
--- |
| 6125 |
// -> (icmp eq Abs(A), C) |
--- |
6125 |
// -> (icmp eq Abs(A), C) |
--- |
| 6126 |
// (icmp ne A, C) & (icmp ne A, -C) |
--- |
6126 |
// (icmp ne A, C) & (icmp ne A, -C) |
--- |
| 6127 |
// -> (icmp ne Abs(A), C) |
--- |
6127 |
// -> (icmp ne Abs(A), C) |
--- |
| 6128 |
SDValue AbsOp = DAG.getNode(ISD::ABS, DL, OpVT, LHS0); |
0 |
6128 |
SDValue AbsOp = DAG.getNode(ISD::ABS, DL, OpVT, LHS0); |
0 |
| 6129 |
return DAG.getNode(ISD::SETCC, DL, VT, AbsOp, |
0 |
6129 |
return DAG.getNode(ISD::SETCC, DL, VT, AbsOp, |
0 |
| 6130 |
DAG.getConstant(C, DL, OpVT), LHS.getOperand(2)); |
0 |
6130 |
DAG.getConstant(C, DL, OpVT), LHS.getOperand(2)); |
0 |
| 6131 |
} else if (TargetPreference & |
0 |
6131 |
} else if (TargetPreference & |
0 |
| 6132 |
(AndOrSETCCFoldKind::AddAnd | AndOrSETCCFoldKind::NotAnd)) { |
--- |
6132 |
(AndOrSETCCFoldKind::AddAnd | AndOrSETCCFoldKind::NotAnd)) { |
--- |
| 6133 |
|
--- |
6133 |
|
--- |
| 6134 |
// AndOrSETCCFoldKind::AddAnd: |
--- |
6134 |
// AndOrSETCCFoldKind::AddAnd: |
--- |
| 6135 |
// A == C0 | A == C1 |
--- |
6135 |
// A == C0 | A == C1 |
--- |
| 6136 |
// IF IsPow2(smax(C0, C1)-smin(C0, C1)) |
--- |
6136 |
// IF IsPow2(smax(C0, C1)-smin(C0, C1)) |
--- |
| 6137 |
// -> ((A - smin(C0, C1)) & ~(smax(C0, C1)-smin(C0, C1))) == 0 |
--- |
6137 |
// -> ((A - smin(C0, C1)) & ~(smax(C0, C1)-smin(C0, C1))) == 0 |
--- |
| 6138 |
// A != C0 & A != C1 |
--- |
6138 |
// A != C0 & A != C1 |
--- |
| 6139 |
// IF IsPow2(smax(C0, C1)-smin(C0, C1)) |
--- |
6139 |
// IF IsPow2(smax(C0, C1)-smin(C0, C1)) |
--- |
| 6140 |
// -> ((A - smin(C0, C1)) & ~(smax(C0, C1)-smin(C0, C1))) != 0 |
--- |
6140 |
// -> ((A - smin(C0, C1)) & ~(smax(C0, C1)-smin(C0, C1))) != 0 |
--- |
| 6141 |
|
--- |
6141 |
|
--- |
| 6142 |
// AndOrSETCCFoldKind::NotAnd: |
--- |
6142 |
// AndOrSETCCFoldKind::NotAnd: |
--- |
| 6143 |
// A == C0 | A == C1 |
--- |
6143 |
// A == C0 | A == C1 |
--- |
| 6144 |
// IF smax(C0, C1) == -1 AND IsPow2(smax(C0, C1) - smin(C0, C1)) |
--- |
6144 |
// IF smax(C0, C1) == -1 AND IsPow2(smax(C0, C1) - smin(C0, C1)) |
--- |
| 6145 |
// -> ~A & smin(C0, C1) == 0 |
--- |
6145 |
// -> ~A & smin(C0, C1) == 0 |
--- |
| 6146 |
// A != C0 & A != C1 |
--- |
6146 |
// A != C0 & A != C1 |
--- |
| 6147 |
// IF smax(C0, C1) == -1 AND IsPow2(smax(C0, C1) - smin(C0, C1)) |
--- |
6147 |
// IF smax(C0, C1) == -1 AND IsPow2(smax(C0, C1) - smin(C0, C1)) |
--- |
| 6148 |
// -> ~A & smin(C0, C1) != 0 |
--- |
6148 |
// -> ~A & smin(C0, C1) != 0 |
--- |
| 6149 |
|
--- |
6149 |
|
--- |
| 6150 |
const APInt &MaxC = APIntOps::smax(APRhs, APLhs); |
0 |
6150 |
const APInt &MaxC = APIntOps::smax(APRhs, APLhs); |
0 |
| 6151 |
const APInt &MinC = APIntOps::smin(APRhs, APLhs); |
0 |
6151 |
const APInt &MinC = APIntOps::smin(APRhs, APLhs); |
0 |
| 6152 |
APInt Dif = MaxC - MinC; |
0 |
6152 |
APInt Dif = MaxC - MinC; |
0 |
| 6153 |
if (!Dif.isZero() && Dif.isPowerOf2()) { |
0 |
6153 |
if (!Dif.isZero() && Dif.isPowerOf2()) { |
0 |
| 6154 |
if (MaxC.isAllOnes() && |
0 |
6154 |
if (MaxC.isAllOnes() && |
0 |
| 6155 |
(TargetPreference & AndOrSETCCFoldKind::NotAnd)) { |
0 |
6155 |
(TargetPreference & AndOrSETCCFoldKind::NotAnd)) { |
0 |
| 6156 |
SDValue NotOp = DAG.getNOT(DL, LHS0, OpVT); |
0 |
6156 |
SDValue NotOp = DAG.getNOT(DL, LHS0, OpVT); |
0 |
| 6157 |
SDValue AndOp = DAG.getNode(ISD::AND, DL, OpVT, NotOp, |
0 |
6157 |
SDValue AndOp = DAG.getNode(ISD::AND, DL, OpVT, NotOp, |
0 |
| 6158 |
DAG.getConstant(MinC, DL, OpVT)); |
--- |
6158 |
DAG.getConstant(MinC, DL, OpVT)); |
--- |
| 6159 |
return DAG.getNode(ISD::SETCC, DL, VT, AndOp, |
0 |
6159 |
return DAG.getNode(ISD::SETCC, DL, VT, AndOp, |
0 |
| 6160 |
DAG.getConstant(0, DL, OpVT), LHS.getOperand(2)); |
0 |
6160 |
DAG.getConstant(0, DL, OpVT), LHS.getOperand(2)); |
0 |
| 6161 |
} else if (TargetPreference & AndOrSETCCFoldKind::AddAnd) { |
0 |
6161 |
} else if (TargetPreference & AndOrSETCCFoldKind::AddAnd) { |
0 |
| 6162 |
|
--- |
6162 |
|
--- |
| 6163 |
SDValue AddOp = DAG.getNode(ISD::ADD, DL, OpVT, LHS0, |
0 |
6163 |
SDValue AddOp = DAG.getNode(ISD::ADD, DL, OpVT, LHS0, |
0 |
| 6164 |
DAG.getConstant(-MinC, DL, OpVT)); |
0 |
6164 |
DAG.getConstant(-MinC, DL, OpVT)); |
0 |
| 6165 |
SDValue AndOp = DAG.getNode(ISD::AND, DL, OpVT, AddOp, |
0 |
6165 |
SDValue AndOp = DAG.getNode(ISD::AND, DL, OpVT, AddOp, |
0 |
| 6166 |
DAG.getConstant(~Dif, DL, OpVT)); |
0 |
6166 |
DAG.getConstant(~Dif, DL, OpVT)); |
0 |
| 6167 |
return DAG.getNode(ISD::SETCC, DL, VT, AndOp, |
0 |
6167 |
return DAG.getNode(ISD::SETCC, DL, VT, AndOp, |
0 |
| 6168 |
DAG.getConstant(0, DL, OpVT), LHS.getOperand(2)); |
0 |
6168 |
DAG.getConstant(0, DL, OpVT), LHS.getOperand(2)); |
0 |
| 6169 |
} |
--- |
6169 |
} |
--- |
| 6170 |
} |
--- |
6170 |
} |
--- |
| 6171 |
} |
0 |
6171 |
} |
0 |
| 6172 |
} |
--- |
6172 |
} |
--- |
| 6173 |
|
--- |
6173 |
|
--- |
| 6174 |
return SDValue(); |
0 |
6174 |
return SDValue(); |
0 |
| 6175 |
} |
0 |
6175 |
} |
0 |
| 6176 |
|
--- |
6176 |
|
--- |
| 6177 |
/// This contains all DAGCombine rules which reduce two values combined by |
--- |
6177 |
/// This contains all DAGCombine rules which reduce two values combined by |
--- |
| 6178 |
/// an And operation to a single value. This makes them reusable in the context |
--- |
6178 |
/// an And operation to a single value. This makes them reusable in the context |
--- |
| 6179 |
/// of visitSELECT(). Rules involving constants are not included as |
--- |
6179 |
/// of visitSELECT(). Rules involving constants are not included as |
--- |
| 6180 |
/// visitSELECT() already handles those cases. |
--- |
6180 |
/// visitSELECT() already handles those cases. |
--- |
| 6181 |
SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) { |
1 |
6181 |
SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) { |
1 |
| 6182 |
EVT VT = N1.getValueType(); |
1 |
6182 |
EVT VT = N1.getValueType(); |
1 |
| 6183 |
SDLoc DL(N); |
1 |
6183 |
SDLoc DL(N); |
1 |
| 6184 |
|
--- |
6184 |
|
--- |
| 6185 |
// fold (and x, undef) -> 0 |
--- |
6185 |
// fold (and x, undef) -> 0 |
--- |
| 6186 |
if (N0.isUndef() || N1.isUndef()) |
1 |
6186 |
if (N0.isUndef() || N1.isUndef()) |
1 |
| 6187 |
return DAG.getConstant(0, DL, VT); |
0 |
6187 |
return DAG.getConstant(0, DL, VT); |
0 |
| 6188 |
|
--- |
6188 |
|
--- |
| 6189 |
if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL)) |
1 |
6189 |
if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL)) |
1 |
| 6190 |
return V; |
0 |
6190 |
return V; |
0 |
| 6191 |
|
--- |
6191 |
|
--- |
| 6192 |
// Canonicalize: |
--- |
6192 |
// Canonicalize: |
--- |
| 6193 |
// and(x, add) -> and(add, x) |
--- |
6193 |
// and(x, add) -> and(add, x) |
--- |
| 6194 |
if (N1.getOpcode() == ISD::ADD) |
1 |
6194 |
if (N1.getOpcode() == ISD::ADD) |
1 |
| 6195 |
std::swap(N0, N1); |
0 |
6195 |
std::swap(N0, N1); |
0 |
| 6196 |
|
--- |
6196 |
|
--- |
| 6197 |
// TODO: Rewrite this to return a new 'AND' instead of using CombineTo. |
--- |
6197 |
// TODO: Rewrite this to return a new 'AND' instead of using CombineTo. |
--- |
| 6198 |
if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && |
1 |
6198 |
if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && |
1 |
| 6199 |
VT.getSizeInBits() <= 64 && N0->hasOneUse()) { |
1 |
6199 |
VT.getSizeInBits() <= 64 && N0->hasOneUse()) { |
1 |
| 6200 |
if (ConstantSDNode *ADDI = dyn_cast(N0.getOperand(1))) { |
0 |
6200 |
if (ConstantSDNode *ADDI = dyn_cast(N0.getOperand(1))) { |
0 |
| 6201 |
if (ConstantSDNode *SRLI = dyn_cast(N1.getOperand(1))) { |
0 |
6201 |
if (ConstantSDNode *SRLI = dyn_cast(N1.getOperand(1))) { |
0 |
| 6202 |
// Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal |
--- |
6202 |
// Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal |
--- |
| 6203 |
// immediate for an add, but it is legal if its top c2 bits are set, |
--- |
6203 |
// immediate for an add, but it is legal if its top c2 bits are set, |
--- |
| 6204 |
// transform the ADD so the immediate doesn't need to be materialized |
--- |
6204 |
// transform the ADD so the immediate doesn't need to be materialized |
--- |
| 6205 |
// in a register. |
--- |
6205 |
// in a register. |
--- |
| 6206 |
APInt ADDC = ADDI->getAPIntValue(); |
0 |
6206 |
APInt ADDC = ADDI->getAPIntValue(); |
0 |
| 6207 |
APInt SRLC = SRLI->getAPIntValue(); |
0 |
6207 |
APInt SRLC = SRLI->getAPIntValue(); |
0 |
| 6208 |
if (ADDC.getSignificantBits() <= 64 && SRLC.ult(VT.getSizeInBits()) && |
0 |
6208 |
if (ADDC.getSignificantBits() <= 64 && SRLC.ult(VT.getSizeInBits()) && |
0 |
| 6209 |
!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { |
0 |
6209 |
!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { |
0 |
| 6210 |
APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), |
0 |
6210 |
APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), |
0 |
| 6211 |
SRLC.getZExtValue()); |
0 |
6211 |
SRLC.getZExtValue()); |
0 |
| 6212 |
if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { |
0 |
6212 |
if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { |
0 |
| 6213 |
ADDC |= Mask; |
0 |
6213 |
ADDC |= Mask; |
0 |
| 6214 |
if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { |
0 |
6214 |
if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { |
0 |
| 6215 |
SDLoc DL0(N0); |
0 |
6215 |
SDLoc DL0(N0); |
0 |
| 6216 |
SDValue NewAdd = |
--- |
6216 |
SDValue NewAdd = |
--- |
| 6217 |
DAG.getNode(ISD::ADD, DL0, VT, |
0 |
6217 |
DAG.getNode(ISD::ADD, DL0, VT, |
0 |
| 6218 |
N0.getOperand(0), DAG.getConstant(ADDC, DL, VT)); |
0 |
6218 |
N0.getOperand(0), DAG.getConstant(ADDC, DL, VT)); |
0 |
| 6219 |
CombineTo(N0.getNode(), NewAdd); |
0 |
6219 |
CombineTo(N0.getNode(), NewAdd); |
0 |
| 6220 |
// Return N so it doesn't get rechecked! |
--- |
6220 |
// Return N so it doesn't get rechecked! |
--- |
| 6221 |
return SDValue(N, 0); |
0 |
6221 |
return SDValue(N, 0); |
0 |
| 6222 |
} |
0 |
6222 |
} |
0 |
| 6223 |
} |
--- |
6223 |
} |
--- |
| 6224 |
} |
0 |
6224 |
} |
0 |
| 6225 |
} |
0 |
6225 |
} |
0 |
| 6226 |
} |
--- |
6226 |
} |
--- |
| 6227 |
} |
--- |
6227 |
} |
--- |
| 6228 |
|
--- |
6228 |
|
--- |
| 6229 |
return SDValue(); |
1 |
6229 |
return SDValue(); |
1 |
| 6230 |
} |
1 |
6230 |
} |
1 |
| 6231 |
|
--- |
6231 |
|
--- |
| 6232 |
bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN, |
0 |
6232 |
bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN, |
0 |
| 6233 |
EVT LoadResultTy, EVT &ExtVT) { |
--- |
6233 |
EVT LoadResultTy, EVT &ExtVT) { |
--- |
| 6234 |
if (!AndC->getAPIntValue().isMask()) |
0 |
6234 |
if (!AndC->getAPIntValue().isMask()) |
0 |
| 6235 |
return false; |
0 |
6235 |
return false; |
0 |
| 6236 |
|
--- |
6236 |
|
--- |
| 6237 |
unsigned ActiveBits = AndC->getAPIntValue().countr_one(); |
0 |
6237 |
unsigned ActiveBits = AndC->getAPIntValue().countr_one(); |
0 |
| 6238 |
|
--- |
6238 |
|
--- |
| 6239 |
ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); |
0 |
6239 |
ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); |
0 |
| 6240 |
EVT LoadedVT = LoadN->getMemoryVT(); |
0 |
6240 |
EVT LoadedVT = LoadN->getMemoryVT(); |
0 |
| 6241 |
|
--- |
6241 |
|
--- |
| 6242 |
if (ExtVT == LoadedVT && |
0 |
6242 |
if (ExtVT == LoadedVT && |
0 |
| 6243 |
(!LegalOperations || |
0 |
6243 |
(!LegalOperations || |
0 |
| 6244 |
TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) { |
0 |
6244 |
TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) { |
0 |
| 6245 |
// ZEXTLOAD will match without needing to change the size of the value being |
--- |
6245 |
// ZEXTLOAD will match without needing to change the size of the value being |
--- |
| 6246 |
// loaded. |
--- |
6246 |
// loaded. |
--- |
| 6247 |
return true; |
0 |
6247 |
return true; |
0 |
| 6248 |
} |
--- |
6248 |
} |
--- |
| 6249 |
|
--- |
6249 |
|
--- |
| 6250 |
// Do not change the width of a volatile or atomic loads. |
--- |
6250 |
// Do not change the width of a volatile or atomic loads. |
--- |
| 6251 |
if (!LoadN->isSimple()) |
0 |
6251 |
if (!LoadN->isSimple()) |
0 |
| 6252 |
return false; |
0 |
6252 |
return false; |
0 |
| 6253 |
|
--- |
6253 |
|
--- |
| 6254 |
// Do not generate loads of non-round integer types since these can |
--- |
6254 |
// Do not generate loads of non-round integer types since these can |
--- |
| 6255 |
// be expensive (and would be wrong if the type is not byte sized). |
--- |
6255 |
// be expensive (and would be wrong if the type is not byte sized). |
--- |
| 6256 |
if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) |
0 |
6256 |
if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) |
0 |
| 6257 |
return false; |
0 |
6257 |
return false; |
0 |
| 6258 |
|
--- |
6258 |
|
--- |
| 6259 |
if (LegalOperations && |
0 |
6259 |
if (LegalOperations && |
0 |
| 6260 |
!TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT)) |
0 |
6260 |
!TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT)) |
0 |
| 6261 |
return false; |
0 |
6261 |
return false; |
0 |
| 6262 |
|
--- |
6262 |
|
--- |
| 6263 |
if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT)) |
0 |
6263 |
if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT)) |
0 |
| 6264 |
return false; |
0 |
6264 |
return false; |
0 |
| 6265 |
|
--- |
6265 |
|
--- |
| 6266 |
return true; |
0 |
6266 |
return true; |
0 |
| 6267 |
} |
--- |
6267 |
} |
--- |
| 6268 |
|
--- |
6268 |
|
--- |
| 6269 |
bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST, |
0 |
6269 |
bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST, |
0 |
| 6270 |
ISD::LoadExtType ExtType, EVT &MemVT, |
--- |
6270 |
ISD::LoadExtType ExtType, EVT &MemVT, |
--- |
| 6271 |
unsigned ShAmt) { |
--- |
6271 |
unsigned ShAmt) { |
--- |
| 6272 |
if (!LDST) |
0 |
6272 |
if (!LDST) |
0 |
| 6273 |
return false; |
0 |
6273 |
return false; |
0 |
| 6274 |
// Only allow byte offsets. |
--- |
6274 |
// Only allow byte offsets. |
--- |
| 6275 |
if (ShAmt % 8) |
0 |
6275 |
if (ShAmt % 8) |
0 |
| 6276 |
return false; |
0 |
6276 |
return false; |
0 |
| 6277 |
|
--- |
6277 |
|
--- |
| 6278 |
// Do not generate loads of non-round integer types since these can |
--- |
6278 |
// Do not generate loads of non-round integer types since these can |
--- |
| 6279 |
// be expensive (and would be wrong if the type is not byte sized). |
--- |
6279 |
// be expensive (and would be wrong if the type is not byte sized). |
--- |
| 6280 |
if (!MemVT.isRound()) |
0 |
6280 |
if (!MemVT.isRound()) |
0 |
| 6281 |
return false; |
0 |
6281 |
return false; |
0 |
| 6282 |
|
--- |
6282 |
|
--- |
| 6283 |
// Don't change the width of a volatile or atomic loads. |
--- |
6283 |
// Don't change the width of a volatile or atomic loads. |
--- |
| 6284 |
if (!LDST->isSimple()) |
0 |
6284 |
if (!LDST->isSimple()) |
0 |
| 6285 |
return false; |
0 |
6285 |
return false; |
0 |
| 6286 |
|
--- |
6286 |
|
--- |
| 6287 |
EVT LdStMemVT = LDST->getMemoryVT(); |
0 |
6287 |
EVT LdStMemVT = LDST->getMemoryVT(); |
0 |
| 6288 |
|
--- |
6288 |
|
--- |
| 6289 |
// Bail out when changing the scalable property, since we can't be sure that |
--- |
6289 |
// Bail out when changing the scalable property, since we can't be sure that |
--- |
| 6290 |
// we're actually narrowing here. |
--- |
6290 |
// we're actually narrowing here. |
--- |
| 6291 |
if (LdStMemVT.isScalableVector() != MemVT.isScalableVector()) |
0 |
6291 |
if (LdStMemVT.isScalableVector() != MemVT.isScalableVector()) |
0 |
| 6292 |
return false; |
0 |
6292 |
return false; |
0 |
| 6293 |
|
--- |
6293 |
|
--- |
| 6294 |
// Verify that we are actually reducing a load width here. |
--- |
6294 |
// Verify that we are actually reducing a load width here. |
--- |
| 6295 |
if (LdStMemVT.bitsLT(MemVT)) |
0 |
6295 |
if (LdStMemVT.bitsLT(MemVT)) |
0 |
| 6296 |
return false; |
0 |
6296 |
return false; |
0 |
| 6297 |
|
--- |
6297 |
|
--- |
| 6298 |
// Ensure that this isn't going to produce an unsupported memory access. |
--- |
6298 |
// Ensure that this isn't going to produce an unsupported memory access. |
--- |
| 6299 |
if (ShAmt) { |
0 |
6299 |
if (ShAmt) { |
0 |
| 6300 |
assert(ShAmt % 8 == 0 && "ShAmt is byte offset"); |
0 |
6300 |
assert(ShAmt % 8 == 0 && "ShAmt is byte offset"); |
0 |
| 6301 |
const unsigned ByteShAmt = ShAmt / 8; |
0 |
6301 |
const unsigned ByteShAmt = ShAmt / 8; |
0 |
| 6302 |
const Align LDSTAlign = LDST->getAlign(); |
0 |
6302 |
const Align LDSTAlign = LDST->getAlign(); |
0 |
| 6303 |
const Align NarrowAlign = commonAlignment(LDSTAlign, ByteShAmt); |
0 |
6303 |
const Align NarrowAlign = commonAlignment(LDSTAlign, ByteShAmt); |
0 |
| 6304 |
if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT, |
0 |
6304 |
if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT, |
0 |
| 6305 |
LDST->getAddressSpace(), NarrowAlign, |
--- |
6305 |
LDST->getAddressSpace(), NarrowAlign, |
--- |
| 6306 |
LDST->getMemOperand()->getFlags())) |
0 |
6306 |
LDST->getMemOperand()->getFlags())) |
0 |
| 6307 |
return false; |
0 |
6307 |
return false; |
0 |
| 6308 |
} |
--- |
6308 |
} |
--- |
| 6309 |
|
--- |
6309 |
|
--- |
| 6310 |
// It's not possible to generate a constant of extended or untyped type. |
--- |
6310 |
// It's not possible to generate a constant of extended or untyped type. |
--- |
| 6311 |
EVT PtrType = LDST->getBasePtr().getValueType(); |
0 |
6311 |
EVT PtrType = LDST->getBasePtr().getValueType(); |
0 |
| 6312 |
if (PtrType == MVT::Untyped || PtrType.isExtended()) |
0 |
6312 |
if (PtrType == MVT::Untyped || PtrType.isExtended()) |
0 |
| 6313 |
return false; |
0 |
6313 |
return false; |
0 |
| 6314 |
|
--- |
6314 |
|
--- |
| 6315 |
if (isa(LDST)) { |
0 |
6315 |
if (isa(LDST)) { |
0 |
| 6316 |
LoadSDNode *Load = cast(LDST); |
0 |
6316 |
LoadSDNode *Load = cast(LDST); |
0 |
| 6317 |
// Don't transform one with multiple uses, this would require adding a new |
--- |
6317 |
// Don't transform one with multiple uses, this would require adding a new |
--- |
| 6318 |
// load. |
--- |
6318 |
// load. |
--- |
| 6319 |
if (!SDValue(Load, 0).hasOneUse()) |
0 |
6319 |
if (!SDValue(Load, 0).hasOneUse()) |
0 |
| 6320 |
return false; |
0 |
6320 |
return false; |
0 |
| 6321 |
|
--- |
6321 |
|
--- |
| 6322 |
if (LegalOperations && |
0 |
6322 |
if (LegalOperations && |
0 |
| 6323 |
!TLI.isLoadExtLegal(ExtType, Load->getValueType(0), MemVT)) |
0 |
6323 |
!TLI.isLoadExtLegal(ExtType, Load->getValueType(0), MemVT)) |
0 |
| 6324 |
return false; |
0 |
6324 |
return false; |
0 |
| 6325 |
|
--- |
6325 |
|
--- |
| 6326 |
// For the transform to be legal, the load must produce only two values |
--- |
6326 |
// For the transform to be legal, the load must produce only two values |
--- |
| 6327 |
// (the value loaded and the chain). Don't transform a pre-increment |
--- |
6327 |
// (the value loaded and the chain). Don't transform a pre-increment |
--- |
| 6328 |
// load, for example, which produces an extra value. Otherwise the |
--- |
6328 |
// load, for example, which produces an extra value. Otherwise the |
--- |
| 6329 |
// transformation is not equivalent, and the downstream logic to replace |
--- |
6329 |
// transformation is not equivalent, and the downstream logic to replace |
--- |
| 6330 |
// uses gets things wrong. |
--- |
6330 |
// uses gets things wrong. |
--- |
| 6331 |
if (Load->getNumValues() > 2) |
0 |
6331 |
if (Load->getNumValues() > 2) |
0 |
| 6332 |
return false; |
0 |
6332 |
return false; |
0 |
| 6333 |
|
--- |
6333 |
|
--- |
| 6334 |
// If the load that we're shrinking is an extload and we're not just |
--- |
6334 |
// If the load that we're shrinking is an extload and we're not just |
--- |
| 6335 |
// discarding the extension we can't simply shrink the load. Bail. |
--- |
6335 |
// discarding the extension we can't simply shrink the load. Bail. |
--- |
| 6336 |
// TODO: It would be possible to merge the extensions in some cases. |
--- |
6336 |
// TODO: It would be possible to merge the extensions in some cases. |
--- |
| 6337 |
if (Load->getExtensionType() != ISD::NON_EXTLOAD && |
0 |
6337 |
if (Load->getExtensionType() != ISD::NON_EXTLOAD && |
0 |
| 6338 |
Load->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt) |
0 |
6338 |
Load->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt) |
0 |
| 6339 |
return false; |
0 |
6339 |
return false; |
0 |
| 6340 |
|
--- |
6340 |
|
--- |
| 6341 |
if (!TLI.shouldReduceLoadWidth(Load, ExtType, MemVT)) |
0 |
6341 |
if (!TLI.shouldReduceLoadWidth(Load, ExtType, MemVT)) |
0 |
| 6342 |
return false; |
0 |
6342 |
return false; |
0 |
| 6343 |
} else { |
--- |
6343 |
} else { |
--- |
| 6344 |
assert(isa(LDST) && "It is not a Load nor a Store SDNode"); |
0 |
6344 |
assert(isa(LDST) && "It is not a Load nor a Store SDNode"); |
0 |
| 6345 |
StoreSDNode *Store = cast(LDST); |
0 |
6345 |
StoreSDNode *Store = cast(LDST); |
0 |
| 6346 |
// Can't write outside the original store |
--- |
6346 |
// Can't write outside the original store |
--- |
| 6347 |
if (Store->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt) |
0 |
6347 |
if (Store->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt) |
0 |
| 6348 |
return false; |
0 |
6348 |
return false; |
0 |
| 6349 |
|
--- |
6349 |
|
--- |
| 6350 |
if (LegalOperations && |
0 |
6350 |
if (LegalOperations && |
0 |
| 6351 |
!TLI.isTruncStoreLegal(Store->getValue().getValueType(), MemVT)) |
0 |
6351 |
!TLI.isTruncStoreLegal(Store->getValue().getValueType(), MemVT)) |
0 |
| 6352 |
return false; |
0 |
6352 |
return false; |
0 |
| 6353 |
} |
--- |
6353 |
} |
--- |
| 6354 |
return true; |
0 |
6354 |
return true; |
0 |
| 6355 |
} |
--- |
6355 |
} |
--- |
| 6356 |
|
--- |
6356 |
|
--- |
| 6357 |
bool DAGCombiner::SearchForAndLoads(SDNode *N, |
1 |
6357 |
bool DAGCombiner::SearchForAndLoads(SDNode *N, |
1 |
| 6358 |
SmallVectorImpl &Loads, |
--- |
6358 |
SmallVectorImpl &Loads, |
--- |
| 6359 |
SmallPtrSetImpl &NodesWithConsts, |
--- |
6359 |
SmallPtrSetImpl &NodesWithConsts, |
--- |
| 6360 |
ConstantSDNode *Mask, |
--- |
6360 |
ConstantSDNode *Mask, |
--- |
| 6361 |
SDNode *&NodeToMask) { |
--- |
6361 |
SDNode *&NodeToMask) { |
--- |
| 6362 |
// Recursively search for the operands, looking for loads which can be |
--- |
6362 |
// Recursively search for the operands, looking for loads which can be |
--- |
| 6363 |
// narrowed. |
--- |
6363 |
// narrowed. |
--- |
| 6364 |
for (SDValue Op : N->op_values()) { |
3 |
6364 |
for (SDValue Op : N->op_values()) { |
3 |
| 6365 |
if (Op.getValueType().isVector()) |
2 |
6365 |
if (Op.getValueType().isVector()) |
2 |
| 6366 |
return false; |
0 |
6366 |
return false; |
0 |
| 6367 |
|
--- |
6367 |
|
--- |
| 6368 |
// Some constants may need fixing up later if they are too large. |
--- |
6368 |
// Some constants may need fixing up later if they are too large. |
--- |
| 6369 |
if (auto *C = dyn_cast(Op)) { |
2 |
6369 |
if (auto *C = dyn_cast(Op)) { |
2 |
| 6370 |
if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) && |
1 |
6370 |
if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) && |
1 |
| 6371 |
(Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue()) |
1 |
6371 |
(Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue()) |
1 |
| 6372 |
NodesWithConsts.insert(N); |
0 |
6372 |
NodesWithConsts.insert(N); |
0 |
| 6373 |
continue; |
1 |
6373 |
continue; |
1 |
| 6374 |
} |
--- |
6374 |
} |
--- |
| 6375 |
|
--- |
6375 |
|
--- |
| 6376 |
if (!Op.hasOneUse()) |
1 |
6376 |
if (!Op.hasOneUse()) |
1 |
| 6377 |
return false; |
0 |
6377 |
return false; |
0 |
| 6378 |
|
--- |
6378 |
|
--- |
| 6379 |
switch(Op.getOpcode()) { |
1 |
6379 |
switch(Op.getOpcode()) { |
1 |
| 6380 |
case ISD::LOAD: { |
0 |
6380 |
case ISD::LOAD: { |
0 |
| 6381 |
auto *Load = cast(Op); |
0 |
6381 |
auto *Load = cast(Op); |
0 |
| 6382 |
EVT ExtVT; |
0 |
6382 |
EVT ExtVT; |
0 |
| 6383 |
if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) && |
0 |
6383 |
if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) && |
0 |
| 6384 |
isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) { |
0 |
6384 |
isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) { |
0 |
| 6385 |
|
--- |
6385 |
|
--- |
| 6386 |
// ZEXTLOAD is already small enough. |
--- |
6386 |
// ZEXTLOAD is already small enough. |
--- |
| 6387 |
if (Load->getExtensionType() == ISD::ZEXTLOAD && |
0 |
6387 |
if (Load->getExtensionType() == ISD::ZEXTLOAD && |
0 |
| 6388 |
ExtVT.bitsGE(Load->getMemoryVT())) |
0 |
6388 |
ExtVT.bitsGE(Load->getMemoryVT())) |
0 |
| 6389 |
continue; |
0 |
6389 |
continue; |
0 |
| 6390 |
|
--- |
6390 |
|
--- |
| 6391 |
// Use LE to convert equal sized loads to zext. |
--- |
6391 |
// Use LE to convert equal sized loads to zext. |
--- |
| 6392 |
if (ExtVT.bitsLE(Load->getMemoryVT())) |
0 |
6392 |
if (ExtVT.bitsLE(Load->getMemoryVT())) |
0 |
| 6393 |
Loads.push_back(Load); |
0 |
6393 |
Loads.push_back(Load); |
0 |
| 6394 |
|
--- |
6394 |
|
--- |
| 6395 |
continue; |
0 |
6395 |
continue; |
0 |
| 6396 |
} |
--- |
6396 |
} |
--- |
| 6397 |
return false; |
0 |
6397 |
return false; |
0 |
| 6398 |
} |
--- |
6398 |
} |
--- |
| 6399 |
case ISD::ZERO_EXTEND: |
0 |
6399 |
case ISD::ZERO_EXTEND: |
0 |
| 6400 |
case ISD::AssertZext: { |
--- |
6400 |
case ISD::AssertZext: { |
--- |
| 6401 |
unsigned ActiveBits = Mask->getAPIntValue().countr_one(); |
0 |
6401 |
unsigned ActiveBits = Mask->getAPIntValue().countr_one(); |
0 |
| 6402 |
EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); |
0 |
6402 |
EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); |
0 |
| 6403 |
EVT VT = Op.getOpcode() == ISD::AssertZext ? |
0 |
6403 |
EVT VT = Op.getOpcode() == ISD::AssertZext ? |
0 |
| 6404 |
cast(Op.getOperand(1))->getVT() : |
0 |
6404 |
cast(Op.getOperand(1))->getVT() : |
0 |
| 6405 |
Op.getOperand(0).getValueType(); |
0 |
6405 |
Op.getOperand(0).getValueType(); |
0 |
| 6406 |
|
--- |
6406 |
|
--- |
| 6407 |
// We can accept extending nodes if the mask is wider or an equal |
--- |
6407 |
// We can accept extending nodes if the mask is wider or an equal |
--- |
| 6408 |
// width to the original type. |
--- |
6408 |
// width to the original type. |
--- |
| 6409 |
if (ExtVT.bitsGE(VT)) |
0 |
6409 |
if (ExtVT.bitsGE(VT)) |
0 |
| 6410 |
continue; |
0 |
6410 |
continue; |
0 |
| 6411 |
break; |
0 |
6411 |
break; |
0 |
| 6412 |
} |
--- |
6412 |
} |
--- |
| 6413 |
case ISD::OR: |
0 |
6413 |
case ISD::OR: |
0 |
| 6414 |
case ISD::XOR: |
--- |
6414 |
case ISD::XOR: |
--- |
| 6415 |
case ISD::AND: |
--- |
6415 |
case ISD::AND: |
--- |
| 6416 |
if (!SearchForAndLoads(Op.getNode(), Loads, NodesWithConsts, Mask, |
0 |
6416 |
if (!SearchForAndLoads(Op.getNode(), Loads, NodesWithConsts, Mask, |
0 |
| 6417 |
NodeToMask)) |
--- |
6417 |
NodeToMask)) |
--- |
| 6418 |
return false; |
0 |
6418 |
return false; |
0 |
| 6419 |
continue; |
0 |
6419 |
continue; |
0 |
| 6420 |
} |
0 |
6420 |
} |
0 |
| 6421 |
|
--- |
6421 |
|
--- |
| 6422 |
// Allow one node which will masked along with any loads found. |
--- |
6422 |
// Allow one node which will masked along with any loads found. |
--- |
| 6423 |
if (NodeToMask) |
1 |
6423 |
if (NodeToMask) |
1 |
| 6424 |
return false; |
0 |
6424 |
return false; |
0 |
| 6425 |
|
--- |
6425 |
|
--- |
| 6426 |
// Also ensure that the node to be masked only produces one data result. |
--- |
6426 |
// Also ensure that the node to be masked only produces one data result. |
--- |
| 6427 |
NodeToMask = Op.getNode(); |
1 |
6427 |
NodeToMask = Op.getNode(); |
1 |
| 6428 |
if (NodeToMask->getNumValues() > 1) { |
1 |
6428 |
if (NodeToMask->getNumValues() > 1) { |
1 |
| 6429 |
bool HasValue = false; |
0 |
6429 |
bool HasValue = false; |
0 |
| 6430 |
for (unsigned i = 0, e = NodeToMask->getNumValues(); i < e; ++i) { |
0 |
6430 |
for (unsigned i = 0, e = NodeToMask->getNumValues(); i < e; ++i) { |
0 |
| 6431 |
MVT VT = SDValue(NodeToMask, i).getSimpleValueType(); |
0 |
6431 |
MVT VT = SDValue(NodeToMask, i).getSimpleValueType(); |
0 |
| 6432 |
if (VT != MVT::Glue && VT != MVT::Other) { |
0 |
6432 |
if (VT != MVT::Glue && VT != MVT::Other) { |
0 |
| 6433 |
if (HasValue) { |
0 |
6433 |
if (HasValue) { |
0 |
| 6434 |
NodeToMask = nullptr; |
0 |
6434 |
NodeToMask = nullptr; |
0 |
| 6435 |
return false; |
0 |
6435 |
return false; |
0 |
| 6436 |
} |
--- |
6436 |
} |
--- |
| 6437 |
HasValue = true; |
0 |
6437 |
HasValue = true; |
0 |
| 6438 |
} |
--- |
6438 |
} |
--- |
| 6439 |
} |
--- |
6439 |
} |
--- |
| 6440 |
assert(HasValue && "Node to be masked has no data result?"); |
0 |
6440 |
assert(HasValue && "Node to be masked has no data result?"); |
0 |
| 6441 |
} |
--- |
6441 |
} |
--- |
| 6442 |
} |
--- |
6442 |
} |
--- |
| 6443 |
return true; |
1 |
6443 |
return true; |
1 |
| 6444 |
} |
--- |
6444 |
} |
--- |
| 6445 |
|
--- |
6445 |
|
--- |
| 6446 |
bool DAGCombiner::BackwardsPropagateMask(SDNode *N) { |
1 |
6446 |
bool DAGCombiner::BackwardsPropagateMask(SDNode *N) { |
1 |
| 6447 |
auto *Mask = dyn_cast(N->getOperand(1)); |
1 |
6447 |
auto *Mask = dyn_cast(N->getOperand(1)); |
1 |
| 6448 |
if (!Mask) |
1 |
6448 |
if (!Mask) |
1 |
| 6449 |
return false; |
0 |
6449 |
return false; |
0 |
| 6450 |
|
--- |
6450 |
|
--- |
| 6451 |
if (!Mask->getAPIntValue().isMask()) |
1 |
6451 |
if (!Mask->getAPIntValue().isMask()) |
1 |
| 6452 |
return false; |
0 |
6452 |
return false; |
0 |
| 6453 |
|
--- |
6453 |
|
--- |
| 6454 |
// No need to do anything if the and directly uses a load. |
--- |
6454 |
// No need to do anything if the and directly uses a load. |
--- |
| 6455 |
if (isa(N->getOperand(0))) |
1 |
6455 |
if (isa(N->getOperand(0))) |
1 |
| 6456 |
return false; |
0 |
6456 |
return false; |
0 |
| 6457 |
|
--- |
6457 |
|
--- |
| 6458 |
SmallVector Loads; |
1 |
6458 |
SmallVector Loads; |
1 |
| 6459 |
SmallPtrSet NodesWithConsts; |
1 |
6459 |
SmallPtrSet NodesWithConsts; |
1 |
| 6460 |
SDNode *FixupNode = nullptr; |
1 |
6460 |
SDNode *FixupNode = nullptr; |
1 |
| 6461 |
if (SearchForAndLoads(N, Loads, NodesWithConsts, Mask, FixupNode)) { |
1 |
6461 |
if (SearchForAndLoads(N, Loads, NodesWithConsts, Mask, FixupNode)) { |
1 |
| 6462 |
if (Loads.size() == 0) |
1 |
6462 |
if (Loads.size() == 0) |
1 |
| 6463 |
return false; |
1 |
6463 |
return false; |
1 |
| 6464 |
|
--- |
6464 |
|
--- |
| 6465 |
LLVM_DEBUG(dbgs() << "Backwards propagate AND: "; N->dump()); |
0 |
6465 |
LLVM_DEBUG(dbgs() << "Backwards propagate AND: "; N->dump()); |
0 |
| 6466 |
SDValue MaskOp = N->getOperand(1); |
0 |
6466 |
SDValue MaskOp = N->getOperand(1); |
0 |
| 6467 |
|
--- |
6467 |
|
--- |
| 6468 |
// If it exists, fixup the single node we allow in the tree that needs |
--- |
6468 |
// If it exists, fixup the single node we allow in the tree that needs |
--- |
| 6469 |
// masking. |
--- |
6469 |
// masking. |
--- |
| 6470 |
if (FixupNode) { |
0 |
6470 |
if (FixupNode) { |
0 |
| 6471 |
LLVM_DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump()); |
0 |
6471 |
LLVM_DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump()); |
0 |
| 6472 |
SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode), |
0 |
6472 |
SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode), |
0 |
| 6473 |
FixupNode->getValueType(0), |
--- |
6473 |
FixupNode->getValueType(0), |
--- |
| 6474 |
SDValue(FixupNode, 0), MaskOp); |
--- |
6474 |
SDValue(FixupNode, 0), MaskOp); |
--- |
| 6475 |
DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And); |
0 |
6475 |
DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And); |
0 |
| 6476 |
if (And.getOpcode() == ISD ::AND) |
0 |
6476 |
if (And.getOpcode() == ISD ::AND) |
0 |
| 6477 |
DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0), MaskOp); |
0 |
6477 |
DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0), MaskOp); |
0 |
| 6478 |
} |
--- |
6478 |
} |
--- |
| 6479 |
|
--- |
6479 |
|
--- |
| 6480 |
// Narrow any constants that need it. |
--- |
6480 |
// Narrow any constants that need it. |
--- |
| 6481 |
for (auto *LogicN : NodesWithConsts) { |
0 |
6481 |
for (auto *LogicN : NodesWithConsts) { |
0 |
| 6482 |
SDValue Op0 = LogicN->getOperand(0); |
0 |
6482 |
SDValue Op0 = LogicN->getOperand(0); |
0 |
| 6483 |
SDValue Op1 = LogicN->getOperand(1); |
0 |
6483 |
SDValue Op1 = LogicN->getOperand(1); |
0 |
| 6484 |
|
--- |
6484 |
|
--- |
| 6485 |
if (isa(Op0)) |
0 |
6485 |
if (isa(Op0)) |
0 |
| 6486 |
std::swap(Op0, Op1); |
0 |
6486 |
std::swap(Op0, Op1); |
0 |
| 6487 |
|
--- |
6487 |
|
--- |
| 6488 |
SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(), |
0 |
6488 |
SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(), |
0 |
| 6489 |
Op1, MaskOp); |
--- |
6489 |
Op1, MaskOp); |
--- |
| 6490 |
|
--- |
6490 |
|
--- |
| 6491 |
DAG.UpdateNodeOperands(LogicN, Op0, And); |
0 |
6491 |
DAG.UpdateNodeOperands(LogicN, Op0, And); |
0 |
| 6492 |
} |
--- |
6492 |
} |
--- |
| 6493 |
|
--- |
6493 |
|
--- |
| 6494 |
// Create narrow loads. |
--- |
6494 |
// Create narrow loads. |
--- |
| 6495 |
for (auto *Load : Loads) { |
0 |
6495 |
for (auto *Load : Loads) { |
0 |
| 6496 |
LLVM_DEBUG(dbgs() << "Propagate AND back to: "; Load->dump()); |
0 |
6496 |
LLVM_DEBUG(dbgs() << "Propagate AND back to: "; Load->dump()); |
0 |
| 6497 |
SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0), |
0 |
6497 |
SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0), |
0 |
| 6498 |
SDValue(Load, 0), MaskOp); |
--- |
6498 |
SDValue(Load, 0), MaskOp); |
--- |
| 6499 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And); |
0 |
6499 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And); |
0 |
| 6500 |
if (And.getOpcode() == ISD ::AND) |
0 |
6500 |
if (And.getOpcode() == ISD ::AND) |
0 |
| 6501 |
And = SDValue( |
0 |
6501 |
And = SDValue( |
0 |
| 6502 |
DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOp), 0); |
0 |
6502 |
DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOp), 0); |
0 |
| 6503 |
SDValue NewLoad = reduceLoadWidth(And.getNode()); |
0 |
6503 |
SDValue NewLoad = reduceLoadWidth(And.getNode()); |
0 |
| 6504 |
assert(NewLoad && |
0 |
6504 |
assert(NewLoad && |
0 |
| 6505 |
"Shouldn't be masking the load if it can't be narrowed"); |
--- |
6505 |
"Shouldn't be masking the load if it can't be narrowed"); |
--- |
| 6506 |
CombineTo(Load, NewLoad, NewLoad.getValue(1)); |
0 |
6506 |
CombineTo(Load, NewLoad, NewLoad.getValue(1)); |
0 |
| 6507 |
} |
--- |
6507 |
} |
--- |
| 6508 |
DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode()); |
0 |
6508 |
DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode()); |
0 |
| 6509 |
return true; |
0 |
6509 |
return true; |
0 |
| 6510 |
} |
--- |
6510 |
} |
--- |
| 6511 |
return false; |
0 |
6511 |
return false; |
0 |
| 6512 |
} |
1 |
6512 |
} |
1 |
| 6513 |
|
--- |
6513 |
|
--- |
| 6514 |
// Unfold |
--- |
6514 |
// Unfold |
--- |
| 6515 |
// x & (-1 'logical shift' y) |
--- |
6515 |
// x & (-1 'logical shift' y) |
--- |
| 6516 |
// To |
--- |
6516 |
// To |
--- |
| 6517 |
// (x 'opposite logical shift' y) 'logical shift' y |
--- |
6517 |
// (x 'opposite logical shift' y) 'logical shift' y |
--- |
| 6518 |
// if it is better for performance. |
--- |
6518 |
// if it is better for performance. |
--- |
| 6519 |
SDValue DAGCombiner::unfoldExtremeBitClearingToShifts(SDNode *N) { |
0 |
6519 |
SDValue DAGCombiner::unfoldExtremeBitClearingToShifts(SDNode *N) { |
0 |
| 6520 |
assert(N->getOpcode() == ISD::AND); |
0 |
6520 |
assert(N->getOpcode() == ISD::AND); |
0 |
| 6521 |
|
--- |
6521 |
|
--- |
| 6522 |
SDValue N0 = N->getOperand(0); |
0 |
6522 |
SDValue N0 = N->getOperand(0); |
0 |
| 6523 |
SDValue N1 = N->getOperand(1); |
0 |
6523 |
SDValue N1 = N->getOperand(1); |
0 |
| 6524 |
|
--- |
6524 |
|
--- |
| 6525 |
// Do we actually prefer shifts over mask? |
--- |
6525 |
// Do we actually prefer shifts over mask? |
--- |
| 6526 |
if (!TLI.shouldFoldMaskToVariableShiftPair(N0)) |
0 |
6526 |
if (!TLI.shouldFoldMaskToVariableShiftPair(N0)) |
0 |
| 6527 |
return SDValue(); |
0 |
6527 |
return SDValue(); |
0 |
| 6528 |
|
--- |
6528 |
|
--- |
| 6529 |
// Try to match (-1 '[outer] logical shift' y) |
--- |
6529 |
// Try to match (-1 '[outer] logical shift' y) |
--- |
| 6530 |
unsigned OuterShift; |
--- |
6530 |
unsigned OuterShift; |
--- |
| 6531 |
unsigned InnerShift; // The opposite direction to the OuterShift. |
--- |
6531 |
unsigned InnerShift; // The opposite direction to the OuterShift. |
--- |
| 6532 |
SDValue Y; // Shift amount. |
0 |
6532 |
SDValue Y; // Shift amount. |
0 |
| 6533 |
auto matchMask = [&OuterShift, &InnerShift, &Y](SDValue M) -> bool { |
0 |
6533 |
auto matchMask = [&OuterShift, &InnerShift, &Y](SDValue M) -> bool { |
0 |
| 6534 |
if (!M.hasOneUse()) |
0 |
6534 |
if (!M.hasOneUse()) |
0 |
| 6535 |
return false; |
0 |
6535 |
return false; |
0 |
| 6536 |
OuterShift = M->getOpcode(); |
0 |
6536 |
OuterShift = M->getOpcode(); |
0 |
| 6537 |
if (OuterShift == ISD::SHL) |
0 |
6537 |
if (OuterShift == ISD::SHL) |
0 |
| 6538 |
InnerShift = ISD::SRL; |
0 |
6538 |
InnerShift = ISD::SRL; |
0 |
| 6539 |
else if (OuterShift == ISD::SRL) |
0 |
6539 |
else if (OuterShift == ISD::SRL) |
0 |
| 6540 |
InnerShift = ISD::SHL; |
0 |
6540 |
InnerShift = ISD::SHL; |
0 |
| 6541 |
else |
--- |
6541 |
else |
--- |
| 6542 |
return false; |
0 |
6542 |
return false; |
0 |
| 6543 |
if (!isAllOnesConstant(M->getOperand(0))) |
0 |
6543 |
if (!isAllOnesConstant(M->getOperand(0))) |
0 |
| 6544 |
return false; |
0 |
6544 |
return false; |
0 |
| 6545 |
Y = M->getOperand(1); |
0 |
6545 |
Y = M->getOperand(1); |
0 |
| 6546 |
return true; |
0 |
6546 |
return true; |
0 |
| 6547 |
}; |
0 |
6547 |
}; |
0 |
| 6548 |
|
--- |
6548 |
|
--- |
| 6549 |
SDValue X; |
0 |
6549 |
SDValue X; |
0 |
| 6550 |
if (matchMask(N1)) |
0 |
6550 |
if (matchMask(N1)) |
0 |
| 6551 |
X = N0; |
0 |
6551 |
X = N0; |
0 |
| 6552 |
else if (matchMask(N0)) |
0 |
6552 |
else if (matchMask(N0)) |
0 |
| 6553 |
X = N1; |
0 |
6553 |
X = N1; |
0 |
| 6554 |
else |
--- |
6554 |
else |
--- |
| 6555 |
return SDValue(); |
0 |
6555 |
return SDValue(); |
0 |
| 6556 |
|
--- |
6556 |
|
--- |
| 6557 |
SDLoc DL(N); |
0 |
6557 |
SDLoc DL(N); |
0 |
| 6558 |
EVT VT = N->getValueType(0); |
0 |
6558 |
EVT VT = N->getValueType(0); |
0 |
| 6559 |
|
--- |
6559 |
|
--- |
| 6560 |
// tmp = x 'opposite logical shift' y |
--- |
6560 |
// tmp = x 'opposite logical shift' y |
--- |
| 6561 |
SDValue T0 = DAG.getNode(InnerShift, DL, VT, X, Y); |
0 |
6561 |
SDValue T0 = DAG.getNode(InnerShift, DL, VT, X, Y); |
0 |
| 6562 |
// ret = tmp 'logical shift' y |
--- |
6562 |
// ret = tmp 'logical shift' y |
--- |
| 6563 |
SDValue T1 = DAG.getNode(OuterShift, DL, VT, T0, Y); |
0 |
6563 |
SDValue T1 = DAG.getNode(OuterShift, DL, VT, T0, Y); |
0 |
| 6564 |
|
--- |
6564 |
|
--- |
| 6565 |
return T1; |
0 |
6565 |
return T1; |
0 |
| 6566 |
} |
0 |
6566 |
} |
0 |
| 6567 |
|
--- |
6567 |
|
--- |
| 6568 |
/// Try to replace shift/logic that tests if a bit is clear with mask + setcc. |
--- |
6568 |
/// Try to replace shift/logic that tests if a bit is clear with mask + setcc. |
--- |
| 6569 |
/// For a target with a bit test, this is expected to become test + set and save |
--- |
6569 |
/// For a target with a bit test, this is expected to become test + set and save |
--- |
| 6570 |
/// at least 1 instruction. |
--- |
6570 |
/// at least 1 instruction. |
--- |
| 6571 |
static SDValue combineShiftAnd1ToBitTest(SDNode *And, SelectionDAG &DAG) { |
0 |
6571 |
static SDValue combineShiftAnd1ToBitTest(SDNode *And, SelectionDAG &DAG) { |
0 |
| 6572 |
assert(And->getOpcode() == ISD::AND && "Expected an 'and' op"); |
0 |
6572 |
assert(And->getOpcode() == ISD::AND && "Expected an 'and' op"); |
0 |
| 6573 |
|
--- |
6573 |
|
--- |
| 6574 |
// Look through an optional extension. |
--- |
6574 |
// Look through an optional extension. |
--- |
| 6575 |
SDValue And0 = And->getOperand(0), And1 = And->getOperand(1); |
0 |
6575 |
SDValue And0 = And->getOperand(0), And1 = And->getOperand(1); |
0 |
| 6576 |
if (And0.getOpcode() == ISD::ANY_EXTEND && And0.hasOneUse()) |
0 |
6576 |
if (And0.getOpcode() == ISD::ANY_EXTEND && And0.hasOneUse()) |
0 |
| 6577 |
And0 = And0.getOperand(0); |
0 |
6577 |
And0 = And0.getOperand(0); |
0 |
| 6578 |
if (!isOneConstant(And1) || !And0.hasOneUse()) |
0 |
6578 |
if (!isOneConstant(And1) || !And0.hasOneUse()) |
0 |
| 6579 |
return SDValue(); |
0 |
6579 |
return SDValue(); |
0 |
| 6580 |
|
--- |
6580 |
|
--- |
| 6581 |
SDValue Src = And0; |
0 |
6581 |
SDValue Src = And0; |
0 |
| 6582 |
|
--- |
6582 |
|
--- |
| 6583 |
// Attempt to find a 'not' op. |
--- |
6583 |
// Attempt to find a 'not' op. |
--- |
| 6584 |
// TODO: Should we favor test+set even without the 'not' op? |
--- |
6584 |
// TODO: Should we favor test+set even without the 'not' op? |
--- |
| 6585 |
bool FoundNot = false; |
0 |
6585 |
bool FoundNot = false; |
0 |
| 6586 |
if (isBitwiseNot(Src)) { |
0 |
6586 |
if (isBitwiseNot(Src)) { |
0 |
| 6587 |
FoundNot = true; |
0 |
6587 |
FoundNot = true; |
0 |
| 6588 |
Src = Src.getOperand(0); |
0 |
6588 |
Src = Src.getOperand(0); |
0 |
| 6589 |
|
--- |
6589 |
|
--- |
| 6590 |
// Look though an optional truncation. The source operand may not be the |
--- |
6590 |
// Look though an optional truncation. The source operand may not be the |
--- |
| 6591 |
// same type as the original 'and', but that is ok because we are masking |
--- |
6591 |
// same type as the original 'and', but that is ok because we are masking |
--- |
| 6592 |
// off everything but the low bit. |
--- |
6592 |
// off everything but the low bit. |
--- |
| 6593 |
if (Src.getOpcode() == ISD::TRUNCATE && Src.hasOneUse()) |
0 |
6593 |
if (Src.getOpcode() == ISD::TRUNCATE && Src.hasOneUse()) |
0 |
| 6594 |
Src = Src.getOperand(0); |
0 |
6594 |
Src = Src.getOperand(0); |
0 |
| 6595 |
} |
--- |
6595 |
} |
--- |
| 6596 |
|
--- |
6596 |
|
--- |
| 6597 |
// Match a shift-right by constant. |
--- |
6597 |
// Match a shift-right by constant. |
--- |
| 6598 |
if (Src.getOpcode() != ISD::SRL || !Src.hasOneUse()) |
0 |
6598 |
if (Src.getOpcode() != ISD::SRL || !Src.hasOneUse()) |
0 |
| 6599 |
return SDValue(); |
0 |
6599 |
return SDValue(); |
0 |
| 6600 |
|
--- |
6600 |
|
--- |
| 6601 |
// This is probably not worthwhile without a supported type. |
--- |
6601 |
// This is probably not worthwhile without a supported type. |
--- |
| 6602 |
EVT SrcVT = Src.getValueType(); |
0 |
6602 |
EVT SrcVT = Src.getValueType(); |
0 |
| 6603 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
6603 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 6604 |
if (!TLI.isTypeLegal(SrcVT)) |
0 |
6604 |
if (!TLI.isTypeLegal(SrcVT)) |
0 |
| 6605 |
return SDValue(); |
0 |
6605 |
return SDValue(); |
0 |
| 6606 |
|
--- |
6606 |
|
--- |
| 6607 |
// We might have looked through casts that make this transform invalid. |
--- |
6607 |
// We might have looked through casts that make this transform invalid. |
--- |
| 6608 |
unsigned BitWidth = SrcVT.getScalarSizeInBits(); |
0 |
6608 |
unsigned BitWidth = SrcVT.getScalarSizeInBits(); |
0 |
| 6609 |
SDValue ShiftAmt = Src.getOperand(1); |
0 |
6609 |
SDValue ShiftAmt = Src.getOperand(1); |
0 |
| 6610 |
auto *ShiftAmtC = dyn_cast(ShiftAmt); |
0 |
6610 |
auto *ShiftAmtC = dyn_cast(ShiftAmt); |
0 |
| 6611 |
if (!ShiftAmtC || !ShiftAmtC->getAPIntValue().ult(BitWidth)) |
0 |
6611 |
if (!ShiftAmtC || !ShiftAmtC->getAPIntValue().ult(BitWidth)) |
0 |
| 6612 |
return SDValue(); |
0 |
6612 |
return SDValue(); |
0 |
| 6613 |
|
--- |
6613 |
|
--- |
| 6614 |
// Set source to shift source. |
--- |
6614 |
// Set source to shift source. |
--- |
| 6615 |
Src = Src.getOperand(0); |
0 |
6615 |
Src = Src.getOperand(0); |
0 |
| 6616 |
|
--- |
6616 |
|
--- |
| 6617 |
// Try again to find a 'not' op. |
--- |
6617 |
// Try again to find a 'not' op. |
--- |
| 6618 |
// TODO: Should we favor test+set even with two 'not' ops? |
--- |
6618 |
// TODO: Should we favor test+set even with two 'not' ops? |
--- |
| 6619 |
if (!FoundNot) { |
0 |
6619 |
if (!FoundNot) { |
0 |
| 6620 |
if (!isBitwiseNot(Src)) |
0 |
6620 |
if (!isBitwiseNot(Src)) |
0 |
| 6621 |
return SDValue(); |
0 |
6621 |
return SDValue(); |
0 |
| 6622 |
Src = Src.getOperand(0); |
0 |
6622 |
Src = Src.getOperand(0); |
0 |
| 6623 |
} |
--- |
6623 |
} |
--- |
| 6624 |
|
--- |
6624 |
|
--- |
| 6625 |
if (!TLI.hasBitTest(Src, ShiftAmt)) |
0 |
6625 |
if (!TLI.hasBitTest(Src, ShiftAmt)) |
0 |
| 6626 |
return SDValue(); |
0 |
6626 |
return SDValue(); |
0 |
| 6627 |
|
--- |
6627 |
|
--- |
| 6628 |
// Turn this into a bit-test pattern using mask op + setcc: |
--- |
6628 |
// Turn this into a bit-test pattern using mask op + setcc: |
--- |
| 6629 |
// and (not (srl X, C)), 1 --> (and X, 1<
| --- |
6629 |
// and (not (srl X, C)), 1 --> (and X, 1<
| --- |
| |
| 6630 |
// and (srl (not X), C)), 1 --> (and X, 1<
| --- |
6630 |
// and (srl (not X), C)), 1 --> (and X, 1<
| --- |
| |
| 6631 |
SDLoc DL(And); |
0 |
6631 |
SDLoc DL(And); |
0 |
| 6632 |
SDValue X = DAG.getZExtOrTrunc(Src, DL, SrcVT); |
0 |
6632 |
SDValue X = DAG.getZExtOrTrunc(Src, DL, SrcVT); |
0 |
| 6633 |
EVT CCVT = |
--- |
6633 |
EVT CCVT = |
--- |
| 6634 |
TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT); |
0 |
6634 |
TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT); |
0 |
| 6635 |
SDValue Mask = DAG.getConstant( |
0 |
6635 |
SDValue Mask = DAG.getConstant( |
0 |
| 6636 |
APInt::getOneBitSet(BitWidth, ShiftAmtC->getZExtValue()), DL, SrcVT); |
0 |
6636 |
APInt::getOneBitSet(BitWidth, ShiftAmtC->getZExtValue()), DL, SrcVT); |
0 |
| 6637 |
SDValue NewAnd = DAG.getNode(ISD::AND, DL, SrcVT, X, Mask); |
0 |
6637 |
SDValue NewAnd = DAG.getNode(ISD::AND, DL, SrcVT, X, Mask); |
0 |
| 6638 |
SDValue Zero = DAG.getConstant(0, DL, SrcVT); |
0 |
6638 |
SDValue Zero = DAG.getConstant(0, DL, SrcVT); |
0 |
| 6639 |
SDValue Setcc = DAG.getSetCC(DL, CCVT, NewAnd, Zero, ISD::SETEQ); |
0 |
6639 |
SDValue Setcc = DAG.getSetCC(DL, CCVT, NewAnd, Zero, ISD::SETEQ); |
0 |
| 6640 |
return DAG.getZExtOrTrunc(Setcc, DL, And->getValueType(0)); |
0 |
6640 |
return DAG.getZExtOrTrunc(Setcc, DL, And->getValueType(0)); |
0 |
| 6641 |
} |
0 |
6641 |
} |
0 |
| 6642 |
|
--- |
6642 |
|
--- |
| 6643 |
/// For targets that support usubsat, match a bit-hack form of that operation |
--- |
6643 |
/// For targets that support usubsat, match a bit-hack form of that operation |
--- |
| 6644 |
/// that ends in 'and' and convert it. |
--- |
6644 |
/// that ends in 'and' and convert it. |
--- |
| 6645 |
static SDValue foldAndToUsubsat(SDNode *N, SelectionDAG &DAG) { |
0 |
6645 |
static SDValue foldAndToUsubsat(SDNode *N, SelectionDAG &DAG) { |
0 |
| 6646 |
SDValue N0 = N->getOperand(0); |
0 |
6646 |
SDValue N0 = N->getOperand(0); |
0 |
| 6647 |
SDValue N1 = N->getOperand(1); |
0 |
6647 |
SDValue N1 = N->getOperand(1); |
0 |
| 6648 |
EVT VT = N1.getValueType(); |
0 |
6648 |
EVT VT = N1.getValueType(); |
0 |
| 6649 |
|
--- |
6649 |
|
--- |
| 6650 |
// Canonicalize SRA as operand 1. |
--- |
6650 |
// Canonicalize SRA as operand 1. |
--- |
| 6651 |
if (N0.getOpcode() == ISD::SRA) |
0 |
6651 |
if (N0.getOpcode() == ISD::SRA) |
0 |
| 6652 |
std::swap(N0, N1); |
0 |
6652 |
std::swap(N0, N1); |
0 |
| 6653 |
|
--- |
6653 |
|
--- |
| 6654 |
// xor/add with SMIN (signmask) are logically equivalent. |
--- |
6654 |
// xor/add with SMIN (signmask) are logically equivalent. |
--- |
| 6655 |
if (N0.getOpcode() != ISD::XOR && N0.getOpcode() != ISD::ADD) |
0 |
6655 |
if (N0.getOpcode() != ISD::XOR && N0.getOpcode() != ISD::ADD) |
0 |
| 6656 |
return SDValue(); |
0 |
6656 |
return SDValue(); |
0 |
| 6657 |
|
--- |
6657 |
|
--- |
| 6658 |
if (N1.getOpcode() != ISD::SRA || !N0.hasOneUse() || !N1.hasOneUse() || |
0 |
6658 |
if (N1.getOpcode() != ISD::SRA || !N0.hasOneUse() || !N1.hasOneUse() || |
0 |
| 6659 |
N0.getOperand(0) != N1.getOperand(0)) |
0 |
6659 |
N0.getOperand(0) != N1.getOperand(0)) |
0 |
| 6660 |
return SDValue(); |
0 |
6660 |
return SDValue(); |
0 |
| 6661 |
|
--- |
6661 |
|
--- |
| 6662 |
unsigned BitWidth = VT.getScalarSizeInBits(); |
0 |
6662 |
unsigned BitWidth = VT.getScalarSizeInBits(); |
0 |
| 6663 |
ConstantSDNode *XorC = isConstOrConstSplat(N0.getOperand(1), true); |
0 |
6663 |
ConstantSDNode *XorC = isConstOrConstSplat(N0.getOperand(1), true); |
0 |
| 6664 |
ConstantSDNode *SraC = isConstOrConstSplat(N1.getOperand(1), true); |
0 |
6664 |
ConstantSDNode *SraC = isConstOrConstSplat(N1.getOperand(1), true); |
0 |
| 6665 |
if (!XorC || !XorC->getAPIntValue().isSignMask() || |
0 |
6665 |
if (!XorC || !XorC->getAPIntValue().isSignMask() || |
0 |
| 6666 |
!SraC || SraC->getAPIntValue() != BitWidth - 1) |
0 |
6666 |
!SraC || SraC->getAPIntValue() != BitWidth - 1) |
0 |
| 6667 |
return SDValue(); |
0 |
6667 |
return SDValue(); |
0 |
| 6668 |
|
--- |
6668 |
|
--- |
| 6669 |
// (i8 X ^ 128) & (i8 X s>> 7) --> usubsat X, 128 |
--- |
6669 |
// (i8 X ^ 128) & (i8 X s>> 7) --> usubsat X, 128 |
--- |
| 6670 |
// (i8 X + 128) & (i8 X s>> 7) --> usubsat X, 128 |
--- |
6670 |
// (i8 X + 128) & (i8 X s>> 7) --> usubsat X, 128 |
--- |
| 6671 |
SDLoc DL(N); |
0 |
6671 |
SDLoc DL(N); |
0 |
| 6672 |
SDValue SignMask = DAG.getConstant(XorC->getAPIntValue(), DL, VT); |
0 |
6672 |
SDValue SignMask = DAG.getConstant(XorC->getAPIntValue(), DL, VT); |
0 |
| 6673 |
return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0), SignMask); |
0 |
6673 |
return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0), SignMask); |
0 |
| 6674 |
} |
0 |
6674 |
} |
0 |
| 6675 |
|
--- |
6675 |
|
--- |
| 6676 |
/// Given a bitwise logic operation N with a matching bitwise logic operand, |
--- |
6676 |
/// Given a bitwise logic operation N with a matching bitwise logic operand, |
--- |
| 6677 |
/// fold a pattern where 2 of the source operands are identically shifted |
--- |
6677 |
/// fold a pattern where 2 of the source operands are identically shifted |
--- |
| 6678 |
/// values. For example: |
--- |
6678 |
/// values. For example: |
--- |
| 6679 |
/// ((X0 << Y) | Z) | (X1 << Y) --> ((X0 | X1) << Y) | Z |
--- |
6679 |
/// ((X0 << Y) | Z) | (X1 << Y) --> ((X0 | X1) << Y) | Z |
--- |
| 6680 |
static SDValue foldLogicOfShifts(SDNode *N, SDValue LogicOp, SDValue ShiftOp, |
2 |
6680 |
static SDValue foldLogicOfShifts(SDNode *N, SDValue LogicOp, SDValue ShiftOp, |
2 |
| 6681 |
SelectionDAG &DAG) { |
--- |
6681 |
SelectionDAG &DAG) { |
--- |
| 6682 |
unsigned LogicOpcode = N->getOpcode(); |
2 |
6682 |
unsigned LogicOpcode = N->getOpcode(); |
2 |
| 6683 |
assert(ISD::isBitwiseLogicOp(LogicOpcode) && |
2 |
6683 |
assert(ISD::isBitwiseLogicOp(LogicOpcode) && |
2 |
| 6684 |
"Expected bitwise logic operation"); |
--- |
6684 |
"Expected bitwise logic operation"); |
--- |
| 6685 |
|
--- |
6685 |
|
--- |
| 6686 |
if (!LogicOp.hasOneUse() || !ShiftOp.hasOneUse()) |
2 |
6686 |
if (!LogicOp.hasOneUse() || !ShiftOp.hasOneUse()) |
2 |
| 6687 |
return SDValue(); |
0 |
6687 |
return SDValue(); |
0 |
| 6688 |
|
--- |
6688 |
|
--- |
| 6689 |
// Match another bitwise logic op and a shift. |
--- |
6689 |
// Match another bitwise logic op and a shift. |
--- |
| 6690 |
unsigned ShiftOpcode = ShiftOp.getOpcode(); |
2 |
6690 |
unsigned ShiftOpcode = ShiftOp.getOpcode(); |
2 |
| 6691 |
if (LogicOp.getOpcode() != LogicOpcode || |
2 |
6691 |
if (LogicOp.getOpcode() != LogicOpcode || |
2 |
| 6692 |
!(ShiftOpcode == ISD::SHL || ShiftOpcode == ISD::SRL || |
0 |
6692 |
!(ShiftOpcode == ISD::SHL || ShiftOpcode == ISD::SRL || |
0 |
| 6693 |
ShiftOpcode == ISD::SRA)) |
--- |
6693 |
ShiftOpcode == ISD::SRA)) |
--- |
| 6694 |
return SDValue(); |
2 |
6694 |
return SDValue(); |
2 |
| 6695 |
|
--- |
6695 |
|
--- |
| 6696 |
// Match another shift op inside the first logic operand. Handle both commuted |
--- |
6696 |
// Match another shift op inside the first logic operand. Handle both commuted |
--- |
| 6697 |
// possibilities. |
--- |
6697 |
// possibilities. |
--- |
| 6698 |
// LOGIC (LOGIC (SH X0, Y), Z), (SH X1, Y) --> LOGIC (SH (LOGIC X0, X1), Y), Z |
--- |
6698 |
// LOGIC (LOGIC (SH X0, Y), Z), (SH X1, Y) --> LOGIC (SH (LOGIC X0, X1), Y), Z |
--- |
| 6699 |
// LOGIC (LOGIC Z, (SH X0, Y)), (SH X1, Y) --> LOGIC (SH (LOGIC X0, X1), Y), Z |
--- |
6699 |
// LOGIC (LOGIC Z, (SH X0, Y)), (SH X1, Y) --> LOGIC (SH (LOGIC X0, X1), Y), Z |
--- |
| 6700 |
SDValue X1 = ShiftOp.getOperand(0); |
0 |
6700 |
SDValue X1 = ShiftOp.getOperand(0); |
0 |
| 6701 |
SDValue Y = ShiftOp.getOperand(1); |
0 |
6701 |
SDValue Y = ShiftOp.getOperand(1); |
0 |
| 6702 |
SDValue X0, Z; |
0 |
6702 |
SDValue X0, Z; |
0 |
| 6703 |
if (LogicOp.getOperand(0).getOpcode() == ShiftOpcode && |
0 |
6703 |
if (LogicOp.getOperand(0).getOpcode() == ShiftOpcode && |
0 |
| 6704 |
LogicOp.getOperand(0).getOperand(1) == Y) { |
0 |
6704 |
LogicOp.getOperand(0).getOperand(1) == Y) { |
0 |
| 6705 |
X0 = LogicOp.getOperand(0).getOperand(0); |
0 |
6705 |
X0 = LogicOp.getOperand(0).getOperand(0); |
0 |
| 6706 |
Z = LogicOp.getOperand(1); |
0 |
6706 |
Z = LogicOp.getOperand(1); |
0 |
| 6707 |
} else if (LogicOp.getOperand(1).getOpcode() == ShiftOpcode && |
0 |
6707 |
} else if (LogicOp.getOperand(1).getOpcode() == ShiftOpcode && |
0 |
| 6708 |
LogicOp.getOperand(1).getOperand(1) == Y) { |
0 |
6708 |
LogicOp.getOperand(1).getOperand(1) == Y) { |
0 |
| 6709 |
X0 = LogicOp.getOperand(1).getOperand(0); |
0 |
6709 |
X0 = LogicOp.getOperand(1).getOperand(0); |
0 |
| 6710 |
Z = LogicOp.getOperand(0); |
0 |
6710 |
Z = LogicOp.getOperand(0); |
0 |
| 6711 |
} else { |
--- |
6711 |
} else { |
--- |
| 6712 |
return SDValue(); |
0 |
6712 |
return SDValue(); |
0 |
| 6713 |
} |
--- |
6713 |
} |
--- |
| 6714 |
|
--- |
6714 |
|
--- |
| 6715 |
EVT VT = N->getValueType(0); |
0 |
6715 |
EVT VT = N->getValueType(0); |
0 |
| 6716 |
SDLoc DL(N); |
0 |
6716 |
SDLoc DL(N); |
0 |
| 6717 |
SDValue LogicX = DAG.getNode(LogicOpcode, DL, VT, X0, X1); |
0 |
6717 |
SDValue LogicX = DAG.getNode(LogicOpcode, DL, VT, X0, X1); |
0 |
| 6718 |
SDValue NewShift = DAG.getNode(ShiftOpcode, DL, VT, LogicX, Y); |
0 |
6718 |
SDValue NewShift = DAG.getNode(ShiftOpcode, DL, VT, LogicX, Y); |
0 |
| 6719 |
return DAG.getNode(LogicOpcode, DL, VT, NewShift, Z); |
0 |
6719 |
return DAG.getNode(LogicOpcode, DL, VT, NewShift, Z); |
0 |
| 6720 |
} |
0 |
6720 |
} |
0 |
| 6721 |
|
--- |
6721 |
|
--- |
| 6722 |
/// Given a tree of logic operations with shape like |
--- |
6722 |
/// Given a tree of logic operations with shape like |
--- |
| 6723 |
/// (LOGIC (LOGIC (X, Y), LOGIC (Z, Y))) |
--- |
6723 |
/// (LOGIC (LOGIC (X, Y), LOGIC (Z, Y))) |
--- |
| 6724 |
/// try to match and fold shift operations with the same shift amount. |
--- |
6724 |
/// try to match and fold shift operations with the same shift amount. |
--- |
| 6725 |
/// For example: |
--- |
6725 |
/// For example: |
--- |
| 6726 |
/// LOGIC (LOGIC (SH X0, Y), Z), (LOGIC (SH X1, Y), W) --> |
--- |
6726 |
/// LOGIC (LOGIC (SH X0, Y), Z), (LOGIC (SH X1, Y), W) --> |
--- |
| 6727 |
/// --> LOGIC (SH (LOGIC X0, X1), Y), (LOGIC Z, W) |
--- |
6727 |
/// --> LOGIC (SH (LOGIC X0, X1), Y), (LOGIC Z, W) |
--- |
| 6728 |
static SDValue foldLogicTreeOfShifts(SDNode *N, SDValue LeftHand, |
0 |
6728 |
static SDValue foldLogicTreeOfShifts(SDNode *N, SDValue LeftHand, |
0 |
| 6729 |
SDValue RightHand, SelectionDAG &DAG) { |
--- |
6729 |
SDValue RightHand, SelectionDAG &DAG) { |
--- |
| 6730 |
unsigned LogicOpcode = N->getOpcode(); |
0 |
6730 |
unsigned LogicOpcode = N->getOpcode(); |
0 |
| 6731 |
assert(ISD::isBitwiseLogicOp(LogicOpcode) && |
0 |
6731 |
assert(ISD::isBitwiseLogicOp(LogicOpcode) && |
0 |
| 6732 |
"Expected bitwise logic operation"); |
--- |
6732 |
"Expected bitwise logic operation"); |
--- |
| 6733 |
if (LeftHand.getOpcode() != LogicOpcode || |
0 |
6733 |
if (LeftHand.getOpcode() != LogicOpcode || |
0 |
| 6734 |
RightHand.getOpcode() != LogicOpcode) |
0 |
6734 |
RightHand.getOpcode() != LogicOpcode) |
0 |
| 6735 |
return SDValue(); |
0 |
6735 |
return SDValue(); |
0 |
| 6736 |
if (!LeftHand.hasOneUse() || !RightHand.hasOneUse()) |
0 |
6736 |
if (!LeftHand.hasOneUse() || !RightHand.hasOneUse()) |
0 |
| 6737 |
return SDValue(); |
0 |
6737 |
return SDValue(); |
0 |
| 6738 |
|
--- |
6738 |
|
--- |
| 6739 |
// Try to match one of following patterns: |
--- |
6739 |
// Try to match one of following patterns: |
--- |
| 6740 |
// LOGIC (LOGIC (SH X0, Y), Z), (LOGIC (SH X1, Y), W) |
--- |
6740 |
// LOGIC (LOGIC (SH X0, Y), Z), (LOGIC (SH X1, Y), W) |
--- |
| 6741 |
// LOGIC (LOGIC (SH X0, Y), Z), (LOGIC W, (SH X1, Y)) |
--- |
6741 |
// LOGIC (LOGIC (SH X0, Y), Z), (LOGIC W, (SH X1, Y)) |
--- |
| 6742 |
// Note that foldLogicOfShifts will handle commuted versions of the left hand |
--- |
6742 |
// Note that foldLogicOfShifts will handle commuted versions of the left hand |
--- |
| 6743 |
// itself. |
--- |
6743 |
// itself. |
--- |
| 6744 |
SDValue CombinedShifts, W; |
0 |
6744 |
SDValue CombinedShifts, W; |
0 |
| 6745 |
SDValue R0 = RightHand.getOperand(0); |
0 |
6745 |
SDValue R0 = RightHand.getOperand(0); |
0 |
| 6746 |
SDValue R1 = RightHand.getOperand(1); |
0 |
6746 |
SDValue R1 = RightHand.getOperand(1); |
0 |
| 6747 |
if ((CombinedShifts = foldLogicOfShifts(N, LeftHand, R0, DAG))) |
0 |
6747 |
if ((CombinedShifts = foldLogicOfShifts(N, LeftHand, R0, DAG))) |
0 |
| 6748 |
W = R1; |
0 |
6748 |
W = R1; |
0 |
| 6749 |
else if ((CombinedShifts = foldLogicOfShifts(N, LeftHand, R1, DAG))) |
0 |
6749 |
else if ((CombinedShifts = foldLogicOfShifts(N, LeftHand, R1, DAG))) |
0 |
| 6750 |
W = R0; |
0 |
6750 |
W = R0; |
0 |
| 6751 |
else |
--- |
6751 |
else |
--- |
| 6752 |
return SDValue(); |
0 |
6752 |
return SDValue(); |
0 |
| 6753 |
|
--- |
6753 |
|
--- |
| 6754 |
EVT VT = N->getValueType(0); |
0 |
6754 |
EVT VT = N->getValueType(0); |
0 |
| 6755 |
SDLoc DL(N); |
0 |
6755 |
SDLoc DL(N); |
0 |
| 6756 |
return DAG.getNode(LogicOpcode, DL, VT, CombinedShifts, W); |
0 |
6756 |
return DAG.getNode(LogicOpcode, DL, VT, CombinedShifts, W); |
0 |
| 6757 |
} |
0 |
6757 |
} |
0 |
| 6758 |
|
--- |
6758 |
|
--- |
| 6759 |
SDValue DAGCombiner::visitAND(SDNode *N) { |
1 |
6759 |
SDValue DAGCombiner::visitAND(SDNode *N) { |
1 |
| 6760 |
SDValue N0 = N->getOperand(0); |
1 |
6760 |
SDValue N0 = N->getOperand(0); |
1 |
| 6761 |
SDValue N1 = N->getOperand(1); |
1 |
6761 |
SDValue N1 = N->getOperand(1); |
1 |
| 6762 |
EVT VT = N1.getValueType(); |
1 |
6762 |
EVT VT = N1.getValueType(); |
1 |
| 6763 |
|
--- |
6763 |
|
--- |
| 6764 |
// x & x --> x |
--- |
6764 |
// x & x --> x |
--- |
| 6765 |
if (N0 == N1) |
1 |
6765 |
if (N0 == N1) |
1 |
| 6766 |
return N0; |
0 |
6766 |
return N0; |
0 |
| 6767 |
|
--- |
6767 |
|
--- |
| 6768 |
// fold (and c1, c2) -> c1&c2 |
--- |
6768 |
// fold (and c1, c2) -> c1&c2 |
--- |
| 6769 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, {N0, N1})) |
1 |
6769 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, {N0, N1})) |
1 |
| 6770 |
return C; |
0 |
6770 |
return C; |
0 |
| 6771 |
|
--- |
6771 |
|
--- |
| 6772 |
// canonicalize constant to RHS |
--- |
6772 |
// canonicalize constant to RHS |
--- |
| 6773 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
1 |
6773 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
1 |
| 6774 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
6774 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 6775 |
return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0); |
0 |
6775 |
return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0); |
0 |
| 6776 |
|
--- |
6776 |
|
--- |
| 6777 |
if (areBitwiseNotOfEachother(N0, N1)) |
1 |
6777 |
if (areBitwiseNotOfEachother(N0, N1)) |
1 |
| 6778 |
return DAG.getConstant(APInt::getZero(VT.getScalarSizeInBits()), SDLoc(N), |
0 |
6778 |
return DAG.getConstant(APInt::getZero(VT.getScalarSizeInBits()), SDLoc(N), |
0 |
| 6779 |
VT); |
0 |
6779 |
VT); |
0 |
| 6780 |
|
--- |
6780 |
|
--- |
| 6781 |
// fold vector ops |
--- |
6781 |
// fold vector ops |
--- |
| 6782 |
if (VT.isVector()) { |
1 |
6782 |
if (VT.isVector()) { |
1 |
| 6783 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N))) |
0 |
6783 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N))) |
0 |
| 6784 |
return FoldedVOp; |
0 |
6784 |
return FoldedVOp; |
0 |
| 6785 |
|
--- |
6785 |
|
--- |
| 6786 |
// fold (and x, 0) -> 0, vector edition |
--- |
6786 |
// fold (and x, 0) -> 0, vector edition |
--- |
| 6787 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
6787 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
| 6788 |
// do not return N1, because undef node may exist in N1 |
--- |
6788 |
// do not return N1, because undef node may exist in N1 |
--- |
| 6789 |
return DAG.getConstant(APInt::getZero(N1.getScalarValueSizeInBits()), |
0 |
6789 |
return DAG.getConstant(APInt::getZero(N1.getScalarValueSizeInBits()), |
0 |
| 6790 |
SDLoc(N), N1.getValueType()); |
0 |
6790 |
SDLoc(N), N1.getValueType()); |
0 |
| 6791 |
|
--- |
6791 |
|
--- |
| 6792 |
// fold (and x, -1) -> x, vector edition |
--- |
6792 |
// fold (and x, -1) -> x, vector edition |
--- |
| 6793 |
if (ISD::isConstantSplatVectorAllOnes(N1.getNode())) |
0 |
6793 |
if (ISD::isConstantSplatVectorAllOnes(N1.getNode())) |
0 |
| 6794 |
return N0; |
0 |
6794 |
return N0; |
0 |
| 6795 |
|
--- |
6795 |
|
--- |
| 6796 |
// fold (and (masked_load) (splat_vec (x, ...))) to zext_masked_load |
--- |
6796 |
// fold (and (masked_load) (splat_vec (x, ...))) to zext_masked_load |
--- |
| 6797 |
auto *MLoad = dyn_cast(N0); |
0 |
6797 |
auto *MLoad = dyn_cast(N0); |
0 |
| 6798 |
ConstantSDNode *Splat = isConstOrConstSplat(N1, true, true); |
0 |
6798 |
ConstantSDNode *Splat = isConstOrConstSplat(N1, true, true); |
0 |
| 6799 |
if (MLoad && MLoad->getExtensionType() == ISD::EXTLOAD && Splat && |
0 |
6799 |
if (MLoad && MLoad->getExtensionType() == ISD::EXTLOAD && Splat && |
0 |
| 6800 |
N1.hasOneUse()) { |
0 |
6800 |
N1.hasOneUse()) { |
0 |
| 6801 |
EVT LoadVT = MLoad->getMemoryVT(); |
0 |
6801 |
EVT LoadVT = MLoad->getMemoryVT(); |
0 |
| 6802 |
EVT ExtVT = VT; |
0 |
6802 |
EVT ExtVT = VT; |
0 |
| 6803 |
if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) { |
0 |
6803 |
if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) { |
0 |
| 6804 |
// For this AND to be a zero extension of the masked load the elements |
--- |
6804 |
// For this AND to be a zero extension of the masked load the elements |
--- |
| 6805 |
// of the BuildVec must mask the bottom bits of the extended element |
--- |
6805 |
// of the BuildVec must mask the bottom bits of the extended element |
--- |
| 6806 |
// type |
--- |
6806 |
// type |
--- |
| 6807 |
uint64_t ElementSize = |
--- |
6807 |
uint64_t ElementSize = |
--- |
| 6808 |
LoadVT.getVectorElementType().getScalarSizeInBits(); |
0 |
6808 |
LoadVT.getVectorElementType().getScalarSizeInBits(); |
0 |
| 6809 |
if (Splat->getAPIntValue().isMask(ElementSize)) { |
0 |
6809 |
if (Splat->getAPIntValue().isMask(ElementSize)) { |
0 |
| 6810 |
auto NewLoad = DAG.getMaskedLoad( |
0 |
6810 |
auto NewLoad = DAG.getMaskedLoad( |
0 |
| 6811 |
ExtVT, SDLoc(N), MLoad->getChain(), MLoad->getBasePtr(), |
0 |
6811 |
ExtVT, SDLoc(N), MLoad->getChain(), MLoad->getBasePtr(), |
0 |
| 6812 |
MLoad->getOffset(), MLoad->getMask(), MLoad->getPassThru(), |
0 |
6812 |
MLoad->getOffset(), MLoad->getMask(), MLoad->getPassThru(), |
0 |
| 6813 |
LoadVT, MLoad->getMemOperand(), MLoad->getAddressingMode(), |
--- |
6813 |
LoadVT, MLoad->getMemOperand(), MLoad->getAddressingMode(), |
--- |
| 6814 |
ISD::ZEXTLOAD, MLoad->isExpandingLoad()); |
0 |
6814 |
ISD::ZEXTLOAD, MLoad->isExpandingLoad()); |
0 |
| 6815 |
bool LoadHasOtherUsers = !N0.hasOneUse(); |
0 |
6815 |
bool LoadHasOtherUsers = !N0.hasOneUse(); |
0 |
| 6816 |
CombineTo(N, NewLoad); |
0 |
6816 |
CombineTo(N, NewLoad); |
0 |
| 6817 |
if (LoadHasOtherUsers) |
0 |
6817 |
if (LoadHasOtherUsers) |
0 |
| 6818 |
CombineTo(MLoad, NewLoad.getValue(0), NewLoad.getValue(1)); |
0 |
6818 |
CombineTo(MLoad, NewLoad.getValue(0), NewLoad.getValue(1)); |
0 |
| 6819 |
return SDValue(N, 0); |
0 |
6819 |
return SDValue(N, 0); |
0 |
| 6820 |
} |
--- |
6820 |
} |
--- |
| 6821 |
} |
--- |
6821 |
} |
--- |
| 6822 |
} |
--- |
6822 |
} |
--- |
| 6823 |
} |
--- |
6823 |
} |
--- |
| 6824 |
|
--- |
6824 |
|
--- |
| 6825 |
// fold (and x, -1) -> x |
--- |
6825 |
// fold (and x, -1) -> x |
--- |
| 6826 |
if (isAllOnesConstant(N1)) |
1 |
6826 |
if (isAllOnesConstant(N1)) |
1 |
| 6827 |
return N0; |
0 |
6827 |
return N0; |
0 |
| 6828 |
|
--- |
6828 |
|
--- |
| 6829 |
// if (and x, c) is known to be zero, return 0 |
--- |
6829 |
// if (and x, c) is known to be zero, return 0 |
--- |
| 6830 |
unsigned BitWidth = VT.getScalarSizeInBits(); |
1 |
6830 |
unsigned BitWidth = VT.getScalarSizeInBits(); |
1 |
| 6831 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
1 |
6831 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
1 |
| 6832 |
if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(BitWidth))) |
1 |
6832 |
if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(BitWidth))) |
1 |
| 6833 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
6833 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
| 6834 |
|
--- |
6834 |
|
--- |
| 6835 |
if (SDValue R = foldAndOrOfSETCC(N, DAG)) |
1 |
6835 |
if (SDValue R = foldAndOrOfSETCC(N, DAG)) |
1 |
| 6836 |
return R; |
0 |
6836 |
return R; |
0 |
| 6837 |
|
--- |
6837 |
|
--- |
| 6838 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
1 |
6838 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
1 |
| 6839 |
return NewSel; |
0 |
6839 |
return NewSel; |
0 |
| 6840 |
|
--- |
6840 |
|
--- |
| 6841 |
// reassociate and |
--- |
6841 |
// reassociate and |
--- |
| 6842 |
if (SDValue RAND = reassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags())) |
1 |
6842 |
if (SDValue RAND = reassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags())) |
1 |
| 6843 |
return RAND; |
0 |
6843 |
return RAND; |
0 |
| 6844 |
|
--- |
6844 |
|
--- |
| 6845 |
// Fold and(vecreduce(x), vecreduce(y)) -> vecreduce(and(x, y)) |
--- |
6845 |
// Fold and(vecreduce(x), vecreduce(y)) -> vecreduce(and(x, y)) |
--- |
| 6846 |
if (SDValue SD = reassociateReduction(ISD::VECREDUCE_AND, ISD::AND, SDLoc(N), |
2 |
6846 |
if (SDValue SD = reassociateReduction(ISD::VECREDUCE_AND, ISD::AND, SDLoc(N), |
2 |
| 6847 |
VT, N0, N1)) |
1 |
6847 |
VT, N0, N1)) |
1 |
| 6848 |
return SD; |
0 |
6848 |
return SD; |
0 |
| 6849 |
|
--- |
6849 |
|
--- |
| 6850 |
// fold (and (or x, C), D) -> D if (C & D) == D |
--- |
6850 |
// fold (and (or x, C), D) -> D if (C & D) == D |
--- |
| 6851 |
auto MatchSubset = [](ConstantSDNode *LHS, ConstantSDNode *RHS) { |
0 |
6851 |
auto MatchSubset = [](ConstantSDNode *LHS, ConstantSDNode *RHS) { |
0 |
| 6852 |
return RHS->getAPIntValue().isSubsetOf(LHS->getAPIntValue()); |
0 |
6852 |
return RHS->getAPIntValue().isSubsetOf(LHS->getAPIntValue()); |
0 |
| 6853 |
}; |
--- |
6853 |
}; |
--- |
| 6854 |
if (N0.getOpcode() == ISD::OR && |
1 |
6854 |
if (N0.getOpcode() == ISD::OR && |
1 |
| 6855 |
ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchSubset)) |
1 |
6855 |
ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchSubset)) |
1 |
| 6856 |
return N1; |
0 |
6856 |
return N1; |
0 |
| 6857 |
|
--- |
6857 |
|
--- |
| 6858 |
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { |
1 |
6858 |
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { |
1 |
| 6859 |
SDValue N0Op0 = N0.getOperand(0); |
0 |
6859 |
SDValue N0Op0 = N0.getOperand(0); |
0 |
| 6860 |
EVT SrcVT = N0Op0.getValueType(); |
0 |
6860 |
EVT SrcVT = N0Op0.getValueType(); |
0 |
| 6861 |
unsigned SrcBitWidth = SrcVT.getScalarSizeInBits(); |
0 |
6861 |
unsigned SrcBitWidth = SrcVT.getScalarSizeInBits(); |
0 |
| 6862 |
APInt Mask = ~N1C->getAPIntValue(); |
0 |
6862 |
APInt Mask = ~N1C->getAPIntValue(); |
0 |
| 6863 |
Mask = Mask.trunc(SrcBitWidth); |
0 |
6863 |
Mask = Mask.trunc(SrcBitWidth); |
0 |
| 6864 |
|
--- |
6864 |
|
--- |
| 6865 |
// fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. |
--- |
6865 |
// fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. |
--- |
| 6866 |
if (DAG.MaskedValueIsZero(N0Op0, Mask)) |
0 |
6866 |
if (DAG.MaskedValueIsZero(N0Op0, Mask)) |
0 |
| 6867 |
return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0Op0); |
0 |
6867 |
return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0Op0); |
0 |
| 6868 |
|
--- |
6868 |
|
--- |
| 6869 |
// fold (and (any_ext V), c) -> (zero_ext (and (trunc V), c)) if profitable. |
--- |
6869 |
// fold (and (any_ext V), c) -> (zero_ext (and (trunc V), c)) if profitable. |
--- |
| 6870 |
if (N1C->getAPIntValue().countLeadingZeros() >= (BitWidth - SrcBitWidth) && |
0 |
6870 |
if (N1C->getAPIntValue().countLeadingZeros() >= (BitWidth - SrcBitWidth) && |
0 |
| 6871 |
TLI.isTruncateFree(VT, SrcVT) && TLI.isZExtFree(SrcVT, VT) && |
0 |
6871 |
TLI.isTruncateFree(VT, SrcVT) && TLI.isZExtFree(SrcVT, VT) && |
0 |
| 6872 |
TLI.isTypeDesirableForOp(ISD::AND, SrcVT) && |
0 |
6872 |
TLI.isTypeDesirableForOp(ISD::AND, SrcVT) && |
0 |
| 6873 |
TLI.isNarrowingProfitable(VT, SrcVT)) { |
0 |
6873 |
TLI.isNarrowingProfitable(VT, SrcVT)) { |
0 |
| 6874 |
SDLoc DL(N); |
0 |
6874 |
SDLoc DL(N); |
0 |
| 6875 |
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, |
0 |
6875 |
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, |
0 |
| 6876 |
DAG.getNode(ISD::AND, DL, SrcVT, N0Op0, |
0 |
6876 |
DAG.getNode(ISD::AND, DL, SrcVT, N0Op0, |
0 |
| 6877 |
DAG.getZExtOrTrunc(N1, DL, SrcVT))); |
0 |
6877 |
DAG.getZExtOrTrunc(N1, DL, SrcVT))); |
0 |
| 6878 |
} |
0 |
6878 |
} |
0 |
| 6879 |
} |
0 |
6879 |
} |
0 |
| 6880 |
|
--- |
6880 |
|
--- |
| 6881 |
// fold (and (ext (and V, c1)), c2) -> (and (ext V), (and c1, (ext c2))) |
--- |
6881 |
// fold (and (ext (and V, c1)), c2) -> (and (ext V), (and c1, (ext c2))) |
--- |
| 6882 |
if (ISD::isExtOpcode(N0.getOpcode())) { |
1 |
6882 |
if (ISD::isExtOpcode(N0.getOpcode())) { |
1 |
| 6883 |
unsigned ExtOpc = N0.getOpcode(); |
0 |
6883 |
unsigned ExtOpc = N0.getOpcode(); |
0 |
| 6884 |
SDValue N0Op0 = N0.getOperand(0); |
0 |
6884 |
SDValue N0Op0 = N0.getOperand(0); |
0 |
| 6885 |
if (N0Op0.getOpcode() == ISD::AND && |
0 |
6885 |
if (N0Op0.getOpcode() == ISD::AND && |
0 |
| 6886 |
(ExtOpc != ISD::ZERO_EXTEND || !TLI.isZExtFree(N0Op0, VT)) && |
0 |
6886 |
(ExtOpc != ISD::ZERO_EXTEND || !TLI.isZExtFree(N0Op0, VT)) && |
0 |
| 6887 |
DAG.isConstantIntBuildVectorOrConstantInt(N1) && |
0 |
6887 |
DAG.isConstantIntBuildVectorOrConstantInt(N1) && |
0 |
| 6888 |
DAG.isConstantIntBuildVectorOrConstantInt(N0Op0.getOperand(1)) && |
0 |
6888 |
DAG.isConstantIntBuildVectorOrConstantInt(N0Op0.getOperand(1)) && |
0 |
| 6889 |
N0->hasOneUse() && N0Op0->hasOneUse()) { |
0 |
6889 |
N0->hasOneUse() && N0Op0->hasOneUse()) { |
0 |
| 6890 |
SDLoc DL(N); |
0 |
6890 |
SDLoc DL(N); |
0 |
| 6891 |
SDValue NewMask = |
--- |
6891 |
SDValue NewMask = |
--- |
| 6892 |
DAG.getNode(ISD::AND, DL, VT, N1, |
0 |
6892 |
DAG.getNode(ISD::AND, DL, VT, N1, |
0 |
| 6893 |
DAG.getNode(ExtOpc, DL, VT, N0Op0.getOperand(1))); |
0 |
6893 |
DAG.getNode(ExtOpc, DL, VT, N0Op0.getOperand(1))); |
0 |
| 6894 |
return DAG.getNode(ISD::AND, DL, VT, |
0 |
6894 |
return DAG.getNode(ISD::AND, DL, VT, |
0 |
| 6895 |
DAG.getNode(ExtOpc, DL, VT, N0Op0.getOperand(0)), |
0 |
6895 |
DAG.getNode(ExtOpc, DL, VT, N0Op0.getOperand(0)), |
0 |
| 6896 |
NewMask); |
0 |
6896 |
NewMask); |
0 |
| 6897 |
} |
0 |
6897 |
} |
0 |
| 6898 |
} |
--- |
6898 |
} |
--- |
| 6899 |
|
--- |
6899 |
|
--- |
| 6900 |
// similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> |
--- |
6900 |
// similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> |
--- |
| 6901 |
// (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must |
--- |
6901 |
// (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must |
--- |
| 6902 |
// already be zero by virtue of the width of the base type of the load. |
--- |
6902 |
// already be zero by virtue of the width of the base type of the load. |
--- |
| 6903 |
// |
--- |
6903 |
// |
--- |
| 6904 |
// the 'X' node here can either be nothing or an extract_vector_elt to catch |
--- |
6904 |
// the 'X' node here can either be nothing or an extract_vector_elt to catch |
--- |
| 6905 |
// more cases. |
--- |
6905 |
// more cases. |
--- |
| 6906 |
if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
1 |
6906 |
if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
1 |
| 6907 |
N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() && |
0 |
6907 |
N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() && |
0 |
| 6908 |
N0.getOperand(0).getOpcode() == ISD::LOAD && |
0 |
6908 |
N0.getOperand(0).getOpcode() == ISD::LOAD && |
0 |
| 6909 |
N0.getOperand(0).getResNo() == 0) || |
2 |
6909 |
N0.getOperand(0).getResNo() == 0) || |
2 |
| 6910 |
(N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) { |
1 |
6910 |
(N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) { |
1 |
| 6911 |
LoadSDNode *Load = cast( (N0.getOpcode() == ISD::LOAD) ? |
0 |
6911 |
LoadSDNode *Load = cast( (N0.getOpcode() == ISD::LOAD) ? |
0 |
| 6912 |
N0 : N0.getOperand(0) ); |
0 |
6912 |
N0 : N0.getOperand(0) ); |
0 |
| 6913 |
|
--- |
6913 |
|
--- |
| 6914 |
// Get the constant (if applicable) the zero'th operand is being ANDed with. |
--- |
6914 |
// Get the constant (if applicable) the zero'th operand is being ANDed with. |
--- |
| 6915 |
// This can be a pure constant or a vector splat, in which case we treat the |
--- |
6915 |
// This can be a pure constant or a vector splat, in which case we treat the |
--- |
| 6916 |
// vector as a scalar and use the splat value. |
--- |
6916 |
// vector as a scalar and use the splat value. |
--- |
| 6917 |
APInt Constant = APInt::getZero(1); |
0 |
6917 |
APInt Constant = APInt::getZero(1); |
0 |
| 6918 |
if (const ConstantSDNode *C = isConstOrConstSplat( |
0 |
6918 |
if (const ConstantSDNode *C = isConstOrConstSplat( |
0 |
| 6919 |
N1, /*AllowUndef=*/false, /*AllowTruncation=*/true)) { |
--- |
6919 |
N1, /*AllowUndef=*/false, /*AllowTruncation=*/true)) { |
--- |
| 6920 |
Constant = C->getAPIntValue(); |
0 |
6920 |
Constant = C->getAPIntValue(); |
0 |
| 6921 |
} else if (BuildVectorSDNode *Vector = dyn_cast(N1)) { |
0 |
6921 |
} else if (BuildVectorSDNode *Vector = dyn_cast(N1)) { |
0 |
| 6922 |
APInt SplatValue, SplatUndef; |
0 |
6922 |
APInt SplatValue, SplatUndef; |
0 |
| 6923 |
unsigned SplatBitSize; |
--- |
6923 |
unsigned SplatBitSize; |
--- |
| 6924 |
bool HasAnyUndefs; |
--- |
6924 |
bool HasAnyUndefs; |
--- |
| 6925 |
bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, |
0 |
6925 |
bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, |
0 |
| 6926 |
SplatBitSize, HasAnyUndefs); |
--- |
6926 |
SplatBitSize, HasAnyUndefs); |
--- |
| 6927 |
if (IsSplat) { |
0 |
6927 |
if (IsSplat) { |
0 |
| 6928 |
// Undef bits can contribute to a possible optimisation if set, so |
--- |
6928 |
// Undef bits can contribute to a possible optimisation if set, so |
--- |
| 6929 |
// set them. |
--- |
6929 |
// set them. |
--- |
| 6930 |
SplatValue |= SplatUndef; |
0 |
6930 |
SplatValue |= SplatUndef; |
0 |
| 6931 |
|
--- |
6931 |
|
--- |
| 6932 |
// The splat value may be something like "0x00FFFFFF", which means 0 for |
--- |
6932 |
// The splat value may be something like "0x00FFFFFF", which means 0 for |
--- |
| 6933 |
// the first vector value and FF for the rest, repeating. We need a mask |
--- |
6933 |
// the first vector value and FF for the rest, repeating. We need a mask |
--- |
| 6934 |
// that will apply equally to all members of the vector, so AND all the |
--- |
6934 |
// that will apply equally to all members of the vector, so AND all the |
--- |
| 6935 |
// lanes of the constant together. |
--- |
6935 |
// lanes of the constant together. |
--- |
| 6936 |
unsigned EltBitWidth = Vector->getValueType(0).getScalarSizeInBits(); |
0 |
6936 |
unsigned EltBitWidth = Vector->getValueType(0).getScalarSizeInBits(); |
0 |
| 6937 |
|
--- |
6937 |
|
--- |
| 6938 |
// If the splat value has been compressed to a bitlength lower |
--- |
6938 |
// If the splat value has been compressed to a bitlength lower |
--- |
| 6939 |
// than the size of the vector lane, we need to re-expand it to |
--- |
6939 |
// than the size of the vector lane, we need to re-expand it to |
--- |
| 6940 |
// the lane size. |
--- |
6940 |
// the lane size. |
--- |
| 6941 |
if (EltBitWidth > SplatBitSize) |
0 |
6941 |
if (EltBitWidth > SplatBitSize) |
0 |
| 6942 |
for (SplatValue = SplatValue.zextOrTrunc(EltBitWidth); |
0 |
6942 |
for (SplatValue = SplatValue.zextOrTrunc(EltBitWidth); |
0 |
| 6943 |
SplatBitSize < EltBitWidth; SplatBitSize = SplatBitSize * 2) |
0 |
6943 |
SplatBitSize < EltBitWidth; SplatBitSize = SplatBitSize * 2) |
0 |
| 6944 |
SplatValue |= SplatValue.shl(SplatBitSize); |
0 |
6944 |
SplatValue |= SplatValue.shl(SplatBitSize); |
0 |
| 6945 |
|
--- |
6945 |
|
--- |
| 6946 |
// Make sure that variable 'Constant' is only set if 'SplatBitSize' is a |
--- |
6946 |
// Make sure that variable 'Constant' is only set if 'SplatBitSize' is a |
--- |
| 6947 |
// multiple of 'BitWidth'. Otherwise, we could propagate a wrong value. |
--- |
6947 |
// multiple of 'BitWidth'. Otherwise, we could propagate a wrong value. |
--- |
| 6948 |
if ((SplatBitSize % EltBitWidth) == 0) { |
0 |
6948 |
if ((SplatBitSize % EltBitWidth) == 0) { |
0 |
| 6949 |
Constant = APInt::getAllOnes(EltBitWidth); |
0 |
6949 |
Constant = APInt::getAllOnes(EltBitWidth); |
0 |
| 6950 |
for (unsigned i = 0, n = (SplatBitSize / EltBitWidth); i < n; ++i) |
0 |
6950 |
for (unsigned i = 0, n = (SplatBitSize / EltBitWidth); i < n; ++i) |
0 |
| 6951 |
Constant &= SplatValue.extractBits(EltBitWidth, i * EltBitWidth); |
0 |
6951 |
Constant &= SplatValue.extractBits(EltBitWidth, i * EltBitWidth); |
0 |
| 6952 |
} |
--- |
6952 |
} |
--- |
| 6953 |
} |
--- |
6953 |
} |
--- |
| 6954 |
} |
0 |
6954 |
} |
0 |
| 6955 |
|
--- |
6955 |
|
--- |
| 6956 |
// If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is |
--- |
6956 |
// If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is |
--- |
| 6957 |
// actually legal and isn't going to get expanded, else this is a false |
--- |
6957 |
// actually legal and isn't going to get expanded, else this is a false |
--- |
| 6958 |
// optimisation. |
--- |
6958 |
// optimisation. |
--- |
| 6959 |
bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, |
0 |
6959 |
bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, |
0 |
| 6960 |
Load->getValueType(0), |
--- |
6960 |
Load->getValueType(0), |
--- |
| 6961 |
Load->getMemoryVT()); |
--- |
6961 |
Load->getMemoryVT()); |
--- |
| 6962 |
|
--- |
6962 |
|
--- |
| 6963 |
// Resize the constant to the same size as the original memory access before |
--- |
6963 |
// Resize the constant to the same size as the original memory access before |
--- |
| 6964 |
// extension. If it is still the AllOnesValue then this AND is completely |
--- |
6964 |
// extension. If it is still the AllOnesValue then this AND is completely |
--- |
| 6965 |
// unneeded. |
--- |
6965 |
// unneeded. |
--- |
| 6966 |
Constant = Constant.zextOrTrunc(Load->getMemoryVT().getScalarSizeInBits()); |
0 |
6966 |
Constant = Constant.zextOrTrunc(Load->getMemoryVT().getScalarSizeInBits()); |
0 |
| 6967 |
|
--- |
6967 |
|
--- |
| 6968 |
bool B; |
--- |
6968 |
bool B; |
--- |
| 6969 |
switch (Load->getExtensionType()) { |
0 |
6969 |
switch (Load->getExtensionType()) { |
0 |
| 6970 |
default: B = false; break; |
0 |
6970 |
default: B = false; break; |
0 |
| 6971 |
case ISD::EXTLOAD: B = CanZextLoadProfitably; break; |
0 |
6971 |
case ISD::EXTLOAD: B = CanZextLoadProfitably; break; |
0 |
| 6972 |
case ISD::ZEXTLOAD: |
0 |
6972 |
case ISD::ZEXTLOAD: |
0 |
| 6973 |
case ISD::NON_EXTLOAD: B = true; break; |
0 |
6973 |
case ISD::NON_EXTLOAD: B = true; break; |
0 |
| 6974 |
} |
--- |
6974 |
} |
--- |
| 6975 |
|
--- |
6975 |
|
--- |
| 6976 |
if (B && Constant.isAllOnes()) { |
0 |
6976 |
if (B && Constant.isAllOnes()) { |
0 |
| 6977 |
// If the load type was an EXTLOAD, convert to ZEXTLOAD in order to |
--- |
6977 |
// If the load type was an EXTLOAD, convert to ZEXTLOAD in order to |
--- |
| 6978 |
// preserve semantics once we get rid of the AND. |
--- |
6978 |
// preserve semantics once we get rid of the AND. |
--- |
| 6979 |
SDValue NewLoad(Load, 0); |
0 |
6979 |
SDValue NewLoad(Load, 0); |
0 |
| 6980 |
|
--- |
6980 |
|
--- |
| 6981 |
// Fold the AND away. NewLoad may get replaced immediately. |
--- |
6981 |
// Fold the AND away. NewLoad may get replaced immediately. |
--- |
| 6982 |
CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); |
0 |
6982 |
CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); |
0 |
| 6983 |
|
--- |
6983 |
|
--- |
| 6984 |
if (Load->getExtensionType() == ISD::EXTLOAD) { |
0 |
6984 |
if (Load->getExtensionType() == ISD::EXTLOAD) { |
0 |
| 6985 |
NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, |
0 |
6985 |
NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, |
0 |
| 6986 |
Load->getValueType(0), SDLoc(Load), |
0 |
6986 |
Load->getValueType(0), SDLoc(Load), |
0 |
| 6987 |
Load->getChain(), Load->getBasePtr(), |
0 |
6987 |
Load->getChain(), Load->getBasePtr(), |
0 |
| 6988 |
Load->getOffset(), Load->getMemoryVT(), |
0 |
6988 |
Load->getOffset(), Load->getMemoryVT(), |
0 |
| 6989 |
Load->getMemOperand()); |
--- |
6989 |
Load->getMemOperand()); |
--- |
| 6990 |
// Replace uses of the EXTLOAD with the new ZEXTLOAD. |
--- |
6990 |
// Replace uses of the EXTLOAD with the new ZEXTLOAD. |
--- |
| 6991 |
if (Load->getNumValues() == 3) { |
0 |
6991 |
if (Load->getNumValues() == 3) { |
0 |
| 6992 |
// PRE/POST_INC loads have 3 values. |
--- |
6992 |
// PRE/POST_INC loads have 3 values. |
--- |
| 6993 |
SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), |
0 |
6993 |
SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), |
0 |
| 6994 |
NewLoad.getValue(2) }; |
0 |
6994 |
NewLoad.getValue(2) }; |
0 |
| 6995 |
CombineTo(Load, To, 3, true); |
0 |
6995 |
CombineTo(Load, To, 3, true); |
0 |
| 6996 |
} else { |
--- |
6996 |
} else { |
--- |
| 6997 |
CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); |
0 |
6997 |
CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); |
0 |
| 6998 |
} |
--- |
6998 |
} |
--- |
| 6999 |
} |
--- |
6999 |
} |
--- |
| 7000 |
|
--- |
7000 |
|
--- |
| 7001 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
7001 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 7002 |
} |
--- |
7002 |
} |
--- |
| 7003 |
} |
0 |
7003 |
} |
0 |
| 7004 |
|
--- |
7004 |
|
--- |
| 7005 |
// Try to convert a constant mask AND into a shuffle clear mask. |
--- |
7005 |
// Try to convert a constant mask AND into a shuffle clear mask. |
--- |
| 7006 |
if (VT.isVector()) |
1 |
7006 |
if (VT.isVector()) |
1 |
| 7007 |
if (SDValue Shuffle = XformToShuffleWithZero(N)) |
0 |
7007 |
if (SDValue Shuffle = XformToShuffleWithZero(N)) |
0 |
| 7008 |
return Shuffle; |
0 |
7008 |
return Shuffle; |
0 |
| 7009 |
|
--- |
7009 |
|
--- |
| 7010 |
if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N)) |
1 |
7010 |
if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N)) |
1 |
| 7011 |
return Combined; |
0 |
7011 |
return Combined; |
0 |
| 7012 |
|
--- |
7012 |
|
--- |
| 7013 |
if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C && |
1 |
7013 |
if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C && |
1 |
| 7014 |
ISD::isExtOpcode(N0.getOperand(0).getOpcode())) { |
0 |
7014 |
ISD::isExtOpcode(N0.getOperand(0).getOpcode())) { |
0 |
| 7015 |
SDValue Ext = N0.getOperand(0); |
0 |
7015 |
SDValue Ext = N0.getOperand(0); |
0 |
| 7016 |
EVT ExtVT = Ext->getValueType(0); |
0 |
7016 |
EVT ExtVT = Ext->getValueType(0); |
0 |
| 7017 |
SDValue Extendee = Ext->getOperand(0); |
0 |
7017 |
SDValue Extendee = Ext->getOperand(0); |
0 |
| 7018 |
|
--- |
7018 |
|
--- |
| 7019 |
unsigned ScalarWidth = Extendee.getValueType().getScalarSizeInBits(); |
0 |
7019 |
unsigned ScalarWidth = Extendee.getValueType().getScalarSizeInBits(); |
0 |
| 7020 |
if (N1C->getAPIntValue().isMask(ScalarWidth) && |
0 |
7020 |
if (N1C->getAPIntValue().isMask(ScalarWidth) && |
0 |
| 7021 |
(!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, ExtVT))) { |
0 |
7021 |
(!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, ExtVT))) { |
0 |
| 7022 |
// (and (extract_subvector (zext|anyext|sext v) _) iN_mask) |
--- |
7022 |
// (and (extract_subvector (zext|anyext|sext v) _) iN_mask) |
--- |
| 7023 |
// => (extract_subvector (iN_zeroext v)) |
--- |
7023 |
// => (extract_subvector (iN_zeroext v)) |
--- |
| 7024 |
SDValue ZeroExtExtendee = |
--- |
7024 |
SDValue ZeroExtExtendee = |
--- |
| 7025 |
DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), ExtVT, Extendee); |
0 |
7025 |
DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), ExtVT, Extendee); |
0 |
| 7026 |
|
--- |
7026 |
|
--- |
| 7027 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), VT, ZeroExtExtendee, |
0 |
7027 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), VT, ZeroExtExtendee, |
0 |
| 7028 |
N0.getOperand(1)); |
0 |
7028 |
N0.getOperand(1)); |
0 |
| 7029 |
} |
--- |
7029 |
} |
--- |
| 7030 |
} |
--- |
7030 |
} |
--- |
| 7031 |
|
--- |
7031 |
|
--- |
| 7032 |
// fold (and (masked_gather x)) -> (zext_masked_gather x) |
--- |
7032 |
// fold (and (masked_gather x)) -> (zext_masked_gather x) |
--- |
| 7033 |
if (auto *GN0 = dyn_cast(N0)) { |
1 |
7033 |
if (auto *GN0 = dyn_cast(N0)) { |
1 |
| 7034 |
EVT MemVT = GN0->getMemoryVT(); |
0 |
7034 |
EVT MemVT = GN0->getMemoryVT(); |
0 |
| 7035 |
EVT ScalarVT = MemVT.getScalarType(); |
0 |
7035 |
EVT ScalarVT = MemVT.getScalarType(); |
0 |
| 7036 |
|
--- |
7036 |
|
--- |
| 7037 |
if (SDValue(GN0, 0).hasOneUse() && |
0 |
7037 |
if (SDValue(GN0, 0).hasOneUse() && |
0 |
| 7038 |
isConstantSplatVectorMaskForType(N1.getNode(), ScalarVT) && |
0 |
7038 |
isConstantSplatVectorMaskForType(N1.getNode(), ScalarVT) && |
0 |
| 7039 |
TLI.isVectorLoadExtDesirable(SDValue(SDValue(GN0, 0)))) { |
0 |
7039 |
TLI.isVectorLoadExtDesirable(SDValue(SDValue(GN0, 0)))) { |
0 |
| 7040 |
SDValue Ops[] = {GN0->getChain(), GN0->getPassThru(), GN0->getMask(), |
0 |
7040 |
SDValue Ops[] = {GN0->getChain(), GN0->getPassThru(), GN0->getMask(), |
0 |
| 7041 |
GN0->getBasePtr(), GN0->getIndex(), GN0->getScale()}; |
0 |
7041 |
GN0->getBasePtr(), GN0->getIndex(), GN0->getScale()}; |
0 |
| 7042 |
|
--- |
7042 |
|
--- |
| 7043 |
SDValue ZExtLoad = DAG.getMaskedGather( |
0 |
7043 |
SDValue ZExtLoad = DAG.getMaskedGather( |
0 |
| 7044 |
DAG.getVTList(VT, MVT::Other), MemVT, SDLoc(N), Ops, |
0 |
7044 |
DAG.getVTList(VT, MVT::Other), MemVT, SDLoc(N), Ops, |
0 |
| 7045 |
GN0->getMemOperand(), GN0->getIndexType(), ISD::ZEXTLOAD); |
--- |
7045 |
GN0->getMemOperand(), GN0->getIndexType(), ISD::ZEXTLOAD); |
--- |
| 7046 |
|
--- |
7046 |
|
--- |
| 7047 |
CombineTo(N, ZExtLoad); |
0 |
7047 |
CombineTo(N, ZExtLoad); |
0 |
| 7048 |
AddToWorklist(ZExtLoad.getNode()); |
0 |
7048 |
AddToWorklist(ZExtLoad.getNode()); |
0 |
| 7049 |
// Avoid recheck of N. |
--- |
7049 |
// Avoid recheck of N. |
--- |
| 7050 |
return SDValue(N, 0); |
0 |
7050 |
return SDValue(N, 0); |
0 |
| 7051 |
} |
--- |
7051 |
} |
--- |
| 7052 |
} |
--- |
7052 |
} |
--- |
| 7053 |
|
--- |
7053 |
|
--- |
| 7054 |
// fold (and (load x), 255) -> (zextload x, i8) |
--- |
7054 |
// fold (and (load x), 255) -> (zextload x, i8) |
--- |
| 7055 |
// fold (and (extload x, i16), 255) -> (zextload x, i8) |
--- |
7055 |
// fold (and (extload x, i16), 255) -> (zextload x, i8) |
--- |
| 7056 |
if (N1C && N0.getOpcode() == ISD::LOAD && !VT.isVector()) |
1 |
7056 |
if (N1C && N0.getOpcode() == ISD::LOAD && !VT.isVector()) |
1 |
| 7057 |
if (SDValue Res = reduceLoadWidth(N)) |
0 |
7057 |
if (SDValue Res = reduceLoadWidth(N)) |
0 |
| 7058 |
return Res; |
0 |
7058 |
return Res; |
0 |
| 7059 |
|
--- |
7059 |
|
--- |
| 7060 |
if (LegalTypes) { |
1 |
7060 |
if (LegalTypes) { |
1 |
| 7061 |
// Attempt to propagate the AND back up to the leaves which, if they're |
--- |
7061 |
// Attempt to propagate the AND back up to the leaves which, if they're |
--- |
| 7062 |
// loads, can be combined to narrow loads and the AND node can be removed. |
--- |
7062 |
// loads, can be combined to narrow loads and the AND node can be removed. |
--- |
| 7063 |
// Perform after legalization so that extend nodes will already be |
--- |
7063 |
// Perform after legalization so that extend nodes will already be |
--- |
| 7064 |
// combined into the loads. |
--- |
7064 |
// combined into the loads. |
--- |
| 7065 |
if (BackwardsPropagateMask(N)) |
1 |
7065 |
if (BackwardsPropagateMask(N)) |
1 |
| 7066 |
return SDValue(N, 0); |
0 |
7066 |
return SDValue(N, 0); |
0 |
| 7067 |
} |
--- |
7067 |
} |
--- |
| 7068 |
|
--- |
7068 |
|
--- |
| 7069 |
if (SDValue Combined = visitANDLike(N0, N1, N)) |
1 |
7069 |
if (SDValue Combined = visitANDLike(N0, N1, N)) |
1 |
| 7070 |
return Combined; |
0 |
7070 |
return Combined; |
0 |
| 7071 |
|
--- |
7071 |
|
--- |
| 7072 |
// Simplify: (and (op x...), (op y...)) -> (op (and x, y)) |
--- |
7072 |
// Simplify: (and (op x...), (op y...)) -> (op (and x, y)) |
--- |
| 7073 |
if (N0.getOpcode() == N1.getOpcode()) |
1 |
7073 |
if (N0.getOpcode() == N1.getOpcode()) |
1 |
| 7074 |
if (SDValue V = hoistLogicOpWithSameOpcodeHands(N)) |
0 |
7074 |
if (SDValue V = hoistLogicOpWithSameOpcodeHands(N)) |
0 |
| 7075 |
return V; |
0 |
7075 |
return V; |
0 |
| 7076 |
|
--- |
7076 |
|
--- |
| 7077 |
if (SDValue R = foldLogicOfShifts(N, N0, N1, DAG)) |
1 |
7077 |
if (SDValue R = foldLogicOfShifts(N, N0, N1, DAG)) |
1 |
| 7078 |
return R; |
0 |
7078 |
return R; |
0 |
| 7079 |
if (SDValue R = foldLogicOfShifts(N, N1, N0, DAG)) |
1 |
7079 |
if (SDValue R = foldLogicOfShifts(N, N1, N0, DAG)) |
1 |
| 7080 |
return R; |
0 |
7080 |
return R; |
0 |
| 7081 |
|
--- |
7081 |
|
--- |
| 7082 |
// Masking the negated extension of a boolean is just the zero-extended |
--- |
7082 |
// Masking the negated extension of a boolean is just the zero-extended |
--- |
| 7083 |
// boolean: |
--- |
7083 |
// boolean: |
--- |
| 7084 |
// and (sub 0, zext(bool X)), 1 --> zext(bool X) |
--- |
7084 |
// and (sub 0, zext(bool X)), 1 --> zext(bool X) |
--- |
| 7085 |
// and (sub 0, sext(bool X)), 1 --> zext(bool X) |
--- |
7085 |
// and (sub 0, sext(bool X)), 1 --> zext(bool X) |
--- |
| 7086 |
// |
--- |
7086 |
// |
--- |
| 7087 |
// Note: the SimplifyDemandedBits fold below can make an information-losing |
--- |
7087 |
// Note: the SimplifyDemandedBits fold below can make an information-losing |
--- |
| 7088 |
// transform, and then we have no way to find this better fold. |
--- |
7088 |
// transform, and then we have no way to find this better fold. |
--- |
| 7089 |
if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) { |
1 |
7089 |
if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) { |
1 |
| 7090 |
if (isNullOrNullSplat(N0.getOperand(0))) { |
0 |
7090 |
if (isNullOrNullSplat(N0.getOperand(0))) { |
0 |
| 7091 |
SDValue SubRHS = N0.getOperand(1); |
0 |
7091 |
SDValue SubRHS = N0.getOperand(1); |
0 |
| 7092 |
if (SubRHS.getOpcode() == ISD::ZERO_EXTEND && |
0 |
7092 |
if (SubRHS.getOpcode() == ISD::ZERO_EXTEND && |
0 |
| 7093 |
SubRHS.getOperand(0).getScalarValueSizeInBits() == 1) |
0 |
7093 |
SubRHS.getOperand(0).getScalarValueSizeInBits() == 1) |
0 |
| 7094 |
return SubRHS; |
0 |
7094 |
return SubRHS; |
0 |
| 7095 |
if (SubRHS.getOpcode() == ISD::SIGN_EXTEND && |
0 |
7095 |
if (SubRHS.getOpcode() == ISD::SIGN_EXTEND && |
0 |
| 7096 |
SubRHS.getOperand(0).getScalarValueSizeInBits() == 1) |
0 |
7096 |
SubRHS.getOperand(0).getScalarValueSizeInBits() == 1) |
0 |
| 7097 |
return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0)); |
0 |
7097 |
return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0)); |
0 |
| 7098 |
} |
--- |
7098 |
} |
--- |
| 7099 |
} |
--- |
7099 |
} |
--- |
| 7100 |
|
--- |
7100 |
|
--- |
| 7101 |
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) |
--- |
7101 |
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) |
--- |
| 7102 |
// fold (and (sra)) -> (and (srl)) when possible. |
--- |
7102 |
// fold (and (sra)) -> (and (srl)) when possible. |
--- |
| 7103 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
1 |
7103 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
1 |
| 7104 |
return SDValue(N, 0); |
1 |
7104 |
return SDValue(N, 0); |
1 |
| 7105 |
|
--- |
7105 |
|
--- |
| 7106 |
// fold (zext_inreg (extload x)) -> (zextload x) |
--- |
7106 |
// fold (zext_inreg (extload x)) -> (zextload x) |
--- |
| 7107 |
// fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use |
--- |
7107 |
// fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use |
--- |
| 7108 |
if (ISD::isUNINDEXEDLoad(N0.getNode()) && |
0 |
7108 |
if (ISD::isUNINDEXEDLoad(N0.getNode()) && |
0 |
| 7109 |
(ISD::isEXTLoad(N0.getNode()) || |
0 |
7109 |
(ISD::isEXTLoad(N0.getNode()) || |
0 |
| 7110 |
(ISD::isSEXTLoad(N0.getNode()) && N0.hasOneUse()))) { |
0 |
7110 |
(ISD::isSEXTLoad(N0.getNode()) && N0.hasOneUse()))) { |
0 |
| 7111 |
LoadSDNode *LN0 = cast(N0); |
0 |
7111 |
LoadSDNode *LN0 = cast(N0); |
0 |
| 7112 |
EVT MemVT = LN0->getMemoryVT(); |
0 |
7112 |
EVT MemVT = LN0->getMemoryVT(); |
0 |
| 7113 |
// If we zero all the possible extended bits, then we can turn this into |
--- |
7113 |
// If we zero all the possible extended bits, then we can turn this into |
--- |
| 7114 |
// a zextload if we are running before legalize or the operation is legal. |
--- |
7114 |
// a zextload if we are running before legalize or the operation is legal. |
--- |
| 7115 |
unsigned ExtBitSize = N1.getScalarValueSizeInBits(); |
0 |
7115 |
unsigned ExtBitSize = N1.getScalarValueSizeInBits(); |
0 |
| 7116 |
unsigned MemBitSize = MemVT.getScalarSizeInBits(); |
0 |
7116 |
unsigned MemBitSize = MemVT.getScalarSizeInBits(); |
0 |
| 7117 |
APInt ExtBits = APInt::getHighBitsSet(ExtBitSize, ExtBitSize - MemBitSize); |
0 |
7117 |
APInt ExtBits = APInt::getHighBitsSet(ExtBitSize, ExtBitSize - MemBitSize); |
0 |
| 7118 |
if (DAG.MaskedValueIsZero(N1, ExtBits) && |
0 |
7118 |
if (DAG.MaskedValueIsZero(N1, ExtBits) && |
0 |
| 7119 |
((!LegalOperations && LN0->isSimple()) || |
0 |
7119 |
((!LegalOperations && LN0->isSimple()) || |
0 |
| 7120 |
TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) { |
0 |
7120 |
TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) { |
0 |
| 7121 |
SDValue ExtLoad = |
--- |
7121 |
SDValue ExtLoad = |
--- |
| 7122 |
DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(), |
0 |
7122 |
DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(), |
0 |
| 7123 |
LN0->getBasePtr(), MemVT, LN0->getMemOperand()); |
0 |
7123 |
LN0->getBasePtr(), MemVT, LN0->getMemOperand()); |
0 |
| 7124 |
AddToWorklist(N); |
0 |
7124 |
AddToWorklist(N); |
0 |
| 7125 |
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); |
0 |
7125 |
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); |
0 |
| 7126 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
7126 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 7127 |
} |
--- |
7127 |
} |
--- |
| 7128 |
} |
0 |
7128 |
} |
0 |
| 7129 |
|
--- |
7129 |
|
--- |
| 7130 |
// fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const) |
--- |
7130 |
// fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const) |
--- |
| 7131 |
if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) { |
0 |
7131 |
if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) { |
0 |
| 7132 |
if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), |
0 |
7132 |
if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), |
0 |
| 7133 |
N0.getOperand(1), false)) |
0 |
7133 |
N0.getOperand(1), false)) |
0 |
| 7134 |
return BSwap; |
0 |
7134 |
return BSwap; |
0 |
| 7135 |
} |
--- |
7135 |
} |
--- |
| 7136 |
|
--- |
7136 |
|
--- |
| 7137 |
if (SDValue Shifts = unfoldExtremeBitClearingToShifts(N)) |
0 |
7137 |
if (SDValue Shifts = unfoldExtremeBitClearingToShifts(N)) |
0 |
| 7138 |
return Shifts; |
0 |
7138 |
return Shifts; |
0 |
| 7139 |
|
--- |
7139 |
|
--- |
| 7140 |
if (SDValue V = combineShiftAnd1ToBitTest(N, DAG)) |
0 |
7140 |
if (SDValue V = combineShiftAnd1ToBitTest(N, DAG)) |
0 |
| 7141 |
return V; |
0 |
7141 |
return V; |
0 |
| 7142 |
|
--- |
7142 |
|
--- |
| 7143 |
// Recognize the following pattern: |
--- |
7143 |
// Recognize the following pattern: |
--- |
| 7144 |
// |
--- |
7144 |
// |
--- |
| 7145 |
// AndVT = (and (sign_extend NarrowVT to AndVT) #bitmask) |
--- |
7145 |
// AndVT = (and (sign_extend NarrowVT to AndVT) #bitmask) |
--- |
| 7146 |
// |
--- |
7146 |
// |
--- |
| 7147 |
// where bitmask is a mask that clears the upper bits of AndVT. The |
--- |
7147 |
// where bitmask is a mask that clears the upper bits of AndVT. The |
--- |
| 7148 |
// number of bits in bitmask must be a power of two. |
--- |
7148 |
// number of bits in bitmask must be a power of two. |
--- |
| 7149 |
auto IsAndZeroExtMask = [](SDValue LHS, SDValue RHS) { |
0 |
7149 |
auto IsAndZeroExtMask = [](SDValue LHS, SDValue RHS) { |
0 |
| 7150 |
if (LHS->getOpcode() != ISD::SIGN_EXTEND) |
0 |
7150 |
if (LHS->getOpcode() != ISD::SIGN_EXTEND) |
0 |
| 7151 |
return false; |
0 |
7151 |
return false; |
0 |
| 7152 |
|
--- |
7152 |
|
--- |
| 7153 |
auto *C = dyn_cast(RHS); |
0 |
7153 |
auto *C = dyn_cast(RHS); |
0 |
| 7154 |
if (!C) |
0 |
7154 |
if (!C) |
0 |
| 7155 |
return false; |
0 |
7155 |
return false; |
0 |
| 7156 |
|
--- |
7156 |
|
--- |
| 7157 |
if (!C->getAPIntValue().isMask( |
0 |
7157 |
if (!C->getAPIntValue().isMask( |
0 |
| 7158 |
LHS.getOperand(0).getValueType().getFixedSizeInBits())) |
0 |
7158 |
LHS.getOperand(0).getValueType().getFixedSizeInBits())) |
0 |
| 7159 |
return false; |
0 |
7159 |
return false; |
0 |
| 7160 |
|
--- |
7160 |
|
--- |
| 7161 |
return true; |
0 |
7161 |
return true; |
0 |
| 7162 |
}; |
--- |
7162 |
}; |
--- |
| 7163 |
|
--- |
7163 |
|
--- |
| 7164 |
// Replace (and (sign_extend ...) #bitmask) with (zero_extend ...). |
--- |
7164 |
// Replace (and (sign_extend ...) #bitmask) with (zero_extend ...). |
--- |
| 7165 |
if (IsAndZeroExtMask(N0, N1)) |
0 |
7165 |
if (IsAndZeroExtMask(N0, N1)) |
0 |
| 7166 |
return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0.getOperand(0)); |
0 |
7166 |
return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0.getOperand(0)); |
0 |
| 7167 |
|
--- |
7167 |
|
--- |
| 7168 |
if (hasOperation(ISD::USUBSAT, VT)) |
0 |
7168 |
if (hasOperation(ISD::USUBSAT, VT)) |
0 |
| 7169 |
if (SDValue V = foldAndToUsubsat(N, DAG)) |
0 |
7169 |
if (SDValue V = foldAndToUsubsat(N, DAG)) |
0 |
| 7170 |
return V; |
0 |
7170 |
return V; |
0 |
| 7171 |
|
--- |
7171 |
|
--- |
| 7172 |
// Postpone until legalization completed to avoid interference with bswap |
--- |
7172 |
// Postpone until legalization completed to avoid interference with bswap |
--- |
| 7173 |
// folding |
--- |
7173 |
// folding |
--- |
| 7174 |
if (LegalOperations || VT.isVector()) |
0 |
7174 |
if (LegalOperations || VT.isVector()) |
0 |
| 7175 |
if (SDValue R = foldLogicTreeOfShifts(N, N0, N1, DAG)) |
0 |
7175 |
if (SDValue R = foldLogicTreeOfShifts(N, N0, N1, DAG)) |
0 |
| 7176 |
return R; |
0 |
7176 |
return R; |
0 |
| 7177 |
|
--- |
7177 |
|
--- |
| 7178 |
return SDValue(); |
0 |
7178 |
return SDValue(); |
0 |
| 7179 |
} |
--- |
7179 |
} |
--- |
| 7180 |
|
--- |
7180 |
|
--- |
| 7181 |
/// Match (a >> 8) | (a << 8) as (bswap a) >> 16. |
--- |
7181 |
/// Match (a >> 8) | (a << 8) as (bswap a) >> 16. |
--- |
| 7182 |
SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, |
0 |
7182 |
SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, |
0 |
| 7183 |
bool DemandHighBits) { |
--- |
7183 |
bool DemandHighBits) { |
--- |
| 7184 |
if (!LegalOperations) |
0 |
7184 |
if (!LegalOperations) |
0 |
| 7185 |
return SDValue(); |
0 |
7185 |
return SDValue(); |
0 |
| 7186 |
|
--- |
7186 |
|
--- |
| 7187 |
EVT VT = N->getValueType(0); |
0 |
7187 |
EVT VT = N->getValueType(0); |
0 |
| 7188 |
if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) |
0 |
7188 |
if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) |
0 |
| 7189 |
return SDValue(); |
0 |
7189 |
return SDValue(); |
0 |
| 7190 |
if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT)) |
0 |
7190 |
if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT)) |
0 |
| 7191 |
return SDValue(); |
0 |
7191 |
return SDValue(); |
0 |
| 7192 |
|
--- |
7192 |
|
--- |
| 7193 |
// Recognize (and (shl a, 8), 0xff00), (and (srl a, 8), 0xff) |
--- |
7193 |
// Recognize (and (shl a, 8), 0xff00), (and (srl a, 8), 0xff) |
--- |
| 7194 |
bool LookPassAnd0 = false; |
0 |
7194 |
bool LookPassAnd0 = false; |
0 |
| 7195 |
bool LookPassAnd1 = false; |
0 |
7195 |
bool LookPassAnd1 = false; |
0 |
| 7196 |
if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) |
0 |
7196 |
if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) |
0 |
| 7197 |
std::swap(N0, N1); |
0 |
7197 |
std::swap(N0, N1); |
0 |
| 7198 |
if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) |
0 |
7198 |
if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) |
0 |
| 7199 |
std::swap(N0, N1); |
0 |
7199 |
std::swap(N0, N1); |
0 |
| 7200 |
if (N0.getOpcode() == ISD::AND) { |
0 |
7200 |
if (N0.getOpcode() == ISD::AND) { |
0 |
| 7201 |
if (!N0->hasOneUse()) |
0 |
7201 |
if (!N0->hasOneUse()) |
0 |
| 7202 |
return SDValue(); |
0 |
7202 |
return SDValue(); |
0 |
| 7203 |
ConstantSDNode *N01C = dyn_cast(N0.getOperand(1)); |
0 |
7203 |
ConstantSDNode *N01C = dyn_cast(N0.getOperand(1)); |
0 |
| 7204 |
// Also handle 0xffff since the LHS is guaranteed to have zeros there. |
--- |
7204 |
// Also handle 0xffff since the LHS is guaranteed to have zeros there. |
--- |
| 7205 |
// This is needed for X86. |
--- |
7205 |
// This is needed for X86. |
--- |
| 7206 |
if (!N01C || (N01C->getZExtValue() != 0xFF00 && |
0 |
7206 |
if (!N01C || (N01C->getZExtValue() != 0xFF00 && |
0 |
| 7207 |
N01C->getZExtValue() != 0xFFFF)) |
0 |
7207 |
N01C->getZExtValue() != 0xFFFF)) |
0 |
| 7208 |
return SDValue(); |
0 |
7208 |
return SDValue(); |
0 |
| 7209 |
N0 = N0.getOperand(0); |
0 |
7209 |
N0 = N0.getOperand(0); |
0 |
| 7210 |
LookPassAnd0 = true; |
0 |
7210 |
LookPassAnd0 = true; |
0 |
| 7211 |
} |
--- |
7211 |
} |
--- |
| 7212 |
|
--- |
7212 |
|
--- |
| 7213 |
if (N1.getOpcode() == ISD::AND) { |
0 |
7213 |
if (N1.getOpcode() == ISD::AND) { |
0 |
| 7214 |
if (!N1->hasOneUse()) |
0 |
7214 |
if (!N1->hasOneUse()) |
0 |
| 7215 |
return SDValue(); |
0 |
7215 |
return SDValue(); |
0 |
| 7216 |
ConstantSDNode *N11C = dyn_cast(N1.getOperand(1)); |
0 |
7216 |
ConstantSDNode *N11C = dyn_cast(N1.getOperand(1)); |
0 |
| 7217 |
if (!N11C || N11C->getZExtValue() != 0xFF) |
0 |
7217 |
if (!N11C || N11C->getZExtValue() != 0xFF) |
0 |
| 7218 |
return SDValue(); |
0 |
7218 |
return SDValue(); |
0 |
| 7219 |
N1 = N1.getOperand(0); |
0 |
7219 |
N1 = N1.getOperand(0); |
0 |
| 7220 |
LookPassAnd1 = true; |
0 |
7220 |
LookPassAnd1 = true; |
0 |
| 7221 |
} |
--- |
7221 |
} |
--- |
| 7222 |
|
--- |
7222 |
|
--- |
| 7223 |
if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) |
0 |
7223 |
if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) |
0 |
| 7224 |
std::swap(N0, N1); |
0 |
7224 |
std::swap(N0, N1); |
0 |
| 7225 |
if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) |
0 |
7225 |
if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) |
0 |
| 7226 |
return SDValue(); |
0 |
7226 |
return SDValue(); |
0 |
| 7227 |
if (!N0->hasOneUse() || !N1->hasOneUse()) |
0 |
7227 |
if (!N0->hasOneUse() || !N1->hasOneUse()) |
0 |
| 7228 |
return SDValue(); |
0 |
7228 |
return SDValue(); |
0 |
| 7229 |
|
--- |
7229 |
|
--- |
| 7230 |
ConstantSDNode *N01C = dyn_cast(N0.getOperand(1)); |
0 |
7230 |
ConstantSDNode *N01C = dyn_cast(N0.getOperand(1)); |
0 |
| 7231 |
ConstantSDNode *N11C = dyn_cast(N1.getOperand(1)); |
0 |
7231 |
ConstantSDNode *N11C = dyn_cast(N1.getOperand(1)); |
0 |
| 7232 |
if (!N01C || !N11C) |
0 |
7232 |
if (!N01C || !N11C) |
0 |
| 7233 |
return SDValue(); |
0 |
7233 |
return SDValue(); |
0 |
| 7234 |
if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) |
0 |
7234 |
if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) |
0 |
| 7235 |
return SDValue(); |
0 |
7235 |
return SDValue(); |
0 |
| 7236 |
|
--- |
7236 |
|
--- |
| 7237 |
// Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) |
--- |
7237 |
// Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) |
--- |
| 7238 |
SDValue N00 = N0->getOperand(0); |
0 |
7238 |
SDValue N00 = N0->getOperand(0); |
0 |
| 7239 |
if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { |
0 |
7239 |
if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { |
0 |
| 7240 |
if (!N00->hasOneUse()) |
0 |
7240 |
if (!N00->hasOneUse()) |
0 |
| 7241 |
return SDValue(); |
0 |
7241 |
return SDValue(); |
0 |
| 7242 |
ConstantSDNode *N001C = dyn_cast(N00.getOperand(1)); |
0 |
7242 |
ConstantSDNode *N001C = dyn_cast(N00.getOperand(1)); |
0 |
| 7243 |
if (!N001C || N001C->getZExtValue() != 0xFF) |
0 |
7243 |
if (!N001C || N001C->getZExtValue() != 0xFF) |
0 |
| 7244 |
return SDValue(); |
0 |
7244 |
return SDValue(); |
0 |
| 7245 |
N00 = N00.getOperand(0); |
0 |
7245 |
N00 = N00.getOperand(0); |
0 |
| 7246 |
LookPassAnd0 = true; |
0 |
7246 |
LookPassAnd0 = true; |
0 |
| 7247 |
} |
--- |
7247 |
} |
--- |
| 7248 |
|
--- |
7248 |
|
--- |
| 7249 |
SDValue N10 = N1->getOperand(0); |
0 |
7249 |
SDValue N10 = N1->getOperand(0); |
0 |
| 7250 |
if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { |
0 |
7250 |
if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { |
0 |
| 7251 |
if (!N10->hasOneUse()) |
0 |
7251 |
if (!N10->hasOneUse()) |
0 |
| 7252 |
return SDValue(); |
0 |
7252 |
return SDValue(); |
0 |
| 7253 |
ConstantSDNode *N101C = dyn_cast(N10.getOperand(1)); |
0 |
7253 |
ConstantSDNode *N101C = dyn_cast(N10.getOperand(1)); |
0 |
| 7254 |
// Also allow 0xFFFF since the bits will be shifted out. This is needed |
--- |
7254 |
// Also allow 0xFFFF since the bits will be shifted out. This is needed |
--- |
| 7255 |
// for X86. |
--- |
7255 |
// for X86. |
--- |
| 7256 |
if (!N101C || (N101C->getZExtValue() != 0xFF00 && |
0 |
7256 |
if (!N101C || (N101C->getZExtValue() != 0xFF00 && |
0 |
| 7257 |
N101C->getZExtValue() != 0xFFFF)) |
0 |
7257 |
N101C->getZExtValue() != 0xFFFF)) |
0 |
| 7258 |
return SDValue(); |
0 |
7258 |
return SDValue(); |
0 |
| 7259 |
N10 = N10.getOperand(0); |
0 |
7259 |
N10 = N10.getOperand(0); |
0 |
| 7260 |
LookPassAnd1 = true; |
0 |
7260 |
LookPassAnd1 = true; |
0 |
| 7261 |
} |
--- |
7261 |
} |
--- |
| 7262 |
|
--- |
7262 |
|
--- |
| 7263 |
if (N00 != N10) |
0 |
7263 |
if (N00 != N10) |
0 |
| 7264 |
return SDValue(); |
0 |
7264 |
return SDValue(); |
0 |
| 7265 |
|
--- |
7265 |
|
--- |
| 7266 |
// Make sure everything beyond the low halfword gets set to zero since the SRL |
--- |
7266 |
// Make sure everything beyond the low halfword gets set to zero since the SRL |
--- |
| 7267 |
// 16 will clear the top bits. |
--- |
7267 |
// 16 will clear the top bits. |
--- |
| 7268 |
unsigned OpSizeInBits = VT.getSizeInBits(); |
0 |
7268 |
unsigned OpSizeInBits = VT.getSizeInBits(); |
0 |
| 7269 |
if (OpSizeInBits > 16) { |
0 |
7269 |
if (OpSizeInBits > 16) { |
0 |
| 7270 |
// If the left-shift isn't masked out then the only way this is a bswap is |
--- |
7270 |
// If the left-shift isn't masked out then the only way this is a bswap is |
--- |
| 7271 |
// if all bits beyond the low 8 are 0. In that case the entire pattern |
--- |
7271 |
// if all bits beyond the low 8 are 0. In that case the entire pattern |
--- |
| 7272 |
// reduces to a left shift anyway: leave it for other parts of the combiner. |
--- |
7272 |
// reduces to a left shift anyway: leave it for other parts of the combiner. |
--- |
| 7273 |
if (DemandHighBits && !LookPassAnd0) |
0 |
7273 |
if (DemandHighBits && !LookPassAnd0) |
0 |
| 7274 |
return SDValue(); |
0 |
7274 |
return SDValue(); |
0 |
| 7275 |
|
--- |
7275 |
|
--- |
| 7276 |
// However, if the right shift isn't masked out then it might be because |
--- |
7276 |
// However, if the right shift isn't masked out then it might be because |
--- |
| 7277 |
// it's not needed. See if we can spot that too. If the high bits aren't |
--- |
7277 |
// it's not needed. See if we can spot that too. If the high bits aren't |
--- |
| 7278 |
// demanded, we only need bits 23:16 to be zero. Otherwise, we need all |
--- |
7278 |
// demanded, we only need bits 23:16 to be zero. Otherwise, we need all |
--- |
| 7279 |
// upper bits to be zero. |
--- |
7279 |
// upper bits to be zero. |
--- |
| 7280 |
if (!LookPassAnd1) { |
0 |
7280 |
if (!LookPassAnd1) { |
0 |
| 7281 |
unsigned HighBit = DemandHighBits ? OpSizeInBits : 24; |
0 |
7281 |
unsigned HighBit = DemandHighBits ? OpSizeInBits : 24; |
0 |
| 7282 |
if (!DAG.MaskedValueIsZero(N10, |
0 |
7282 |
if (!DAG.MaskedValueIsZero(N10, |
0 |
| 7283 |
APInt::getBitsSet(OpSizeInBits, 16, HighBit))) |
0 |
7283 |
APInt::getBitsSet(OpSizeInBits, 16, HighBit))) |
0 |
| 7284 |
return SDValue(); |
0 |
7284 |
return SDValue(); |
0 |
| 7285 |
} |
--- |
7285 |
} |
--- |
| 7286 |
} |
--- |
7286 |
} |
--- |
| 7287 |
|
--- |
7287 |
|
--- |
| 7288 |
SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00); |
0 |
7288 |
SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00); |
0 |
| 7289 |
if (OpSizeInBits > 16) { |
0 |
7289 |
if (OpSizeInBits > 16) { |
0 |
| 7290 |
SDLoc DL(N); |
0 |
7290 |
SDLoc DL(N); |
0 |
| 7291 |
Res = DAG.getNode(ISD::SRL, DL, VT, Res, |
0 |
7291 |
Res = DAG.getNode(ISD::SRL, DL, VT, Res, |
0 |
| 7292 |
DAG.getConstant(OpSizeInBits - 16, DL, |
0 |
7292 |
DAG.getConstant(OpSizeInBits - 16, DL, |
0 |
| 7293 |
getShiftAmountTy(VT))); |
--- |
7293 |
getShiftAmountTy(VT))); |
--- |
| 7294 |
} |
0 |
7294 |
} |
0 |
| 7295 |
return Res; |
0 |
7295 |
return Res; |
0 |
| 7296 |
} |
--- |
7296 |
} |
--- |
| 7297 |
|
--- |
7297 |
|
--- |
| 7298 |
/// Return true if the specified node is an element that makes up a 32-bit |
--- |
7298 |
/// Return true if the specified node is an element that makes up a 32-bit |
--- |
| 7299 |
/// packed halfword byteswap. |
--- |
7299 |
/// packed halfword byteswap. |
--- |
| 7300 |
/// ((x & 0x000000ff) << 8) | |
--- |
7300 |
/// ((x & 0x000000ff) << 8) | |
--- |
| 7301 |
/// ((x & 0x0000ff00) >> 8) | |
--- |
7301 |
/// ((x & 0x0000ff00) >> 8) | |
--- |
| 7302 |
/// ((x & 0x00ff0000) << 8) | |
--- |
7302 |
/// ((x & 0x00ff0000) << 8) | |
--- |
| 7303 |
/// ((x & 0xff000000) >> 8) |
--- |
7303 |
/// ((x & 0xff000000) >> 8) |
--- |
| 7304 |
static bool isBSwapHWordElement(SDValue N, MutableArrayRef Parts) { |
0 |
7304 |
static bool isBSwapHWordElement(SDValue N, MutableArrayRef Parts) { |
0 |
| 7305 |
if (!N->hasOneUse()) |
0 |
7305 |
if (!N->hasOneUse()) |
0 |
| 7306 |
return false; |
0 |
7306 |
return false; |
0 |
| 7307 |
|
--- |
7307 |
|
--- |
| 7308 |
unsigned Opc = N.getOpcode(); |
0 |
7308 |
unsigned Opc = N.getOpcode(); |
0 |
| 7309 |
if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) |
0 |
7309 |
if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) |
0 |
| 7310 |
return false; |
0 |
7310 |
return false; |
0 |
| 7311 |
|
--- |
7311 |
|
--- |
| 7312 |
SDValue N0 = N.getOperand(0); |
0 |
7312 |
SDValue N0 = N.getOperand(0); |
0 |
| 7313 |
unsigned Opc0 = N0.getOpcode(); |
0 |
7313 |
unsigned Opc0 = N0.getOpcode(); |
0 |
| 7314 |
if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL) |
0 |
7314 |
if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL) |
0 |
| 7315 |
return false; |
0 |
7315 |
return false; |
0 |
| 7316 |
|
--- |
7316 |
|
--- |
| 7317 |
ConstantSDNode *N1C = nullptr; |
0 |
7317 |
ConstantSDNode *N1C = nullptr; |
0 |
| 7318 |
// SHL or SRL: look upstream for AND mask operand |
--- |
7318 |
// SHL or SRL: look upstream for AND mask operand |
--- |
| 7319 |
if (Opc == ISD::AND) |
0 |
7319 |
if (Opc == ISD::AND) |
0 |
| 7320 |
N1C = dyn_cast(N.getOperand(1)); |
0 |
7320 |
N1C = dyn_cast(N.getOperand(1)); |
0 |
| 7321 |
else if (Opc0 == ISD::AND) |
0 |
7321 |
else if (Opc0 == ISD::AND) |
0 |
| 7322 |
N1C = dyn_cast(N0.getOperand(1)); |
0 |
7322 |
N1C = dyn_cast(N0.getOperand(1)); |
0 |
| 7323 |
if (!N1C) |
0 |
7323 |
if (!N1C) |
0 |
| 7324 |
return false; |
0 |
7324 |
return false; |
0 |
| 7325 |
|
--- |
7325 |
|
--- |
| 7326 |
unsigned MaskByteOffset; |
--- |
7326 |
unsigned MaskByteOffset; |
--- |
| 7327 |
switch (N1C->getZExtValue()) { |
0 |
7327 |
switch (N1C->getZExtValue()) { |
0 |
| 7328 |
default: |
0 |
7328 |
default: |
0 |
| 7329 |
return false; |
0 |
7329 |
return false; |
0 |
| 7330 |
case 0xFF: MaskByteOffset = 0; break; |
0 |
7330 |
case 0xFF: MaskByteOffset = 0; break; |
0 |
| 7331 |
case 0xFF00: MaskByteOffset = 1; break; |
0 |
7331 |
case 0xFF00: MaskByteOffset = 1; break; |
0 |
| 7332 |
case 0xFFFF: |
0 |
7332 |
case 0xFFFF: |
0 |
| 7333 |
// In case demanded bits didn't clear the bits that will be shifted out. |
--- |
7333 |
// In case demanded bits didn't clear the bits that will be shifted out. |
--- |
| 7334 |
// This is needed for X86. |
--- |
7334 |
// This is needed for X86. |
--- |
| 7335 |
if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) { |
0 |
7335 |
if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) { |
0 |
| 7336 |
MaskByteOffset = 1; |
0 |
7336 |
MaskByteOffset = 1; |
0 |
| 7337 |
break; |
0 |
7337 |
break; |
0 |
| 7338 |
} |
--- |
7338 |
} |
--- |
| 7339 |
return false; |
0 |
7339 |
return false; |
0 |
| 7340 |
case 0xFF0000: MaskByteOffset = 2; break; |
0 |
7340 |
case 0xFF0000: MaskByteOffset = 2; break; |
0 |
| 7341 |
case 0xFF000000: MaskByteOffset = 3; break; |
0 |
7341 |
case 0xFF000000: MaskByteOffset = 3; break; |
0 |
| 7342 |
} |
--- |
7342 |
} |
--- |
| 7343 |
|
--- |
7343 |
|
--- |
| 7344 |
// Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). |
--- |
7344 |
// Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). |
--- |
| 7345 |
if (Opc == ISD::AND) { |
0 |
7345 |
if (Opc == ISD::AND) { |
0 |
| 7346 |
if (MaskByteOffset == 0 || MaskByteOffset == 2) { |
0 |
7346 |
if (MaskByteOffset == 0 || MaskByteOffset == 2) { |
0 |
| 7347 |
// (x >> 8) & 0xff |
--- |
7347 |
// (x >> 8) & 0xff |
--- |
| 7348 |
// (x >> 8) & 0xff0000 |
--- |
7348 |
// (x >> 8) & 0xff0000 |
--- |
| 7349 |
if (Opc0 != ISD::SRL) |
0 |
7349 |
if (Opc0 != ISD::SRL) |
0 |
| 7350 |
return false; |
0 |
7350 |
return false; |
0 |
| 7351 |
ConstantSDNode *C = dyn_cast(N0.getOperand(1)); |
0 |
7351 |
ConstantSDNode *C = dyn_cast(N0.getOperand(1)); |
0 |
| 7352 |
if (!C || C->getZExtValue() != 8) |
0 |
7352 |
if (!C || C->getZExtValue() != 8) |
0 |
| 7353 |
return false; |
0 |
7353 |
return false; |
0 |
| 7354 |
} else { |
0 |
7354 |
} else { |
0 |
| 7355 |
// (x << 8) & 0xff00 |
--- |
7355 |
// (x << 8) & 0xff00 |
--- |
| 7356 |
// (x << 8) & 0xff000000 |
--- |
7356 |
// (x << 8) & 0xff000000 |
--- |
| 7357 |
if (Opc0 != ISD::SHL) |
0 |
7357 |
if (Opc0 != ISD::SHL) |
0 |
| 7358 |
return false; |
0 |
7358 |
return false; |
0 |
| 7359 |
ConstantSDNode *C = dyn_cast(N0.getOperand(1)); |
0 |
7359 |
ConstantSDNode *C = dyn_cast(N0.getOperand(1)); |
0 |
| 7360 |
if (!C || C->getZExtValue() != 8) |
0 |
7360 |
if (!C || C->getZExtValue() != 8) |
0 |
| 7361 |
return false; |
0 |
7361 |
return false; |
0 |
| 7362 |
} |
--- |
7362 |
} |
--- |
| 7363 |
} else if (Opc == ISD::SHL) { |
0 |
7363 |
} else if (Opc == ISD::SHL) { |
0 |
| 7364 |
// (x & 0xff) << 8 |
--- |
7364 |
// (x & 0xff) << 8 |
--- |
| 7365 |
// (x & 0xff0000) << 8 |
--- |
7365 |
// (x & 0xff0000) << 8 |
--- |
| 7366 |
if (MaskByteOffset != 0 && MaskByteOffset != 2) |
0 |
7366 |
if (MaskByteOffset != 0 && MaskByteOffset != 2) |
0 |
| 7367 |
return false; |
0 |
7367 |
return false; |
0 |
| 7368 |
ConstantSDNode *C = dyn_cast(N.getOperand(1)); |
0 |
7368 |
ConstantSDNode *C = dyn_cast(N.getOperand(1)); |
0 |
| 7369 |
if (!C || C->getZExtValue() != 8) |
0 |
7369 |
if (!C || C->getZExtValue() != 8) |
0 |
| 7370 |
return false; |
0 |
7370 |
return false; |
0 |
| 7371 |
} else { // Opc == ISD::SRL |
--- |
7371 |
} else { // Opc == ISD::SRL |
--- |
| 7372 |
// (x & 0xff00) >> 8 |
--- |
7372 |
// (x & 0xff00) >> 8 |
--- |
| 7373 |
// (x & 0xff000000) >> 8 |
--- |
7373 |
// (x & 0xff000000) >> 8 |
--- |
| 7374 |
if (MaskByteOffset != 1 && MaskByteOffset != 3) |
0 |
7374 |
if (MaskByteOffset != 1 && MaskByteOffset != 3) |
0 |
| 7375 |
return false; |
0 |
7375 |
return false; |
0 |
| 7376 |
ConstantSDNode *C = dyn_cast(N.getOperand(1)); |
0 |
7376 |
ConstantSDNode *C = dyn_cast(N.getOperand(1)); |
0 |
| 7377 |
if (!C || C->getZExtValue() != 8) |
0 |
7377 |
if (!C || C->getZExtValue() != 8) |
0 |
| 7378 |
return false; |
0 |
7378 |
return false; |
0 |
| 7379 |
} |
--- |
7379 |
} |
--- |
| 7380 |
|
--- |
7380 |
|
--- |
| 7381 |
if (Parts[MaskByteOffset]) |
0 |
7381 |
if (Parts[MaskByteOffset]) |
0 |
| 7382 |
return false; |
0 |
7382 |
return false; |
0 |
| 7383 |
|
--- |
7383 |
|
--- |
| 7384 |
Parts[MaskByteOffset] = N0.getOperand(0).getNode(); |
0 |
7384 |
Parts[MaskByteOffset] = N0.getOperand(0).getNode(); |
0 |
| 7385 |
return true; |
0 |
7385 |
return true; |
0 |
| 7386 |
} |
--- |
7386 |
} |
--- |
| 7387 |
|
--- |
7387 |
|
--- |
| 7388 |
// Match 2 elements of a packed halfword bswap. |
--- |
7388 |
// Match 2 elements of a packed halfword bswap. |
--- |
| 7389 |
static bool isBSwapHWordPair(SDValue N, MutableArrayRef Parts) { |
0 |
7389 |
static bool isBSwapHWordPair(SDValue N, MutableArrayRef Parts) { |
0 |
| 7390 |
if (N.getOpcode() == ISD::OR) |
0 |
7390 |
if (N.getOpcode() == ISD::OR) |
0 |
| 7391 |
return isBSwapHWordElement(N.getOperand(0), Parts) && |
0 |
7391 |
return isBSwapHWordElement(N.getOperand(0), Parts) && |
0 |
| 7392 |
isBSwapHWordElement(N.getOperand(1), Parts); |
0 |
7392 |
isBSwapHWordElement(N.getOperand(1), Parts); |
0 |
| 7393 |
|
--- |
7393 |
|
--- |
| 7394 |
if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) { |
0 |
7394 |
if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) { |
0 |
| 7395 |
ConstantSDNode *C = isConstOrConstSplat(N.getOperand(1)); |
0 |
7395 |
ConstantSDNode *C = isConstOrConstSplat(N.getOperand(1)); |
0 |
| 7396 |
if (!C || C->getAPIntValue() != 16) |
0 |
7396 |
if (!C || C->getAPIntValue() != 16) |
0 |
| 7397 |
return false; |
0 |
7397 |
return false; |
0 |
| 7398 |
Parts[0] = Parts[1] = N.getOperand(0).getOperand(0).getNode(); |
0 |
7398 |
Parts[0] = Parts[1] = N.getOperand(0).getOperand(0).getNode(); |
0 |
| 7399 |
return true; |
0 |
7399 |
return true; |
0 |
| 7400 |
} |
--- |
7400 |
} |
--- |
| 7401 |
|
--- |
7401 |
|
--- |
| 7402 |
return false; |
0 |
7402 |
return false; |
0 |
| 7403 |
} |
--- |
7403 |
} |
--- |
| 7404 |
|
--- |
7404 |
|
--- |
| 7405 |
// Match this pattern: |
--- |
7405 |
// Match this pattern: |
--- |
| 7406 |
// (or (and (shl (A, 8)), 0xff00ff00), (and (srl (A, 8)), 0x00ff00ff)) |
--- |
7406 |
// (or (and (shl (A, 8)), 0xff00ff00), (and (srl (A, 8)), 0x00ff00ff)) |
--- |
| 7407 |
// And rewrite this to: |
--- |
7407 |
// And rewrite this to: |
--- |
| 7408 |
// (rotr (bswap A), 16) |
--- |
7408 |
// (rotr (bswap A), 16) |
--- |
| 7409 |
static SDValue matchBSwapHWordOrAndAnd(const TargetLowering &TLI, |
0 |
7409 |
static SDValue matchBSwapHWordOrAndAnd(const TargetLowering &TLI, |
0 |
| 7410 |
SelectionDAG &DAG, SDNode *N, SDValue N0, |
--- |
7410 |
SelectionDAG &DAG, SDNode *N, SDValue N0, |
--- |
| 7411 |
SDValue N1, EVT VT, EVT ShiftAmountTy) { |
--- |
7411 |
SDValue N1, EVT VT, EVT ShiftAmountTy) { |
--- |
| 7412 |
assert(N->getOpcode() == ISD::OR && VT == MVT::i32 && |
0 |
7412 |
assert(N->getOpcode() == ISD::OR && VT == MVT::i32 && |
0 |
| 7413 |
"MatchBSwapHWordOrAndAnd: expecting i32"); |
--- |
7413 |
"MatchBSwapHWordOrAndAnd: expecting i32"); |
--- |
| 7414 |
if (!TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) |
0 |
7414 |
if (!TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) |
0 |
| 7415 |
return SDValue(); |
0 |
7415 |
return SDValue(); |
0 |
| 7416 |
if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND) |
0 |
7416 |
if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND) |
0 |
| 7417 |
return SDValue(); |
0 |
7417 |
return SDValue(); |
0 |
| 7418 |
// TODO: this is too restrictive; lifting this restriction requires more tests |
--- |
7418 |
// TODO: this is too restrictive; lifting this restriction requires more tests |
--- |
| 7419 |
if (!N0->hasOneUse() || !N1->hasOneUse()) |
0 |
7419 |
if (!N0->hasOneUse() || !N1->hasOneUse()) |
0 |
| 7420 |
return SDValue(); |
0 |
7420 |
return SDValue(); |
0 |
| 7421 |
ConstantSDNode *Mask0 = isConstOrConstSplat(N0.getOperand(1)); |
0 |
7421 |
ConstantSDNode *Mask0 = isConstOrConstSplat(N0.getOperand(1)); |
0 |
| 7422 |
ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1)); |
0 |
7422 |
ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1)); |
0 |
| 7423 |
if (!Mask0 || !Mask1) |
0 |
7423 |
if (!Mask0 || !Mask1) |
0 |
| 7424 |
return SDValue(); |
0 |
7424 |
return SDValue(); |
0 |
| 7425 |
if (Mask0->getAPIntValue() != 0xff00ff00 || |
0 |
7425 |
if (Mask0->getAPIntValue() != 0xff00ff00 || |
0 |
| 7426 |
Mask1->getAPIntValue() != 0x00ff00ff) |
0 |
7426 |
Mask1->getAPIntValue() != 0x00ff00ff) |
0 |
| 7427 |
return SDValue(); |
0 |
7427 |
return SDValue(); |
0 |
| 7428 |
SDValue Shift0 = N0.getOperand(0); |
0 |
7428 |
SDValue Shift0 = N0.getOperand(0); |
0 |
| 7429 |
SDValue Shift1 = N1.getOperand(0); |
0 |
7429 |
SDValue Shift1 = N1.getOperand(0); |
0 |
| 7430 |
if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) |
0 |
7430 |
if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) |
0 |
| 7431 |
return SDValue(); |
0 |
7431 |
return SDValue(); |
0 |
| 7432 |
ConstantSDNode *ShiftAmt0 = isConstOrConstSplat(Shift0.getOperand(1)); |
0 |
7432 |
ConstantSDNode *ShiftAmt0 = isConstOrConstSplat(Shift0.getOperand(1)); |
0 |
| 7433 |
ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1)); |
0 |
7433 |
ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1)); |
0 |
| 7434 |
if (!ShiftAmt0 || !ShiftAmt1) |
0 |
7434 |
if (!ShiftAmt0 || !ShiftAmt1) |
0 |
| 7435 |
return SDValue(); |
0 |
7435 |
return SDValue(); |
0 |
| 7436 |
if (ShiftAmt0->getAPIntValue() != 8 || ShiftAmt1->getAPIntValue() != 8) |
0 |
7436 |
if (ShiftAmt0->getAPIntValue() != 8 || ShiftAmt1->getAPIntValue() != 8) |
0 |
| 7437 |
return SDValue(); |
0 |
7437 |
return SDValue(); |
0 |
| 7438 |
if (Shift0.getOperand(0) != Shift1.getOperand(0)) |
0 |
7438 |
if (Shift0.getOperand(0) != Shift1.getOperand(0)) |
0 |
| 7439 |
return SDValue(); |
0 |
7439 |
return SDValue(); |
0 |
| 7440 |
|
--- |
7440 |
|
--- |
| 7441 |
SDLoc DL(N); |
0 |
7441 |
SDLoc DL(N); |
0 |
| 7442 |
SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, Shift0.getOperand(0)); |
0 |
7442 |
SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, Shift0.getOperand(0)); |
0 |
| 7443 |
SDValue ShAmt = DAG.getConstant(16, DL, ShiftAmountTy); |
0 |
7443 |
SDValue ShAmt = DAG.getConstant(16, DL, ShiftAmountTy); |
0 |
| 7444 |
return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt); |
0 |
7444 |
return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt); |
0 |
| 7445 |
} |
0 |
7445 |
} |
0 |
| 7446 |
|
--- |
7446 |
|
--- |
| 7447 |
/// Match a 32-bit packed halfword bswap. That is |
--- |
7447 |
/// Match a 32-bit packed halfword bswap. That is |
--- |
| 7448 |
/// ((x & 0x000000ff) << 8) | |
--- |
7448 |
/// ((x & 0x000000ff) << 8) | |
--- |
| 7449 |
/// ((x & 0x0000ff00) >> 8) | |
--- |
7449 |
/// ((x & 0x0000ff00) >> 8) | |
--- |
| 7450 |
/// ((x & 0x00ff0000) << 8) | |
--- |
7450 |
/// ((x & 0x00ff0000) << 8) | |
--- |
| 7451 |
/// ((x & 0xff000000) >> 8) |
--- |
7451 |
/// ((x & 0xff000000) >> 8) |
--- |
| 7452 |
/// => (rotl (bswap x), 16) |
--- |
7452 |
/// => (rotl (bswap x), 16) |
--- |
| 7453 |
SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { |
0 |
7453 |
SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { |
0 |
| 7454 |
if (!LegalOperations) |
0 |
7454 |
if (!LegalOperations) |
0 |
| 7455 |
return SDValue(); |
0 |
7455 |
return SDValue(); |
0 |
| 7456 |
|
--- |
7456 |
|
--- |
| 7457 |
EVT VT = N->getValueType(0); |
0 |
7457 |
EVT VT = N->getValueType(0); |
0 |
| 7458 |
if (VT != MVT::i32) |
0 |
7458 |
if (VT != MVT::i32) |
0 |
| 7459 |
return SDValue(); |
0 |
7459 |
return SDValue(); |
0 |
| 7460 |
if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT)) |
0 |
7460 |
if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT)) |
0 |
| 7461 |
return SDValue(); |
0 |
7461 |
return SDValue(); |
0 |
| 7462 |
|
--- |
7462 |
|
--- |
| 7463 |
if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N0, N1, VT, |
0 |
7463 |
if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N0, N1, VT, |
0 |
| 7464 |
getShiftAmountTy(VT))) |
0 |
7464 |
getShiftAmountTy(VT))) |
0 |
| 7465 |
return BSwap; |
0 |
7465 |
return BSwap; |
0 |
| 7466 |
|
--- |
7466 |
|
--- |
| 7467 |
// Try again with commuted operands. |
--- |
7467 |
// Try again with commuted operands. |
--- |
| 7468 |
if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N1, N0, VT, |
0 |
7468 |
if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N1, N0, VT, |
0 |
| 7469 |
getShiftAmountTy(VT))) |
0 |
7469 |
getShiftAmountTy(VT))) |
0 |
| 7470 |
return BSwap; |
0 |
7470 |
return BSwap; |
0 |
| 7471 |
|
--- |
7471 |
|
--- |
| 7472 |
|
--- |
7472 |
|
--- |
| 7473 |
// Look for either |
--- |
7473 |
// Look for either |
--- |
| 7474 |
// (or (bswaphpair), (bswaphpair)) |
--- |
7474 |
// (or (bswaphpair), (bswaphpair)) |
--- |
| 7475 |
// (or (or (bswaphpair), (and)), (and)) |
--- |
7475 |
// (or (or (bswaphpair), (and)), (and)) |
--- |
| 7476 |
// (or (or (and), (bswaphpair)), (and)) |
--- |
7476 |
// (or (or (and), (bswaphpair)), (and)) |
--- |
| 7477 |
SDNode *Parts[4] = {}; |
0 |
7477 |
SDNode *Parts[4] = {}; |
0 |
| 7478 |
|
--- |
7478 |
|
--- |
| 7479 |
if (isBSwapHWordPair(N0, Parts)) { |
0 |
7479 |
if (isBSwapHWordPair(N0, Parts)) { |
0 |
| 7480 |
// (or (or (and), (and)), (or (and), (and))) |
--- |
7480 |
// (or (or (and), (and)), (or (and), (and))) |
--- |
| 7481 |
if (!isBSwapHWordPair(N1, Parts)) |
0 |
7481 |
if (!isBSwapHWordPair(N1, Parts)) |
0 |
| 7482 |
return SDValue(); |
0 |
7482 |
return SDValue(); |
0 |
| 7483 |
} else if (N0.getOpcode() == ISD::OR) { |
0 |
7483 |
} else if (N0.getOpcode() == ISD::OR) { |
0 |
| 7484 |
// (or (or (or (and), (and)), (and)), (and)) |
--- |
7484 |
// (or (or (or (and), (and)), (and)), (and)) |
--- |
| 7485 |
if (!isBSwapHWordElement(N1, Parts)) |
0 |
7485 |
if (!isBSwapHWordElement(N1, Parts)) |
0 |
| 7486 |
return SDValue(); |
0 |
7486 |
return SDValue(); |
0 |
| 7487 |
SDValue N00 = N0.getOperand(0); |
0 |
7487 |
SDValue N00 = N0.getOperand(0); |
0 |
| 7488 |
SDValue N01 = N0.getOperand(1); |
0 |
7488 |
SDValue N01 = N0.getOperand(1); |
0 |
| 7489 |
if (!(isBSwapHWordElement(N01, Parts) && isBSwapHWordPair(N00, Parts)) && |
0 |
7489 |
if (!(isBSwapHWordElement(N01, Parts) && isBSwapHWordPair(N00, Parts)) && |
0 |
| 7490 |
!(isBSwapHWordElement(N00, Parts) && isBSwapHWordPair(N01, Parts))) |
0 |
7490 |
!(isBSwapHWordElement(N00, Parts) && isBSwapHWordPair(N01, Parts))) |
0 |
| 7491 |
return SDValue(); |
0 |
7491 |
return SDValue(); |
0 |
| 7492 |
} else { |
--- |
7492 |
} else { |
--- |
| 7493 |
return SDValue(); |
0 |
7493 |
return SDValue(); |
0 |
| 7494 |
} |
--- |
7494 |
} |
--- |
| 7495 |
|
--- |
7495 |
|
--- |
| 7496 |
// Make sure the parts are all coming from the same node. |
--- |
7496 |
// Make sure the parts are all coming from the same node. |
--- |
| 7497 |
if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) |
0 |
7497 |
if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) |
0 |
| 7498 |
return SDValue(); |
0 |
7498 |
return SDValue(); |
0 |
| 7499 |
|
--- |
7499 |
|
--- |
| 7500 |
SDLoc DL(N); |
0 |
7500 |
SDLoc DL(N); |
0 |
| 7501 |
SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, |
0 |
7501 |
SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, |
0 |
| 7502 |
SDValue(Parts[0], 0)); |
--- |
7502 |
SDValue(Parts[0], 0)); |
--- |
| 7503 |
|
--- |
7503 |
|
--- |
| 7504 |
// Result of the bswap should be rotated by 16. If it's not legal, then |
--- |
7504 |
// Result of the bswap should be rotated by 16. If it's not legal, then |
--- |
| 7505 |
// do (x << 16) | (x >> 16). |
--- |
7505 |
// do (x << 16) | (x >> 16). |
--- |
| 7506 |
SDValue ShAmt = DAG.getConstant(16, DL, getShiftAmountTy(VT)); |
0 |
7506 |
SDValue ShAmt = DAG.getConstant(16, DL, getShiftAmountTy(VT)); |
0 |
| 7507 |
if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) |
0 |
7507 |
if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) |
0 |
| 7508 |
return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt); |
0 |
7508 |
return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt); |
0 |
| 7509 |
if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) |
0 |
7509 |
if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) |
0 |
| 7510 |
return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt); |
0 |
7510 |
return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt); |
0 |
| 7511 |
return DAG.getNode(ISD::OR, DL, VT, |
0 |
7511 |
return DAG.getNode(ISD::OR, DL, VT, |
0 |
| 7512 |
DAG.getNode(ISD::SHL, DL, VT, BSwap, ShAmt), |
0 |
7512 |
DAG.getNode(ISD::SHL, DL, VT, BSwap, ShAmt), |
0 |
| 7513 |
DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt)); |
0 |
7513 |
DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt)); |
0 |
| 7514 |
} |
0 |
7514 |
} |
0 |
| 7515 |
|
--- |
7515 |
|
--- |
| 7516 |
/// This contains all DAGCombine rules which reduce two values combined by |
--- |
7516 |
/// This contains all DAGCombine rules which reduce two values combined by |
--- |
| 7517 |
/// an Or operation to a single value \see visitANDLike(). |
--- |
7517 |
/// an Or operation to a single value \see visitANDLike(). |
--- |
| 7518 |
SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *N) { |
0 |
7518 |
SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *N) { |
0 |
| 7519 |
EVT VT = N1.getValueType(); |
0 |
7519 |
EVT VT = N1.getValueType(); |
0 |
| 7520 |
SDLoc DL(N); |
0 |
7520 |
SDLoc DL(N); |
0 |
| 7521 |
|
--- |
7521 |
|
--- |
| 7522 |
// fold (or x, undef) -> -1 |
--- |
7522 |
// fold (or x, undef) -> -1 |
--- |
| 7523 |
if (!LegalOperations && (N0.isUndef() || N1.isUndef())) |
0 |
7523 |
if (!LegalOperations && (N0.isUndef() || N1.isUndef())) |
0 |
| 7524 |
return DAG.getAllOnesConstant(DL, VT); |
0 |
7524 |
return DAG.getAllOnesConstant(DL, VT); |
0 |
| 7525 |
|
--- |
7525 |
|
--- |
| 7526 |
if (SDValue V = foldLogicOfSetCCs(false, N0, N1, DL)) |
0 |
7526 |
if (SDValue V = foldLogicOfSetCCs(false, N0, N1, DL)) |
0 |
| 7527 |
return V; |
0 |
7527 |
return V; |
0 |
| 7528 |
|
--- |
7528 |
|
--- |
| 7529 |
// (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. |
--- |
7529 |
// (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. |
--- |
| 7530 |
if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND && |
0 |
7530 |
if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND && |
0 |
| 7531 |
// Don't increase # computations. |
--- |
7531 |
// Don't increase # computations. |
--- |
| 7532 |
(N0->hasOneUse() || N1->hasOneUse())) { |
0 |
7532 |
(N0->hasOneUse() || N1->hasOneUse())) { |
0 |
| 7533 |
// We can only do this xform if we know that bits from X that are set in C2 |
--- |
7533 |
// We can only do this xform if we know that bits from X that are set in C2 |
--- |
| 7534 |
// but not in C1 are already zero. Likewise for Y. |
--- |
7534 |
// but not in C1 are already zero. Likewise for Y. |
--- |
| 7535 |
if (const ConstantSDNode *N0O1C = |
0 |
7535 |
if (const ConstantSDNode *N0O1C = |
0 |
| 7536 |
getAsNonOpaqueConstant(N0.getOperand(1))) { |
0 |
7536 |
getAsNonOpaqueConstant(N0.getOperand(1))) { |
0 |
| 7537 |
if (const ConstantSDNode *N1O1C = |
0 |
7537 |
if (const ConstantSDNode *N1O1C = |
0 |
| 7538 |
getAsNonOpaqueConstant(N1.getOperand(1))) { |
0 |
7538 |
getAsNonOpaqueConstant(N1.getOperand(1))) { |
0 |
| 7539 |
// We can only do this xform if we know that bits from X that are set in |
--- |
7539 |
// We can only do this xform if we know that bits from X that are set in |
--- |
| 7540 |
// C2 but not in C1 are already zero. Likewise for Y. |
--- |
7540 |
// C2 but not in C1 are already zero. Likewise for Y. |
--- |
| 7541 |
const APInt &LHSMask = N0O1C->getAPIntValue(); |
0 |
7541 |
const APInt &LHSMask = N0O1C->getAPIntValue(); |
0 |
| 7542 |
const APInt &RHSMask = N1O1C->getAPIntValue(); |
0 |
7542 |
const APInt &RHSMask = N1O1C->getAPIntValue(); |
0 |
| 7543 |
|
--- |
7543 |
|
--- |
| 7544 |
if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && |
0 |
7544 |
if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && |
0 |
| 7545 |
DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { |
0 |
7545 |
DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { |
0 |
| 7546 |
SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT, |
0 |
7546 |
SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT, |
0 |
| 7547 |
N0.getOperand(0), N1.getOperand(0)); |
0 |
7547 |
N0.getOperand(0), N1.getOperand(0)); |
0 |
| 7548 |
return DAG.getNode(ISD::AND, DL, VT, X, |
0 |
7548 |
return DAG.getNode(ISD::AND, DL, VT, X, |
0 |
| 7549 |
DAG.getConstant(LHSMask | RHSMask, DL, VT)); |
0 |
7549 |
DAG.getConstant(LHSMask | RHSMask, DL, VT)); |
0 |
| 7550 |
} |
--- |
7550 |
} |
--- |
| 7551 |
} |
--- |
7551 |
} |
--- |
| 7552 |
} |
--- |
7552 |
} |
--- |
| 7553 |
} |
--- |
7553 |
} |
--- |
| 7554 |
|
--- |
7554 |
|
--- |
| 7555 |
// (or (and X, M), (and X, N)) -> (and X, (or M, N)) |
--- |
7555 |
// (or (and X, M), (and X, N)) -> (and X, (or M, N)) |
--- |
| 7556 |
if (N0.getOpcode() == ISD::AND && |
0 |
7556 |
if (N0.getOpcode() == ISD::AND && |
0 |
| 7557 |
N1.getOpcode() == ISD::AND && |
0 |
7557 |
N1.getOpcode() == ISD::AND && |
0 |
| 7558 |
N0.getOperand(0) == N1.getOperand(0) && |
0 |
7558 |
N0.getOperand(0) == N1.getOperand(0) && |
0 |
| 7559 |
// Don't increase # computations. |
--- |
7559 |
// Don't increase # computations. |
--- |
| 7560 |
(N0->hasOneUse() || N1->hasOneUse())) { |
0 |
7560 |
(N0->hasOneUse() || N1->hasOneUse())) { |
0 |
| 7561 |
SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT, |
0 |
7561 |
SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT, |
0 |
| 7562 |
N0.getOperand(1), N1.getOperand(1)); |
0 |
7562 |
N0.getOperand(1), N1.getOperand(1)); |
0 |
| 7563 |
return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), X); |
0 |
7563 |
return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), X); |
0 |
| 7564 |
} |
--- |
7564 |
} |
--- |
| 7565 |
|
--- |
7565 |
|
--- |
| 7566 |
return SDValue(); |
0 |
7566 |
return SDValue(); |
0 |
| 7567 |
} |
0 |
7567 |
} |
0 |
| 7568 |
|
--- |
7568 |
|
--- |
| 7569 |
/// OR combines for which the commuted variant will be tried as well. |
--- |
7569 |
/// OR combines for which the commuted variant will be tried as well. |
--- |
| 7570 |
static SDValue visitORCommutative(SelectionDAG &DAG, SDValue N0, SDValue N1, |
0 |
7570 |
static SDValue visitORCommutative(SelectionDAG &DAG, SDValue N0, SDValue N1, |
0 |
| 7571 |
SDNode *N) { |
--- |
7571 |
SDNode *N) { |
--- |
| 7572 |
EVT VT = N0.getValueType(); |
0 |
7572 |
EVT VT = N0.getValueType(); |
0 |
| 7573 |
|
--- |
7573 |
|
--- |
| 7574 |
auto peekThroughResize = [](SDValue V) { |
0 |
7574 |
auto peekThroughResize = [](SDValue V) { |
0 |
| 7575 |
if (V->getOpcode() == ISD::ZERO_EXTEND || V->getOpcode() == ISD::TRUNCATE) |
0 |
7575 |
if (V->getOpcode() == ISD::ZERO_EXTEND || V->getOpcode() == ISD::TRUNCATE) |
0 |
| 7576 |
return V->getOperand(0); |
0 |
7576 |
return V->getOperand(0); |
0 |
| 7577 |
return V; |
0 |
7577 |
return V; |
0 |
| 7578 |
}; |
--- |
7578 |
}; |
--- |
| 7579 |
|
--- |
7579 |
|
--- |
| 7580 |
SDValue N0Resized = peekThroughResize(N0); |
0 |
7580 |
SDValue N0Resized = peekThroughResize(N0); |
0 |
| 7581 |
if (N0Resized.getOpcode() == ISD::AND) { |
0 |
7581 |
if (N0Resized.getOpcode() == ISD::AND) { |
0 |
| 7582 |
SDValue N1Resized = peekThroughResize(N1); |
0 |
7582 |
SDValue N1Resized = peekThroughResize(N1); |
0 |
| 7583 |
SDValue N00 = N0Resized.getOperand(0); |
0 |
7583 |
SDValue N00 = N0Resized.getOperand(0); |
0 |
| 7584 |
SDValue N01 = N0Resized.getOperand(1); |
0 |
7584 |
SDValue N01 = N0Resized.getOperand(1); |
0 |
| 7585 |
|
--- |
7585 |
|
--- |
| 7586 |
// fold or (and x, y), x --> x |
--- |
7586 |
// fold or (and x, y), x --> x |
--- |
| 7587 |
if (N00 == N1Resized || N01 == N1Resized) |
0 |
7587 |
if (N00 == N1Resized || N01 == N1Resized) |
0 |
| 7588 |
return N1; |
0 |
7588 |
return N1; |
0 |
| 7589 |
|
--- |
7589 |
|
--- |
| 7590 |
// fold (or (and X, (xor Y, -1)), Y) -> (or X, Y) |
--- |
7590 |
// fold (or (and X, (xor Y, -1)), Y) -> (or X, Y) |
--- |
| 7591 |
// TODO: Set AllowUndefs = true. |
--- |
7591 |
// TODO: Set AllowUndefs = true. |
--- |
| 7592 |
if (SDValue NotOperand = getBitwiseNotOperand(N01, N00, |
0 |
7592 |
if (SDValue NotOperand = getBitwiseNotOperand(N01, N00, |
0 |
| 7593 |
/* AllowUndefs */ false)) { |
0 |
7593 |
/* AllowUndefs */ false)) { |
0 |
| 7594 |
if (peekThroughResize(NotOperand) == N1Resized) |
0 |
7594 |
if (peekThroughResize(NotOperand) == N1Resized) |
0 |
| 7595 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, |
0 |
7595 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, |
0 |
| 7596 |
DAG.getZExtOrTrunc(N00, SDLoc(N), VT), N1); |
0 |
7596 |
DAG.getZExtOrTrunc(N00, SDLoc(N), VT), N1); |
0 |
| 7597 |
} |
--- |
7597 |
} |
--- |
| 7598 |
|
--- |
7598 |
|
--- |
| 7599 |
// fold (or (and (xor Y, -1), X), Y) -> (or X, Y) |
--- |
7599 |
// fold (or (and (xor Y, -1), X), Y) -> (or X, Y) |
--- |
| 7600 |
if (SDValue NotOperand = getBitwiseNotOperand(N00, N01, |
0 |
7600 |
if (SDValue NotOperand = getBitwiseNotOperand(N00, N01, |
0 |
| 7601 |
/* AllowUndefs */ false)) { |
0 |
7601 |
/* AllowUndefs */ false)) { |
0 |
| 7602 |
if (peekThroughResize(NotOperand) == N1Resized) |
0 |
7602 |
if (peekThroughResize(NotOperand) == N1Resized) |
0 |
| 7603 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, |
0 |
7603 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, |
0 |
| 7604 |
DAG.getZExtOrTrunc(N01, SDLoc(N), VT), N1); |
0 |
7604 |
DAG.getZExtOrTrunc(N01, SDLoc(N), VT), N1); |
0 |
| 7605 |
} |
--- |
7605 |
} |
--- |
| 7606 |
} |
--- |
7606 |
} |
--- |
| 7607 |
|
--- |
7607 |
|
--- |
| 7608 |
if (N0.getOpcode() == ISD::XOR) { |
0 |
7608 |
if (N0.getOpcode() == ISD::XOR) { |
0 |
| 7609 |
// fold or (xor x, y), x --> or x, y |
--- |
7609 |
// fold or (xor x, y), x --> or x, y |
--- |
| 7610 |
// or (xor x, y), (x and/or y) --> or x, y |
--- |
7610 |
// or (xor x, y), (x and/or y) --> or x, y |
--- |
| 7611 |
SDValue N00 = N0.getOperand(0); |
0 |
7611 |
SDValue N00 = N0.getOperand(0); |
0 |
| 7612 |
SDValue N01 = N0.getOperand(1); |
0 |
7612 |
SDValue N01 = N0.getOperand(1); |
0 |
| 7613 |
if (N00 == N1) |
0 |
7613 |
if (N00 == N1) |
0 |
| 7614 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, N01, N1); |
0 |
7614 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, N01, N1); |
0 |
| 7615 |
if (N01 == N1) |
0 |
7615 |
if (N01 == N1) |
0 |
| 7616 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, N00, N1); |
0 |
7616 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, N00, N1); |
0 |
| 7617 |
|
--- |
7617 |
|
--- |
| 7618 |
if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { |
0 |
7618 |
if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { |
0 |
| 7619 |
SDValue N10 = N1.getOperand(0); |
0 |
7619 |
SDValue N10 = N1.getOperand(0); |
0 |
| 7620 |
SDValue N11 = N1.getOperand(1); |
0 |
7620 |
SDValue N11 = N1.getOperand(1); |
0 |
| 7621 |
if ((N00 == N10 && N01 == N11) || (N00 == N11 && N01 == N10)) |
0 |
7621 |
if ((N00 == N10 && N01 == N11) || (N00 == N11 && N01 == N10)) |
0 |
| 7622 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, N00, N01); |
0 |
7622 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, N00, N01); |
0 |
| 7623 |
} |
--- |
7623 |
} |
--- |
| 7624 |
} |
--- |
7624 |
} |
--- |
| 7625 |
|
--- |
7625 |
|
--- |
| 7626 |
if (SDValue R = foldLogicOfShifts(N, N0, N1, DAG)) |
0 |
7626 |
if (SDValue R = foldLogicOfShifts(N, N0, N1, DAG)) |
0 |
| 7627 |
return R; |
0 |
7627 |
return R; |
0 |
| 7628 |
|
--- |
7628 |
|
--- |
| 7629 |
auto peekThroughZext = [](SDValue V) { |
0 |
7629 |
auto peekThroughZext = [](SDValue V) { |
0 |
| 7630 |
if (V->getOpcode() == ISD::ZERO_EXTEND) |
0 |
7630 |
if (V->getOpcode() == ISD::ZERO_EXTEND) |
0 |
| 7631 |
return V->getOperand(0); |
0 |
7631 |
return V->getOperand(0); |
0 |
| 7632 |
return V; |
0 |
7632 |
return V; |
0 |
| 7633 |
}; |
--- |
7633 |
}; |
--- |
| 7634 |
|
--- |
7634 |
|
--- |
| 7635 |
// (fshl X, ?, Y) | (shl X, Y) --> fshl X, ?, Y |
--- |
7635 |
// (fshl X, ?, Y) | (shl X, Y) --> fshl X, ?, Y |
--- |
| 7636 |
if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL && |
0 |
7636 |
if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL && |
0 |
| 7637 |
N0.getOperand(0) == N1.getOperand(0) && |
0 |
7637 |
N0.getOperand(0) == N1.getOperand(0) && |
0 |
| 7638 |
peekThroughZext(N0.getOperand(2)) == peekThroughZext(N1.getOperand(1))) |
0 |
7638 |
peekThroughZext(N0.getOperand(2)) == peekThroughZext(N1.getOperand(1))) |
0 |
| 7639 |
return N0; |
0 |
7639 |
return N0; |
0 |
| 7640 |
|
--- |
7640 |
|
--- |
| 7641 |
// (fshr ?, X, Y) | (srl X, Y) --> fshr ?, X, Y |
--- |
7641 |
// (fshr ?, X, Y) | (srl X, Y) --> fshr ?, X, Y |
--- |
| 7642 |
if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && |
0 |
7642 |
if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && |
0 |
| 7643 |
N0.getOperand(1) == N1.getOperand(0) && |
0 |
7643 |
N0.getOperand(1) == N1.getOperand(0) && |
0 |
| 7644 |
peekThroughZext(N0.getOperand(2)) == peekThroughZext(N1.getOperand(1))) |
0 |
7644 |
peekThroughZext(N0.getOperand(2)) == peekThroughZext(N1.getOperand(1))) |
0 |
| 7645 |
return N0; |
0 |
7645 |
return N0; |
0 |
| 7646 |
|
--- |
7646 |
|
--- |
| 7647 |
return SDValue(); |
0 |
7647 |
return SDValue(); |
0 |
| 7648 |
} |
--- |
7648 |
} |
--- |
| 7649 |
|
--- |
7649 |
|
--- |
| 7650 |
SDValue DAGCombiner::visitOR(SDNode *N) { |
0 |
7650 |
SDValue DAGCombiner::visitOR(SDNode *N) { |
0 |
| 7651 |
SDValue N0 = N->getOperand(0); |
0 |
7651 |
SDValue N0 = N->getOperand(0); |
0 |
| 7652 |
SDValue N1 = N->getOperand(1); |
0 |
7652 |
SDValue N1 = N->getOperand(1); |
0 |
| 7653 |
EVT VT = N1.getValueType(); |
0 |
7653 |
EVT VT = N1.getValueType(); |
0 |
| 7654 |
|
--- |
7654 |
|
--- |
| 7655 |
// x | x --> x |
--- |
7655 |
// x | x --> x |
--- |
| 7656 |
if (N0 == N1) |
0 |
7656 |
if (N0 == N1) |
0 |
| 7657 |
return N0; |
0 |
7657 |
return N0; |
0 |
| 7658 |
|
--- |
7658 |
|
--- |
| 7659 |
// fold (or c1, c2) -> c1|c2 |
--- |
7659 |
// fold (or c1, c2) -> c1|c2 |
--- |
| 7660 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, {N0, N1})) |
0 |
7660 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, {N0, N1})) |
0 |
| 7661 |
return C; |
0 |
7661 |
return C; |
0 |
| 7662 |
|
--- |
7662 |
|
--- |
| 7663 |
// canonicalize constant to RHS |
--- |
7663 |
// canonicalize constant to RHS |
--- |
| 7664 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
7664 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 7665 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
7665 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 7666 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0); |
0 |
7666 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0); |
0 |
| 7667 |
|
--- |
7667 |
|
--- |
| 7668 |
// fold vector ops |
--- |
7668 |
// fold vector ops |
--- |
| 7669 |
if (VT.isVector()) { |
0 |
7669 |
if (VT.isVector()) { |
0 |
| 7670 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N))) |
0 |
7670 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N))) |
0 |
| 7671 |
return FoldedVOp; |
0 |
7671 |
return FoldedVOp; |
0 |
| 7672 |
|
--- |
7672 |
|
--- |
| 7673 |
// fold (or x, 0) -> x, vector edition |
--- |
7673 |
// fold (or x, 0) -> x, vector edition |
--- |
| 7674 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
7674 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
| 7675 |
return N0; |
0 |
7675 |
return N0; |
0 |
| 7676 |
|
--- |
7676 |
|
--- |
| 7677 |
// fold (or x, -1) -> -1, vector edition |
--- |
7677 |
// fold (or x, -1) -> -1, vector edition |
--- |
| 7678 |
if (ISD::isConstantSplatVectorAllOnes(N1.getNode())) |
0 |
7678 |
if (ISD::isConstantSplatVectorAllOnes(N1.getNode())) |
0 |
| 7679 |
// do not return N1, because undef node may exist in N1 |
--- |
7679 |
// do not return N1, because undef node may exist in N1 |
--- |
| 7680 |
return DAG.getAllOnesConstant(SDLoc(N), N1.getValueType()); |
0 |
7680 |
return DAG.getAllOnesConstant(SDLoc(N), N1.getValueType()); |
0 |
| 7681 |
|
--- |
7681 |
|
--- |
| 7682 |
// fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask) |
--- |
7682 |
// fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask) |
--- |
| 7683 |
// Do this only if the resulting type / shuffle is legal. |
--- |
7683 |
// Do this only if the resulting type / shuffle is legal. |
--- |
| 7684 |
auto *SV0 = dyn_cast(N0); |
0 |
7684 |
auto *SV0 = dyn_cast(N0); |
0 |
| 7685 |
auto *SV1 = dyn_cast(N1); |
0 |
7685 |
auto *SV1 = dyn_cast(N1); |
0 |
| 7686 |
if (SV0 && SV1 && TLI.isTypeLegal(VT)) { |
0 |
7686 |
if (SV0 && SV1 && TLI.isTypeLegal(VT)) { |
0 |
| 7687 |
bool ZeroN00 = ISD::isBuildVectorAllZeros(N0.getOperand(0).getNode()); |
0 |
7687 |
bool ZeroN00 = ISD::isBuildVectorAllZeros(N0.getOperand(0).getNode()); |
0 |
| 7688 |
bool ZeroN01 = ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode()); |
0 |
7688 |
bool ZeroN01 = ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode()); |
0 |
| 7689 |
bool ZeroN10 = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode()); |
0 |
7689 |
bool ZeroN10 = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode()); |
0 |
| 7690 |
bool ZeroN11 = ISD::isBuildVectorAllZeros(N1.getOperand(1).getNode()); |
0 |
7690 |
bool ZeroN11 = ISD::isBuildVectorAllZeros(N1.getOperand(1).getNode()); |
0 |
| 7691 |
// Ensure both shuffles have a zero input. |
--- |
7691 |
// Ensure both shuffles have a zero input. |
--- |
| 7692 |
if ((ZeroN00 != ZeroN01) && (ZeroN10 != ZeroN11)) { |
0 |
7692 |
if ((ZeroN00 != ZeroN01) && (ZeroN10 != ZeroN11)) { |
0 |
| 7693 |
assert((!ZeroN00 || !ZeroN01) && "Both inputs zero!"); |
0 |
7693 |
assert((!ZeroN00 || !ZeroN01) && "Both inputs zero!"); |
0 |
| 7694 |
assert((!ZeroN10 || !ZeroN11) && "Both inputs zero!"); |
0 |
7694 |
assert((!ZeroN10 || !ZeroN11) && "Both inputs zero!"); |
0 |
| 7695 |
bool CanFold = true; |
0 |
7695 |
bool CanFold = true; |
0 |
| 7696 |
int NumElts = VT.getVectorNumElements(); |
0 |
7696 |
int NumElts = VT.getVectorNumElements(); |
0 |
| 7697 |
SmallVector Mask(NumElts, -1); |
0 |
7697 |
SmallVector Mask(NumElts, -1); |
0 |
| 7698 |
|
--- |
7698 |
|
--- |
| 7699 |
for (int i = 0; i != NumElts; ++i) { |
0 |
7699 |
for (int i = 0; i != NumElts; ++i) { |
0 |
| 7700 |
int M0 = SV0->getMaskElt(i); |
0 |
7700 |
int M0 = SV0->getMaskElt(i); |
0 |
| 7701 |
int M1 = SV1->getMaskElt(i); |
0 |
7701 |
int M1 = SV1->getMaskElt(i); |
0 |
| 7702 |
|
--- |
7702 |
|
--- |
| 7703 |
// Determine if either index is pointing to a zero vector. |
--- |
7703 |
// Determine if either index is pointing to a zero vector. |
--- |
| 7704 |
bool M0Zero = M0 < 0 || (ZeroN00 == (M0 < NumElts)); |
0 |
7704 |
bool M0Zero = M0 < 0 || (ZeroN00 == (M0 < NumElts)); |
0 |
| 7705 |
bool M1Zero = M1 < 0 || (ZeroN10 == (M1 < NumElts)); |
0 |
7705 |
bool M1Zero = M1 < 0 || (ZeroN10 == (M1 < NumElts)); |
0 |
| 7706 |
|
--- |
7706 |
|
--- |
| 7707 |
// If one element is zero and the otherside is undef, keep undef. |
--- |
7707 |
// If one element is zero and the otherside is undef, keep undef. |
--- |
| 7708 |
// This also handles the case that both are undef. |
--- |
7708 |
// This also handles the case that both are undef. |
--- |
| 7709 |
if ((M0Zero && M1 < 0) || (M1Zero && M0 < 0)) |
0 |
7709 |
if ((M0Zero && M1 < 0) || (M1Zero && M0 < 0)) |
0 |
| 7710 |
continue; |
0 |
7710 |
continue; |
0 |
| 7711 |
|
--- |
7711 |
|
--- |
| 7712 |
// Make sure only one of the elements is zero. |
--- |
7712 |
// Make sure only one of the elements is zero. |
--- |
| 7713 |
if (M0Zero == M1Zero) { |
0 |
7713 |
if (M0Zero == M1Zero) { |
0 |
| 7714 |
CanFold = false; |
0 |
7714 |
CanFold = false; |
0 |
| 7715 |
break; |
0 |
7715 |
break; |
0 |
| 7716 |
} |
--- |
7716 |
} |
--- |
| 7717 |
|
--- |
7717 |
|
--- |
| 7718 |
assert((M0 >= 0 || M1 >= 0) && "Undef index!"); |
0 |
7718 |
assert((M0 >= 0 || M1 >= 0) && "Undef index!"); |
0 |
| 7719 |
|
--- |
7719 |
|
--- |
| 7720 |
// We have a zero and non-zero element. If the non-zero came from |
--- |
7720 |
// We have a zero and non-zero element. If the non-zero came from |
--- |
| 7721 |
// SV0 make the index a LHS index. If it came from SV1, make it |
--- |
7721 |
// SV0 make the index a LHS index. If it came from SV1, make it |
--- |
| 7722 |
// a RHS index. We need to mod by NumElts because we don't care |
--- |
7722 |
// a RHS index. We need to mod by NumElts because we don't care |
--- |
| 7723 |
// which operand it came from in the original shuffles. |
--- |
7723 |
// which operand it came from in the original shuffles. |
--- |
| 7724 |
Mask[i] = M1Zero ? M0 % NumElts : (M1 % NumElts) + NumElts; |
0 |
7724 |
Mask[i] = M1Zero ? M0 % NumElts : (M1 % NumElts) + NumElts; |
0 |
| 7725 |
} |
--- |
7725 |
} |
--- |
| 7726 |
|
--- |
7726 |
|
--- |
| 7727 |
if (CanFold) { |
0 |
7727 |
if (CanFold) { |
0 |
| 7728 |
SDValue NewLHS = ZeroN00 ? N0.getOperand(1) : N0.getOperand(0); |
0 |
7728 |
SDValue NewLHS = ZeroN00 ? N0.getOperand(1) : N0.getOperand(0); |
0 |
| 7729 |
SDValue NewRHS = ZeroN10 ? N1.getOperand(1) : N1.getOperand(0); |
0 |
7729 |
SDValue NewRHS = ZeroN10 ? N1.getOperand(1) : N1.getOperand(0); |
0 |
| 7730 |
|
--- |
7730 |
|
--- |
| 7731 |
SDValue LegalShuffle = |
--- |
7731 |
SDValue LegalShuffle = |
--- |
| 7732 |
TLI.buildLegalVectorShuffle(VT, SDLoc(N), NewLHS, NewRHS, |
0 |
7732 |
TLI.buildLegalVectorShuffle(VT, SDLoc(N), NewLHS, NewRHS, |
0 |
| 7733 |
Mask, DAG); |
--- |
7733 |
Mask, DAG); |
--- |
| 7734 |
if (LegalShuffle) |
0 |
7734 |
if (LegalShuffle) |
0 |
| 7735 |
return LegalShuffle; |
0 |
7735 |
return LegalShuffle; |
0 |
| 7736 |
} |
--- |
7736 |
} |
--- |
| 7737 |
} |
0 |
7737 |
} |
0 |
| 7738 |
} |
--- |
7738 |
} |
--- |
| 7739 |
} |
--- |
7739 |
} |
--- |
| 7740 |
|
--- |
7740 |
|
--- |
| 7741 |
// fold (or x, 0) -> x |
--- |
7741 |
// fold (or x, 0) -> x |
--- |
| 7742 |
if (isNullConstant(N1)) |
0 |
7742 |
if (isNullConstant(N1)) |
0 |
| 7743 |
return N0; |
0 |
7743 |
return N0; |
0 |
| 7744 |
|
--- |
7744 |
|
--- |
| 7745 |
// fold (or x, -1) -> -1 |
--- |
7745 |
// fold (or x, -1) -> -1 |
--- |
| 7746 |
if (isAllOnesConstant(N1)) |
0 |
7746 |
if (isAllOnesConstant(N1)) |
0 |
| 7747 |
return N1; |
0 |
7747 |
return N1; |
0 |
| 7748 |
|
--- |
7748 |
|
--- |
| 7749 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
7749 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 7750 |
return NewSel; |
0 |
7750 |
return NewSel; |
0 |
| 7751 |
|
--- |
7751 |
|
--- |
| 7752 |
// fold (or x, c) -> c iff (x & ~c) == 0 |
--- |
7752 |
// fold (or x, c) -> c iff (x & ~c) == 0 |
--- |
| 7753 |
ConstantSDNode *N1C = dyn_cast(N1); |
0 |
7753 |
ConstantSDNode *N1C = dyn_cast(N1); |
0 |
| 7754 |
if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) |
0 |
7754 |
if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) |
0 |
| 7755 |
return N1; |
0 |
7755 |
return N1; |
0 |
| 7756 |
|
--- |
7756 |
|
--- |
| 7757 |
if (SDValue R = foldAndOrOfSETCC(N, DAG)) |
0 |
7757 |
if (SDValue R = foldAndOrOfSETCC(N, DAG)) |
0 |
| 7758 |
return R; |
0 |
7758 |
return R; |
0 |
| 7759 |
|
--- |
7759 |
|
--- |
| 7760 |
if (SDValue Combined = visitORLike(N0, N1, N)) |
0 |
7760 |
if (SDValue Combined = visitORLike(N0, N1, N)) |
0 |
| 7761 |
return Combined; |
0 |
7761 |
return Combined; |
0 |
| 7762 |
|
--- |
7762 |
|
--- |
| 7763 |
if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N)) |
0 |
7763 |
if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N)) |
0 |
| 7764 |
return Combined; |
0 |
7764 |
return Combined; |
0 |
| 7765 |
|
--- |
7765 |
|
--- |
| 7766 |
// Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) |
--- |
7766 |
// Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) |
--- |
| 7767 |
if (SDValue BSwap = MatchBSwapHWord(N, N0, N1)) |
0 |
7767 |
if (SDValue BSwap = MatchBSwapHWord(N, N0, N1)) |
0 |
| 7768 |
return BSwap; |
0 |
7768 |
return BSwap; |
0 |
| 7769 |
if (SDValue BSwap = MatchBSwapHWordLow(N, N0, N1)) |
0 |
7769 |
if (SDValue BSwap = MatchBSwapHWordLow(N, N0, N1)) |
0 |
| 7770 |
return BSwap; |
0 |
7770 |
return BSwap; |
0 |
| 7771 |
|
--- |
7771 |
|
--- |
| 7772 |
// reassociate or |
--- |
7772 |
// reassociate or |
--- |
| 7773 |
if (SDValue ROR = reassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags())) |
0 |
7773 |
if (SDValue ROR = reassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags())) |
0 |
| 7774 |
return ROR; |
0 |
7774 |
return ROR; |
0 |
| 7775 |
|
--- |
7775 |
|
--- |
| 7776 |
// Fold or(vecreduce(x), vecreduce(y)) -> vecreduce(or(x, y)) |
--- |
7776 |
// Fold or(vecreduce(x), vecreduce(y)) -> vecreduce(or(x, y)) |
--- |
| 7777 |
if (SDValue SD = reassociateReduction(ISD::VECREDUCE_OR, ISD::OR, SDLoc(N), |
0 |
7777 |
if (SDValue SD = reassociateReduction(ISD::VECREDUCE_OR, ISD::OR, SDLoc(N), |
0 |
| 7778 |
VT, N0, N1)) |
0 |
7778 |
VT, N0, N1)) |
0 |
| 7779 |
return SD; |
0 |
7779 |
return SD; |
0 |
| 7780 |
|
--- |
7780 |
|
--- |
| 7781 |
// Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) |
--- |
7781 |
// Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) |
--- |
| 7782 |
// iff (c1 & c2) != 0 or c1/c2 are undef. |
--- |
7782 |
// iff (c1 & c2) != 0 or c1/c2 are undef. |
--- |
| 7783 |
auto MatchIntersect = [](ConstantSDNode *C1, ConstantSDNode *C2) { |
0 |
7783 |
auto MatchIntersect = [](ConstantSDNode *C1, ConstantSDNode *C2) { |
0 |
| 7784 |
return !C1 || !C2 || C1->getAPIntValue().intersects(C2->getAPIntValue()); |
0 |
7784 |
return !C1 || !C2 || C1->getAPIntValue().intersects(C2->getAPIntValue()); |
0 |
| 7785 |
}; |
--- |
7785 |
}; |
--- |
| 7786 |
if (N0.getOpcode() == ISD::AND && N0->hasOneUse() && |
0 |
7786 |
if (N0.getOpcode() == ISD::AND && N0->hasOneUse() && |
0 |
| 7787 |
ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchIntersect, true)) { |
0 |
7787 |
ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchIntersect, true)) { |
0 |
| 7788 |
if (SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N1), VT, |
0 |
7788 |
if (SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N1), VT, |
0 |
| 7789 |
{N1, N0.getOperand(1)})) { |
0 |
7789 |
{N1, N0.getOperand(1)})) { |
0 |
| 7790 |
SDValue IOR = DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1); |
0 |
7790 |
SDValue IOR = DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1); |
0 |
| 7791 |
AddToWorklist(IOR.getNode()); |
0 |
7791 |
AddToWorklist(IOR.getNode()); |
0 |
| 7792 |
return DAG.getNode(ISD::AND, SDLoc(N), VT, COR, IOR); |
0 |
7792 |
return DAG.getNode(ISD::AND, SDLoc(N), VT, COR, IOR); |
0 |
| 7793 |
} |
--- |
7793 |
} |
--- |
| 7794 |
} |
--- |
7794 |
} |
--- |
| 7795 |
|
--- |
7795 |
|
--- |
| 7796 |
if (SDValue Combined = visitORCommutative(DAG, N0, N1, N)) |
0 |
7796 |
if (SDValue Combined = visitORCommutative(DAG, N0, N1, N)) |
0 |
| 7797 |
return Combined; |
0 |
7797 |
return Combined; |
0 |
| 7798 |
if (SDValue Combined = visitORCommutative(DAG, N1, N0, N)) |
0 |
7798 |
if (SDValue Combined = visitORCommutative(DAG, N1, N0, N)) |
0 |
| 7799 |
return Combined; |
0 |
7799 |
return Combined; |
0 |
| 7800 |
|
--- |
7800 |
|
--- |
| 7801 |
// Simplify: (or (op x...), (op y...)) -> (op (or x, y)) |
--- |
7801 |
// Simplify: (or (op x...), (op y...)) -> (op (or x, y)) |
--- |
| 7802 |
if (N0.getOpcode() == N1.getOpcode()) |
0 |
7802 |
if (N0.getOpcode() == N1.getOpcode()) |
0 |
| 7803 |
if (SDValue V = hoistLogicOpWithSameOpcodeHands(N)) |
0 |
7803 |
if (SDValue V = hoistLogicOpWithSameOpcodeHands(N)) |
0 |
| 7804 |
return V; |
0 |
7804 |
return V; |
0 |
| 7805 |
|
--- |
7805 |
|
--- |
| 7806 |
// See if this is some rotate idiom. |
--- |
7806 |
// See if this is some rotate idiom. |
--- |
| 7807 |
if (SDValue Rot = MatchRotate(N0, N1, SDLoc(N))) |
0 |
7807 |
if (SDValue Rot = MatchRotate(N0, N1, SDLoc(N))) |
0 |
| 7808 |
return Rot; |
0 |
7808 |
return Rot; |
0 |
| 7809 |
|
--- |
7809 |
|
--- |
| 7810 |
if (SDValue Load = MatchLoadCombine(N)) |
0 |
7810 |
if (SDValue Load = MatchLoadCombine(N)) |
0 |
| 7811 |
return Load; |
0 |
7811 |
return Load; |
0 |
| 7812 |
|
--- |
7812 |
|
--- |
| 7813 |
// Simplify the operands using demanded-bits information. |
--- |
7813 |
// Simplify the operands using demanded-bits information. |
--- |
| 7814 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
7814 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
| 7815 |
return SDValue(N, 0); |
0 |
7815 |
return SDValue(N, 0); |
0 |
| 7816 |
|
--- |
7816 |
|
--- |
| 7817 |
// If OR can be rewritten into ADD, try combines based on ADD. |
--- |
7817 |
// If OR can be rewritten into ADD, try combines based on ADD. |
--- |
| 7818 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::ADD, VT)) && |
0 |
7818 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::ADD, VT)) && |
0 |
| 7819 |
DAG.haveNoCommonBitsSet(N0, N1)) |
0 |
7819 |
DAG.haveNoCommonBitsSet(N0, N1)) |
0 |
| 7820 |
if (SDValue Combined = visitADDLike(N)) |
0 |
7820 |
if (SDValue Combined = visitADDLike(N)) |
0 |
| 7821 |
return Combined; |
0 |
7821 |
return Combined; |
0 |
| 7822 |
|
--- |
7822 |
|
--- |
| 7823 |
// Postpone until legalization completed to avoid interference with bswap |
--- |
7823 |
// Postpone until legalization completed to avoid interference with bswap |
--- |
| 7824 |
// folding |
--- |
7824 |
// folding |
--- |
| 7825 |
if (LegalOperations || VT.isVector()) |
0 |
7825 |
if (LegalOperations || VT.isVector()) |
0 |
| 7826 |
if (SDValue R = foldLogicTreeOfShifts(N, N0, N1, DAG)) |
0 |
7826 |
if (SDValue R = foldLogicTreeOfShifts(N, N0, N1, DAG)) |
0 |
| 7827 |
return R; |
0 |
7827 |
return R; |
0 |
| 7828 |
|
--- |
7828 |
|
--- |
| 7829 |
return SDValue(); |
0 |
7829 |
return SDValue(); |
0 |
| 7830 |
} |
--- |
7830 |
} |
--- |
| 7831 |
|
--- |
7831 |
|
--- |
| 7832 |
static SDValue stripConstantMask(const SelectionDAG &DAG, SDValue Op, |
0 |
7832 |
static SDValue stripConstantMask(const SelectionDAG &DAG, SDValue Op, |
0 |
| 7833 |
SDValue &Mask) { |
--- |
7833 |
SDValue &Mask) { |
--- |
| 7834 |
if (Op.getOpcode() == ISD::AND && |
0 |
7834 |
if (Op.getOpcode() == ISD::AND && |
0 |
| 7835 |
DAG.isConstantIntBuildVectorOrConstantInt(Op.getOperand(1))) { |
0 |
7835 |
DAG.isConstantIntBuildVectorOrConstantInt(Op.getOperand(1))) { |
0 |
| 7836 |
Mask = Op.getOperand(1); |
0 |
7836 |
Mask = Op.getOperand(1); |
0 |
| 7837 |
return Op.getOperand(0); |
0 |
7837 |
return Op.getOperand(0); |
0 |
| 7838 |
} |
--- |
7838 |
} |
--- |
| 7839 |
return Op; |
0 |
7839 |
return Op; |
0 |
| 7840 |
} |
--- |
7840 |
} |
--- |
| 7841 |
|
--- |
7841 |
|
--- |
| 7842 |
/// Match "(X shl/srl V1) & V2" where V2 may not be present. |
--- |
7842 |
/// Match "(X shl/srl V1) & V2" where V2 may not be present. |
--- |
| 7843 |
static bool matchRotateHalf(const SelectionDAG &DAG, SDValue Op, SDValue &Shift, |
0 |
7843 |
static bool matchRotateHalf(const SelectionDAG &DAG, SDValue Op, SDValue &Shift, |
0 |
| 7844 |
SDValue &Mask) { |
--- |
7844 |
SDValue &Mask) { |
--- |
| 7845 |
Op = stripConstantMask(DAG, Op, Mask); |
0 |
7845 |
Op = stripConstantMask(DAG, Op, Mask); |
0 |
| 7846 |
if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { |
0 |
7846 |
if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { |
0 |
| 7847 |
Shift = Op; |
0 |
7847 |
Shift = Op; |
0 |
| 7848 |
return true; |
0 |
7848 |
return true; |
0 |
| 7849 |
} |
--- |
7849 |
} |
--- |
| 7850 |
return false; |
0 |
7850 |
return false; |
0 |
| 7851 |
} |
--- |
7851 |
} |
--- |
| 7852 |
|
--- |
7852 |
|
--- |
| 7853 |
/// Helper function for visitOR to extract the needed side of a rotate idiom |
--- |
7853 |
/// Helper function for visitOR to extract the needed side of a rotate idiom |
--- |
| 7854 |
/// from a shl/srl/mul/udiv. This is meant to handle cases where |
--- |
7854 |
/// from a shl/srl/mul/udiv. This is meant to handle cases where |
--- |
| 7855 |
/// InstCombine merged some outside op with one of the shifts from |
--- |
7855 |
/// InstCombine merged some outside op with one of the shifts from |
--- |
| 7856 |
/// the rotate pattern. |
--- |
7856 |
/// the rotate pattern. |
--- |
| 7857 |
/// \returns An empty \c SDValue if the needed shift couldn't be extracted. |
--- |
7857 |
/// \returns An empty \c SDValue if the needed shift couldn't be extracted. |
--- |
| 7858 |
/// Otherwise, returns an expansion of \p ExtractFrom based on the following |
--- |
7858 |
/// Otherwise, returns an expansion of \p ExtractFrom based on the following |
--- |
| 7859 |
/// patterns: |
--- |
7859 |
/// patterns: |
--- |
| 7860 |
/// |
--- |
7860 |
/// |
--- |
| 7861 |
/// (or (add v v) (shrl v bitwidth-1)): |
--- |
7861 |
/// (or (add v v) (shrl v bitwidth-1)): |
--- |
| 7862 |
/// expands (add v v) -> (shl v 1) |
--- |
7862 |
/// expands (add v v) -> (shl v 1) |
--- |
| 7863 |
/// |
--- |
7863 |
/// |
--- |
| 7864 |
/// (or (mul v c0) (shrl (mul v c1) c2)): |
--- |
7864 |
/// (or (mul v c0) (shrl (mul v c1) c2)): |
--- |
| 7865 |
/// expands (mul v c0) -> (shl (mul v c1) c3) |
--- |
7865 |
/// expands (mul v c0) -> (shl (mul v c1) c3) |
--- |
| 7866 |
/// |
--- |
7866 |
/// |
--- |
| 7867 |
/// (or (udiv v c0) (shl (udiv v c1) c2)): |
--- |
7867 |
/// (or (udiv v c0) (shl (udiv v c1) c2)): |
--- |
| 7868 |
/// expands (udiv v c0) -> (shrl (udiv v c1) c3) |
--- |
7868 |
/// expands (udiv v c0) -> (shrl (udiv v c1) c3) |
--- |
| 7869 |
/// |
--- |
7869 |
/// |
--- |
| 7870 |
/// (or (shl v c0) (shrl (shl v c1) c2)): |
--- |
7870 |
/// (or (shl v c0) (shrl (shl v c1) c2)): |
--- |
| 7871 |
/// expands (shl v c0) -> (shl (shl v c1) c3) |
--- |
7871 |
/// expands (shl v c0) -> (shl (shl v c1) c3) |
--- |
| 7872 |
/// |
--- |
7872 |
/// |
--- |
| 7873 |
/// (or (shrl v c0) (shl (shrl v c1) c2)): |
--- |
7873 |
/// (or (shrl v c0) (shl (shrl v c1) c2)): |
--- |
| 7874 |
/// expands (shrl v c0) -> (shrl (shrl v c1) c3) |
--- |
7874 |
/// expands (shrl v c0) -> (shrl (shrl v c1) c3) |
--- |
| 7875 |
/// |
--- |
7875 |
/// |
--- |
| 7876 |
/// Such that in all cases, c3+c2==bitwidth(op v c1). |
--- |
7876 |
/// Such that in all cases, c3+c2==bitwidth(op v c1). |
--- |
| 7877 |
static SDValue extractShiftForRotate(SelectionDAG &DAG, SDValue OppShift, |
0 |
7877 |
static SDValue extractShiftForRotate(SelectionDAG &DAG, SDValue OppShift, |
0 |
| 7878 |
SDValue ExtractFrom, SDValue &Mask, |
--- |
7878 |
SDValue ExtractFrom, SDValue &Mask, |
--- |
| 7879 |
const SDLoc &DL) { |
--- |
7879 |
const SDLoc &DL) { |
--- |
| 7880 |
assert(OppShift && ExtractFrom && "Empty SDValue"); |
0 |
7880 |
assert(OppShift && ExtractFrom && "Empty SDValue"); |
0 |
| 7881 |
if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL) |
0 |
7881 |
if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL) |
0 |
| 7882 |
return SDValue(); |
0 |
7882 |
return SDValue(); |
0 |
| 7883 |
|
--- |
7883 |
|
--- |
| 7884 |
ExtractFrom = stripConstantMask(DAG, ExtractFrom, Mask); |
0 |
7884 |
ExtractFrom = stripConstantMask(DAG, ExtractFrom, Mask); |
0 |
| 7885 |
|
--- |
7885 |
|
--- |
| 7886 |
// Value and Type of the shift. |
--- |
7886 |
// Value and Type of the shift. |
--- |
| 7887 |
SDValue OppShiftLHS = OppShift.getOperand(0); |
0 |
7887 |
SDValue OppShiftLHS = OppShift.getOperand(0); |
0 |
| 7888 |
EVT ShiftedVT = OppShiftLHS.getValueType(); |
0 |
7888 |
EVT ShiftedVT = OppShiftLHS.getValueType(); |
0 |
| 7889 |
|
--- |
7889 |
|
--- |
| 7890 |
// Amount of the existing shift. |
--- |
7890 |
// Amount of the existing shift. |
--- |
| 7891 |
ConstantSDNode *OppShiftCst = isConstOrConstSplat(OppShift.getOperand(1)); |
0 |
7891 |
ConstantSDNode *OppShiftCst = isConstOrConstSplat(OppShift.getOperand(1)); |
0 |
| 7892 |
|
--- |
7892 |
|
--- |
| 7893 |
// (add v v) -> (shl v 1) |
--- |
7893 |
// (add v v) -> (shl v 1) |
--- |
| 7894 |
// TODO: Should this be a general DAG canonicalization? |
--- |
7894 |
// TODO: Should this be a general DAG canonicalization? |
--- |
| 7895 |
if (OppShift.getOpcode() == ISD::SRL && OppShiftCst && |
0 |
7895 |
if (OppShift.getOpcode() == ISD::SRL && OppShiftCst && |
0 |
| 7896 |
ExtractFrom.getOpcode() == ISD::ADD && |
0 |
7896 |
ExtractFrom.getOpcode() == ISD::ADD && |
0 |
| 7897 |
ExtractFrom.getOperand(0) == ExtractFrom.getOperand(1) && |
0 |
7897 |
ExtractFrom.getOperand(0) == ExtractFrom.getOperand(1) && |
0 |
| 7898 |
ExtractFrom.getOperand(0) == OppShiftLHS && |
0 |
7898 |
ExtractFrom.getOperand(0) == OppShiftLHS && |
0 |
| 7899 |
OppShiftCst->getAPIntValue() == ShiftedVT.getScalarSizeInBits() - 1) |
0 |
7899 |
OppShiftCst->getAPIntValue() == ShiftedVT.getScalarSizeInBits() - 1) |
0 |
| 7900 |
return DAG.getNode(ISD::SHL, DL, ShiftedVT, OppShiftLHS, |
0 |
7900 |
return DAG.getNode(ISD::SHL, DL, ShiftedVT, OppShiftLHS, |
0 |
| 7901 |
DAG.getShiftAmountConstant(1, ShiftedVT, DL)); |
0 |
7901 |
DAG.getShiftAmountConstant(1, ShiftedVT, DL)); |
0 |
| 7902 |
|
--- |
7902 |
|
--- |
| 7903 |
// Preconditions: |
--- |
7903 |
// Preconditions: |
--- |
| 7904 |
// (or (op0 v c0) (shiftl/r (op0 v c1) c2)) |
--- |
7904 |
// (or (op0 v c0) (shiftl/r (op0 v c1) c2)) |
--- |
| 7905 |
// |
--- |
7905 |
// |
--- |
| 7906 |
// Find opcode of the needed shift to be extracted from (op0 v c0). |
--- |
7906 |
// Find opcode of the needed shift to be extracted from (op0 v c0). |
--- |
| 7907 |
unsigned Opcode = ISD::DELETED_NODE; |
0 |
7907 |
unsigned Opcode = ISD::DELETED_NODE; |
0 |
| 7908 |
bool IsMulOrDiv = false; |
0 |
7908 |
bool IsMulOrDiv = false; |
0 |
| 7909 |
// Set Opcode and IsMulOrDiv if the extract opcode matches the needed shift |
--- |
7909 |
// Set Opcode and IsMulOrDiv if the extract opcode matches the needed shift |
--- |
| 7910 |
// opcode or its arithmetic (mul or udiv) variant. |
--- |
7910 |
// opcode or its arithmetic (mul or udiv) variant. |
--- |
| 7911 |
auto SelectOpcode = [&](unsigned NeededShift, unsigned MulOrDivVariant) { |
0 |
7911 |
auto SelectOpcode = [&](unsigned NeededShift, unsigned MulOrDivVariant) { |
0 |
| 7912 |
IsMulOrDiv = ExtractFrom.getOpcode() == MulOrDivVariant; |
0 |
7912 |
IsMulOrDiv = ExtractFrom.getOpcode() == MulOrDivVariant; |
0 |
| 7913 |
if (!IsMulOrDiv && ExtractFrom.getOpcode() != NeededShift) |
0 |
7913 |
if (!IsMulOrDiv && ExtractFrom.getOpcode() != NeededShift) |
0 |
| 7914 |
return false; |
0 |
7914 |
return false; |
0 |
| 7915 |
Opcode = NeededShift; |
0 |
7915 |
Opcode = NeededShift; |
0 |
| 7916 |
return true; |
0 |
7916 |
return true; |
0 |
| 7917 |
}; |
0 |
7917 |
}; |
0 |
| 7918 |
// op0 must be either the needed shift opcode or the mul/udiv equivalent |
--- |
7918 |
// op0 must be either the needed shift opcode or the mul/udiv equivalent |
--- |
| 7919 |
// that the needed shift can be extracted from. |
--- |
7919 |
// that the needed shift can be extracted from. |
--- |
| 7920 |
if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) && |
0 |
7920 |
if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) && |
0 |
| 7921 |
(OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV))) |
0 |
7921 |
(OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV))) |
0 |
| 7922 |
return SDValue(); |
0 |
7922 |
return SDValue(); |
0 |
| 7923 |
|
--- |
7923 |
|
--- |
| 7924 |
// op0 must be the same opcode on both sides, have the same LHS argument, |
--- |
7924 |
// op0 must be the same opcode on both sides, have the same LHS argument, |
--- |
| 7925 |
// and produce the same value type. |
--- |
7925 |
// and produce the same value type. |
--- |
| 7926 |
if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() || |
0 |
7926 |
if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() || |
0 |
| 7927 |
OppShiftLHS.getOperand(0) != ExtractFrom.getOperand(0) || |
0 |
7927 |
OppShiftLHS.getOperand(0) != ExtractFrom.getOperand(0) || |
0 |
| 7928 |
ShiftedVT != ExtractFrom.getValueType()) |
0 |
7928 |
ShiftedVT != ExtractFrom.getValueType()) |
0 |
| 7929 |
return SDValue(); |
0 |
7929 |
return SDValue(); |
0 |
| 7930 |
|
--- |
7930 |
|
--- |
| 7931 |
// Constant mul/udiv/shift amount from the RHS of the shift's LHS op. |
--- |
7931 |
// Constant mul/udiv/shift amount from the RHS of the shift's LHS op. |
--- |
| 7932 |
ConstantSDNode *OppLHSCst = isConstOrConstSplat(OppShiftLHS.getOperand(1)); |
0 |
7932 |
ConstantSDNode *OppLHSCst = isConstOrConstSplat(OppShiftLHS.getOperand(1)); |
0 |
| 7933 |
// Constant mul/udiv/shift amount from the RHS of the ExtractFrom op. |
--- |
7933 |
// Constant mul/udiv/shift amount from the RHS of the ExtractFrom op. |
--- |
| 7934 |
ConstantSDNode *ExtractFromCst = |
--- |
7934 |
ConstantSDNode *ExtractFromCst = |
--- |
| 7935 |
isConstOrConstSplat(ExtractFrom.getOperand(1)); |
0 |
7935 |
isConstOrConstSplat(ExtractFrom.getOperand(1)); |
0 |
| 7936 |
// TODO: We should be able to handle non-uniform constant vectors for these values |
--- |
7936 |
// TODO: We should be able to handle non-uniform constant vectors for these values |
--- |
| 7937 |
// Check that we have constant values. |
--- |
7937 |
// Check that we have constant values. |
--- |
| 7938 |
if (!OppShiftCst || !OppShiftCst->getAPIntValue() || |
0 |
7938 |
if (!OppShiftCst || !OppShiftCst->getAPIntValue() || |
0 |
| 7939 |
!OppLHSCst || !OppLHSCst->getAPIntValue() || |
0 |
7939 |
!OppLHSCst || !OppLHSCst->getAPIntValue() || |
0 |
| 7940 |
!ExtractFromCst || !ExtractFromCst->getAPIntValue()) |
0 |
7940 |
!ExtractFromCst || !ExtractFromCst->getAPIntValue()) |
0 |
| 7941 |
return SDValue(); |
0 |
7941 |
return SDValue(); |
0 |
| 7942 |
|
--- |
7942 |
|
--- |
| 7943 |
// Compute the shift amount we need to extract to complete the rotate. |
--- |
7943 |
// Compute the shift amount we need to extract to complete the rotate. |
--- |
| 7944 |
const unsigned VTWidth = ShiftedVT.getScalarSizeInBits(); |
0 |
7944 |
const unsigned VTWidth = ShiftedVT.getScalarSizeInBits(); |
0 |
| 7945 |
if (OppShiftCst->getAPIntValue().ugt(VTWidth)) |
0 |
7945 |
if (OppShiftCst->getAPIntValue().ugt(VTWidth)) |
0 |
| 7946 |
return SDValue(); |
0 |
7946 |
return SDValue(); |
0 |
| 7947 |
APInt NeededShiftAmt = VTWidth - OppShiftCst->getAPIntValue(); |
0 |
7947 |
APInt NeededShiftAmt = VTWidth - OppShiftCst->getAPIntValue(); |
0 |
| 7948 |
// Normalize the bitwidth of the two mul/udiv/shift constant operands. |
--- |
7948 |
// Normalize the bitwidth of the two mul/udiv/shift constant operands. |
--- |
| 7949 |
APInt ExtractFromAmt = ExtractFromCst->getAPIntValue(); |
0 |
7949 |
APInt ExtractFromAmt = ExtractFromCst->getAPIntValue(); |
0 |
| 7950 |
APInt OppLHSAmt = OppLHSCst->getAPIntValue(); |
0 |
7950 |
APInt OppLHSAmt = OppLHSCst->getAPIntValue(); |
0 |
| 7951 |
zeroExtendToMatch(ExtractFromAmt, OppLHSAmt); |
0 |
7951 |
zeroExtendToMatch(ExtractFromAmt, OppLHSAmt); |
0 |
| 7952 |
|
--- |
7952 |
|
--- |
| 7953 |
// Now try extract the needed shift from the ExtractFrom op and see if the |
--- |
7953 |
// Now try extract the needed shift from the ExtractFrom op and see if the |
--- |
| 7954 |
// result matches up with the existing shift's LHS op. |
--- |
7954 |
// result matches up with the existing shift's LHS op. |
--- |
| 7955 |
if (IsMulOrDiv) { |
0 |
7955 |
if (IsMulOrDiv) { |
0 |
| 7956 |
// Op to extract from is a mul or udiv by a constant. |
--- |
7956 |
// Op to extract from is a mul or udiv by a constant. |
--- |
| 7957 |
// Check: |
--- |
7957 |
// Check: |
--- |
| 7958 |
// c2 / (1 << (bitwidth(op0 v c0) - c1)) == c0 |
--- |
7958 |
// c2 / (1 << (bitwidth(op0 v c0) - c1)) == c0 |
--- |
| 7959 |
// c2 % (1 << (bitwidth(op0 v c0) - c1)) == 0 |
--- |
7959 |
// c2 % (1 << (bitwidth(op0 v c0) - c1)) == 0 |
--- |
| 7960 |
const APInt ExtractDiv = APInt::getOneBitSet(ExtractFromAmt.getBitWidth(), |
--- |
7960 |
const APInt ExtractDiv = APInt::getOneBitSet(ExtractFromAmt.getBitWidth(), |
--- |
| 7961 |
NeededShiftAmt.getZExtValue()); |
0 |
7961 |
NeededShiftAmt.getZExtValue()); |
0 |
| 7962 |
APInt ResultAmt; |
0 |
7962 |
APInt ResultAmt; |
0 |
| 7963 |
APInt Rem; |
0 |
7963 |
APInt Rem; |
0 |
| 7964 |
APInt::udivrem(ExtractFromAmt, ExtractDiv, ResultAmt, Rem); |
0 |
7964 |
APInt::udivrem(ExtractFromAmt, ExtractDiv, ResultAmt, Rem); |
0 |
| 7965 |
if (Rem != 0 || ResultAmt != OppLHSAmt) |
0 |
7965 |
if (Rem != 0 || ResultAmt != OppLHSAmt) |
0 |
| 7966 |
return SDValue(); |
0 |
7966 |
return SDValue(); |
0 |
| 7967 |
} else { |
0 |
7967 |
} else { |
0 |
| 7968 |
// Op to extract from is a shift by a constant. |
--- |
7968 |
// Op to extract from is a shift by a constant. |
--- |
| 7969 |
// Check: |
--- |
7969 |
// Check: |
--- |
| 7970 |
// c2 - (bitwidth(op0 v c0) - c1) == c0 |
--- |
7970 |
// c2 - (bitwidth(op0 v c0) - c1) == c0 |
--- |
| 7971 |
if (OppLHSAmt != ExtractFromAmt - NeededShiftAmt.zextOrTrunc( |
0 |
7971 |
if (OppLHSAmt != ExtractFromAmt - NeededShiftAmt.zextOrTrunc( |
0 |
| 7972 |
ExtractFromAmt.getBitWidth())) |
--- |
7972 |
ExtractFromAmt.getBitWidth())) |
--- |
| 7973 |
return SDValue(); |
0 |
7973 |
return SDValue(); |
0 |
| 7974 |
} |
--- |
7974 |
} |
--- |
| 7975 |
|
--- |
7975 |
|
--- |
| 7976 |
// Return the expanded shift op that should allow a rotate to be formed. |
--- |
7976 |
// Return the expanded shift op that should allow a rotate to be formed. |
--- |
| 7977 |
EVT ShiftVT = OppShift.getOperand(1).getValueType(); |
0 |
7977 |
EVT ShiftVT = OppShift.getOperand(1).getValueType(); |
0 |
| 7978 |
EVT ResVT = ExtractFrom.getValueType(); |
0 |
7978 |
EVT ResVT = ExtractFrom.getValueType(); |
0 |
| 7979 |
SDValue NewShiftNode = DAG.getConstant(NeededShiftAmt, DL, ShiftVT); |
0 |
7979 |
SDValue NewShiftNode = DAG.getConstant(NeededShiftAmt, DL, ShiftVT); |
0 |
| 7980 |
return DAG.getNode(Opcode, DL, ResVT, OppShiftLHS, NewShiftNode); |
0 |
7980 |
return DAG.getNode(Opcode, DL, ResVT, OppShiftLHS, NewShiftNode); |
0 |
| 7981 |
} |
0 |
7981 |
} |
0 |
| 7982 |
|
--- |
7982 |
|
--- |
| 7983 |
// Return true if we can prove that, whenever Neg and Pos are both in the |
--- |
7983 |
// Return true if we can prove that, whenever Neg and Pos are both in the |
--- |
| 7984 |
// range [0, EltSize), Neg == (Pos == 0 ? 0 : EltSize - Pos). This means that |
--- |
7984 |
// range [0, EltSize), Neg == (Pos == 0 ? 0 : EltSize - Pos). This means that |
--- |
| 7985 |
// for two opposing shifts shift1 and shift2 and a value X with OpBits bits: |
--- |
7985 |
// for two opposing shifts shift1 and shift2 and a value X with OpBits bits: |
--- |
| 7986 |
// |
--- |
7986 |
// |
--- |
| 7987 |
// (or (shift1 X, Neg), (shift2 X, Pos)) |
--- |
7987 |
// (or (shift1 X, Neg), (shift2 X, Pos)) |
--- |
| 7988 |
// |
--- |
7988 |
// |
--- |
| 7989 |
// reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate |
--- |
7989 |
// reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate |
--- |
| 7990 |
// in direction shift1 by Neg. The range [0, EltSize) means that we only need |
--- |
7990 |
// in direction shift1 by Neg. The range [0, EltSize) means that we only need |
--- |
| 7991 |
// to consider shift amounts with defined behavior. |
--- |
7991 |
// to consider shift amounts with defined behavior. |
--- |
| 7992 |
// |
--- |
7992 |
// |
--- |
| 7993 |
// The IsRotate flag should be set when the LHS of both shifts is the same. |
--- |
7993 |
// The IsRotate flag should be set when the LHS of both shifts is the same. |
--- |
| 7994 |
// Otherwise if matching a general funnel shift, it should be clear. |
--- |
7994 |
// Otherwise if matching a general funnel shift, it should be clear. |
--- |
| 7995 |
static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize, |
0 |
7995 |
static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize, |
0 |
| 7996 |
SelectionDAG &DAG, bool IsRotate) { |
--- |
7996 |
SelectionDAG &DAG, bool IsRotate) { |
--- |
| 7997 |
const auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
7997 |
const auto &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 7998 |
// If EltSize is a power of 2 then: |
--- |
7998 |
// If EltSize is a power of 2 then: |
--- |
| 7999 |
// |
--- |
7999 |
// |
--- |
| 8000 |
// (a) (Pos == 0 ? 0 : EltSize - Pos) == (EltSize - Pos) & (EltSize - 1) |
--- |
8000 |
// (a) (Pos == 0 ? 0 : EltSize - Pos) == (EltSize - Pos) & (EltSize - 1) |
--- |
| 8001 |
// (b) Neg == Neg & (EltSize - 1) whenever Neg is in [0, EltSize). |
--- |
8001 |
// (b) Neg == Neg & (EltSize - 1) whenever Neg is in [0, EltSize). |
--- |
| 8002 |
// |
--- |
8002 |
// |
--- |
| 8003 |
// So if EltSize is a power of 2 and Neg is (and Neg', EltSize-1), we check |
--- |
8003 |
// So if EltSize is a power of 2 and Neg is (and Neg', EltSize-1), we check |
--- |
| 8004 |
// for the stronger condition: |
--- |
8004 |
// for the stronger condition: |
--- |
| 8005 |
// |
--- |
8005 |
// |
--- |
| 8006 |
// Neg & (EltSize - 1) == (EltSize - Pos) & (EltSize - 1) [A] |
--- |
8006 |
// Neg & (EltSize - 1) == (EltSize - Pos) & (EltSize - 1) [A] |
--- |
| 8007 |
// |
--- |
8007 |
// |
--- |
| 8008 |
// for all Neg and Pos. Since Neg & (EltSize - 1) == Neg' & (EltSize - 1) |
--- |
8008 |
// for all Neg and Pos. Since Neg & (EltSize - 1) == Neg' & (EltSize - 1) |
--- |
| 8009 |
// we can just replace Neg with Neg' for the rest of the function. |
--- |
8009 |
// we can just replace Neg with Neg' for the rest of the function. |
--- |
| 8010 |
// |
--- |
8010 |
// |
--- |
| 8011 |
// In other cases we check for the even stronger condition: |
--- |
8011 |
// In other cases we check for the even stronger condition: |
--- |
| 8012 |
// |
--- |
8012 |
// |
--- |
| 8013 |
// Neg == EltSize - Pos [B] |
--- |
8013 |
// Neg == EltSize - Pos [B] |
--- |
| 8014 |
// |
--- |
8014 |
// |
--- |
| 8015 |
// for all Neg and Pos. Note that the (or ...) then invokes undefined |
--- |
8015 |
// for all Neg and Pos. Note that the (or ...) then invokes undefined |
--- |
| 8016 |
// behavior if Pos == 0 (and consequently Neg == EltSize). |
--- |
8016 |
// behavior if Pos == 0 (and consequently Neg == EltSize). |
--- |
| 8017 |
// |
--- |
8017 |
// |
--- |
| 8018 |
// We could actually use [A] whenever EltSize is a power of 2, but the |
--- |
8018 |
// We could actually use [A] whenever EltSize is a power of 2, but the |
--- |
| 8019 |
// only extra cases that it would match are those uninteresting ones |
--- |
8019 |
// only extra cases that it would match are those uninteresting ones |
--- |
| 8020 |
// where Neg and Pos are never in range at the same time. E.g. for |
--- |
8020 |
// where Neg and Pos are never in range at the same time. E.g. for |
--- |
| 8021 |
// EltSize == 32, using [A] would allow a Neg of the form (sub 64, Pos) |
--- |
8021 |
// EltSize == 32, using [A] would allow a Neg of the form (sub 64, Pos) |
--- |
| 8022 |
// as well as (sub 32, Pos), but: |
--- |
8022 |
// as well as (sub 32, Pos), but: |
--- |
| 8023 |
// |
--- |
8023 |
// |
--- |
| 8024 |
// (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos)) |
--- |
8024 |
// (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos)) |
--- |
| 8025 |
// |
--- |
8025 |
// |
--- |
| 8026 |
// always invokes undefined behavior for 32-bit X. |
--- |
8026 |
// always invokes undefined behavior for 32-bit X. |
--- |
| 8027 |
// |
--- |
8027 |
// |
--- |
| 8028 |
// Below, Mask == EltSize - 1 when using [A] and is all-ones otherwise. |
--- |
8028 |
// Below, Mask == EltSize - 1 when using [A] and is all-ones otherwise. |
--- |
| 8029 |
// This allows us to peek through any operations that only affect Mask's |
--- |
8029 |
// This allows us to peek through any operations that only affect Mask's |
--- |
| 8030 |
// un-demanded bits. |
--- |
8030 |
// un-demanded bits. |
--- |
| 8031 |
// |
--- |
8031 |
// |
--- |
| 8032 |
// NOTE: We can only do this when matching operations which won't modify the |
--- |
8032 |
// NOTE: We can only do this when matching operations which won't modify the |
--- |
| 8033 |
// least Log2(EltSize) significant bits and not a general funnel shift. |
--- |
8033 |
// least Log2(EltSize) significant bits and not a general funnel shift. |
--- |
| 8034 |
unsigned MaskLoBits = 0; |
0 |
8034 |
unsigned MaskLoBits = 0; |
0 |
| 8035 |
if (IsRotate && isPowerOf2_64(EltSize)) { |
0 |
8035 |
if (IsRotate && isPowerOf2_64(EltSize)) { |
0 |
| 8036 |
unsigned Bits = Log2_64(EltSize); |
0 |
8036 |
unsigned Bits = Log2_64(EltSize); |
0 |
| 8037 |
unsigned NegBits = Neg.getScalarValueSizeInBits(); |
0 |
8037 |
unsigned NegBits = Neg.getScalarValueSizeInBits(); |
0 |
| 8038 |
if (NegBits >= Bits) { |
0 |
8038 |
if (NegBits >= Bits) { |
0 |
| 8039 |
APInt DemandedBits = APInt::getLowBitsSet(NegBits, Bits); |
0 |
8039 |
APInt DemandedBits = APInt::getLowBitsSet(NegBits, Bits); |
0 |
| 8040 |
if (SDValue Inner = |
0 |
8040 |
if (SDValue Inner = |
0 |
| 8041 |
TLI.SimplifyMultipleUseDemandedBits(Neg, DemandedBits, DAG)) { |
0 |
8041 |
TLI.SimplifyMultipleUseDemandedBits(Neg, DemandedBits, DAG)) { |
0 |
| 8042 |
Neg = Inner; |
0 |
8042 |
Neg = Inner; |
0 |
| 8043 |
MaskLoBits = Bits; |
0 |
8043 |
MaskLoBits = Bits; |
0 |
| 8044 |
} |
--- |
8044 |
} |
--- |
| 8045 |
} |
0 |
8045 |
} |
0 |
| 8046 |
} |
--- |
8046 |
} |
--- |
| 8047 |
|
--- |
8047 |
|
--- |
| 8048 |
// Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1. |
--- |
8048 |
// Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1. |
--- |
| 8049 |
if (Neg.getOpcode() != ISD::SUB) |
0 |
8049 |
if (Neg.getOpcode() != ISD::SUB) |
0 |
| 8050 |
return false; |
0 |
8050 |
return false; |
0 |
| 8051 |
ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(0)); |
0 |
8051 |
ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(0)); |
0 |
| 8052 |
if (!NegC) |
0 |
8052 |
if (!NegC) |
0 |
| 8053 |
return false; |
0 |
8053 |
return false; |
0 |
| 8054 |
SDValue NegOp1 = Neg.getOperand(1); |
0 |
8054 |
SDValue NegOp1 = Neg.getOperand(1); |
0 |
| 8055 |
|
--- |
8055 |
|
--- |
| 8056 |
// On the RHS of [A], if Pos is the result of operation on Pos' that won't |
--- |
8056 |
// On the RHS of [A], if Pos is the result of operation on Pos' that won't |
--- |
| 8057 |
// affect Mask's demanded bits, just replace Pos with Pos'. These operations |
--- |
8057 |
// affect Mask's demanded bits, just replace Pos with Pos'. These operations |
--- |
| 8058 |
// are redundant for the purpose of the equality. |
--- |
8058 |
// are redundant for the purpose of the equality. |
--- |
| 8059 |
if (MaskLoBits) { |
0 |
8059 |
if (MaskLoBits) { |
0 |
| 8060 |
unsigned PosBits = Pos.getScalarValueSizeInBits(); |
0 |
8060 |
unsigned PosBits = Pos.getScalarValueSizeInBits(); |
0 |
| 8061 |
if (PosBits >= MaskLoBits) { |
0 |
8061 |
if (PosBits >= MaskLoBits) { |
0 |
| 8062 |
APInt DemandedBits = APInt::getLowBitsSet(PosBits, MaskLoBits); |
0 |
8062 |
APInt DemandedBits = APInt::getLowBitsSet(PosBits, MaskLoBits); |
0 |
| 8063 |
if (SDValue Inner = |
0 |
8063 |
if (SDValue Inner = |
0 |
| 8064 |
TLI.SimplifyMultipleUseDemandedBits(Pos, DemandedBits, DAG)) { |
0 |
8064 |
TLI.SimplifyMultipleUseDemandedBits(Pos, DemandedBits, DAG)) { |
0 |
| 8065 |
Pos = Inner; |
0 |
8065 |
Pos = Inner; |
0 |
| 8066 |
} |
--- |
8066 |
} |
--- |
| 8067 |
} |
0 |
8067 |
} |
0 |
| 8068 |
} |
--- |
8068 |
} |
--- |
| 8069 |
|
--- |
8069 |
|
--- |
| 8070 |
// The condition we need is now: |
--- |
8070 |
// The condition we need is now: |
--- |
| 8071 |
// |
--- |
8071 |
// |
--- |
| 8072 |
// (NegC - NegOp1) & Mask == (EltSize - Pos) & Mask |
--- |
8072 |
// (NegC - NegOp1) & Mask == (EltSize - Pos) & Mask |
--- |
| 8073 |
// |
--- |
8073 |
// |
--- |
| 8074 |
// If NegOp1 == Pos then we need: |
--- |
8074 |
// If NegOp1 == Pos then we need: |
--- |
| 8075 |
// |
--- |
8075 |
// |
--- |
| 8076 |
// EltSize & Mask == NegC & Mask |
--- |
8076 |
// EltSize & Mask == NegC & Mask |
--- |
| 8077 |
// |
--- |
8077 |
// |
--- |
| 8078 |
// (because "x & Mask" is a truncation and distributes through subtraction). |
--- |
8078 |
// (because "x & Mask" is a truncation and distributes through subtraction). |
--- |
| 8079 |
// |
--- |
8079 |
// |
--- |
| 8080 |
// We also need to account for a potential truncation of NegOp1 if the amount |
--- |
8080 |
// We also need to account for a potential truncation of NegOp1 if the amount |
--- |
| 8081 |
// has already been legalized to a shift amount type. |
--- |
8081 |
// has already been legalized to a shift amount type. |
--- |
| 8082 |
APInt Width; |
0 |
8082 |
APInt Width; |
0 |
| 8083 |
if ((Pos == NegOp1) || |
0 |
8083 |
if ((Pos == NegOp1) || |
0 |
| 8084 |
(NegOp1.getOpcode() == ISD::TRUNCATE && Pos == NegOp1.getOperand(0))) |
0 |
8084 |
(NegOp1.getOpcode() == ISD::TRUNCATE && Pos == NegOp1.getOperand(0))) |
0 |
| 8085 |
Width = NegC->getAPIntValue(); |
0 |
8085 |
Width = NegC->getAPIntValue(); |
0 |
| 8086 |
|
--- |
8086 |
|
--- |
| 8087 |
// Check for cases where Pos has the form (add NegOp1, PosC) for some PosC. |
--- |
8087 |
// Check for cases where Pos has the form (add NegOp1, PosC) for some PosC. |
--- |
| 8088 |
// Then the condition we want to prove becomes: |
--- |
8088 |
// Then the condition we want to prove becomes: |
--- |
| 8089 |
// |
--- |
8089 |
// |
--- |
| 8090 |
// (NegC - NegOp1) & Mask == (EltSize - (NegOp1 + PosC)) & Mask |
--- |
8090 |
// (NegC - NegOp1) & Mask == (EltSize - (NegOp1 + PosC)) & Mask |
--- |
| 8091 |
// |
--- |
8091 |
// |
--- |
| 8092 |
// which, again because "x & Mask" is a truncation, becomes: |
--- |
8092 |
// which, again because "x & Mask" is a truncation, becomes: |
--- |
| 8093 |
// |
--- |
8093 |
// |
--- |
| 8094 |
// NegC & Mask == (EltSize - PosC) & Mask |
--- |
8094 |
// NegC & Mask == (EltSize - PosC) & Mask |
--- |
| 8095 |
// EltSize & Mask == (NegC + PosC) & Mask |
--- |
8095 |
// EltSize & Mask == (NegC + PosC) & Mask |
--- |
| 8096 |
else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) { |
0 |
8096 |
else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) { |
0 |
| 8097 |
if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1))) |
0 |
8097 |
if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1))) |
0 |
| 8098 |
Width = PosC->getAPIntValue() + NegC->getAPIntValue(); |
0 |
8098 |
Width = PosC->getAPIntValue() + NegC->getAPIntValue(); |
0 |
| 8099 |
else |
--- |
8099 |
else |
--- |
| 8100 |
return false; |
0 |
8100 |
return false; |
0 |
| 8101 |
} else |
--- |
8101 |
} else |
--- |
| 8102 |
return false; |
0 |
8102 |
return false; |
0 |
| 8103 |
|
--- |
8103 |
|
--- |
| 8104 |
// Now we just need to check that EltSize & Mask == Width & Mask. |
--- |
8104 |
// Now we just need to check that EltSize & Mask == Width & Mask. |
--- |
| 8105 |
if (MaskLoBits) |
0 |
8105 |
if (MaskLoBits) |
0 |
| 8106 |
// EltSize & Mask is 0 since Mask is EltSize - 1. |
--- |
8106 |
// EltSize & Mask is 0 since Mask is EltSize - 1. |
--- |
| 8107 |
return Width.getLoBits(MaskLoBits) == 0; |
0 |
8107 |
return Width.getLoBits(MaskLoBits) == 0; |
0 |
| 8108 |
return Width == EltSize; |
0 |
8108 |
return Width == EltSize; |
0 |
| 8109 |
} |
0 |
8109 |
} |
0 |
| 8110 |
|
--- |
8110 |
|
--- |
| 8111 |
// A subroutine of MatchRotate used once we have found an OR of two opposite |
--- |
8111 |
// A subroutine of MatchRotate used once we have found an OR of two opposite |
--- |
| 8112 |
// shifts of Shifted. If Neg == - Pos then the OR reduces |
--- |
8112 |
// shifts of Shifted. If Neg == - Pos then the OR reduces |
--- |
| 8113 |
// to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the |
--- |
8113 |
// to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the |
--- |
| 8114 |
// former being preferred if supported. InnerPos and InnerNeg are Pos and |
--- |
8114 |
// former being preferred if supported. InnerPos and InnerNeg are Pos and |
--- |
| 8115 |
// Neg with outer conversions stripped away. |
--- |
8115 |
// Neg with outer conversions stripped away. |
--- |
| 8116 |
SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos, |
0 |
8116 |
SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos, |
0 |
| 8117 |
SDValue Neg, SDValue InnerPos, |
--- |
8117 |
SDValue Neg, SDValue InnerPos, |
--- |
| 8118 |
SDValue InnerNeg, bool HasPos, |
--- |
8118 |
SDValue InnerNeg, bool HasPos, |
--- |
| 8119 |
unsigned PosOpcode, unsigned NegOpcode, |
--- |
8119 |
unsigned PosOpcode, unsigned NegOpcode, |
--- |
| 8120 |
const SDLoc &DL) { |
--- |
8120 |
const SDLoc &DL) { |
--- |
| 8121 |
// fold (or (shl x, (*ext y)), |
--- |
8121 |
// fold (or (shl x, (*ext y)), |
--- |
| 8122 |
// (srl x, (*ext (sub 32, y)))) -> |
--- |
8122 |
// (srl x, (*ext (sub 32, y)))) -> |
--- |
| 8123 |
// (rotl x, y) or (rotr x, (sub 32, y)) |
--- |
8123 |
// (rotl x, y) or (rotr x, (sub 32, y)) |
--- |
| 8124 |
// |
--- |
8124 |
// |
--- |
| 8125 |
// fold (or (shl x, (*ext (sub 32, y))), |
--- |
8125 |
// fold (or (shl x, (*ext (sub 32, y))), |
--- |
| 8126 |
// (srl x, (*ext y))) -> |
--- |
8126 |
// (srl x, (*ext y))) -> |
--- |
| 8127 |
// (rotr x, y) or (rotl x, (sub 32, y)) |
--- |
8127 |
// (rotr x, y) or (rotl x, (sub 32, y)) |
--- |
| 8128 |
EVT VT = Shifted.getValueType(); |
0 |
8128 |
EVT VT = Shifted.getValueType(); |
0 |
| 8129 |
if (matchRotateSub(InnerPos, InnerNeg, VT.getScalarSizeInBits(), DAG, |
0 |
8129 |
if (matchRotateSub(InnerPos, InnerNeg, VT.getScalarSizeInBits(), DAG, |
0 |
| 8130 |
/*IsRotate*/ true)) { |
--- |
8130 |
/*IsRotate*/ true)) { |
--- |
| 8131 |
return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted, |
0 |
8131 |
return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted, |
0 |
| 8132 |
HasPos ? Pos : Neg); |
0 |
8132 |
HasPos ? Pos : Neg); |
0 |
| 8133 |
} |
--- |
8133 |
} |
--- |
| 8134 |
|
--- |
8134 |
|
--- |
| 8135 |
return SDValue(); |
0 |
8135 |
return SDValue(); |
0 |
| 8136 |
} |
--- |
8136 |
} |
--- |
| 8137 |
|
--- |
8137 |
|
--- |
| 8138 |
// A subroutine of MatchRotate used once we have found an OR of two opposite |
--- |
8138 |
// A subroutine of MatchRotate used once we have found an OR of two opposite |
--- |
| 8139 |
// shifts of N0 + N1. If Neg == - Pos then the OR reduces |
--- |
8139 |
// shifts of N0 + N1. If Neg == - Pos then the OR reduces |
--- |
| 8140 |
// to both (PosOpcode N0, N1, Pos) and (NegOpcode N0, N1, Neg), with the |
--- |
8140 |
// to both (PosOpcode N0, N1, Pos) and (NegOpcode N0, N1, Neg), with the |
--- |
| 8141 |
// former being preferred if supported. InnerPos and InnerNeg are Pos and |
--- |
8141 |
// former being preferred if supported. InnerPos and InnerNeg are Pos and |
--- |
| 8142 |
// Neg with outer conversions stripped away. |
--- |
8142 |
// Neg with outer conversions stripped away. |
--- |
| 8143 |
// TODO: Merge with MatchRotatePosNeg. |
--- |
8143 |
// TODO: Merge with MatchRotatePosNeg. |
--- |
| 8144 |
SDValue DAGCombiner::MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos, |
0 |
8144 |
SDValue DAGCombiner::MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos, |
0 |
| 8145 |
SDValue Neg, SDValue InnerPos, |
--- |
8145 |
SDValue Neg, SDValue InnerPos, |
--- |
| 8146 |
SDValue InnerNeg, bool HasPos, |
--- |
8146 |
SDValue InnerNeg, bool HasPos, |
--- |
| 8147 |
unsigned PosOpcode, unsigned NegOpcode, |
--- |
8147 |
unsigned PosOpcode, unsigned NegOpcode, |
--- |
| 8148 |
const SDLoc &DL) { |
--- |
8148 |
const SDLoc &DL) { |
--- |
| 8149 |
EVT VT = N0.getValueType(); |
0 |
8149 |
EVT VT = N0.getValueType(); |
0 |
| 8150 |
unsigned EltBits = VT.getScalarSizeInBits(); |
0 |
8150 |
unsigned EltBits = VT.getScalarSizeInBits(); |
0 |
| 8151 |
|
--- |
8151 |
|
--- |
| 8152 |
// fold (or (shl x0, (*ext y)), |
--- |
8152 |
// fold (or (shl x0, (*ext y)), |
--- |
| 8153 |
// (srl x1, (*ext (sub 32, y)))) -> |
--- |
8153 |
// (srl x1, (*ext (sub 32, y)))) -> |
--- |
| 8154 |
// (fshl x0, x1, y) or (fshr x0, x1, (sub 32, y)) |
--- |
8154 |
// (fshl x0, x1, y) or (fshr x0, x1, (sub 32, y)) |
--- |
| 8155 |
// |
--- |
8155 |
// |
--- |
| 8156 |
// fold (or (shl x0, (*ext (sub 32, y))), |
--- |
8156 |
// fold (or (shl x0, (*ext (sub 32, y))), |
--- |
| 8157 |
// (srl x1, (*ext y))) -> |
--- |
8157 |
// (srl x1, (*ext y))) -> |
--- |
| 8158 |
// (fshr x0, x1, y) or (fshl x0, x1, (sub 32, y)) |
--- |
8158 |
// (fshr x0, x1, y) or (fshl x0, x1, (sub 32, y)) |
--- |
| 8159 |
if (matchRotateSub(InnerPos, InnerNeg, EltBits, DAG, /*IsRotate*/ N0 == N1)) { |
0 |
8159 |
if (matchRotateSub(InnerPos, InnerNeg, EltBits, DAG, /*IsRotate*/ N0 == N1)) { |
0 |
| 8160 |
return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, N0, N1, |
0 |
8160 |
return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, N0, N1, |
0 |
| 8161 |
HasPos ? Pos : Neg); |
0 |
8161 |
HasPos ? Pos : Neg); |
0 |
| 8162 |
} |
--- |
8162 |
} |
--- |
| 8163 |
|
--- |
8163 |
|
--- |
| 8164 |
// Matching the shift+xor cases, we can't easily use the xor'd shift amount |
--- |
8164 |
// Matching the shift+xor cases, we can't easily use the xor'd shift amount |
--- |
| 8165 |
// so for now just use the PosOpcode case if its legal. |
--- |
8165 |
// so for now just use the PosOpcode case if its legal. |
--- |
| 8166 |
// TODO: When can we use the NegOpcode case? |
--- |
8166 |
// TODO: When can we use the NegOpcode case? |
--- |
| 8167 |
if (PosOpcode == ISD::FSHL && isPowerOf2_32(EltBits)) { |
0 |
8167 |
if (PosOpcode == ISD::FSHL && isPowerOf2_32(EltBits)) { |
0 |
| 8168 |
auto IsBinOpImm = [](SDValue Op, unsigned BinOpc, unsigned Imm) { |
0 |
8168 |
auto IsBinOpImm = [](SDValue Op, unsigned BinOpc, unsigned Imm) { |
0 |
| 8169 |
if (Op.getOpcode() != BinOpc) |
0 |
8169 |
if (Op.getOpcode() != BinOpc) |
0 |
| 8170 |
return false; |
0 |
8170 |
return false; |
0 |
| 8171 |
ConstantSDNode *Cst = isConstOrConstSplat(Op.getOperand(1)); |
0 |
8171 |
ConstantSDNode *Cst = isConstOrConstSplat(Op.getOperand(1)); |
0 |
| 8172 |
return Cst && (Cst->getAPIntValue() == Imm); |
0 |
8172 |
return Cst && (Cst->getAPIntValue() == Imm); |
0 |
| 8173 |
}; |
--- |
8173 |
}; |
--- |
| 8174 |
|
--- |
8174 |
|
--- |
| 8175 |
// fold (or (shl x0, y), (srl (srl x1, 1), (xor y, 31))) |
--- |
8175 |
// fold (or (shl x0, y), (srl (srl x1, 1), (xor y, 31))) |
--- |
| 8176 |
// -> (fshl x0, x1, y) |
--- |
8176 |
// -> (fshl x0, x1, y) |
--- |
| 8177 |
if (IsBinOpImm(N1, ISD::SRL, 1) && |
0 |
8177 |
if (IsBinOpImm(N1, ISD::SRL, 1) && |
0 |
| 8178 |
IsBinOpImm(InnerNeg, ISD::XOR, EltBits - 1) && |
0 |
8178 |
IsBinOpImm(InnerNeg, ISD::XOR, EltBits - 1) && |
0 |
| 8179 |
InnerPos == InnerNeg.getOperand(0) && |
0 |
8179 |
InnerPos == InnerNeg.getOperand(0) && |
0 |
| 8180 |
TLI.isOperationLegalOrCustom(ISD::FSHL, VT)) { |
0 |
8180 |
TLI.isOperationLegalOrCustom(ISD::FSHL, VT)) { |
0 |
| 8181 |
return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos); |
0 |
8181 |
return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos); |
0 |
| 8182 |
} |
--- |
8182 |
} |
--- |
| 8183 |
|
--- |
8183 |
|
--- |
| 8184 |
// fold (or (shl (shl x0, 1), (xor y, 31)), (srl x1, y)) |
--- |
8184 |
// fold (or (shl (shl x0, 1), (xor y, 31)), (srl x1, y)) |
--- |
| 8185 |
// -> (fshr x0, x1, y) |
--- |
8185 |
// -> (fshr x0, x1, y) |
--- |
| 8186 |
if (IsBinOpImm(N0, ISD::SHL, 1) && |
0 |
8186 |
if (IsBinOpImm(N0, ISD::SHL, 1) && |
0 |
| 8187 |
IsBinOpImm(InnerPos, ISD::XOR, EltBits - 1) && |
0 |
8187 |
IsBinOpImm(InnerPos, ISD::XOR, EltBits - 1) && |
0 |
| 8188 |
InnerNeg == InnerPos.getOperand(0) && |
0 |
8188 |
InnerNeg == InnerPos.getOperand(0) && |
0 |
| 8189 |
TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { |
0 |
8189 |
TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { |
0 |
| 8190 |
return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); |
0 |
8190 |
return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); |
0 |
| 8191 |
} |
--- |
8191 |
} |
--- |
| 8192 |
|
--- |
8192 |
|
--- |
| 8193 |
// fold (or (shl (add x0, x0), (xor y, 31)), (srl x1, y)) |
--- |
8193 |
// fold (or (shl (add x0, x0), (xor y, 31)), (srl x1, y)) |
--- |
| 8194 |
// -> (fshr x0, x1, y) |
--- |
8194 |
// -> (fshr x0, x1, y) |
--- |
| 8195 |
// TODO: Should add(x,x) -> shl(x,1) be a general DAG canonicalization? |
--- |
8195 |
// TODO: Should add(x,x) -> shl(x,1) be a general DAG canonicalization? |
--- |
| 8196 |
if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N0.getOperand(1) && |
0 |
8196 |
if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N0.getOperand(1) && |
0 |
| 8197 |
IsBinOpImm(InnerPos, ISD::XOR, EltBits - 1) && |
0 |
8197 |
IsBinOpImm(InnerPos, ISD::XOR, EltBits - 1) && |
0 |
| 8198 |
InnerNeg == InnerPos.getOperand(0) && |
0 |
8198 |
InnerNeg == InnerPos.getOperand(0) && |
0 |
| 8199 |
TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { |
0 |
8199 |
TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { |
0 |
| 8200 |
return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); |
0 |
8200 |
return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); |
0 |
| 8201 |
} |
--- |
8201 |
} |
--- |
| 8202 |
} |
--- |
8202 |
} |
--- |
| 8203 |
|
--- |
8203 |
|
--- |
| 8204 |
return SDValue(); |
0 |
8204 |
return SDValue(); |
0 |
| 8205 |
} |
--- |
8205 |
} |
--- |
| 8206 |
|
--- |
8206 |
|
--- |
| 8207 |
// MatchRotate - Handle an 'or' of two operands. If this is one of the many |
--- |
8207 |
// MatchRotate - Handle an 'or' of two operands. If this is one of the many |
--- |
| 8208 |
// idioms for rotate, and if the target supports rotation instructions, generate |
--- |
8208 |
// idioms for rotate, and if the target supports rotation instructions, generate |
--- |
| 8209 |
// a rot[lr]. This also matches funnel shift patterns, similar to rotation but |
--- |
8209 |
// a rot[lr]. This also matches funnel shift patterns, similar to rotation but |
--- |
| 8210 |
// with different shifted sources. |
--- |
8210 |
// with different shifted sources. |
--- |
| 8211 |
SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) { |
0 |
8211 |
SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) { |
0 |
| 8212 |
EVT VT = LHS.getValueType(); |
0 |
8212 |
EVT VT = LHS.getValueType(); |
0 |
| 8213 |
|
--- |
8213 |
|
--- |
| 8214 |
// The target must have at least one rotate/funnel flavor. |
--- |
8214 |
// The target must have at least one rotate/funnel flavor. |
--- |
| 8215 |
// We still try to match rotate by constant pre-legalization. |
--- |
8215 |
// We still try to match rotate by constant pre-legalization. |
--- |
| 8216 |
// TODO: Support pre-legalization funnel-shift by constant. |
--- |
8216 |
// TODO: Support pre-legalization funnel-shift by constant. |
--- |
| 8217 |
bool HasROTL = hasOperation(ISD::ROTL, VT); |
0 |
8217 |
bool HasROTL = hasOperation(ISD::ROTL, VT); |
0 |
| 8218 |
bool HasROTR = hasOperation(ISD::ROTR, VT); |
0 |
8218 |
bool HasROTR = hasOperation(ISD::ROTR, VT); |
0 |
| 8219 |
bool HasFSHL = hasOperation(ISD::FSHL, VT); |
0 |
8219 |
bool HasFSHL = hasOperation(ISD::FSHL, VT); |
0 |
| 8220 |
bool HasFSHR = hasOperation(ISD::FSHR, VT); |
0 |
8220 |
bool HasFSHR = hasOperation(ISD::FSHR, VT); |
0 |
| 8221 |
|
--- |
8221 |
|
--- |
| 8222 |
// If the type is going to be promoted and the target has enabled custom |
--- |
8222 |
// If the type is going to be promoted and the target has enabled custom |
--- |
| 8223 |
// lowering for rotate, allow matching rotate by non-constants. Only allow |
--- |
8223 |
// lowering for rotate, allow matching rotate by non-constants. Only allow |
--- |
| 8224 |
// this for scalar types. |
--- |
8224 |
// this for scalar types. |
--- |
| 8225 |
if (VT.isScalarInteger() && TLI.getTypeAction(*DAG.getContext(), VT) == |
0 |
8225 |
if (VT.isScalarInteger() && TLI.getTypeAction(*DAG.getContext(), VT) == |
0 |
| 8226 |
TargetLowering::TypePromoteInteger) { |
--- |
8226 |
TargetLowering::TypePromoteInteger) { |
--- |
| 8227 |
HasROTL |= TLI.getOperationAction(ISD::ROTL, VT) == TargetLowering::Custom; |
0 |
8227 |
HasROTL |= TLI.getOperationAction(ISD::ROTL, VT) == TargetLowering::Custom; |
0 |
| 8228 |
HasROTR |= TLI.getOperationAction(ISD::ROTR, VT) == TargetLowering::Custom; |
0 |
8228 |
HasROTR |= TLI.getOperationAction(ISD::ROTR, VT) == TargetLowering::Custom; |
0 |
| 8229 |
} |
--- |
8229 |
} |
--- |
| 8230 |
|
--- |
8230 |
|
--- |
| 8231 |
if (LegalOperations && !HasROTL && !HasROTR && !HasFSHL && !HasFSHR) |
0 |
8231 |
if (LegalOperations && !HasROTL && !HasROTR && !HasFSHL && !HasFSHR) |
0 |
| 8232 |
return SDValue(); |
0 |
8232 |
return SDValue(); |
0 |
| 8233 |
|
--- |
8233 |
|
--- |
| 8234 |
// Check for truncated rotate. |
--- |
8234 |
// Check for truncated rotate. |
--- |
| 8235 |
if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE && |
0 |
8235 |
if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE && |
0 |
| 8236 |
LHS.getOperand(0).getValueType() == RHS.getOperand(0).getValueType()) { |
0 |
8236 |
LHS.getOperand(0).getValueType() == RHS.getOperand(0).getValueType()) { |
0 |
| 8237 |
assert(LHS.getValueType() == RHS.getValueType()); |
0 |
8237 |
assert(LHS.getValueType() == RHS.getValueType()); |
0 |
| 8238 |
if (SDValue Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) { |
0 |
8238 |
if (SDValue Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) { |
0 |
| 8239 |
return DAG.getNode(ISD::TRUNCATE, SDLoc(LHS), LHS.getValueType(), Rot); |
0 |
8239 |
return DAG.getNode(ISD::TRUNCATE, SDLoc(LHS), LHS.getValueType(), Rot); |
0 |
| 8240 |
} |
--- |
8240 |
} |
--- |
| 8241 |
} |
--- |
8241 |
} |
--- |
| 8242 |
|
--- |
8242 |
|
--- |
| 8243 |
// Match "(X shl/srl V1) & V2" where V2 may not be present. |
--- |
8243 |
// Match "(X shl/srl V1) & V2" where V2 may not be present. |
--- |
| 8244 |
SDValue LHSShift; // The shift. |
0 |
8244 |
SDValue LHSShift; // The shift. |
0 |
| 8245 |
SDValue LHSMask; // AND value if any. |
0 |
8245 |
SDValue LHSMask; // AND value if any. |
0 |
| 8246 |
matchRotateHalf(DAG, LHS, LHSShift, LHSMask); |
0 |
8246 |
matchRotateHalf(DAG, LHS, LHSShift, LHSMask); |
0 |
| 8247 |
|
--- |
8247 |
|
--- |
| 8248 |
SDValue RHSShift; // The shift. |
0 |
8248 |
SDValue RHSShift; // The shift. |
0 |
| 8249 |
SDValue RHSMask; // AND value if any. |
0 |
8249 |
SDValue RHSMask; // AND value if any. |
0 |
| 8250 |
matchRotateHalf(DAG, RHS, RHSShift, RHSMask); |
0 |
8250 |
matchRotateHalf(DAG, RHS, RHSShift, RHSMask); |
0 |
| 8251 |
|
--- |
8251 |
|
--- |
| 8252 |
// If neither side matched a rotate half, bail |
--- |
8252 |
// If neither side matched a rotate half, bail |
--- |
| 8253 |
if (!LHSShift && !RHSShift) |
0 |
8253 |
if (!LHSShift && !RHSShift) |
0 |
| 8254 |
return SDValue(); |
0 |
8254 |
return SDValue(); |
0 |
| 8255 |
|
--- |
8255 |
|
--- |
| 8256 |
// InstCombine may have combined a constant shl, srl, mul, or udiv with one |
--- |
8256 |
// InstCombine may have combined a constant shl, srl, mul, or udiv with one |
--- |
| 8257 |
// side of the rotate, so try to handle that here. In all cases we need to |
--- |
8257 |
// side of the rotate, so try to handle that here. In all cases we need to |
--- |
| 8258 |
// pass the matched shift from the opposite side to compute the opcode and |
--- |
8258 |
// pass the matched shift from the opposite side to compute the opcode and |
--- |
| 8259 |
// needed shift amount to extract. We still want to do this if both sides |
--- |
8259 |
// needed shift amount to extract. We still want to do this if both sides |
--- |
| 8260 |
// matched a rotate half because one half may be a potential overshift that |
--- |
8260 |
// matched a rotate half because one half may be a potential overshift that |
--- |
| 8261 |
// can be broken down (ie if InstCombine merged two shl or srl ops into a |
--- |
8261 |
// can be broken down (ie if InstCombine merged two shl or srl ops into a |
--- |
| 8262 |
// single one). |
--- |
8262 |
// single one). |
--- |
| 8263 |
|
--- |
8263 |
|
--- |
| 8264 |
// Have LHS side of the rotate, try to extract the needed shift from the RHS. |
--- |
8264 |
// Have LHS side of the rotate, try to extract the needed shift from the RHS. |
--- |
| 8265 |
if (LHSShift) |
0 |
8265 |
if (LHSShift) |
0 |
| 8266 |
if (SDValue NewRHSShift = |
0 |
8266 |
if (SDValue NewRHSShift = |
0 |
| 8267 |
extractShiftForRotate(DAG, LHSShift, RHS, RHSMask, DL)) |
0 |
8267 |
extractShiftForRotate(DAG, LHSShift, RHS, RHSMask, DL)) |
0 |
| 8268 |
RHSShift = NewRHSShift; |
0 |
8268 |
RHSShift = NewRHSShift; |
0 |
| 8269 |
// Have RHS side of the rotate, try to extract the needed shift from the LHS. |
--- |
8269 |
// Have RHS side of the rotate, try to extract the needed shift from the LHS. |
--- |
| 8270 |
if (RHSShift) |
0 |
8270 |
if (RHSShift) |
0 |
| 8271 |
if (SDValue NewLHSShift = |
0 |
8271 |
if (SDValue NewLHSShift = |
0 |
| 8272 |
extractShiftForRotate(DAG, RHSShift, LHS, LHSMask, DL)) |
0 |
8272 |
extractShiftForRotate(DAG, RHSShift, LHS, LHSMask, DL)) |
0 |
| 8273 |
LHSShift = NewLHSShift; |
0 |
8273 |
LHSShift = NewLHSShift; |
0 |
| 8274 |
|
--- |
8274 |
|
--- |
| 8275 |
// If a side is still missing, nothing else we can do. |
--- |
8275 |
// If a side is still missing, nothing else we can do. |
--- |
| 8276 |
if (!RHSShift || !LHSShift) |
0 |
8276 |
if (!RHSShift || !LHSShift) |
0 |
| 8277 |
return SDValue(); |
0 |
8277 |
return SDValue(); |
0 |
| 8278 |
|
--- |
8278 |
|
--- |
| 8279 |
// At this point we've matched or extracted a shift op on each side. |
--- |
8279 |
// At this point we've matched or extracted a shift op on each side. |
--- |
| 8280 |
|
--- |
8280 |
|
--- |
| 8281 |
if (LHSShift.getOpcode() == RHSShift.getOpcode()) |
0 |
8281 |
if (LHSShift.getOpcode() == RHSShift.getOpcode()) |
0 |
| 8282 |
return SDValue(); // Shifts must disagree. |
0 |
8282 |
return SDValue(); // Shifts must disagree. |
0 |
| 8283 |
|
--- |
8283 |
|
--- |
| 8284 |
// Canonicalize shl to left side in a shl/srl pair. |
--- |
8284 |
// Canonicalize shl to left side in a shl/srl pair. |
--- |
| 8285 |
if (RHSShift.getOpcode() == ISD::SHL) { |
0 |
8285 |
if (RHSShift.getOpcode() == ISD::SHL) { |
0 |
| 8286 |
std::swap(LHS, RHS); |
0 |
8286 |
std::swap(LHS, RHS); |
0 |
| 8287 |
std::swap(LHSShift, RHSShift); |
0 |
8287 |
std::swap(LHSShift, RHSShift); |
0 |
| 8288 |
std::swap(LHSMask, RHSMask); |
0 |
8288 |
std::swap(LHSMask, RHSMask); |
0 |
| 8289 |
} |
--- |
8289 |
} |
--- |
| 8290 |
|
--- |
8290 |
|
--- |
| 8291 |
// Something has gone wrong - we've lost the shl/srl pair - bail. |
--- |
8291 |
// Something has gone wrong - we've lost the shl/srl pair - bail. |
--- |
| 8292 |
if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL) |
0 |
8292 |
if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL) |
0 |
| 8293 |
return SDValue(); |
0 |
8293 |
return SDValue(); |
0 |
| 8294 |
|
--- |
8294 |
|
--- |
| 8295 |
unsigned EltSizeInBits = VT.getScalarSizeInBits(); |
0 |
8295 |
unsigned EltSizeInBits = VT.getScalarSizeInBits(); |
0 |
| 8296 |
SDValue LHSShiftArg = LHSShift.getOperand(0); |
0 |
8296 |
SDValue LHSShiftArg = LHSShift.getOperand(0); |
0 |
| 8297 |
SDValue LHSShiftAmt = LHSShift.getOperand(1); |
0 |
8297 |
SDValue LHSShiftAmt = LHSShift.getOperand(1); |
0 |
| 8298 |
SDValue RHSShiftArg = RHSShift.getOperand(0); |
0 |
8298 |
SDValue RHSShiftArg = RHSShift.getOperand(0); |
0 |
| 8299 |
SDValue RHSShiftAmt = RHSShift.getOperand(1); |
0 |
8299 |
SDValue RHSShiftAmt = RHSShift.getOperand(1); |
0 |
| 8300 |
|
--- |
8300 |
|
--- |
| 8301 |
auto MatchRotateSum = [EltSizeInBits](ConstantSDNode *LHS, |
0 |
8301 |
auto MatchRotateSum = [EltSizeInBits](ConstantSDNode *LHS, |
0 |
| 8302 |
ConstantSDNode *RHS) { |
0 |
8302 |
ConstantSDNode *RHS) { |
0 |
| 8303 |
return (LHS->getAPIntValue() + RHS->getAPIntValue()) == EltSizeInBits; |
0 |
8303 |
return (LHS->getAPIntValue() + RHS->getAPIntValue()) == EltSizeInBits; |
0 |
| 8304 |
}; |
0 |
8304 |
}; |
0 |
| 8305 |
|
--- |
8305 |
|
--- |
| 8306 |
auto ApplyMasks = [&](SDValue Res) { |
0 |
8306 |
auto ApplyMasks = [&](SDValue Res) { |
0 |
| 8307 |
// If there is an AND of either shifted operand, apply it to the result. |
--- |
8307 |
// If there is an AND of either shifted operand, apply it to the result. |
--- |
| 8308 |
if (LHSMask.getNode() || RHSMask.getNode()) { |
0 |
8308 |
if (LHSMask.getNode() || RHSMask.getNode()) { |
0 |
| 8309 |
SDValue AllOnes = DAG.getAllOnesConstant(DL, VT); |
0 |
8309 |
SDValue AllOnes = DAG.getAllOnesConstant(DL, VT); |
0 |
| 8310 |
SDValue Mask = AllOnes; |
0 |
8310 |
SDValue Mask = AllOnes; |
0 |
| 8311 |
|
--- |
8311 |
|
--- |
| 8312 |
if (LHSMask.getNode()) { |
0 |
8312 |
if (LHSMask.getNode()) { |
0 |
| 8313 |
SDValue RHSBits = DAG.getNode(ISD::SRL, DL, VT, AllOnes, RHSShiftAmt); |
0 |
8313 |
SDValue RHSBits = DAG.getNode(ISD::SRL, DL, VT, AllOnes, RHSShiftAmt); |
0 |
| 8314 |
Mask = DAG.getNode(ISD::AND, DL, VT, Mask, |
0 |
8314 |
Mask = DAG.getNode(ISD::AND, DL, VT, Mask, |
0 |
| 8315 |
DAG.getNode(ISD::OR, DL, VT, LHSMask, RHSBits)); |
0 |
8315 |
DAG.getNode(ISD::OR, DL, VT, LHSMask, RHSBits)); |
0 |
| 8316 |
} |
--- |
8316 |
} |
--- |
| 8317 |
if (RHSMask.getNode()) { |
0 |
8317 |
if (RHSMask.getNode()) { |
0 |
| 8318 |
SDValue LHSBits = DAG.getNode(ISD::SHL, DL, VT, AllOnes, LHSShiftAmt); |
0 |
8318 |
SDValue LHSBits = DAG.getNode(ISD::SHL, DL, VT, AllOnes, LHSShiftAmt); |
0 |
| 8319 |
Mask = DAG.getNode(ISD::AND, DL, VT, Mask, |
0 |
8319 |
Mask = DAG.getNode(ISD::AND, DL, VT, Mask, |
0 |
| 8320 |
DAG.getNode(ISD::OR, DL, VT, RHSMask, LHSBits)); |
0 |
8320 |
DAG.getNode(ISD::OR, DL, VT, RHSMask, LHSBits)); |
0 |
| 8321 |
} |
--- |
8321 |
} |
--- |
| 8322 |
|
--- |
8322 |
|
--- |
| 8323 |
Res = DAG.getNode(ISD::AND, DL, VT, Res, Mask); |
0 |
8323 |
Res = DAG.getNode(ISD::AND, DL, VT, Res, Mask); |
0 |
| 8324 |
} |
--- |
8324 |
} |
--- |
| 8325 |
|
--- |
8325 |
|
--- |
| 8326 |
return Res; |
0 |
8326 |
return Res; |
0 |
| 8327 |
}; |
0 |
8327 |
}; |
0 |
| 8328 |
|
--- |
8328 |
|
--- |
| 8329 |
// TODO: Support pre-legalization funnel-shift by constant. |
--- |
8329 |
// TODO: Support pre-legalization funnel-shift by constant. |
--- |
| 8330 |
bool IsRotate = LHSShiftArg == RHSShiftArg; |
0 |
8330 |
bool IsRotate = LHSShiftArg == RHSShiftArg; |
0 |
| 8331 |
if (!IsRotate && !(HasFSHL || HasFSHR)) { |
0 |
8331 |
if (!IsRotate && !(HasFSHL || HasFSHR)) { |
0 |
| 8332 |
if (TLI.isTypeLegal(VT) && LHS.hasOneUse() && RHS.hasOneUse() && |
0 |
8332 |
if (TLI.isTypeLegal(VT) && LHS.hasOneUse() && RHS.hasOneUse() && |
0 |
| 8333 |
ISD::matchBinaryPredicate(LHSShiftAmt, RHSShiftAmt, MatchRotateSum)) { |
0 |
8333 |
ISD::matchBinaryPredicate(LHSShiftAmt, RHSShiftAmt, MatchRotateSum)) { |
0 |
| 8334 |
// Look for a disguised rotate by constant. |
--- |
8334 |
// Look for a disguised rotate by constant. |
--- |
| 8335 |
// The common shifted operand X may be hidden inside another 'or'. |
--- |
8335 |
// The common shifted operand X may be hidden inside another 'or'. |
--- |
| 8336 |
SDValue X, Y; |
0 |
8336 |
SDValue X, Y; |
0 |
| 8337 |
auto matchOr = [&X, &Y](SDValue Or, SDValue CommonOp) { |
0 |
8337 |
auto matchOr = [&X, &Y](SDValue Or, SDValue CommonOp) { |
0 |
| 8338 |
if (!Or.hasOneUse() || Or.getOpcode() != ISD::OR) |
0 |
8338 |
if (!Or.hasOneUse() || Or.getOpcode() != ISD::OR) |
0 |
| 8339 |
return false; |
0 |
8339 |
return false; |
0 |
| 8340 |
if (CommonOp == Or.getOperand(0)) { |
0 |
8340 |
if (CommonOp == Or.getOperand(0)) { |
0 |
| 8341 |
X = CommonOp; |
0 |
8341 |
X = CommonOp; |
0 |
| 8342 |
Y = Or.getOperand(1); |
0 |
8342 |
Y = Or.getOperand(1); |
0 |
| 8343 |
return true; |
0 |
8343 |
return true; |
0 |
| 8344 |
} |
--- |
8344 |
} |
--- |
| 8345 |
if (CommonOp == Or.getOperand(1)) { |
0 |
8345 |
if (CommonOp == Or.getOperand(1)) { |
0 |
| 8346 |
X = CommonOp; |
0 |
8346 |
X = CommonOp; |
0 |
| 8347 |
Y = Or.getOperand(0); |
0 |
8347 |
Y = Or.getOperand(0); |
0 |
| 8348 |
return true; |
0 |
8348 |
return true; |
0 |
| 8349 |
} |
--- |
8349 |
} |
--- |
| 8350 |
return false; |
0 |
8350 |
return false; |
0 |
| 8351 |
}; |
0 |
8351 |
}; |
0 |
| 8352 |
|
--- |
8352 |
|
--- |
| 8353 |
SDValue Res; |
0 |
8353 |
SDValue Res; |
0 |
| 8354 |
if (matchOr(LHSShiftArg, RHSShiftArg)) { |
0 |
8354 |
if (matchOr(LHSShiftArg, RHSShiftArg)) { |
0 |
| 8355 |
// (shl (X | Y), C1) | (srl X, C2) --> (rotl X, C1) | (shl Y, C1) |
--- |
8355 |
// (shl (X | Y), C1) | (srl X, C2) --> (rotl X, C1) | (shl Y, C1) |
--- |
| 8356 |
SDValue RotX = DAG.getNode(ISD::ROTL, DL, VT, X, LHSShiftAmt); |
0 |
8356 |
SDValue RotX = DAG.getNode(ISD::ROTL, DL, VT, X, LHSShiftAmt); |
0 |
| 8357 |
SDValue ShlY = DAG.getNode(ISD::SHL, DL, VT, Y, LHSShiftAmt); |
0 |
8357 |
SDValue ShlY = DAG.getNode(ISD::SHL, DL, VT, Y, LHSShiftAmt); |
0 |
| 8358 |
Res = DAG.getNode(ISD::OR, DL, VT, RotX, ShlY); |
0 |
8358 |
Res = DAG.getNode(ISD::OR, DL, VT, RotX, ShlY); |
0 |
| 8359 |
} else if (matchOr(RHSShiftArg, LHSShiftArg)) { |
0 |
8359 |
} else if (matchOr(RHSShiftArg, LHSShiftArg)) { |
0 |
| 8360 |
// (shl X, C1) | (srl (X | Y), C2) --> (rotl X, C1) | (srl Y, C2) |
--- |
8360 |
// (shl X, C1) | (srl (X | Y), C2) --> (rotl X, C1) | (srl Y, C2) |
--- |
| 8361 |
SDValue RotX = DAG.getNode(ISD::ROTL, DL, VT, X, LHSShiftAmt); |
0 |
8361 |
SDValue RotX = DAG.getNode(ISD::ROTL, DL, VT, X, LHSShiftAmt); |
0 |
| 8362 |
SDValue SrlY = DAG.getNode(ISD::SRL, DL, VT, Y, RHSShiftAmt); |
0 |
8362 |
SDValue SrlY = DAG.getNode(ISD::SRL, DL, VT, Y, RHSShiftAmt); |
0 |
| 8363 |
Res = DAG.getNode(ISD::OR, DL, VT, RotX, SrlY); |
0 |
8363 |
Res = DAG.getNode(ISD::OR, DL, VT, RotX, SrlY); |
0 |
| 8364 |
} else { |
--- |
8364 |
} else { |
--- |
| 8365 |
return SDValue(); |
0 |
8365 |
return SDValue(); |
0 |
| 8366 |
} |
--- |
8366 |
} |
--- |
| 8367 |
|
--- |
8367 |
|
--- |
| 8368 |
return ApplyMasks(Res); |
0 |
8368 |
return ApplyMasks(Res); |
0 |
| 8369 |
} |
--- |
8369 |
} |
--- |
| 8370 |
|
--- |
8370 |
|
--- |
| 8371 |
return SDValue(); // Requires funnel shift support. |
0 |
8371 |
return SDValue(); // Requires funnel shift support. |
0 |
| 8372 |
} |
--- |
8372 |
} |
--- |
| 8373 |
|
--- |
8373 |
|
--- |
| 8374 |
// fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) |
--- |
8374 |
// fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) |
--- |
| 8375 |
// fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) |
--- |
8375 |
// fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) |
--- |
| 8376 |
// fold (or (shl x, C1), (srl y, C2)) -> (fshl x, y, C1) |
--- |
8376 |
// fold (or (shl x, C1), (srl y, C2)) -> (fshl x, y, C1) |
--- |
| 8377 |
// fold (or (shl x, C1), (srl y, C2)) -> (fshr x, y, C2) |
--- |
8377 |
// fold (or (shl x, C1), (srl y, C2)) -> (fshr x, y, C2) |
--- |
| 8378 |
// iff C1+C2 == EltSizeInBits |
--- |
8378 |
// iff C1+C2 == EltSizeInBits |
--- |
| 8379 |
if (ISD::matchBinaryPredicate(LHSShiftAmt, RHSShiftAmt, MatchRotateSum)) { |
0 |
8379 |
if (ISD::matchBinaryPredicate(LHSShiftAmt, RHSShiftAmt, MatchRotateSum)) { |
0 |
| 8380 |
SDValue Res; |
0 |
8380 |
SDValue Res; |
0 |
| 8381 |
if (IsRotate && (HasROTL || HasROTR || !(HasFSHL || HasFSHR))) { |
0 |
8381 |
if (IsRotate && (HasROTL || HasROTR || !(HasFSHL || HasFSHR))) { |
0 |
| 8382 |
bool UseROTL = !LegalOperations || HasROTL; |
0 |
8382 |
bool UseROTL = !LegalOperations || HasROTL; |
0 |
| 8383 |
Res = DAG.getNode(UseROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, |
0 |
8383 |
Res = DAG.getNode(UseROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, |
0 |
| 8384 |
UseROTL ? LHSShiftAmt : RHSShiftAmt); |
0 |
8384 |
UseROTL ? LHSShiftAmt : RHSShiftAmt); |
0 |
| 8385 |
} else { |
0 |
8385 |
} else { |
0 |
| 8386 |
bool UseFSHL = !LegalOperations || HasFSHL; |
0 |
8386 |
bool UseFSHL = !LegalOperations || HasFSHL; |
0 |
| 8387 |
Res = DAG.getNode(UseFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, |
0 |
8387 |
Res = DAG.getNode(UseFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, |
0 |
| 8388 |
RHSShiftArg, UseFSHL ? LHSShiftAmt : RHSShiftAmt); |
0 |
8388 |
RHSShiftArg, UseFSHL ? LHSShiftAmt : RHSShiftAmt); |
0 |
| 8389 |
} |
--- |
8389 |
} |
--- |
| 8390 |
|
--- |
8390 |
|
--- |
| 8391 |
return ApplyMasks(Res); |
0 |
8391 |
return ApplyMasks(Res); |
0 |
| 8392 |
} |
--- |
8392 |
} |
--- |
| 8393 |
|
--- |
8393 |
|
--- |
| 8394 |
// Even pre-legalization, we can't easily rotate/funnel-shift by a variable |
--- |
8394 |
// Even pre-legalization, we can't easily rotate/funnel-shift by a variable |
--- |
| 8395 |
// shift. |
--- |
8395 |
// shift. |
--- |
| 8396 |
if (!HasROTL && !HasROTR && !HasFSHL && !HasFSHR) |
0 |
8396 |
if (!HasROTL && !HasROTR && !HasFSHL && !HasFSHR) |
0 |
| 8397 |
return SDValue(); |
0 |
8397 |
return SDValue(); |
0 |
| 8398 |
|
--- |
8398 |
|
--- |
| 8399 |
// If there is a mask here, and we have a variable shift, we can't be sure |
--- |
8399 |
// If there is a mask here, and we have a variable shift, we can't be sure |
--- |
| 8400 |
// that we're masking out the right stuff. |
--- |
8400 |
// that we're masking out the right stuff. |
--- |
| 8401 |
if (LHSMask.getNode() || RHSMask.getNode()) |
0 |
8401 |
if (LHSMask.getNode() || RHSMask.getNode()) |
0 |
| 8402 |
return SDValue(); |
0 |
8402 |
return SDValue(); |
0 |
| 8403 |
|
--- |
8403 |
|
--- |
| 8404 |
// If the shift amount is sign/zext/any-extended just peel it off. |
--- |
8404 |
// If the shift amount is sign/zext/any-extended just peel it off. |
--- |
| 8405 |
SDValue LExtOp0 = LHSShiftAmt; |
0 |
8405 |
SDValue LExtOp0 = LHSShiftAmt; |
0 |
| 8406 |
SDValue RExtOp0 = RHSShiftAmt; |
0 |
8406 |
SDValue RExtOp0 = RHSShiftAmt; |
0 |
| 8407 |
if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || |
0 |
8407 |
if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || |
0 |
| 8408 |
LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || |
0 |
8408 |
LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || |
0 |
| 8409 |
LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || |
0 |
8409 |
LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || |
0 |
| 8410 |
LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && |
0 |
8410 |
LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && |
0 |
| 8411 |
(RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || |
0 |
8411 |
(RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || |
0 |
| 8412 |
RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || |
0 |
8412 |
RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || |
0 |
| 8413 |
RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || |
0 |
8413 |
RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || |
0 |
| 8414 |
RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { |
0 |
8414 |
RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { |
0 |
| 8415 |
LExtOp0 = LHSShiftAmt.getOperand(0); |
0 |
8415 |
LExtOp0 = LHSShiftAmt.getOperand(0); |
0 |
| 8416 |
RExtOp0 = RHSShiftAmt.getOperand(0); |
0 |
8416 |
RExtOp0 = RHSShiftAmt.getOperand(0); |
0 |
| 8417 |
} |
--- |
8417 |
} |
--- |
| 8418 |
|
--- |
8418 |
|
--- |
| 8419 |
if (IsRotate && (HasROTL || HasROTR)) { |
0 |
8419 |
if (IsRotate && (HasROTL || HasROTR)) { |
0 |
| 8420 |
SDValue TryL = |
--- |
8420 |
SDValue TryL = |
--- |
| 8421 |
MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt, LExtOp0, |
0 |
8421 |
MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt, LExtOp0, |
0 |
| 8422 |
RExtOp0, HasROTL, ISD::ROTL, ISD::ROTR, DL); |
--- |
8422 |
RExtOp0, HasROTL, ISD::ROTL, ISD::ROTR, DL); |
--- |
| 8423 |
if (TryL) |
0 |
8423 |
if (TryL) |
0 |
| 8424 |
return TryL; |
0 |
8424 |
return TryL; |
0 |
| 8425 |
|
--- |
8425 |
|
--- |
| 8426 |
SDValue TryR = |
--- |
8426 |
SDValue TryR = |
--- |
| 8427 |
MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt, RExtOp0, |
0 |
8427 |
MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt, RExtOp0, |
0 |
| 8428 |
LExtOp0, HasROTR, ISD::ROTR, ISD::ROTL, DL); |
--- |
8428 |
LExtOp0, HasROTR, ISD::ROTR, ISD::ROTL, DL); |
--- |
| 8429 |
if (TryR) |
0 |
8429 |
if (TryR) |
0 |
| 8430 |
return TryR; |
0 |
8430 |
return TryR; |
0 |
| 8431 |
} |
--- |
8431 |
} |
--- |
| 8432 |
|
--- |
8432 |
|
--- |
| 8433 |
SDValue TryL = |
--- |
8433 |
SDValue TryL = |
--- |
| 8434 |
MatchFunnelPosNeg(LHSShiftArg, RHSShiftArg, LHSShiftAmt, RHSShiftAmt, |
0 |
8434 |
MatchFunnelPosNeg(LHSShiftArg, RHSShiftArg, LHSShiftAmt, RHSShiftAmt, |
0 |
| 8435 |
LExtOp0, RExtOp0, HasFSHL, ISD::FSHL, ISD::FSHR, DL); |
--- |
8435 |
LExtOp0, RExtOp0, HasFSHL, ISD::FSHL, ISD::FSHR, DL); |
--- |
| 8436 |
if (TryL) |
0 |
8436 |
if (TryL) |
0 |
| 8437 |
return TryL; |
0 |
8437 |
return TryL; |
0 |
| 8438 |
|
--- |
8438 |
|
--- |
| 8439 |
SDValue TryR = |
--- |
8439 |
SDValue TryR = |
--- |
| 8440 |
MatchFunnelPosNeg(LHSShiftArg, RHSShiftArg, RHSShiftAmt, LHSShiftAmt, |
0 |
8440 |
MatchFunnelPosNeg(LHSShiftArg, RHSShiftArg, RHSShiftAmt, LHSShiftAmt, |
0 |
| 8441 |
RExtOp0, LExtOp0, HasFSHR, ISD::FSHR, ISD::FSHL, DL); |
--- |
8441 |
RExtOp0, LExtOp0, HasFSHR, ISD::FSHR, ISD::FSHL, DL); |
--- |
| 8442 |
if (TryR) |
0 |
8442 |
if (TryR) |
0 |
| 8443 |
return TryR; |
0 |
8443 |
return TryR; |
0 |
| 8444 |
|
--- |
8444 |
|
--- |
| 8445 |
return SDValue(); |
0 |
8445 |
return SDValue(); |
0 |
| 8446 |
} |
--- |
8446 |
} |
--- |
| 8447 |
|
--- |
8447 |
|
--- |
| 8448 |
/// Recursively traverses the expression calculating the origin of the requested |
--- |
8448 |
/// Recursively traverses the expression calculating the origin of the requested |
--- |
| 8449 |
/// byte of the given value. Returns std::nullopt if the provider can't be |
--- |
8449 |
/// byte of the given value. Returns std::nullopt if the provider can't be |
--- |
| 8450 |
/// calculated. |
--- |
8450 |
/// calculated. |
--- |
| 8451 |
/// |
--- |
8451 |
/// |
--- |
| 8452 |
/// For all the values except the root of the expression, we verify that the |
--- |
8452 |
/// For all the values except the root of the expression, we verify that the |
--- |
| 8453 |
/// value has exactly one use and if not then return std::nullopt. This way if |
--- |
8453 |
/// value has exactly one use and if not then return std::nullopt. This way if |
--- |
| 8454 |
/// the origin of the byte is returned it's guaranteed that the values which |
--- |
8454 |
/// the origin of the byte is returned it's guaranteed that the values which |
--- |
| 8455 |
/// contribute to the byte are not used outside of this expression. |
--- |
8455 |
/// contribute to the byte are not used outside of this expression. |
--- |
| 8456 |
|
--- |
8456 |
|
--- |
| 8457 |
/// However, there is a special case when dealing with vector loads -- we allow |
--- |
8457 |
/// However, there is a special case when dealing with vector loads -- we allow |
--- |
| 8458 |
/// more than one use if the load is a vector type. Since the values that |
--- |
8458 |
/// more than one use if the load is a vector type. Since the values that |
--- |
| 8459 |
/// contribute to the byte ultimately come from the ExtractVectorElements of the |
--- |
8459 |
/// contribute to the byte ultimately come from the ExtractVectorElements of the |
--- |
| 8460 |
/// Load, we don't care if the Load has uses other than ExtractVectorElements, |
--- |
8460 |
/// Load, we don't care if the Load has uses other than ExtractVectorElements, |
--- |
| 8461 |
/// because those operations are independent from the pattern to be combined. |
--- |
8461 |
/// because those operations are independent from the pattern to be combined. |
--- |
| 8462 |
/// For vector loads, we simply care that the ByteProviders are adjacent |
--- |
8462 |
/// For vector loads, we simply care that the ByteProviders are adjacent |
--- |
| 8463 |
/// positions of the same vector, and their index matches the byte that is being |
--- |
8463 |
/// positions of the same vector, and their index matches the byte that is being |
--- |
| 8464 |
/// provided. This is captured by the \p VectorIndex algorithm. \p VectorIndex |
--- |
8464 |
/// provided. This is captured by the \p VectorIndex algorithm. \p VectorIndex |
--- |
| 8465 |
/// is the index used in an ExtractVectorElement, and \p StartingIndex is the |
--- |
8465 |
/// is the index used in an ExtractVectorElement, and \p StartingIndex is the |
--- |
| 8466 |
/// byte position we are trying to provide for the LoadCombine. If these do |
--- |
8466 |
/// byte position we are trying to provide for the LoadCombine. If these do |
--- |
| 8467 |
/// not match, then we can not combine the vector loads. \p Index uses the |
--- |
8467 |
/// not match, then we can not combine the vector loads. \p Index uses the |
--- |
| 8468 |
/// byte position we are trying to provide for and is matched against the |
--- |
8468 |
/// byte position we are trying to provide for and is matched against the |
--- |
| 8469 |
/// shl and load size. The \p Index algorithm ensures the requested byte is |
--- |
8469 |
/// shl and load size. The \p Index algorithm ensures the requested byte is |
--- |
| 8470 |
/// provided for by the pattern, and the pattern does not over provide bytes. |
--- |
8470 |
/// provided for by the pattern, and the pattern does not over provide bytes. |
--- |
| 8471 |
/// |
--- |
8471 |
/// |
--- |
| 8472 |
/// |
--- |
8472 |
/// |
--- |
| 8473 |
/// The supported LoadCombine pattern for vector loads is as follows |
--- |
8473 |
/// The supported LoadCombine pattern for vector loads is as follows |
--- |
| 8474 |
/// or |
--- |
8474 |
/// or |
--- |
| 8475 |
/// / \ |
--- |
8475 |
/// / \ |
--- |
| 8476 |
/// or shl |
--- |
8476 |
/// or shl |
--- |
| 8477 |
/// / \ | |
--- |
8477 |
/// / \ | |
--- |
| 8478 |
/// or shl zext |
--- |
8478 |
/// or shl zext |
--- |
| 8479 |
/// / \ | | |
--- |
8479 |
/// / \ | | |
--- |
| 8480 |
/// shl zext zext EVE* |
--- |
8480 |
/// shl zext zext EVE* |
--- |
| 8481 |
/// | | | | |
--- |
8481 |
/// | | | | |
--- |
| 8482 |
/// zext EVE* EVE* LOAD |
--- |
8482 |
/// zext EVE* EVE* LOAD |
--- |
| 8483 |
/// | | | |
--- |
8483 |
/// | | | |
--- |
| 8484 |
/// EVE* LOAD LOAD |
--- |
8484 |
/// EVE* LOAD LOAD |
--- |
| 8485 |
/// | |
--- |
8485 |
/// | |
--- |
| 8486 |
/// LOAD |
--- |
8486 |
/// LOAD |
--- |
| 8487 |
/// |
--- |
8487 |
/// |
--- |
| 8488 |
/// *ExtractVectorElement |
--- |
8488 |
/// *ExtractVectorElement |
--- |
| 8489 |
using SDByteProvider = ByteProvider; |
--- |
8489 |
using SDByteProvider = ByteProvider; |
--- |
| 8490 |
|
--- |
8490 |
|
--- |
| 8491 |
static const std::optional |
--- |
8491 |
static const std::optional |
--- |
| 8492 |
calculateByteProvider(SDValue Op, unsigned Index, unsigned Depth, |
0 |
8492 |
calculateByteProvider(SDValue Op, unsigned Index, unsigned Depth, |
0 |
| 8493 |
std::optional VectorIndex, |
--- |
8493 |
std::optional VectorIndex, |
--- |
| 8494 |
unsigned StartingIndex = 0) { |
--- |
8494 |
unsigned StartingIndex = 0) { |
--- |
| 8495 |
|
--- |
8495 |
|
--- |
| 8496 |
// Typical i64 by i8 pattern requires recursion up to 8 calls depth |
--- |
8496 |
// Typical i64 by i8 pattern requires recursion up to 8 calls depth |
--- |
| 8497 |
if (Depth == 10) |
0 |
8497 |
if (Depth == 10) |
0 |
| 8498 |
return std::nullopt; |
0 |
8498 |
return std::nullopt; |
0 |
| 8499 |
|
--- |
8499 |
|
--- |
| 8500 |
// Only allow multiple uses if the instruction is a vector load (in which |
--- |
8500 |
// Only allow multiple uses if the instruction is a vector load (in which |
--- |
| 8501 |
// case we will use the load for every ExtractVectorElement) |
--- |
8501 |
// case we will use the load for every ExtractVectorElement) |
--- |
| 8502 |
if (Depth && !Op.hasOneUse() && |
0 |
8502 |
if (Depth && !Op.hasOneUse() && |
0 |
| 8503 |
(Op.getOpcode() != ISD::LOAD || !Op.getValueType().isVector())) |
0 |
8503 |
(Op.getOpcode() != ISD::LOAD || !Op.getValueType().isVector())) |
0 |
| 8504 |
return std::nullopt; |
0 |
8504 |
return std::nullopt; |
0 |
| 8505 |
|
--- |
8505 |
|
--- |
| 8506 |
// Fail to combine if we have encountered anything but a LOAD after handling |
--- |
8506 |
// Fail to combine if we have encountered anything but a LOAD after handling |
--- |
| 8507 |
// an ExtractVectorElement. |
--- |
8507 |
// an ExtractVectorElement. |
--- |
| 8508 |
if (Op.getOpcode() != ISD::LOAD && VectorIndex.has_value()) |
0 |
8508 |
if (Op.getOpcode() != ISD::LOAD && VectorIndex.has_value()) |
0 |
| 8509 |
return std::nullopt; |
0 |
8509 |
return std::nullopt; |
0 |
| 8510 |
|
--- |
8510 |
|
--- |
| 8511 |
unsigned BitWidth = Op.getValueSizeInBits(); |
0 |
8511 |
unsigned BitWidth = Op.getValueSizeInBits(); |
0 |
| 8512 |
if (BitWidth % 8 != 0) |
0 |
8512 |
if (BitWidth % 8 != 0) |
0 |
| 8513 |
return std::nullopt; |
0 |
8513 |
return std::nullopt; |
0 |
| 8514 |
unsigned ByteWidth = BitWidth / 8; |
0 |
8514 |
unsigned ByteWidth = BitWidth / 8; |
0 |
| 8515 |
assert(Index < ByteWidth && "invalid index requested"); |
0 |
8515 |
assert(Index < ByteWidth && "invalid index requested"); |
0 |
| 8516 |
(void) ByteWidth; |
--- |
8516 |
(void) ByteWidth; |
--- |
| 8517 |
|
--- |
8517 |
|
--- |
| 8518 |
switch (Op.getOpcode()) { |
0 |
8518 |
switch (Op.getOpcode()) { |
0 |
| 8519 |
case ISD::OR: { |
0 |
8519 |
case ISD::OR: { |
0 |
| 8520 |
auto LHS = |
--- |
8520 |
auto LHS = |
--- |
| 8521 |
calculateByteProvider(Op->getOperand(0), Index, Depth + 1, VectorIndex); |
0 |
8521 |
calculateByteProvider(Op->getOperand(0), Index, Depth + 1, VectorIndex); |
0 |
| 8522 |
if (!LHS) |
0 |
8522 |
if (!LHS) |
0 |
| 8523 |
return std::nullopt; |
0 |
8523 |
return std::nullopt; |
0 |
| 8524 |
auto RHS = |
--- |
8524 |
auto RHS = |
--- |
| 8525 |
calculateByteProvider(Op->getOperand(1), Index, Depth + 1, VectorIndex); |
0 |
8525 |
calculateByteProvider(Op->getOperand(1), Index, Depth + 1, VectorIndex); |
0 |
| 8526 |
if (!RHS) |
0 |
8526 |
if (!RHS) |
0 |
| 8527 |
return std::nullopt; |
0 |
8527 |
return std::nullopt; |
0 |
| 8528 |
|
--- |
8528 |
|
--- |
| 8529 |
if (LHS->isConstantZero()) |
0 |
8529 |
if (LHS->isConstantZero()) |
0 |
| 8530 |
return RHS; |
0 |
8530 |
return RHS; |
0 |
| 8531 |
if (RHS->isConstantZero()) |
0 |
8531 |
if (RHS->isConstantZero()) |
0 |
| 8532 |
return LHS; |
0 |
8532 |
return LHS; |
0 |
| 8533 |
return std::nullopt; |
0 |
8533 |
return std::nullopt; |
0 |
| 8534 |
} |
--- |
8534 |
} |
--- |
| 8535 |
case ISD::SHL: { |
0 |
8535 |
case ISD::SHL: { |
0 |
| 8536 |
auto ShiftOp = dyn_cast(Op->getOperand(1)); |
0 |
8536 |
auto ShiftOp = dyn_cast(Op->getOperand(1)); |
0 |
| 8537 |
if (!ShiftOp) |
0 |
8537 |
if (!ShiftOp) |
0 |
| 8538 |
return std::nullopt; |
0 |
8538 |
return std::nullopt; |
0 |
| 8539 |
|
--- |
8539 |
|
--- |
| 8540 |
uint64_t BitShift = ShiftOp->getZExtValue(); |
0 |
8540 |
uint64_t BitShift = ShiftOp->getZExtValue(); |
0 |
| 8541 |
|
--- |
8541 |
|
--- |
| 8542 |
if (BitShift % 8 != 0) |
0 |
8542 |
if (BitShift % 8 != 0) |
0 |
| 8543 |
return std::nullopt; |
0 |
8543 |
return std::nullopt; |
0 |
| 8544 |
uint64_t ByteShift = BitShift / 8; |
0 |
8544 |
uint64_t ByteShift = BitShift / 8; |
0 |
| 8545 |
|
--- |
8545 |
|
--- |
| 8546 |
// If we are shifting by an amount greater than the index we are trying to |
--- |
8546 |
// If we are shifting by an amount greater than the index we are trying to |
--- |
| 8547 |
// provide, then do not provide anything. Otherwise, subtract the index by |
--- |
8547 |
// provide, then do not provide anything. Otherwise, subtract the index by |
--- |
| 8548 |
// the amount we shifted by. |
--- |
8548 |
// the amount we shifted by. |
--- |
| 8549 |
return Index < ByteShift |
0 |
8549 |
return Index < ByteShift |
0 |
| 8550 |
? SDByteProvider::getConstantZero() |
0 |
8550 |
? SDByteProvider::getConstantZero() |
0 |
| 8551 |
: calculateByteProvider(Op->getOperand(0), Index - ByteShift, |
0 |
8551 |
: calculateByteProvider(Op->getOperand(0), Index - ByteShift, |
0 |
| 8552 |
Depth + 1, VectorIndex, Index); |
0 |
8552 |
Depth + 1, VectorIndex, Index); |
0 |
| 8553 |
} |
--- |
8553 |
} |
--- |
| 8554 |
case ISD::ANY_EXTEND: |
0 |
8554 |
case ISD::ANY_EXTEND: |
0 |
| 8555 |
case ISD::SIGN_EXTEND: |
--- |
8555 |
case ISD::SIGN_EXTEND: |
--- |
| 8556 |
case ISD::ZERO_EXTEND: { |
--- |
8556 |
case ISD::ZERO_EXTEND: { |
--- |
| 8557 |
SDValue NarrowOp = Op->getOperand(0); |
0 |
8557 |
SDValue NarrowOp = Op->getOperand(0); |
0 |
| 8558 |
unsigned NarrowBitWidth = NarrowOp.getScalarValueSizeInBits(); |
0 |
8558 |
unsigned NarrowBitWidth = NarrowOp.getScalarValueSizeInBits(); |
0 |
| 8559 |
if (NarrowBitWidth % 8 != 0) |
0 |
8559 |
if (NarrowBitWidth % 8 != 0) |
0 |
| 8560 |
return std::nullopt; |
0 |
8560 |
return std::nullopt; |
0 |
| 8561 |
uint64_t NarrowByteWidth = NarrowBitWidth / 8; |
0 |
8561 |
uint64_t NarrowByteWidth = NarrowBitWidth / 8; |
0 |
| 8562 |
|
--- |
8562 |
|
--- |
| 8563 |
if (Index >= NarrowByteWidth) |
0 |
8563 |
if (Index >= NarrowByteWidth) |
0 |
| 8564 |
return Op.getOpcode() == ISD::ZERO_EXTEND |
0 |
8564 |
return Op.getOpcode() == ISD::ZERO_EXTEND |
0 |
| 8565 |
? std::optional( |
--- |
8565 |
? std::optional( |
--- |
| 8566 |
SDByteProvider::getConstantZero()) |
0 |
8566 |
SDByteProvider::getConstantZero()) |
0 |
| 8567 |
: std::nullopt; |
0 |
8567 |
: std::nullopt; |
0 |
| 8568 |
return calculateByteProvider(NarrowOp, Index, Depth + 1, VectorIndex, |
0 |
8568 |
return calculateByteProvider(NarrowOp, Index, Depth + 1, VectorIndex, |
0 |
| 8569 |
StartingIndex); |
0 |
8569 |
StartingIndex); |
0 |
| 8570 |
} |
--- |
8570 |
} |
--- |
| 8571 |
case ISD::BSWAP: |
0 |
8571 |
case ISD::BSWAP: |
0 |
| 8572 |
return calculateByteProvider(Op->getOperand(0), ByteWidth - Index - 1, |
0 |
8572 |
return calculateByteProvider(Op->getOperand(0), ByteWidth - Index - 1, |
0 |
| 8573 |
Depth + 1, VectorIndex, StartingIndex); |
0 |
8573 |
Depth + 1, VectorIndex, StartingIndex); |
0 |
| 8574 |
case ISD::EXTRACT_VECTOR_ELT: { |
0 |
8574 |
case ISD::EXTRACT_VECTOR_ELT: { |
0 |
| 8575 |
auto OffsetOp = dyn_cast(Op->getOperand(1)); |
0 |
8575 |
auto OffsetOp = dyn_cast(Op->getOperand(1)); |
0 |
| 8576 |
if (!OffsetOp) |
0 |
8576 |
if (!OffsetOp) |
0 |
| 8577 |
return std::nullopt; |
0 |
8577 |
return std::nullopt; |
0 |
| 8578 |
|
--- |
8578 |
|
--- |
| 8579 |
VectorIndex = OffsetOp->getZExtValue(); |
0 |
8579 |
VectorIndex = OffsetOp->getZExtValue(); |
0 |
| 8580 |
|
--- |
8580 |
|
--- |
| 8581 |
SDValue NarrowOp = Op->getOperand(0); |
0 |
8581 |
SDValue NarrowOp = Op->getOperand(0); |
0 |
| 8582 |
unsigned NarrowBitWidth = NarrowOp.getScalarValueSizeInBits(); |
0 |
8582 |
unsigned NarrowBitWidth = NarrowOp.getScalarValueSizeInBits(); |
0 |
| 8583 |
if (NarrowBitWidth % 8 != 0) |
0 |
8583 |
if (NarrowBitWidth % 8 != 0) |
0 |
| 8584 |
return std::nullopt; |
0 |
8584 |
return std::nullopt; |
0 |
| 8585 |
uint64_t NarrowByteWidth = NarrowBitWidth / 8; |
0 |
8585 |
uint64_t NarrowByteWidth = NarrowBitWidth / 8; |
0 |
| 8586 |
|
--- |
8586 |
|
--- |
| 8587 |
// Check to see if the position of the element in the vector corresponds |
--- |
8587 |
// Check to see if the position of the element in the vector corresponds |
--- |
| 8588 |
// with the byte we are trying to provide for. In the case of a vector of |
--- |
8588 |
// with the byte we are trying to provide for. In the case of a vector of |
--- |
| 8589 |
// i8, this simply means the VectorIndex == StartingIndex. For non i8 cases, |
--- |
8589 |
// i8, this simply means the VectorIndex == StartingIndex. For non i8 cases, |
--- |
| 8590 |
// the element will provide a range of bytes. For example, if we have a |
--- |
8590 |
// the element will provide a range of bytes. For example, if we have a |
--- |
| 8591 |
// vector of i16s, each element provides two bytes (V[1] provides byte 2 and |
--- |
8591 |
// vector of i16s, each element provides two bytes (V[1] provides byte 2 and |
--- |
| 8592 |
// 3). |
--- |
8592 |
// 3). |
--- |
| 8593 |
if (*VectorIndex * NarrowByteWidth > StartingIndex) |
0 |
8593 |
if (*VectorIndex * NarrowByteWidth > StartingIndex) |
0 |
| 8594 |
return std::nullopt; |
0 |
8594 |
return std::nullopt; |
0 |
| 8595 |
if ((*VectorIndex + 1) * NarrowByteWidth <= StartingIndex) |
0 |
8595 |
if ((*VectorIndex + 1) * NarrowByteWidth <= StartingIndex) |
0 |
| 8596 |
return std::nullopt; |
0 |
8596 |
return std::nullopt; |
0 |
| 8597 |
|
--- |
8597 |
|
--- |
| 8598 |
return calculateByteProvider(Op->getOperand(0), Index, Depth + 1, |
0 |
8598 |
return calculateByteProvider(Op->getOperand(0), Index, Depth + 1, |
0 |
| 8599 |
VectorIndex, StartingIndex); |
0 |
8599 |
VectorIndex, StartingIndex); |
0 |
| 8600 |
} |
--- |
8600 |
} |
--- |
| 8601 |
case ISD::LOAD: { |
0 |
8601 |
case ISD::LOAD: { |
0 |
| 8602 |
auto L = cast(Op.getNode()); |
0 |
8602 |
auto L = cast(Op.getNode()); |
0 |
| 8603 |
if (!L->isSimple() || L->isIndexed()) |
0 |
8603 |
if (!L->isSimple() || L->isIndexed()) |
0 |
| 8604 |
return std::nullopt; |
0 |
8604 |
return std::nullopt; |
0 |
| 8605 |
|
--- |
8605 |
|
--- |
| 8606 |
unsigned NarrowBitWidth = L->getMemoryVT().getSizeInBits(); |
0 |
8606 |
unsigned NarrowBitWidth = L->getMemoryVT().getSizeInBits(); |
0 |
| 8607 |
if (NarrowBitWidth % 8 != 0) |
0 |
8607 |
if (NarrowBitWidth % 8 != 0) |
0 |
| 8608 |
return std::nullopt; |
0 |
8608 |
return std::nullopt; |
0 |
| 8609 |
uint64_t NarrowByteWidth = NarrowBitWidth / 8; |
0 |
8609 |
uint64_t NarrowByteWidth = NarrowBitWidth / 8; |
0 |
| 8610 |
|
--- |
8610 |
|
--- |
| 8611 |
// If the width of the load does not reach byte we are trying to provide for |
--- |
8611 |
// If the width of the load does not reach byte we are trying to provide for |
--- |
| 8612 |
// and it is not a ZEXTLOAD, then the load does not provide for the byte in |
--- |
8612 |
// and it is not a ZEXTLOAD, then the load does not provide for the byte in |
--- |
| 8613 |
// question |
--- |
8613 |
// question |
--- |
| 8614 |
if (Index >= NarrowByteWidth) |
0 |
8614 |
if (Index >= NarrowByteWidth) |
0 |
| 8615 |
return L->getExtensionType() == ISD::ZEXTLOAD |
0 |
8615 |
return L->getExtensionType() == ISD::ZEXTLOAD |
0 |
| 8616 |
? std::optional( |
--- |
8616 |
? std::optional( |
--- |
| 8617 |
SDByteProvider::getConstantZero()) |
0 |
8617 |
SDByteProvider::getConstantZero()) |
0 |
| 8618 |
: std::nullopt; |
0 |
8618 |
: std::nullopt; |
0 |
| 8619 |
|
--- |
8619 |
|
--- |
| 8620 |
unsigned BPVectorIndex = VectorIndex.value_or(0U); |
0 |
8620 |
unsigned BPVectorIndex = VectorIndex.value_or(0U); |
0 |
| 8621 |
return SDByteProvider::getSrc(L, Index, BPVectorIndex); |
0 |
8621 |
return SDByteProvider::getSrc(L, Index, BPVectorIndex); |
0 |
| 8622 |
} |
--- |
8622 |
} |
--- |
| 8623 |
} |
--- |
8623 |
} |
--- |
| 8624 |
|
--- |
8624 |
|
--- |
| 8625 |
return std::nullopt; |
0 |
8625 |
return std::nullopt; |
0 |
| 8626 |
} |
--- |
8626 |
} |
--- |
| 8627 |
|
--- |
8627 |
|
--- |
| 8628 |
static unsigned littleEndianByteAt(unsigned BW, unsigned i) { |
0 |
8628 |
static unsigned littleEndianByteAt(unsigned BW, unsigned i) { |
0 |
| 8629 |
return i; |
0 |
8629 |
return i; |
0 |
| 8630 |
} |
--- |
8630 |
} |
--- |
| 8631 |
|
--- |
8631 |
|
--- |
| 8632 |
static unsigned bigEndianByteAt(unsigned BW, unsigned i) { |
0 |
8632 |
static unsigned bigEndianByteAt(unsigned BW, unsigned i) { |
0 |
| 8633 |
return BW - i - 1; |
0 |
8633 |
return BW - i - 1; |
0 |
| 8634 |
} |
--- |
8634 |
} |
--- |
| 8635 |
|
--- |
8635 |
|
--- |
| 8636 |
// Check if the bytes offsets we are looking at match with either big or |
--- |
8636 |
// Check if the bytes offsets we are looking at match with either big or |
--- |
| 8637 |
// little endian value loaded. Return true for big endian, false for little |
--- |
8637 |
// little endian value loaded. Return true for big endian, false for little |
--- |
| 8638 |
// endian, and std::nullopt if match failed. |
--- |
8638 |
// endian, and std::nullopt if match failed. |
--- |
| 8639 |
static std::optional isBigEndian(const ArrayRef ByteOffsets, |
0 |
8639 |
static std::optional isBigEndian(const ArrayRef ByteOffsets, |
0 |
| 8640 |
int64_t FirstOffset) { |
--- |
8640 |
int64_t FirstOffset) { |
--- |
| 8641 |
// The endian can be decided only when it is 2 bytes at least. |
--- |
8641 |
// The endian can be decided only when it is 2 bytes at least. |
--- |
| 8642 |
unsigned Width = ByteOffsets.size(); |
0 |
8642 |
unsigned Width = ByteOffsets.size(); |
0 |
| 8643 |
if (Width < 2) |
0 |
8643 |
if (Width < 2) |
0 |
| 8644 |
return std::nullopt; |
0 |
8644 |
return std::nullopt; |
0 |
| 8645 |
|
--- |
8645 |
|
--- |
| 8646 |
bool BigEndian = true, LittleEndian = true; |
0 |
8646 |
bool BigEndian = true, LittleEndian = true; |
0 |
| 8647 |
for (unsigned i = 0; i < Width; i++) { |
0 |
8647 |
for (unsigned i = 0; i < Width; i++) { |
0 |
| 8648 |
int64_t CurrentByteOffset = ByteOffsets[i] - FirstOffset; |
0 |
8648 |
int64_t CurrentByteOffset = ByteOffsets[i] - FirstOffset; |
0 |
| 8649 |
LittleEndian &= CurrentByteOffset == littleEndianByteAt(Width, i); |
0 |
8649 |
LittleEndian &= CurrentByteOffset == littleEndianByteAt(Width, i); |
0 |
| 8650 |
BigEndian &= CurrentByteOffset == bigEndianByteAt(Width, i); |
0 |
8650 |
BigEndian &= CurrentByteOffset == bigEndianByteAt(Width, i); |
0 |
| 8651 |
if (!BigEndian && !LittleEndian) |
0 |
8651 |
if (!BigEndian && !LittleEndian) |
0 |
| 8652 |
return std::nullopt; |
0 |
8652 |
return std::nullopt; |
0 |
| 8653 |
} |
--- |
8653 |
} |
--- |
| 8654 |
|
--- |
8654 |
|
--- |
| 8655 |
assert((BigEndian != LittleEndian) && "It should be either big endian or" |
0 |
8655 |
assert((BigEndian != LittleEndian) && "It should be either big endian or" |
0 |
| 8656 |
"little endian"); |
--- |
8656 |
"little endian"); |
--- |
| 8657 |
return BigEndian; |
0 |
8657 |
return BigEndian; |
0 |
| 8658 |
} |
--- |
8658 |
} |
--- |
| 8659 |
|
--- |
8659 |
|
--- |
| 8660 |
static SDValue stripTruncAndExt(SDValue Value) { |
0 |
8660 |
static SDValue stripTruncAndExt(SDValue Value) { |
0 |
| 8661 |
switch (Value.getOpcode()) { |
0 |
8661 |
switch (Value.getOpcode()) { |
0 |
| 8662 |
case ISD::TRUNCATE: |
0 |
8662 |
case ISD::TRUNCATE: |
0 |
| 8663 |
case ISD::ZERO_EXTEND: |
--- |
8663 |
case ISD::ZERO_EXTEND: |
--- |
| 8664 |
case ISD::SIGN_EXTEND: |
--- |
8664 |
case ISD::SIGN_EXTEND: |
--- |
| 8665 |
case ISD::ANY_EXTEND: |
--- |
8665 |
case ISD::ANY_EXTEND: |
--- |
| 8666 |
return stripTruncAndExt(Value.getOperand(0)); |
0 |
8666 |
return stripTruncAndExt(Value.getOperand(0)); |
0 |
| 8667 |
} |
--- |
8667 |
} |
--- |
| 8668 |
return Value; |
0 |
8668 |
return Value; |
0 |
| 8669 |
} |
--- |
8669 |
} |
--- |
| 8670 |
|
--- |
8670 |
|
--- |
| 8671 |
/// Match a pattern where a wide type scalar value is stored by several narrow |
--- |
8671 |
/// Match a pattern where a wide type scalar value is stored by several narrow |
--- |
| 8672 |
/// stores. Fold it into a single store or a BSWAP and a store if the targets |
--- |
8672 |
/// stores. Fold it into a single store or a BSWAP and a store if the targets |
--- |
| 8673 |
/// supports it. |
--- |
8673 |
/// supports it. |
--- |
| 8674 |
/// |
--- |
8674 |
/// |
--- |
| 8675 |
/// Assuming little endian target: |
--- |
8675 |
/// Assuming little endian target: |
--- |
| 8676 |
/// i8 *p = ... |
--- |
8676 |
/// i8 *p = ... |
--- |
| 8677 |
/// i32 val = ... |
--- |
8677 |
/// i32 val = ... |
--- |
| 8678 |
/// p[0] = (val >> 0) & 0xFF; |
--- |
8678 |
/// p[0] = (val >> 0) & 0xFF; |
--- |
| 8679 |
/// p[1] = (val >> 8) & 0xFF; |
--- |
8679 |
/// p[1] = (val >> 8) & 0xFF; |
--- |
| 8680 |
/// p[2] = (val >> 16) & 0xFF; |
--- |
8680 |
/// p[2] = (val >> 16) & 0xFF; |
--- |
| 8681 |
/// p[3] = (val >> 24) & 0xFF; |
--- |
8681 |
/// p[3] = (val >> 24) & 0xFF; |
--- |
| 8682 |
/// => |
--- |
8682 |
/// => |
--- |
| 8683 |
/// *((i32)p) = val; |
--- |
8683 |
/// *((i32)p) = val; |
--- |
| 8684 |
/// |
--- |
8684 |
/// |
--- |
| 8685 |
/// i8 *p = ... |
--- |
8685 |
/// i8 *p = ... |
--- |
| 8686 |
/// i32 val = ... |
--- |
8686 |
/// i32 val = ... |
--- |
| 8687 |
/// p[0] = (val >> 24) & 0xFF; |
--- |
8687 |
/// p[0] = (val >> 24) & 0xFF; |
--- |
| 8688 |
/// p[1] = (val >> 16) & 0xFF; |
--- |
8688 |
/// p[1] = (val >> 16) & 0xFF; |
--- |
| 8689 |
/// p[2] = (val >> 8) & 0xFF; |
--- |
8689 |
/// p[2] = (val >> 8) & 0xFF; |
--- |
| 8690 |
/// p[3] = (val >> 0) & 0xFF; |
--- |
8690 |
/// p[3] = (val >> 0) & 0xFF; |
--- |
| 8691 |
/// => |
--- |
8691 |
/// => |
--- |
| 8692 |
/// *((i32)p) = BSWAP(val); |
--- |
8692 |
/// *((i32)p) = BSWAP(val); |
--- |
| 8693 |
SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) { |
10 |
8693 |
SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) { |
10 |
| 8694 |
// The matching looks for "store (trunc x)" patterns that appear early but are |
--- |
8694 |
// The matching looks for "store (trunc x)" patterns that appear early but are |
--- |
| 8695 |
// likely to be replaced by truncating store nodes during combining. |
--- |
8695 |
// likely to be replaced by truncating store nodes during combining. |
--- |
| 8696 |
// TODO: If there is evidence that running this later would help, this |
--- |
8696 |
// TODO: If there is evidence that running this later would help, this |
--- |
| 8697 |
// limitation could be removed. Legality checks may need to be added |
--- |
8697 |
// limitation could be removed. Legality checks may need to be added |
--- |
| 8698 |
// for the created store and optional bswap/rotate. |
--- |
8698 |
// for the created store and optional bswap/rotate. |
--- |
| 8699 |
if (LegalOperations || OptLevel == CodeGenOpt::None) |
10 |
8699 |
if (LegalOperations || OptLevel == CodeGenOpt::None) |
10 |
| 8700 |
return SDValue(); |
10 |
8700 |
return SDValue(); |
10 |
| 8701 |
|
--- |
8701 |
|
--- |
| 8702 |
// We only handle merging simple stores of 1-4 bytes. |
--- |
8702 |
// We only handle merging simple stores of 1-4 bytes. |
--- |
| 8703 |
// TODO: Allow unordered atomics when wider type is legal (see D66309) |
--- |
8703 |
// TODO: Allow unordered atomics when wider type is legal (see D66309) |
--- |
| 8704 |
EVT MemVT = N->getMemoryVT(); |
0 |
8704 |
EVT MemVT = N->getMemoryVT(); |
0 |
| 8705 |
if (!(MemVT == MVT::i8 || MemVT == MVT::i16 || MemVT == MVT::i32) || |
0 |
8705 |
if (!(MemVT == MVT::i8 || MemVT == MVT::i16 || MemVT == MVT::i32) || |
0 |
| 8706 |
!N->isSimple() || N->isIndexed()) |
0 |
8706 |
!N->isSimple() || N->isIndexed()) |
0 |
| 8707 |
return SDValue(); |
0 |
8707 |
return SDValue(); |
0 |
| 8708 |
|
--- |
8708 |
|
--- |
| 8709 |
// Collect all of the stores in the chain, upto the maximum store width (i64). |
--- |
8709 |
// Collect all of the stores in the chain, upto the maximum store width (i64). |
--- |
| 8710 |
SDValue Chain = N->getChain(); |
0 |
8710 |
SDValue Chain = N->getChain(); |
0 |
| 8711 |
SmallVector Stores = {N}; |
0 |
8711 |
SmallVector Stores = {N}; |
0 |
| 8712 |
unsigned NarrowNumBits = MemVT.getScalarSizeInBits(); |
0 |
8712 |
unsigned NarrowNumBits = MemVT.getScalarSizeInBits(); |
0 |
| 8713 |
unsigned MaxWideNumBits = 64; |
0 |
8713 |
unsigned MaxWideNumBits = 64; |
0 |
| 8714 |
unsigned MaxStores = MaxWideNumBits / NarrowNumBits; |
0 |
8714 |
unsigned MaxStores = MaxWideNumBits / NarrowNumBits; |
0 |
| 8715 |
while (auto *Store = dyn_cast(Chain)) { |
0 |
8715 |
while (auto *Store = dyn_cast(Chain)) { |
0 |
| 8716 |
// All stores must be the same size to ensure that we are writing all of the |
--- |
8716 |
// All stores must be the same size to ensure that we are writing all of the |
--- |
| 8717 |
// bytes in the wide value. |
--- |
8717 |
// bytes in the wide value. |
--- |
| 8718 |
// This store should have exactly one use as a chain operand for another |
--- |
8718 |
// This store should have exactly one use as a chain operand for another |
--- |
| 8719 |
// store in the merging set. If there are other chain uses, then the |
--- |
8719 |
// store in the merging set. If there are other chain uses, then the |
--- |
| 8720 |
// transform may not be safe because order of loads/stores outside of this |
--- |
8720 |
// transform may not be safe because order of loads/stores outside of this |
--- |
| 8721 |
// set may not be preserved. |
--- |
8721 |
// set may not be preserved. |
--- |
| 8722 |
// TODO: We could allow multiple sizes by tracking each stored byte. |
--- |
8722 |
// TODO: We could allow multiple sizes by tracking each stored byte. |
--- |
| 8723 |
if (Store->getMemoryVT() != MemVT || !Store->isSimple() || |
0 |
8723 |
if (Store->getMemoryVT() != MemVT || !Store->isSimple() || |
0 |
| 8724 |
Store->isIndexed() || !Store->hasOneUse()) |
0 |
8724 |
Store->isIndexed() || !Store->hasOneUse()) |
0 |
| 8725 |
return SDValue(); |
0 |
8725 |
return SDValue(); |
0 |
| 8726 |
Stores.push_back(Store); |
0 |
8726 |
Stores.push_back(Store); |
0 |
| 8727 |
Chain = Store->getChain(); |
0 |
8727 |
Chain = Store->getChain(); |
0 |
| 8728 |
if (MaxStores < Stores.size()) |
0 |
8728 |
if (MaxStores < Stores.size()) |
0 |
| 8729 |
return SDValue(); |
0 |
8729 |
return SDValue(); |
0 |
| 8730 |
} |
0 |
8730 |
} |
0 |
| 8731 |
// There is no reason to continue if we do not have at least a pair of stores. |
--- |
8731 |
// There is no reason to continue if we do not have at least a pair of stores. |
--- |
| 8732 |
if (Stores.size() < 2) |
0 |
8732 |
if (Stores.size() < 2) |
0 |
| 8733 |
return SDValue(); |
0 |
8733 |
return SDValue(); |
0 |
| 8734 |
|
--- |
8734 |
|
--- |
| 8735 |
// Handle simple types only. |
--- |
8735 |
// Handle simple types only. |
--- |
| 8736 |
LLVMContext &Context = *DAG.getContext(); |
0 |
8736 |
LLVMContext &Context = *DAG.getContext(); |
0 |
| 8737 |
unsigned NumStores = Stores.size(); |
0 |
8737 |
unsigned NumStores = Stores.size(); |
0 |
| 8738 |
unsigned WideNumBits = NumStores * NarrowNumBits; |
0 |
8738 |
unsigned WideNumBits = NumStores * NarrowNumBits; |
0 |
| 8739 |
EVT WideVT = EVT::getIntegerVT(Context, WideNumBits); |
0 |
8739 |
EVT WideVT = EVT::getIntegerVT(Context, WideNumBits); |
0 |
| 8740 |
if (WideVT != MVT::i16 && WideVT != MVT::i32 && WideVT != MVT::i64) |
0 |
8740 |
if (WideVT != MVT::i16 && WideVT != MVT::i32 && WideVT != MVT::i64) |
0 |
| 8741 |
return SDValue(); |
0 |
8741 |
return SDValue(); |
0 |
| 8742 |
|
--- |
8742 |
|
--- |
| 8743 |
// Check if all bytes of the source value that we are looking at are stored |
--- |
8743 |
// Check if all bytes of the source value that we are looking at are stored |
--- |
| 8744 |
// to the same base address. Collect offsets from Base address into OffsetMap. |
--- |
8744 |
// to the same base address. Collect offsets from Base address into OffsetMap. |
--- |
| 8745 |
SDValue SourceValue; |
0 |
8745 |
SDValue SourceValue; |
0 |
| 8746 |
SmallVector OffsetMap(NumStores, INT64_MAX); |
0 |
8746 |
SmallVector OffsetMap(NumStores, INT64_MAX); |
0 |
| 8747 |
int64_t FirstOffset = INT64_MAX; |
0 |
8747 |
int64_t FirstOffset = INT64_MAX; |
0 |
| 8748 |
StoreSDNode *FirstStore = nullptr; |
0 |
8748 |
StoreSDNode *FirstStore = nullptr; |
0 |
| 8749 |
std::optional Base; |
0 |
8749 |
std::optional Base; |
0 |
| 8750 |
for (auto *Store : Stores) { |
0 |
8750 |
for (auto *Store : Stores) { |
0 |
| 8751 |
// All the stores store different parts of the CombinedValue. A truncate is |
--- |
8751 |
// All the stores store different parts of the CombinedValue. A truncate is |
--- |
| 8752 |
// required to get the partial value. |
--- |
8752 |
// required to get the partial value. |
--- |
| 8753 |
SDValue Trunc = Store->getValue(); |
0 |
8753 |
SDValue Trunc = Store->getValue(); |
0 |
| 8754 |
if (Trunc.getOpcode() != ISD::TRUNCATE) |
0 |
8754 |
if (Trunc.getOpcode() != ISD::TRUNCATE) |
0 |
| 8755 |
return SDValue(); |
0 |
8755 |
return SDValue(); |
0 |
| 8756 |
// Other than the first/last part, a shift operation is required to get the |
--- |
8756 |
// Other than the first/last part, a shift operation is required to get the |
--- |
| 8757 |
// offset. |
--- |
8757 |
// offset. |
--- |
| 8758 |
int64_t Offset = 0; |
0 |
8758 |
int64_t Offset = 0; |
0 |
| 8759 |
SDValue WideVal = Trunc.getOperand(0); |
0 |
8759 |
SDValue WideVal = Trunc.getOperand(0); |
0 |
| 8760 |
if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) && |
0 |
8760 |
if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) && |
0 |
| 8761 |
isa(WideVal.getOperand(1))) { |
0 |
8761 |
isa(WideVal.getOperand(1))) { |
0 |
| 8762 |
// The shift amount must be a constant multiple of the narrow type. |
--- |
8762 |
// The shift amount must be a constant multiple of the narrow type. |
--- |
| 8763 |
// It is translated to the offset address in the wide source value "y". |
--- |
8763 |
// It is translated to the offset address in the wide source value "y". |
--- |
| 8764 |
// |
--- |
8764 |
// |
--- |
| 8765 |
// x = srl y, ShiftAmtC |
--- |
8765 |
// x = srl y, ShiftAmtC |
--- |
| 8766 |
// i8 z = trunc x |
--- |
8766 |
// i8 z = trunc x |
--- |
| 8767 |
// store z, ... |
--- |
8767 |
// store z, ... |
--- |
| 8768 |
uint64_t ShiftAmtC = WideVal.getConstantOperandVal(1); |
0 |
8768 |
uint64_t ShiftAmtC = WideVal.getConstantOperandVal(1); |
0 |
| 8769 |
if (ShiftAmtC % NarrowNumBits != 0) |
0 |
8769 |
if (ShiftAmtC % NarrowNumBits != 0) |
0 |
| 8770 |
return SDValue(); |
0 |
8770 |
return SDValue(); |
0 |
| 8771 |
|
--- |
8771 |
|
--- |
| 8772 |
Offset = ShiftAmtC / NarrowNumBits; |
0 |
8772 |
Offset = ShiftAmtC / NarrowNumBits; |
0 |
| 8773 |
WideVal = WideVal.getOperand(0); |
0 |
8773 |
WideVal = WideVal.getOperand(0); |
0 |
| 8774 |
} |
--- |
8774 |
} |
--- |
| 8775 |
|
--- |
8775 |
|
--- |
| 8776 |
// Stores must share the same source value with different offsets. |
--- |
8776 |
// Stores must share the same source value with different offsets. |
--- |
| 8777 |
// Truncate and extends should be stripped to get the single source value. |
--- |
8777 |
// Truncate and extends should be stripped to get the single source value. |
--- |
| 8778 |
if (!SourceValue) |
0 |
8778 |
if (!SourceValue) |
0 |
| 8779 |
SourceValue = WideVal; |
0 |
8779 |
SourceValue = WideVal; |
0 |
| 8780 |
else if (stripTruncAndExt(SourceValue) != stripTruncAndExt(WideVal)) |
0 |
8780 |
else if (stripTruncAndExt(SourceValue) != stripTruncAndExt(WideVal)) |
0 |
| 8781 |
return SDValue(); |
0 |
8781 |
return SDValue(); |
0 |
| 8782 |
else if (SourceValue.getValueType() != WideVT) { |
0 |
8782 |
else if (SourceValue.getValueType() != WideVT) { |
0 |
| 8783 |
if (WideVal.getValueType() == WideVT || |
0 |
8783 |
if (WideVal.getValueType() == WideVT || |
0 |
| 8784 |
WideVal.getScalarValueSizeInBits() > |
0 |
8784 |
WideVal.getScalarValueSizeInBits() > |
0 |
| 8785 |
SourceValue.getScalarValueSizeInBits()) |
0 |
8785 |
SourceValue.getScalarValueSizeInBits()) |
0 |
| 8786 |
SourceValue = WideVal; |
0 |
8786 |
SourceValue = WideVal; |
0 |
| 8787 |
// Give up if the source value type is smaller than the store size. |
--- |
8787 |
// Give up if the source value type is smaller than the store size. |
--- |
| 8788 |
if (SourceValue.getScalarValueSizeInBits() < WideVT.getScalarSizeInBits()) |
0 |
8788 |
if (SourceValue.getScalarValueSizeInBits() < WideVT.getScalarSizeInBits()) |
0 |
| 8789 |
return SDValue(); |
0 |
8789 |
return SDValue(); |
0 |
| 8790 |
} |
--- |
8790 |
} |
--- |
| 8791 |
|
--- |
8791 |
|
--- |
| 8792 |
// Stores must share the same base address. |
--- |
8792 |
// Stores must share the same base address. |
--- |
| 8793 |
BaseIndexOffset Ptr = BaseIndexOffset::match(Store, DAG); |
0 |
8793 |
BaseIndexOffset Ptr = BaseIndexOffset::match(Store, DAG); |
0 |
| 8794 |
int64_t ByteOffsetFromBase = 0; |
0 |
8794 |
int64_t ByteOffsetFromBase = 0; |
0 |
| 8795 |
if (!Base) |
0 |
8795 |
if (!Base) |
0 |
| 8796 |
Base = Ptr; |
0 |
8796 |
Base = Ptr; |
0 |
| 8797 |
else if (!Base->equalBaseIndex(Ptr, DAG, ByteOffsetFromBase)) |
0 |
8797 |
else if (!Base->equalBaseIndex(Ptr, DAG, ByteOffsetFromBase)) |
0 |
| 8798 |
return SDValue(); |
0 |
8798 |
return SDValue(); |
0 |
| 8799 |
|
--- |
8799 |
|
--- |
| 8800 |
// Remember the first store. |
--- |
8800 |
// Remember the first store. |
--- |
| 8801 |
if (ByteOffsetFromBase < FirstOffset) { |
0 |
8801 |
if (ByteOffsetFromBase < FirstOffset) { |
0 |
| 8802 |
FirstStore = Store; |
0 |
8802 |
FirstStore = Store; |
0 |
| 8803 |
FirstOffset = ByteOffsetFromBase; |
0 |
8803 |
FirstOffset = ByteOffsetFromBase; |
0 |
| 8804 |
} |
--- |
8804 |
} |
--- |
| 8805 |
// Map the offset in the store and the offset in the combined value, and |
--- |
8805 |
// Map the offset in the store and the offset in the combined value, and |
--- |
| 8806 |
// early return if it has been set before. |
--- |
8806 |
// early return if it has been set before. |
--- |
| 8807 |
if (Offset < 0 || Offset >= NumStores || OffsetMap[Offset] != INT64_MAX) |
0 |
8807 |
if (Offset < 0 || Offset >= NumStores || OffsetMap[Offset] != INT64_MAX) |
0 |
| 8808 |
return SDValue(); |
0 |
8808 |
return SDValue(); |
0 |
| 8809 |
OffsetMap[Offset] = ByteOffsetFromBase; |
0 |
8809 |
OffsetMap[Offset] = ByteOffsetFromBase; |
0 |
| 8810 |
} |
--- |
8810 |
} |
--- |
| 8811 |
|
--- |
8811 |
|
--- |
| 8812 |
assert(FirstOffset != INT64_MAX && "First byte offset must be set"); |
0 |
8812 |
assert(FirstOffset != INT64_MAX && "First byte offset must be set"); |
0 |
| 8813 |
assert(FirstStore && "First store must be set"); |
0 |
8813 |
assert(FirstStore && "First store must be set"); |
0 |
| 8814 |
|
--- |
8814 |
|
--- |
| 8815 |
// Check that a store of the wide type is both allowed and fast on the target |
--- |
8815 |
// Check that a store of the wide type is both allowed and fast on the target |
--- |
| 8816 |
const DataLayout &Layout = DAG.getDataLayout(); |
0 |
8816 |
const DataLayout &Layout = DAG.getDataLayout(); |
0 |
| 8817 |
unsigned Fast = 0; |
0 |
8817 |
unsigned Fast = 0; |
0 |
| 8818 |
bool Allowed = TLI.allowsMemoryAccess(Context, Layout, WideVT, |
0 |
8818 |
bool Allowed = TLI.allowsMemoryAccess(Context, Layout, WideVT, |
0 |
| 8819 |
*FirstStore->getMemOperand(), &Fast); |
0 |
8819 |
*FirstStore->getMemOperand(), &Fast); |
0 |
| 8820 |
if (!Allowed || !Fast) |
0 |
8820 |
if (!Allowed || !Fast) |
0 |
| 8821 |
return SDValue(); |
0 |
8821 |
return SDValue(); |
0 |
| 8822 |
|
--- |
8822 |
|
--- |
| 8823 |
// Check if the pieces of the value are going to the expected places in memory |
--- |
8823 |
// Check if the pieces of the value are going to the expected places in memory |
--- |
| 8824 |
// to merge the stores. |
--- |
8824 |
// to merge the stores. |
--- |
| 8825 |
auto checkOffsets = [&](bool MatchLittleEndian) { |
0 |
8825 |
auto checkOffsets = [&](bool MatchLittleEndian) { |
0 |
| 8826 |
if (MatchLittleEndian) { |
0 |
8826 |
if (MatchLittleEndian) { |
0 |
| 8827 |
for (unsigned i = 0; i != NumStores; ++i) |
0 |
8827 |
for (unsigned i = 0; i != NumStores; ++i) |
0 |
| 8828 |
if (OffsetMap[i] != i * (NarrowNumBits / 8) + FirstOffset) |
0 |
8828 |
if (OffsetMap[i] != i * (NarrowNumBits / 8) + FirstOffset) |
0 |
| 8829 |
return false; |
0 |
8829 |
return false; |
0 |
| 8830 |
} else { // MatchBigEndian by reversing loop counter. |
--- |
8830 |
} else { // MatchBigEndian by reversing loop counter. |
--- |
| 8831 |
for (unsigned i = 0, j = NumStores - 1; i != NumStores; ++i, --j) |
0 |
8831 |
for (unsigned i = 0, j = NumStores - 1; i != NumStores; ++i, --j) |
0 |
| 8832 |
if (OffsetMap[j] != i * (NarrowNumBits / 8) + FirstOffset) |
0 |
8832 |
if (OffsetMap[j] != i * (NarrowNumBits / 8) + FirstOffset) |
0 |
| 8833 |
return false; |
0 |
8833 |
return false; |
0 |
| 8834 |
} |
--- |
8834 |
} |
--- |
| 8835 |
return true; |
0 |
8835 |
return true; |
0 |
| 8836 |
}; |
0 |
8836 |
}; |
0 |
| 8837 |
|
--- |
8837 |
|
--- |
| 8838 |
// Check if the offsets line up for the native data layout of this target. |
--- |
8838 |
// Check if the offsets line up for the native data layout of this target. |
--- |
| 8839 |
bool NeedBswap = false; |
0 |
8839 |
bool NeedBswap = false; |
0 |
| 8840 |
bool NeedRotate = false; |
0 |
8840 |
bool NeedRotate = false; |
0 |
| 8841 |
if (!checkOffsets(Layout.isLittleEndian())) { |
0 |
8841 |
if (!checkOffsets(Layout.isLittleEndian())) { |
0 |
| 8842 |
// Special-case: check if byte offsets line up for the opposite endian. |
--- |
8842 |
// Special-case: check if byte offsets line up for the opposite endian. |
--- |
| 8843 |
if (NarrowNumBits == 8 && checkOffsets(Layout.isBigEndian())) |
0 |
8843 |
if (NarrowNumBits == 8 && checkOffsets(Layout.isBigEndian())) |
0 |
| 8844 |
NeedBswap = true; |
0 |
8844 |
NeedBswap = true; |
0 |
| 8845 |
else if (NumStores == 2 && checkOffsets(Layout.isBigEndian())) |
0 |
8845 |
else if (NumStores == 2 && checkOffsets(Layout.isBigEndian())) |
0 |
| 8846 |
NeedRotate = true; |
0 |
8846 |
NeedRotate = true; |
0 |
| 8847 |
else |
--- |
8847 |
else |
--- |
| 8848 |
return SDValue(); |
0 |
8848 |
return SDValue(); |
0 |
| 8849 |
} |
--- |
8849 |
} |
--- |
| 8850 |
|
--- |
8850 |
|
--- |
| 8851 |
SDLoc DL(N); |
0 |
8851 |
SDLoc DL(N); |
0 |
| 8852 |
if (WideVT != SourceValue.getValueType()) { |
0 |
8852 |
if (WideVT != SourceValue.getValueType()) { |
0 |
| 8853 |
assert(SourceValue.getValueType().getScalarSizeInBits() > WideNumBits && |
0 |
8853 |
assert(SourceValue.getValueType().getScalarSizeInBits() > WideNumBits && |
0 |
| 8854 |
"Unexpected store value to merge"); |
--- |
8854 |
"Unexpected store value to merge"); |
--- |
| 8855 |
SourceValue = DAG.getNode(ISD::TRUNCATE, DL, WideVT, SourceValue); |
0 |
8855 |
SourceValue = DAG.getNode(ISD::TRUNCATE, DL, WideVT, SourceValue); |
0 |
| 8856 |
} |
--- |
8856 |
} |
--- |
| 8857 |
|
--- |
8857 |
|
--- |
| 8858 |
// Before legalize we can introduce illegal bswaps/rotates which will be later |
--- |
8858 |
// Before legalize we can introduce illegal bswaps/rotates which will be later |
--- |
| 8859 |
// converted to an explicit bswap sequence. This way we end up with a single |
--- |
8859 |
// converted to an explicit bswap sequence. This way we end up with a single |
--- |
| 8860 |
// store and byte shuffling instead of several stores and byte shuffling. |
--- |
8860 |
// store and byte shuffling instead of several stores and byte shuffling. |
--- |
| 8861 |
if (NeedBswap) { |
0 |
8861 |
if (NeedBswap) { |
0 |
| 8862 |
SourceValue = DAG.getNode(ISD::BSWAP, DL, WideVT, SourceValue); |
0 |
8862 |
SourceValue = DAG.getNode(ISD::BSWAP, DL, WideVT, SourceValue); |
0 |
| 8863 |
} else if (NeedRotate) { |
0 |
8863 |
} else if (NeedRotate) { |
0 |
| 8864 |
assert(WideNumBits % 2 == 0 && "Unexpected type for rotate"); |
0 |
8864 |
assert(WideNumBits % 2 == 0 && "Unexpected type for rotate"); |
0 |
| 8865 |
SDValue RotAmt = DAG.getConstant(WideNumBits / 2, DL, WideVT); |
0 |
8865 |
SDValue RotAmt = DAG.getConstant(WideNumBits / 2, DL, WideVT); |
0 |
| 8866 |
SourceValue = DAG.getNode(ISD::ROTR, DL, WideVT, SourceValue, RotAmt); |
0 |
8866 |
SourceValue = DAG.getNode(ISD::ROTR, DL, WideVT, SourceValue, RotAmt); |
0 |
| 8867 |
} |
--- |
8867 |
} |
--- |
| 8868 |
|
--- |
8868 |
|
--- |
| 8869 |
SDValue NewStore = |
--- |
8869 |
SDValue NewStore = |
--- |
| 8870 |
DAG.getStore(Chain, DL, SourceValue, FirstStore->getBasePtr(), |
0 |
8870 |
DAG.getStore(Chain, DL, SourceValue, FirstStore->getBasePtr(), |
0 |
| 8871 |
FirstStore->getPointerInfo(), FirstStore->getAlign()); |
0 |
8871 |
FirstStore->getPointerInfo(), FirstStore->getAlign()); |
0 |
| 8872 |
|
--- |
8872 |
|
--- |
| 8873 |
// Rely on other DAG combine rules to remove the other individual stores. |
--- |
8873 |
// Rely on other DAG combine rules to remove the other individual stores. |
--- |
| 8874 |
DAG.ReplaceAllUsesWith(N, NewStore.getNode()); |
0 |
8874 |
DAG.ReplaceAllUsesWith(N, NewStore.getNode()); |
0 |
| 8875 |
return NewStore; |
0 |
8875 |
return NewStore; |
0 |
| 8876 |
} |
0 |
8876 |
} |
0 |
| 8877 |
|
--- |
8877 |
|
--- |
| 8878 |
/// Match a pattern where a wide type scalar value is loaded by several narrow |
--- |
8878 |
/// Match a pattern where a wide type scalar value is loaded by several narrow |
--- |
| 8879 |
/// loads and combined by shifts and ors. Fold it into a single load or a load |
--- |
8879 |
/// loads and combined by shifts and ors. Fold it into a single load or a load |
--- |
| 8880 |
/// and a BSWAP if the targets supports it. |
--- |
8880 |
/// and a BSWAP if the targets supports it. |
--- |
| 8881 |
/// |
--- |
8881 |
/// |
--- |
| 8882 |
/// Assuming little endian target: |
--- |
8882 |
/// Assuming little endian target: |
--- |
| 8883 |
/// i8 *a = ... |
--- |
8883 |
/// i8 *a = ... |
--- |
| 8884 |
/// i32 val = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24) |
--- |
8884 |
/// i32 val = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24) |
--- |
| 8885 |
/// => |
--- |
8885 |
/// => |
--- |
| 8886 |
/// i32 val = *((i32)a) |
--- |
8886 |
/// i32 val = *((i32)a) |
--- |
| 8887 |
/// |
--- |
8887 |
/// |
--- |
| 8888 |
/// i8 *a = ... |
--- |
8888 |
/// i8 *a = ... |
--- |
| 8889 |
/// i32 val = (a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3] |
--- |
8889 |
/// i32 val = (a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3] |
--- |
| 8890 |
/// => |
--- |
8890 |
/// => |
--- |
| 8891 |
/// i32 val = BSWAP(*((i32)a)) |
--- |
8891 |
/// i32 val = BSWAP(*((i32)a)) |
--- |
| 8892 |
/// |
--- |
8892 |
/// |
--- |
| 8893 |
/// TODO: This rule matches complex patterns with OR node roots and doesn't |
--- |
8893 |
/// TODO: This rule matches complex patterns with OR node roots and doesn't |
--- |
| 8894 |
/// interact well with the worklist mechanism. When a part of the pattern is |
--- |
8894 |
/// interact well with the worklist mechanism. When a part of the pattern is |
--- |
| 8895 |
/// updated (e.g. one of the loads) its direct users are put into the worklist, |
--- |
8895 |
/// updated (e.g. one of the loads) its direct users are put into the worklist, |
--- |
| 8896 |
/// but the root node of the pattern which triggers the load combine is not |
--- |
8896 |
/// but the root node of the pattern which triggers the load combine is not |
--- |
| 8897 |
/// necessarily a direct user of the changed node. For example, once the address |
--- |
8897 |
/// necessarily a direct user of the changed node. For example, once the address |
--- |
| 8898 |
/// of t28 load is reassociated load combine won't be triggered: |
--- |
8898 |
/// of t28 load is reassociated load combine won't be triggered: |
--- |
| 8899 |
/// t25: i32 = add t4, Constant:i32<2> |
--- |
8899 |
/// t25: i32 = add t4, Constant:i32<2> |
--- |
| 8900 |
/// t26: i64 = sign_extend t25 |
--- |
8900 |
/// t26: i64 = sign_extend t25 |
--- |
| 8901 |
/// t27: i64 = add t2, t26 |
--- |
8901 |
/// t27: i64 = add t2, t26 |
--- |
| 8902 |
/// t28: i8,ch = load t0, t27, undef:i64 |
--- |
8902 |
/// t28: i8,ch = load t0, t27, undef:i64 |
--- |
| 8903 |
/// t29: i32 = zero_extend t28 |
--- |
8903 |
/// t29: i32 = zero_extend t28 |
--- |
| 8904 |
/// t32: i32 = shl t29, Constant:i8<8> |
--- |
8904 |
/// t32: i32 = shl t29, Constant:i8<8> |
--- |
| 8905 |
/// t33: i32 = or t23, t32 |
--- |
8905 |
/// t33: i32 = or t23, t32 |
--- |
| 8906 |
/// As a possible fix visitLoad can check if the load can be a part of a load |
--- |
8906 |
/// As a possible fix visitLoad can check if the load can be a part of a load |
--- |
| 8907 |
/// combine pattern and add corresponding OR roots to the worklist. |
--- |
8907 |
/// combine pattern and add corresponding OR roots to the worklist. |
--- |
| 8908 |
SDValue DAGCombiner::MatchLoadCombine(SDNode *N) { |
0 |
8908 |
SDValue DAGCombiner::MatchLoadCombine(SDNode *N) { |
0 |
| 8909 |
assert(N->getOpcode() == ISD::OR && |
0 |
8909 |
assert(N->getOpcode() == ISD::OR && |
0 |
| 8910 |
"Can only match load combining against OR nodes"); |
--- |
8910 |
"Can only match load combining against OR nodes"); |
--- |
| 8911 |
|
--- |
8911 |
|
--- |
| 8912 |
// Handles simple types only |
--- |
8912 |
// Handles simple types only |
--- |
| 8913 |
EVT VT = N->getValueType(0); |
0 |
8913 |
EVT VT = N->getValueType(0); |
0 |
| 8914 |
if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) |
0 |
8914 |
if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) |
0 |
| 8915 |
return SDValue(); |
0 |
8915 |
return SDValue(); |
0 |
| 8916 |
unsigned ByteWidth = VT.getSizeInBits() / 8; |
0 |
8916 |
unsigned ByteWidth = VT.getSizeInBits() / 8; |
0 |
| 8917 |
|
--- |
8917 |
|
--- |
| 8918 |
bool IsBigEndianTarget = DAG.getDataLayout().isBigEndian(); |
0 |
8918 |
bool IsBigEndianTarget = DAG.getDataLayout().isBigEndian(); |
0 |
| 8919 |
auto MemoryByteOffset = [&](SDByteProvider P) { |
0 |
8919 |
auto MemoryByteOffset = [&](SDByteProvider P) { |
0 |
| 8920 |
assert(P.hasSrc() && "Must be a memory byte provider"); |
0 |
8920 |
assert(P.hasSrc() && "Must be a memory byte provider"); |
0 |
| 8921 |
auto *Load = cast(P.Src.value()); |
0 |
8921 |
auto *Load = cast(P.Src.value()); |
0 |
| 8922 |
|
--- |
8922 |
|
--- |
| 8923 |
unsigned LoadBitWidth = Load->getMemoryVT().getScalarSizeInBits(); |
0 |
8923 |
unsigned LoadBitWidth = Load->getMemoryVT().getScalarSizeInBits(); |
0 |
| 8924 |
|
--- |
8924 |
|
--- |
| 8925 |
assert(LoadBitWidth % 8 == 0 && |
0 |
8925 |
assert(LoadBitWidth % 8 == 0 && |
0 |
| 8926 |
"can only analyze providers for individual bytes not bit"); |
--- |
8926 |
"can only analyze providers for individual bytes not bit"); |
--- |
| 8927 |
unsigned LoadByteWidth = LoadBitWidth / 8; |
0 |
8927 |
unsigned LoadByteWidth = LoadBitWidth / 8; |
0 |
| 8928 |
return IsBigEndianTarget ? bigEndianByteAt(LoadByteWidth, P.DestOffset) |
0 |
8928 |
return IsBigEndianTarget ? bigEndianByteAt(LoadByteWidth, P.DestOffset) |
0 |
| 8929 |
: littleEndianByteAt(LoadByteWidth, P.DestOffset); |
0 |
8929 |
: littleEndianByteAt(LoadByteWidth, P.DestOffset); |
0 |
| 8930 |
}; |
0 |
8930 |
}; |
0 |
| 8931 |
|
--- |
8931 |
|
--- |
| 8932 |
std::optional Base; |
0 |
8932 |
std::optional Base; |
0 |
| 8933 |
SDValue Chain; |
0 |
8933 |
SDValue Chain; |
0 |
| 8934 |
|
--- |
8934 |
|
--- |
| 8935 |
SmallPtrSet Loads; |
0 |
8935 |
SmallPtrSet Loads; |
0 |
| 8936 |
std::optional FirstByteProvider; |
0 |
8936 |
std::optional FirstByteProvider; |
0 |
| 8937 |
int64_t FirstOffset = INT64_MAX; |
0 |
8937 |
int64_t FirstOffset = INT64_MAX; |
0 |
| 8938 |
|
--- |
8938 |
|
--- |
| 8939 |
// Check if all the bytes of the OR we are looking at are loaded from the same |
--- |
8939 |
// Check if all the bytes of the OR we are looking at are loaded from the same |
--- |
| 8940 |
// base address. Collect bytes offsets from Base address in ByteOffsets. |
--- |
8940 |
// base address. Collect bytes offsets from Base address in ByteOffsets. |
--- |
| 8941 |
SmallVector ByteOffsets(ByteWidth); |
0 |
8941 |
SmallVector ByteOffsets(ByteWidth); |
0 |
| 8942 |
unsigned ZeroExtendedBytes = 0; |
0 |
8942 |
unsigned ZeroExtendedBytes = 0; |
0 |
| 8943 |
for (int i = ByteWidth - 1; i >= 0; --i) { |
0 |
8943 |
for (int i = ByteWidth - 1; i >= 0; --i) { |
0 |
| 8944 |
auto P = |
--- |
8944 |
auto P = |
--- |
| 8945 |
calculateByteProvider(SDValue(N, 0), i, 0, /*VectorIndex*/ std::nullopt, |
0 |
8945 |
calculateByteProvider(SDValue(N, 0), i, 0, /*VectorIndex*/ std::nullopt, |
0 |
| 8946 |
/*StartingIndex*/ i); |
--- |
8946 |
/*StartingIndex*/ i); |
--- |
| 8947 |
if (!P) |
0 |
8947 |
if (!P) |
0 |
| 8948 |
return SDValue(); |
0 |
8948 |
return SDValue(); |
0 |
| 8949 |
|
--- |
8949 |
|
--- |
| 8950 |
if (P->isConstantZero()) { |
0 |
8950 |
if (P->isConstantZero()) { |
0 |
| 8951 |
// It's OK for the N most significant bytes to be 0, we can just |
--- |
8951 |
// It's OK for the N most significant bytes to be 0, we can just |
--- |
| 8952 |
// zero-extend the load. |
--- |
8952 |
// zero-extend the load. |
--- |
| 8953 |
if (++ZeroExtendedBytes != (ByteWidth - static_cast(i))) |
0 |
8953 |
if (++ZeroExtendedBytes != (ByteWidth - static_cast(i))) |
0 |
| 8954 |
return SDValue(); |
0 |
8954 |
return SDValue(); |
0 |
| 8955 |
continue; |
0 |
8955 |
continue; |
0 |
| 8956 |
} |
--- |
8956 |
} |
--- |
| 8957 |
assert(P->hasSrc() && "provenance should either be memory or zero"); |
0 |
8957 |
assert(P->hasSrc() && "provenance should either be memory or zero"); |
0 |
| 8958 |
auto *L = cast(P->Src.value()); |
0 |
8958 |
auto *L = cast(P->Src.value()); |
0 |
| 8959 |
|
--- |
8959 |
|
--- |
| 8960 |
// All loads must share the same chain |
--- |
8960 |
// All loads must share the same chain |
--- |
| 8961 |
SDValue LChain = L->getChain(); |
0 |
8961 |
SDValue LChain = L->getChain(); |
0 |
| 8962 |
if (!Chain) |
0 |
8962 |
if (!Chain) |
0 |
| 8963 |
Chain = LChain; |
0 |
8963 |
Chain = LChain; |
0 |
| 8964 |
else if (Chain != LChain) |
0 |
8964 |
else if (Chain != LChain) |
0 |
| 8965 |
return SDValue(); |
0 |
8965 |
return SDValue(); |
0 |
| 8966 |
|
--- |
8966 |
|
--- |
| 8967 |
// Loads must share the same base address |
--- |
8967 |
// Loads must share the same base address |
--- |
| 8968 |
BaseIndexOffset Ptr = BaseIndexOffset::match(L, DAG); |
0 |
8968 |
BaseIndexOffset Ptr = BaseIndexOffset::match(L, DAG); |
0 |
| 8969 |
int64_t ByteOffsetFromBase = 0; |
0 |
8969 |
int64_t ByteOffsetFromBase = 0; |
0 |
| 8970 |
|
--- |
8970 |
|
--- |
| 8971 |
// For vector loads, the expected load combine pattern will have an |
--- |
8971 |
// For vector loads, the expected load combine pattern will have an |
--- |
| 8972 |
// ExtractElement for each index in the vector. While each of these |
--- |
8972 |
// ExtractElement for each index in the vector. While each of these |
--- |
| 8973 |
// ExtractElements will be accessing the same base address as determined |
--- |
8973 |
// ExtractElements will be accessing the same base address as determined |
--- |
| 8974 |
// by the load instruction, the actual bytes they interact with will differ |
--- |
8974 |
// by the load instruction, the actual bytes they interact with will differ |
--- |
| 8975 |
// due to different ExtractElement indices. To accurately determine the |
--- |
8975 |
// due to different ExtractElement indices. To accurately determine the |
--- |
| 8976 |
// byte position of an ExtractElement, we offset the base load ptr with |
--- |
8976 |
// byte position of an ExtractElement, we offset the base load ptr with |
--- |
| 8977 |
// the index multiplied by the byte size of each element in the vector. |
--- |
8977 |
// the index multiplied by the byte size of each element in the vector. |
--- |
| 8978 |
if (L->getMemoryVT().isVector()) { |
0 |
8978 |
if (L->getMemoryVT().isVector()) { |
0 |
| 8979 |
unsigned LoadWidthInBit = L->getMemoryVT().getScalarSizeInBits(); |
0 |
8979 |
unsigned LoadWidthInBit = L->getMemoryVT().getScalarSizeInBits(); |
0 |
| 8980 |
if (LoadWidthInBit % 8 != 0) |
0 |
8980 |
if (LoadWidthInBit % 8 != 0) |
0 |
| 8981 |
return SDValue(); |
0 |
8981 |
return SDValue(); |
0 |
| 8982 |
unsigned ByteOffsetFromVector = P->SrcOffset * LoadWidthInBit / 8; |
0 |
8982 |
unsigned ByteOffsetFromVector = P->SrcOffset * LoadWidthInBit / 8; |
0 |
| 8983 |
Ptr.addToOffset(ByteOffsetFromVector); |
0 |
8983 |
Ptr.addToOffset(ByteOffsetFromVector); |
0 |
| 8984 |
} |
--- |
8984 |
} |
--- |
| 8985 |
|
--- |
8985 |
|
--- |
| 8986 |
if (!Base) |
0 |
8986 |
if (!Base) |
0 |
| 8987 |
Base = Ptr; |
0 |
8987 |
Base = Ptr; |
0 |
| 8988 |
|
--- |
8988 |
|
--- |
| 8989 |
else if (!Base->equalBaseIndex(Ptr, DAG, ByteOffsetFromBase)) |
0 |
8989 |
else if (!Base->equalBaseIndex(Ptr, DAG, ByteOffsetFromBase)) |
0 |
| 8990 |
return SDValue(); |
0 |
8990 |
return SDValue(); |
0 |
| 8991 |
|
--- |
8991 |
|
--- |
| 8992 |
// Calculate the offset of the current byte from the base address |
--- |
8992 |
// Calculate the offset of the current byte from the base address |
--- |
| 8993 |
ByteOffsetFromBase += MemoryByteOffset(*P); |
0 |
8993 |
ByteOffsetFromBase += MemoryByteOffset(*P); |
0 |
| 8994 |
ByteOffsets[i] = ByteOffsetFromBase; |
0 |
8994 |
ByteOffsets[i] = ByteOffsetFromBase; |
0 |
| 8995 |
|
--- |
8995 |
|
--- |
| 8996 |
// Remember the first byte load |
--- |
8996 |
// Remember the first byte load |
--- |
| 8997 |
if (ByteOffsetFromBase < FirstOffset) { |
0 |
8997 |
if (ByteOffsetFromBase < FirstOffset) { |
0 |
| 8998 |
FirstByteProvider = P; |
0 |
8998 |
FirstByteProvider = P; |
0 |
| 8999 |
FirstOffset = ByteOffsetFromBase; |
0 |
8999 |
FirstOffset = ByteOffsetFromBase; |
0 |
| 9000 |
} |
--- |
9000 |
} |
--- |
| 9001 |
|
--- |
9001 |
|
--- |
| 9002 |
Loads.insert(L); |
0 |
9002 |
Loads.insert(L); |
0 |
| 9003 |
} |
--- |
9003 |
} |
--- |
| 9004 |
|
--- |
9004 |
|
--- |
| 9005 |
assert(!Loads.empty() && "All the bytes of the value must be loaded from " |
0 |
9005 |
assert(!Loads.empty() && "All the bytes of the value must be loaded from " |
0 |
| 9006 |
"memory, so there must be at least one load which produces the value"); |
--- |
9006 |
"memory, so there must be at least one load which produces the value"); |
--- |
| 9007 |
assert(Base && "Base address of the accessed memory location must be set"); |
0 |
9007 |
assert(Base && "Base address of the accessed memory location must be set"); |
0 |
| 9008 |
assert(FirstOffset != INT64_MAX && "First byte offset must be set"); |
0 |
9008 |
assert(FirstOffset != INT64_MAX && "First byte offset must be set"); |
0 |
| 9009 |
|
--- |
9009 |
|
--- |
| 9010 |
bool NeedsZext = ZeroExtendedBytes > 0; |
0 |
9010 |
bool NeedsZext = ZeroExtendedBytes > 0; |
0 |
| 9011 |
|
--- |
9011 |
|
--- |
| 9012 |
EVT MemVT = |
--- |
9012 |
EVT MemVT = |
--- |
| 9013 |
EVT::getIntegerVT(*DAG.getContext(), (ByteWidth - ZeroExtendedBytes) * 8); |
0 |
9013 |
EVT::getIntegerVT(*DAG.getContext(), (ByteWidth - ZeroExtendedBytes) * 8); |
0 |
| 9014 |
|
--- |
9014 |
|
--- |
| 9015 |
if (!MemVT.isSimple()) |
0 |
9015 |
if (!MemVT.isSimple()) |
0 |
| 9016 |
return SDValue(); |
0 |
9016 |
return SDValue(); |
0 |
| 9017 |
|
--- |
9017 |
|
--- |
| 9018 |
// Before legalize we can introduce too wide illegal loads which will be later |
--- |
9018 |
// Before legalize we can introduce too wide illegal loads which will be later |
--- |
| 9019 |
// split into legal sized loads. This enables us to combine i64 load by i8 |
--- |
9019 |
// split into legal sized loads. This enables us to combine i64 load by i8 |
--- |
| 9020 |
// patterns to a couple of i32 loads on 32 bit targets. |
--- |
9020 |
// patterns to a couple of i32 loads on 32 bit targets. |
--- |
| 9021 |
if (LegalOperations && |
0 |
9021 |
if (LegalOperations && |
0 |
| 9022 |
!TLI.isOperationLegal(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD, |
0 |
9022 |
!TLI.isOperationLegal(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD, |
0 |
| 9023 |
MemVT)) |
--- |
9023 |
MemVT)) |
--- |
| 9024 |
return SDValue(); |
0 |
9024 |
return SDValue(); |
0 |
| 9025 |
|
--- |
9025 |
|
--- |
| 9026 |
// Check if the bytes of the OR we are looking at match with either big or |
--- |
9026 |
// Check if the bytes of the OR we are looking at match with either big or |
--- |
| 9027 |
// little endian value load |
--- |
9027 |
// little endian value load |
--- |
| 9028 |
std::optional IsBigEndian = isBigEndian( |
0 |
9028 |
std::optional IsBigEndian = isBigEndian( |
0 |
| 9029 |
ArrayRef(ByteOffsets).drop_back(ZeroExtendedBytes), FirstOffset); |
0 |
9029 |
ArrayRef(ByteOffsets).drop_back(ZeroExtendedBytes), FirstOffset); |
0 |
| 9030 |
if (!IsBigEndian) |
0 |
9030 |
if (!IsBigEndian) |
0 |
| 9031 |
return SDValue(); |
0 |
9031 |
return SDValue(); |
0 |
| 9032 |
|
--- |
9032 |
|
--- |
| 9033 |
assert(FirstByteProvider && "must be set"); |
0 |
9033 |
assert(FirstByteProvider && "must be set"); |
0 |
| 9034 |
|
--- |
9034 |
|
--- |
| 9035 |
// Ensure that the first byte is loaded from zero offset of the first load. |
--- |
9035 |
// Ensure that the first byte is loaded from zero offset of the first load. |
--- |
| 9036 |
// So the combined value can be loaded from the first load address. |
--- |
9036 |
// So the combined value can be loaded from the first load address. |
--- |
| 9037 |
if (MemoryByteOffset(*FirstByteProvider) != 0) |
0 |
9037 |
if (MemoryByteOffset(*FirstByteProvider) != 0) |
0 |
| 9038 |
return SDValue(); |
0 |
9038 |
return SDValue(); |
0 |
| 9039 |
auto *FirstLoad = cast(FirstByteProvider->Src.value()); |
0 |
9039 |
auto *FirstLoad = cast(FirstByteProvider->Src.value()); |
0 |
| 9040 |
|
--- |
9040 |
|
--- |
| 9041 |
// The node we are looking at matches with the pattern, check if we can |
--- |
9041 |
// The node we are looking at matches with the pattern, check if we can |
--- |
| 9042 |
// replace it with a single (possibly zero-extended) load and bswap + shift if |
--- |
9042 |
// replace it with a single (possibly zero-extended) load and bswap + shift if |
--- |
| 9043 |
// needed. |
--- |
9043 |
// needed. |
--- |
| 9044 |
|
--- |
9044 |
|
--- |
| 9045 |
// If the load needs byte swap check if the target supports it |
--- |
9045 |
// If the load needs byte swap check if the target supports it |
--- |
| 9046 |
bool NeedsBswap = IsBigEndianTarget != *IsBigEndian; |
0 |
9046 |
bool NeedsBswap = IsBigEndianTarget != *IsBigEndian; |
0 |
| 9047 |
|
--- |
9047 |
|
--- |
| 9048 |
// Before legalize we can introduce illegal bswaps which will be later |
--- |
9048 |
// Before legalize we can introduce illegal bswaps which will be later |
--- |
| 9049 |
// converted to an explicit bswap sequence. This way we end up with a single |
--- |
9049 |
// converted to an explicit bswap sequence. This way we end up with a single |
--- |
| 9050 |
// load and byte shuffling instead of several loads and byte shuffling. |
--- |
9050 |
// load and byte shuffling instead of several loads and byte shuffling. |
--- |
| 9051 |
// We do not introduce illegal bswaps when zero-extending as this tends to |
--- |
9051 |
// We do not introduce illegal bswaps when zero-extending as this tends to |
--- |
| 9052 |
// introduce too many arithmetic instructions. |
--- |
9052 |
// introduce too many arithmetic instructions. |
--- |
| 9053 |
if (NeedsBswap && (LegalOperations || NeedsZext) && |
0 |
9053 |
if (NeedsBswap && (LegalOperations || NeedsZext) && |
0 |
| 9054 |
!TLI.isOperationLegal(ISD::BSWAP, VT)) |
0 |
9054 |
!TLI.isOperationLegal(ISD::BSWAP, VT)) |
0 |
| 9055 |
return SDValue(); |
0 |
9055 |
return SDValue(); |
0 |
| 9056 |
|
--- |
9056 |
|
--- |
| 9057 |
// If we need to bswap and zero extend, we have to insert a shift. Check that |
--- |
9057 |
// If we need to bswap and zero extend, we have to insert a shift. Check that |
--- |
| 9058 |
// it is legal. |
--- |
9058 |
// it is legal. |
--- |
| 9059 |
if (NeedsBswap && NeedsZext && LegalOperations && |
0 |
9059 |
if (NeedsBswap && NeedsZext && LegalOperations && |
0 |
| 9060 |
!TLI.isOperationLegal(ISD::SHL, VT)) |
0 |
9060 |
!TLI.isOperationLegal(ISD::SHL, VT)) |
0 |
| 9061 |
return SDValue(); |
0 |
9061 |
return SDValue(); |
0 |
| 9062 |
|
--- |
9062 |
|
--- |
| 9063 |
// Check that a load of the wide type is both allowed and fast on the target |
--- |
9063 |
// Check that a load of the wide type is both allowed and fast on the target |
--- |
| 9064 |
unsigned Fast = 0; |
0 |
9064 |
unsigned Fast = 0; |
0 |
| 9065 |
bool Allowed = |
--- |
9065 |
bool Allowed = |
--- |
| 9066 |
TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT, |
0 |
9066 |
TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT, |
0 |
| 9067 |
*FirstLoad->getMemOperand(), &Fast); |
0 |
9067 |
*FirstLoad->getMemOperand(), &Fast); |
0 |
| 9068 |
if (!Allowed || !Fast) |
0 |
9068 |
if (!Allowed || !Fast) |
0 |
| 9069 |
return SDValue(); |
0 |
9069 |
return SDValue(); |
0 |
| 9070 |
|
--- |
9070 |
|
--- |
| 9071 |
SDValue NewLoad = |
--- |
9071 |
SDValue NewLoad = |
--- |
| 9072 |
DAG.getExtLoad(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD, SDLoc(N), VT, |
0 |
9072 |
DAG.getExtLoad(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD, SDLoc(N), VT, |
0 |
| 9073 |
Chain, FirstLoad->getBasePtr(), |
0 |
9073 |
Chain, FirstLoad->getBasePtr(), |
0 |
| 9074 |
FirstLoad->getPointerInfo(), MemVT, FirstLoad->getAlign()); |
0 |
9074 |
FirstLoad->getPointerInfo(), MemVT, FirstLoad->getAlign()); |
0 |
| 9075 |
|
--- |
9075 |
|
--- |
| 9076 |
// Transfer chain users from old loads to the new load. |
--- |
9076 |
// Transfer chain users from old loads to the new load. |
--- |
| 9077 |
for (LoadSDNode *L : Loads) |
0 |
9077 |
for (LoadSDNode *L : Loads) |
0 |
| 9078 |
DAG.ReplaceAllUsesOfValueWith(SDValue(L, 1), SDValue(NewLoad.getNode(), 1)); |
0 |
9078 |
DAG.ReplaceAllUsesOfValueWith(SDValue(L, 1), SDValue(NewLoad.getNode(), 1)); |
0 |
| 9079 |
|
--- |
9079 |
|
--- |
| 9080 |
if (!NeedsBswap) |
0 |
9080 |
if (!NeedsBswap) |
0 |
| 9081 |
return NewLoad; |
0 |
9081 |
return NewLoad; |
0 |
| 9082 |
|
--- |
9082 |
|
--- |
| 9083 |
SDValue ShiftedLoad = |
--- |
9083 |
SDValue ShiftedLoad = |
--- |
| 9084 |
NeedsZext |
--- |
9084 |
NeedsZext |
--- |
| 9085 |
? DAG.getNode(ISD::SHL, SDLoc(N), VT, NewLoad, |
0 |
9085 |
? DAG.getNode(ISD::SHL, SDLoc(N), VT, NewLoad, |
0 |
| 9086 |
DAG.getShiftAmountConstant(ZeroExtendedBytes * 8, VT, |
0 |
9086 |
DAG.getShiftAmountConstant(ZeroExtendedBytes * 8, VT, |
0 |
| 9087 |
SDLoc(N), LegalOperations)) |
0 |
9087 |
SDLoc(N), LegalOperations)) |
0 |
| 9088 |
: NewLoad; |
0 |
9088 |
: NewLoad; |
0 |
| 9089 |
return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, ShiftedLoad); |
0 |
9089 |
return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, ShiftedLoad); |
0 |
| 9090 |
} |
0 |
9090 |
} |
0 |
| 9091 |
|
--- |
9091 |
|
--- |
| 9092 |
// If the target has andn, bsl, or a similar bit-select instruction, |
--- |
9092 |
// If the target has andn, bsl, or a similar bit-select instruction, |
--- |
| 9093 |
// we want to unfold masked merge, with canonical pattern of: |
--- |
9093 |
// we want to unfold masked merge, with canonical pattern of: |
--- |
| 9094 |
// | A | |B| |
--- |
9094 |
// | A | |B| |
--- |
| 9095 |
// ((x ^ y) & m) ^ y |
--- |
9095 |
// ((x ^ y) & m) ^ y |
--- |
| 9096 |
// | D | |
--- |
9096 |
// | D | |
--- |
| 9097 |
// Into: |
--- |
9097 |
// Into: |
--- |
| 9098 |
// (x & m) | (y & ~m) |
--- |
9098 |
// (x & m) | (y & ~m) |
--- |
| 9099 |
// If y is a constant, m is not a 'not', and the 'andn' does not work with |
--- |
9099 |
// If y is a constant, m is not a 'not', and the 'andn' does not work with |
--- |
| 9100 |
// immediates, we unfold into a different pattern: |
--- |
9100 |
// immediates, we unfold into a different pattern: |
--- |
| 9101 |
// ~(~x & m) & (m | y) |
--- |
9101 |
// ~(~x & m) & (m | y) |
--- |
| 9102 |
// If x is a constant, m is a 'not', and the 'andn' does not work with |
--- |
9102 |
// If x is a constant, m is a 'not', and the 'andn' does not work with |
--- |
| 9103 |
// immediates, we unfold into a different pattern: |
--- |
9103 |
// immediates, we unfold into a different pattern: |
--- |
| 9104 |
// (x | ~m) & ~(~m & ~y) |
--- |
9104 |
// (x | ~m) & ~(~m & ~y) |
--- |
| 9105 |
// NOTE: we don't unfold the pattern if 'xor' is actually a 'not', because at |
--- |
9105 |
// NOTE: we don't unfold the pattern if 'xor' is actually a 'not', because at |
--- |
| 9106 |
// the very least that breaks andnpd / andnps patterns, and because those |
--- |
9106 |
// the very least that breaks andnpd / andnps patterns, and because those |
--- |
| 9107 |
// patterns are simplified in IR and shouldn't be created in the DAG |
--- |
9107 |
// patterns are simplified in IR and shouldn't be created in the DAG |
--- |
| 9108 |
SDValue DAGCombiner::unfoldMaskedMerge(SDNode *N) { |
0 |
9108 |
SDValue DAGCombiner::unfoldMaskedMerge(SDNode *N) { |
0 |
| 9109 |
assert(N->getOpcode() == ISD::XOR); |
0 |
9109 |
assert(N->getOpcode() == ISD::XOR); |
0 |
| 9110 |
|
--- |
9110 |
|
--- |
| 9111 |
// Don't touch 'not' (i.e. where y = -1). |
--- |
9111 |
// Don't touch 'not' (i.e. where y = -1). |
--- |
| 9112 |
if (isAllOnesOrAllOnesSplat(N->getOperand(1))) |
0 |
9112 |
if (isAllOnesOrAllOnesSplat(N->getOperand(1))) |
0 |
| 9113 |
return SDValue(); |
0 |
9113 |
return SDValue(); |
0 |
| 9114 |
|
--- |
9114 |
|
--- |
| 9115 |
EVT VT = N->getValueType(0); |
0 |
9115 |
EVT VT = N->getValueType(0); |
0 |
| 9116 |
|
--- |
9116 |
|
--- |
| 9117 |
// There are 3 commutable operators in the pattern, |
--- |
9117 |
// There are 3 commutable operators in the pattern, |
--- |
| 9118 |
// so we have to deal with 8 possible variants of the basic pattern. |
--- |
9118 |
// so we have to deal with 8 possible variants of the basic pattern. |
--- |
| 9119 |
SDValue X, Y, M; |
0 |
9119 |
SDValue X, Y, M; |
0 |
| 9120 |
auto matchAndXor = [&X, &Y, &M](SDValue And, unsigned XorIdx, SDValue Other) { |
0 |
9120 |
auto matchAndXor = [&X, &Y, &M](SDValue And, unsigned XorIdx, SDValue Other) { |
0 |
| 9121 |
if (And.getOpcode() != ISD::AND || !And.hasOneUse()) |
0 |
9121 |
if (And.getOpcode() != ISD::AND || !And.hasOneUse()) |
0 |
| 9122 |
return false; |
0 |
9122 |
return false; |
0 |
| 9123 |
SDValue Xor = And.getOperand(XorIdx); |
0 |
9123 |
SDValue Xor = And.getOperand(XorIdx); |
0 |
| 9124 |
if (Xor.getOpcode() != ISD::XOR || !Xor.hasOneUse()) |
0 |
9124 |
if (Xor.getOpcode() != ISD::XOR || !Xor.hasOneUse()) |
0 |
| 9125 |
return false; |
0 |
9125 |
return false; |
0 |
| 9126 |
SDValue Xor0 = Xor.getOperand(0); |
0 |
9126 |
SDValue Xor0 = Xor.getOperand(0); |
0 |
| 9127 |
SDValue Xor1 = Xor.getOperand(1); |
0 |
9127 |
SDValue Xor1 = Xor.getOperand(1); |
0 |
| 9128 |
// Don't touch 'not' (i.e. where y = -1). |
--- |
9128 |
// Don't touch 'not' (i.e. where y = -1). |
--- |
| 9129 |
if (isAllOnesOrAllOnesSplat(Xor1)) |
0 |
9129 |
if (isAllOnesOrAllOnesSplat(Xor1)) |
0 |
| 9130 |
return false; |
0 |
9130 |
return false; |
0 |
| 9131 |
if (Other == Xor0) |
0 |
9131 |
if (Other == Xor0) |
0 |
| 9132 |
std::swap(Xor0, Xor1); |
0 |
9132 |
std::swap(Xor0, Xor1); |
0 |
| 9133 |
if (Other != Xor1) |
0 |
9133 |
if (Other != Xor1) |
0 |
| 9134 |
return false; |
0 |
9134 |
return false; |
0 |
| 9135 |
X = Xor0; |
0 |
9135 |
X = Xor0; |
0 |
| 9136 |
Y = Xor1; |
0 |
9136 |
Y = Xor1; |
0 |
| 9137 |
M = And.getOperand(XorIdx ? 0 : 1); |
0 |
9137 |
M = And.getOperand(XorIdx ? 0 : 1); |
0 |
| 9138 |
return true; |
0 |
9138 |
return true; |
0 |
| 9139 |
}; |
0 |
9139 |
}; |
0 |
| 9140 |
|
--- |
9140 |
|
--- |
| 9141 |
SDValue N0 = N->getOperand(0); |
0 |
9141 |
SDValue N0 = N->getOperand(0); |
0 |
| 9142 |
SDValue N1 = N->getOperand(1); |
0 |
9142 |
SDValue N1 = N->getOperand(1); |
0 |
| 9143 |
if (!matchAndXor(N0, 0, N1) && !matchAndXor(N0, 1, N1) && |
0 |
9143 |
if (!matchAndXor(N0, 0, N1) && !matchAndXor(N0, 1, N1) && |
0 |
| 9144 |
!matchAndXor(N1, 0, N0) && !matchAndXor(N1, 1, N0)) |
0 |
9144 |
!matchAndXor(N1, 0, N0) && !matchAndXor(N1, 1, N0)) |
0 |
| 9145 |
return SDValue(); |
0 |
9145 |
return SDValue(); |
0 |
| 9146 |
|
--- |
9146 |
|
--- |
| 9147 |
// Don't do anything if the mask is constant. This should not be reachable. |
--- |
9147 |
// Don't do anything if the mask is constant. This should not be reachable. |
--- |
| 9148 |
// InstCombine should have already unfolded this pattern, and DAGCombiner |
--- |
9148 |
// InstCombine should have already unfolded this pattern, and DAGCombiner |
--- |
| 9149 |
// probably shouldn't produce it, too. |
--- |
9149 |
// probably shouldn't produce it, too. |
--- |
| 9150 |
if (isa(M.getNode())) |
0 |
9150 |
if (isa(M.getNode())) |
0 |
| 9151 |
return SDValue(); |
0 |
9151 |
return SDValue(); |
0 |
| 9152 |
|
--- |
9152 |
|
--- |
| 9153 |
// We can transform if the target has AndNot |
--- |
9153 |
// We can transform if the target has AndNot |
--- |
| 9154 |
if (!TLI.hasAndNot(M)) |
0 |
9154 |
if (!TLI.hasAndNot(M)) |
0 |
| 9155 |
return SDValue(); |
0 |
9155 |
return SDValue(); |
0 |
| 9156 |
|
--- |
9156 |
|
--- |
| 9157 |
SDLoc DL(N); |
0 |
9157 |
SDLoc DL(N); |
0 |
| 9158 |
|
--- |
9158 |
|
--- |
| 9159 |
// If Y is a constant, check that 'andn' works with immediates. Unless M is |
--- |
9159 |
// If Y is a constant, check that 'andn' works with immediates. Unless M is |
--- |
| 9160 |
// a bitwise not that would already allow ANDN to be used. |
--- |
9160 |
// a bitwise not that would already allow ANDN to be used. |
--- |
| 9161 |
if (!TLI.hasAndNot(Y) && !isBitwiseNot(M)) { |
0 |
9161 |
if (!TLI.hasAndNot(Y) && !isBitwiseNot(M)) { |
0 |
| 9162 |
assert(TLI.hasAndNot(X) && "Only mask is a variable? Unreachable."); |
0 |
9162 |
assert(TLI.hasAndNot(X) && "Only mask is a variable? Unreachable."); |
0 |
| 9163 |
// If not, we need to do a bit more work to make sure andn is still used. |
--- |
9163 |
// If not, we need to do a bit more work to make sure andn is still used. |
--- |
| 9164 |
SDValue NotX = DAG.getNOT(DL, X, VT); |
0 |
9164 |
SDValue NotX = DAG.getNOT(DL, X, VT); |
0 |
| 9165 |
SDValue LHS = DAG.getNode(ISD::AND, DL, VT, NotX, M); |
0 |
9165 |
SDValue LHS = DAG.getNode(ISD::AND, DL, VT, NotX, M); |
0 |
| 9166 |
SDValue NotLHS = DAG.getNOT(DL, LHS, VT); |
0 |
9166 |
SDValue NotLHS = DAG.getNOT(DL, LHS, VT); |
0 |
| 9167 |
SDValue RHS = DAG.getNode(ISD::OR, DL, VT, M, Y); |
0 |
9167 |
SDValue RHS = DAG.getNode(ISD::OR, DL, VT, M, Y); |
0 |
| 9168 |
return DAG.getNode(ISD::AND, DL, VT, NotLHS, RHS); |
0 |
9168 |
return DAG.getNode(ISD::AND, DL, VT, NotLHS, RHS); |
0 |
| 9169 |
} |
--- |
9169 |
} |
--- |
| 9170 |
|
--- |
9170 |
|
--- |
| 9171 |
// If X is a constant and M is a bitwise not, check that 'andn' works with |
--- |
9171 |
// If X is a constant and M is a bitwise not, check that 'andn' works with |
--- |
| 9172 |
// immediates. |
--- |
9172 |
// immediates. |
--- |
| 9173 |
if (!TLI.hasAndNot(X) && isBitwiseNot(M)) { |
0 |
9173 |
if (!TLI.hasAndNot(X) && isBitwiseNot(M)) { |
0 |
| 9174 |
assert(TLI.hasAndNot(Y) && "Only mask is a variable? Unreachable."); |
0 |
9174 |
assert(TLI.hasAndNot(Y) && "Only mask is a variable? Unreachable."); |
0 |
| 9175 |
// If not, we need to do a bit more work to make sure andn is still used. |
--- |
9175 |
// If not, we need to do a bit more work to make sure andn is still used. |
--- |
| 9176 |
SDValue NotM = M.getOperand(0); |
0 |
9176 |
SDValue NotM = M.getOperand(0); |
0 |
| 9177 |
SDValue LHS = DAG.getNode(ISD::OR, DL, VT, X, NotM); |
0 |
9177 |
SDValue LHS = DAG.getNode(ISD::OR, DL, VT, X, NotM); |
0 |
| 9178 |
SDValue NotY = DAG.getNOT(DL, Y, VT); |
0 |
9178 |
SDValue NotY = DAG.getNOT(DL, Y, VT); |
0 |
| 9179 |
SDValue RHS = DAG.getNode(ISD::AND, DL, VT, NotM, NotY); |
0 |
9179 |
SDValue RHS = DAG.getNode(ISD::AND, DL, VT, NotM, NotY); |
0 |
| 9180 |
SDValue NotRHS = DAG.getNOT(DL, RHS, VT); |
0 |
9180 |
SDValue NotRHS = DAG.getNOT(DL, RHS, VT); |
0 |
| 9181 |
return DAG.getNode(ISD::AND, DL, VT, LHS, NotRHS); |
0 |
9181 |
return DAG.getNode(ISD::AND, DL, VT, LHS, NotRHS); |
0 |
| 9182 |
} |
--- |
9182 |
} |
--- |
| 9183 |
|
--- |
9183 |
|
--- |
| 9184 |
SDValue LHS = DAG.getNode(ISD::AND, DL, VT, X, M); |
0 |
9184 |
SDValue LHS = DAG.getNode(ISD::AND, DL, VT, X, M); |
0 |
| 9185 |
SDValue NotM = DAG.getNOT(DL, M, VT); |
0 |
9185 |
SDValue NotM = DAG.getNOT(DL, M, VT); |
0 |
| 9186 |
SDValue RHS = DAG.getNode(ISD::AND, DL, VT, Y, NotM); |
0 |
9186 |
SDValue RHS = DAG.getNode(ISD::AND, DL, VT, Y, NotM); |
0 |
| 9187 |
|
--- |
9187 |
|
--- |
| 9188 |
return DAG.getNode(ISD::OR, DL, VT, LHS, RHS); |
0 |
9188 |
return DAG.getNode(ISD::OR, DL, VT, LHS, RHS); |
0 |
| 9189 |
} |
0 |
9189 |
} |
0 |
| 9190 |
|
--- |
9190 |
|
--- |
| 9191 |
SDValue DAGCombiner::visitXOR(SDNode *N) { |
1 |
9191 |
SDValue DAGCombiner::visitXOR(SDNode *N) { |
1 |
| 9192 |
SDValue N0 = N->getOperand(0); |
1 |
9192 |
SDValue N0 = N->getOperand(0); |
1 |
| 9193 |
SDValue N1 = N->getOperand(1); |
1 |
9193 |
SDValue N1 = N->getOperand(1); |
1 |
| 9194 |
EVT VT = N0.getValueType(); |
1 |
9194 |
EVT VT = N0.getValueType(); |
1 |
| 9195 |
SDLoc DL(N); |
1 |
9195 |
SDLoc DL(N); |
1 |
| 9196 |
|
--- |
9196 |
|
--- |
| 9197 |
// fold (xor undef, undef) -> 0. This is a common idiom (misuse). |
--- |
9197 |
// fold (xor undef, undef) -> 0. This is a common idiom (misuse). |
--- |
| 9198 |
if (N0.isUndef() && N1.isUndef()) |
1 |
9198 |
if (N0.isUndef() && N1.isUndef()) |
1 |
| 9199 |
return DAG.getConstant(0, DL, VT); |
0 |
9199 |
return DAG.getConstant(0, DL, VT); |
0 |
| 9200 |
|
--- |
9200 |
|
--- |
| 9201 |
// fold (xor x, undef) -> undef |
--- |
9201 |
// fold (xor x, undef) -> undef |
--- |
| 9202 |
if (N0.isUndef()) |
1 |
9202 |
if (N0.isUndef()) |
1 |
| 9203 |
return N0; |
0 |
9203 |
return N0; |
0 |
| 9204 |
if (N1.isUndef()) |
1 |
9204 |
if (N1.isUndef()) |
1 |
| 9205 |
return N1; |
0 |
9205 |
return N1; |
0 |
| 9206 |
|
--- |
9206 |
|
--- |
| 9207 |
// fold (xor c1, c2) -> c1^c2 |
--- |
9207 |
// fold (xor c1, c2) -> c1^c2 |
--- |
| 9208 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::XOR, DL, VT, {N0, N1})) |
1 |
9208 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::XOR, DL, VT, {N0, N1})) |
1 |
| 9209 |
return C; |
0 |
9209 |
return C; |
0 |
| 9210 |
|
--- |
9210 |
|
--- |
| 9211 |
// canonicalize constant to RHS |
--- |
9211 |
// canonicalize constant to RHS |
--- |
| 9212 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
1 |
9212 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
1 |
| 9213 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
9213 |
!DAG.isConstantIntBuildVectorOrConstantInt(N1)) |
0 |
| 9214 |
return DAG.getNode(ISD::XOR, DL, VT, N1, N0); |
0 |
9214 |
return DAG.getNode(ISD::XOR, DL, VT, N1, N0); |
0 |
| 9215 |
|
--- |
9215 |
|
--- |
| 9216 |
// fold vector ops |
--- |
9216 |
// fold vector ops |
--- |
| 9217 |
if (VT.isVector()) { |
1 |
9217 |
if (VT.isVector()) { |
1 |
| 9218 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
9218 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 9219 |
return FoldedVOp; |
0 |
9219 |
return FoldedVOp; |
0 |
| 9220 |
|
--- |
9220 |
|
--- |
| 9221 |
// fold (xor x, 0) -> x, vector edition |
--- |
9221 |
// fold (xor x, 0) -> x, vector edition |
--- |
| 9222 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
9222 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) |
0 |
| 9223 |
return N0; |
0 |
9223 |
return N0; |
0 |
| 9224 |
} |
--- |
9224 |
} |
--- |
| 9225 |
|
--- |
9225 |
|
--- |
| 9226 |
// fold (xor x, 0) -> x |
--- |
9226 |
// fold (xor x, 0) -> x |
--- |
| 9227 |
if (isNullConstant(N1)) |
1 |
9227 |
if (isNullConstant(N1)) |
1 |
| 9228 |
return N0; |
0 |
9228 |
return N0; |
0 |
| 9229 |
|
--- |
9229 |
|
--- |
| 9230 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
1 |
9230 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
1 |
| 9231 |
return NewSel; |
0 |
9231 |
return NewSel; |
0 |
| 9232 |
|
--- |
9232 |
|
--- |
| 9233 |
// reassociate xor |
--- |
9233 |
// reassociate xor |
--- |
| 9234 |
if (SDValue RXOR = reassociateOps(ISD::XOR, DL, N0, N1, N->getFlags())) |
1 |
9234 |
if (SDValue RXOR = reassociateOps(ISD::XOR, DL, N0, N1, N->getFlags())) |
1 |
| 9235 |
return RXOR; |
0 |
9235 |
return RXOR; |
0 |
| 9236 |
|
--- |
9236 |
|
--- |
| 9237 |
// Fold xor(vecreduce(x), vecreduce(y)) -> vecreduce(xor(x, y)) |
--- |
9237 |
// Fold xor(vecreduce(x), vecreduce(y)) -> vecreduce(xor(x, y)) |
--- |
| 9238 |
if (SDValue SD = |
1 |
9238 |
if (SDValue SD = |
1 |
| 9239 |
reassociateReduction(ISD::VECREDUCE_XOR, ISD::XOR, DL, VT, N0, N1)) |
1 |
9239 |
reassociateReduction(ISD::VECREDUCE_XOR, ISD::XOR, DL, VT, N0, N1)) |
1 |
| 9240 |
return SD; |
0 |
9240 |
return SD; |
0 |
| 9241 |
|
--- |
9241 |
|
--- |
| 9242 |
// fold (a^b) -> (a|b) iff a and b share no bits. |
--- |
9242 |
// fold (a^b) -> (a|b) iff a and b share no bits. |
--- |
| 9243 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && |
2 |
9243 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && |
2 |
| 9244 |
DAG.haveNoCommonBitsSet(N0, N1)) |
1 |
9244 |
DAG.haveNoCommonBitsSet(N0, N1)) |
1 |
| 9245 |
return DAG.getNode(ISD::OR, DL, VT, N0, N1); |
0 |
9245 |
return DAG.getNode(ISD::OR, DL, VT, N0, N1); |
0 |
| 9246 |
|
--- |
9246 |
|
--- |
| 9247 |
// look for 'add-like' folds: |
--- |
9247 |
// look for 'add-like' folds: |
--- |
| 9248 |
// XOR(N0,MIN_SIGNED_VALUE) == ADD(N0,MIN_SIGNED_VALUE) |
--- |
9248 |
// XOR(N0,MIN_SIGNED_VALUE) == ADD(N0,MIN_SIGNED_VALUE) |
--- |
| 9249 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::ADD, VT)) && |
2 |
9249 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::ADD, VT)) && |
2 |
| 9250 |
isMinSignedConstant(N1)) |
1 |
9250 |
isMinSignedConstant(N1)) |
1 |
| 9251 |
if (SDValue Combined = visitADDLike(N)) |
1 |
9251 |
if (SDValue Combined = visitADDLike(N)) |
1 |
| 9252 |
return Combined; |
0 |
9252 |
return Combined; |
0 |
| 9253 |
|
--- |
9253 |
|
--- |
| 9254 |
// fold !(x cc y) -> (x !cc y) |
--- |
9254 |
// fold !(x cc y) -> (x !cc y) |
--- |
| 9255 |
unsigned N0Opcode = N0.getOpcode(); |
1 |
9255 |
unsigned N0Opcode = N0.getOpcode(); |
1 |
| 9256 |
SDValue LHS, RHS, CC; |
1 |
9256 |
SDValue LHS, RHS, CC; |
1 |
| 9257 |
if (TLI.isConstTrueVal(N1) && |
2 |
9257 |
if (TLI.isConstTrueVal(N1) && |
2 |
| 9258 |
isSetCCEquivalent(N0, LHS, RHS, CC, /*MatchStrict*/ true)) { |
1 |
9258 |
isSetCCEquivalent(N0, LHS, RHS, CC, /*MatchStrict*/ true)) { |
1 |
| 9259 |
ISD::CondCode NotCC = ISD::getSetCCInverse(cast(CC)->get(), |
1 |
9259 |
ISD::CondCode NotCC = ISD::getSetCCInverse(cast(CC)->get(), |
1 |
| 9260 |
LHS.getValueType()); |
--- |
9260 |
LHS.getValueType()); |
--- |
| 9261 |
if (!LegalOperations || |
1 |
9261 |
if (!LegalOperations || |
1 |
| 9262 |
TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) { |
0 |
9262 |
TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) { |
0 |
| 9263 |
switch (N0Opcode) { |
1 |
9263 |
switch (N0Opcode) { |
1 |
| 9264 |
default: |
0 |
9264 |
default: |
0 |
| 9265 |
llvm_unreachable("Unhandled SetCC Equivalent!"); |
0 |
9265 |
llvm_unreachable("Unhandled SetCC Equivalent!"); |
0 |
| 9266 |
case ISD::SETCC: |
1 |
9266 |
case ISD::SETCC: |
1 |
| 9267 |
return DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC); |
1 |
9267 |
return DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC); |
1 |
| 9268 |
case ISD::SELECT_CC: |
0 |
9268 |
case ISD::SELECT_CC: |
0 |
| 9269 |
return DAG.getSelectCC(SDLoc(N0), LHS, RHS, N0.getOperand(2), |
0 |
9269 |
return DAG.getSelectCC(SDLoc(N0), LHS, RHS, N0.getOperand(2), |
0 |
| 9270 |
N0.getOperand(3), NotCC); |
0 |
9270 |
N0.getOperand(3), NotCC); |
0 |
| 9271 |
case ISD::STRICT_FSETCC: |
0 |
9271 |
case ISD::STRICT_FSETCC: |
0 |
| 9272 |
case ISD::STRICT_FSETCCS: { |
--- |
9272 |
case ISD::STRICT_FSETCCS: { |
--- |
| 9273 |
if (N0.hasOneUse()) { |
0 |
9273 |
if (N0.hasOneUse()) { |
0 |
| 9274 |
// FIXME Can we handle multiple uses? Could we token factor the chain |
--- |
9274 |
// FIXME Can we handle multiple uses? Could we token factor the chain |
--- |
| 9275 |
// results from the new/old setcc? |
--- |
9275 |
// results from the new/old setcc? |
--- |
| 9276 |
SDValue SetCC = |
--- |
9276 |
SDValue SetCC = |
--- |
| 9277 |
DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC, |
0 |
9277 |
DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC, |
0 |
| 9278 |
N0.getOperand(0), N0Opcode == ISD::STRICT_FSETCCS); |
0 |
9278 |
N0.getOperand(0), N0Opcode == ISD::STRICT_FSETCCS); |
0 |
| 9279 |
CombineTo(N, SetCC); |
0 |
9279 |
CombineTo(N, SetCC); |
0 |
| 9280 |
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), SetCC.getValue(1)); |
0 |
9280 |
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), SetCC.getValue(1)); |
0 |
| 9281 |
recursivelyDeleteUnusedNodes(N0.getNode()); |
0 |
9281 |
recursivelyDeleteUnusedNodes(N0.getNode()); |
0 |
| 9282 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
9282 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 9283 |
} |
--- |
9283 |
} |
--- |
| 9284 |
break; |
0 |
9284 |
break; |
0 |
| 9285 |
} |
--- |
9285 |
} |
--- |
| 9286 |
} |
--- |
9286 |
} |
--- |
| 9287 |
} |
--- |
9287 |
} |
--- |
| 9288 |
} |
--- |
9288 |
} |
--- |
| 9289 |
|
--- |
9289 |
|
--- |
| 9290 |
// fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) |
--- |
9290 |
// fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) |
--- |
| 9291 |
if (isOneConstant(N1) && N0Opcode == ISD::ZERO_EXTEND && N0.hasOneUse() && |
0 |
9291 |
if (isOneConstant(N1) && N0Opcode == ISD::ZERO_EXTEND && N0.hasOneUse() && |
0 |
| 9292 |
isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ |
0 |
9292 |
isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ |
0 |
| 9293 |
SDValue V = N0.getOperand(0); |
0 |
9293 |
SDValue V = N0.getOperand(0); |
0 |
| 9294 |
SDLoc DL0(N0); |
0 |
9294 |
SDLoc DL0(N0); |
0 |
| 9295 |
V = DAG.getNode(ISD::XOR, DL0, V.getValueType(), V, |
0 |
9295 |
V = DAG.getNode(ISD::XOR, DL0, V.getValueType(), V, |
0 |
| 9296 |
DAG.getConstant(1, DL0, V.getValueType())); |
0 |
9296 |
DAG.getConstant(1, DL0, V.getValueType())); |
0 |
| 9297 |
AddToWorklist(V.getNode()); |
0 |
9297 |
AddToWorklist(V.getNode()); |
0 |
| 9298 |
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, V); |
0 |
9298 |
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, V); |
0 |
| 9299 |
} |
0 |
9299 |
} |
0 |
| 9300 |
|
--- |
9300 |
|
--- |
| 9301 |
// fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc |
--- |
9301 |
// fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc |
--- |
| 9302 |
if (isOneConstant(N1) && VT == MVT::i1 && N0.hasOneUse() && |
0 |
9302 |
if (isOneConstant(N1) && VT == MVT::i1 && N0.hasOneUse() && |
0 |
| 9303 |
(N0Opcode == ISD::OR || N0Opcode == ISD::AND)) { |
0 |
9303 |
(N0Opcode == ISD::OR || N0Opcode == ISD::AND)) { |
0 |
| 9304 |
SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1); |
0 |
9304 |
SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1); |
0 |
| 9305 |
if (isOneUseSetCC(N01) || isOneUseSetCC(N00)) { |
0 |
9305 |
if (isOneUseSetCC(N01) || isOneUseSetCC(N00)) { |
0 |
| 9306 |
unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND; |
0 |
9306 |
unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND; |
0 |
| 9307 |
N00 = DAG.getNode(ISD::XOR, SDLoc(N00), VT, N00, N1); // N00 = ~N00 |
0 |
9307 |
N00 = DAG.getNode(ISD::XOR, SDLoc(N00), VT, N00, N1); // N00 = ~N00 |
0 |
| 9308 |
N01 = DAG.getNode(ISD::XOR, SDLoc(N01), VT, N01, N1); // N01 = ~N01 |
0 |
9308 |
N01 = DAG.getNode(ISD::XOR, SDLoc(N01), VT, N01, N1); // N01 = ~N01 |
0 |
| 9309 |
AddToWorklist(N00.getNode()); AddToWorklist(N01.getNode()); |
0 |
9309 |
AddToWorklist(N00.getNode()); AddToWorklist(N01.getNode()); |
0 |
| 9310 |
return DAG.getNode(NewOpcode, DL, VT, N00, N01); |
0 |
9310 |
return DAG.getNode(NewOpcode, DL, VT, N00, N01); |
0 |
| 9311 |
} |
--- |
9311 |
} |
--- |
| 9312 |
} |
--- |
9312 |
} |
--- |
| 9313 |
// fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants |
--- |
9313 |
// fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants |
--- |
| 9314 |
if (isAllOnesConstant(N1) && N0.hasOneUse() && |
0 |
9314 |
if (isAllOnesConstant(N1) && N0.hasOneUse() && |
0 |
| 9315 |
(N0Opcode == ISD::OR || N0Opcode == ISD::AND)) { |
0 |
9315 |
(N0Opcode == ISD::OR || N0Opcode == ISD::AND)) { |
0 |
| 9316 |
SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1); |
0 |
9316 |
SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1); |
0 |
| 9317 |
if (isa(N01) || isa(N00)) { |
0 |
9317 |
if (isa(N01) || isa(N00)) { |
0 |
| 9318 |
unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND; |
0 |
9318 |
unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND; |
0 |
| 9319 |
N00 = DAG.getNode(ISD::XOR, SDLoc(N00), VT, N00, N1); // N00 = ~N00 |
0 |
9319 |
N00 = DAG.getNode(ISD::XOR, SDLoc(N00), VT, N00, N1); // N00 = ~N00 |
0 |
| 9320 |
N01 = DAG.getNode(ISD::XOR, SDLoc(N01), VT, N01, N1); // N01 = ~N01 |
0 |
9320 |
N01 = DAG.getNode(ISD::XOR, SDLoc(N01), VT, N01, N1); // N01 = ~N01 |
0 |
| 9321 |
AddToWorklist(N00.getNode()); AddToWorklist(N01.getNode()); |
0 |
9321 |
AddToWorklist(N00.getNode()); AddToWorklist(N01.getNode()); |
0 |
| 9322 |
return DAG.getNode(NewOpcode, DL, VT, N00, N01); |
0 |
9322 |
return DAG.getNode(NewOpcode, DL, VT, N00, N01); |
0 |
| 9323 |
} |
--- |
9323 |
} |
--- |
| 9324 |
} |
--- |
9324 |
} |
--- |
| 9325 |
|
--- |
9325 |
|
--- |
| 9326 |
// fold (not (neg x)) -> (add X, -1) |
--- |
9326 |
// fold (not (neg x)) -> (add X, -1) |
--- |
| 9327 |
// FIXME: This can be generalized to (not (sub Y, X)) -> (add X, ~Y) if |
--- |
9327 |
// FIXME: This can be generalized to (not (sub Y, X)) -> (add X, ~Y) if |
--- |
| 9328 |
// Y is a constant or the subtract has a single use. |
--- |
9328 |
// Y is a constant or the subtract has a single use. |
--- |
| 9329 |
if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB && |
0 |
9329 |
if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB && |
0 |
| 9330 |
isNullConstant(N0.getOperand(0))) { |
0 |
9330 |
isNullConstant(N0.getOperand(0))) { |
0 |
| 9331 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), |
0 |
9331 |
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), |
0 |
| 9332 |
DAG.getAllOnesConstant(DL, VT)); |
0 |
9332 |
DAG.getAllOnesConstant(DL, VT)); |
0 |
| 9333 |
} |
--- |
9333 |
} |
--- |
| 9334 |
|
--- |
9334 |
|
--- |
| 9335 |
// fold (not (add X, -1)) -> (neg X) |
--- |
9335 |
// fold (not (add X, -1)) -> (neg X) |
--- |
| 9336 |
if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD && |
0 |
9336 |
if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD && |
0 |
| 9337 |
isAllOnesOrAllOnesSplat(N0.getOperand(1))) { |
0 |
9337 |
isAllOnesOrAllOnesSplat(N0.getOperand(1))) { |
0 |
| 9338 |
return DAG.getNegative(N0.getOperand(0), DL, VT); |
0 |
9338 |
return DAG.getNegative(N0.getOperand(0), DL, VT); |
0 |
| 9339 |
} |
--- |
9339 |
} |
--- |
| 9340 |
|
--- |
9340 |
|
--- |
| 9341 |
// fold (xor (and x, y), y) -> (and (not x), y) |
--- |
9341 |
// fold (xor (and x, y), y) -> (and (not x), y) |
--- |
| 9342 |
if (N0Opcode == ISD::AND && N0.hasOneUse() && N0->getOperand(1) == N1) { |
0 |
9342 |
if (N0Opcode == ISD::AND && N0.hasOneUse() && N0->getOperand(1) == N1) { |
0 |
| 9343 |
SDValue X = N0.getOperand(0); |
0 |
9343 |
SDValue X = N0.getOperand(0); |
0 |
| 9344 |
SDValue NotX = DAG.getNOT(SDLoc(X), X, VT); |
0 |
9344 |
SDValue NotX = DAG.getNOT(SDLoc(X), X, VT); |
0 |
| 9345 |
AddToWorklist(NotX.getNode()); |
0 |
9345 |
AddToWorklist(NotX.getNode()); |
0 |
| 9346 |
return DAG.getNode(ISD::AND, DL, VT, NotX, N1); |
0 |
9346 |
return DAG.getNode(ISD::AND, DL, VT, NotX, N1); |
0 |
| 9347 |
} |
--- |
9347 |
} |
--- |
| 9348 |
|
--- |
9348 |
|
--- |
| 9349 |
// fold Y = sra (X, size(X)-1); xor (add (X, Y), Y) -> (abs X) |
--- |
9349 |
// fold Y = sra (X, size(X)-1); xor (add (X, Y), Y) -> (abs X) |
--- |
| 9350 |
if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { |
0 |
9350 |
if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { |
0 |
| 9351 |
SDValue A = N0Opcode == ISD::ADD ? N0 : N1; |
0 |
9351 |
SDValue A = N0Opcode == ISD::ADD ? N0 : N1; |
0 |
| 9352 |
SDValue S = N0Opcode == ISD::SRA ? N0 : N1; |
0 |
9352 |
SDValue S = N0Opcode == ISD::SRA ? N0 : N1; |
0 |
| 9353 |
if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) { |
0 |
9353 |
if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) { |
0 |
| 9354 |
SDValue A0 = A.getOperand(0), A1 = A.getOperand(1); |
0 |
9354 |
SDValue A0 = A.getOperand(0), A1 = A.getOperand(1); |
0 |
| 9355 |
SDValue S0 = S.getOperand(0); |
0 |
9355 |
SDValue S0 = S.getOperand(0); |
0 |
| 9356 |
if ((A0 == S && A1 == S0) || (A1 == S && A0 == S0)) |
0 |
9356 |
if ((A0 == S && A1 == S0) || (A1 == S && A0 == S0)) |
0 |
| 9357 |
if (ConstantSDNode *C = isConstOrConstSplat(S.getOperand(1))) |
0 |
9357 |
if (ConstantSDNode *C = isConstOrConstSplat(S.getOperand(1))) |
0 |
| 9358 |
if (C->getAPIntValue() == (VT.getScalarSizeInBits() - 1)) |
0 |
9358 |
if (C->getAPIntValue() == (VT.getScalarSizeInBits() - 1)) |
0 |
| 9359 |
return DAG.getNode(ISD::ABS, DL, VT, S0); |
0 |
9359 |
return DAG.getNode(ISD::ABS, DL, VT, S0); |
0 |
| 9360 |
} |
--- |
9360 |
} |
--- |
| 9361 |
} |
--- |
9361 |
} |
--- |
| 9362 |
|
--- |
9362 |
|
--- |
| 9363 |
// fold (xor x, x) -> 0 |
--- |
9363 |
// fold (xor x, x) -> 0 |
--- |
| 9364 |
if (N0 == N1) |
0 |
9364 |
if (N0 == N1) |
0 |
| 9365 |
return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); |
0 |
9365 |
return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); |
0 |
| 9366 |
|
--- |
9366 |
|
--- |
| 9367 |
// fold (xor (shl 1, x), -1) -> (rotl ~1, x) |
--- |
9367 |
// fold (xor (shl 1, x), -1) -> (rotl ~1, x) |
--- |
| 9368 |
// Here is a concrete example of this equivalence: |
--- |
9368 |
// Here is a concrete example of this equivalence: |
--- |
| 9369 |
// i16 x == 14 |
--- |
9369 |
// i16 x == 14 |
--- |
| 9370 |
// i16 shl == 1 << 14 == 16384 == 0b0100000000000000 |
--- |
9370 |
// i16 shl == 1 << 14 == 16384 == 0b0100000000000000 |
--- |
| 9371 |
// i16 xor == ~(1 << 14) == 49151 == 0b1011111111111111 |
--- |
9371 |
// i16 xor == ~(1 << 14) == 49151 == 0b1011111111111111 |
--- |
| 9372 |
// |
--- |
9372 |
// |
--- |
| 9373 |
// => |
--- |
9373 |
// => |
--- |
| 9374 |
// |
--- |
9374 |
// |
--- |
| 9375 |
// i16 ~1 == 0b1111111111111110 |
--- |
9375 |
// i16 ~1 == 0b1111111111111110 |
--- |
| 9376 |
// i16 rol(~1, 14) == 0b1011111111111111 |
--- |
9376 |
// i16 rol(~1, 14) == 0b1011111111111111 |
--- |
| 9377 |
// |
--- |
9377 |
// |
--- |
| 9378 |
// Some additional tips to help conceptualize this transform: |
--- |
9378 |
// Some additional tips to help conceptualize this transform: |
--- |
| 9379 |
// - Try to see the operation as placing a single zero in a value of all ones. |
--- |
9379 |
// - Try to see the operation as placing a single zero in a value of all ones. |
--- |
| 9380 |
// - There exists no value for x which would allow the result to contain zero. |
--- |
9380 |
// - There exists no value for x which would allow the result to contain zero. |
--- |
| 9381 |
// - Values of x larger than the bitwidth are undefined and do not require a |
--- |
9381 |
// - Values of x larger than the bitwidth are undefined and do not require a |
--- |
| 9382 |
// consistent result. |
--- |
9382 |
// consistent result. |
--- |
| 9383 |
// - Pushing the zero left requires shifting one bits in from the right. |
--- |
9383 |
// - Pushing the zero left requires shifting one bits in from the right. |
--- |
| 9384 |
// A rotate left of ~1 is a nice way of achieving the desired result. |
--- |
9384 |
// A rotate left of ~1 is a nice way of achieving the desired result. |
--- |
| 9385 |
if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0Opcode == ISD::SHL && |
0 |
9385 |
if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0Opcode == ISD::SHL && |
0 |
| 9386 |
isAllOnesConstant(N1) && isOneConstant(N0.getOperand(0))) { |
0 |
9386 |
isAllOnesConstant(N1) && isOneConstant(N0.getOperand(0))) { |
0 |
| 9387 |
return DAG.getNode(ISD::ROTL, DL, VT, DAG.getConstant(~1, DL, VT), |
0 |
9387 |
return DAG.getNode(ISD::ROTL, DL, VT, DAG.getConstant(~1, DL, VT), |
0 |
| 9388 |
N0.getOperand(1)); |
0 |
9388 |
N0.getOperand(1)); |
0 |
| 9389 |
} |
--- |
9389 |
} |
--- |
| 9390 |
|
--- |
9390 |
|
--- |
| 9391 |
// Simplify: xor (op x...), (op y...) -> (op (xor x, y)) |
--- |
9391 |
// Simplify: xor (op x...), (op y...) -> (op (xor x, y)) |
--- |
| 9392 |
if (N0Opcode == N1.getOpcode()) |
0 |
9392 |
if (N0Opcode == N1.getOpcode()) |
0 |
| 9393 |
if (SDValue V = hoistLogicOpWithSameOpcodeHands(N)) |
0 |
9393 |
if (SDValue V = hoistLogicOpWithSameOpcodeHands(N)) |
0 |
| 9394 |
return V; |
0 |
9394 |
return V; |
0 |
| 9395 |
|
--- |
9395 |
|
--- |
| 9396 |
if (SDValue R = foldLogicOfShifts(N, N0, N1, DAG)) |
0 |
9396 |
if (SDValue R = foldLogicOfShifts(N, N0, N1, DAG)) |
0 |
| 9397 |
return R; |
0 |
9397 |
return R; |
0 |
| 9398 |
if (SDValue R = foldLogicOfShifts(N, N1, N0, DAG)) |
0 |
9398 |
if (SDValue R = foldLogicOfShifts(N, N1, N0, DAG)) |
0 |
| 9399 |
return R; |
0 |
9399 |
return R; |
0 |
| 9400 |
if (SDValue R = foldLogicTreeOfShifts(N, N0, N1, DAG)) |
0 |
9400 |
if (SDValue R = foldLogicTreeOfShifts(N, N0, N1, DAG)) |
0 |
| 9401 |
return R; |
0 |
9401 |
return R; |
0 |
| 9402 |
|
--- |
9402 |
|
--- |
| 9403 |
// Unfold ((x ^ y) & m) ^ y into (x & m) | (y & ~m) if profitable |
--- |
9403 |
// Unfold ((x ^ y) & m) ^ y into (x & m) | (y & ~m) if profitable |
--- |
| 9404 |
if (SDValue MM = unfoldMaskedMerge(N)) |
0 |
9404 |
if (SDValue MM = unfoldMaskedMerge(N)) |
0 |
| 9405 |
return MM; |
0 |
9405 |
return MM; |
0 |
| 9406 |
|
--- |
9406 |
|
--- |
| 9407 |
// Simplify the expression using non-local knowledge. |
--- |
9407 |
// Simplify the expression using non-local knowledge. |
--- |
| 9408 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
9408 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
| 9409 |
return SDValue(N, 0); |
0 |
9409 |
return SDValue(N, 0); |
0 |
| 9410 |
|
--- |
9410 |
|
--- |
| 9411 |
if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N)) |
0 |
9411 |
if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N)) |
0 |
| 9412 |
return Combined; |
0 |
9412 |
return Combined; |
0 |
| 9413 |
|
--- |
9413 |
|
--- |
| 9414 |
return SDValue(); |
0 |
9414 |
return SDValue(); |
0 |
| 9415 |
} |
1 |
9415 |
} |
1 |
| 9416 |
|
--- |
9416 |
|
--- |
| 9417 |
/// If we have a shift-by-constant of a bitwise logic op that itself has a |
--- |
9417 |
/// If we have a shift-by-constant of a bitwise logic op that itself has a |
--- |
| 9418 |
/// shift-by-constant operand with identical opcode, we may be able to convert |
--- |
9418 |
/// shift-by-constant operand with identical opcode, we may be able to convert |
--- |
| 9419 |
/// that into 2 independent shifts followed by the logic op. This is a |
--- |
9419 |
/// that into 2 independent shifts followed by the logic op. This is a |
--- |
| 9420 |
/// throughput improvement. |
--- |
9420 |
/// throughput improvement. |
--- |
| 9421 |
static SDValue combineShiftOfShiftedLogic(SDNode *Shift, SelectionDAG &DAG) { |
0 |
9421 |
static SDValue combineShiftOfShiftedLogic(SDNode *Shift, SelectionDAG &DAG) { |
0 |
| 9422 |
// Match a one-use bitwise logic op. |
--- |
9422 |
// Match a one-use bitwise logic op. |
--- |
| 9423 |
SDValue LogicOp = Shift->getOperand(0); |
0 |
9423 |
SDValue LogicOp = Shift->getOperand(0); |
0 |
| 9424 |
if (!LogicOp.hasOneUse()) |
0 |
9424 |
if (!LogicOp.hasOneUse()) |
0 |
| 9425 |
return SDValue(); |
0 |
9425 |
return SDValue(); |
0 |
| 9426 |
|
--- |
9426 |
|
--- |
| 9427 |
unsigned LogicOpcode = LogicOp.getOpcode(); |
0 |
9427 |
unsigned LogicOpcode = LogicOp.getOpcode(); |
0 |
| 9428 |
if (LogicOpcode != ISD::AND && LogicOpcode != ISD::OR && |
0 |
9428 |
if (LogicOpcode != ISD::AND && LogicOpcode != ISD::OR && |
0 |
| 9429 |
LogicOpcode != ISD::XOR) |
--- |
9429 |
LogicOpcode != ISD::XOR) |
--- |
| 9430 |
return SDValue(); |
0 |
9430 |
return SDValue(); |
0 |
| 9431 |
|
--- |
9431 |
|
--- |
| 9432 |
// Find a matching one-use shift by constant. |
--- |
9432 |
// Find a matching one-use shift by constant. |
--- |
| 9433 |
unsigned ShiftOpcode = Shift->getOpcode(); |
0 |
9433 |
unsigned ShiftOpcode = Shift->getOpcode(); |
0 |
| 9434 |
SDValue C1 = Shift->getOperand(1); |
0 |
9434 |
SDValue C1 = Shift->getOperand(1); |
0 |
| 9435 |
ConstantSDNode *C1Node = isConstOrConstSplat(C1); |
0 |
9435 |
ConstantSDNode *C1Node = isConstOrConstSplat(C1); |
0 |
| 9436 |
assert(C1Node && "Expected a shift with constant operand"); |
0 |
9436 |
assert(C1Node && "Expected a shift with constant operand"); |
0 |
| 9437 |
const APInt &C1Val = C1Node->getAPIntValue(); |
0 |
9437 |
const APInt &C1Val = C1Node->getAPIntValue(); |
0 |
| 9438 |
auto matchFirstShift = [&](SDValue V, SDValue &ShiftOp, |
0 |
9438 |
auto matchFirstShift = [&](SDValue V, SDValue &ShiftOp, |
0 |
| 9439 |
const APInt *&ShiftAmtVal) { |
--- |
9439 |
const APInt *&ShiftAmtVal) { |
--- |
| 9440 |
if (V.getOpcode() != ShiftOpcode || !V.hasOneUse()) |
0 |
9440 |
if (V.getOpcode() != ShiftOpcode || !V.hasOneUse()) |
0 |
| 9441 |
return false; |
0 |
9441 |
return false; |
0 |
| 9442 |
|
--- |
9442 |
|
--- |
| 9443 |
ConstantSDNode *ShiftCNode = isConstOrConstSplat(V.getOperand(1)); |
0 |
9443 |
ConstantSDNode *ShiftCNode = isConstOrConstSplat(V.getOperand(1)); |
0 |
| 9444 |
if (!ShiftCNode) |
0 |
9444 |
if (!ShiftCNode) |
0 |
| 9445 |
return false; |
0 |
9445 |
return false; |
0 |
| 9446 |
|
--- |
9446 |
|
--- |
| 9447 |
// Capture the shifted operand and shift amount value. |
--- |
9447 |
// Capture the shifted operand and shift amount value. |
--- |
| 9448 |
ShiftOp = V.getOperand(0); |
0 |
9448 |
ShiftOp = V.getOperand(0); |
0 |
| 9449 |
ShiftAmtVal = &ShiftCNode->getAPIntValue(); |
0 |
9449 |
ShiftAmtVal = &ShiftCNode->getAPIntValue(); |
0 |
| 9450 |
|
--- |
9450 |
|
--- |
| 9451 |
// Shift amount types do not have to match their operand type, so check that |
--- |
9451 |
// Shift amount types do not have to match their operand type, so check that |
--- |
| 9452 |
// the constants are the same width. |
--- |
9452 |
// the constants are the same width. |
--- |
| 9453 |
if (ShiftAmtVal->getBitWidth() != C1Val.getBitWidth()) |
0 |
9453 |
if (ShiftAmtVal->getBitWidth() != C1Val.getBitWidth()) |
0 |
| 9454 |
return false; |
0 |
9454 |
return false; |
0 |
| 9455 |
|
--- |
9455 |
|
--- |
| 9456 |
// The fold is not valid if the sum of the shift values exceeds bitwidth. |
--- |
9456 |
// The fold is not valid if the sum of the shift values exceeds bitwidth. |
--- |
| 9457 |
if ((*ShiftAmtVal + C1Val).uge(V.getScalarValueSizeInBits())) |
0 |
9457 |
if ((*ShiftAmtVal + C1Val).uge(V.getScalarValueSizeInBits())) |
0 |
| 9458 |
return false; |
0 |
9458 |
return false; |
0 |
| 9459 |
|
--- |
9459 |
|
--- |
| 9460 |
return true; |
0 |
9460 |
return true; |
0 |
| 9461 |
}; |
0 |
9461 |
}; |
0 |
| 9462 |
|
--- |
9462 |
|
--- |
| 9463 |
// Logic ops are commutative, so check each operand for a match. |
--- |
9463 |
// Logic ops are commutative, so check each operand for a match. |
--- |
| 9464 |
SDValue X, Y; |
0 |
9464 |
SDValue X, Y; |
0 |
| 9465 |
const APInt *C0Val; |
--- |
9465 |
const APInt *C0Val; |
--- |
| 9466 |
if (matchFirstShift(LogicOp.getOperand(0), X, C0Val)) |
0 |
9466 |
if (matchFirstShift(LogicOp.getOperand(0), X, C0Val)) |
0 |
| 9467 |
Y = LogicOp.getOperand(1); |
0 |
9467 |
Y = LogicOp.getOperand(1); |
0 |
| 9468 |
else if (matchFirstShift(LogicOp.getOperand(1), X, C0Val)) |
0 |
9468 |
else if (matchFirstShift(LogicOp.getOperand(1), X, C0Val)) |
0 |
| 9469 |
Y = LogicOp.getOperand(0); |
0 |
9469 |
Y = LogicOp.getOperand(0); |
0 |
| 9470 |
else |
--- |
9470 |
else |
--- |
| 9471 |
return SDValue(); |
0 |
9471 |
return SDValue(); |
0 |
| 9472 |
|
--- |
9472 |
|
--- |
| 9473 |
// shift (logic (shift X, C0), Y), C1 -> logic (shift X, C0+C1), (shift Y, C1) |
--- |
9473 |
// shift (logic (shift X, C0), Y), C1 -> logic (shift X, C0+C1), (shift Y, C1) |
--- |
| 9474 |
SDLoc DL(Shift); |
0 |
9474 |
SDLoc DL(Shift); |
0 |
| 9475 |
EVT VT = Shift->getValueType(0); |
0 |
9475 |
EVT VT = Shift->getValueType(0); |
0 |
| 9476 |
EVT ShiftAmtVT = Shift->getOperand(1).getValueType(); |
0 |
9476 |
EVT ShiftAmtVT = Shift->getOperand(1).getValueType(); |
0 |
| 9477 |
SDValue ShiftSumC = DAG.getConstant(*C0Val + C1Val, DL, ShiftAmtVT); |
0 |
9477 |
SDValue ShiftSumC = DAG.getConstant(*C0Val + C1Val, DL, ShiftAmtVT); |
0 |
| 9478 |
SDValue NewShift1 = DAG.getNode(ShiftOpcode, DL, VT, X, ShiftSumC); |
0 |
9478 |
SDValue NewShift1 = DAG.getNode(ShiftOpcode, DL, VT, X, ShiftSumC); |
0 |
| 9479 |
SDValue NewShift2 = DAG.getNode(ShiftOpcode, DL, VT, Y, C1); |
0 |
9479 |
SDValue NewShift2 = DAG.getNode(ShiftOpcode, DL, VT, Y, C1); |
0 |
| 9480 |
return DAG.getNode(LogicOpcode, DL, VT, NewShift1, NewShift2); |
0 |
9480 |
return DAG.getNode(LogicOpcode, DL, VT, NewShift1, NewShift2); |
0 |
| 9481 |
} |
0 |
9481 |
} |
0 |
| 9482 |
|
--- |
9482 |
|
--- |
| 9483 |
/// Handle transforms common to the three shifts, when the shift amount is a |
--- |
9483 |
/// Handle transforms common to the three shifts, when the shift amount is a |
--- |
| 9484 |
/// constant. |
--- |
9484 |
/// constant. |
--- |
| 9485 |
/// We are looking for: (shift being one of shl/sra/srl) |
--- |
9485 |
/// We are looking for: (shift being one of shl/sra/srl) |
--- |
| 9486 |
/// shift (binop X, C0), C1 |
--- |
9486 |
/// shift (binop X, C0), C1 |
--- |
| 9487 |
/// And want to transform into: |
--- |
9487 |
/// And want to transform into: |
--- |
| 9488 |
/// binop (shift X, C1), (shift C0, C1) |
--- |
9488 |
/// binop (shift X, C1), (shift C0, C1) |
--- |
| 9489 |
SDValue DAGCombiner::visitShiftByConstant(SDNode *N) { |
0 |
9489 |
SDValue DAGCombiner::visitShiftByConstant(SDNode *N) { |
0 |
| 9490 |
assert(isConstOrConstSplat(N->getOperand(1)) && "Expected constant operand"); |
0 |
9490 |
assert(isConstOrConstSplat(N->getOperand(1)) && "Expected constant operand"); |
0 |
| 9491 |
|
--- |
9491 |
|
--- |
| 9492 |
// Do not turn a 'not' into a regular xor. |
--- |
9492 |
// Do not turn a 'not' into a regular xor. |
--- |
| 9493 |
if (isBitwiseNot(N->getOperand(0))) |
0 |
9493 |
if (isBitwiseNot(N->getOperand(0))) |
0 |
| 9494 |
return SDValue(); |
0 |
9494 |
return SDValue(); |
0 |
| 9495 |
|
--- |
9495 |
|
--- |
| 9496 |
// The inner binop must be one-use, since we want to replace it. |
--- |
9496 |
// The inner binop must be one-use, since we want to replace it. |
--- |
| 9497 |
SDValue LHS = N->getOperand(0); |
0 |
9497 |
SDValue LHS = N->getOperand(0); |
0 |
| 9498 |
if (!LHS.hasOneUse() || !TLI.isDesirableToCommuteWithShift(N, Level)) |
0 |
9498 |
if (!LHS.hasOneUse() || !TLI.isDesirableToCommuteWithShift(N, Level)) |
0 |
| 9499 |
return SDValue(); |
0 |
9499 |
return SDValue(); |
0 |
| 9500 |
|
--- |
9500 |
|
--- |
| 9501 |
// Fold shift(bitop(shift(x,c1),y), c2) -> bitop(shift(x,c1+c2),shift(y,c2)). |
--- |
9501 |
// Fold shift(bitop(shift(x,c1),y), c2) -> bitop(shift(x,c1+c2),shift(y,c2)). |
--- |
| 9502 |
if (SDValue R = combineShiftOfShiftedLogic(N, DAG)) |
0 |
9502 |
if (SDValue R = combineShiftOfShiftedLogic(N, DAG)) |
0 |
| 9503 |
return R; |
0 |
9503 |
return R; |
0 |
| 9504 |
|
--- |
9504 |
|
--- |
| 9505 |
// We want to pull some binops through shifts, so that we have (and (shift)) |
--- |
9505 |
// We want to pull some binops through shifts, so that we have (and (shift)) |
--- |
| 9506 |
// instead of (shift (and)), likewise for add, or, xor, etc. This sort of |
--- |
9506 |
// instead of (shift (and)), likewise for add, or, xor, etc. This sort of |
--- |
| 9507 |
// thing happens with address calculations, so it's important to canonicalize |
--- |
9507 |
// thing happens with address calculations, so it's important to canonicalize |
--- |
| 9508 |
// it. |
--- |
9508 |
// it. |
--- |
| 9509 |
switch (LHS.getOpcode()) { |
0 |
9509 |
switch (LHS.getOpcode()) { |
0 |
| 9510 |
default: |
0 |
9510 |
default: |
0 |
| 9511 |
return SDValue(); |
0 |
9511 |
return SDValue(); |
0 |
| 9512 |
case ISD::OR: |
0 |
9512 |
case ISD::OR: |
0 |
| 9513 |
case ISD::XOR: |
--- |
9513 |
case ISD::XOR: |
--- |
| 9514 |
case ISD::AND: |
--- |
9514 |
case ISD::AND: |
--- |
| 9515 |
break; |
0 |
9515 |
break; |
0 |
| 9516 |
case ISD::ADD: |
0 |
9516 |
case ISD::ADD: |
0 |
| 9517 |
if (N->getOpcode() != ISD::SHL) |
0 |
9517 |
if (N->getOpcode() != ISD::SHL) |
0 |
| 9518 |
return SDValue(); // only shl(add) not sr[al](add). |
0 |
9518 |
return SDValue(); // only shl(add) not sr[al](add). |
0 |
| 9519 |
break; |
0 |
9519 |
break; |
0 |
| 9520 |
} |
--- |
9520 |
} |
--- |
| 9521 |
|
--- |
9521 |
|
--- |
| 9522 |
// FIXME: disable this unless the input to the binop is a shift by a constant |
--- |
9522 |
// FIXME: disable this unless the input to the binop is a shift by a constant |
--- |
| 9523 |
// or is copy/select. Enable this in other cases when figure out it's exactly |
--- |
9523 |
// or is copy/select. Enable this in other cases when figure out it's exactly |
--- |
| 9524 |
// profitable. |
--- |
9524 |
// profitable. |
--- |
| 9525 |
SDValue BinOpLHSVal = LHS.getOperand(0); |
0 |
9525 |
SDValue BinOpLHSVal = LHS.getOperand(0); |
0 |
| 9526 |
bool IsShiftByConstant = (BinOpLHSVal.getOpcode() == ISD::SHL || |
0 |
9526 |
bool IsShiftByConstant = (BinOpLHSVal.getOpcode() == ISD::SHL || |
0 |
| 9527 |
BinOpLHSVal.getOpcode() == ISD::SRA || |
0 |
9527 |
BinOpLHSVal.getOpcode() == ISD::SRA || |
0 |
| 9528 |
BinOpLHSVal.getOpcode() == ISD::SRL) && |
0 |
9528 |
BinOpLHSVal.getOpcode() == ISD::SRL) && |
0 |
| 9529 |
isa(BinOpLHSVal.getOperand(1)); |
0 |
9529 |
isa(BinOpLHSVal.getOperand(1)); |
0 |
| 9530 |
bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg || |
0 |
9530 |
bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg || |
0 |
| 9531 |
BinOpLHSVal.getOpcode() == ISD::SELECT; |
0 |
9531 |
BinOpLHSVal.getOpcode() == ISD::SELECT; |
0 |
| 9532 |
|
--- |
9532 |
|
--- |
| 9533 |
if (!IsShiftByConstant && !IsCopyOrSelect) |
0 |
9533 |
if (!IsShiftByConstant && !IsCopyOrSelect) |
0 |
| 9534 |
return SDValue(); |
0 |
9534 |
return SDValue(); |
0 |
| 9535 |
|
--- |
9535 |
|
--- |
| 9536 |
if (IsCopyOrSelect && N->hasOneUse()) |
0 |
9536 |
if (IsCopyOrSelect && N->hasOneUse()) |
0 |
| 9537 |
return SDValue(); |
0 |
9537 |
return SDValue(); |
0 |
| 9538 |
|
--- |
9538 |
|
--- |
| 9539 |
// Attempt to fold the constants, shifting the binop RHS by the shift amount. |
--- |
9539 |
// Attempt to fold the constants, shifting the binop RHS by the shift amount. |
--- |
| 9540 |
SDLoc DL(N); |
0 |
9540 |
SDLoc DL(N); |
0 |
| 9541 |
EVT VT = N->getValueType(0); |
0 |
9541 |
EVT VT = N->getValueType(0); |
0 |
| 9542 |
if (SDValue NewRHS = DAG.FoldConstantArithmetic( |
0 |
9542 |
if (SDValue NewRHS = DAG.FoldConstantArithmetic( |
0 |
| 9543 |
N->getOpcode(), DL, VT, {LHS.getOperand(1), N->getOperand(1)})) { |
0 |
9543 |
N->getOpcode(), DL, VT, {LHS.getOperand(1), N->getOperand(1)})) { |
0 |
| 9544 |
SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), |
0 |
9544 |
SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), |
0 |
| 9545 |
N->getOperand(1)); |
0 |
9545 |
N->getOperand(1)); |
0 |
| 9546 |
return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); |
0 |
9546 |
return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); |
0 |
| 9547 |
} |
--- |
9547 |
} |
--- |
| 9548 |
|
--- |
9548 |
|
--- |
| 9549 |
return SDValue(); |
0 |
9549 |
return SDValue(); |
0 |
| 9550 |
} |
--- |
9550 |
} |
--- |
| 9551 |
|
--- |
9551 |
|
--- |
| 9552 |
SDValue DAGCombiner::distributeTruncateThroughAnd(SDNode *N) { |
0 |
9552 |
SDValue DAGCombiner::distributeTruncateThroughAnd(SDNode *N) { |
0 |
| 9553 |
assert(N->getOpcode() == ISD::TRUNCATE); |
0 |
9553 |
assert(N->getOpcode() == ISD::TRUNCATE); |
0 |
| 9554 |
assert(N->getOperand(0).getOpcode() == ISD::AND); |
0 |
9554 |
assert(N->getOperand(0).getOpcode() == ISD::AND); |
0 |
| 9555 |
|
--- |
9555 |
|
--- |
| 9556 |
// (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC) |
--- |
9556 |
// (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC) |
--- |
| 9557 |
EVT TruncVT = N->getValueType(0); |
0 |
9557 |
EVT TruncVT = N->getValueType(0); |
0 |
| 9558 |
if (N->hasOneUse() && N->getOperand(0).hasOneUse() && |
0 |
9558 |
if (N->hasOneUse() && N->getOperand(0).hasOneUse() && |
0 |
| 9559 |
TLI.isTypeDesirableForOp(ISD::AND, TruncVT)) { |
0 |
9559 |
TLI.isTypeDesirableForOp(ISD::AND, TruncVT)) { |
0 |
| 9560 |
SDValue N01 = N->getOperand(0).getOperand(1); |
0 |
9560 |
SDValue N01 = N->getOperand(0).getOperand(1); |
0 |
| 9561 |
if (isConstantOrConstantVector(N01, /* NoOpaques */ true)) { |
0 |
9561 |
if (isConstantOrConstantVector(N01, /* NoOpaques */ true)) { |
0 |
| 9562 |
SDLoc DL(N); |
0 |
9562 |
SDLoc DL(N); |
0 |
| 9563 |
SDValue N00 = N->getOperand(0).getOperand(0); |
0 |
9563 |
SDValue N00 = N->getOperand(0).getOperand(0); |
0 |
| 9564 |
SDValue Trunc00 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N00); |
0 |
9564 |
SDValue Trunc00 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N00); |
0 |
| 9565 |
SDValue Trunc01 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N01); |
0 |
9565 |
SDValue Trunc01 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N01); |
0 |
| 9566 |
AddToWorklist(Trunc00.getNode()); |
0 |
9566 |
AddToWorklist(Trunc00.getNode()); |
0 |
| 9567 |
AddToWorklist(Trunc01.getNode()); |
0 |
9567 |
AddToWorklist(Trunc01.getNode()); |
0 |
| 9568 |
return DAG.getNode(ISD::AND, DL, TruncVT, Trunc00, Trunc01); |
0 |
9568 |
return DAG.getNode(ISD::AND, DL, TruncVT, Trunc00, Trunc01); |
0 |
| 9569 |
} |
0 |
9569 |
} |
0 |
| 9570 |
} |
--- |
9570 |
} |
--- |
| 9571 |
|
--- |
9571 |
|
--- |
| 9572 |
return SDValue(); |
0 |
9572 |
return SDValue(); |
0 |
| 9573 |
} |
--- |
9573 |
} |
--- |
| 9574 |
|
--- |
9574 |
|
--- |
| 9575 |
SDValue DAGCombiner::visitRotate(SDNode *N) { |
0 |
9575 |
SDValue DAGCombiner::visitRotate(SDNode *N) { |
0 |
| 9576 |
SDLoc dl(N); |
0 |
9576 |
SDLoc dl(N); |
0 |
| 9577 |
SDValue N0 = N->getOperand(0); |
0 |
9577 |
SDValue N0 = N->getOperand(0); |
0 |
| 9578 |
SDValue N1 = N->getOperand(1); |
0 |
9578 |
SDValue N1 = N->getOperand(1); |
0 |
| 9579 |
EVT VT = N->getValueType(0); |
0 |
9579 |
EVT VT = N->getValueType(0); |
0 |
| 9580 |
unsigned Bitsize = VT.getScalarSizeInBits(); |
0 |
9580 |
unsigned Bitsize = VT.getScalarSizeInBits(); |
0 |
| 9581 |
|
--- |
9581 |
|
--- |
| 9582 |
// fold (rot x, 0) -> x |
--- |
9582 |
// fold (rot x, 0) -> x |
--- |
| 9583 |
if (isNullOrNullSplat(N1)) |
0 |
9583 |
if (isNullOrNullSplat(N1)) |
0 |
| 9584 |
return N0; |
0 |
9584 |
return N0; |
0 |
| 9585 |
|
--- |
9585 |
|
--- |
| 9586 |
// fold (rot x, c) -> x iff (c % BitSize) == 0 |
--- |
9586 |
// fold (rot x, c) -> x iff (c % BitSize) == 0 |
--- |
| 9587 |
if (isPowerOf2_32(Bitsize) && Bitsize > 1) { |
0 |
9587 |
if (isPowerOf2_32(Bitsize) && Bitsize > 1) { |
0 |
| 9588 |
APInt ModuloMask(N1.getScalarValueSizeInBits(), Bitsize - 1); |
0 |
9588 |
APInt ModuloMask(N1.getScalarValueSizeInBits(), Bitsize - 1); |
0 |
| 9589 |
if (DAG.MaskedValueIsZero(N1, ModuloMask)) |
0 |
9589 |
if (DAG.MaskedValueIsZero(N1, ModuloMask)) |
0 |
| 9590 |
return N0; |
0 |
9590 |
return N0; |
0 |
| 9591 |
} |
0 |
9591 |
} |
0 |
| 9592 |
|
--- |
9592 |
|
--- |
| 9593 |
// fold (rot x, c) -> (rot x, c % BitSize) |
--- |
9593 |
// fold (rot x, c) -> (rot x, c % BitSize) |
--- |
| 9594 |
bool OutOfRange = false; |
0 |
9594 |
bool OutOfRange = false; |
0 |
| 9595 |
auto MatchOutOfRange = [Bitsize, &OutOfRange](ConstantSDNode *C) { |
0 |
9595 |
auto MatchOutOfRange = [Bitsize, &OutOfRange](ConstantSDNode *C) { |
0 |
| 9596 |
OutOfRange |= C->getAPIntValue().uge(Bitsize); |
0 |
9596 |
OutOfRange |= C->getAPIntValue().uge(Bitsize); |
0 |
| 9597 |
return true; |
0 |
9597 |
return true; |
0 |
| 9598 |
}; |
0 |
9598 |
}; |
0 |
| 9599 |
if (ISD::matchUnaryPredicate(N1, MatchOutOfRange) && OutOfRange) { |
0 |
9599 |
if (ISD::matchUnaryPredicate(N1, MatchOutOfRange) && OutOfRange) { |
0 |
| 9600 |
EVT AmtVT = N1.getValueType(); |
0 |
9600 |
EVT AmtVT = N1.getValueType(); |
0 |
| 9601 |
SDValue Bits = DAG.getConstant(Bitsize, dl, AmtVT); |
0 |
9601 |
SDValue Bits = DAG.getConstant(Bitsize, dl, AmtVT); |
0 |
| 9602 |
if (SDValue Amt = |
0 |
9602 |
if (SDValue Amt = |
0 |
| 9603 |
DAG.FoldConstantArithmetic(ISD::UREM, dl, AmtVT, {N1, Bits})) |
0 |
9603 |
DAG.FoldConstantArithmetic(ISD::UREM, dl, AmtVT, {N1, Bits})) |
0 |
| 9604 |
return DAG.getNode(N->getOpcode(), dl, VT, N0, Amt); |
0 |
9604 |
return DAG.getNode(N->getOpcode(), dl, VT, N0, Amt); |
0 |
| 9605 |
} |
--- |
9605 |
} |
--- |
| 9606 |
|
--- |
9606 |
|
--- |
| 9607 |
// rot i16 X, 8 --> bswap X |
--- |
9607 |
// rot i16 X, 8 --> bswap X |
--- |
| 9608 |
auto *RotAmtC = isConstOrConstSplat(N1); |
0 |
9608 |
auto *RotAmtC = isConstOrConstSplat(N1); |
0 |
| 9609 |
if (RotAmtC && RotAmtC->getAPIntValue() == 8 && |
0 |
9609 |
if (RotAmtC && RotAmtC->getAPIntValue() == 8 && |
0 |
| 9610 |
VT.getScalarSizeInBits() == 16 && hasOperation(ISD::BSWAP, VT)) |
0 |
9610 |
VT.getScalarSizeInBits() == 16 && hasOperation(ISD::BSWAP, VT)) |
0 |
| 9611 |
return DAG.getNode(ISD::BSWAP, dl, VT, N0); |
0 |
9611 |
return DAG.getNode(ISD::BSWAP, dl, VT, N0); |
0 |
| 9612 |
|
--- |
9612 |
|
--- |
| 9613 |
// Simplify the operands using demanded-bits information. |
--- |
9613 |
// Simplify the operands using demanded-bits information. |
--- |
| 9614 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
9614 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
| 9615 |
return SDValue(N, 0); |
0 |
9615 |
return SDValue(N, 0); |
0 |
| 9616 |
|
--- |
9616 |
|
--- |
| 9617 |
// fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))). |
--- |
9617 |
// fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))). |
--- |
| 9618 |
if (N1.getOpcode() == ISD::TRUNCATE && |
0 |
9618 |
if (N1.getOpcode() == ISD::TRUNCATE && |
0 |
| 9619 |
N1.getOperand(0).getOpcode() == ISD::AND) { |
0 |
9619 |
N1.getOperand(0).getOpcode() == ISD::AND) { |
0 |
| 9620 |
if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode())) |
0 |
9620 |
if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode())) |
0 |
| 9621 |
return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1); |
0 |
9621 |
return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1); |
0 |
| 9622 |
} |
--- |
9622 |
} |
--- |
| 9623 |
|
--- |
9623 |
|
--- |
| 9624 |
unsigned NextOp = N0.getOpcode(); |
0 |
9624 |
unsigned NextOp = N0.getOpcode(); |
0 |
| 9625 |
|
--- |
9625 |
|
--- |
| 9626 |
// fold (rot* (rot* x, c2), c1) |
--- |
9626 |
// fold (rot* (rot* x, c2), c1) |
--- |
| 9627 |
// -> (rot* x, ((c1 % bitsize) +- (c2 % bitsize) + bitsize) % bitsize) |
--- |
9627 |
// -> (rot* x, ((c1 % bitsize) +- (c2 % bitsize) + bitsize) % bitsize) |
--- |
| 9628 |
if (NextOp == ISD::ROTL || NextOp == ISD::ROTR) { |
0 |
9628 |
if (NextOp == ISD::ROTL || NextOp == ISD::ROTR) { |
0 |
| 9629 |
SDNode *C1 = DAG.isConstantIntBuildVectorOrConstantInt(N1); |
0 |
9629 |
SDNode *C1 = DAG.isConstantIntBuildVectorOrConstantInt(N1); |
0 |
| 9630 |
SDNode *C2 = DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)); |
0 |
9630 |
SDNode *C2 = DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)); |
0 |
| 9631 |
if (C1 && C2 && C1->getValueType(0) == C2->getValueType(0)) { |
0 |
9631 |
if (C1 && C2 && C1->getValueType(0) == C2->getValueType(0)) { |
0 |
| 9632 |
EVT ShiftVT = C1->getValueType(0); |
0 |
9632 |
EVT ShiftVT = C1->getValueType(0); |
0 |
| 9633 |
bool SameSide = (N->getOpcode() == NextOp); |
0 |
9633 |
bool SameSide = (N->getOpcode() == NextOp); |
0 |
| 9634 |
unsigned CombineOp = SameSide ? ISD::ADD : ISD::SUB; |
0 |
9634 |
unsigned CombineOp = SameSide ? ISD::ADD : ISD::SUB; |
0 |
| 9635 |
SDValue BitsizeC = DAG.getConstant(Bitsize, dl, ShiftVT); |
0 |
9635 |
SDValue BitsizeC = DAG.getConstant(Bitsize, dl, ShiftVT); |
0 |
| 9636 |
SDValue Norm1 = DAG.FoldConstantArithmetic(ISD::UREM, dl, ShiftVT, |
0 |
9636 |
SDValue Norm1 = DAG.FoldConstantArithmetic(ISD::UREM, dl, ShiftVT, |
0 |
| 9637 |
{N1, BitsizeC}); |
--- |
9637 |
{N1, BitsizeC}); |
--- |
| 9638 |
SDValue Norm2 = DAG.FoldConstantArithmetic(ISD::UREM, dl, ShiftVT, |
0 |
9638 |
SDValue Norm2 = DAG.FoldConstantArithmetic(ISD::UREM, dl, ShiftVT, |
0 |
| 9639 |
{N0.getOperand(1), BitsizeC}); |
0 |
9639 |
{N0.getOperand(1), BitsizeC}); |
0 |
| 9640 |
if (Norm1 && Norm2) |
0 |
9640 |
if (Norm1 && Norm2) |
0 |
| 9641 |
if (SDValue CombinedShift = DAG.FoldConstantArithmetic( |
0 |
9641 |
if (SDValue CombinedShift = DAG.FoldConstantArithmetic( |
0 |
| 9642 |
CombineOp, dl, ShiftVT, {Norm1, Norm2})) { |
0 |
9642 |
CombineOp, dl, ShiftVT, {Norm1, Norm2})) { |
0 |
| 9643 |
CombinedShift = DAG.FoldConstantArithmetic(ISD::ADD, dl, ShiftVT, |
0 |
9643 |
CombinedShift = DAG.FoldConstantArithmetic(ISD::ADD, dl, ShiftVT, |
0 |
| 9644 |
{CombinedShift, BitsizeC}); |
--- |
9644 |
{CombinedShift, BitsizeC}); |
--- |
| 9645 |
SDValue CombinedShiftNorm = DAG.FoldConstantArithmetic( |
0 |
9645 |
SDValue CombinedShiftNorm = DAG.FoldConstantArithmetic( |
0 |
| 9646 |
ISD::UREM, dl, ShiftVT, {CombinedShift, BitsizeC}); |
--- |
9646 |
ISD::UREM, dl, ShiftVT, {CombinedShift, BitsizeC}); |
--- |
| 9647 |
return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0), |
0 |
9647 |
return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0), |
0 |
| 9648 |
CombinedShiftNorm); |
0 |
9648 |
CombinedShiftNorm); |
0 |
| 9649 |
} |
--- |
9649 |
} |
--- |
| 9650 |
} |
--- |
9650 |
} |
--- |
| 9651 |
} |
--- |
9651 |
} |
--- |
| 9652 |
return SDValue(); |
0 |
9652 |
return SDValue(); |
0 |
| 9653 |
} |
0 |
9653 |
} |
0 |
| 9654 |
|
--- |
9654 |
|
--- |
| 9655 |
SDValue DAGCombiner::visitSHL(SDNode *N) { |
0 |
9655 |
SDValue DAGCombiner::visitSHL(SDNode *N) { |
0 |
| 9656 |
SDValue N0 = N->getOperand(0); |
0 |
9656 |
SDValue N0 = N->getOperand(0); |
0 |
| 9657 |
SDValue N1 = N->getOperand(1); |
0 |
9657 |
SDValue N1 = N->getOperand(1); |
0 |
| 9658 |
if (SDValue V = DAG.simplifyShift(N0, N1)) |
0 |
9658 |
if (SDValue V = DAG.simplifyShift(N0, N1)) |
0 |
| 9659 |
return V; |
0 |
9659 |
return V; |
0 |
| 9660 |
|
--- |
9660 |
|
--- |
| 9661 |
EVT VT = N0.getValueType(); |
0 |
9661 |
EVT VT = N0.getValueType(); |
0 |
| 9662 |
EVT ShiftVT = N1.getValueType(); |
0 |
9662 |
EVT ShiftVT = N1.getValueType(); |
0 |
| 9663 |
unsigned OpSizeInBits = VT.getScalarSizeInBits(); |
0 |
9663 |
unsigned OpSizeInBits = VT.getScalarSizeInBits(); |
0 |
| 9664 |
|
--- |
9664 |
|
--- |
| 9665 |
// fold (shl c1, c2) -> c1<
| --- |
9665 |
// fold (shl c1, c2) -> c1<
| --- |
| |
| 9666 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT, {N0, N1})) |
0 |
9666 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT, {N0, N1})) |
0 |
| 9667 |
return C; |
0 |
9667 |
return C; |
0 |
| 9668 |
|
--- |
9668 |
|
--- |
| 9669 |
// fold vector ops |
--- |
9669 |
// fold vector ops |
--- |
| 9670 |
if (VT.isVector()) { |
0 |
9670 |
if (VT.isVector()) { |
0 |
| 9671 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N))) |
0 |
9671 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N))) |
0 |
| 9672 |
return FoldedVOp; |
0 |
9672 |
return FoldedVOp; |
0 |
| 9673 |
|
--- |
9673 |
|
--- |
| 9674 |
BuildVectorSDNode *N1CV = dyn_cast(N1); |
0 |
9674 |
BuildVectorSDNode *N1CV = dyn_cast(N1); |
0 |
| 9675 |
// If setcc produces all-one true value then: |
--- |
9675 |
// If setcc produces all-one true value then: |
--- |
| 9676 |
// (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<
| --- |
9676 |
// (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<
| --- |
| |
| 9677 |
if (N1CV && N1CV->isConstant()) { |
0 |
9677 |
if (N1CV && N1CV->isConstant()) { |
0 |
| 9678 |
if (N0.getOpcode() == ISD::AND) { |
0 |
9678 |
if (N0.getOpcode() == ISD::AND) { |
0 |
| 9679 |
SDValue N00 = N0->getOperand(0); |
0 |
9679 |
SDValue N00 = N0->getOperand(0); |
0 |
| 9680 |
SDValue N01 = N0->getOperand(1); |
0 |
9680 |
SDValue N01 = N0->getOperand(1); |
0 |
| 9681 |
BuildVectorSDNode *N01CV = dyn_cast(N01); |
0 |
9681 |
BuildVectorSDNode *N01CV = dyn_cast(N01); |
0 |
| 9682 |
|
--- |
9682 |
|
--- |
| 9683 |
if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC && |
0 |
9683 |
if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC && |
0 |
| 9684 |
TLI.getBooleanContents(N00.getOperand(0).getValueType()) == |
0 |
9684 |
TLI.getBooleanContents(N00.getOperand(0).getValueType()) == |
0 |
| 9685 |
TargetLowering::ZeroOrNegativeOneBooleanContent) { |
--- |
9685 |
TargetLowering::ZeroOrNegativeOneBooleanContent) { |
--- |
| 9686 |
if (SDValue C = |
0 |
9686 |
if (SDValue C = |
0 |
| 9687 |
DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT, {N01, N1})) |
0 |
9687 |
DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT, {N01, N1})) |
0 |
| 9688 |
return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C); |
0 |
9688 |
return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C); |
0 |
| 9689 |
} |
--- |
9689 |
} |
--- |
| 9690 |
} |
--- |
9690 |
} |
--- |
| 9691 |
} |
--- |
9691 |
} |
--- |
| 9692 |
} |
--- |
9692 |
} |
--- |
| 9693 |
|
--- |
9693 |
|
--- |
| 9694 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
9694 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 9695 |
return NewSel; |
0 |
9695 |
return NewSel; |
0 |
| 9696 |
|
--- |
9696 |
|
--- |
| 9697 |
// if (shl x, c) is known to be zero, return 0 |
--- |
9697 |
// if (shl x, c) is known to be zero, return 0 |
--- |
| 9698 |
if (DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(OpSizeInBits))) |
0 |
9698 |
if (DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(OpSizeInBits))) |
0 |
| 9699 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
9699 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
| 9700 |
|
--- |
9700 |
|
--- |
| 9701 |
// fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). |
--- |
9701 |
// fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). |
--- |
| 9702 |
if (N1.getOpcode() == ISD::TRUNCATE && |
0 |
9702 |
if (N1.getOpcode() == ISD::TRUNCATE && |
0 |
| 9703 |
N1.getOperand(0).getOpcode() == ISD::AND) { |
0 |
9703 |
N1.getOperand(0).getOpcode() == ISD::AND) { |
0 |
| 9704 |
if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode())) |
0 |
9704 |
if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode())) |
0 |
| 9705 |
return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1); |
0 |
9705 |
return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1); |
0 |
| 9706 |
} |
--- |
9706 |
} |
--- |
| 9707 |
|
--- |
9707 |
|
--- |
| 9708 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
9708 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
| 9709 |
return SDValue(N, 0); |
0 |
9709 |
return SDValue(N, 0); |
0 |
| 9710 |
|
--- |
9710 |
|
--- |
| 9711 |
// fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) |
--- |
9711 |
// fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) |
--- |
| 9712 |
if (N0.getOpcode() == ISD::SHL) { |
0 |
9712 |
if (N0.getOpcode() == ISD::SHL) { |
0 |
| 9713 |
auto MatchOutOfRange = [OpSizeInBits](ConstantSDNode *LHS, |
0 |
9713 |
auto MatchOutOfRange = [OpSizeInBits](ConstantSDNode *LHS, |
0 |
| 9714 |
ConstantSDNode *RHS) { |
0 |
9714 |
ConstantSDNode *RHS) { |
0 |
| 9715 |
APInt c1 = LHS->getAPIntValue(); |
0 |
9715 |
APInt c1 = LHS->getAPIntValue(); |
0 |
| 9716 |
APInt c2 = RHS->getAPIntValue(); |
0 |
9716 |
APInt c2 = RHS->getAPIntValue(); |
0 |
| 9717 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
9717 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
| 9718 |
return (c1 + c2).uge(OpSizeInBits); |
0 |
9718 |
return (c1 + c2).uge(OpSizeInBits); |
0 |
| 9719 |
}; |
0 |
9719 |
}; |
0 |
| 9720 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange)) |
0 |
9720 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange)) |
0 |
| 9721 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
9721 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
| 9722 |
|
--- |
9722 |
|
--- |
| 9723 |
auto MatchInRange = [OpSizeInBits](ConstantSDNode *LHS, |
0 |
9723 |
auto MatchInRange = [OpSizeInBits](ConstantSDNode *LHS, |
0 |
| 9724 |
ConstantSDNode *RHS) { |
0 |
9724 |
ConstantSDNode *RHS) { |
0 |
| 9725 |
APInt c1 = LHS->getAPIntValue(); |
0 |
9725 |
APInt c1 = LHS->getAPIntValue(); |
0 |
| 9726 |
APInt c2 = RHS->getAPIntValue(); |
0 |
9726 |
APInt c2 = RHS->getAPIntValue(); |
0 |
| 9727 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
9727 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
| 9728 |
return (c1 + c2).ult(OpSizeInBits); |
0 |
9728 |
return (c1 + c2).ult(OpSizeInBits); |
0 |
| 9729 |
}; |
0 |
9729 |
}; |
0 |
| 9730 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) { |
0 |
9730 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) { |
0 |
| 9731 |
SDLoc DL(N); |
0 |
9731 |
SDLoc DL(N); |
0 |
| 9732 |
SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1)); |
0 |
9732 |
SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1)); |
0 |
| 9733 |
return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Sum); |
0 |
9733 |
return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Sum); |
0 |
| 9734 |
} |
0 |
9734 |
} |
0 |
| 9735 |
} |
--- |
9735 |
} |
--- |
| 9736 |
|
--- |
9736 |
|
--- |
| 9737 |
// fold (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) |
--- |
9737 |
// fold (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) |
--- |
| 9738 |
// For this to be valid, the second form must not preserve any of the bits |
--- |
9738 |
// For this to be valid, the second form must not preserve any of the bits |
--- |
| 9739 |
// that are shifted out by the inner shift in the first form. This means |
--- |
9739 |
// that are shifted out by the inner shift in the first form. This means |
--- |
| 9740 |
// the outer shift size must be >= the number of bits added by the ext. |
--- |
9740 |
// the outer shift size must be >= the number of bits added by the ext. |
--- |
| 9741 |
// As a corollary, we don't care what kind of ext it is. |
--- |
9741 |
// As a corollary, we don't care what kind of ext it is. |
--- |
| 9742 |
if ((N0.getOpcode() == ISD::ZERO_EXTEND || |
0 |
9742 |
if ((N0.getOpcode() == ISD::ZERO_EXTEND || |
0 |
| 9743 |
N0.getOpcode() == ISD::ANY_EXTEND || |
0 |
9743 |
N0.getOpcode() == ISD::ANY_EXTEND || |
0 |
| 9744 |
N0.getOpcode() == ISD::SIGN_EXTEND) && |
0 |
9744 |
N0.getOpcode() == ISD::SIGN_EXTEND) && |
0 |
| 9745 |
N0.getOperand(0).getOpcode() == ISD::SHL) { |
0 |
9745 |
N0.getOperand(0).getOpcode() == ISD::SHL) { |
0 |
| 9746 |
SDValue N0Op0 = N0.getOperand(0); |
0 |
9746 |
SDValue N0Op0 = N0.getOperand(0); |
0 |
| 9747 |
SDValue InnerShiftAmt = N0Op0.getOperand(1); |
0 |
9747 |
SDValue InnerShiftAmt = N0Op0.getOperand(1); |
0 |
| 9748 |
EVT InnerVT = N0Op0.getValueType(); |
0 |
9748 |
EVT InnerVT = N0Op0.getValueType(); |
0 |
| 9749 |
uint64_t InnerBitwidth = InnerVT.getScalarSizeInBits(); |
0 |
9749 |
uint64_t InnerBitwidth = InnerVT.getScalarSizeInBits(); |
0 |
| 9750 |
|
--- |
9750 |
|
--- |
| 9751 |
auto MatchOutOfRange = [OpSizeInBits, InnerBitwidth](ConstantSDNode *LHS, |
0 |
9751 |
auto MatchOutOfRange = [OpSizeInBits, InnerBitwidth](ConstantSDNode *LHS, |
0 |
| 9752 |
ConstantSDNode *RHS) { |
0 |
9752 |
ConstantSDNode *RHS) { |
0 |
| 9753 |
APInt c1 = LHS->getAPIntValue(); |
0 |
9753 |
APInt c1 = LHS->getAPIntValue(); |
0 |
| 9754 |
APInt c2 = RHS->getAPIntValue(); |
0 |
9754 |
APInt c2 = RHS->getAPIntValue(); |
0 |
| 9755 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
9755 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
| 9756 |
return c2.uge(OpSizeInBits - InnerBitwidth) && |
0 |
9756 |
return c2.uge(OpSizeInBits - InnerBitwidth) && |
0 |
| 9757 |
(c1 + c2).uge(OpSizeInBits); |
0 |
9757 |
(c1 + c2).uge(OpSizeInBits); |
0 |
| 9758 |
}; |
0 |
9758 |
}; |
0 |
| 9759 |
if (ISD::matchBinaryPredicate(InnerShiftAmt, N1, MatchOutOfRange, |
0 |
9759 |
if (ISD::matchBinaryPredicate(InnerShiftAmt, N1, MatchOutOfRange, |
0 |
| 9760 |
/*AllowUndefs*/ false, |
--- |
9760 |
/*AllowUndefs*/ false, |
--- |
| 9761 |
/*AllowTypeMismatch*/ true)) |
--- |
9761 |
/*AllowTypeMismatch*/ true)) |
--- |
| 9762 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
9762 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
| 9763 |
|
--- |
9763 |
|
--- |
| 9764 |
auto MatchInRange = [OpSizeInBits, InnerBitwidth](ConstantSDNode *LHS, |
0 |
9764 |
auto MatchInRange = [OpSizeInBits, InnerBitwidth](ConstantSDNode *LHS, |
0 |
| 9765 |
ConstantSDNode *RHS) { |
0 |
9765 |
ConstantSDNode *RHS) { |
0 |
| 9766 |
APInt c1 = LHS->getAPIntValue(); |
0 |
9766 |
APInt c1 = LHS->getAPIntValue(); |
0 |
| 9767 |
APInt c2 = RHS->getAPIntValue(); |
0 |
9767 |
APInt c2 = RHS->getAPIntValue(); |
0 |
| 9768 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
9768 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
| 9769 |
return c2.uge(OpSizeInBits - InnerBitwidth) && |
0 |
9769 |
return c2.uge(OpSizeInBits - InnerBitwidth) && |
0 |
| 9770 |
(c1 + c2).ult(OpSizeInBits); |
0 |
9770 |
(c1 + c2).ult(OpSizeInBits); |
0 |
| 9771 |
}; |
0 |
9771 |
}; |
0 |
| 9772 |
if (ISD::matchBinaryPredicate(InnerShiftAmt, N1, MatchInRange, |
0 |
9772 |
if (ISD::matchBinaryPredicate(InnerShiftAmt, N1, MatchInRange, |
0 |
| 9773 |
/*AllowUndefs*/ false, |
--- |
9773 |
/*AllowUndefs*/ false, |
--- |
| 9774 |
/*AllowTypeMismatch*/ true)) { |
--- |
9774 |
/*AllowTypeMismatch*/ true)) { |
--- |
| 9775 |
SDLoc DL(N); |
0 |
9775 |
SDLoc DL(N); |
0 |
| 9776 |
SDValue Ext = DAG.getNode(N0.getOpcode(), DL, VT, N0Op0.getOperand(0)); |
0 |
9776 |
SDValue Ext = DAG.getNode(N0.getOpcode(), DL, VT, N0Op0.getOperand(0)); |
0 |
| 9777 |
SDValue Sum = DAG.getZExtOrTrunc(InnerShiftAmt, DL, ShiftVT); |
0 |
9777 |
SDValue Sum = DAG.getZExtOrTrunc(InnerShiftAmt, DL, ShiftVT); |
0 |
| 9778 |
Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, Sum, N1); |
0 |
9778 |
Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, Sum, N1); |
0 |
| 9779 |
return DAG.getNode(ISD::SHL, DL, VT, Ext, Sum); |
0 |
9779 |
return DAG.getNode(ISD::SHL, DL, VT, Ext, Sum); |
0 |
| 9780 |
} |
0 |
9780 |
} |
0 |
| 9781 |
} |
--- |
9781 |
} |
--- |
| 9782 |
|
--- |
9782 |
|
--- |
| 9783 |
// fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C)) |
--- |
9783 |
// fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C)) |
--- |
| 9784 |
// Only fold this if the inner zext has no other uses to avoid increasing |
--- |
9784 |
// Only fold this if the inner zext has no other uses to avoid increasing |
--- |
| 9785 |
// the total number of instructions. |
--- |
9785 |
// the total number of instructions. |
--- |
| 9786 |
if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() && |
0 |
9786 |
if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() && |
0 |
| 9787 |
N0.getOperand(0).getOpcode() == ISD::SRL) { |
0 |
9787 |
N0.getOperand(0).getOpcode() == ISD::SRL) { |
0 |
| 9788 |
SDValue N0Op0 = N0.getOperand(0); |
0 |
9788 |
SDValue N0Op0 = N0.getOperand(0); |
0 |
| 9789 |
SDValue InnerShiftAmt = N0Op0.getOperand(1); |
0 |
9789 |
SDValue InnerShiftAmt = N0Op0.getOperand(1); |
0 |
| 9790 |
|
--- |
9790 |
|
--- |
| 9791 |
auto MatchEqual = [VT](ConstantSDNode *LHS, ConstantSDNode *RHS) { |
0 |
9791 |
auto MatchEqual = [VT](ConstantSDNode *LHS, ConstantSDNode *RHS) { |
0 |
| 9792 |
APInt c1 = LHS->getAPIntValue(); |
0 |
9792 |
APInt c1 = LHS->getAPIntValue(); |
0 |
| 9793 |
APInt c2 = RHS->getAPIntValue(); |
0 |
9793 |
APInt c2 = RHS->getAPIntValue(); |
0 |
| 9794 |
zeroExtendToMatch(c1, c2); |
0 |
9794 |
zeroExtendToMatch(c1, c2); |
0 |
| 9795 |
return c1.ult(VT.getScalarSizeInBits()) && (c1 == c2); |
0 |
9795 |
return c1.ult(VT.getScalarSizeInBits()) && (c1 == c2); |
0 |
| 9796 |
}; |
0 |
9796 |
}; |
0 |
| 9797 |
if (ISD::matchBinaryPredicate(InnerShiftAmt, N1, MatchEqual, |
0 |
9797 |
if (ISD::matchBinaryPredicate(InnerShiftAmt, N1, MatchEqual, |
0 |
| 9798 |
/*AllowUndefs*/ false, |
--- |
9798 |
/*AllowUndefs*/ false, |
--- |
| 9799 |
/*AllowTypeMismatch*/ true)) { |
--- |
9799 |
/*AllowTypeMismatch*/ true)) { |
--- |
| 9800 |
SDLoc DL(N); |
0 |
9800 |
SDLoc DL(N); |
0 |
| 9801 |
EVT InnerShiftAmtVT = N0Op0.getOperand(1).getValueType(); |
0 |
9801 |
EVT InnerShiftAmtVT = N0Op0.getOperand(1).getValueType(); |
0 |
| 9802 |
SDValue NewSHL = DAG.getZExtOrTrunc(N1, DL, InnerShiftAmtVT); |
0 |
9802 |
SDValue NewSHL = DAG.getZExtOrTrunc(N1, DL, InnerShiftAmtVT); |
0 |
| 9803 |
NewSHL = DAG.getNode(ISD::SHL, DL, N0Op0.getValueType(), N0Op0, NewSHL); |
0 |
9803 |
NewSHL = DAG.getNode(ISD::SHL, DL, N0Op0.getValueType(), N0Op0, NewSHL); |
0 |
| 9804 |
AddToWorklist(NewSHL.getNode()); |
0 |
9804 |
AddToWorklist(NewSHL.getNode()); |
0 |
| 9805 |
return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL); |
0 |
9805 |
return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL); |
0 |
| 9806 |
} |
0 |
9806 |
} |
0 |
| 9807 |
} |
--- |
9807 |
} |
--- |
| 9808 |
|
--- |
9808 |
|
--- |
| 9809 |
if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) { |
0 |
9809 |
if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) { |
0 |
| 9810 |
auto MatchShiftAmount = [OpSizeInBits](ConstantSDNode *LHS, |
0 |
9810 |
auto MatchShiftAmount = [OpSizeInBits](ConstantSDNode *LHS, |
0 |
| 9811 |
ConstantSDNode *RHS) { |
0 |
9811 |
ConstantSDNode *RHS) { |
0 |
| 9812 |
const APInt &LHSC = LHS->getAPIntValue(); |
0 |
9812 |
const APInt &LHSC = LHS->getAPIntValue(); |
0 |
| 9813 |
const APInt &RHSC = RHS->getAPIntValue(); |
0 |
9813 |
const APInt &RHSC = RHS->getAPIntValue(); |
0 |
| 9814 |
return LHSC.ult(OpSizeInBits) && RHSC.ult(OpSizeInBits) && |
0 |
9814 |
return LHSC.ult(OpSizeInBits) && RHSC.ult(OpSizeInBits) && |
0 |
| 9815 |
LHSC.getZExtValue() <= RHSC.getZExtValue(); |
0 |
9815 |
LHSC.getZExtValue() <= RHSC.getZExtValue(); |
0 |
| 9816 |
}; |
0 |
9816 |
}; |
0 |
| 9817 |
|
--- |
9817 |
|
--- |
| 9818 |
SDLoc DL(N); |
0 |
9818 |
SDLoc DL(N); |
0 |
| 9819 |
|
--- |
9819 |
|
--- |
| 9820 |
// fold (shl (sr[la] exact X, C1), C2) -> (shl X, (C2-C1)) if C1 <= C2 |
--- |
9820 |
// fold (shl (sr[la] exact X, C1), C2) -> (shl X, (C2-C1)) if C1 <= C2 |
--- |
| 9821 |
// fold (shl (sr[la] exact X, C1), C2) -> (sr[la] X, (C2-C1)) if C1 >= C2 |
--- |
9821 |
// fold (shl (sr[la] exact X, C1), C2) -> (sr[la] X, (C2-C1)) if C1 >= C2 |
--- |
| 9822 |
if (N0->getFlags().hasExact()) { |
0 |
9822 |
if (N0->getFlags().hasExact()) { |
0 |
| 9823 |
if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount, |
0 |
9823 |
if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount, |
0 |
| 9824 |
/*AllowUndefs*/ false, |
--- |
9824 |
/*AllowUndefs*/ false, |
--- |
| 9825 |
/*AllowTypeMismatch*/ true)) { |
--- |
9825 |
/*AllowTypeMismatch*/ true)) { |
--- |
| 9826 |
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT); |
0 |
9826 |
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT); |
0 |
| 9827 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N1, N01); |
0 |
9827 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N1, N01); |
0 |
| 9828 |
return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff); |
0 |
9828 |
return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff); |
0 |
| 9829 |
} |
--- |
9829 |
} |
--- |
| 9830 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount, |
0 |
9830 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount, |
0 |
| 9831 |
/*AllowUndefs*/ false, |
--- |
9831 |
/*AllowUndefs*/ false, |
--- |
| 9832 |
/*AllowTypeMismatch*/ true)) { |
--- |
9832 |
/*AllowTypeMismatch*/ true)) { |
--- |
| 9833 |
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT); |
0 |
9833 |
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT); |
0 |
| 9834 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N01, N1); |
0 |
9834 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N01, N1); |
0 |
| 9835 |
return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Diff); |
0 |
9835 |
return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Diff); |
0 |
| 9836 |
} |
--- |
9836 |
} |
--- |
| 9837 |
} |
--- |
9837 |
} |
--- |
| 9838 |
|
--- |
9838 |
|
--- |
| 9839 |
// fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or |
--- |
9839 |
// fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or |
--- |
| 9840 |
// (and (srl x, (sub c1, c2), MASK) |
--- |
9840 |
// (and (srl x, (sub c1, c2), MASK) |
--- |
| 9841 |
// Only fold this if the inner shift has no other uses -- if it does, |
--- |
9841 |
// Only fold this if the inner shift has no other uses -- if it does, |
--- |
| 9842 |
// folding this will increase the total number of instructions. |
--- |
9842 |
// folding this will increase the total number of instructions. |
--- |
| 9843 |
if (N0.getOpcode() == ISD::SRL && |
0 |
9843 |
if (N0.getOpcode() == ISD::SRL && |
0 |
| 9844 |
(N0.getOperand(1) == N1 || N0.hasOneUse()) && |
0 |
9844 |
(N0.getOperand(1) == N1 || N0.hasOneUse()) && |
0 |
| 9845 |
TLI.shouldFoldConstantShiftPairToMask(N, Level)) { |
0 |
9845 |
TLI.shouldFoldConstantShiftPairToMask(N, Level)) { |
0 |
| 9846 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount, |
0 |
9846 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount, |
0 |
| 9847 |
/*AllowUndefs*/ false, |
--- |
9847 |
/*AllowUndefs*/ false, |
--- |
| 9848 |
/*AllowTypeMismatch*/ true)) { |
--- |
9848 |
/*AllowTypeMismatch*/ true)) { |
--- |
| 9849 |
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT); |
0 |
9849 |
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT); |
0 |
| 9850 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N01, N1); |
0 |
9850 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N01, N1); |
0 |
| 9851 |
SDValue Mask = DAG.getAllOnesConstant(DL, VT); |
0 |
9851 |
SDValue Mask = DAG.getAllOnesConstant(DL, VT); |
0 |
| 9852 |
Mask = DAG.getNode(ISD::SHL, DL, VT, Mask, N01); |
0 |
9852 |
Mask = DAG.getNode(ISD::SHL, DL, VT, Mask, N01); |
0 |
| 9853 |
Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, Diff); |
0 |
9853 |
Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, Diff); |
0 |
| 9854 |
SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff); |
0 |
9854 |
SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff); |
0 |
| 9855 |
return DAG.getNode(ISD::AND, DL, VT, Shift, Mask); |
0 |
9855 |
return DAG.getNode(ISD::AND, DL, VT, Shift, Mask); |
0 |
| 9856 |
} |
--- |
9856 |
} |
--- |
| 9857 |
if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount, |
0 |
9857 |
if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount, |
0 |
| 9858 |
/*AllowUndefs*/ false, |
--- |
9858 |
/*AllowUndefs*/ false, |
--- |
| 9859 |
/*AllowTypeMismatch*/ true)) { |
--- |
9859 |
/*AllowTypeMismatch*/ true)) { |
--- |
| 9860 |
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT); |
0 |
9860 |
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT); |
0 |
| 9861 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N1, N01); |
0 |
9861 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N1, N01); |
0 |
| 9862 |
SDValue Mask = DAG.getAllOnesConstant(DL, VT); |
0 |
9862 |
SDValue Mask = DAG.getAllOnesConstant(DL, VT); |
0 |
| 9863 |
Mask = DAG.getNode(ISD::SHL, DL, VT, Mask, N1); |
0 |
9863 |
Mask = DAG.getNode(ISD::SHL, DL, VT, Mask, N1); |
0 |
| 9864 |
SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff); |
0 |
9864 |
SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff); |
0 |
| 9865 |
return DAG.getNode(ISD::AND, DL, VT, Shift, Mask); |
0 |
9865 |
return DAG.getNode(ISD::AND, DL, VT, Shift, Mask); |
0 |
| 9866 |
} |
--- |
9866 |
} |
--- |
| 9867 |
} |
--- |
9867 |
} |
--- |
| 9868 |
} |
0 |
9868 |
} |
0 |
| 9869 |
|
--- |
9869 |
|
--- |
| 9870 |
// fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) |
--- |
9870 |
// fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) |
--- |
| 9871 |
if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) && |
0 |
9871 |
if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) && |
0 |
| 9872 |
isConstantOrConstantVector(N1, /* No Opaques */ true)) { |
0 |
9872 |
isConstantOrConstantVector(N1, /* No Opaques */ true)) { |
0 |
| 9873 |
SDLoc DL(N); |
0 |
9873 |
SDLoc DL(N); |
0 |
| 9874 |
SDValue AllBits = DAG.getAllOnesConstant(DL, VT); |
0 |
9874 |
SDValue AllBits = DAG.getAllOnesConstant(DL, VT); |
0 |
| 9875 |
SDValue HiBitsMask = DAG.getNode(ISD::SHL, DL, VT, AllBits, N1); |
0 |
9875 |
SDValue HiBitsMask = DAG.getNode(ISD::SHL, DL, VT, AllBits, N1); |
0 |
| 9876 |
return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), HiBitsMask); |
0 |
9876 |
return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), HiBitsMask); |
0 |
| 9877 |
} |
0 |
9877 |
} |
0 |
| 9878 |
|
--- |
9878 |
|
--- |
| 9879 |
// fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) |
--- |
9879 |
// fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) |
--- |
| 9880 |
// fold (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) |
--- |
9880 |
// fold (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) |
--- |
| 9881 |
// Variant of version done on multiply, except mul by a power of 2 is turned |
--- |
9881 |
// Variant of version done on multiply, except mul by a power of 2 is turned |
--- |
| 9882 |
// into a shift. |
--- |
9882 |
// into a shift. |
--- |
| 9883 |
if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) && |
0 |
9883 |
if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) && |
0 |
| 9884 |
N0->hasOneUse() && |
0 |
9884 |
N0->hasOneUse() && |
0 |
| 9885 |
isConstantOrConstantVector(N1, /* No Opaques */ true) && |
0 |
9885 |
isConstantOrConstantVector(N1, /* No Opaques */ true) && |
0 |
| 9886 |
isConstantOrConstantVector(N0.getOperand(1), /* No Opaques */ true) && |
0 |
9886 |
isConstantOrConstantVector(N0.getOperand(1), /* No Opaques */ true) && |
0 |
| 9887 |
TLI.isDesirableToCommuteWithShift(N, Level)) { |
0 |
9887 |
TLI.isDesirableToCommuteWithShift(N, Level)) { |
0 |
| 9888 |
SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1); |
0 |
9888 |
SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1); |
0 |
| 9889 |
SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1); |
0 |
9889 |
SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1); |
0 |
| 9890 |
AddToWorklist(Shl0.getNode()); |
0 |
9890 |
AddToWorklist(Shl0.getNode()); |
0 |
| 9891 |
AddToWorklist(Shl1.getNode()); |
0 |
9891 |
AddToWorklist(Shl1.getNode()); |
0 |
| 9892 |
return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Shl0, Shl1); |
0 |
9892 |
return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Shl0, Shl1); |
0 |
| 9893 |
} |
--- |
9893 |
} |
--- |
| 9894 |
|
--- |
9894 |
|
--- |
| 9895 |
// fold (shl (mul x, c1), c2) -> (mul x, c1 << c2) |
--- |
9895 |
// fold (shl (mul x, c1), c2) -> (mul x, c1 << c2) |
--- |
| 9896 |
if (N0.getOpcode() == ISD::MUL && N0->hasOneUse()) { |
0 |
9896 |
if (N0.getOpcode() == ISD::MUL && N0->hasOneUse()) { |
0 |
| 9897 |
SDValue N01 = N0.getOperand(1); |
0 |
9897 |
SDValue N01 = N0.getOperand(1); |
0 |
| 9898 |
if (SDValue Shl = |
0 |
9898 |
if (SDValue Shl = |
0 |
| 9899 |
DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N1), VT, {N01, N1})) |
0 |
9899 |
DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N1), VT, {N01, N1})) |
0 |
| 9900 |
return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), Shl); |
0 |
9900 |
return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), Shl); |
0 |
| 9901 |
} |
--- |
9901 |
} |
--- |
| 9902 |
|
--- |
9902 |
|
--- |
| 9903 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
9903 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
| 9904 |
if (N1C && !N1C->isOpaque()) |
0 |
9904 |
if (N1C && !N1C->isOpaque()) |
0 |
| 9905 |
if (SDValue NewSHL = visitShiftByConstant(N)) |
0 |
9905 |
if (SDValue NewSHL = visitShiftByConstant(N)) |
0 |
| 9906 |
return NewSHL; |
0 |
9906 |
return NewSHL; |
0 |
| 9907 |
|
--- |
9907 |
|
--- |
| 9908 |
// Fold (shl (vscale * C0), C1) to (vscale * (C0 << C1)). |
--- |
9908 |
// Fold (shl (vscale * C0), C1) to (vscale * (C0 << C1)). |
--- |
| 9909 |
if (N0.getOpcode() == ISD::VSCALE && N1C) { |
0 |
9909 |
if (N0.getOpcode() == ISD::VSCALE && N1C) { |
0 |
| 9910 |
const APInt &C0 = N0.getConstantOperandAPInt(0); |
0 |
9910 |
const APInt &C0 = N0.getConstantOperandAPInt(0); |
0 |
| 9911 |
const APInt &C1 = N1C->getAPIntValue(); |
0 |
9911 |
const APInt &C1 = N1C->getAPIntValue(); |
0 |
| 9912 |
return DAG.getVScale(SDLoc(N), VT, C0 << C1); |
0 |
9912 |
return DAG.getVScale(SDLoc(N), VT, C0 << C1); |
0 |
| 9913 |
} |
--- |
9913 |
} |
--- |
| 9914 |
|
--- |
9914 |
|
--- |
| 9915 |
// Fold (shl step_vector(C0), C1) to (step_vector(C0 << C1)). |
--- |
9915 |
// Fold (shl step_vector(C0), C1) to (step_vector(C0 << C1)). |
--- |
| 9916 |
APInt ShlVal; |
0 |
9916 |
APInt ShlVal; |
0 |
| 9917 |
if (N0.getOpcode() == ISD::STEP_VECTOR && |
0 |
9917 |
if (N0.getOpcode() == ISD::STEP_VECTOR && |
0 |
| 9918 |
ISD::isConstantSplatVector(N1.getNode(), ShlVal)) { |
0 |
9918 |
ISD::isConstantSplatVector(N1.getNode(), ShlVal)) { |
0 |
| 9919 |
const APInt &C0 = N0.getConstantOperandAPInt(0); |
0 |
9919 |
const APInt &C0 = N0.getConstantOperandAPInt(0); |
0 |
| 9920 |
if (ShlVal.ult(C0.getBitWidth())) { |
0 |
9920 |
if (ShlVal.ult(C0.getBitWidth())) { |
0 |
| 9921 |
APInt NewStep = C0 << ShlVal; |
0 |
9921 |
APInt NewStep = C0 << ShlVal; |
0 |
| 9922 |
return DAG.getStepVector(SDLoc(N), VT, NewStep); |
0 |
9922 |
return DAG.getStepVector(SDLoc(N), VT, NewStep); |
0 |
| 9923 |
} |
0 |
9923 |
} |
0 |
| 9924 |
} |
--- |
9924 |
} |
--- |
| 9925 |
|
--- |
9925 |
|
--- |
| 9926 |
return SDValue(); |
0 |
9926 |
return SDValue(); |
0 |
| 9927 |
} |
0 |
9927 |
} |
0 |
| 9928 |
|
--- |
9928 |
|
--- |
| 9929 |
// Transform a right shift of a multiply into a multiply-high. |
--- |
9929 |
// Transform a right shift of a multiply into a multiply-high. |
--- |
| 9930 |
// Examples: |
--- |
9930 |
// Examples: |
--- |
| 9931 |
// (srl (mul (zext i32:$a to i64), (zext i32:$a to i64)), 32) -> (mulhu $a, $b) |
--- |
9931 |
// (srl (mul (zext i32:$a to i64), (zext i32:$a to i64)), 32) -> (mulhu $a, $b) |
--- |
| 9932 |
// (sra (mul (sext i32:$a to i64), (sext i32:$a to i64)), 32) -> (mulhs $a, $b) |
--- |
9932 |
// (sra (mul (sext i32:$a to i64), (sext i32:$a to i64)), 32) -> (mulhs $a, $b) |
--- |
| 9933 |
static SDValue combineShiftToMULH(SDNode *N, SelectionDAG &DAG, |
0 |
9933 |
static SDValue combineShiftToMULH(SDNode *N, SelectionDAG &DAG, |
0 |
| 9934 |
const TargetLowering &TLI) { |
--- |
9934 |
const TargetLowering &TLI) { |
--- |
| 9935 |
assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && |
0 |
9935 |
assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && |
0 |
| 9936 |
"SRL or SRA node is required here!"); |
--- |
9936 |
"SRL or SRA node is required here!"); |
--- |
| 9937 |
|
--- |
9937 |
|
--- |
| 9938 |
// Check the shift amount. Proceed with the transformation if the shift |
--- |
9938 |
// Check the shift amount. Proceed with the transformation if the shift |
--- |
| 9939 |
// amount is constant. |
--- |
9939 |
// amount is constant. |
--- |
| 9940 |
ConstantSDNode *ShiftAmtSrc = isConstOrConstSplat(N->getOperand(1)); |
0 |
9940 |
ConstantSDNode *ShiftAmtSrc = isConstOrConstSplat(N->getOperand(1)); |
0 |
| 9941 |
if (!ShiftAmtSrc) |
0 |
9941 |
if (!ShiftAmtSrc) |
0 |
| 9942 |
return SDValue(); |
0 |
9942 |
return SDValue(); |
0 |
| 9943 |
|
--- |
9943 |
|
--- |
| 9944 |
SDLoc DL(N); |
0 |
9944 |
SDLoc DL(N); |
0 |
| 9945 |
|
--- |
9945 |
|
--- |
| 9946 |
// The operation feeding into the shift must be a multiply. |
--- |
9946 |
// The operation feeding into the shift must be a multiply. |
--- |
| 9947 |
SDValue ShiftOperand = N->getOperand(0); |
0 |
9947 |
SDValue ShiftOperand = N->getOperand(0); |
0 |
| 9948 |
if (ShiftOperand.getOpcode() != ISD::MUL) |
0 |
9948 |
if (ShiftOperand.getOpcode() != ISD::MUL) |
0 |
| 9949 |
return SDValue(); |
0 |
9949 |
return SDValue(); |
0 |
| 9950 |
|
--- |
9950 |
|
--- |
| 9951 |
// Both operands must be equivalent extend nodes. |
--- |
9951 |
// Both operands must be equivalent extend nodes. |
--- |
| 9952 |
SDValue LeftOp = ShiftOperand.getOperand(0); |
0 |
9952 |
SDValue LeftOp = ShiftOperand.getOperand(0); |
0 |
| 9953 |
SDValue RightOp = ShiftOperand.getOperand(1); |
0 |
9953 |
SDValue RightOp = ShiftOperand.getOperand(1); |
0 |
| 9954 |
|
--- |
9954 |
|
--- |
| 9955 |
bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; |
0 |
9955 |
bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; |
0 |
| 9956 |
bool IsZeroExt = LeftOp.getOpcode() == ISD::ZERO_EXTEND; |
0 |
9956 |
bool IsZeroExt = LeftOp.getOpcode() == ISD::ZERO_EXTEND; |
0 |
| 9957 |
|
--- |
9957 |
|
--- |
| 9958 |
if (!IsSignExt && !IsZeroExt) |
0 |
9958 |
if (!IsSignExt && !IsZeroExt) |
0 |
| 9959 |
return SDValue(); |
0 |
9959 |
return SDValue(); |
0 |
| 9960 |
|
--- |
9960 |
|
--- |
| 9961 |
EVT NarrowVT = LeftOp.getOperand(0).getValueType(); |
0 |
9961 |
EVT NarrowVT = LeftOp.getOperand(0).getValueType(); |
0 |
| 9962 |
unsigned NarrowVTSize = NarrowVT.getScalarSizeInBits(); |
0 |
9962 |
unsigned NarrowVTSize = NarrowVT.getScalarSizeInBits(); |
0 |
| 9963 |
|
--- |
9963 |
|
--- |
| 9964 |
// return true if U may use the lower bits of its operands |
--- |
9964 |
// return true if U may use the lower bits of its operands |
--- |
| 9965 |
auto UserOfLowerBits = [NarrowVTSize](SDNode *U) { |
0 |
9965 |
auto UserOfLowerBits = [NarrowVTSize](SDNode *U) { |
0 |
| 9966 |
if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) { |
0 |
9966 |
if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) { |
0 |
| 9967 |
return true; |
0 |
9967 |
return true; |
0 |
| 9968 |
} |
--- |
9968 |
} |
--- |
| 9969 |
ConstantSDNode *UShiftAmtSrc = isConstOrConstSplat(U->getOperand(1)); |
0 |
9969 |
ConstantSDNode *UShiftAmtSrc = isConstOrConstSplat(U->getOperand(1)); |
0 |
| 9970 |
if (!UShiftAmtSrc) { |
0 |
9970 |
if (!UShiftAmtSrc) { |
0 |
| 9971 |
return true; |
0 |
9971 |
return true; |
0 |
| 9972 |
} |
--- |
9972 |
} |
--- |
| 9973 |
unsigned UShiftAmt = UShiftAmtSrc->getZExtValue(); |
0 |
9973 |
unsigned UShiftAmt = UShiftAmtSrc->getZExtValue(); |
0 |
| 9974 |
return UShiftAmt < NarrowVTSize; |
0 |
9974 |
return UShiftAmt < NarrowVTSize; |
0 |
| 9975 |
}; |
0 |
9975 |
}; |
0 |
| 9976 |
|
--- |
9976 |
|
--- |
| 9977 |
// If the lower part of the MUL is also used and MUL_LOHI is supported |
--- |
9977 |
// If the lower part of the MUL is also used and MUL_LOHI is supported |
--- |
| 9978 |
// do not introduce the MULH in favor of MUL_LOHI |
--- |
9978 |
// do not introduce the MULH in favor of MUL_LOHI |
--- |
| 9979 |
unsigned MulLoHiOp = IsSignExt ? ISD::SMUL_LOHI : ISD::UMUL_LOHI; |
0 |
9979 |
unsigned MulLoHiOp = IsSignExt ? ISD::SMUL_LOHI : ISD::UMUL_LOHI; |
0 |
| 9980 |
if (!ShiftOperand.hasOneUse() && |
0 |
9980 |
if (!ShiftOperand.hasOneUse() && |
0 |
| 9981 |
TLI.isOperationLegalOrCustom(MulLoHiOp, NarrowVT) && |
0 |
9981 |
TLI.isOperationLegalOrCustom(MulLoHiOp, NarrowVT) && |
0 |
| 9982 |
llvm::any_of(ShiftOperand->uses(), UserOfLowerBits)) { |
0 |
9982 |
llvm::any_of(ShiftOperand->uses(), UserOfLowerBits)) { |
0 |
| 9983 |
return SDValue(); |
0 |
9983 |
return SDValue(); |
0 |
| 9984 |
} |
--- |
9984 |
} |
--- |
| 9985 |
|
--- |
9985 |
|
--- |
| 9986 |
SDValue MulhRightOp; |
0 |
9986 |
SDValue MulhRightOp; |
0 |
| 9987 |
if (ConstantSDNode *Constant = isConstOrConstSplat(RightOp)) { |
0 |
9987 |
if (ConstantSDNode *Constant = isConstOrConstSplat(RightOp)) { |
0 |
| 9988 |
unsigned ActiveBits = IsSignExt |
--- |
9988 |
unsigned ActiveBits = IsSignExt |
--- |
| 9989 |
? Constant->getAPIntValue().getSignificantBits() |
0 |
9989 |
? Constant->getAPIntValue().getSignificantBits() |
0 |
| 9990 |
: Constant->getAPIntValue().getActiveBits(); |
0 |
9990 |
: Constant->getAPIntValue().getActiveBits(); |
0 |
| 9991 |
if (ActiveBits > NarrowVTSize) |
0 |
9991 |
if (ActiveBits > NarrowVTSize) |
0 |
| 9992 |
return SDValue(); |
0 |
9992 |
return SDValue(); |
0 |
| 9993 |
MulhRightOp = DAG.getConstant( |
0 |
9993 |
MulhRightOp = DAG.getConstant( |
0 |
| 9994 |
Constant->getAPIntValue().trunc(NarrowVT.getScalarSizeInBits()), DL, |
0 |
9994 |
Constant->getAPIntValue().trunc(NarrowVT.getScalarSizeInBits()), DL, |
0 |
| 9995 |
NarrowVT); |
--- |
9995 |
NarrowVT); |
--- |
| 9996 |
} else { |
--- |
9996 |
} else { |
--- |
| 9997 |
if (LeftOp.getOpcode() != RightOp.getOpcode()) |
0 |
9997 |
if (LeftOp.getOpcode() != RightOp.getOpcode()) |
0 |
| 9998 |
return SDValue(); |
0 |
9998 |
return SDValue(); |
0 |
| 9999 |
// Check that the two extend nodes are the same type. |
--- |
9999 |
// Check that the two extend nodes are the same type. |
--- |
| 10000 |
if (NarrowVT != RightOp.getOperand(0).getValueType()) |
0 |
10000 |
if (NarrowVT != RightOp.getOperand(0).getValueType()) |
0 |
| 10001 |
return SDValue(); |
0 |
10001 |
return SDValue(); |
0 |
| 10002 |
MulhRightOp = RightOp.getOperand(0); |
0 |
10002 |
MulhRightOp = RightOp.getOperand(0); |
0 |
| 10003 |
} |
--- |
10003 |
} |
--- |
| 10004 |
|
--- |
10004 |
|
--- |
| 10005 |
EVT WideVT = LeftOp.getValueType(); |
0 |
10005 |
EVT WideVT = LeftOp.getValueType(); |
0 |
| 10006 |
// Proceed with the transformation if the wide types match. |
--- |
10006 |
// Proceed with the transformation if the wide types match. |
--- |
| 10007 |
assert((WideVT == RightOp.getValueType()) && |
0 |
10007 |
assert((WideVT == RightOp.getValueType()) && |
0 |
| 10008 |
"Cannot have a multiply node with two different operand types."); |
--- |
10008 |
"Cannot have a multiply node with two different operand types."); |
--- |
| 10009 |
|
--- |
10009 |
|
--- |
| 10010 |
// Proceed with the transformation if the wide type is twice as large |
--- |
10010 |
// Proceed with the transformation if the wide type is twice as large |
--- |
| 10011 |
// as the narrow type. |
--- |
10011 |
// as the narrow type. |
--- |
| 10012 |
if (WideVT.getScalarSizeInBits() != 2 * NarrowVTSize) |
0 |
10012 |
if (WideVT.getScalarSizeInBits() != 2 * NarrowVTSize) |
0 |
| 10013 |
return SDValue(); |
0 |
10013 |
return SDValue(); |
0 |
| 10014 |
|
--- |
10014 |
|
--- |
| 10015 |
// Check the shift amount with the narrow type size. |
--- |
10015 |
// Check the shift amount with the narrow type size. |
--- |
| 10016 |
// Proceed with the transformation if the shift amount is the width |
--- |
10016 |
// Proceed with the transformation if the shift amount is the width |
--- |
| 10017 |
// of the narrow type. |
--- |
10017 |
// of the narrow type. |
--- |
| 10018 |
unsigned ShiftAmt = ShiftAmtSrc->getZExtValue(); |
0 |
10018 |
unsigned ShiftAmt = ShiftAmtSrc->getZExtValue(); |
0 |
| 10019 |
if (ShiftAmt != NarrowVTSize) |
0 |
10019 |
if (ShiftAmt != NarrowVTSize) |
0 |
| 10020 |
return SDValue(); |
0 |
10020 |
return SDValue(); |
0 |
| 10021 |
|
--- |
10021 |
|
--- |
| 10022 |
// If the operation feeding into the MUL is a sign extend (sext), |
--- |
10022 |
// If the operation feeding into the MUL is a sign extend (sext), |
--- |
| 10023 |
// we use mulhs. Othewise, zero extends (zext) use mulhu. |
--- |
10023 |
// we use mulhs. Othewise, zero extends (zext) use mulhu. |
--- |
| 10024 |
unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; |
0 |
10024 |
unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; |
0 |
| 10025 |
|
--- |
10025 |
|
--- |
| 10026 |
// Combine to mulh if mulh is legal/custom for the narrow type on the target |
--- |
10026 |
// Combine to mulh if mulh is legal/custom for the narrow type on the target |
--- |
| 10027 |
// or if it is a vector type then we could transform to an acceptable type and |
--- |
10027 |
// or if it is a vector type then we could transform to an acceptable type and |
--- |
| 10028 |
// rely on legalization to split/combine the result. |
--- |
10028 |
// rely on legalization to split/combine the result. |
--- |
| 10029 |
if (NarrowVT.isVector()) { |
0 |
10029 |
if (NarrowVT.isVector()) { |
0 |
| 10030 |
EVT TransformVT = TLI.getTypeToTransformTo(*DAG.getContext(), NarrowVT); |
0 |
10030 |
EVT TransformVT = TLI.getTypeToTransformTo(*DAG.getContext(), NarrowVT); |
0 |
| 10031 |
if (TransformVT.getVectorElementType() != NarrowVT.getVectorElementType() || |
0 |
10031 |
if (TransformVT.getVectorElementType() != NarrowVT.getVectorElementType() || |
0 |
| 10032 |
!TLI.isOperationLegalOrCustom(MulhOpcode, TransformVT)) |
0 |
10032 |
!TLI.isOperationLegalOrCustom(MulhOpcode, TransformVT)) |
0 |
| 10033 |
return SDValue(); |
0 |
10033 |
return SDValue(); |
0 |
| 10034 |
} else { |
--- |
10034 |
} else { |
--- |
| 10035 |
if (!TLI.isOperationLegalOrCustom(MulhOpcode, NarrowVT)) |
0 |
10035 |
if (!TLI.isOperationLegalOrCustom(MulhOpcode, NarrowVT)) |
0 |
| 10036 |
return SDValue(); |
0 |
10036 |
return SDValue(); |
0 |
| 10037 |
} |
--- |
10037 |
} |
--- |
| 10038 |
|
--- |
10038 |
|
--- |
| 10039 |
SDValue Result = |
--- |
10039 |
SDValue Result = |
--- |
| 10040 |
DAG.getNode(MulhOpcode, DL, NarrowVT, LeftOp.getOperand(0), MulhRightOp); |
0 |
10040 |
DAG.getNode(MulhOpcode, DL, NarrowVT, LeftOp.getOperand(0), MulhRightOp); |
0 |
| 10041 |
bool IsSigned = N->getOpcode() == ISD::SRA; |
0 |
10041 |
bool IsSigned = N->getOpcode() == ISD::SRA; |
0 |
| 10042 |
return DAG.getExtOrTrunc(IsSigned, Result, DL, WideVT); |
0 |
10042 |
return DAG.getExtOrTrunc(IsSigned, Result, DL, WideVT); |
0 |
| 10043 |
} |
0 |
10043 |
} |
0 |
| 10044 |
|
--- |
10044 |
|
--- |
| 10045 |
// fold (bswap (logic_op(bswap(x),y))) -> logic_op(x,bswap(y)) |
--- |
10045 |
// fold (bswap (logic_op(bswap(x),y))) -> logic_op(x,bswap(y)) |
--- |
| 10046 |
// This helper function accept SDNode with opcode ISD::BSWAP and ISD::BITREVERSE |
--- |
10046 |
// This helper function accept SDNode with opcode ISD::BSWAP and ISD::BITREVERSE |
--- |
| 10047 |
static SDValue foldBitOrderCrossLogicOp(SDNode *N, SelectionDAG &DAG) { |
0 |
10047 |
static SDValue foldBitOrderCrossLogicOp(SDNode *N, SelectionDAG &DAG) { |
0 |
| 10048 |
unsigned Opcode = N->getOpcode(); |
0 |
10048 |
unsigned Opcode = N->getOpcode(); |
0 |
| 10049 |
if (Opcode != ISD::BSWAP && Opcode != ISD::BITREVERSE) |
0 |
10049 |
if (Opcode != ISD::BSWAP && Opcode != ISD::BITREVERSE) |
0 |
| 10050 |
return SDValue(); |
0 |
10050 |
return SDValue(); |
0 |
| 10051 |
|
--- |
10051 |
|
--- |
| 10052 |
SDValue N0 = N->getOperand(0); |
0 |
10052 |
SDValue N0 = N->getOperand(0); |
0 |
| 10053 |
EVT VT = N->getValueType(0); |
0 |
10053 |
EVT VT = N->getValueType(0); |
0 |
| 10054 |
SDLoc DL(N); |
0 |
10054 |
SDLoc DL(N); |
0 |
| 10055 |
if (ISD::isBitwiseLogicOp(N0.getOpcode()) && N0.hasOneUse()) { |
0 |
10055 |
if (ISD::isBitwiseLogicOp(N0.getOpcode()) && N0.hasOneUse()) { |
0 |
| 10056 |
SDValue OldLHS = N0.getOperand(0); |
0 |
10056 |
SDValue OldLHS = N0.getOperand(0); |
0 |
| 10057 |
SDValue OldRHS = N0.getOperand(1); |
0 |
10057 |
SDValue OldRHS = N0.getOperand(1); |
0 |
| 10058 |
|
--- |
10058 |
|
--- |
| 10059 |
// If both operands are bswap/bitreverse, ignore the multiuse |
--- |
10059 |
// If both operands are bswap/bitreverse, ignore the multiuse |
--- |
| 10060 |
// Otherwise need to ensure logic_op and bswap/bitreverse(x) have one use. |
--- |
10060 |
// Otherwise need to ensure logic_op and bswap/bitreverse(x) have one use. |
--- |
| 10061 |
if (OldLHS.getOpcode() == Opcode && OldRHS.getOpcode() == Opcode) { |
0 |
10061 |
if (OldLHS.getOpcode() == Opcode && OldRHS.getOpcode() == Opcode) { |
0 |
| 10062 |
return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0), |
0 |
10062 |
return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0), |
0 |
| 10063 |
OldRHS.getOperand(0)); |
0 |
10063 |
OldRHS.getOperand(0)); |
0 |
| 10064 |
} |
--- |
10064 |
} |
--- |
| 10065 |
|
--- |
10065 |
|
--- |
| 10066 |
if (OldLHS.getOpcode() == Opcode && OldLHS.hasOneUse()) { |
0 |
10066 |
if (OldLHS.getOpcode() == Opcode && OldLHS.hasOneUse()) { |
0 |
| 10067 |
SDValue NewBitReorder = DAG.getNode(Opcode, DL, VT, OldRHS); |
0 |
10067 |
SDValue NewBitReorder = DAG.getNode(Opcode, DL, VT, OldRHS); |
0 |
| 10068 |
return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0), |
0 |
10068 |
return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0), |
0 |
| 10069 |
NewBitReorder); |
0 |
10069 |
NewBitReorder); |
0 |
| 10070 |
} |
--- |
10070 |
} |
--- |
| 10071 |
|
--- |
10071 |
|
--- |
| 10072 |
if (OldRHS.getOpcode() == Opcode && OldRHS.hasOneUse()) { |
0 |
10072 |
if (OldRHS.getOpcode() == Opcode && OldRHS.hasOneUse()) { |
0 |
| 10073 |
SDValue NewBitReorder = DAG.getNode(Opcode, DL, VT, OldLHS); |
0 |
10073 |
SDValue NewBitReorder = DAG.getNode(Opcode, DL, VT, OldLHS); |
0 |
| 10074 |
return DAG.getNode(N0.getOpcode(), DL, VT, NewBitReorder, |
0 |
10074 |
return DAG.getNode(N0.getOpcode(), DL, VT, NewBitReorder, |
0 |
| 10075 |
OldRHS.getOperand(0)); |
0 |
10075 |
OldRHS.getOperand(0)); |
0 |
| 10076 |
} |
--- |
10076 |
} |
--- |
| 10077 |
} |
--- |
10077 |
} |
--- |
| 10078 |
return SDValue(); |
0 |
10078 |
return SDValue(); |
0 |
| 10079 |
} |
0 |
10079 |
} |
0 |
| 10080 |
|
--- |
10080 |
|
--- |
| 10081 |
SDValue DAGCombiner::visitSRA(SDNode *N) { |
0 |
10081 |
SDValue DAGCombiner::visitSRA(SDNode *N) { |
0 |
| 10082 |
SDValue N0 = N->getOperand(0); |
0 |
10082 |
SDValue N0 = N->getOperand(0); |
0 |
| 10083 |
SDValue N1 = N->getOperand(1); |
0 |
10083 |
SDValue N1 = N->getOperand(1); |
0 |
| 10084 |
if (SDValue V = DAG.simplifyShift(N0, N1)) |
0 |
10084 |
if (SDValue V = DAG.simplifyShift(N0, N1)) |
0 |
| 10085 |
return V; |
0 |
10085 |
return V; |
0 |
| 10086 |
|
--- |
10086 |
|
--- |
| 10087 |
EVT VT = N0.getValueType(); |
0 |
10087 |
EVT VT = N0.getValueType(); |
0 |
| 10088 |
unsigned OpSizeInBits = VT.getScalarSizeInBits(); |
0 |
10088 |
unsigned OpSizeInBits = VT.getScalarSizeInBits(); |
0 |
| 10089 |
|
--- |
10089 |
|
--- |
| 10090 |
// fold (sra c1, c2) -> (sra c1, c2) |
--- |
10090 |
// fold (sra c1, c2) -> (sra c1, c2) |
--- |
| 10091 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRA, SDLoc(N), VT, {N0, N1})) |
0 |
10091 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRA, SDLoc(N), VT, {N0, N1})) |
0 |
| 10092 |
return C; |
0 |
10092 |
return C; |
0 |
| 10093 |
|
--- |
10093 |
|
--- |
| 10094 |
// Arithmetic shifting an all-sign-bit value is a no-op. |
--- |
10094 |
// Arithmetic shifting an all-sign-bit value is a no-op. |
--- |
| 10095 |
// fold (sra 0, x) -> 0 |
--- |
10095 |
// fold (sra 0, x) -> 0 |
--- |
| 10096 |
// fold (sra -1, x) -> -1 |
--- |
10096 |
// fold (sra -1, x) -> -1 |
--- |
| 10097 |
if (DAG.ComputeNumSignBits(N0) == OpSizeInBits) |
0 |
10097 |
if (DAG.ComputeNumSignBits(N0) == OpSizeInBits) |
0 |
| 10098 |
return N0; |
0 |
10098 |
return N0; |
0 |
| 10099 |
|
--- |
10099 |
|
--- |
| 10100 |
// fold vector ops |
--- |
10100 |
// fold vector ops |
--- |
| 10101 |
if (VT.isVector()) |
0 |
10101 |
if (VT.isVector()) |
0 |
| 10102 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N))) |
0 |
10102 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N))) |
0 |
| 10103 |
return FoldedVOp; |
0 |
10103 |
return FoldedVOp; |
0 |
| 10104 |
|
--- |
10104 |
|
--- |
| 10105 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
10105 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 10106 |
return NewSel; |
0 |
10106 |
return NewSel; |
0 |
| 10107 |
|
--- |
10107 |
|
--- |
| 10108 |
// fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports |
--- |
10108 |
// fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports |
--- |
| 10109 |
// sext_inreg. |
--- |
10109 |
// sext_inreg. |
--- |
| 10110 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
10110 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
| 10111 |
if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { |
0 |
10111 |
if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { |
0 |
| 10112 |
unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); |
0 |
10112 |
unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); |
0 |
| 10113 |
EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); |
0 |
10113 |
EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); |
0 |
| 10114 |
if (VT.isVector()) |
0 |
10114 |
if (VT.isVector()) |
0 |
| 10115 |
ExtVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, |
0 |
10115 |
ExtVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, |
0 |
| 10116 |
VT.getVectorElementCount()); |
--- |
10116 |
VT.getVectorElementCount()); |
--- |
| 10117 |
if (!LegalOperations || |
0 |
10117 |
if (!LegalOperations || |
0 |
| 10118 |
TLI.getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) == |
0 |
10118 |
TLI.getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) == |
0 |
| 10119 |
TargetLowering::Legal) |
--- |
10119 |
TargetLowering::Legal) |
--- |
| 10120 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, |
0 |
10120 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, |
0 |
| 10121 |
N0.getOperand(0), DAG.getValueType(ExtVT)); |
0 |
10121 |
N0.getOperand(0), DAG.getValueType(ExtVT)); |
0 |
| 10122 |
// Even if we can't convert to sext_inreg, we might be able to remove |
--- |
10122 |
// Even if we can't convert to sext_inreg, we might be able to remove |
--- |
| 10123 |
// this shift pair if the input is already sign extended. |
--- |
10123 |
// this shift pair if the input is already sign extended. |
--- |
| 10124 |
if (DAG.ComputeNumSignBits(N0.getOperand(0)) > N1C->getZExtValue()) |
0 |
10124 |
if (DAG.ComputeNumSignBits(N0.getOperand(0)) > N1C->getZExtValue()) |
0 |
| 10125 |
return N0.getOperand(0); |
0 |
10125 |
return N0.getOperand(0); |
0 |
| 10126 |
} |
--- |
10126 |
} |
--- |
| 10127 |
|
--- |
10127 |
|
--- |
| 10128 |
// fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) |
--- |
10128 |
// fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) |
--- |
| 10129 |
// clamp (add c1, c2) to max shift. |
--- |
10129 |
// clamp (add c1, c2) to max shift. |
--- |
| 10130 |
if (N0.getOpcode() == ISD::SRA) { |
0 |
10130 |
if (N0.getOpcode() == ISD::SRA) { |
0 |
| 10131 |
SDLoc DL(N); |
0 |
10131 |
SDLoc DL(N); |
0 |
| 10132 |
EVT ShiftVT = N1.getValueType(); |
0 |
10132 |
EVT ShiftVT = N1.getValueType(); |
0 |
| 10133 |
EVT ShiftSVT = ShiftVT.getScalarType(); |
0 |
10133 |
EVT ShiftSVT = ShiftVT.getScalarType(); |
0 |
| 10134 |
SmallVector ShiftValues; |
0 |
10134 |
SmallVector ShiftValues; |
0 |
| 10135 |
|
--- |
10135 |
|
--- |
| 10136 |
auto SumOfShifts = [&](ConstantSDNode *LHS, ConstantSDNode *RHS) { |
0 |
10136 |
auto SumOfShifts = [&](ConstantSDNode *LHS, ConstantSDNode *RHS) { |
0 |
| 10137 |
APInt c1 = LHS->getAPIntValue(); |
0 |
10137 |
APInt c1 = LHS->getAPIntValue(); |
0 |
| 10138 |
APInt c2 = RHS->getAPIntValue(); |
0 |
10138 |
APInt c2 = RHS->getAPIntValue(); |
0 |
| 10139 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
10139 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
| 10140 |
APInt Sum = c1 + c2; |
0 |
10140 |
APInt Sum = c1 + c2; |
0 |
| 10141 |
unsigned ShiftSum = |
--- |
10141 |
unsigned ShiftSum = |
--- |
| 10142 |
Sum.uge(OpSizeInBits) ? (OpSizeInBits - 1) : Sum.getZExtValue(); |
0 |
10142 |
Sum.uge(OpSizeInBits) ? (OpSizeInBits - 1) : Sum.getZExtValue(); |
0 |
| 10143 |
ShiftValues.push_back(DAG.getConstant(ShiftSum, DL, ShiftSVT)); |
0 |
10143 |
ShiftValues.push_back(DAG.getConstant(ShiftSum, DL, ShiftSVT)); |
0 |
| 10144 |
return true; |
0 |
10144 |
return true; |
0 |
| 10145 |
}; |
0 |
10145 |
}; |
0 |
| 10146 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), SumOfShifts)) { |
0 |
10146 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), SumOfShifts)) { |
0 |
| 10147 |
SDValue ShiftValue; |
0 |
10147 |
SDValue ShiftValue; |
0 |
| 10148 |
if (N1.getOpcode() == ISD::BUILD_VECTOR) |
0 |
10148 |
if (N1.getOpcode() == ISD::BUILD_VECTOR) |
0 |
| 10149 |
ShiftValue = DAG.getBuildVector(ShiftVT, DL, ShiftValues); |
0 |
10149 |
ShiftValue = DAG.getBuildVector(ShiftVT, DL, ShiftValues); |
0 |
| 10150 |
else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { |
0 |
10150 |
else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { |
0 |
| 10151 |
assert(ShiftValues.size() == 1 && |
0 |
10151 |
assert(ShiftValues.size() == 1 && |
0 |
| 10152 |
"Expected matchBinaryPredicate to return one element for " |
--- |
10152 |
"Expected matchBinaryPredicate to return one element for " |
--- |
| 10153 |
"SPLAT_VECTORs"); |
--- |
10153 |
"SPLAT_VECTORs"); |
--- |
| 10154 |
ShiftValue = DAG.getSplatVector(ShiftVT, DL, ShiftValues[0]); |
0 |
10154 |
ShiftValue = DAG.getSplatVector(ShiftVT, DL, ShiftValues[0]); |
0 |
| 10155 |
} else |
--- |
10155 |
} else |
--- |
| 10156 |
ShiftValue = ShiftValues[0]; |
0 |
10156 |
ShiftValue = ShiftValues[0]; |
0 |
| 10157 |
return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0), ShiftValue); |
0 |
10157 |
return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0), ShiftValue); |
0 |
| 10158 |
} |
--- |
10158 |
} |
--- |
| 10159 |
} |
0 |
10159 |
} |
0 |
| 10160 |
|
--- |
10160 |
|
--- |
| 10161 |
// fold (sra (shl X, m), (sub result_size, n)) |
--- |
10161 |
// fold (sra (shl X, m), (sub result_size, n)) |
--- |
| 10162 |
// -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for |
--- |
10162 |
// -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for |
--- |
| 10163 |
// result_size - n != m. |
--- |
10163 |
// result_size - n != m. |
--- |
| 10164 |
// If truncate is free for the target sext(shl) is likely to result in better |
--- |
10164 |
// If truncate is free for the target sext(shl) is likely to result in better |
--- |
| 10165 |
// code. |
--- |
10165 |
// code. |
--- |
| 10166 |
if (N0.getOpcode() == ISD::SHL && N1C) { |
0 |
10166 |
if (N0.getOpcode() == ISD::SHL && N1C) { |
0 |
| 10167 |
// Get the two constanst of the shifts, CN0 = m, CN = n. |
--- |
10167 |
// Get the two constanst of the shifts, CN0 = m, CN = n. |
--- |
| 10168 |
const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1)); |
0 |
10168 |
const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1)); |
0 |
| 10169 |
if (N01C) { |
0 |
10169 |
if (N01C) { |
0 |
| 10170 |
LLVMContext &Ctx = *DAG.getContext(); |
0 |
10170 |
LLVMContext &Ctx = *DAG.getContext(); |
0 |
| 10171 |
// Determine what the truncate's result bitsize and type would be. |
--- |
10171 |
// Determine what the truncate's result bitsize and type would be. |
--- |
| 10172 |
EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue()); |
0 |
10172 |
EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue()); |
0 |
| 10173 |
|
--- |
10173 |
|
--- |
| 10174 |
if (VT.isVector()) |
0 |
10174 |
if (VT.isVector()) |
0 |
| 10175 |
TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorElementCount()); |
0 |
10175 |
TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorElementCount()); |
0 |
| 10176 |
|
--- |
10176 |
|
--- |
| 10177 |
// Determine the residual right-shift amount. |
--- |
10177 |
// Determine the residual right-shift amount. |
--- |
| 10178 |
int ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); |
0 |
10178 |
int ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); |
0 |
| 10179 |
|
--- |
10179 |
|
--- |
| 10180 |
// If the shift is not a no-op (in which case this should be just a sign |
--- |
10180 |
// If the shift is not a no-op (in which case this should be just a sign |
--- |
| 10181 |
// extend already), the truncated to type is legal, sign_extend is legal |
--- |
10181 |
// extend already), the truncated to type is legal, sign_extend is legal |
--- |
| 10182 |
// on that type, and the truncate to that type is both legal and free, |
--- |
10182 |
// on that type, and the truncate to that type is both legal and free, |
--- |
| 10183 |
// perform the transform. |
--- |
10183 |
// perform the transform. |
--- |
| 10184 |
if ((ShiftAmt > 0) && |
0 |
10184 |
if ((ShiftAmt > 0) && |
0 |
| 10185 |
TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && |
0 |
10185 |
TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && |
0 |
| 10186 |
TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && |
0 |
10186 |
TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && |
0 |
| 10187 |
TLI.isTruncateFree(VT, TruncVT)) { |
0 |
10187 |
TLI.isTruncateFree(VT, TruncVT)) { |
0 |
| 10188 |
SDLoc DL(N); |
0 |
10188 |
SDLoc DL(N); |
0 |
| 10189 |
SDValue Amt = DAG.getConstant(ShiftAmt, DL, |
0 |
10189 |
SDValue Amt = DAG.getConstant(ShiftAmt, DL, |
0 |
| 10190 |
getShiftAmountTy(N0.getOperand(0).getValueType())); |
0 |
10190 |
getShiftAmountTy(N0.getOperand(0).getValueType())); |
0 |
| 10191 |
SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, |
0 |
10191 |
SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, |
0 |
| 10192 |
N0.getOperand(0), Amt); |
0 |
10192 |
N0.getOperand(0), Amt); |
0 |
| 10193 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, |
0 |
10193 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, |
0 |
| 10194 |
Shift); |
--- |
10194 |
Shift); |
--- |
| 10195 |
return DAG.getNode(ISD::SIGN_EXTEND, DL, |
0 |
10195 |
return DAG.getNode(ISD::SIGN_EXTEND, DL, |
0 |
| 10196 |
N->getValueType(0), Trunc); |
0 |
10196 |
N->getValueType(0), Trunc); |
0 |
| 10197 |
} |
0 |
10197 |
} |
0 |
| 10198 |
} |
--- |
10198 |
} |
--- |
| 10199 |
} |
--- |
10199 |
} |
--- |
| 10200 |
|
--- |
10200 |
|
--- |
| 10201 |
// We convert trunc/ext to opposing shifts in IR, but casts may be cheaper. |
--- |
10201 |
// We convert trunc/ext to opposing shifts in IR, but casts may be cheaper. |
--- |
| 10202 |
// sra (add (shl X, N1C), AddC), N1C --> |
--- |
10202 |
// sra (add (shl X, N1C), AddC), N1C --> |
--- |
| 10203 |
// sext (add (trunc X to (width - N1C)), AddC') |
--- |
10203 |
// sext (add (trunc X to (width - N1C)), AddC') |
--- |
| 10204 |
// sra (sub AddC, (shl X, N1C)), N1C --> |
--- |
10204 |
// sra (sub AddC, (shl X, N1C)), N1C --> |
--- |
| 10205 |
// sext (sub AddC1',(trunc X to (width - N1C))) |
--- |
10205 |
// sext (sub AddC1',(trunc X to (width - N1C))) |
--- |
| 10206 |
if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB) && N1C && |
0 |
10206 |
if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB) && N1C && |
0 |
| 10207 |
N0.hasOneUse()) { |
0 |
10207 |
N0.hasOneUse()) { |
0 |
| 10208 |
bool IsAdd = N0.getOpcode() == ISD::ADD; |
0 |
10208 |
bool IsAdd = N0.getOpcode() == ISD::ADD; |
0 |
| 10209 |
SDValue Shl = N0.getOperand(IsAdd ? 0 : 1); |
0 |
10209 |
SDValue Shl = N0.getOperand(IsAdd ? 0 : 1); |
0 |
| 10210 |
if (Shl.getOpcode() == ISD::SHL && Shl.getOperand(1) == N1 && |
0 |
10210 |
if (Shl.getOpcode() == ISD::SHL && Shl.getOperand(1) == N1 && |
0 |
| 10211 |
Shl.hasOneUse()) { |
0 |
10211 |
Shl.hasOneUse()) { |
0 |
| 10212 |
// TODO: AddC does not need to be a splat. |
--- |
10212 |
// TODO: AddC does not need to be a splat. |
--- |
| 10213 |
if (ConstantSDNode *AddC = |
0 |
10213 |
if (ConstantSDNode *AddC = |
0 |
| 10214 |
isConstOrConstSplat(N0.getOperand(IsAdd ? 1 : 0))) { |
0 |
10214 |
isConstOrConstSplat(N0.getOperand(IsAdd ? 1 : 0))) { |
0 |
| 10215 |
// Determine what the truncate's type would be and ask the target if |
--- |
10215 |
// Determine what the truncate's type would be and ask the target if |
--- |
| 10216 |
// that is a free operation. |
--- |
10216 |
// that is a free operation. |
--- |
| 10217 |
LLVMContext &Ctx = *DAG.getContext(); |
0 |
10217 |
LLVMContext &Ctx = *DAG.getContext(); |
0 |
| 10218 |
unsigned ShiftAmt = N1C->getZExtValue(); |
0 |
10218 |
unsigned ShiftAmt = N1C->getZExtValue(); |
0 |
| 10219 |
EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - ShiftAmt); |
0 |
10219 |
EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - ShiftAmt); |
0 |
| 10220 |
if (VT.isVector()) |
0 |
10220 |
if (VT.isVector()) |
0 |
| 10221 |
TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorElementCount()); |
0 |
10221 |
TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorElementCount()); |
0 |
| 10222 |
|
--- |
10222 |
|
--- |
| 10223 |
// TODO: The simple type check probably belongs in the default hook |
--- |
10223 |
// TODO: The simple type check probably belongs in the default hook |
--- |
| 10224 |
// implementation and/or target-specific overrides (because |
--- |
10224 |
// implementation and/or target-specific overrides (because |
--- |
| 10225 |
// non-simple types likely require masking when legalized), but |
--- |
10225 |
// non-simple types likely require masking when legalized), but |
--- |
| 10226 |
// that restriction may conflict with other transforms. |
--- |
10226 |
// that restriction may conflict with other transforms. |
--- |
| 10227 |
if (TruncVT.isSimple() && isTypeLegal(TruncVT) && |
0 |
10227 |
if (TruncVT.isSimple() && isTypeLegal(TruncVT) && |
0 |
| 10228 |
TLI.isTruncateFree(VT, TruncVT)) { |
0 |
10228 |
TLI.isTruncateFree(VT, TruncVT)) { |
0 |
| 10229 |
SDLoc DL(N); |
0 |
10229 |
SDLoc DL(N); |
0 |
| 10230 |
SDValue Trunc = DAG.getZExtOrTrunc(Shl.getOperand(0), DL, TruncVT); |
0 |
10230 |
SDValue Trunc = DAG.getZExtOrTrunc(Shl.getOperand(0), DL, TruncVT); |
0 |
| 10231 |
SDValue ShiftC = |
--- |
10231 |
SDValue ShiftC = |
--- |
| 10232 |
DAG.getConstant(AddC->getAPIntValue().lshr(ShiftAmt).trunc( |
0 |
10232 |
DAG.getConstant(AddC->getAPIntValue().lshr(ShiftAmt).trunc( |
0 |
| 10233 |
TruncVT.getScalarSizeInBits()), |
0 |
10233 |
TruncVT.getScalarSizeInBits()), |
0 |
| 10234 |
DL, TruncVT); |
--- |
10234 |
DL, TruncVT); |
--- |
| 10235 |
SDValue Add; |
0 |
10235 |
SDValue Add; |
0 |
| 10236 |
if (IsAdd) |
0 |
10236 |
if (IsAdd) |
0 |
| 10237 |
Add = DAG.getNode(ISD::ADD, DL, TruncVT, Trunc, ShiftC); |
0 |
10237 |
Add = DAG.getNode(ISD::ADD, DL, TruncVT, Trunc, ShiftC); |
0 |
| 10238 |
else |
--- |
10238 |
else |
--- |
| 10239 |
Add = DAG.getNode(ISD::SUB, DL, TruncVT, ShiftC, Trunc); |
0 |
10239 |
Add = DAG.getNode(ISD::SUB, DL, TruncVT, ShiftC, Trunc); |
0 |
| 10240 |
return DAG.getSExtOrTrunc(Add, DL, VT); |
0 |
10240 |
return DAG.getSExtOrTrunc(Add, DL, VT); |
0 |
| 10241 |
} |
0 |
10241 |
} |
0 |
| 10242 |
} |
--- |
10242 |
} |
--- |
| 10243 |
} |
--- |
10243 |
} |
--- |
| 10244 |
} |
--- |
10244 |
} |
--- |
| 10245 |
|
--- |
10245 |
|
--- |
| 10246 |
// fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). |
--- |
10246 |
// fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). |
--- |
| 10247 |
if (N1.getOpcode() == ISD::TRUNCATE && |
0 |
10247 |
if (N1.getOpcode() == ISD::TRUNCATE && |
0 |
| 10248 |
N1.getOperand(0).getOpcode() == ISD::AND) { |
0 |
10248 |
N1.getOperand(0).getOpcode() == ISD::AND) { |
0 |
| 10249 |
if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode())) |
0 |
10249 |
if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode())) |
0 |
| 10250 |
return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1); |
0 |
10250 |
return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1); |
0 |
| 10251 |
} |
--- |
10251 |
} |
--- |
| 10252 |
|
--- |
10252 |
|
--- |
| 10253 |
// fold (sra (trunc (sra x, c1)), c2) -> (trunc (sra x, c1 + c2)) |
--- |
10253 |
// fold (sra (trunc (sra x, c1)), c2) -> (trunc (sra x, c1 + c2)) |
--- |
| 10254 |
// fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2)) |
--- |
10254 |
// fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2)) |
--- |
| 10255 |
// if c1 is equal to the number of bits the trunc removes |
--- |
10255 |
// if c1 is equal to the number of bits the trunc removes |
--- |
| 10256 |
// TODO - support non-uniform vector shift amounts. |
--- |
10256 |
// TODO - support non-uniform vector shift amounts. |
--- |
| 10257 |
if (N0.getOpcode() == ISD::TRUNCATE && |
0 |
10257 |
if (N0.getOpcode() == ISD::TRUNCATE && |
0 |
| 10258 |
(N0.getOperand(0).getOpcode() == ISD::SRL || |
0 |
10258 |
(N0.getOperand(0).getOpcode() == ISD::SRL || |
0 |
| 10259 |
N0.getOperand(0).getOpcode() == ISD::SRA) && |
0 |
10259 |
N0.getOperand(0).getOpcode() == ISD::SRA) && |
0 |
| 10260 |
N0.getOperand(0).hasOneUse() && |
0 |
10260 |
N0.getOperand(0).hasOneUse() && |
0 |
| 10261 |
N0.getOperand(0).getOperand(1).hasOneUse() && N1C) { |
0 |
10261 |
N0.getOperand(0).getOperand(1).hasOneUse() && N1C) { |
0 |
| 10262 |
SDValue N0Op0 = N0.getOperand(0); |
0 |
10262 |
SDValue N0Op0 = N0.getOperand(0); |
0 |
| 10263 |
if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) { |
0 |
10263 |
if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) { |
0 |
| 10264 |
EVT LargeVT = N0Op0.getValueType(); |
0 |
10264 |
EVT LargeVT = N0Op0.getValueType(); |
0 |
| 10265 |
unsigned TruncBits = LargeVT.getScalarSizeInBits() - OpSizeInBits; |
0 |
10265 |
unsigned TruncBits = LargeVT.getScalarSizeInBits() - OpSizeInBits; |
0 |
| 10266 |
if (LargeShift->getAPIntValue() == TruncBits) { |
0 |
10266 |
if (LargeShift->getAPIntValue() == TruncBits) { |
0 |
| 10267 |
SDLoc DL(N); |
0 |
10267 |
SDLoc DL(N); |
0 |
| 10268 |
EVT LargeShiftVT = getShiftAmountTy(LargeVT); |
0 |
10268 |
EVT LargeShiftVT = getShiftAmountTy(LargeVT); |
0 |
| 10269 |
SDValue Amt = DAG.getZExtOrTrunc(N1, DL, LargeShiftVT); |
0 |
10269 |
SDValue Amt = DAG.getZExtOrTrunc(N1, DL, LargeShiftVT); |
0 |
| 10270 |
Amt = DAG.getNode(ISD::ADD, DL, LargeShiftVT, Amt, |
0 |
10270 |
Amt = DAG.getNode(ISD::ADD, DL, LargeShiftVT, Amt, |
0 |
| 10271 |
DAG.getConstant(TruncBits, DL, LargeShiftVT)); |
0 |
10271 |
DAG.getConstant(TruncBits, DL, LargeShiftVT)); |
0 |
| 10272 |
SDValue SRA = |
--- |
10272 |
SDValue SRA = |
--- |
| 10273 |
DAG.getNode(ISD::SRA, DL, LargeVT, N0Op0.getOperand(0), Amt); |
0 |
10273 |
DAG.getNode(ISD::SRA, DL, LargeVT, N0Op0.getOperand(0), Amt); |
0 |
| 10274 |
return DAG.getNode(ISD::TRUNCATE, DL, VT, SRA); |
0 |
10274 |
return DAG.getNode(ISD::TRUNCATE, DL, VT, SRA); |
0 |
| 10275 |
} |
0 |
10275 |
} |
0 |
| 10276 |
} |
--- |
10276 |
} |
--- |
| 10277 |
} |
--- |
10277 |
} |
--- |
| 10278 |
|
--- |
10278 |
|
--- |
| 10279 |
// Simplify, based on bits shifted out of the LHS. |
--- |
10279 |
// Simplify, based on bits shifted out of the LHS. |
--- |
| 10280 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
10280 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
| 10281 |
return SDValue(N, 0); |
0 |
10281 |
return SDValue(N, 0); |
0 |
| 10282 |
|
--- |
10282 |
|
--- |
| 10283 |
// If the sign bit is known to be zero, switch this to a SRL. |
--- |
10283 |
// If the sign bit is known to be zero, switch this to a SRL. |
--- |
| 10284 |
if (DAG.SignBitIsZero(N0)) |
0 |
10284 |
if (DAG.SignBitIsZero(N0)) |
0 |
| 10285 |
return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1); |
0 |
10285 |
return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1); |
0 |
| 10286 |
|
--- |
10286 |
|
--- |
| 10287 |
if (N1C && !N1C->isOpaque()) |
0 |
10287 |
if (N1C && !N1C->isOpaque()) |
0 |
| 10288 |
if (SDValue NewSRA = visitShiftByConstant(N)) |
0 |
10288 |
if (SDValue NewSRA = visitShiftByConstant(N)) |
0 |
| 10289 |
return NewSRA; |
0 |
10289 |
return NewSRA; |
0 |
| 10290 |
|
--- |
10290 |
|
--- |
| 10291 |
// Try to transform this shift into a multiply-high if |
--- |
10291 |
// Try to transform this shift into a multiply-high if |
--- |
| 10292 |
// it matches the appropriate pattern detected in combineShiftToMULH. |
--- |
10292 |
// it matches the appropriate pattern detected in combineShiftToMULH. |
--- |
| 10293 |
if (SDValue MULH = combineShiftToMULH(N, DAG, TLI)) |
0 |
10293 |
if (SDValue MULH = combineShiftToMULH(N, DAG, TLI)) |
0 |
| 10294 |
return MULH; |
0 |
10294 |
return MULH; |
0 |
| 10295 |
|
--- |
10295 |
|
--- |
| 10296 |
// Attempt to convert a sra of a load into a narrower sign-extending load. |
--- |
10296 |
// Attempt to convert a sra of a load into a narrower sign-extending load. |
--- |
| 10297 |
if (SDValue NarrowLoad = reduceLoadWidth(N)) |
0 |
10297 |
if (SDValue NarrowLoad = reduceLoadWidth(N)) |
0 |
| 10298 |
return NarrowLoad; |
0 |
10298 |
return NarrowLoad; |
0 |
| 10299 |
|
--- |
10299 |
|
--- |
| 10300 |
return SDValue(); |
0 |
10300 |
return SDValue(); |
0 |
| 10301 |
} |
--- |
10301 |
} |
--- |
| 10302 |
|
--- |
10302 |
|
--- |
| 10303 |
SDValue DAGCombiner::visitSRL(SDNode *N) { |
0 |
10303 |
SDValue DAGCombiner::visitSRL(SDNode *N) { |
0 |
| 10304 |
SDValue N0 = N->getOperand(0); |
0 |
10304 |
SDValue N0 = N->getOperand(0); |
0 |
| 10305 |
SDValue N1 = N->getOperand(1); |
0 |
10305 |
SDValue N1 = N->getOperand(1); |
0 |
| 10306 |
if (SDValue V = DAG.simplifyShift(N0, N1)) |
0 |
10306 |
if (SDValue V = DAG.simplifyShift(N0, N1)) |
0 |
| 10307 |
return V; |
0 |
10307 |
return V; |
0 |
| 10308 |
|
--- |
10308 |
|
--- |
| 10309 |
EVT VT = N0.getValueType(); |
0 |
10309 |
EVT VT = N0.getValueType(); |
0 |
| 10310 |
EVT ShiftVT = N1.getValueType(); |
0 |
10310 |
EVT ShiftVT = N1.getValueType(); |
0 |
| 10311 |
unsigned OpSizeInBits = VT.getScalarSizeInBits(); |
0 |
10311 |
unsigned OpSizeInBits = VT.getScalarSizeInBits(); |
0 |
| 10312 |
|
--- |
10312 |
|
--- |
| 10313 |
// fold (srl c1, c2) -> c1 >>u c2 |
--- |
10313 |
// fold (srl c1, c2) -> c1 >>u c2 |
--- |
| 10314 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRL, SDLoc(N), VT, {N0, N1})) |
0 |
10314 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRL, SDLoc(N), VT, {N0, N1})) |
0 |
| 10315 |
return C; |
0 |
10315 |
return C; |
0 |
| 10316 |
|
--- |
10316 |
|
--- |
| 10317 |
// fold vector ops |
--- |
10317 |
// fold vector ops |
--- |
| 10318 |
if (VT.isVector()) |
0 |
10318 |
if (VT.isVector()) |
0 |
| 10319 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N))) |
0 |
10319 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N))) |
0 |
| 10320 |
return FoldedVOp; |
0 |
10320 |
return FoldedVOp; |
0 |
| 10321 |
|
--- |
10321 |
|
--- |
| 10322 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
10322 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 10323 |
return NewSel; |
0 |
10323 |
return NewSel; |
0 |
| 10324 |
|
--- |
10324 |
|
--- |
| 10325 |
// if (srl x, c) is known to be zero, return 0 |
--- |
10325 |
// if (srl x, c) is known to be zero, return 0 |
--- |
| 10326 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
10326 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
| 10327 |
if (N1C && |
0 |
10327 |
if (N1C && |
0 |
| 10328 |
DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(OpSizeInBits))) |
0 |
10328 |
DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(OpSizeInBits))) |
0 |
| 10329 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
10329 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
| 10330 |
|
--- |
10330 |
|
--- |
| 10331 |
// fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) |
--- |
10331 |
// fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) |
--- |
| 10332 |
if (N0.getOpcode() == ISD::SRL) { |
0 |
10332 |
if (N0.getOpcode() == ISD::SRL) { |
0 |
| 10333 |
auto MatchOutOfRange = [OpSizeInBits](ConstantSDNode *LHS, |
0 |
10333 |
auto MatchOutOfRange = [OpSizeInBits](ConstantSDNode *LHS, |
0 |
| 10334 |
ConstantSDNode *RHS) { |
0 |
10334 |
ConstantSDNode *RHS) { |
0 |
| 10335 |
APInt c1 = LHS->getAPIntValue(); |
0 |
10335 |
APInt c1 = LHS->getAPIntValue(); |
0 |
| 10336 |
APInt c2 = RHS->getAPIntValue(); |
0 |
10336 |
APInt c2 = RHS->getAPIntValue(); |
0 |
| 10337 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
10337 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
| 10338 |
return (c1 + c2).uge(OpSizeInBits); |
0 |
10338 |
return (c1 + c2).uge(OpSizeInBits); |
0 |
| 10339 |
}; |
0 |
10339 |
}; |
0 |
| 10340 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange)) |
0 |
10340 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange)) |
0 |
| 10341 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
10341 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
| 10342 |
|
--- |
10342 |
|
--- |
| 10343 |
auto MatchInRange = [OpSizeInBits](ConstantSDNode *LHS, |
0 |
10343 |
auto MatchInRange = [OpSizeInBits](ConstantSDNode *LHS, |
0 |
| 10344 |
ConstantSDNode *RHS) { |
0 |
10344 |
ConstantSDNode *RHS) { |
0 |
| 10345 |
APInt c1 = LHS->getAPIntValue(); |
0 |
10345 |
APInt c1 = LHS->getAPIntValue(); |
0 |
| 10346 |
APInt c2 = RHS->getAPIntValue(); |
0 |
10346 |
APInt c2 = RHS->getAPIntValue(); |
0 |
| 10347 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
10347 |
zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */); |
0 |
| 10348 |
return (c1 + c2).ult(OpSizeInBits); |
0 |
10348 |
return (c1 + c2).ult(OpSizeInBits); |
0 |
| 10349 |
}; |
0 |
10349 |
}; |
0 |
| 10350 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) { |
0 |
10350 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) { |
0 |
| 10351 |
SDLoc DL(N); |
0 |
10351 |
SDLoc DL(N); |
0 |
| 10352 |
SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1)); |
0 |
10352 |
SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1)); |
0 |
| 10353 |
return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Sum); |
0 |
10353 |
return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Sum); |
0 |
| 10354 |
} |
0 |
10354 |
} |
0 |
| 10355 |
} |
--- |
10355 |
} |
--- |
| 10356 |
|
--- |
10356 |
|
--- |
| 10357 |
if (N1C && N0.getOpcode() == ISD::TRUNCATE && |
0 |
10357 |
if (N1C && N0.getOpcode() == ISD::TRUNCATE && |
0 |
| 10358 |
N0.getOperand(0).getOpcode() == ISD::SRL) { |
0 |
10358 |
N0.getOperand(0).getOpcode() == ISD::SRL) { |
0 |
| 10359 |
SDValue InnerShift = N0.getOperand(0); |
0 |
10359 |
SDValue InnerShift = N0.getOperand(0); |
0 |
| 10360 |
// TODO - support non-uniform vector shift amounts. |
--- |
10360 |
// TODO - support non-uniform vector shift amounts. |
--- |
| 10361 |
if (auto *N001C = isConstOrConstSplat(InnerShift.getOperand(1))) { |
0 |
10361 |
if (auto *N001C = isConstOrConstSplat(InnerShift.getOperand(1))) { |
0 |
| 10362 |
uint64_t c1 = N001C->getZExtValue(); |
0 |
10362 |
uint64_t c1 = N001C->getZExtValue(); |
0 |
| 10363 |
uint64_t c2 = N1C->getZExtValue(); |
0 |
10363 |
uint64_t c2 = N1C->getZExtValue(); |
0 |
| 10364 |
EVT InnerShiftVT = InnerShift.getValueType(); |
0 |
10364 |
EVT InnerShiftVT = InnerShift.getValueType(); |
0 |
| 10365 |
EVT ShiftAmtVT = InnerShift.getOperand(1).getValueType(); |
0 |
10365 |
EVT ShiftAmtVT = InnerShift.getOperand(1).getValueType(); |
0 |
| 10366 |
uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits(); |
0 |
10366 |
uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits(); |
0 |
| 10367 |
// srl (trunc (srl x, c1)), c2 --> 0 or (trunc (srl x, (add c1, c2))) |
--- |
10367 |
// srl (trunc (srl x, c1)), c2 --> 0 or (trunc (srl x, (add c1, c2))) |
--- |
| 10368 |
// This is only valid if the OpSizeInBits + c1 = size of inner shift. |
--- |
10368 |
// This is only valid if the OpSizeInBits + c1 = size of inner shift. |
--- |
| 10369 |
if (c1 + OpSizeInBits == InnerShiftSize) { |
0 |
10369 |
if (c1 + OpSizeInBits == InnerShiftSize) { |
0 |
| 10370 |
SDLoc DL(N); |
0 |
10370 |
SDLoc DL(N); |
0 |
| 10371 |
if (c1 + c2 >= InnerShiftSize) |
0 |
10371 |
if (c1 + c2 >= InnerShiftSize) |
0 |
| 10372 |
return DAG.getConstant(0, DL, VT); |
0 |
10372 |
return DAG.getConstant(0, DL, VT); |
0 |
| 10373 |
SDValue NewShiftAmt = DAG.getConstant(c1 + c2, DL, ShiftAmtVT); |
0 |
10373 |
SDValue NewShiftAmt = DAG.getConstant(c1 + c2, DL, ShiftAmtVT); |
0 |
| 10374 |
SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, |
0 |
10374 |
SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, |
0 |
| 10375 |
InnerShift.getOperand(0), NewShiftAmt); |
0 |
10375 |
InnerShift.getOperand(0), NewShiftAmt); |
0 |
| 10376 |
return DAG.getNode(ISD::TRUNCATE, DL, VT, NewShift); |
0 |
10376 |
return DAG.getNode(ISD::TRUNCATE, DL, VT, NewShift); |
0 |
| 10377 |
} |
0 |
10377 |
} |
0 |
| 10378 |
// In the more general case, we can clear the high bits after the shift: |
--- |
10378 |
// In the more general case, we can clear the high bits after the shift: |
--- |
| 10379 |
// srl (trunc (srl x, c1)), c2 --> trunc (and (srl x, (c1+c2)), Mask) |
--- |
10379 |
// srl (trunc (srl x, c1)), c2 --> trunc (and (srl x, (c1+c2)), Mask) |
--- |
| 10380 |
if (N0.hasOneUse() && InnerShift.hasOneUse() && |
0 |
10380 |
if (N0.hasOneUse() && InnerShift.hasOneUse() && |
0 |
| 10381 |
c1 + c2 < InnerShiftSize) { |
0 |
10381 |
c1 + c2 < InnerShiftSize) { |
0 |
| 10382 |
SDLoc DL(N); |
0 |
10382 |
SDLoc DL(N); |
0 |
| 10383 |
SDValue NewShiftAmt = DAG.getConstant(c1 + c2, DL, ShiftAmtVT); |
0 |
10383 |
SDValue NewShiftAmt = DAG.getConstant(c1 + c2, DL, ShiftAmtVT); |
0 |
| 10384 |
SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, |
0 |
10384 |
SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, |
0 |
| 10385 |
InnerShift.getOperand(0), NewShiftAmt); |
0 |
10385 |
InnerShift.getOperand(0), NewShiftAmt); |
0 |
| 10386 |
SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(InnerShiftSize, |
0 |
10386 |
SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(InnerShiftSize, |
0 |
| 10387 |
OpSizeInBits - c2), |
--- |
10387 |
OpSizeInBits - c2), |
--- |
| 10388 |
DL, InnerShiftVT); |
--- |
10388 |
DL, InnerShiftVT); |
--- |
| 10389 |
SDValue And = DAG.getNode(ISD::AND, DL, InnerShiftVT, NewShift, Mask); |
0 |
10389 |
SDValue And = DAG.getNode(ISD::AND, DL, InnerShiftVT, NewShift, Mask); |
0 |
| 10390 |
return DAG.getNode(ISD::TRUNCATE, DL, VT, And); |
0 |
10390 |
return DAG.getNode(ISD::TRUNCATE, DL, VT, And); |
0 |
| 10391 |
} |
0 |
10391 |
} |
0 |
| 10392 |
} |
--- |
10392 |
} |
--- |
| 10393 |
} |
--- |
10393 |
} |
--- |
| 10394 |
|
--- |
10394 |
|
--- |
| 10395 |
// fold (srl (shl x, c1), c2) -> (and (shl x, (sub c1, c2), MASK) or |
--- |
10395 |
// fold (srl (shl x, c1), c2) -> (and (shl x, (sub c1, c2), MASK) or |
--- |
| 10396 |
// (and (srl x, (sub c2, c1), MASK) |
--- |
10396 |
// (and (srl x, (sub c2, c1), MASK) |
--- |
| 10397 |
if (N0.getOpcode() == ISD::SHL && |
0 |
10397 |
if (N0.getOpcode() == ISD::SHL && |
0 |
| 10398 |
(N0.getOperand(1) == N1 || N0->hasOneUse()) && |
0 |
10398 |
(N0.getOperand(1) == N1 || N0->hasOneUse()) && |
0 |
| 10399 |
TLI.shouldFoldConstantShiftPairToMask(N, Level)) { |
0 |
10399 |
TLI.shouldFoldConstantShiftPairToMask(N, Level)) { |
0 |
| 10400 |
auto MatchShiftAmount = [OpSizeInBits](ConstantSDNode *LHS, |
0 |
10400 |
auto MatchShiftAmount = [OpSizeInBits](ConstantSDNode *LHS, |
0 |
| 10401 |
ConstantSDNode *RHS) { |
0 |
10401 |
ConstantSDNode *RHS) { |
0 |
| 10402 |
const APInt &LHSC = LHS->getAPIntValue(); |
0 |
10402 |
const APInt &LHSC = LHS->getAPIntValue(); |
0 |
| 10403 |
const APInt &RHSC = RHS->getAPIntValue(); |
0 |
10403 |
const APInt &RHSC = RHS->getAPIntValue(); |
0 |
| 10404 |
return LHSC.ult(OpSizeInBits) && RHSC.ult(OpSizeInBits) && |
0 |
10404 |
return LHSC.ult(OpSizeInBits) && RHSC.ult(OpSizeInBits) && |
0 |
| 10405 |
LHSC.getZExtValue() <= RHSC.getZExtValue(); |
0 |
10405 |
LHSC.getZExtValue() <= RHSC.getZExtValue(); |
0 |
| 10406 |
}; |
0 |
10406 |
}; |
0 |
| 10407 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount, |
0 |
10407 |
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount, |
0 |
| 10408 |
/*AllowUndefs*/ false, |
--- |
10408 |
/*AllowUndefs*/ false, |
--- |
| 10409 |
/*AllowTypeMismatch*/ true)) { |
--- |
10409 |
/*AllowTypeMismatch*/ true)) { |
--- |
| 10410 |
SDLoc DL(N); |
0 |
10410 |
SDLoc DL(N); |
0 |
| 10411 |
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT); |
0 |
10411 |
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT); |
0 |
| 10412 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N01, N1); |
0 |
10412 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N01, N1); |
0 |
| 10413 |
SDValue Mask = DAG.getAllOnesConstant(DL, VT); |
0 |
10413 |
SDValue Mask = DAG.getAllOnesConstant(DL, VT); |
0 |
| 10414 |
Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N01); |
0 |
10414 |
Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N01); |
0 |
| 10415 |
Mask = DAG.getNode(ISD::SHL, DL, VT, Mask, Diff); |
0 |
10415 |
Mask = DAG.getNode(ISD::SHL, DL, VT, Mask, Diff); |
0 |
| 10416 |
SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff); |
0 |
10416 |
SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff); |
0 |
| 10417 |
return DAG.getNode(ISD::AND, DL, VT, Shift, Mask); |
0 |
10417 |
return DAG.getNode(ISD::AND, DL, VT, Shift, Mask); |
0 |
| 10418 |
} |
0 |
10418 |
} |
0 |
| 10419 |
if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount, |
0 |
10419 |
if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount, |
0 |
| 10420 |
/*AllowUndefs*/ false, |
--- |
10420 |
/*AllowUndefs*/ false, |
--- |
| 10421 |
/*AllowTypeMismatch*/ true)) { |
--- |
10421 |
/*AllowTypeMismatch*/ true)) { |
--- |
| 10422 |
SDLoc DL(N); |
0 |
10422 |
SDLoc DL(N); |
0 |
| 10423 |
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT); |
0 |
10423 |
SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT); |
0 |
| 10424 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N1, N01); |
0 |
10424 |
SDValue Diff = DAG.getNode(ISD::SUB, DL, ShiftVT, N1, N01); |
0 |
| 10425 |
SDValue Mask = DAG.getAllOnesConstant(DL, VT); |
0 |
10425 |
SDValue Mask = DAG.getAllOnesConstant(DL, VT); |
0 |
| 10426 |
Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N1); |
0 |
10426 |
Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N1); |
0 |
| 10427 |
SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff); |
0 |
10427 |
SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff); |
0 |
| 10428 |
return DAG.getNode(ISD::AND, DL, VT, Shift, Mask); |
0 |
10428 |
return DAG.getNode(ISD::AND, DL, VT, Shift, Mask); |
0 |
| 10429 |
} |
0 |
10429 |
} |
0 |
| 10430 |
} |
--- |
10430 |
} |
--- |
| 10431 |
|
--- |
10431 |
|
--- |
| 10432 |
// fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask) |
--- |
10432 |
// fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask) |
--- |
| 10433 |
// TODO - support non-uniform vector shift amounts. |
--- |
10433 |
// TODO - support non-uniform vector shift amounts. |
--- |
| 10434 |
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { |
0 |
10434 |
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { |
0 |
| 10435 |
// Shifting in all undef bits? |
--- |
10435 |
// Shifting in all undef bits? |
--- |
| 10436 |
EVT SmallVT = N0.getOperand(0).getValueType(); |
0 |
10436 |
EVT SmallVT = N0.getOperand(0).getValueType(); |
0 |
| 10437 |
unsigned BitSize = SmallVT.getScalarSizeInBits(); |
0 |
10437 |
unsigned BitSize = SmallVT.getScalarSizeInBits(); |
0 |
| 10438 |
if (N1C->getAPIntValue().uge(BitSize)) |
0 |
10438 |
if (N1C->getAPIntValue().uge(BitSize)) |
0 |
| 10439 |
return DAG.getUNDEF(VT); |
0 |
10439 |
return DAG.getUNDEF(VT); |
0 |
| 10440 |
|
--- |
10440 |
|
--- |
| 10441 |
if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { |
0 |
10441 |
if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { |
0 |
| 10442 |
uint64_t ShiftAmt = N1C->getZExtValue(); |
0 |
10442 |
uint64_t ShiftAmt = N1C->getZExtValue(); |
0 |
| 10443 |
SDLoc DL0(N0); |
0 |
10443 |
SDLoc DL0(N0); |
0 |
| 10444 |
SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT, |
0 |
10444 |
SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT, |
0 |
| 10445 |
N0.getOperand(0), |
0 |
10445 |
N0.getOperand(0), |
0 |
| 10446 |
DAG.getConstant(ShiftAmt, DL0, |
0 |
10446 |
DAG.getConstant(ShiftAmt, DL0, |
0 |
| 10447 |
getShiftAmountTy(SmallVT))); |
--- |
10447 |
getShiftAmountTy(SmallVT))); |
--- |
| 10448 |
AddToWorklist(SmallShift.getNode()); |
0 |
10448 |
AddToWorklist(SmallShift.getNode()); |
0 |
| 10449 |
APInt Mask = APInt::getLowBitsSet(OpSizeInBits, OpSizeInBits - ShiftAmt); |
0 |
10449 |
APInt Mask = APInt::getLowBitsSet(OpSizeInBits, OpSizeInBits - ShiftAmt); |
0 |
| 10450 |
SDLoc DL(N); |
0 |
10450 |
SDLoc DL(N); |
0 |
| 10451 |
return DAG.getNode(ISD::AND, DL, VT, |
0 |
10451 |
return DAG.getNode(ISD::AND, DL, VT, |
0 |
| 10452 |
DAG.getNode(ISD::ANY_EXTEND, DL, VT, SmallShift), |
0 |
10452 |
DAG.getNode(ISD::ANY_EXTEND, DL, VT, SmallShift), |
0 |
| 10453 |
DAG.getConstant(Mask, DL, VT)); |
0 |
10453 |
DAG.getConstant(Mask, DL, VT)); |
0 |
| 10454 |
} |
0 |
10454 |
} |
0 |
| 10455 |
} |
--- |
10455 |
} |
--- |
| 10456 |
|
--- |
10456 |
|
--- |
| 10457 |
// fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign |
--- |
10457 |
// fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign |
--- |
| 10458 |
// bit, which is unmodified by sra. |
--- |
10458 |
// bit, which is unmodified by sra. |
--- |
| 10459 |
if (N1C && N1C->getAPIntValue() == (OpSizeInBits - 1)) { |
0 |
10459 |
if (N1C && N1C->getAPIntValue() == (OpSizeInBits - 1)) { |
0 |
| 10460 |
if (N0.getOpcode() == ISD::SRA) |
0 |
10460 |
if (N0.getOpcode() == ISD::SRA) |
0 |
| 10461 |
return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1); |
0 |
10461 |
return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1); |
0 |
| 10462 |
} |
--- |
10462 |
} |
--- |
| 10463 |
|
--- |
10463 |
|
--- |
| 10464 |
// fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit), and x has a power |
--- |
10464 |
// fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit), and x has a power |
--- |
| 10465 |
// of two bitwidth. The "5" represents (log2 (bitwidth x)). |
--- |
10465 |
// of two bitwidth. The "5" represents (log2 (bitwidth x)). |
--- |
| 10466 |
if (N1C && N0.getOpcode() == ISD::CTLZ && |
0 |
10466 |
if (N1C && N0.getOpcode() == ISD::CTLZ && |
0 |
| 10467 |
isPowerOf2_32(OpSizeInBits) && |
0 |
10467 |
isPowerOf2_32(OpSizeInBits) && |
0 |
| 10468 |
N1C->getAPIntValue() == Log2_32(OpSizeInBits)) { |
0 |
10468 |
N1C->getAPIntValue() == Log2_32(OpSizeInBits)) { |
0 |
| 10469 |
KnownBits Known = DAG.computeKnownBits(N0.getOperand(0)); |
0 |
10469 |
KnownBits Known = DAG.computeKnownBits(N0.getOperand(0)); |
0 |
| 10470 |
|
--- |
10470 |
|
--- |
| 10471 |
// If any of the input bits are KnownOne, then the input couldn't be all |
--- |
10471 |
// If any of the input bits are KnownOne, then the input couldn't be all |
--- |
| 10472 |
// zeros, thus the result of the srl will always be zero. |
--- |
10472 |
// zeros, thus the result of the srl will always be zero. |
--- |
| 10473 |
if (Known.One.getBoolValue()) return DAG.getConstant(0, SDLoc(N0), VT); |
0 |
10473 |
if (Known.One.getBoolValue()) return DAG.getConstant(0, SDLoc(N0), VT); |
0 |
| 10474 |
|
--- |
10474 |
|
--- |
| 10475 |
// If all of the bits input the to ctlz node are known to be zero, then |
--- |
10475 |
// If all of the bits input the to ctlz node are known to be zero, then |
--- |
| 10476 |
// the result of the ctlz is "32" and the result of the shift is one. |
--- |
10476 |
// the result of the ctlz is "32" and the result of the shift is one. |
--- |
| 10477 |
APInt UnknownBits = ~Known.Zero; |
0 |
10477 |
APInt UnknownBits = ~Known.Zero; |
0 |
| 10478 |
if (UnknownBits == 0) return DAG.getConstant(1, SDLoc(N0), VT); |
0 |
10478 |
if (UnknownBits == 0) return DAG.getConstant(1, SDLoc(N0), VT); |
0 |
| 10479 |
|
--- |
10479 |
|
--- |
| 10480 |
// Otherwise, check to see if there is exactly one bit input to the ctlz. |
--- |
10480 |
// Otherwise, check to see if there is exactly one bit input to the ctlz. |
--- |
| 10481 |
if (UnknownBits.isPowerOf2()) { |
0 |
10481 |
if (UnknownBits.isPowerOf2()) { |
0 |
| 10482 |
// Okay, we know that only that the single bit specified by UnknownBits |
--- |
10482 |
// Okay, we know that only that the single bit specified by UnknownBits |
--- |
| 10483 |
// could be set on input to the CTLZ node. If this bit is set, the SRL |
--- |
10483 |
// could be set on input to the CTLZ node. If this bit is set, the SRL |
--- |
| 10484 |
// will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair |
--- |
10484 |
// will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair |
--- |
| 10485 |
// to an SRL/XOR pair, which is likely to simplify more. |
--- |
10485 |
// to an SRL/XOR pair, which is likely to simplify more. |
--- |
| 10486 |
unsigned ShAmt = UnknownBits.countr_zero(); |
0 |
10486 |
unsigned ShAmt = UnknownBits.countr_zero(); |
0 |
| 10487 |
SDValue Op = N0.getOperand(0); |
0 |
10487 |
SDValue Op = N0.getOperand(0); |
0 |
| 10488 |
|
--- |
10488 |
|
--- |
| 10489 |
if (ShAmt) { |
0 |
10489 |
if (ShAmt) { |
0 |
| 10490 |
SDLoc DL(N0); |
0 |
10490 |
SDLoc DL(N0); |
0 |
| 10491 |
Op = DAG.getNode(ISD::SRL, DL, VT, Op, |
0 |
10491 |
Op = DAG.getNode(ISD::SRL, DL, VT, Op, |
0 |
| 10492 |
DAG.getConstant(ShAmt, DL, |
0 |
10492 |
DAG.getConstant(ShAmt, DL, |
0 |
| 10493 |
getShiftAmountTy(Op.getValueType()))); |
--- |
10493 |
getShiftAmountTy(Op.getValueType()))); |
--- |
| 10494 |
AddToWorklist(Op.getNode()); |
0 |
10494 |
AddToWorklist(Op.getNode()); |
0 |
| 10495 |
} |
0 |
10495 |
} |
0 |
| 10496 |
|
--- |
10496 |
|
--- |
| 10497 |
SDLoc DL(N); |
0 |
10497 |
SDLoc DL(N); |
0 |
| 10498 |
return DAG.getNode(ISD::XOR, DL, VT, |
0 |
10498 |
return DAG.getNode(ISD::XOR, DL, VT, |
0 |
| 10499 |
Op, DAG.getConstant(1, DL, VT)); |
0 |
10499 |
Op, DAG.getConstant(1, DL, VT)); |
0 |
| 10500 |
} |
0 |
10500 |
} |
0 |
| 10501 |
} |
0 |
10501 |
} |
0 |
| 10502 |
|
--- |
10502 |
|
--- |
| 10503 |
// fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). |
--- |
10503 |
// fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). |
--- |
| 10504 |
if (N1.getOpcode() == ISD::TRUNCATE && |
0 |
10504 |
if (N1.getOpcode() == ISD::TRUNCATE && |
0 |
| 10505 |
N1.getOperand(0).getOpcode() == ISD::AND) { |
0 |
10505 |
N1.getOperand(0).getOpcode() == ISD::AND) { |
0 |
| 10506 |
if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode())) |
0 |
10506 |
if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode())) |
0 |
| 10507 |
return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1); |
0 |
10507 |
return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1); |
0 |
| 10508 |
} |
--- |
10508 |
} |
--- |
| 10509 |
|
--- |
10509 |
|
--- |
| 10510 |
// fold operands of srl based on knowledge that the low bits are not |
--- |
10510 |
// fold operands of srl based on knowledge that the low bits are not |
--- |
| 10511 |
// demanded. |
--- |
10511 |
// demanded. |
--- |
| 10512 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
10512 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
| 10513 |
return SDValue(N, 0); |
0 |
10513 |
return SDValue(N, 0); |
0 |
| 10514 |
|
--- |
10514 |
|
--- |
| 10515 |
if (N1C && !N1C->isOpaque()) |
0 |
10515 |
if (N1C && !N1C->isOpaque()) |
0 |
| 10516 |
if (SDValue NewSRL = visitShiftByConstant(N)) |
0 |
10516 |
if (SDValue NewSRL = visitShiftByConstant(N)) |
0 |
| 10517 |
return NewSRL; |
0 |
10517 |
return NewSRL; |
0 |
| 10518 |
|
--- |
10518 |
|
--- |
| 10519 |
// Attempt to convert a srl of a load into a narrower zero-extending load. |
--- |
10519 |
// Attempt to convert a srl of a load into a narrower zero-extending load. |
--- |
| 10520 |
if (SDValue NarrowLoad = reduceLoadWidth(N)) |
0 |
10520 |
if (SDValue NarrowLoad = reduceLoadWidth(N)) |
0 |
| 10521 |
return NarrowLoad; |
0 |
10521 |
return NarrowLoad; |
0 |
| 10522 |
|
--- |
10522 |
|
--- |
| 10523 |
// Here is a common situation. We want to optimize: |
--- |
10523 |
// Here is a common situation. We want to optimize: |
--- |
| 10524 |
// |
--- |
10524 |
// |
--- |
| 10525 |
// %a = ... |
--- |
10525 |
// %a = ... |
--- |
| 10526 |
// %b = and i32 %a, 2 |
--- |
10526 |
// %b = and i32 %a, 2 |
--- |
| 10527 |
// %c = srl i32 %b, 1 |
--- |
10527 |
// %c = srl i32 %b, 1 |
--- |
| 10528 |
// brcond i32 %c ... |
--- |
10528 |
// brcond i32 %c ... |
--- |
| 10529 |
// |
--- |
10529 |
// |
--- |
| 10530 |
// into |
--- |
10530 |
// into |
--- |
| 10531 |
// |
--- |
10531 |
// |
--- |
| 10532 |
// %a = ... |
--- |
10532 |
// %a = ... |
--- |
| 10533 |
// %b = and %a, 2 |
--- |
10533 |
// %b = and %a, 2 |
--- |
| 10534 |
// %c = setcc eq %b, 0 |
--- |
10534 |
// %c = setcc eq %b, 0 |
--- |
| 10535 |
// brcond %c ... |
--- |
10535 |
// brcond %c ... |
--- |
| 10536 |
// |
--- |
10536 |
// |
--- |
| 10537 |
// However when after the source operand of SRL is optimized into AND, the SRL |
--- |
10537 |
// However when after the source operand of SRL is optimized into AND, the SRL |
--- |
| 10538 |
// itself may not be optimized further. Look for it and add the BRCOND into |
--- |
10538 |
// itself may not be optimized further. Look for it and add the BRCOND into |
--- |
| 10539 |
// the worklist. |
--- |
10539 |
// the worklist. |
--- |
| 10540 |
// |
--- |
10540 |
// |
--- |
| 10541 |
// The also tends to happen for binary operations when SimplifyDemandedBits |
--- |
10541 |
// The also tends to happen for binary operations when SimplifyDemandedBits |
--- |
| 10542 |
// is involved. |
--- |
10542 |
// is involved. |
--- |
| 10543 |
// |
--- |
10543 |
// |
--- |
| 10544 |
// FIXME: This is unecessary if we process the DAG in topological order, |
--- |
10544 |
// FIXME: This is unecessary if we process the DAG in topological order, |
--- |
| 10545 |
// which we plan to do. This workaround can be removed once the DAG is |
--- |
10545 |
// which we plan to do. This workaround can be removed once the DAG is |
--- |
| 10546 |
// processed in topological order. |
--- |
10546 |
// processed in topological order. |
--- |
| 10547 |
if (N->hasOneUse()) { |
0 |
10547 |
if (N->hasOneUse()) { |
0 |
| 10548 |
SDNode *Use = *N->use_begin(); |
0 |
10548 |
SDNode *Use = *N->use_begin(); |
0 |
| 10549 |
|
--- |
10549 |
|
--- |
| 10550 |
// Look pass the truncate. |
--- |
10550 |
// Look pass the truncate. |
--- |
| 10551 |
if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) |
0 |
10551 |
if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) |
0 |
| 10552 |
Use = *Use->use_begin(); |
0 |
10552 |
Use = *Use->use_begin(); |
0 |
| 10553 |
|
--- |
10553 |
|
--- |
| 10554 |
if (Use->getOpcode() == ISD::BRCOND || Use->getOpcode() == ISD::AND || |
0 |
10554 |
if (Use->getOpcode() == ISD::BRCOND || Use->getOpcode() == ISD::AND || |
0 |
| 10555 |
Use->getOpcode() == ISD::OR || Use->getOpcode() == ISD::XOR) |
0 |
10555 |
Use->getOpcode() == ISD::OR || Use->getOpcode() == ISD::XOR) |
0 |
| 10556 |
AddToWorklist(Use); |
0 |
10556 |
AddToWorklist(Use); |
0 |
| 10557 |
} |
--- |
10557 |
} |
--- |
| 10558 |
|
--- |
10558 |
|
--- |
| 10559 |
// Try to transform this shift into a multiply-high if |
--- |
10559 |
// Try to transform this shift into a multiply-high if |
--- |
| 10560 |
// it matches the appropriate pattern detected in combineShiftToMULH. |
--- |
10560 |
// it matches the appropriate pattern detected in combineShiftToMULH. |
--- |
| 10561 |
if (SDValue MULH = combineShiftToMULH(N, DAG, TLI)) |
0 |
10561 |
if (SDValue MULH = combineShiftToMULH(N, DAG, TLI)) |
0 |
| 10562 |
return MULH; |
0 |
10562 |
return MULH; |
0 |
| 10563 |
|
--- |
10563 |
|
--- |
| 10564 |
return SDValue(); |
0 |
10564 |
return SDValue(); |
0 |
| 10565 |
} |
--- |
10565 |
} |
--- |
| 10566 |
|
--- |
10566 |
|
--- |
| 10567 |
SDValue DAGCombiner::visitFunnelShift(SDNode *N) { |
0 |
10567 |
SDValue DAGCombiner::visitFunnelShift(SDNode *N) { |
0 |
| 10568 |
EVT VT = N->getValueType(0); |
0 |
10568 |
EVT VT = N->getValueType(0); |
0 |
| 10569 |
SDValue N0 = N->getOperand(0); |
0 |
10569 |
SDValue N0 = N->getOperand(0); |
0 |
| 10570 |
SDValue N1 = N->getOperand(1); |
0 |
10570 |
SDValue N1 = N->getOperand(1); |
0 |
| 10571 |
SDValue N2 = N->getOperand(2); |
0 |
10571 |
SDValue N2 = N->getOperand(2); |
0 |
| 10572 |
bool IsFSHL = N->getOpcode() == ISD::FSHL; |
0 |
10572 |
bool IsFSHL = N->getOpcode() == ISD::FSHL; |
0 |
| 10573 |
unsigned BitWidth = VT.getScalarSizeInBits(); |
0 |
10573 |
unsigned BitWidth = VT.getScalarSizeInBits(); |
0 |
| 10574 |
|
--- |
10574 |
|
--- |
| 10575 |
// fold (fshl N0, N1, 0) -> N0 |
--- |
10575 |
// fold (fshl N0, N1, 0) -> N0 |
--- |
| 10576 |
// fold (fshr N0, N1, 0) -> N1 |
--- |
10576 |
// fold (fshr N0, N1, 0) -> N1 |
--- |
| 10577 |
if (isPowerOf2_32(BitWidth)) |
0 |
10577 |
if (isPowerOf2_32(BitWidth)) |
0 |
| 10578 |
if (DAG.MaskedValueIsZero( |
0 |
10578 |
if (DAG.MaskedValueIsZero( |
0 |
| 10579 |
N2, APInt(N2.getScalarValueSizeInBits(), BitWidth - 1))) |
0 |
10579 |
N2, APInt(N2.getScalarValueSizeInBits(), BitWidth - 1))) |
0 |
| 10580 |
return IsFSHL ? N0 : N1; |
0 |
10580 |
return IsFSHL ? N0 : N1; |
0 |
| 10581 |
|
--- |
10581 |
|
--- |
| 10582 |
auto IsUndefOrZero = [](SDValue V) { |
0 |
10582 |
auto IsUndefOrZero = [](SDValue V) { |
0 |
| 10583 |
return V.isUndef() || isNullOrNullSplat(V, /*AllowUndefs*/ true); |
0 |
10583 |
return V.isUndef() || isNullOrNullSplat(V, /*AllowUndefs*/ true); |
0 |
| 10584 |
}; |
--- |
10584 |
}; |
--- |
| 10585 |
|
--- |
10585 |
|
--- |
| 10586 |
// TODO - support non-uniform vector shift amounts. |
--- |
10586 |
// TODO - support non-uniform vector shift amounts. |
--- |
| 10587 |
if (ConstantSDNode *Cst = isConstOrConstSplat(N2)) { |
0 |
10587 |
if (ConstantSDNode *Cst = isConstOrConstSplat(N2)) { |
0 |
| 10588 |
EVT ShAmtTy = N2.getValueType(); |
0 |
10588 |
EVT ShAmtTy = N2.getValueType(); |
0 |
| 10589 |
|
--- |
10589 |
|
--- |
| 10590 |
// fold (fsh* N0, N1, c) -> (fsh* N0, N1, c % BitWidth) |
--- |
10590 |
// fold (fsh* N0, N1, c) -> (fsh* N0, N1, c % BitWidth) |
--- |
| 10591 |
if (Cst->getAPIntValue().uge(BitWidth)) { |
0 |
10591 |
if (Cst->getAPIntValue().uge(BitWidth)) { |
0 |
| 10592 |
uint64_t RotAmt = Cst->getAPIntValue().urem(BitWidth); |
0 |
10592 |
uint64_t RotAmt = Cst->getAPIntValue().urem(BitWidth); |
0 |
| 10593 |
return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0, N1, |
0 |
10593 |
return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0, N1, |
0 |
| 10594 |
DAG.getConstant(RotAmt, SDLoc(N), ShAmtTy)); |
0 |
10594 |
DAG.getConstant(RotAmt, SDLoc(N), ShAmtTy)); |
0 |
| 10595 |
} |
--- |
10595 |
} |
--- |
| 10596 |
|
--- |
10596 |
|
--- |
| 10597 |
unsigned ShAmt = Cst->getZExtValue(); |
0 |
10597 |
unsigned ShAmt = Cst->getZExtValue(); |
0 |
| 10598 |
if (ShAmt == 0) |
0 |
10598 |
if (ShAmt == 0) |
0 |
| 10599 |
return IsFSHL ? N0 : N1; |
0 |
10599 |
return IsFSHL ? N0 : N1; |
0 |
| 10600 |
|
--- |
10600 |
|
--- |
| 10601 |
// fold fshl(undef_or_zero, N1, C) -> lshr(N1, BW-C) |
--- |
10601 |
// fold fshl(undef_or_zero, N1, C) -> lshr(N1, BW-C) |
--- |
| 10602 |
// fold fshr(undef_or_zero, N1, C) -> lshr(N1, C) |
--- |
10602 |
// fold fshr(undef_or_zero, N1, C) -> lshr(N1, C) |
--- |
| 10603 |
// fold fshl(N0, undef_or_zero, C) -> shl(N0, C) |
--- |
10603 |
// fold fshl(N0, undef_or_zero, C) -> shl(N0, C) |
--- |
| 10604 |
// fold fshr(N0, undef_or_zero, C) -> shl(N0, BW-C) |
--- |
10604 |
// fold fshr(N0, undef_or_zero, C) -> shl(N0, BW-C) |
--- |
| 10605 |
if (IsUndefOrZero(N0)) |
0 |
10605 |
if (IsUndefOrZero(N0)) |
0 |
| 10606 |
return DAG.getNode(ISD::SRL, SDLoc(N), VT, N1, |
0 |
10606 |
return DAG.getNode(ISD::SRL, SDLoc(N), VT, N1, |
0 |
| 10607 |
DAG.getConstant(IsFSHL ? BitWidth - ShAmt : ShAmt, |
0 |
10607 |
DAG.getConstant(IsFSHL ? BitWidth - ShAmt : ShAmt, |
0 |
| 10608 |
SDLoc(N), ShAmtTy)); |
0 |
10608 |
SDLoc(N), ShAmtTy)); |
0 |
| 10609 |
if (IsUndefOrZero(N1)) |
0 |
10609 |
if (IsUndefOrZero(N1)) |
0 |
| 10610 |
return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, |
0 |
10610 |
return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, |
0 |
| 10611 |
DAG.getConstant(IsFSHL ? ShAmt : BitWidth - ShAmt, |
0 |
10611 |
DAG.getConstant(IsFSHL ? ShAmt : BitWidth - ShAmt, |
0 |
| 10612 |
SDLoc(N), ShAmtTy)); |
0 |
10612 |
SDLoc(N), ShAmtTy)); |
0 |
| 10613 |
|
--- |
10613 |
|
--- |
| 10614 |
// fold (fshl ld1, ld0, c) -> (ld0[ofs]) iff ld0 and ld1 are consecutive. |
--- |
10614 |
// fold (fshl ld1, ld0, c) -> (ld0[ofs]) iff ld0 and ld1 are consecutive. |
--- |
| 10615 |
// fold (fshr ld1, ld0, c) -> (ld0[ofs]) iff ld0 and ld1 are consecutive. |
--- |
10615 |
// fold (fshr ld1, ld0, c) -> (ld0[ofs]) iff ld0 and ld1 are consecutive. |
--- |
| 10616 |
// TODO - bigendian support once we have test coverage. |
--- |
10616 |
// TODO - bigendian support once we have test coverage. |
--- |
| 10617 |
// TODO - can we merge this with CombineConseutiveLoads/MatchLoadCombine? |
--- |
10617 |
// TODO - can we merge this with CombineConseutiveLoads/MatchLoadCombine? |
--- |
| 10618 |
// TODO - permit LHS EXTLOAD if extensions are shifted out. |
--- |
10618 |
// TODO - permit LHS EXTLOAD if extensions are shifted out. |
--- |
| 10619 |
if ((BitWidth % 8) == 0 && (ShAmt % 8) == 0 && !VT.isVector() && |
0 |
10619 |
if ((BitWidth % 8) == 0 && (ShAmt % 8) == 0 && !VT.isVector() && |
0 |
| 10620 |
!DAG.getDataLayout().isBigEndian()) { |
0 |
10620 |
!DAG.getDataLayout().isBigEndian()) { |
0 |
| 10621 |
auto *LHS = dyn_cast(N0); |
0 |
10621 |
auto *LHS = dyn_cast(N0); |
0 |
| 10622 |
auto *RHS = dyn_cast(N1); |
0 |
10622 |
auto *RHS = dyn_cast(N1); |
0 |
| 10623 |
if (LHS && RHS && LHS->isSimple() && RHS->isSimple() && |
0 |
10623 |
if (LHS && RHS && LHS->isSimple() && RHS->isSimple() && |
0 |
| 10624 |
LHS->getAddressSpace() == RHS->getAddressSpace() && |
0 |
10624 |
LHS->getAddressSpace() == RHS->getAddressSpace() && |
0 |
| 10625 |
(LHS->hasOneUse() || RHS->hasOneUse()) && ISD::isNON_EXTLoad(RHS) && |
0 |
10625 |
(LHS->hasOneUse() || RHS->hasOneUse()) && ISD::isNON_EXTLoad(RHS) && |
0 |
| 10626 |
ISD::isNON_EXTLoad(LHS)) { |
0 |
10626 |
ISD::isNON_EXTLoad(LHS)) { |
0 |
| 10627 |
if (DAG.areNonVolatileConsecutiveLoads(LHS, RHS, BitWidth / 8, 1)) { |
0 |
10627 |
if (DAG.areNonVolatileConsecutiveLoads(LHS, RHS, BitWidth / 8, 1)) { |
0 |
| 10628 |
SDLoc DL(RHS); |
0 |
10628 |
SDLoc DL(RHS); |
0 |
| 10629 |
uint64_t PtrOff = |
0 |
10629 |
uint64_t PtrOff = |
0 |
| 10630 |
IsFSHL ? (((BitWidth - ShAmt) % BitWidth) / 8) : (ShAmt / 8); |
0 |
10630 |
IsFSHL ? (((BitWidth - ShAmt) % BitWidth) / 8) : (ShAmt / 8); |
0 |
| 10631 |
Align NewAlign = commonAlignment(RHS->getAlign(), PtrOff); |
0 |
10631 |
Align NewAlign = commonAlignment(RHS->getAlign(), PtrOff); |
0 |
| 10632 |
unsigned Fast = 0; |
0 |
10632 |
unsigned Fast = 0; |
0 |
| 10633 |
if (TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, |
0 |
10633 |
if (TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, |
0 |
| 10634 |
RHS->getAddressSpace(), NewAlign, |
--- |
10634 |
RHS->getAddressSpace(), NewAlign, |
--- |
| 10635 |
RHS->getMemOperand()->getFlags(), &Fast) && |
0 |
10635 |
RHS->getMemOperand()->getFlags(), &Fast) && |
0 |
| 10636 |
Fast) { |
0 |
10636 |
Fast) { |
0 |
| 10637 |
SDValue NewPtr = DAG.getMemBasePlusOffset( |
0 |
10637 |
SDValue NewPtr = DAG.getMemBasePlusOffset( |
0 |
| 10638 |
RHS->getBasePtr(), TypeSize::Fixed(PtrOff), DL); |
0 |
10638 |
RHS->getBasePtr(), TypeSize::Fixed(PtrOff), DL); |
0 |
| 10639 |
AddToWorklist(NewPtr.getNode()); |
0 |
10639 |
AddToWorklist(NewPtr.getNode()); |
0 |
| 10640 |
SDValue Load = DAG.getLoad( |
0 |
10640 |
SDValue Load = DAG.getLoad( |
0 |
| 10641 |
VT, DL, RHS->getChain(), NewPtr, |
0 |
10641 |
VT, DL, RHS->getChain(), NewPtr, |
0 |
| 10642 |
RHS->getPointerInfo().getWithOffset(PtrOff), NewAlign, |
0 |
10642 |
RHS->getPointerInfo().getWithOffset(PtrOff), NewAlign, |
0 |
| 10643 |
RHS->getMemOperand()->getFlags(), RHS->getAAInfo()); |
0 |
10643 |
RHS->getMemOperand()->getFlags(), RHS->getAAInfo()); |
0 |
| 10644 |
// Replace the old load's chain with the new load's chain. |
--- |
10644 |
// Replace the old load's chain with the new load's chain. |
--- |
| 10645 |
WorklistRemover DeadNodes(*this); |
0 |
10645 |
WorklistRemover DeadNodes(*this); |
0 |
| 10646 |
DAG.ReplaceAllUsesOfValueWith(N1.getValue(1), Load.getValue(1)); |
0 |
10646 |
DAG.ReplaceAllUsesOfValueWith(N1.getValue(1), Load.getValue(1)); |
0 |
| 10647 |
return Load; |
0 |
10647 |
return Load; |
0 |
| 10648 |
} |
0 |
10648 |
} |
0 |
| 10649 |
} |
0 |
10649 |
} |
0 |
| 10650 |
} |
--- |
10650 |
} |
--- |
| 10651 |
} |
--- |
10651 |
} |
--- |
| 10652 |
} |
--- |
10652 |
} |
--- |
| 10653 |
|
--- |
10653 |
|
--- |
| 10654 |
// fold fshr(undef_or_zero, N1, N2) -> lshr(N1, N2) |
--- |
10654 |
// fold fshr(undef_or_zero, N1, N2) -> lshr(N1, N2) |
--- |
| 10655 |
// fold fshl(N0, undef_or_zero, N2) -> shl(N0, N2) |
--- |
10655 |
// fold fshl(N0, undef_or_zero, N2) -> shl(N0, N2) |
--- |
| 10656 |
// iff We know the shift amount is in range. |
--- |
10656 |
// iff We know the shift amount is in range. |
--- |
| 10657 |
// TODO: when is it worth doing SUB(BW, N2) as well? |
--- |
10657 |
// TODO: when is it worth doing SUB(BW, N2) as well? |
--- |
| 10658 |
if (isPowerOf2_32(BitWidth)) { |
0 |
10658 |
if (isPowerOf2_32(BitWidth)) { |
0 |
| 10659 |
APInt ModuloBits(N2.getScalarValueSizeInBits(), BitWidth - 1); |
0 |
10659 |
APInt ModuloBits(N2.getScalarValueSizeInBits(), BitWidth - 1); |
0 |
| 10660 |
if (IsUndefOrZero(N0) && !IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits)) |
0 |
10660 |
if (IsUndefOrZero(N0) && !IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits)) |
0 |
| 10661 |
return DAG.getNode(ISD::SRL, SDLoc(N), VT, N1, N2); |
0 |
10661 |
return DAG.getNode(ISD::SRL, SDLoc(N), VT, N1, N2); |
0 |
| 10662 |
if (IsUndefOrZero(N1) && IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits)) |
0 |
10662 |
if (IsUndefOrZero(N1) && IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits)) |
0 |
| 10663 |
return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, N2); |
0 |
10663 |
return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, N2); |
0 |
| 10664 |
} |
0 |
10664 |
} |
0 |
| 10665 |
|
--- |
10665 |
|
--- |
| 10666 |
// fold (fshl N0, N0, N2) -> (rotl N0, N2) |
--- |
10666 |
// fold (fshl N0, N0, N2) -> (rotl N0, N2) |
--- |
| 10667 |
// fold (fshr N0, N0, N2) -> (rotr N0, N2) |
--- |
10667 |
// fold (fshr N0, N0, N2) -> (rotr N0, N2) |
--- |
| 10668 |
// TODO: Investigate flipping this rotate if only one is legal, if funnel shift |
--- |
10668 |
// TODO: Investigate flipping this rotate if only one is legal, if funnel shift |
--- |
| 10669 |
// is legal as well we might be better off avoiding non-constant (BW - N2). |
--- |
10669 |
// is legal as well we might be better off avoiding non-constant (BW - N2). |
--- |
| 10670 |
unsigned RotOpc = IsFSHL ? ISD::ROTL : ISD::ROTR; |
0 |
10670 |
unsigned RotOpc = IsFSHL ? ISD::ROTL : ISD::ROTR; |
0 |
| 10671 |
if (N0 == N1 && hasOperation(RotOpc, VT)) |
0 |
10671 |
if (N0 == N1 && hasOperation(RotOpc, VT)) |
0 |
| 10672 |
return DAG.getNode(RotOpc, SDLoc(N), VT, N0, N2); |
0 |
10672 |
return DAG.getNode(RotOpc, SDLoc(N), VT, N0, N2); |
0 |
| 10673 |
|
--- |
10673 |
|
--- |
| 10674 |
// Simplify, based on bits shifted out of N0/N1. |
--- |
10674 |
// Simplify, based on bits shifted out of N0/N1. |
--- |
| 10675 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
10675 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
| 10676 |
return SDValue(N, 0); |
0 |
10676 |
return SDValue(N, 0); |
0 |
| 10677 |
|
--- |
10677 |
|
--- |
| 10678 |
return SDValue(); |
0 |
10678 |
return SDValue(); |
0 |
| 10679 |
} |
--- |
10679 |
} |
--- |
| 10680 |
|
--- |
10680 |
|
--- |
| 10681 |
SDValue DAGCombiner::visitSHLSAT(SDNode *N) { |
0 |
10681 |
SDValue DAGCombiner::visitSHLSAT(SDNode *N) { |
0 |
| 10682 |
SDValue N0 = N->getOperand(0); |
0 |
10682 |
SDValue N0 = N->getOperand(0); |
0 |
| 10683 |
SDValue N1 = N->getOperand(1); |
0 |
10683 |
SDValue N1 = N->getOperand(1); |
0 |
| 10684 |
if (SDValue V = DAG.simplifyShift(N0, N1)) |
0 |
10684 |
if (SDValue V = DAG.simplifyShift(N0, N1)) |
0 |
| 10685 |
return V; |
0 |
10685 |
return V; |
0 |
| 10686 |
|
--- |
10686 |
|
--- |
| 10687 |
EVT VT = N0.getValueType(); |
0 |
10687 |
EVT VT = N0.getValueType(); |
0 |
| 10688 |
|
--- |
10688 |
|
--- |
| 10689 |
// fold (*shlsat c1, c2) -> c1<
| --- |
10689 |
// fold (*shlsat c1, c2) -> c1<
| --- |
| |
| 10690 |
if (SDValue C = |
0 |
10690 |
if (SDValue C = |
0 |
| 10691 |
DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, {N0, N1})) |
0 |
10691 |
DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, {N0, N1})) |
0 |
| 10692 |
return C; |
0 |
10692 |
return C; |
0 |
| 10693 |
|
--- |
10693 |
|
--- |
| 10694 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
10694 |
ConstantSDNode *N1C = isConstOrConstSplat(N1); |
0 |
| 10695 |
|
--- |
10695 |
|
--- |
| 10696 |
if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::SHL, VT)) { |
0 |
10696 |
if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::SHL, VT)) { |
0 |
| 10697 |
// fold (sshlsat x, c) -> (shl x, c) |
--- |
10697 |
// fold (sshlsat x, c) -> (shl x, c) |
--- |
| 10698 |
if (N->getOpcode() == ISD::SSHLSAT && N1C && |
0 |
10698 |
if (N->getOpcode() == ISD::SSHLSAT && N1C && |
0 |
| 10699 |
N1C->getAPIntValue().ult(DAG.ComputeNumSignBits(N0))) |
0 |
10699 |
N1C->getAPIntValue().ult(DAG.ComputeNumSignBits(N0))) |
0 |
| 10700 |
return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, N1); |
0 |
10700 |
return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, N1); |
0 |
| 10701 |
|
--- |
10701 |
|
--- |
| 10702 |
// fold (ushlsat x, c) -> (shl x, c) |
--- |
10702 |
// fold (ushlsat x, c) -> (shl x, c) |
--- |
| 10703 |
if (N->getOpcode() == ISD::USHLSAT && N1C && |
0 |
10703 |
if (N->getOpcode() == ISD::USHLSAT && N1C && |
0 |
| 10704 |
N1C->getAPIntValue().ule( |
0 |
10704 |
N1C->getAPIntValue().ule( |
0 |
| 10705 |
DAG.computeKnownBits(N0).countMinLeadingZeros())) |
0 |
10705 |
DAG.computeKnownBits(N0).countMinLeadingZeros())) |
0 |
| 10706 |
return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, N1); |
0 |
10706 |
return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, N1); |
0 |
| 10707 |
} |
--- |
10707 |
} |
--- |
| 10708 |
|
--- |
10708 |
|
--- |
| 10709 |
return SDValue(); |
0 |
10709 |
return SDValue(); |
0 |
| 10710 |
} |
--- |
10710 |
} |
--- |
| 10711 |
|
--- |
10711 |
|
--- |
| 10712 |
// Given a ABS node, detect the following patterns: |
--- |
10712 |
// Given a ABS node, detect the following patterns: |
--- |
| 10713 |
// (ABS (SUB (EXTEND a), (EXTEND b))). |
--- |
10713 |
// (ABS (SUB (EXTEND a), (EXTEND b))). |
--- |
| 10714 |
// (TRUNC (ABS (SUB (EXTEND a), (EXTEND b)))). |
--- |
10714 |
// (TRUNC (ABS (SUB (EXTEND a), (EXTEND b)))). |
--- |
| 10715 |
// Generates UABD/SABD instruction. |
--- |
10715 |
// Generates UABD/SABD instruction. |
--- |
| 10716 |
SDValue DAGCombiner::foldABSToABD(SDNode *N) { |
0 |
10716 |
SDValue DAGCombiner::foldABSToABD(SDNode *N) { |
0 |
| 10717 |
EVT SrcVT = N->getValueType(0); |
0 |
10717 |
EVT SrcVT = N->getValueType(0); |
0 |
| 10718 |
|
--- |
10718 |
|
--- |
| 10719 |
if (N->getOpcode() == ISD::TRUNCATE) |
0 |
10719 |
if (N->getOpcode() == ISD::TRUNCATE) |
0 |
| 10720 |
N = N->getOperand(0).getNode(); |
0 |
10720 |
N = N->getOperand(0).getNode(); |
0 |
| 10721 |
|
--- |
10721 |
|
--- |
| 10722 |
if (N->getOpcode() != ISD::ABS) |
0 |
10722 |
if (N->getOpcode() != ISD::ABS) |
0 |
| 10723 |
return SDValue(); |
0 |
10723 |
return SDValue(); |
0 |
| 10724 |
|
--- |
10724 |
|
--- |
| 10725 |
EVT VT = N->getValueType(0); |
0 |
10725 |
EVT VT = N->getValueType(0); |
0 |
| 10726 |
SDValue AbsOp1 = N->getOperand(0); |
0 |
10726 |
SDValue AbsOp1 = N->getOperand(0); |
0 |
| 10727 |
SDValue Op0, Op1; |
0 |
10727 |
SDValue Op0, Op1; |
0 |
| 10728 |
SDLoc DL(N); |
0 |
10728 |
SDLoc DL(N); |
0 |
| 10729 |
|
--- |
10729 |
|
--- |
| 10730 |
if (AbsOp1.getOpcode() != ISD::SUB) |
0 |
10730 |
if (AbsOp1.getOpcode() != ISD::SUB) |
0 |
| 10731 |
return SDValue(); |
0 |
10731 |
return SDValue(); |
0 |
| 10732 |
|
--- |
10732 |
|
--- |
| 10733 |
Op0 = AbsOp1.getOperand(0); |
0 |
10733 |
Op0 = AbsOp1.getOperand(0); |
0 |
| 10734 |
Op1 = AbsOp1.getOperand(1); |
0 |
10734 |
Op1 = AbsOp1.getOperand(1); |
0 |
| 10735 |
|
--- |
10735 |
|
--- |
| 10736 |
unsigned Opc0 = Op0.getOpcode(); |
0 |
10736 |
unsigned Opc0 = Op0.getOpcode(); |
0 |
| 10737 |
// Check if the operands of the sub are (zero|sign)-extended. |
--- |
10737 |
// Check if the operands of the sub are (zero|sign)-extended. |
--- |
| 10738 |
if (Opc0 != Op1.getOpcode() || |
0 |
10738 |
if (Opc0 != Op1.getOpcode() || |
0 |
| 10739 |
(Opc0 != ISD::ZERO_EXTEND && Opc0 != ISD::SIGN_EXTEND)) { |
0 |
10739 |
(Opc0 != ISD::ZERO_EXTEND && Opc0 != ISD::SIGN_EXTEND)) { |
0 |
| 10740 |
// fold (abs (sub nsw x, y)) -> abds(x, y) |
--- |
10740 |
// fold (abs (sub nsw x, y)) -> abds(x, y) |
--- |
| 10741 |
if (AbsOp1->getFlags().hasNoSignedWrap() && hasOperation(ISD::ABDS, VT) && |
0 |
10741 |
if (AbsOp1->getFlags().hasNoSignedWrap() && hasOperation(ISD::ABDS, VT) && |
0 |
| 10742 |
TLI.preferABDSToABSWithNSW(VT)) { |
0 |
10742 |
TLI.preferABDSToABSWithNSW(VT)) { |
0 |
| 10743 |
SDValue ABD = DAG.getNode(ISD::ABDS, DL, VT, Op0, Op1); |
0 |
10743 |
SDValue ABD = DAG.getNode(ISD::ABDS, DL, VT, Op0, Op1); |
0 |
| 10744 |
return DAG.getZExtOrTrunc(ABD, DL, SrcVT); |
0 |
10744 |
return DAG.getZExtOrTrunc(ABD, DL, SrcVT); |
0 |
| 10745 |
} |
--- |
10745 |
} |
--- |
| 10746 |
return SDValue(); |
0 |
10746 |
return SDValue(); |
0 |
| 10747 |
} |
--- |
10747 |
} |
--- |
| 10748 |
|
--- |
10748 |
|
--- |
| 10749 |
EVT VT1 = Op0.getOperand(0).getValueType(); |
0 |
10749 |
EVT VT1 = Op0.getOperand(0).getValueType(); |
0 |
| 10750 |
EVT VT2 = Op1.getOperand(0).getValueType(); |
0 |
10750 |
EVT VT2 = Op1.getOperand(0).getValueType(); |
0 |
| 10751 |
unsigned ABDOpcode = (Opc0 == ISD::SIGN_EXTEND) ? ISD::ABDS : ISD::ABDU; |
0 |
10751 |
unsigned ABDOpcode = (Opc0 == ISD::SIGN_EXTEND) ? ISD::ABDS : ISD::ABDU; |
0 |
| 10752 |
|
--- |
10752 |
|
--- |
| 10753 |
// fold abs(sext(x) - sext(y)) -> zext(abds(x, y)) |
--- |
10753 |
// fold abs(sext(x) - sext(y)) -> zext(abds(x, y)) |
--- |
| 10754 |
// fold abs(zext(x) - zext(y)) -> zext(abdu(x, y)) |
--- |
10754 |
// fold abs(zext(x) - zext(y)) -> zext(abdu(x, y)) |
--- |
| 10755 |
// NOTE: Extensions must be equivalent. |
--- |
10755 |
// NOTE: Extensions must be equivalent. |
--- |
| 10756 |
if (VT1 == VT2 && hasOperation(ABDOpcode, VT1)) { |
0 |
10756 |
if (VT1 == VT2 && hasOperation(ABDOpcode, VT1)) { |
0 |
| 10757 |
Op0 = Op0.getOperand(0); |
0 |
10757 |
Op0 = Op0.getOperand(0); |
0 |
| 10758 |
Op1 = Op1.getOperand(0); |
0 |
10758 |
Op1 = Op1.getOperand(0); |
0 |
| 10759 |
SDValue ABD = DAG.getNode(ABDOpcode, DL, VT1, Op0, Op1); |
0 |
10759 |
SDValue ABD = DAG.getNode(ABDOpcode, DL, VT1, Op0, Op1); |
0 |
| 10760 |
ABD = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, ABD); |
0 |
10760 |
ABD = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, ABD); |
0 |
| 10761 |
return DAG.getZExtOrTrunc(ABD, DL, SrcVT); |
0 |
10761 |
return DAG.getZExtOrTrunc(ABD, DL, SrcVT); |
0 |
| 10762 |
} |
--- |
10762 |
} |
--- |
| 10763 |
|
--- |
10763 |
|
--- |
| 10764 |
// fold abs(sext(x) - sext(y)) -> abds(sext(x), sext(y)) |
--- |
10764 |
// fold abs(sext(x) - sext(y)) -> abds(sext(x), sext(y)) |
--- |
| 10765 |
// fold abs(zext(x) - zext(y)) -> abdu(zext(x), zext(y)) |
--- |
10765 |
// fold abs(zext(x) - zext(y)) -> abdu(zext(x), zext(y)) |
--- |
| 10766 |
if (hasOperation(ABDOpcode, VT)) { |
0 |
10766 |
if (hasOperation(ABDOpcode, VT)) { |
0 |
| 10767 |
SDValue ABD = DAG.getNode(ABDOpcode, DL, VT, Op0, Op1); |
0 |
10767 |
SDValue ABD = DAG.getNode(ABDOpcode, DL, VT, Op0, Op1); |
0 |
| 10768 |
return DAG.getZExtOrTrunc(ABD, DL, SrcVT); |
0 |
10768 |
return DAG.getZExtOrTrunc(ABD, DL, SrcVT); |
0 |
| 10769 |
} |
--- |
10769 |
} |
--- |
| 10770 |
|
--- |
10770 |
|
--- |
| 10771 |
return SDValue(); |
0 |
10771 |
return SDValue(); |
0 |
| 10772 |
} |
0 |
10772 |
} |
0 |
| 10773 |
|
--- |
10773 |
|
--- |
| 10774 |
SDValue DAGCombiner::visitABS(SDNode *N) { |
0 |
10774 |
SDValue DAGCombiner::visitABS(SDNode *N) { |
0 |
| 10775 |
SDValue N0 = N->getOperand(0); |
0 |
10775 |
SDValue N0 = N->getOperand(0); |
0 |
| 10776 |
EVT VT = N->getValueType(0); |
0 |
10776 |
EVT VT = N->getValueType(0); |
0 |
| 10777 |
|
--- |
10777 |
|
--- |
| 10778 |
// fold (abs c1) -> c2 |
--- |
10778 |
// fold (abs c1) -> c2 |
--- |
| 10779 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::ABS, SDLoc(N), VT, {N0})) |
0 |
10779 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::ABS, SDLoc(N), VT, {N0})) |
0 |
| 10780 |
return C; |
0 |
10780 |
return C; |
0 |
| 10781 |
// fold (abs (abs x)) -> (abs x) |
--- |
10781 |
// fold (abs (abs x)) -> (abs x) |
--- |
| 10782 |
if (N0.getOpcode() == ISD::ABS) |
0 |
10782 |
if (N0.getOpcode() == ISD::ABS) |
0 |
| 10783 |
return N0; |
0 |
10783 |
return N0; |
0 |
| 10784 |
// fold (abs x) -> x iff not-negative |
--- |
10784 |
// fold (abs x) -> x iff not-negative |
--- |
| 10785 |
if (DAG.SignBitIsZero(N0)) |
0 |
10785 |
if (DAG.SignBitIsZero(N0)) |
0 |
| 10786 |
return N0; |
0 |
10786 |
return N0; |
0 |
| 10787 |
|
--- |
10787 |
|
--- |
| 10788 |
if (SDValue ABD = foldABSToABD(N)) |
0 |
10788 |
if (SDValue ABD = foldABSToABD(N)) |
0 |
| 10789 |
return ABD; |
0 |
10789 |
return ABD; |
0 |
| 10790 |
|
--- |
10790 |
|
--- |
| 10791 |
// fold (abs (sign_extend_inreg x)) -> (zero_extend (abs (truncate x))) |
--- |
10791 |
// fold (abs (sign_extend_inreg x)) -> (zero_extend (abs (truncate x))) |
--- |
| 10792 |
// iff zero_extend/truncate are free. |
--- |
10792 |
// iff zero_extend/truncate are free. |
--- |
| 10793 |
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { |
0 |
10793 |
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { |
0 |
| 10794 |
EVT ExtVT = cast(N0.getOperand(1))->getVT(); |
0 |
10794 |
EVT ExtVT = cast(N0.getOperand(1))->getVT(); |
0 |
| 10795 |
if (TLI.isTruncateFree(VT, ExtVT) && TLI.isZExtFree(ExtVT, VT) && |
0 |
10795 |
if (TLI.isTruncateFree(VT, ExtVT) && TLI.isZExtFree(ExtVT, VT) && |
0 |
| 10796 |
TLI.isTypeDesirableForOp(ISD::ABS, ExtVT) && |
0 |
10796 |
TLI.isTypeDesirableForOp(ISD::ABS, ExtVT) && |
0 |
| 10797 |
hasOperation(ISD::ABS, ExtVT)) { |
0 |
10797 |
hasOperation(ISD::ABS, ExtVT)) { |
0 |
| 10798 |
SDLoc DL(N); |
0 |
10798 |
SDLoc DL(N); |
0 |
| 10799 |
return DAG.getNode( |
0 |
10799 |
return DAG.getNode( |
0 |
| 10800 |
ISD::ZERO_EXTEND, DL, VT, |
--- |
10800 |
ISD::ZERO_EXTEND, DL, VT, |
--- |
| 10801 |
DAG.getNode(ISD::ABS, DL, ExtVT, |
0 |
10801 |
DAG.getNode(ISD::ABS, DL, ExtVT, |
0 |
| 10802 |
DAG.getNode(ISD::TRUNCATE, DL, ExtVT, N0.getOperand(0)))); |
0 |
10802 |
DAG.getNode(ISD::TRUNCATE, DL, ExtVT, N0.getOperand(0)))); |
0 |
| 10803 |
} |
0 |
10803 |
} |
0 |
| 10804 |
} |
--- |
10804 |
} |
--- |
| 10805 |
|
--- |
10805 |
|
--- |
| 10806 |
return SDValue(); |
0 |
10806 |
return SDValue(); |
0 |
| 10807 |
} |
--- |
10807 |
} |
--- |
| 10808 |
|
--- |
10808 |
|
--- |
| 10809 |
SDValue DAGCombiner::visitBSWAP(SDNode *N) { |
0 |
10809 |
SDValue DAGCombiner::visitBSWAP(SDNode *N) { |
0 |
| 10810 |
SDValue N0 = N->getOperand(0); |
0 |
10810 |
SDValue N0 = N->getOperand(0); |
0 |
| 10811 |
EVT VT = N->getValueType(0); |
0 |
10811 |
EVT VT = N->getValueType(0); |
0 |
| 10812 |
SDLoc DL(N); |
0 |
10812 |
SDLoc DL(N); |
0 |
| 10813 |
|
--- |
10813 |
|
--- |
| 10814 |
// fold (bswap c1) -> c2 |
--- |
10814 |
// fold (bswap c1) -> c2 |
--- |
| 10815 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
10815 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
| 10816 |
return DAG.getNode(ISD::BSWAP, DL, VT, N0); |
0 |
10816 |
return DAG.getNode(ISD::BSWAP, DL, VT, N0); |
0 |
| 10817 |
// fold (bswap (bswap x)) -> x |
--- |
10817 |
// fold (bswap (bswap x)) -> x |
--- |
| 10818 |
if (N0.getOpcode() == ISD::BSWAP) |
0 |
10818 |
if (N0.getOpcode() == ISD::BSWAP) |
0 |
| 10819 |
return N0.getOperand(0); |
0 |
10819 |
return N0.getOperand(0); |
0 |
| 10820 |
|
--- |
10820 |
|
--- |
| 10821 |
// Canonicalize bswap(bitreverse(x)) -> bitreverse(bswap(x)). If bitreverse |
--- |
10821 |
// Canonicalize bswap(bitreverse(x)) -> bitreverse(bswap(x)). If bitreverse |
--- |
| 10822 |
// isn't supported, it will be expanded to bswap followed by a manual reversal |
--- |
10822 |
// isn't supported, it will be expanded to bswap followed by a manual reversal |
--- |
| 10823 |
// of bits in each byte. By placing bswaps before bitreverse, we can remove |
--- |
10823 |
// of bits in each byte. By placing bswaps before bitreverse, we can remove |
--- |
| 10824 |
// the two bswaps if the bitreverse gets expanded. |
--- |
10824 |
// the two bswaps if the bitreverse gets expanded. |
--- |
| 10825 |
if (N0.getOpcode() == ISD::BITREVERSE && N0.hasOneUse()) { |
0 |
10825 |
if (N0.getOpcode() == ISD::BITREVERSE && N0.hasOneUse()) { |
0 |
| 10826 |
SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, N0.getOperand(0)); |
0 |
10826 |
SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, N0.getOperand(0)); |
0 |
| 10827 |
return DAG.getNode(ISD::BITREVERSE, DL, VT, BSwap); |
0 |
10827 |
return DAG.getNode(ISD::BITREVERSE, DL, VT, BSwap); |
0 |
| 10828 |
} |
--- |
10828 |
} |
--- |
| 10829 |
|
--- |
10829 |
|
--- |
| 10830 |
// fold (bswap shl(x,c)) -> (zext(bswap(trunc(shl(x,sub(c,bw/2)))))) |
--- |
10830 |
// fold (bswap shl(x,c)) -> (zext(bswap(trunc(shl(x,sub(c,bw/2)))))) |
--- |
| 10831 |
// iff x >= bw/2 (i.e. lower half is known zero) |
--- |
10831 |
// iff x >= bw/2 (i.e. lower half is known zero) |
--- |
| 10832 |
unsigned BW = VT.getScalarSizeInBits(); |
0 |
10832 |
unsigned BW = VT.getScalarSizeInBits(); |
0 |
| 10833 |
if (BW >= 32 && N0.getOpcode() == ISD::SHL && N0.hasOneUse()) { |
0 |
10833 |
if (BW >= 32 && N0.getOpcode() == ISD::SHL && N0.hasOneUse()) { |
0 |
| 10834 |
auto *ShAmt = dyn_cast(N0.getOperand(1)); |
0 |
10834 |
auto *ShAmt = dyn_cast(N0.getOperand(1)); |
0 |
| 10835 |
EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), BW / 2); |
0 |
10835 |
EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), BW / 2); |
0 |
| 10836 |
if (ShAmt && ShAmt->getAPIntValue().ult(BW) && |
0 |
10836 |
if (ShAmt && ShAmt->getAPIntValue().ult(BW) && |
0 |
| 10837 |
ShAmt->getZExtValue() >= (BW / 2) && |
0 |
10837 |
ShAmt->getZExtValue() >= (BW / 2) && |
0 |
| 10838 |
(ShAmt->getZExtValue() % 16) == 0 && TLI.isTypeLegal(HalfVT) && |
0 |
10838 |
(ShAmt->getZExtValue() % 16) == 0 && TLI.isTypeLegal(HalfVT) && |
0 |
| 10839 |
TLI.isTruncateFree(VT, HalfVT) && |
0 |
10839 |
TLI.isTruncateFree(VT, HalfVT) && |
0 |
| 10840 |
(!LegalOperations || hasOperation(ISD::BSWAP, HalfVT))) { |
0 |
10840 |
(!LegalOperations || hasOperation(ISD::BSWAP, HalfVT))) { |
0 |
| 10841 |
SDValue Res = N0.getOperand(0); |
0 |
10841 |
SDValue Res = N0.getOperand(0); |
0 |
| 10842 |
if (uint64_t NewShAmt = (ShAmt->getZExtValue() - (BW / 2))) |
0 |
10842 |
if (uint64_t NewShAmt = (ShAmt->getZExtValue() - (BW / 2))) |
0 |
| 10843 |
Res = DAG.getNode(ISD::SHL, DL, VT, Res, |
0 |
10843 |
Res = DAG.getNode(ISD::SHL, DL, VT, Res, |
0 |
| 10844 |
DAG.getConstant(NewShAmt, DL, getShiftAmountTy(VT))); |
0 |
10844 |
DAG.getConstant(NewShAmt, DL, getShiftAmountTy(VT))); |
0 |
| 10845 |
Res = DAG.getZExtOrTrunc(Res, DL, HalfVT); |
0 |
10845 |
Res = DAG.getZExtOrTrunc(Res, DL, HalfVT); |
0 |
| 10846 |
Res = DAG.getNode(ISD::BSWAP, DL, HalfVT, Res); |
0 |
10846 |
Res = DAG.getNode(ISD::BSWAP, DL, HalfVT, Res); |
0 |
| 10847 |
return DAG.getZExtOrTrunc(Res, DL, VT); |
0 |
10847 |
return DAG.getZExtOrTrunc(Res, DL, VT); |
0 |
| 10848 |
} |
--- |
10848 |
} |
--- |
| 10849 |
} |
--- |
10849 |
} |
--- |
| 10850 |
|
--- |
10850 |
|
--- |
| 10851 |
// Try to canonicalize bswap-of-logical-shift-by-8-bit-multiple as |
--- |
10851 |
// Try to canonicalize bswap-of-logical-shift-by-8-bit-multiple as |
--- |
| 10852 |
// inverse-shift-of-bswap: |
--- |
10852 |
// inverse-shift-of-bswap: |
--- |
| 10853 |
// bswap (X u<< C) --> (bswap X) u>> C |
--- |
10853 |
// bswap (X u<< C) --> (bswap X) u>> C |
--- |
| 10854 |
// bswap (X u>> C) --> (bswap X) u<< C |
--- |
10854 |
// bswap (X u>> C) --> (bswap X) u<< C |
--- |
| 10855 |
if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && |
0 |
10855 |
if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && |
0 |
| 10856 |
N0.hasOneUse()) { |
0 |
10856 |
N0.hasOneUse()) { |
0 |
| 10857 |
auto *ShAmt = dyn_cast(N0.getOperand(1)); |
0 |
10857 |
auto *ShAmt = dyn_cast(N0.getOperand(1)); |
0 |
| 10858 |
if (ShAmt && ShAmt->getAPIntValue().ult(BW) && |
0 |
10858 |
if (ShAmt && ShAmt->getAPIntValue().ult(BW) && |
0 |
| 10859 |
ShAmt->getZExtValue() % 8 == 0) { |
0 |
10859 |
ShAmt->getZExtValue() % 8 == 0) { |
0 |
| 10860 |
SDValue NewSwap = DAG.getNode(ISD::BSWAP, DL, VT, N0.getOperand(0)); |
0 |
10860 |
SDValue NewSwap = DAG.getNode(ISD::BSWAP, DL, VT, N0.getOperand(0)); |
0 |
| 10861 |
unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL; |
0 |
10861 |
unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL; |
0 |
| 10862 |
return DAG.getNode(InverseShift, DL, VT, NewSwap, N0.getOperand(1)); |
0 |
10862 |
return DAG.getNode(InverseShift, DL, VT, NewSwap, N0.getOperand(1)); |
0 |
| 10863 |
} |
--- |
10863 |
} |
--- |
| 10864 |
} |
--- |
10864 |
} |
--- |
| 10865 |
|
--- |
10865 |
|
--- |
| 10866 |
if (SDValue V = foldBitOrderCrossLogicOp(N, DAG)) |
0 |
10866 |
if (SDValue V = foldBitOrderCrossLogicOp(N, DAG)) |
0 |
| 10867 |
return V; |
0 |
10867 |
return V; |
0 |
| 10868 |
|
--- |
10868 |
|
--- |
| 10869 |
return SDValue(); |
0 |
10869 |
return SDValue(); |
0 |
| 10870 |
} |
0 |
10870 |
} |
0 |
| 10871 |
|
--- |
10871 |
|
--- |
| 10872 |
SDValue DAGCombiner::visitBITREVERSE(SDNode *N) { |
0 |
10872 |
SDValue DAGCombiner::visitBITREVERSE(SDNode *N) { |
0 |
| 10873 |
SDValue N0 = N->getOperand(0); |
0 |
10873 |
SDValue N0 = N->getOperand(0); |
0 |
| 10874 |
EVT VT = N->getValueType(0); |
0 |
10874 |
EVT VT = N->getValueType(0); |
0 |
| 10875 |
|
--- |
10875 |
|
--- |
| 10876 |
// fold (bitreverse c1) -> c2 |
--- |
10876 |
// fold (bitreverse c1) -> c2 |
--- |
| 10877 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
10877 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
| 10878 |
return DAG.getNode(ISD::BITREVERSE, SDLoc(N), VT, N0); |
0 |
10878 |
return DAG.getNode(ISD::BITREVERSE, SDLoc(N), VT, N0); |
0 |
| 10879 |
// fold (bitreverse (bitreverse x)) -> x |
--- |
10879 |
// fold (bitreverse (bitreverse x)) -> x |
--- |
| 10880 |
if (N0.getOpcode() == ISD::BITREVERSE) |
0 |
10880 |
if (N0.getOpcode() == ISD::BITREVERSE) |
0 |
| 10881 |
return N0.getOperand(0); |
0 |
10881 |
return N0.getOperand(0); |
0 |
| 10882 |
return SDValue(); |
0 |
10882 |
return SDValue(); |
0 |
| 10883 |
} |
--- |
10883 |
} |
--- |
| 10884 |
|
--- |
10884 |
|
--- |
| 10885 |
SDValue DAGCombiner::visitCTLZ(SDNode *N) { |
0 |
10885 |
SDValue DAGCombiner::visitCTLZ(SDNode *N) { |
0 |
| 10886 |
SDValue N0 = N->getOperand(0); |
0 |
10886 |
SDValue N0 = N->getOperand(0); |
0 |
| 10887 |
EVT VT = N->getValueType(0); |
0 |
10887 |
EVT VT = N->getValueType(0); |
0 |
| 10888 |
|
--- |
10888 |
|
--- |
| 10889 |
// fold (ctlz c1) -> c2 |
--- |
10889 |
// fold (ctlz c1) -> c2 |
--- |
| 10890 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
10890 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
| 10891 |
return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0); |
0 |
10891 |
return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0); |
0 |
| 10892 |
|
--- |
10892 |
|
--- |
| 10893 |
// If the value is known never to be zero, switch to the undef version. |
--- |
10893 |
// If the value is known never to be zero, switch to the undef version. |
--- |
| 10894 |
if (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ_ZERO_UNDEF, VT)) { |
0 |
10894 |
if (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ_ZERO_UNDEF, VT)) { |
0 |
| 10895 |
if (DAG.isKnownNeverZero(N0)) |
0 |
10895 |
if (DAG.isKnownNeverZero(N0)) |
0 |
| 10896 |
return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0); |
0 |
10896 |
return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0); |
0 |
| 10897 |
} |
--- |
10897 |
} |
--- |
| 10898 |
|
--- |
10898 |
|
--- |
| 10899 |
return SDValue(); |
0 |
10899 |
return SDValue(); |
0 |
| 10900 |
} |
--- |
10900 |
} |
--- |
| 10901 |
|
--- |
10901 |
|
--- |
| 10902 |
SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { |
0 |
10902 |
SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { |
0 |
| 10903 |
SDValue N0 = N->getOperand(0); |
0 |
10903 |
SDValue N0 = N->getOperand(0); |
0 |
| 10904 |
EVT VT = N->getValueType(0); |
0 |
10904 |
EVT VT = N->getValueType(0); |
0 |
| 10905 |
|
--- |
10905 |
|
--- |
| 10906 |
// fold (ctlz_zero_undef c1) -> c2 |
--- |
10906 |
// fold (ctlz_zero_undef c1) -> c2 |
--- |
| 10907 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
10907 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
| 10908 |
return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0); |
0 |
10908 |
return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0); |
0 |
| 10909 |
return SDValue(); |
0 |
10909 |
return SDValue(); |
0 |
| 10910 |
} |
--- |
10910 |
} |
--- |
| 10911 |
|
--- |
10911 |
|
--- |
| 10912 |
SDValue DAGCombiner::visitCTTZ(SDNode *N) { |
0 |
10912 |
SDValue DAGCombiner::visitCTTZ(SDNode *N) { |
0 |
| 10913 |
SDValue N0 = N->getOperand(0); |
0 |
10913 |
SDValue N0 = N->getOperand(0); |
0 |
| 10914 |
EVT VT = N->getValueType(0); |
0 |
10914 |
EVT VT = N->getValueType(0); |
0 |
| 10915 |
|
--- |
10915 |
|
--- |
| 10916 |
// fold (cttz c1) -> c2 |
--- |
10916 |
// fold (cttz c1) -> c2 |
--- |
| 10917 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
10917 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
| 10918 |
return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0); |
0 |
10918 |
return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0); |
0 |
| 10919 |
|
--- |
10919 |
|
--- |
| 10920 |
// If the value is known never to be zero, switch to the undef version. |
--- |
10920 |
// If the value is known never to be zero, switch to the undef version. |
--- |
| 10921 |
if (!LegalOperations || TLI.isOperationLegal(ISD::CTTZ_ZERO_UNDEF, VT)) { |
0 |
10921 |
if (!LegalOperations || TLI.isOperationLegal(ISD::CTTZ_ZERO_UNDEF, VT)) { |
0 |
| 10922 |
if (DAG.isKnownNeverZero(N0)) |
0 |
10922 |
if (DAG.isKnownNeverZero(N0)) |
0 |
| 10923 |
return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0); |
0 |
10923 |
return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0); |
0 |
| 10924 |
} |
--- |
10924 |
} |
--- |
| 10925 |
|
--- |
10925 |
|
--- |
| 10926 |
return SDValue(); |
0 |
10926 |
return SDValue(); |
0 |
| 10927 |
} |
--- |
10927 |
} |
--- |
| 10928 |
|
--- |
10928 |
|
--- |
| 10929 |
SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { |
0 |
10929 |
SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { |
0 |
| 10930 |
SDValue N0 = N->getOperand(0); |
0 |
10930 |
SDValue N0 = N->getOperand(0); |
0 |
| 10931 |
EVT VT = N->getValueType(0); |
0 |
10931 |
EVT VT = N->getValueType(0); |
0 |
| 10932 |
|
--- |
10932 |
|
--- |
| 10933 |
// fold (cttz_zero_undef c1) -> c2 |
--- |
10933 |
// fold (cttz_zero_undef c1) -> c2 |
--- |
| 10934 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
10934 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
| 10935 |
return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0); |
0 |
10935 |
return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0); |
0 |
| 10936 |
return SDValue(); |
0 |
10936 |
return SDValue(); |
0 |
| 10937 |
} |
--- |
10937 |
} |
--- |
| 10938 |
|
--- |
10938 |
|
--- |
| 10939 |
SDValue DAGCombiner::visitCTPOP(SDNode *N) { |
0 |
10939 |
SDValue DAGCombiner::visitCTPOP(SDNode *N) { |
0 |
| 10940 |
SDValue N0 = N->getOperand(0); |
0 |
10940 |
SDValue N0 = N->getOperand(0); |
0 |
| 10941 |
EVT VT = N->getValueType(0); |
0 |
10941 |
EVT VT = N->getValueType(0); |
0 |
| 10942 |
|
--- |
10942 |
|
--- |
| 10943 |
// fold (ctpop c1) -> c2 |
--- |
10943 |
// fold (ctpop c1) -> c2 |
--- |
| 10944 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
10944 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
| 10945 |
return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0); |
0 |
10945 |
return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0); |
0 |
| 10946 |
return SDValue(); |
0 |
10946 |
return SDValue(); |
0 |
| 10947 |
} |
--- |
10947 |
} |
--- |
| 10948 |
|
--- |
10948 |
|
--- |
| 10949 |
// FIXME: This should be checking for no signed zeros on individual operands, as |
--- |
10949 |
// FIXME: This should be checking for no signed zeros on individual operands, as |
--- |
| 10950 |
// well as no nans. |
--- |
10950 |
// well as no nans. |
--- |
| 10951 |
static bool isLegalToCombineMinNumMaxNum(SelectionDAG &DAG, SDValue LHS, |
0 |
10951 |
static bool isLegalToCombineMinNumMaxNum(SelectionDAG &DAG, SDValue LHS, |
0 |
| 10952 |
SDValue RHS, |
--- |
10952 |
SDValue RHS, |
--- |
| 10953 |
const TargetLowering &TLI) { |
--- |
10953 |
const TargetLowering &TLI) { |
--- |
| 10954 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
10954 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
| 10955 |
EVT VT = LHS.getValueType(); |
0 |
10955 |
EVT VT = LHS.getValueType(); |
0 |
| 10956 |
|
--- |
10956 |
|
--- |
| 10957 |
return Options.NoSignedZerosFPMath && VT.isFloatingPoint() && |
0 |
10957 |
return Options.NoSignedZerosFPMath && VT.isFloatingPoint() && |
0 |
| 10958 |
TLI.isProfitableToCombineMinNumMaxNum(VT) && |
0 |
10958 |
TLI.isProfitableToCombineMinNumMaxNum(VT) && |
0 |
| 10959 |
DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS); |
0 |
10959 |
DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS); |
0 |
| 10960 |
} |
--- |
10960 |
} |
--- |
| 10961 |
|
--- |
10961 |
|
--- |
| 10962 |
static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS, |
0 |
10962 |
static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS, |
0 |
| 10963 |
SDValue RHS, SDValue True, SDValue False, |
--- |
10963 |
SDValue RHS, SDValue True, SDValue False, |
--- |
| 10964 |
ISD::CondCode CC, |
--- |
10964 |
ISD::CondCode CC, |
--- |
| 10965 |
const TargetLowering &TLI, |
--- |
10965 |
const TargetLowering &TLI, |
--- |
| 10966 |
SelectionDAG &DAG) { |
--- |
10966 |
SelectionDAG &DAG) { |
--- |
| 10967 |
EVT TransformVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); |
0 |
10967 |
EVT TransformVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); |
0 |
| 10968 |
switch (CC) { |
0 |
10968 |
switch (CC) { |
0 |
| 10969 |
case ISD::SETOLT: |
0 |
10969 |
case ISD::SETOLT: |
0 |
| 10970 |
case ISD::SETOLE: |
--- |
10970 |
case ISD::SETOLE: |
--- |
| 10971 |
case ISD::SETLT: |
--- |
10971 |
case ISD::SETLT: |
--- |
| 10972 |
case ISD::SETLE: |
--- |
10972 |
case ISD::SETLE: |
--- |
| 10973 |
case ISD::SETULT: |
--- |
10973 |
case ISD::SETULT: |
--- |
| 10974 |
case ISD::SETULE: { |
--- |
10974 |
case ISD::SETULE: { |
--- |
| 10975 |
// Since it's known never nan to get here already, either fminnum or |
--- |
10975 |
// Since it's known never nan to get here already, either fminnum or |
--- |
| 10976 |
// fminnum_ieee are OK. Try the ieee version first, since it's fminnum is |
--- |
10976 |
// fminnum_ieee are OK. Try the ieee version first, since it's fminnum is |
--- |
| 10977 |
// expanded in terms of it. |
--- |
10977 |
// expanded in terms of it. |
--- |
| 10978 |
unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE; |
0 |
10978 |
unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE; |
0 |
| 10979 |
if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT)) |
0 |
10979 |
if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT)) |
0 |
| 10980 |
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS); |
0 |
10980 |
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS); |
0 |
| 10981 |
|
--- |
10981 |
|
--- |
| 10982 |
unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM; |
0 |
10982 |
unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM; |
0 |
| 10983 |
if (TLI.isOperationLegalOrCustom(Opcode, TransformVT)) |
0 |
10983 |
if (TLI.isOperationLegalOrCustom(Opcode, TransformVT)) |
0 |
| 10984 |
return DAG.getNode(Opcode, DL, VT, LHS, RHS); |
0 |
10984 |
return DAG.getNode(Opcode, DL, VT, LHS, RHS); |
0 |
| 10985 |
return SDValue(); |
0 |
10985 |
return SDValue(); |
0 |
| 10986 |
} |
--- |
10986 |
} |
--- |
| 10987 |
case ISD::SETOGT: |
0 |
10987 |
case ISD::SETOGT: |
0 |
| 10988 |
case ISD::SETOGE: |
--- |
10988 |
case ISD::SETOGE: |
--- |
| 10989 |
case ISD::SETGT: |
--- |
10989 |
case ISD::SETGT: |
--- |
| 10990 |
case ISD::SETGE: |
--- |
10990 |
case ISD::SETGE: |
--- |
| 10991 |
case ISD::SETUGT: |
--- |
10991 |
case ISD::SETUGT: |
--- |
| 10992 |
case ISD::SETUGE: { |
--- |
10992 |
case ISD::SETUGE: { |
--- |
| 10993 |
unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE; |
0 |
10993 |
unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE; |
0 |
| 10994 |
if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT)) |
0 |
10994 |
if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT)) |
0 |
| 10995 |
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS); |
0 |
10995 |
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS); |
0 |
| 10996 |
|
--- |
10996 |
|
--- |
| 10997 |
unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM; |
0 |
10997 |
unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM; |
0 |
| 10998 |
if (TLI.isOperationLegalOrCustom(Opcode, TransformVT)) |
0 |
10998 |
if (TLI.isOperationLegalOrCustom(Opcode, TransformVT)) |
0 |
| 10999 |
return DAG.getNode(Opcode, DL, VT, LHS, RHS); |
0 |
10999 |
return DAG.getNode(Opcode, DL, VT, LHS, RHS); |
0 |
| 11000 |
return SDValue(); |
0 |
11000 |
return SDValue(); |
0 |
| 11001 |
} |
--- |
11001 |
} |
--- |
| 11002 |
default: |
0 |
11002 |
default: |
0 |
| 11003 |
return SDValue(); |
0 |
11003 |
return SDValue(); |
0 |
| 11004 |
} |
--- |
11004 |
} |
--- |
| 11005 |
} |
--- |
11005 |
} |
--- |
| 11006 |
|
--- |
11006 |
|
--- |
| 11007 |
/// Generate Min/Max node |
--- |
11007 |
/// Generate Min/Max node |
--- |
| 11008 |
SDValue DAGCombiner::combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS, |
0 |
11008 |
SDValue DAGCombiner::combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS, |
0 |
| 11009 |
SDValue RHS, SDValue True, |
--- |
11009 |
SDValue RHS, SDValue True, |
--- |
| 11010 |
SDValue False, ISD::CondCode CC) { |
--- |
11010 |
SDValue False, ISD::CondCode CC) { |
--- |
| 11011 |
if ((LHS == True && RHS == False) || (LHS == False && RHS == True)) |
0 |
11011 |
if ((LHS == True && RHS == False) || (LHS == False && RHS == True)) |
0 |
| 11012 |
return combineMinNumMaxNumImpl(DL, VT, LHS, RHS, True, False, CC, TLI, DAG); |
0 |
11012 |
return combineMinNumMaxNumImpl(DL, VT, LHS, RHS, True, False, CC, TLI, DAG); |
0 |
| 11013 |
|
--- |
11013 |
|
--- |
| 11014 |
// If we can't directly match this, try to see if we can pull an fneg out of |
--- |
11014 |
// If we can't directly match this, try to see if we can pull an fneg out of |
--- |
| 11015 |
// the select. |
--- |
11015 |
// the select. |
--- |
| 11016 |
SDValue NegTrue = TLI.getCheaperOrNeutralNegatedExpression( |
0 |
11016 |
SDValue NegTrue = TLI.getCheaperOrNeutralNegatedExpression( |
0 |
| 11017 |
True, DAG, LegalOperations, ForCodeSize); |
0 |
11017 |
True, DAG, LegalOperations, ForCodeSize); |
0 |
| 11018 |
if (!NegTrue) |
0 |
11018 |
if (!NegTrue) |
0 |
| 11019 |
return SDValue(); |
0 |
11019 |
return SDValue(); |
0 |
| 11020 |
|
--- |
11020 |
|
--- |
| 11021 |
HandleSDNode NegTrueHandle(NegTrue); |
0 |
11021 |
HandleSDNode NegTrueHandle(NegTrue); |
0 |
| 11022 |
|
--- |
11022 |
|
--- |
| 11023 |
// Try to unfold an fneg from the select if we are comparing the negated |
--- |
11023 |
// Try to unfold an fneg from the select if we are comparing the negated |
--- |
| 11024 |
// constant. |
--- |
11024 |
// constant. |
--- |
| 11025 |
// |
--- |
11025 |
// |
--- |
| 11026 |
// select (setcc x, K) (fneg x), -K -> fneg(minnum(x, K)) |
--- |
11026 |
// select (setcc x, K) (fneg x), -K -> fneg(minnum(x, K)) |
--- |
| 11027 |
// |
--- |
11027 |
// |
--- |
| 11028 |
// TODO: Handle fabs |
--- |
11028 |
// TODO: Handle fabs |
--- |
| 11029 |
if (LHS == NegTrue) { |
0 |
11029 |
if (LHS == NegTrue) { |
0 |
| 11030 |
// If we can't directly match this, try to see if we can pull an fneg out of |
--- |
11030 |
// If we can't directly match this, try to see if we can pull an fneg out of |
--- |
| 11031 |
// the select. |
--- |
11031 |
// the select. |
--- |
| 11032 |
SDValue NegRHS = TLI.getCheaperOrNeutralNegatedExpression( |
0 |
11032 |
SDValue NegRHS = TLI.getCheaperOrNeutralNegatedExpression( |
0 |
| 11033 |
RHS, DAG, LegalOperations, ForCodeSize); |
0 |
11033 |
RHS, DAG, LegalOperations, ForCodeSize); |
0 |
| 11034 |
if (NegRHS) { |
0 |
11034 |
if (NegRHS) { |
0 |
| 11035 |
HandleSDNode NegRHSHandle(NegRHS); |
0 |
11035 |
HandleSDNode NegRHSHandle(NegRHS); |
0 |
| 11036 |
if (NegRHS == False) { |
0 |
11036 |
if (NegRHS == False) { |
0 |
| 11037 |
SDValue Combined = combineMinNumMaxNumImpl(DL, VT, LHS, RHS, NegTrue, |
0 |
11037 |
SDValue Combined = combineMinNumMaxNumImpl(DL, VT, LHS, RHS, NegTrue, |
0 |
| 11038 |
False, CC, TLI, DAG); |
--- |
11038 |
False, CC, TLI, DAG); |
--- |
| 11039 |
if (Combined) |
0 |
11039 |
if (Combined) |
0 |
| 11040 |
return DAG.getNode(ISD::FNEG, DL, VT, Combined); |
0 |
11040 |
return DAG.getNode(ISD::FNEG, DL, VT, Combined); |
0 |
| 11041 |
} |
--- |
11041 |
} |
--- |
| 11042 |
} |
0 |
11042 |
} |
0 |
| 11043 |
} |
--- |
11043 |
} |
--- |
| 11044 |
|
--- |
11044 |
|
--- |
| 11045 |
return SDValue(); |
0 |
11045 |
return SDValue(); |
0 |
| 11046 |
} |
0 |
11046 |
} |
0 |
| 11047 |
|
--- |
11047 |
|
--- |
| 11048 |
/// If a (v)select has a condition value that is a sign-bit test, try to smear |
--- |
11048 |
/// If a (v)select has a condition value that is a sign-bit test, try to smear |
--- |
| 11049 |
/// the condition operand sign-bit across the value width and use it as a mask. |
--- |
11049 |
/// the condition operand sign-bit across the value width and use it as a mask. |
--- |
| 11050 |
static SDValue foldSelectOfConstantsUsingSra(SDNode *N, SelectionDAG &DAG) { |
0 |
11050 |
static SDValue foldSelectOfConstantsUsingSra(SDNode *N, SelectionDAG &DAG) { |
0 |
| 11051 |
SDValue Cond = N->getOperand(0); |
0 |
11051 |
SDValue Cond = N->getOperand(0); |
0 |
| 11052 |
SDValue C1 = N->getOperand(1); |
0 |
11052 |
SDValue C1 = N->getOperand(1); |
0 |
| 11053 |
SDValue C2 = N->getOperand(2); |
0 |
11053 |
SDValue C2 = N->getOperand(2); |
0 |
| 11054 |
if (!isConstantOrConstantVector(C1) || !isConstantOrConstantVector(C2)) |
0 |
11054 |
if (!isConstantOrConstantVector(C1) || !isConstantOrConstantVector(C2)) |
0 |
| 11055 |
return SDValue(); |
0 |
11055 |
return SDValue(); |
0 |
| 11056 |
|
--- |
11056 |
|
--- |
| 11057 |
EVT VT = N->getValueType(0); |
0 |
11057 |
EVT VT = N->getValueType(0); |
0 |
| 11058 |
if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() || |
0 |
11058 |
if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() || |
0 |
| 11059 |
VT != Cond.getOperand(0).getValueType()) |
0 |
11059 |
VT != Cond.getOperand(0).getValueType()) |
0 |
| 11060 |
return SDValue(); |
0 |
11060 |
return SDValue(); |
0 |
| 11061 |
|
--- |
11061 |
|
--- |
| 11062 |
// The inverted-condition + commuted-select variants of these patterns are |
--- |
11062 |
// The inverted-condition + commuted-select variants of these patterns are |
--- |
| 11063 |
// canonicalized to these forms in IR. |
--- |
11063 |
// canonicalized to these forms in IR. |
--- |
| 11064 |
SDValue X = Cond.getOperand(0); |
0 |
11064 |
SDValue X = Cond.getOperand(0); |
0 |
| 11065 |
SDValue CondC = Cond.getOperand(1); |
0 |
11065 |
SDValue CondC = Cond.getOperand(1); |
0 |
| 11066 |
ISD::CondCode CC = cast(Cond.getOperand(2))->get(); |
0 |
11066 |
ISD::CondCode CC = cast(Cond.getOperand(2))->get(); |
0 |
| 11067 |
if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(CondC) && |
0 |
11067 |
if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(CondC) && |
0 |
| 11068 |
isAllOnesOrAllOnesSplat(C2)) { |
0 |
11068 |
isAllOnesOrAllOnesSplat(C2)) { |
0 |
| 11069 |
// i32 X > -1 ? C1 : -1 --> (X >>s 31) | C1 |
--- |
11069 |
// i32 X > -1 ? C1 : -1 --> (X >>s 31) | C1 |
--- |
| 11070 |
SDLoc DL(N); |
0 |
11070 |
SDLoc DL(N); |
0 |
| 11071 |
SDValue ShAmtC = DAG.getConstant(X.getScalarValueSizeInBits() - 1, DL, VT); |
0 |
11071 |
SDValue ShAmtC = DAG.getConstant(X.getScalarValueSizeInBits() - 1, DL, VT); |
0 |
| 11072 |
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC); |
0 |
11072 |
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC); |
0 |
| 11073 |
return DAG.getNode(ISD::OR, DL, VT, Sra, C1); |
0 |
11073 |
return DAG.getNode(ISD::OR, DL, VT, Sra, C1); |
0 |
| 11074 |
} |
0 |
11074 |
} |
0 |
| 11075 |
if (CC == ISD::SETLT && isNullOrNullSplat(CondC) && isNullOrNullSplat(C2)) { |
0 |
11075 |
if (CC == ISD::SETLT && isNullOrNullSplat(CondC) && isNullOrNullSplat(C2)) { |
0 |
| 11076 |
// i8 X < 0 ? C1 : 0 --> (X >>s 7) & C1 |
--- |
11076 |
// i8 X < 0 ? C1 : 0 --> (X >>s 7) & C1 |
--- |
| 11077 |
SDLoc DL(N); |
0 |
11077 |
SDLoc DL(N); |
0 |
| 11078 |
SDValue ShAmtC = DAG.getConstant(X.getScalarValueSizeInBits() - 1, DL, VT); |
0 |
11078 |
SDValue ShAmtC = DAG.getConstant(X.getScalarValueSizeInBits() - 1, DL, VT); |
0 |
| 11079 |
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC); |
0 |
11079 |
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC); |
0 |
| 11080 |
return DAG.getNode(ISD::AND, DL, VT, Sra, C1); |
0 |
11080 |
return DAG.getNode(ISD::AND, DL, VT, Sra, C1); |
0 |
| 11081 |
} |
0 |
11081 |
} |
0 |
| 11082 |
return SDValue(); |
0 |
11082 |
return SDValue(); |
0 |
| 11083 |
} |
--- |
11083 |
} |
--- |
| 11084 |
|
--- |
11084 |
|
--- |
| 11085 |
static bool shouldConvertSelectOfConstantsToMath(const SDValue &Cond, EVT VT, |
0 |
11085 |
static bool shouldConvertSelectOfConstantsToMath(const SDValue &Cond, EVT VT, |
0 |
| 11086 |
const TargetLowering &TLI) { |
--- |
11086 |
const TargetLowering &TLI) { |
--- |
| 11087 |
if (!TLI.convertSelectOfConstantsToMath(VT)) |
0 |
11087 |
if (!TLI.convertSelectOfConstantsToMath(VT)) |
0 |
| 11088 |
return false; |
0 |
11088 |
return false; |
0 |
| 11089 |
|
--- |
11089 |
|
--- |
| 11090 |
if (Cond.getOpcode() != ISD::SETCC || !Cond->hasOneUse()) |
0 |
11090 |
if (Cond.getOpcode() != ISD::SETCC || !Cond->hasOneUse()) |
0 |
| 11091 |
return true; |
0 |
11091 |
return true; |
0 |
| 11092 |
if (!TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) |
0 |
11092 |
if (!TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) |
0 |
| 11093 |
return true; |
0 |
11093 |
return true; |
0 |
| 11094 |
|
--- |
11094 |
|
--- |
| 11095 |
ISD::CondCode CC = cast(Cond.getOperand(2))->get(); |
0 |
11095 |
ISD::CondCode CC = cast(Cond.getOperand(2))->get(); |
0 |
| 11096 |
if (CC == ISD::SETLT && isNullOrNullSplat(Cond.getOperand(1))) |
0 |
11096 |
if (CC == ISD::SETLT && isNullOrNullSplat(Cond.getOperand(1))) |
0 |
| 11097 |
return true; |
0 |
11097 |
return true; |
0 |
| 11098 |
if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(Cond.getOperand(1))) |
0 |
11098 |
if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(Cond.getOperand(1))) |
0 |
| 11099 |
return true; |
0 |
11099 |
return true; |
0 |
| 11100 |
|
--- |
11100 |
|
--- |
| 11101 |
return false; |
0 |
11101 |
return false; |
0 |
| 11102 |
} |
--- |
11102 |
} |
--- |
| 11103 |
|
--- |
11103 |
|
--- |
| 11104 |
SDValue DAGCombiner::foldSelectOfConstants(SDNode *N) { |
0 |
11104 |
SDValue DAGCombiner::foldSelectOfConstants(SDNode *N) { |
0 |
| 11105 |
SDValue Cond = N->getOperand(0); |
0 |
11105 |
SDValue Cond = N->getOperand(0); |
0 |
| 11106 |
SDValue N1 = N->getOperand(1); |
0 |
11106 |
SDValue N1 = N->getOperand(1); |
0 |
| 11107 |
SDValue N2 = N->getOperand(2); |
0 |
11107 |
SDValue N2 = N->getOperand(2); |
0 |
| 11108 |
EVT VT = N->getValueType(0); |
0 |
11108 |
EVT VT = N->getValueType(0); |
0 |
| 11109 |
EVT CondVT = Cond.getValueType(); |
0 |
11109 |
EVT CondVT = Cond.getValueType(); |
0 |
| 11110 |
SDLoc DL(N); |
0 |
11110 |
SDLoc DL(N); |
0 |
| 11111 |
|
--- |
11111 |
|
--- |
| 11112 |
if (!VT.isInteger()) |
0 |
11112 |
if (!VT.isInteger()) |
0 |
| 11113 |
return SDValue(); |
0 |
11113 |
return SDValue(); |
0 |
| 11114 |
|
--- |
11114 |
|
--- |
| 11115 |
auto *C1 = dyn_cast(N1); |
0 |
11115 |
auto *C1 = dyn_cast(N1); |
0 |
| 11116 |
auto *C2 = dyn_cast(N2); |
0 |
11116 |
auto *C2 = dyn_cast(N2); |
0 |
| 11117 |
if (!C1 || !C2) |
0 |
11117 |
if (!C1 || !C2) |
0 |
| 11118 |
return SDValue(); |
0 |
11118 |
return SDValue(); |
0 |
| 11119 |
|
--- |
11119 |
|
--- |
| 11120 |
if (CondVT != MVT::i1 || LegalOperations) { |
0 |
11120 |
if (CondVT != MVT::i1 || LegalOperations) { |
0 |
| 11121 |
// fold (select Cond, 0, 1) -> (xor Cond, 1) |
--- |
11121 |
// fold (select Cond, 0, 1) -> (xor Cond, 1) |
--- |
| 11122 |
// We can't do this reliably if integer based booleans have different contents |
--- |
11122 |
// We can't do this reliably if integer based booleans have different contents |
--- |
| 11123 |
// to floating point based booleans. This is because we can't tell whether we |
--- |
11123 |
// to floating point based booleans. This is because we can't tell whether we |
--- |
| 11124 |
// have an integer-based boolean or a floating-point-based boolean unless we |
--- |
11124 |
// have an integer-based boolean or a floating-point-based boolean unless we |
--- |
| 11125 |
// can find the SETCC that produced it and inspect its operands. This is |
--- |
11125 |
// can find the SETCC that produced it and inspect its operands. This is |
--- |
| 11126 |
// fairly easy if C is the SETCC node, but it can potentially be |
--- |
11126 |
// fairly easy if C is the SETCC node, but it can potentially be |
--- |
| 11127 |
// undiscoverable (or not reasonably discoverable). For example, it could be |
--- |
11127 |
// undiscoverable (or not reasonably discoverable). For example, it could be |
--- |
| 11128 |
// in another basic block or it could require searching a complicated |
--- |
11128 |
// in another basic block or it could require searching a complicated |
--- |
| 11129 |
// expression. |
--- |
11129 |
// expression. |
--- |
| 11130 |
if (CondVT.isInteger() && |
0 |
11130 |
if (CondVT.isInteger() && |
0 |
| 11131 |
TLI.getBooleanContents(/*isVec*/false, /*isFloat*/true) == |
0 |
11131 |
TLI.getBooleanContents(/*isVec*/false, /*isFloat*/true) == |
0 |
| 11132 |
TargetLowering::ZeroOrOneBooleanContent && |
0 |
11132 |
TargetLowering::ZeroOrOneBooleanContent && |
0 |
| 11133 |
TLI.getBooleanContents(/*isVec*/false, /*isFloat*/false) == |
0 |
11133 |
TLI.getBooleanContents(/*isVec*/false, /*isFloat*/false) == |
0 |
| 11134 |
TargetLowering::ZeroOrOneBooleanContent && |
0 |
11134 |
TargetLowering::ZeroOrOneBooleanContent && |
0 |
| 11135 |
C1->isZero() && C2->isOne()) { |
0 |
11135 |
C1->isZero() && C2->isOne()) { |
0 |
| 11136 |
SDValue NotCond = |
--- |
11136 |
SDValue NotCond = |
--- |
| 11137 |
DAG.getNode(ISD::XOR, DL, CondVT, Cond, DAG.getConstant(1, DL, CondVT)); |
0 |
11137 |
DAG.getNode(ISD::XOR, DL, CondVT, Cond, DAG.getConstant(1, DL, CondVT)); |
0 |
| 11138 |
if (VT.bitsEq(CondVT)) |
0 |
11138 |
if (VT.bitsEq(CondVT)) |
0 |
| 11139 |
return NotCond; |
0 |
11139 |
return NotCond; |
0 |
| 11140 |
return DAG.getZExtOrTrunc(NotCond, DL, VT); |
0 |
11140 |
return DAG.getZExtOrTrunc(NotCond, DL, VT); |
0 |
| 11141 |
} |
--- |
11141 |
} |
--- |
| 11142 |
|
--- |
11142 |
|
--- |
| 11143 |
return SDValue(); |
0 |
11143 |
return SDValue(); |
0 |
| 11144 |
} |
--- |
11144 |
} |
--- |
| 11145 |
|
--- |
11145 |
|
--- |
| 11146 |
// Only do this before legalization to avoid conflicting with target-specific |
--- |
11146 |
// Only do this before legalization to avoid conflicting with target-specific |
--- |
| 11147 |
// transforms in the other direction (create a select from a zext/sext). There |
--- |
11147 |
// transforms in the other direction (create a select from a zext/sext). There |
--- |
| 11148 |
// is also a target-independent combine here in DAGCombiner in the other |
--- |
11148 |
// is also a target-independent combine here in DAGCombiner in the other |
--- |
| 11149 |
// direction for (select Cond, -1, 0) when the condition is not i1. |
--- |
11149 |
// direction for (select Cond, -1, 0) when the condition is not i1. |
--- |
| 11150 |
assert(CondVT == MVT::i1 && !LegalOperations); |
0 |
11150 |
assert(CondVT == MVT::i1 && !LegalOperations); |
0 |
| 11151 |
|
--- |
11151 |
|
--- |
| 11152 |
// select Cond, 1, 0 --> zext (Cond) |
--- |
11152 |
// select Cond, 1, 0 --> zext (Cond) |
--- |
| 11153 |
if (C1->isOne() && C2->isZero()) |
0 |
11153 |
if (C1->isOne() && C2->isZero()) |
0 |
| 11154 |
return DAG.getZExtOrTrunc(Cond, DL, VT); |
0 |
11154 |
return DAG.getZExtOrTrunc(Cond, DL, VT); |
0 |
| 11155 |
|
--- |
11155 |
|
--- |
| 11156 |
// select Cond, -1, 0 --> sext (Cond) |
--- |
11156 |
// select Cond, -1, 0 --> sext (Cond) |
--- |
| 11157 |
if (C1->isAllOnes() && C2->isZero()) |
0 |
11157 |
if (C1->isAllOnes() && C2->isZero()) |
0 |
| 11158 |
return DAG.getSExtOrTrunc(Cond, DL, VT); |
0 |
11158 |
return DAG.getSExtOrTrunc(Cond, DL, VT); |
0 |
| 11159 |
|
--- |
11159 |
|
--- |
| 11160 |
// select Cond, 0, 1 --> zext (!Cond) |
--- |
11160 |
// select Cond, 0, 1 --> zext (!Cond) |
--- |
| 11161 |
if (C1->isZero() && C2->isOne()) { |
0 |
11161 |
if (C1->isZero() && C2->isOne()) { |
0 |
| 11162 |
SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1); |
0 |
11162 |
SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1); |
0 |
| 11163 |
NotCond = DAG.getZExtOrTrunc(NotCond, DL, VT); |
0 |
11163 |
NotCond = DAG.getZExtOrTrunc(NotCond, DL, VT); |
0 |
| 11164 |
return NotCond; |
0 |
11164 |
return NotCond; |
0 |
| 11165 |
} |
--- |
11165 |
} |
--- |
| 11166 |
|
--- |
11166 |
|
--- |
| 11167 |
// select Cond, 0, -1 --> sext (!Cond) |
--- |
11167 |
// select Cond, 0, -1 --> sext (!Cond) |
--- |
| 11168 |
if (C1->isZero() && C2->isAllOnes()) { |
0 |
11168 |
if (C1->isZero() && C2->isAllOnes()) { |
0 |
| 11169 |
SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1); |
0 |
11169 |
SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1); |
0 |
| 11170 |
NotCond = DAG.getSExtOrTrunc(NotCond, DL, VT); |
0 |
11170 |
NotCond = DAG.getSExtOrTrunc(NotCond, DL, VT); |
0 |
| 11171 |
return NotCond; |
0 |
11171 |
return NotCond; |
0 |
| 11172 |
} |
--- |
11172 |
} |
--- |
| 11173 |
|
--- |
11173 |
|
--- |
| 11174 |
// Use a target hook because some targets may prefer to transform in the |
--- |
11174 |
// Use a target hook because some targets may prefer to transform in the |
--- |
| 11175 |
// other direction. |
--- |
11175 |
// other direction. |
--- |
| 11176 |
if (!shouldConvertSelectOfConstantsToMath(Cond, VT, TLI)) |
0 |
11176 |
if (!shouldConvertSelectOfConstantsToMath(Cond, VT, TLI)) |
0 |
| 11177 |
return SDValue(); |
0 |
11177 |
return SDValue(); |
0 |
| 11178 |
|
--- |
11178 |
|
--- |
| 11179 |
// For any constants that differ by 1, we can transform the select into |
--- |
11179 |
// For any constants that differ by 1, we can transform the select into |
--- |
| 11180 |
// an extend and add. |
--- |
11180 |
// an extend and add. |
--- |
| 11181 |
const APInt &C1Val = C1->getAPIntValue(); |
0 |
11181 |
const APInt &C1Val = C1->getAPIntValue(); |
0 |
| 11182 |
const APInt &C2Val = C2->getAPIntValue(); |
0 |
11182 |
const APInt &C2Val = C2->getAPIntValue(); |
0 |
| 11183 |
|
--- |
11183 |
|
--- |
| 11184 |
// select Cond, C1, C1-1 --> add (zext Cond), C1-1 |
--- |
11184 |
// select Cond, C1, C1-1 --> add (zext Cond), C1-1 |
--- |
| 11185 |
if (C1Val - 1 == C2Val) { |
0 |
11185 |
if (C1Val - 1 == C2Val) { |
0 |
| 11186 |
Cond = DAG.getZExtOrTrunc(Cond, DL, VT); |
0 |
11186 |
Cond = DAG.getZExtOrTrunc(Cond, DL, VT); |
0 |
| 11187 |
return DAG.getNode(ISD::ADD, DL, VT, Cond, N2); |
0 |
11187 |
return DAG.getNode(ISD::ADD, DL, VT, Cond, N2); |
0 |
| 11188 |
} |
--- |
11188 |
} |
--- |
| 11189 |
|
--- |
11189 |
|
--- |
| 11190 |
// select Cond, C1, C1+1 --> add (sext Cond), C1+1 |
--- |
11190 |
// select Cond, C1, C1+1 --> add (sext Cond), C1+1 |
--- |
| 11191 |
if (C1Val + 1 == C2Val) { |
0 |
11191 |
if (C1Val + 1 == C2Val) { |
0 |
| 11192 |
Cond = DAG.getSExtOrTrunc(Cond, DL, VT); |
0 |
11192 |
Cond = DAG.getSExtOrTrunc(Cond, DL, VT); |
0 |
| 11193 |
return DAG.getNode(ISD::ADD, DL, VT, Cond, N2); |
0 |
11193 |
return DAG.getNode(ISD::ADD, DL, VT, Cond, N2); |
0 |
| 11194 |
} |
--- |
11194 |
} |
--- |
| 11195 |
|
--- |
11195 |
|
--- |
| 11196 |
// select Cond, Pow2, 0 --> (zext Cond) << log2(Pow2) |
--- |
11196 |
// select Cond, Pow2, 0 --> (zext Cond) << log2(Pow2) |
--- |
| 11197 |
if (C1Val.isPowerOf2() && C2Val.isZero()) { |
0 |
11197 |
if (C1Val.isPowerOf2() && C2Val.isZero()) { |
0 |
| 11198 |
Cond = DAG.getZExtOrTrunc(Cond, DL, VT); |
0 |
11198 |
Cond = DAG.getZExtOrTrunc(Cond, DL, VT); |
0 |
| 11199 |
SDValue ShAmtC = |
--- |
11199 |
SDValue ShAmtC = |
--- |
| 11200 |
DAG.getShiftAmountConstant(C1Val.exactLogBase2(), VT, DL); |
0 |
11200 |
DAG.getShiftAmountConstant(C1Val.exactLogBase2(), VT, DL); |
0 |
| 11201 |
return DAG.getNode(ISD::SHL, DL, VT, Cond, ShAmtC); |
0 |
11201 |
return DAG.getNode(ISD::SHL, DL, VT, Cond, ShAmtC); |
0 |
| 11202 |
} |
--- |
11202 |
} |
--- |
| 11203 |
|
--- |
11203 |
|
--- |
| 11204 |
// select Cond, -1, C --> or (sext Cond), C |
--- |
11204 |
// select Cond, -1, C --> or (sext Cond), C |
--- |
| 11205 |
if (C1->isAllOnes()) { |
0 |
11205 |
if (C1->isAllOnes()) { |
0 |
| 11206 |
Cond = DAG.getSExtOrTrunc(Cond, DL, VT); |
0 |
11206 |
Cond = DAG.getSExtOrTrunc(Cond, DL, VT); |
0 |
| 11207 |
return DAG.getNode(ISD::OR, DL, VT, Cond, N2); |
0 |
11207 |
return DAG.getNode(ISD::OR, DL, VT, Cond, N2); |
0 |
| 11208 |
} |
--- |
11208 |
} |
--- |
| 11209 |
|
--- |
11209 |
|
--- |
| 11210 |
// select Cond, C, -1 --> or (sext (not Cond)), C |
--- |
11210 |
// select Cond, C, -1 --> or (sext (not Cond)), C |
--- |
| 11211 |
if (C2->isAllOnes()) { |
0 |
11211 |
if (C2->isAllOnes()) { |
0 |
| 11212 |
SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1); |
0 |
11212 |
SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1); |
0 |
| 11213 |
NotCond = DAG.getSExtOrTrunc(NotCond, DL, VT); |
0 |
11213 |
NotCond = DAG.getSExtOrTrunc(NotCond, DL, VT); |
0 |
| 11214 |
return DAG.getNode(ISD::OR, DL, VT, NotCond, N1); |
0 |
11214 |
return DAG.getNode(ISD::OR, DL, VT, NotCond, N1); |
0 |
| 11215 |
} |
--- |
11215 |
} |
--- |
| 11216 |
|
--- |
11216 |
|
--- |
| 11217 |
if (SDValue V = foldSelectOfConstantsUsingSra(N, DAG)) |
0 |
11217 |
if (SDValue V = foldSelectOfConstantsUsingSra(N, DAG)) |
0 |
| 11218 |
return V; |
0 |
11218 |
return V; |
0 |
| 11219 |
|
--- |
11219 |
|
--- |
| 11220 |
return SDValue(); |
0 |
11220 |
return SDValue(); |
0 |
| 11221 |
} |
0 |
11221 |
} |
0 |
| 11222 |
|
--- |
11222 |
|
--- |
| 11223 |
static SDValue foldBoolSelectToLogic(SDNode *N, SelectionDAG &DAG) { |
0 |
11223 |
static SDValue foldBoolSelectToLogic(SDNode *N, SelectionDAG &DAG) { |
0 |
| 11224 |
assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT) && |
0 |
11224 |
assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT) && |
0 |
| 11225 |
"Expected a (v)select"); |
--- |
11225 |
"Expected a (v)select"); |
--- |
| 11226 |
SDValue Cond = N->getOperand(0); |
0 |
11226 |
SDValue Cond = N->getOperand(0); |
0 |
| 11227 |
SDValue T = N->getOperand(1), F = N->getOperand(2); |
0 |
11227 |
SDValue T = N->getOperand(1), F = N->getOperand(2); |
0 |
| 11228 |
EVT VT = N->getValueType(0); |
0 |
11228 |
EVT VT = N->getValueType(0); |
0 |
| 11229 |
if (VT != Cond.getValueType() || VT.getScalarSizeInBits() != 1) |
0 |
11229 |
if (VT != Cond.getValueType() || VT.getScalarSizeInBits() != 1) |
0 |
| 11230 |
return SDValue(); |
0 |
11230 |
return SDValue(); |
0 |
| 11231 |
|
--- |
11231 |
|
--- |
| 11232 |
// select Cond, Cond, F --> or Cond, F |
--- |
11232 |
// select Cond, Cond, F --> or Cond, F |
--- |
| 11233 |
// select Cond, 1, F --> or Cond, F |
--- |
11233 |
// select Cond, 1, F --> or Cond, F |
--- |
| 11234 |
if (Cond == T || isOneOrOneSplat(T, /* AllowUndefs */ true)) |
0 |
11234 |
if (Cond == T || isOneOrOneSplat(T, /* AllowUndefs */ true)) |
0 |
| 11235 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, Cond, F); |
0 |
11235 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, Cond, F); |
0 |
| 11236 |
|
--- |
11236 |
|
--- |
| 11237 |
// select Cond, T, Cond --> and Cond, T |
--- |
11237 |
// select Cond, T, Cond --> and Cond, T |
--- |
| 11238 |
// select Cond, T, 0 --> and Cond, T |
--- |
11238 |
// select Cond, T, 0 --> and Cond, T |
--- |
| 11239 |
if (Cond == F || isNullOrNullSplat(F, /* AllowUndefs */ true)) |
0 |
11239 |
if (Cond == F || isNullOrNullSplat(F, /* AllowUndefs */ true)) |
0 |
| 11240 |
return DAG.getNode(ISD::AND, SDLoc(N), VT, Cond, T); |
0 |
11240 |
return DAG.getNode(ISD::AND, SDLoc(N), VT, Cond, T); |
0 |
| 11241 |
|
--- |
11241 |
|
--- |
| 11242 |
// select Cond, T, 1 --> or (not Cond), T |
--- |
11242 |
// select Cond, T, 1 --> or (not Cond), T |
--- |
| 11243 |
if (isOneOrOneSplat(F, /* AllowUndefs */ true)) { |
0 |
11243 |
if (isOneOrOneSplat(F, /* AllowUndefs */ true)) { |
0 |
| 11244 |
SDValue NotCond = DAG.getNOT(SDLoc(N), Cond, VT); |
0 |
11244 |
SDValue NotCond = DAG.getNOT(SDLoc(N), Cond, VT); |
0 |
| 11245 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, NotCond, T); |
0 |
11245 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, NotCond, T); |
0 |
| 11246 |
} |
--- |
11246 |
} |
--- |
| 11247 |
|
--- |
11247 |
|
--- |
| 11248 |
// select Cond, 0, F --> and (not Cond), F |
--- |
11248 |
// select Cond, 0, F --> and (not Cond), F |
--- |
| 11249 |
if (isNullOrNullSplat(T, /* AllowUndefs */ true)) { |
0 |
11249 |
if (isNullOrNullSplat(T, /* AllowUndefs */ true)) { |
0 |
| 11250 |
SDValue NotCond = DAG.getNOT(SDLoc(N), Cond, VT); |
0 |
11250 |
SDValue NotCond = DAG.getNOT(SDLoc(N), Cond, VT); |
0 |
| 11251 |
return DAG.getNode(ISD::AND, SDLoc(N), VT, NotCond, F); |
0 |
11251 |
return DAG.getNode(ISD::AND, SDLoc(N), VT, NotCond, F); |
0 |
| 11252 |
} |
--- |
11252 |
} |
--- |
| 11253 |
|
--- |
11253 |
|
--- |
| 11254 |
return SDValue(); |
0 |
11254 |
return SDValue(); |
0 |
| 11255 |
} |
--- |
11255 |
} |
--- |
| 11256 |
|
--- |
11256 |
|
--- |
| 11257 |
static SDValue foldVSelectToSignBitSplatMask(SDNode *N, SelectionDAG &DAG) { |
0 |
11257 |
static SDValue foldVSelectToSignBitSplatMask(SDNode *N, SelectionDAG &DAG) { |
0 |
| 11258 |
SDValue N0 = N->getOperand(0); |
0 |
11258 |
SDValue N0 = N->getOperand(0); |
0 |
| 11259 |
SDValue N1 = N->getOperand(1); |
0 |
11259 |
SDValue N1 = N->getOperand(1); |
0 |
| 11260 |
SDValue N2 = N->getOperand(2); |
0 |
11260 |
SDValue N2 = N->getOperand(2); |
0 |
| 11261 |
EVT VT = N->getValueType(0); |
0 |
11261 |
EVT VT = N->getValueType(0); |
0 |
| 11262 |
if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse()) |
0 |
11262 |
if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse()) |
0 |
| 11263 |
return SDValue(); |
0 |
11263 |
return SDValue(); |
0 |
| 11264 |
|
--- |
11264 |
|
--- |
| 11265 |
SDValue Cond0 = N0.getOperand(0); |
0 |
11265 |
SDValue Cond0 = N0.getOperand(0); |
0 |
| 11266 |
SDValue Cond1 = N0.getOperand(1); |
0 |
11266 |
SDValue Cond1 = N0.getOperand(1); |
0 |
| 11267 |
ISD::CondCode CC = cast(N0.getOperand(2))->get(); |
0 |
11267 |
ISD::CondCode CC = cast(N0.getOperand(2))->get(); |
0 |
| 11268 |
if (VT != Cond0.getValueType()) |
0 |
11268 |
if (VT != Cond0.getValueType()) |
0 |
| 11269 |
return SDValue(); |
0 |
11269 |
return SDValue(); |
0 |
| 11270 |
|
--- |
11270 |
|
--- |
| 11271 |
// Match a signbit check of Cond0 as "Cond0 s<0". Swap select operands if the |
--- |
11271 |
// Match a signbit check of Cond0 as "Cond0 s<0". Swap select operands if the |
--- |
| 11272 |
// compare is inverted from that pattern ("Cond0 s> -1"). |
--- |
11272 |
// compare is inverted from that pattern ("Cond0 s> -1"). |
--- |
| 11273 |
if (CC == ISD::SETLT && isNullOrNullSplat(Cond1)) |
0 |
11273 |
if (CC == ISD::SETLT && isNullOrNullSplat(Cond1)) |
0 |
| 11274 |
; // This is the pattern we are looking for. |
--- |
11274 |
; // This is the pattern we are looking for. |
--- |
| 11275 |
else if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(Cond1)) |
0 |
11275 |
else if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(Cond1)) |
0 |
| 11276 |
std::swap(N1, N2); |
0 |
11276 |
std::swap(N1, N2); |
0 |
| 11277 |
else |
--- |
11277 |
else |
--- |
| 11278 |
return SDValue(); |
0 |
11278 |
return SDValue(); |
0 |
| 11279 |
|
--- |
11279 |
|
--- |
| 11280 |
// (Cond0 s< 0) ? N1 : 0 --> (Cond0 s>> BW-1) & N1 |
--- |
11280 |
// (Cond0 s< 0) ? N1 : 0 --> (Cond0 s>> BW-1) & N1 |
--- |
| 11281 |
if (isNullOrNullSplat(N2)) { |
0 |
11281 |
if (isNullOrNullSplat(N2)) { |
0 |
| 11282 |
SDLoc DL(N); |
0 |
11282 |
SDLoc DL(N); |
0 |
| 11283 |
SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); |
0 |
11283 |
SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); |
0 |
| 11284 |
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); |
0 |
11284 |
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); |
0 |
| 11285 |
return DAG.getNode(ISD::AND, DL, VT, Sra, N1); |
0 |
11285 |
return DAG.getNode(ISD::AND, DL, VT, Sra, N1); |
0 |
| 11286 |
} |
0 |
11286 |
} |
0 |
| 11287 |
|
--- |
11287 |
|
--- |
| 11288 |
// (Cond0 s< 0) ? -1 : N2 --> (Cond0 s>> BW-1) | N2 |
--- |
11288 |
// (Cond0 s< 0) ? -1 : N2 --> (Cond0 s>> BW-1) | N2 |
--- |
| 11289 |
if (isAllOnesOrAllOnesSplat(N1)) { |
0 |
11289 |
if (isAllOnesOrAllOnesSplat(N1)) { |
0 |
| 11290 |
SDLoc DL(N); |
0 |
11290 |
SDLoc DL(N); |
0 |
| 11291 |
SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); |
0 |
11291 |
SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); |
0 |
| 11292 |
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); |
0 |
11292 |
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); |
0 |
| 11293 |
return DAG.getNode(ISD::OR, DL, VT, Sra, N2); |
0 |
11293 |
return DAG.getNode(ISD::OR, DL, VT, Sra, N2); |
0 |
| 11294 |
} |
0 |
11294 |
} |
0 |
| 11295 |
|
--- |
11295 |
|
--- |
| 11296 |
// If we have to invert the sign bit mask, only do that transform if the |
--- |
11296 |
// If we have to invert the sign bit mask, only do that transform if the |
--- |
| 11297 |
// target has a bitwise 'and not' instruction (the invert is free). |
--- |
11297 |
// target has a bitwise 'and not' instruction (the invert is free). |
--- |
| 11298 |
// (Cond0 s< -0) ? 0 : N2 --> ~(Cond0 s>> BW-1) & N2 |
--- |
11298 |
// (Cond0 s< -0) ? 0 : N2 --> ~(Cond0 s>> BW-1) & N2 |
--- |
| 11299 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
11299 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 11300 |
if (isNullOrNullSplat(N1) && TLI.hasAndNot(N1)) { |
0 |
11300 |
if (isNullOrNullSplat(N1) && TLI.hasAndNot(N1)) { |
0 |
| 11301 |
SDLoc DL(N); |
0 |
11301 |
SDLoc DL(N); |
0 |
| 11302 |
SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); |
0 |
11302 |
SDValue ShiftAmt = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); |
0 |
| 11303 |
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); |
0 |
11303 |
SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); |
0 |
| 11304 |
SDValue Not = DAG.getNOT(DL, Sra, VT); |
0 |
11304 |
SDValue Not = DAG.getNOT(DL, Sra, VT); |
0 |
| 11305 |
return DAG.getNode(ISD::AND, DL, VT, Not, N2); |
0 |
11305 |
return DAG.getNode(ISD::AND, DL, VT, Not, N2); |
0 |
| 11306 |
} |
0 |
11306 |
} |
0 |
| 11307 |
|
--- |
11307 |
|
--- |
| 11308 |
// TODO: There's another pattern in this family, but it may require |
--- |
11308 |
// TODO: There's another pattern in this family, but it may require |
--- |
| 11309 |
// implementing hasOrNot() to check for profitability: |
--- |
11309 |
// implementing hasOrNot() to check for profitability: |
--- |
| 11310 |
// (Cond0 s> -1) ? -1 : N2 --> ~(Cond0 s>> BW-1) | N2 |
--- |
11310 |
// (Cond0 s> -1) ? -1 : N2 --> ~(Cond0 s>> BW-1) | N2 |
--- |
| 11311 |
|
--- |
11311 |
|
--- |
| 11312 |
return SDValue(); |
0 |
11312 |
return SDValue(); |
0 |
| 11313 |
} |
--- |
11313 |
} |
--- |
| 11314 |
|
--- |
11314 |
|
--- |
| 11315 |
SDValue DAGCombiner::visitSELECT(SDNode *N) { |
0 |
11315 |
SDValue DAGCombiner::visitSELECT(SDNode *N) { |
0 |
| 11316 |
SDValue N0 = N->getOperand(0); |
0 |
11316 |
SDValue N0 = N->getOperand(0); |
0 |
| 11317 |
SDValue N1 = N->getOperand(1); |
0 |
11317 |
SDValue N1 = N->getOperand(1); |
0 |
| 11318 |
SDValue N2 = N->getOperand(2); |
0 |
11318 |
SDValue N2 = N->getOperand(2); |
0 |
| 11319 |
EVT VT = N->getValueType(0); |
0 |
11319 |
EVT VT = N->getValueType(0); |
0 |
| 11320 |
EVT VT0 = N0.getValueType(); |
0 |
11320 |
EVT VT0 = N0.getValueType(); |
0 |
| 11321 |
SDLoc DL(N); |
0 |
11321 |
SDLoc DL(N); |
0 |
| 11322 |
SDNodeFlags Flags = N->getFlags(); |
0 |
11322 |
SDNodeFlags Flags = N->getFlags(); |
0 |
| 11323 |
|
--- |
11323 |
|
--- |
| 11324 |
if (SDValue V = DAG.simplifySelect(N0, N1, N2)) |
0 |
11324 |
if (SDValue V = DAG.simplifySelect(N0, N1, N2)) |
0 |
| 11325 |
return V; |
0 |
11325 |
return V; |
0 |
| 11326 |
|
--- |
11326 |
|
--- |
| 11327 |
if (SDValue V = foldBoolSelectToLogic(N, DAG)) |
0 |
11327 |
if (SDValue V = foldBoolSelectToLogic(N, DAG)) |
0 |
| 11328 |
return V; |
0 |
11328 |
return V; |
0 |
| 11329 |
|
--- |
11329 |
|
--- |
| 11330 |
// select (not Cond), N1, N2 -> select Cond, N2, N1 |
--- |
11330 |
// select (not Cond), N1, N2 -> select Cond, N2, N1 |
--- |
| 11331 |
if (SDValue F = extractBooleanFlip(N0, DAG, TLI, false)) { |
0 |
11331 |
if (SDValue F = extractBooleanFlip(N0, DAG, TLI, false)) { |
0 |
| 11332 |
SDValue SelectOp = DAG.getSelect(DL, VT, F, N2, N1); |
0 |
11332 |
SDValue SelectOp = DAG.getSelect(DL, VT, F, N2, N1); |
0 |
| 11333 |
SelectOp->setFlags(Flags); |
0 |
11333 |
SelectOp->setFlags(Flags); |
0 |
| 11334 |
return SelectOp; |
0 |
11334 |
return SelectOp; |
0 |
| 11335 |
} |
--- |
11335 |
} |
--- |
| 11336 |
|
--- |
11336 |
|
--- |
| 11337 |
if (SDValue V = foldSelectOfConstants(N)) |
0 |
11337 |
if (SDValue V = foldSelectOfConstants(N)) |
0 |
| 11338 |
return V; |
0 |
11338 |
return V; |
0 |
| 11339 |
|
--- |
11339 |
|
--- |
| 11340 |
// If we can fold this based on the true/false value, do so. |
--- |
11340 |
// If we can fold this based on the true/false value, do so. |
--- |
| 11341 |
if (SimplifySelectOps(N, N1, N2)) |
0 |
11341 |
if (SimplifySelectOps(N, N1, N2)) |
0 |
| 11342 |
return SDValue(N, 0); // Don't revisit N. |
0 |
11342 |
return SDValue(N, 0); // Don't revisit N. |
0 |
| 11343 |
|
--- |
11343 |
|
--- |
| 11344 |
if (VT0 == MVT::i1) { |
0 |
11344 |
if (VT0 == MVT::i1) { |
0 |
| 11345 |
// The code in this block deals with the following 2 equivalences: |
--- |
11345 |
// The code in this block deals with the following 2 equivalences: |
--- |
| 11346 |
// select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) |
--- |
11346 |
// select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) |
--- |
| 11347 |
// select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) |
--- |
11347 |
// select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) |
--- |
| 11348 |
// The target can specify its preferred form with the |
--- |
11348 |
// The target can specify its preferred form with the |
--- |
| 11349 |
// shouldNormalizeToSelectSequence() callback. However we always transform |
--- |
11349 |
// shouldNormalizeToSelectSequence() callback. However we always transform |
--- |
| 11350 |
// to the right anyway if we find the inner select exists in the DAG anyway |
--- |
11350 |
// to the right anyway if we find the inner select exists in the DAG anyway |
--- |
| 11351 |
// and we always transform to the left side if we know that we can further |
--- |
11351 |
// and we always transform to the left side if we know that we can further |
--- |
| 11352 |
// optimize the combination of the conditions. |
--- |
11352 |
// optimize the combination of the conditions. |
--- |
| 11353 |
bool normalizeToSequence = |
--- |
11353 |
bool normalizeToSequence = |
--- |
| 11354 |
TLI.shouldNormalizeToSelectSequence(*DAG.getContext(), VT); |
0 |
11354 |
TLI.shouldNormalizeToSelectSequence(*DAG.getContext(), VT); |
0 |
| 11355 |
// select (and Cond0, Cond1), X, Y |
--- |
11355 |
// select (and Cond0, Cond1), X, Y |
--- |
| 11356 |
// -> select Cond0, (select Cond1, X, Y), Y |
--- |
11356 |
// -> select Cond0, (select Cond1, X, Y), Y |
--- |
| 11357 |
if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) { |
0 |
11357 |
if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) { |
0 |
| 11358 |
SDValue Cond0 = N0->getOperand(0); |
0 |
11358 |
SDValue Cond0 = N0->getOperand(0); |
0 |
| 11359 |
SDValue Cond1 = N0->getOperand(1); |
0 |
11359 |
SDValue Cond1 = N0->getOperand(1); |
0 |
| 11360 |
SDValue InnerSelect = |
--- |
11360 |
SDValue InnerSelect = |
--- |
| 11361 |
DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond1, N1, N2, Flags); |
0 |
11361 |
DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond1, N1, N2, Flags); |
0 |
| 11362 |
if (normalizeToSequence || !InnerSelect.use_empty()) |
0 |
11362 |
if (normalizeToSequence || !InnerSelect.use_empty()) |
0 |
| 11363 |
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, |
0 |
11363 |
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, |
0 |
| 11364 |
InnerSelect, N2, Flags); |
0 |
11364 |
InnerSelect, N2, Flags); |
0 |
| 11365 |
// Cleanup on failure. |
--- |
11365 |
// Cleanup on failure. |
--- |
| 11366 |
if (InnerSelect.use_empty()) |
0 |
11366 |
if (InnerSelect.use_empty()) |
0 |
| 11367 |
recursivelyDeleteUnusedNodes(InnerSelect.getNode()); |
0 |
11367 |
recursivelyDeleteUnusedNodes(InnerSelect.getNode()); |
0 |
| 11368 |
} |
--- |
11368 |
} |
--- |
| 11369 |
// select (or Cond0, Cond1), X, Y -> select Cond0, X, (select Cond1, X, Y) |
--- |
11369 |
// select (or Cond0, Cond1), X, Y -> select Cond0, X, (select Cond1, X, Y) |
--- |
| 11370 |
if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) { |
0 |
11370 |
if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) { |
0 |
| 11371 |
SDValue Cond0 = N0->getOperand(0); |
0 |
11371 |
SDValue Cond0 = N0->getOperand(0); |
0 |
| 11372 |
SDValue Cond1 = N0->getOperand(1); |
0 |
11372 |
SDValue Cond1 = N0->getOperand(1); |
0 |
| 11373 |
SDValue InnerSelect = DAG.getNode(ISD::SELECT, DL, N1.getValueType(), |
0 |
11373 |
SDValue InnerSelect = DAG.getNode(ISD::SELECT, DL, N1.getValueType(), |
0 |
| 11374 |
Cond1, N1, N2, Flags); |
--- |
11374 |
Cond1, N1, N2, Flags); |
--- |
| 11375 |
if (normalizeToSequence || !InnerSelect.use_empty()) |
0 |
11375 |
if (normalizeToSequence || !InnerSelect.use_empty()) |
0 |
| 11376 |
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, N1, |
0 |
11376 |
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, N1, |
0 |
| 11377 |
InnerSelect, Flags); |
0 |
11377 |
InnerSelect, Flags); |
0 |
| 11378 |
// Cleanup on failure. |
--- |
11378 |
// Cleanup on failure. |
--- |
| 11379 |
if (InnerSelect.use_empty()) |
0 |
11379 |
if (InnerSelect.use_empty()) |
0 |
| 11380 |
recursivelyDeleteUnusedNodes(InnerSelect.getNode()); |
0 |
11380 |
recursivelyDeleteUnusedNodes(InnerSelect.getNode()); |
0 |
| 11381 |
} |
--- |
11381 |
} |
--- |
| 11382 |
|
--- |
11382 |
|
--- |
| 11383 |
// select Cond0, (select Cond1, X, Y), Y -> select (and Cond0, Cond1), X, Y |
--- |
11383 |
// select Cond0, (select Cond1, X, Y), Y -> select (and Cond0, Cond1), X, Y |
--- |
| 11384 |
if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) { |
0 |
11384 |
if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) { |
0 |
| 11385 |
SDValue N1_0 = N1->getOperand(0); |
0 |
11385 |
SDValue N1_0 = N1->getOperand(0); |
0 |
| 11386 |
SDValue N1_1 = N1->getOperand(1); |
0 |
11386 |
SDValue N1_1 = N1->getOperand(1); |
0 |
| 11387 |
SDValue N1_2 = N1->getOperand(2); |
0 |
11387 |
SDValue N1_2 = N1->getOperand(2); |
0 |
| 11388 |
if (N1_2 == N2 && N0.getValueType() == N1_0.getValueType()) { |
0 |
11388 |
if (N1_2 == N2 && N0.getValueType() == N1_0.getValueType()) { |
0 |
| 11389 |
// Create the actual and node if we can generate good code for it. |
--- |
11389 |
// Create the actual and node if we can generate good code for it. |
--- |
| 11390 |
if (!normalizeToSequence) { |
0 |
11390 |
if (!normalizeToSequence) { |
0 |
| 11391 |
SDValue And = DAG.getNode(ISD::AND, DL, N0.getValueType(), N0, N1_0); |
0 |
11391 |
SDValue And = DAG.getNode(ISD::AND, DL, N0.getValueType(), N0, N1_0); |
0 |
| 11392 |
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), And, N1_1, |
0 |
11392 |
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), And, N1_1, |
0 |
| 11393 |
N2, Flags); |
0 |
11393 |
N2, Flags); |
0 |
| 11394 |
} |
--- |
11394 |
} |
--- |
| 11395 |
// Otherwise see if we can optimize the "and" to a better pattern. |
--- |
11395 |
// Otherwise see if we can optimize the "and" to a better pattern. |
--- |
| 11396 |
if (SDValue Combined = visitANDLike(N0, N1_0, N)) { |
0 |
11396 |
if (SDValue Combined = visitANDLike(N0, N1_0, N)) { |
0 |
| 11397 |
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Combined, N1_1, |
0 |
11397 |
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Combined, N1_1, |
0 |
| 11398 |
N2, Flags); |
0 |
11398 |
N2, Flags); |
0 |
| 11399 |
} |
--- |
11399 |
} |
--- |
| 11400 |
} |
--- |
11400 |
} |
--- |
| 11401 |
} |
--- |
11401 |
} |
--- |
| 11402 |
// select Cond0, X, (select Cond1, X, Y) -> select (or Cond0, Cond1), X, Y |
--- |
11402 |
// select Cond0, X, (select Cond1, X, Y) -> select (or Cond0, Cond1), X, Y |
--- |
| 11403 |
if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) { |
0 |
11403 |
if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) { |
0 |
| 11404 |
SDValue N2_0 = N2->getOperand(0); |
0 |
11404 |
SDValue N2_0 = N2->getOperand(0); |
0 |
| 11405 |
SDValue N2_1 = N2->getOperand(1); |
0 |
11405 |
SDValue N2_1 = N2->getOperand(1); |
0 |
| 11406 |
SDValue N2_2 = N2->getOperand(2); |
0 |
11406 |
SDValue N2_2 = N2->getOperand(2); |
0 |
| 11407 |
if (N2_1 == N1 && N0.getValueType() == N2_0.getValueType()) { |
0 |
11407 |
if (N2_1 == N1 && N0.getValueType() == N2_0.getValueType()) { |
0 |
| 11408 |
// Create the actual or node if we can generate good code for it. |
--- |
11408 |
// Create the actual or node if we can generate good code for it. |
--- |
| 11409 |
if (!normalizeToSequence) { |
0 |
11409 |
if (!normalizeToSequence) { |
0 |
| 11410 |
SDValue Or = DAG.getNode(ISD::OR, DL, N0.getValueType(), N0, N2_0); |
0 |
11410 |
SDValue Or = DAG.getNode(ISD::OR, DL, N0.getValueType(), N0, N2_0); |
0 |
| 11411 |
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Or, N1, |
0 |
11411 |
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Or, N1, |
0 |
| 11412 |
N2_2, Flags); |
0 |
11412 |
N2_2, Flags); |
0 |
| 11413 |
} |
--- |
11413 |
} |
--- |
| 11414 |
// Otherwise see if we can optimize to a better pattern. |
--- |
11414 |
// Otherwise see if we can optimize to a better pattern. |
--- |
| 11415 |
if (SDValue Combined = visitORLike(N0, N2_0, N)) |
0 |
11415 |
if (SDValue Combined = visitORLike(N0, N2_0, N)) |
0 |
| 11416 |
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Combined, N1, |
0 |
11416 |
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Combined, N1, |
0 |
| 11417 |
N2_2, Flags); |
0 |
11417 |
N2_2, Flags); |
0 |
| 11418 |
} |
--- |
11418 |
} |
--- |
| 11419 |
} |
--- |
11419 |
} |
--- |
| 11420 |
} |
--- |
11420 |
} |
--- |
| 11421 |
|
--- |
11421 |
|
--- |
| 11422 |
// Fold selects based on a setcc into other things, such as min/max/abs. |
--- |
11422 |
// Fold selects based on a setcc into other things, such as min/max/abs. |
--- |
| 11423 |
if (N0.getOpcode() == ISD::SETCC) { |
0 |
11423 |
if (N0.getOpcode() == ISD::SETCC) { |
0 |
| 11424 |
SDValue Cond0 = N0.getOperand(0), Cond1 = N0.getOperand(1); |
0 |
11424 |
SDValue Cond0 = N0.getOperand(0), Cond1 = N0.getOperand(1); |
0 |
| 11425 |
ISD::CondCode CC = cast(N0.getOperand(2))->get(); |
0 |
11425 |
ISD::CondCode CC = cast(N0.getOperand(2))->get(); |
0 |
| 11426 |
|
--- |
11426 |
|
--- |
| 11427 |
// select (fcmp lt x, y), x, y -> fminnum x, y |
--- |
11427 |
// select (fcmp lt x, y), x, y -> fminnum x, y |
--- |
| 11428 |
// select (fcmp gt x, y), x, y -> fmaxnum x, y |
--- |
11428 |
// select (fcmp gt x, y), x, y -> fmaxnum x, y |
--- |
| 11429 |
// |
--- |
11429 |
// |
--- |
| 11430 |
// This is OK if we don't care what happens if either operand is a NaN. |
--- |
11430 |
// This is OK if we don't care what happens if either operand is a NaN. |
--- |
| 11431 |
if (N0.hasOneUse() && isLegalToCombineMinNumMaxNum(DAG, N1, N2, TLI)) |
0 |
11431 |
if (N0.hasOneUse() && isLegalToCombineMinNumMaxNum(DAG, N1, N2, TLI)) |
0 |
| 11432 |
if (SDValue FMinMax = |
0 |
11432 |
if (SDValue FMinMax = |
0 |
| 11433 |
combineMinNumMaxNum(DL, VT, Cond0, Cond1, N1, N2, CC)) |
0 |
11433 |
combineMinNumMaxNum(DL, VT, Cond0, Cond1, N1, N2, CC)) |
0 |
| 11434 |
return FMinMax; |
0 |
11434 |
return FMinMax; |
0 |
| 11435 |
|
--- |
11435 |
|
--- |
| 11436 |
// Use 'unsigned add with overflow' to optimize an unsigned saturating add. |
--- |
11436 |
// Use 'unsigned add with overflow' to optimize an unsigned saturating add. |
--- |
| 11437 |
// This is conservatively limited to pre-legal-operations to give targets |
--- |
11437 |
// This is conservatively limited to pre-legal-operations to give targets |
--- |
| 11438 |
// a chance to reverse the transform if they want to do that. Also, it is |
--- |
11438 |
// a chance to reverse the transform if they want to do that. Also, it is |
--- |
| 11439 |
// unlikely that the pattern would be formed late, so it's probably not |
--- |
11439 |
// unlikely that the pattern would be formed late, so it's probably not |
--- |
| 11440 |
// worth going through the other checks. |
--- |
11440 |
// worth going through the other checks. |
--- |
| 11441 |
if (!LegalOperations && TLI.isOperationLegalOrCustom(ISD::UADDO, VT) && |
0 |
11441 |
if (!LegalOperations && TLI.isOperationLegalOrCustom(ISD::UADDO, VT) && |
0 |
| 11442 |
CC == ISD::SETUGT && N0.hasOneUse() && isAllOnesConstant(N1) && |
0 |
11442 |
CC == ISD::SETUGT && N0.hasOneUse() && isAllOnesConstant(N1) && |
0 |
| 11443 |
N2.getOpcode() == ISD::ADD && Cond0 == N2.getOperand(0)) { |
0 |
11443 |
N2.getOpcode() == ISD::ADD && Cond0 == N2.getOperand(0)) { |
0 |
| 11444 |
auto *C = dyn_cast(N2.getOperand(1)); |
0 |
11444 |
auto *C = dyn_cast(N2.getOperand(1)); |
0 |
| 11445 |
auto *NotC = dyn_cast(Cond1); |
0 |
11445 |
auto *NotC = dyn_cast(Cond1); |
0 |
| 11446 |
if (C && NotC && C->getAPIntValue() == ~NotC->getAPIntValue()) { |
0 |
11446 |
if (C && NotC && C->getAPIntValue() == ~NotC->getAPIntValue()) { |
0 |
| 11447 |
// select (setcc Cond0, ~C, ugt), -1, (add Cond0, C) --> |
--- |
11447 |
// select (setcc Cond0, ~C, ugt), -1, (add Cond0, C) --> |
--- |
| 11448 |
// uaddo Cond0, C; select uaddo.1, -1, uaddo.0 |
--- |
11448 |
// uaddo Cond0, C; select uaddo.1, -1, uaddo.0 |
--- |
| 11449 |
// |
--- |
11449 |
// |
--- |
| 11450 |
// The IR equivalent of this transform would have this form: |
--- |
11450 |
// The IR equivalent of this transform would have this form: |
--- |
| 11451 |
// %a = add %x, C |
--- |
11451 |
// %a = add %x, C |
--- |
| 11452 |
// %c = icmp ugt %x, ~C |
--- |
11452 |
// %c = icmp ugt %x, ~C |
--- |
| 11453 |
// %r = select %c, -1, %a |
--- |
11453 |
// %r = select %c, -1, %a |
--- |
| 11454 |
// => |
--- |
11454 |
// => |
--- |
| 11455 |
// %u = call {iN,i1} llvm.uadd.with.overflow(%x, C) |
--- |
11455 |
// %u = call {iN,i1} llvm.uadd.with.overflow(%x, C) |
--- |
| 11456 |
// %u0 = extractvalue %u, 0 |
--- |
11456 |
// %u0 = extractvalue %u, 0 |
--- |
| 11457 |
// %u1 = extractvalue %u, 1 |
--- |
11457 |
// %u1 = extractvalue %u, 1 |
--- |
| 11458 |
// %r = select %u1, -1, %u0 |
--- |
11458 |
// %r = select %u1, -1, %u0 |
--- |
| 11459 |
SDVTList VTs = DAG.getVTList(VT, VT0); |
0 |
11459 |
SDVTList VTs = DAG.getVTList(VT, VT0); |
0 |
| 11460 |
SDValue UAO = DAG.getNode(ISD::UADDO, DL, VTs, Cond0, N2.getOperand(1)); |
0 |
11460 |
SDValue UAO = DAG.getNode(ISD::UADDO, DL, VTs, Cond0, N2.getOperand(1)); |
0 |
| 11461 |
return DAG.getSelect(DL, VT, UAO.getValue(1), N1, UAO.getValue(0)); |
0 |
11461 |
return DAG.getSelect(DL, VT, UAO.getValue(1), N1, UAO.getValue(0)); |
0 |
| 11462 |
} |
--- |
11462 |
} |
--- |
| 11463 |
} |
--- |
11463 |
} |
--- |
| 11464 |
|
--- |
11464 |
|
--- |
| 11465 |
if (TLI.isOperationLegal(ISD::SELECT_CC, VT) || |
0 |
11465 |
if (TLI.isOperationLegal(ISD::SELECT_CC, VT) || |
0 |
| 11466 |
(!LegalOperations && |
0 |
11466 |
(!LegalOperations && |
0 |
| 11467 |
TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))) { |
0 |
11467 |
TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))) { |
0 |
| 11468 |
// Any flags available in a select/setcc fold will be on the setcc as they |
--- |
11468 |
// Any flags available in a select/setcc fold will be on the setcc as they |
--- |
| 11469 |
// migrated from fcmp |
--- |
11469 |
// migrated from fcmp |
--- |
| 11470 |
Flags = N0->getFlags(); |
0 |
11470 |
Flags = N0->getFlags(); |
0 |
| 11471 |
SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, VT, Cond0, Cond1, N1, |
0 |
11471 |
SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, VT, Cond0, Cond1, N1, |
0 |
| 11472 |
N2, N0.getOperand(2)); |
0 |
11472 |
N2, N0.getOperand(2)); |
0 |
| 11473 |
SelectNode->setFlags(Flags); |
0 |
11473 |
SelectNode->setFlags(Flags); |
0 |
| 11474 |
return SelectNode; |
0 |
11474 |
return SelectNode; |
0 |
| 11475 |
} |
--- |
11475 |
} |
--- |
| 11476 |
|
--- |
11476 |
|
--- |
| 11477 |
if (SDValue NewSel = SimplifySelect(DL, N0, N1, N2)) |
0 |
11477 |
if (SDValue NewSel = SimplifySelect(DL, N0, N1, N2)) |
0 |
| 11478 |
return NewSel; |
0 |
11478 |
return NewSel; |
0 |
| 11479 |
} |
--- |
11479 |
} |
--- |
| 11480 |
|
--- |
11480 |
|
--- |
| 11481 |
if (!VT.isVector()) |
0 |
11481 |
if (!VT.isVector()) |
0 |
| 11482 |
if (SDValue BinOp = foldSelectOfBinops(N)) |
0 |
11482 |
if (SDValue BinOp = foldSelectOfBinops(N)) |
0 |
| 11483 |
return BinOp; |
0 |
11483 |
return BinOp; |
0 |
| 11484 |
|
--- |
11484 |
|
--- |
| 11485 |
return SDValue(); |
0 |
11485 |
return SDValue(); |
0 |
| 11486 |
} |
0 |
11486 |
} |
0 |
| 11487 |
|
--- |
11487 |
|
--- |
| 11488 |
// This function assumes all the vselect's arguments are CONCAT_VECTOR |
--- |
11488 |
// This function assumes all the vselect's arguments are CONCAT_VECTOR |
--- |
| 11489 |
// nodes and that the condition is a BV of ConstantSDNodes (or undefs). |
--- |
11489 |
// nodes and that the condition is a BV of ConstantSDNodes (or undefs). |
--- |
| 11490 |
static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) { |
0 |
11490 |
static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) { |
0 |
| 11491 |
SDLoc DL(N); |
0 |
11491 |
SDLoc DL(N); |
0 |
| 11492 |
SDValue Cond = N->getOperand(0); |
0 |
11492 |
SDValue Cond = N->getOperand(0); |
0 |
| 11493 |
SDValue LHS = N->getOperand(1); |
0 |
11493 |
SDValue LHS = N->getOperand(1); |
0 |
| 11494 |
SDValue RHS = N->getOperand(2); |
0 |
11494 |
SDValue RHS = N->getOperand(2); |
0 |
| 11495 |
EVT VT = N->getValueType(0); |
0 |
11495 |
EVT VT = N->getValueType(0); |
0 |
| 11496 |
int NumElems = VT.getVectorNumElements(); |
0 |
11496 |
int NumElems = VT.getVectorNumElements(); |
0 |
| 11497 |
assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
11497 |
assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
| 11498 |
RHS.getOpcode() == ISD::CONCAT_VECTORS && |
--- |
11498 |
RHS.getOpcode() == ISD::CONCAT_VECTORS && |
--- |
| 11499 |
Cond.getOpcode() == ISD::BUILD_VECTOR); |
--- |
11499 |
Cond.getOpcode() == ISD::BUILD_VECTOR); |
--- |
| 11500 |
|
--- |
11500 |
|
--- |
| 11501 |
// CONCAT_VECTOR can take an arbitrary number of arguments. We only care about |
--- |
11501 |
// CONCAT_VECTOR can take an arbitrary number of arguments. We only care about |
--- |
| 11502 |
// binary ones here. |
--- |
11502 |
// binary ones here. |
--- |
| 11503 |
if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2) |
0 |
11503 |
if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2) |
0 |
| 11504 |
return SDValue(); |
0 |
11504 |
return SDValue(); |
0 |
| 11505 |
|
--- |
11505 |
|
--- |
| 11506 |
// We're sure we have an even number of elements due to the |
--- |
11506 |
// We're sure we have an even number of elements due to the |
--- |
| 11507 |
// concat_vectors we have as arguments to vselect. |
--- |
11507 |
// concat_vectors we have as arguments to vselect. |
--- |
| 11508 |
// Skip BV elements until we find one that's not an UNDEF |
--- |
11508 |
// Skip BV elements until we find one that's not an UNDEF |
--- |
| 11509 |
// After we find an UNDEF element, keep looping until we get to half the |
--- |
11509 |
// After we find an UNDEF element, keep looping until we get to half the |
--- |
| 11510 |
// length of the BV and see if all the non-undef nodes are the same. |
--- |
11510 |
// length of the BV and see if all the non-undef nodes are the same. |
--- |
| 11511 |
ConstantSDNode *BottomHalf = nullptr; |
0 |
11511 |
ConstantSDNode *BottomHalf = nullptr; |
0 |
| 11512 |
for (int i = 0; i < NumElems / 2; ++i) { |
0 |
11512 |
for (int i = 0; i < NumElems / 2; ++i) { |
0 |
| 11513 |
if (Cond->getOperand(i)->isUndef()) |
0 |
11513 |
if (Cond->getOperand(i)->isUndef()) |
0 |
| 11514 |
continue; |
0 |
11514 |
continue; |
0 |
| 11515 |
|
--- |
11515 |
|
--- |
| 11516 |
if (BottomHalf == nullptr) |
0 |
11516 |
if (BottomHalf == nullptr) |
0 |
| 11517 |
BottomHalf = cast(Cond.getOperand(i)); |
0 |
11517 |
BottomHalf = cast(Cond.getOperand(i)); |
0 |
| 11518 |
else if (Cond->getOperand(i).getNode() != BottomHalf) |
0 |
11518 |
else if (Cond->getOperand(i).getNode() != BottomHalf) |
0 |
| 11519 |
return SDValue(); |
0 |
11519 |
return SDValue(); |
0 |
| 11520 |
} |
--- |
11520 |
} |
--- |
| 11521 |
|
--- |
11521 |
|
--- |
| 11522 |
// Do the same for the second half of the BuildVector |
--- |
11522 |
// Do the same for the second half of the BuildVector |
--- |
| 11523 |
ConstantSDNode *TopHalf = nullptr; |
0 |
11523 |
ConstantSDNode *TopHalf = nullptr; |
0 |
| 11524 |
for (int i = NumElems / 2; i < NumElems; ++i) { |
0 |
11524 |
for (int i = NumElems / 2; i < NumElems; ++i) { |
0 |
| 11525 |
if (Cond->getOperand(i)->isUndef()) |
0 |
11525 |
if (Cond->getOperand(i)->isUndef()) |
0 |
| 11526 |
continue; |
0 |
11526 |
continue; |
0 |
| 11527 |
|
--- |
11527 |
|
--- |
| 11528 |
if (TopHalf == nullptr) |
0 |
11528 |
if (TopHalf == nullptr) |
0 |
| 11529 |
TopHalf = cast(Cond.getOperand(i)); |
0 |
11529 |
TopHalf = cast(Cond.getOperand(i)); |
0 |
| 11530 |
else if (Cond->getOperand(i).getNode() != TopHalf) |
0 |
11530 |
else if (Cond->getOperand(i).getNode() != TopHalf) |
0 |
| 11531 |
return SDValue(); |
0 |
11531 |
return SDValue(); |
0 |
| 11532 |
} |
--- |
11532 |
} |
--- |
| 11533 |
|
--- |
11533 |
|
--- |
| 11534 |
assert(TopHalf && BottomHalf && |
0 |
11534 |
assert(TopHalf && BottomHalf && |
0 |
| 11535 |
"One half of the selector was all UNDEFs and the other was all the " |
--- |
11535 |
"One half of the selector was all UNDEFs and the other was all the " |
--- |
| 11536 |
"same value. This should have been addressed before this function."); |
--- |
11536 |
"same value. This should have been addressed before this function."); |
--- |
| 11537 |
return DAG.getNode( |
0 |
11537 |
return DAG.getNode( |
0 |
| 11538 |
ISD::CONCAT_VECTORS, DL, VT, |
--- |
11538 |
ISD::CONCAT_VECTORS, DL, VT, |
--- |
| 11539 |
BottomHalf->isZero() ? RHS->getOperand(0) : LHS->getOperand(0), |
0 |
11539 |
BottomHalf->isZero() ? RHS->getOperand(0) : LHS->getOperand(0), |
0 |
| 11540 |
TopHalf->isZero() ? RHS->getOperand(1) : LHS->getOperand(1)); |
0 |
11540 |
TopHalf->isZero() ? RHS->getOperand(1) : LHS->getOperand(1)); |
0 |
| 11541 |
} |
0 |
11541 |
} |
0 |
| 11542 |
|
--- |
11542 |
|
--- |
| 11543 |
bool refineUniformBase(SDValue &BasePtr, SDValue &Index, bool IndexIsScaled, |
0 |
11543 |
bool refineUniformBase(SDValue &BasePtr, SDValue &Index, bool IndexIsScaled, |
0 |
| 11544 |
SelectionDAG &DAG, const SDLoc &DL) { |
--- |
11544 |
SelectionDAG &DAG, const SDLoc &DL) { |
--- |
| 11545 |
if (Index.getOpcode() != ISD::ADD) |
0 |
11545 |
if (Index.getOpcode() != ISD::ADD) |
0 |
| 11546 |
return false; |
0 |
11546 |
return false; |
0 |
| 11547 |
|
--- |
11547 |
|
--- |
| 11548 |
// Only perform the transformation when existing operands can be reused. |
--- |
11548 |
// Only perform the transformation when existing operands can be reused. |
--- |
| 11549 |
if (IndexIsScaled) |
0 |
11549 |
if (IndexIsScaled) |
0 |
| 11550 |
return false; |
0 |
11550 |
return false; |
0 |
| 11551 |
|
--- |
11551 |
|
--- |
| 11552 |
if (!isNullConstant(BasePtr) && !Index.hasOneUse()) |
0 |
11552 |
if (!isNullConstant(BasePtr) && !Index.hasOneUse()) |
0 |
| 11553 |
return false; |
0 |
11553 |
return false; |
0 |
| 11554 |
|
--- |
11554 |
|
--- |
| 11555 |
EVT VT = BasePtr.getValueType(); |
0 |
11555 |
EVT VT = BasePtr.getValueType(); |
0 |
| 11556 |
if (SDValue SplatVal = DAG.getSplatValue(Index.getOperand(0)); |
0 |
11556 |
if (SDValue SplatVal = DAG.getSplatValue(Index.getOperand(0)); |
0 |
| 11557 |
SplatVal && SplatVal.getValueType() == VT) { |
0 |
11557 |
SplatVal && SplatVal.getValueType() == VT) { |
0 |
| 11558 |
if (isNullConstant(BasePtr)) |
0 |
11558 |
if (isNullConstant(BasePtr)) |
0 |
| 11559 |
BasePtr = SplatVal; |
0 |
11559 |
BasePtr = SplatVal; |
0 |
| 11560 |
else |
--- |
11560 |
else |
--- |
| 11561 |
BasePtr = DAG.getNode(ISD::ADD, DL, VT, BasePtr, SplatVal); |
0 |
11561 |
BasePtr = DAG.getNode(ISD::ADD, DL, VT, BasePtr, SplatVal); |
0 |
| 11562 |
Index = Index.getOperand(1); |
0 |
11562 |
Index = Index.getOperand(1); |
0 |
| 11563 |
return true; |
0 |
11563 |
return true; |
0 |
| 11564 |
} |
--- |
11564 |
} |
--- |
| 11565 |
if (SDValue SplatVal = DAG.getSplatValue(Index.getOperand(1)); |
0 |
11565 |
if (SDValue SplatVal = DAG.getSplatValue(Index.getOperand(1)); |
0 |
| 11566 |
SplatVal && SplatVal.getValueType() == VT) { |
0 |
11566 |
SplatVal && SplatVal.getValueType() == VT) { |
0 |
| 11567 |
if (isNullConstant(BasePtr)) |
0 |
11567 |
if (isNullConstant(BasePtr)) |
0 |
| 11568 |
BasePtr = SplatVal; |
0 |
11568 |
BasePtr = SplatVal; |
0 |
| 11569 |
else |
--- |
11569 |
else |
--- |
| 11570 |
BasePtr = DAG.getNode(ISD::ADD, DL, VT, BasePtr, SplatVal); |
0 |
11570 |
BasePtr = DAG.getNode(ISD::ADD, DL, VT, BasePtr, SplatVal); |
0 |
| 11571 |
Index = Index.getOperand(0); |
0 |
11571 |
Index = Index.getOperand(0); |
0 |
| 11572 |
return true; |
0 |
11572 |
return true; |
0 |
| 11573 |
} |
--- |
11573 |
} |
--- |
| 11574 |
return false; |
0 |
11574 |
return false; |
0 |
| 11575 |
} |
--- |
11575 |
} |
--- |
| 11576 |
|
--- |
11576 |
|
--- |
| 11577 |
// Fold sext/zext of index into index type. |
--- |
11577 |
// Fold sext/zext of index into index type. |
--- |
| 11578 |
bool refineIndexType(SDValue &Index, ISD::MemIndexType &IndexType, EVT DataVT, |
0 |
11578 |
bool refineIndexType(SDValue &Index, ISD::MemIndexType &IndexType, EVT DataVT, |
0 |
| 11579 |
SelectionDAG &DAG) { |
--- |
11579 |
SelectionDAG &DAG) { |
--- |
| 11580 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
11580 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 11581 |
|
--- |
11581 |
|
--- |
| 11582 |
// It's always safe to look through zero extends. |
--- |
11582 |
// It's always safe to look through zero extends. |
--- |
| 11583 |
if (Index.getOpcode() == ISD::ZERO_EXTEND) { |
0 |
11583 |
if (Index.getOpcode() == ISD::ZERO_EXTEND) { |
0 |
| 11584 |
SDValue Op = Index.getOperand(0); |
0 |
11584 |
SDValue Op = Index.getOperand(0); |
0 |
| 11585 |
if (TLI.shouldRemoveExtendFromGSIndex(Op.getValueType(), DataVT)) { |
0 |
11585 |
if (TLI.shouldRemoveExtendFromGSIndex(Op.getValueType(), DataVT)) { |
0 |
| 11586 |
IndexType = ISD::UNSIGNED_SCALED; |
0 |
11586 |
IndexType = ISD::UNSIGNED_SCALED; |
0 |
| 11587 |
Index = Op; |
0 |
11587 |
Index = Op; |
0 |
| 11588 |
return true; |
0 |
11588 |
return true; |
0 |
| 11589 |
} |
--- |
11589 |
} |
--- |
| 11590 |
if (ISD::isIndexTypeSigned(IndexType)) { |
0 |
11590 |
if (ISD::isIndexTypeSigned(IndexType)) { |
0 |
| 11591 |
IndexType = ISD::UNSIGNED_SCALED; |
0 |
11591 |
IndexType = ISD::UNSIGNED_SCALED; |
0 |
| 11592 |
return true; |
0 |
11592 |
return true; |
0 |
| 11593 |
} |
--- |
11593 |
} |
--- |
| 11594 |
} |
--- |
11594 |
} |
--- |
| 11595 |
|
--- |
11595 |
|
--- |
| 11596 |
// It's only safe to look through sign extends when Index is signed. |
--- |
11596 |
// It's only safe to look through sign extends when Index is signed. |
--- |
| 11597 |
if (Index.getOpcode() == ISD::SIGN_EXTEND && |
0 |
11597 |
if (Index.getOpcode() == ISD::SIGN_EXTEND && |
0 |
| 11598 |
ISD::isIndexTypeSigned(IndexType)) { |
0 |
11598 |
ISD::isIndexTypeSigned(IndexType)) { |
0 |
| 11599 |
SDValue Op = Index.getOperand(0); |
0 |
11599 |
SDValue Op = Index.getOperand(0); |
0 |
| 11600 |
if (TLI.shouldRemoveExtendFromGSIndex(Op.getValueType(), DataVT)) { |
0 |
11600 |
if (TLI.shouldRemoveExtendFromGSIndex(Op.getValueType(), DataVT)) { |
0 |
| 11601 |
Index = Op; |
0 |
11601 |
Index = Op; |
0 |
| 11602 |
return true; |
0 |
11602 |
return true; |
0 |
| 11603 |
} |
--- |
11603 |
} |
--- |
| 11604 |
} |
--- |
11604 |
} |
--- |
| 11605 |
|
--- |
11605 |
|
--- |
| 11606 |
return false; |
0 |
11606 |
return false; |
0 |
| 11607 |
} |
--- |
11607 |
} |
--- |
| 11608 |
|
--- |
11608 |
|
--- |
| 11609 |
SDValue DAGCombiner::visitVPSCATTER(SDNode *N) { |
0 |
11609 |
SDValue DAGCombiner::visitVPSCATTER(SDNode *N) { |
0 |
| 11610 |
VPScatterSDNode *MSC = cast(N); |
0 |
11610 |
VPScatterSDNode *MSC = cast(N); |
0 |
| 11611 |
SDValue Mask = MSC->getMask(); |
0 |
11611 |
SDValue Mask = MSC->getMask(); |
0 |
| 11612 |
SDValue Chain = MSC->getChain(); |
0 |
11612 |
SDValue Chain = MSC->getChain(); |
0 |
| 11613 |
SDValue Index = MSC->getIndex(); |
0 |
11613 |
SDValue Index = MSC->getIndex(); |
0 |
| 11614 |
SDValue Scale = MSC->getScale(); |
0 |
11614 |
SDValue Scale = MSC->getScale(); |
0 |
| 11615 |
SDValue StoreVal = MSC->getValue(); |
0 |
11615 |
SDValue StoreVal = MSC->getValue(); |
0 |
| 11616 |
SDValue BasePtr = MSC->getBasePtr(); |
0 |
11616 |
SDValue BasePtr = MSC->getBasePtr(); |
0 |
| 11617 |
SDValue VL = MSC->getVectorLength(); |
0 |
11617 |
SDValue VL = MSC->getVectorLength(); |
0 |
| 11618 |
ISD::MemIndexType IndexType = MSC->getIndexType(); |
0 |
11618 |
ISD::MemIndexType IndexType = MSC->getIndexType(); |
0 |
| 11619 |
SDLoc DL(N); |
0 |
11619 |
SDLoc DL(N); |
0 |
| 11620 |
|
--- |
11620 |
|
--- |
| 11621 |
// Zap scatters with a zero mask. |
--- |
11621 |
// Zap scatters with a zero mask. |
--- |
| 11622 |
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode())) |
0 |
11622 |
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode())) |
0 |
| 11623 |
return Chain; |
0 |
11623 |
return Chain; |
0 |
| 11624 |
|
--- |
11624 |
|
--- |
| 11625 |
if (refineUniformBase(BasePtr, Index, MSC->isIndexScaled(), DAG, DL)) { |
0 |
11625 |
if (refineUniformBase(BasePtr, Index, MSC->isIndexScaled(), DAG, DL)) { |
0 |
| 11626 |
SDValue Ops[] = {Chain, StoreVal, BasePtr, Index, Scale, Mask, VL}; |
0 |
11626 |
SDValue Ops[] = {Chain, StoreVal, BasePtr, Index, Scale, Mask, VL}; |
0 |
| 11627 |
return DAG.getScatterVP(DAG.getVTList(MVT::Other), MSC->getMemoryVT(), |
0 |
11627 |
return DAG.getScatterVP(DAG.getVTList(MVT::Other), MSC->getMemoryVT(), |
0 |
| 11628 |
DL, Ops, MSC->getMemOperand(), IndexType); |
0 |
11628 |
DL, Ops, MSC->getMemOperand(), IndexType); |
0 |
| 11629 |
} |
--- |
11629 |
} |
--- |
| 11630 |
|
--- |
11630 |
|
--- |
| 11631 |
if (refineIndexType(Index, IndexType, StoreVal.getValueType(), DAG)) { |
0 |
11631 |
if (refineIndexType(Index, IndexType, StoreVal.getValueType(), DAG)) { |
0 |
| 11632 |
SDValue Ops[] = {Chain, StoreVal, BasePtr, Index, Scale, Mask, VL}; |
0 |
11632 |
SDValue Ops[] = {Chain, StoreVal, BasePtr, Index, Scale, Mask, VL}; |
0 |
| 11633 |
return DAG.getScatterVP(DAG.getVTList(MVT::Other), MSC->getMemoryVT(), |
0 |
11633 |
return DAG.getScatterVP(DAG.getVTList(MVT::Other), MSC->getMemoryVT(), |
0 |
| 11634 |
DL, Ops, MSC->getMemOperand(), IndexType); |
0 |
11634 |
DL, Ops, MSC->getMemOperand(), IndexType); |
0 |
| 11635 |
} |
--- |
11635 |
} |
--- |
| 11636 |
|
--- |
11636 |
|
--- |
| 11637 |
return SDValue(); |
0 |
11637 |
return SDValue(); |
0 |
| 11638 |
} |
0 |
11638 |
} |
0 |
| 11639 |
|
--- |
11639 |
|
--- |
| 11640 |
SDValue DAGCombiner::visitMSCATTER(SDNode *N) { |
0 |
11640 |
SDValue DAGCombiner::visitMSCATTER(SDNode *N) { |
0 |
| 11641 |
MaskedScatterSDNode *MSC = cast(N); |
0 |
11641 |
MaskedScatterSDNode *MSC = cast(N); |
0 |
| 11642 |
SDValue Mask = MSC->getMask(); |
0 |
11642 |
SDValue Mask = MSC->getMask(); |
0 |
| 11643 |
SDValue Chain = MSC->getChain(); |
0 |
11643 |
SDValue Chain = MSC->getChain(); |
0 |
| 11644 |
SDValue Index = MSC->getIndex(); |
0 |
11644 |
SDValue Index = MSC->getIndex(); |
0 |
| 11645 |
SDValue Scale = MSC->getScale(); |
0 |
11645 |
SDValue Scale = MSC->getScale(); |
0 |
| 11646 |
SDValue StoreVal = MSC->getValue(); |
0 |
11646 |
SDValue StoreVal = MSC->getValue(); |
0 |
| 11647 |
SDValue BasePtr = MSC->getBasePtr(); |
0 |
11647 |
SDValue BasePtr = MSC->getBasePtr(); |
0 |
| 11648 |
ISD::MemIndexType IndexType = MSC->getIndexType(); |
0 |
11648 |
ISD::MemIndexType IndexType = MSC->getIndexType(); |
0 |
| 11649 |
SDLoc DL(N); |
0 |
11649 |
SDLoc DL(N); |
0 |
| 11650 |
|
--- |
11650 |
|
--- |
| 11651 |
// Zap scatters with a zero mask. |
--- |
11651 |
// Zap scatters with a zero mask. |
--- |
| 11652 |
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode())) |
0 |
11652 |
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode())) |
0 |
| 11653 |
return Chain; |
0 |
11653 |
return Chain; |
0 |
| 11654 |
|
--- |
11654 |
|
--- |
| 11655 |
if (refineUniformBase(BasePtr, Index, MSC->isIndexScaled(), DAG, DL)) { |
0 |
11655 |
if (refineUniformBase(BasePtr, Index, MSC->isIndexScaled(), DAG, DL)) { |
0 |
| 11656 |
SDValue Ops[] = {Chain, StoreVal, Mask, BasePtr, Index, Scale}; |
0 |
11656 |
SDValue Ops[] = {Chain, StoreVal, Mask, BasePtr, Index, Scale}; |
0 |
| 11657 |
return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), MSC->getMemoryVT(), |
0 |
11657 |
return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), MSC->getMemoryVT(), |
0 |
| 11658 |
DL, Ops, MSC->getMemOperand(), IndexType, |
--- |
11658 |
DL, Ops, MSC->getMemOperand(), IndexType, |
--- |
| 11659 |
MSC->isTruncatingStore()); |
0 |
11659 |
MSC->isTruncatingStore()); |
0 |
| 11660 |
} |
--- |
11660 |
} |
--- |
| 11661 |
|
--- |
11661 |
|
--- |
| 11662 |
if (refineIndexType(Index, IndexType, StoreVal.getValueType(), DAG)) { |
0 |
11662 |
if (refineIndexType(Index, IndexType, StoreVal.getValueType(), DAG)) { |
0 |
| 11663 |
SDValue Ops[] = {Chain, StoreVal, Mask, BasePtr, Index, Scale}; |
0 |
11663 |
SDValue Ops[] = {Chain, StoreVal, Mask, BasePtr, Index, Scale}; |
0 |
| 11664 |
return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), MSC->getMemoryVT(), |
0 |
11664 |
return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), MSC->getMemoryVT(), |
0 |
| 11665 |
DL, Ops, MSC->getMemOperand(), IndexType, |
--- |
11665 |
DL, Ops, MSC->getMemOperand(), IndexType, |
--- |
| 11666 |
MSC->isTruncatingStore()); |
0 |
11666 |
MSC->isTruncatingStore()); |
0 |
| 11667 |
} |
--- |
11667 |
} |
--- |
| 11668 |
|
--- |
11668 |
|
--- |
| 11669 |
return SDValue(); |
0 |
11669 |
return SDValue(); |
0 |
| 11670 |
} |
0 |
11670 |
} |
0 |
| 11671 |
|
--- |
11671 |
|
--- |
| 11672 |
SDValue DAGCombiner::visitMSTORE(SDNode *N) { |
0 |
11672 |
SDValue DAGCombiner::visitMSTORE(SDNode *N) { |
0 |
| 11673 |
MaskedStoreSDNode *MST = cast(N); |
0 |
11673 |
MaskedStoreSDNode *MST = cast(N); |
0 |
| 11674 |
SDValue Mask = MST->getMask(); |
0 |
11674 |
SDValue Mask = MST->getMask(); |
0 |
| 11675 |
SDValue Chain = MST->getChain(); |
0 |
11675 |
SDValue Chain = MST->getChain(); |
0 |
| 11676 |
SDValue Value = MST->getValue(); |
0 |
11676 |
SDValue Value = MST->getValue(); |
0 |
| 11677 |
SDValue Ptr = MST->getBasePtr(); |
0 |
11677 |
SDValue Ptr = MST->getBasePtr(); |
0 |
| 11678 |
SDLoc DL(N); |
0 |
11678 |
SDLoc DL(N); |
0 |
| 11679 |
|
--- |
11679 |
|
--- |
| 11680 |
// Zap masked stores with a zero mask. |
--- |
11680 |
// Zap masked stores with a zero mask. |
--- |
| 11681 |
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode())) |
0 |
11681 |
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode())) |
0 |
| 11682 |
return Chain; |
0 |
11682 |
return Chain; |
0 |
| 11683 |
|
--- |
11683 |
|
--- |
| 11684 |
// Remove a masked store if base pointers and masks are equal. |
--- |
11684 |
// Remove a masked store if base pointers and masks are equal. |
--- |
| 11685 |
if (MaskedStoreSDNode *MST1 = dyn_cast(Chain)) { |
0 |
11685 |
if (MaskedStoreSDNode *MST1 = dyn_cast(Chain)) { |
0 |
| 11686 |
if (MST->isUnindexed() && MST->isSimple() && MST1->isUnindexed() && |
0 |
11686 |
if (MST->isUnindexed() && MST->isSimple() && MST1->isUnindexed() && |
0 |
| 11687 |
MST1->isSimple() && MST1->getBasePtr() == Ptr && |
0 |
11687 |
MST1->isSimple() && MST1->getBasePtr() == Ptr && |
0 |
| 11688 |
!MST->getBasePtr().isUndef() && |
0 |
11688 |
!MST->getBasePtr().isUndef() && |
0 |
| 11689 |
((Mask == MST1->getMask() && MST->getMemoryVT().getStoreSize() == |
0 |
11689 |
((Mask == MST1->getMask() && MST->getMemoryVT().getStoreSize() == |
0 |
| 11690 |
MST1->getMemoryVT().getStoreSize()) || |
0 |
11690 |
MST1->getMemoryVT().getStoreSize()) || |
0 |
| 11691 |
ISD::isConstantSplatVectorAllOnes(Mask.getNode())) && |
0 |
11691 |
ISD::isConstantSplatVectorAllOnes(Mask.getNode())) && |
0 |
| 11692 |
TypeSize::isKnownLE(MST1->getMemoryVT().getStoreSize(), |
0 |
11692 |
TypeSize::isKnownLE(MST1->getMemoryVT().getStoreSize(), |
0 |
| 11693 |
MST->getMemoryVT().getStoreSize())) { |
0 |
11693 |
MST->getMemoryVT().getStoreSize())) { |
0 |
| 11694 |
CombineTo(MST1, MST1->getChain()); |
0 |
11694 |
CombineTo(MST1, MST1->getChain()); |
0 |
| 11695 |
if (N->getOpcode() != ISD::DELETED_NODE) |
0 |
11695 |
if (N->getOpcode() != ISD::DELETED_NODE) |
0 |
| 11696 |
AddToWorklist(N); |
0 |
11696 |
AddToWorklist(N); |
0 |
| 11697 |
return SDValue(N, 0); |
0 |
11697 |
return SDValue(N, 0); |
0 |
| 11698 |
} |
--- |
11698 |
} |
--- |
| 11699 |
} |
--- |
11699 |
} |
--- |
| 11700 |
|
--- |
11700 |
|
--- |
| 11701 |
// If this is a masked load with an all ones mask, we can use a unmasked load. |
--- |
11701 |
// If this is a masked load with an all ones mask, we can use a unmasked load. |
--- |
| 11702 |
// FIXME: Can we do this for indexed, compressing, or truncating stores? |
--- |
11702 |
// FIXME: Can we do this for indexed, compressing, or truncating stores? |
--- |
| 11703 |
if (ISD::isConstantSplatVectorAllOnes(Mask.getNode()) && MST->isUnindexed() && |
0 |
11703 |
if (ISD::isConstantSplatVectorAllOnes(Mask.getNode()) && MST->isUnindexed() && |
0 |
| 11704 |
!MST->isCompressingStore() && !MST->isTruncatingStore()) |
0 |
11704 |
!MST->isCompressingStore() && !MST->isTruncatingStore()) |
0 |
| 11705 |
return DAG.getStore(MST->getChain(), SDLoc(N), MST->getValue(), |
0 |
11705 |
return DAG.getStore(MST->getChain(), SDLoc(N), MST->getValue(), |
0 |
| 11706 |
MST->getBasePtr(), MST->getPointerInfo(), |
0 |
11706 |
MST->getBasePtr(), MST->getPointerInfo(), |
0 |
| 11707 |
MST->getOriginalAlign(), MachineMemOperand::MOStore, |
--- |
11707 |
MST->getOriginalAlign(), MachineMemOperand::MOStore, |
--- |
| 11708 |
MST->getAAInfo()); |
0 |
11708 |
MST->getAAInfo()); |
0 |
| 11709 |
|
--- |
11709 |
|
--- |
| 11710 |
// Try transforming N to an indexed store. |
--- |
11710 |
// Try transforming N to an indexed store. |
--- |
| 11711 |
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) |
0 |
11711 |
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) |
0 |
| 11712 |
return SDValue(N, 0); |
0 |
11712 |
return SDValue(N, 0); |
0 |
| 11713 |
|
--- |
11713 |
|
--- |
| 11714 |
if (MST->isTruncatingStore() && MST->isUnindexed() && |
0 |
11714 |
if (MST->isTruncatingStore() && MST->isUnindexed() && |
0 |
| 11715 |
Value.getValueType().isInteger() && |
0 |
11715 |
Value.getValueType().isInteger() && |
0 |
| 11716 |
(!isa(Value) || |
0 |
11716 |
(!isa(Value) || |
0 |
| 11717 |
!cast(Value)->isOpaque())) { |
0 |
11717 |
!cast(Value)->isOpaque())) { |
0 |
| 11718 |
APInt TruncDemandedBits = |
--- |
11718 |
APInt TruncDemandedBits = |
--- |
| 11719 |
APInt::getLowBitsSet(Value.getScalarValueSizeInBits(), |
0 |
11719 |
APInt::getLowBitsSet(Value.getScalarValueSizeInBits(), |
0 |
| 11720 |
MST->getMemoryVT().getScalarSizeInBits()); |
0 |
11720 |
MST->getMemoryVT().getScalarSizeInBits()); |
0 |
| 11721 |
|
--- |
11721 |
|
--- |
| 11722 |
// See if we can simplify the operation with |
--- |
11722 |
// See if we can simplify the operation with |
--- |
| 11723 |
// SimplifyDemandedBits, which only works if the value has a single use. |
--- |
11723 |
// SimplifyDemandedBits, which only works if the value has a single use. |
--- |
| 11724 |
if (SimplifyDemandedBits(Value, TruncDemandedBits)) { |
0 |
11724 |
if (SimplifyDemandedBits(Value, TruncDemandedBits)) { |
0 |
| 11725 |
// Re-visit the store if anything changed and the store hasn't been merged |
--- |
11725 |
// Re-visit the store if anything changed and the store hasn't been merged |
--- |
| 11726 |
// with another node (N is deleted) SimplifyDemandedBits will add Value's |
--- |
11726 |
// with another node (N is deleted) SimplifyDemandedBits will add Value's |
--- |
| 11727 |
// node back to the worklist if necessary, but we also need to re-visit |
--- |
11727 |
// node back to the worklist if necessary, but we also need to re-visit |
--- |
| 11728 |
// the Store node itself. |
--- |
11728 |
// the Store node itself. |
--- |
| 11729 |
if (N->getOpcode() != ISD::DELETED_NODE) |
0 |
11729 |
if (N->getOpcode() != ISD::DELETED_NODE) |
0 |
| 11730 |
AddToWorklist(N); |
0 |
11730 |
AddToWorklist(N); |
0 |
| 11731 |
return SDValue(N, 0); |
0 |
11731 |
return SDValue(N, 0); |
0 |
| 11732 |
} |
--- |
11732 |
} |
--- |
| 11733 |
} |
0 |
11733 |
} |
0 |
| 11734 |
|
--- |
11734 |
|
--- |
| 11735 |
// If this is a TRUNC followed by a masked store, fold this into a masked |
--- |
11735 |
// If this is a TRUNC followed by a masked store, fold this into a masked |
--- |
| 11736 |
// truncating store. We can do this even if this is already a masked |
--- |
11736 |
// truncating store. We can do this even if this is already a masked |
--- |
| 11737 |
// truncstore. |
--- |
11737 |
// truncstore. |
--- |
| 11738 |
// TODO: Try combine to masked compress store if possiable. |
--- |
11738 |
// TODO: Try combine to masked compress store if possiable. |
--- |
| 11739 |
if ((Value.getOpcode() == ISD::TRUNCATE) && Value->hasOneUse() && |
0 |
11739 |
if ((Value.getOpcode() == ISD::TRUNCATE) && Value->hasOneUse() && |
0 |
| 11740 |
MST->isUnindexed() && !MST->isCompressingStore() && |
0 |
11740 |
MST->isUnindexed() && !MST->isCompressingStore() && |
0 |
| 11741 |
TLI.canCombineTruncStore(Value.getOperand(0).getValueType(), |
0 |
11741 |
TLI.canCombineTruncStore(Value.getOperand(0).getValueType(), |
0 |
| 11742 |
MST->getMemoryVT(), LegalOperations)) { |
0 |
11742 |
MST->getMemoryVT(), LegalOperations)) { |
0 |
| 11743 |
auto Mask = TLI.promoteTargetBoolean(DAG, MST->getMask(), |
0 |
11743 |
auto Mask = TLI.promoteTargetBoolean(DAG, MST->getMask(), |
0 |
| 11744 |
Value.getOperand(0).getValueType()); |
0 |
11744 |
Value.getOperand(0).getValueType()); |
0 |
| 11745 |
return DAG.getMaskedStore(Chain, SDLoc(N), Value.getOperand(0), Ptr, |
0 |
11745 |
return DAG.getMaskedStore(Chain, SDLoc(N), Value.getOperand(0), Ptr, |
0 |
| 11746 |
MST->getOffset(), Mask, MST->getMemoryVT(), |
0 |
11746 |
MST->getOffset(), Mask, MST->getMemoryVT(), |
0 |
| 11747 |
MST->getMemOperand(), MST->getAddressingMode(), |
--- |
11747 |
MST->getMemOperand(), MST->getAddressingMode(), |
--- |
| 11748 |
/*IsTruncating=*/true); |
0 |
11748 |
/*IsTruncating=*/true); |
0 |
| 11749 |
} |
--- |
11749 |
} |
--- |
| 11750 |
|
--- |
11750 |
|
--- |
| 11751 |
return SDValue(); |
0 |
11751 |
return SDValue(); |
0 |
| 11752 |
} |
0 |
11752 |
} |
0 |
| 11753 |
|
--- |
11753 |
|
--- |
| 11754 |
SDValue DAGCombiner::visitVPGATHER(SDNode *N) { |
0 |
11754 |
SDValue DAGCombiner::visitVPGATHER(SDNode *N) { |
0 |
| 11755 |
VPGatherSDNode *MGT = cast(N); |
0 |
11755 |
VPGatherSDNode *MGT = cast(N); |
0 |
| 11756 |
SDValue Mask = MGT->getMask(); |
0 |
11756 |
SDValue Mask = MGT->getMask(); |
0 |
| 11757 |
SDValue Chain = MGT->getChain(); |
0 |
11757 |
SDValue Chain = MGT->getChain(); |
0 |
| 11758 |
SDValue Index = MGT->getIndex(); |
0 |
11758 |
SDValue Index = MGT->getIndex(); |
0 |
| 11759 |
SDValue Scale = MGT->getScale(); |
0 |
11759 |
SDValue Scale = MGT->getScale(); |
0 |
| 11760 |
SDValue BasePtr = MGT->getBasePtr(); |
0 |
11760 |
SDValue BasePtr = MGT->getBasePtr(); |
0 |
| 11761 |
SDValue VL = MGT->getVectorLength(); |
0 |
11761 |
SDValue VL = MGT->getVectorLength(); |
0 |
| 11762 |
ISD::MemIndexType IndexType = MGT->getIndexType(); |
0 |
11762 |
ISD::MemIndexType IndexType = MGT->getIndexType(); |
0 |
| 11763 |
SDLoc DL(N); |
0 |
11763 |
SDLoc DL(N); |
0 |
| 11764 |
|
--- |
11764 |
|
--- |
| 11765 |
if (refineUniformBase(BasePtr, Index, MGT->isIndexScaled(), DAG, DL)) { |
0 |
11765 |
if (refineUniformBase(BasePtr, Index, MGT->isIndexScaled(), DAG, DL)) { |
0 |
| 11766 |
SDValue Ops[] = {Chain, BasePtr, Index, Scale, Mask, VL}; |
0 |
11766 |
SDValue Ops[] = {Chain, BasePtr, Index, Scale, Mask, VL}; |
0 |
| 11767 |
return DAG.getGatherVP( |
0 |
11767 |
return DAG.getGatherVP( |
0 |
| 11768 |
DAG.getVTList(N->getValueType(0), MVT::Other), MGT->getMemoryVT(), DL, |
0 |
11768 |
DAG.getVTList(N->getValueType(0), MVT::Other), MGT->getMemoryVT(), DL, |
0 |
| 11769 |
Ops, MGT->getMemOperand(), IndexType); |
0 |
11769 |
Ops, MGT->getMemOperand(), IndexType); |
0 |
| 11770 |
} |
--- |
11770 |
} |
--- |
| 11771 |
|
--- |
11771 |
|
--- |
| 11772 |
if (refineIndexType(Index, IndexType, N->getValueType(0), DAG)) { |
0 |
11772 |
if (refineIndexType(Index, IndexType, N->getValueType(0), DAG)) { |
0 |
| 11773 |
SDValue Ops[] = {Chain, BasePtr, Index, Scale, Mask, VL}; |
0 |
11773 |
SDValue Ops[] = {Chain, BasePtr, Index, Scale, Mask, VL}; |
0 |
| 11774 |
return DAG.getGatherVP( |
0 |
11774 |
return DAG.getGatherVP( |
0 |
| 11775 |
DAG.getVTList(N->getValueType(0), MVT::Other), MGT->getMemoryVT(), DL, |
0 |
11775 |
DAG.getVTList(N->getValueType(0), MVT::Other), MGT->getMemoryVT(), DL, |
0 |
| 11776 |
Ops, MGT->getMemOperand(), IndexType); |
0 |
11776 |
Ops, MGT->getMemOperand(), IndexType); |
0 |
| 11777 |
} |
--- |
11777 |
} |
--- |
| 11778 |
|
--- |
11778 |
|
--- |
| 11779 |
return SDValue(); |
0 |
11779 |
return SDValue(); |
0 |
| 11780 |
} |
0 |
11780 |
} |
0 |
| 11781 |
|
--- |
11781 |
|
--- |
| 11782 |
SDValue DAGCombiner::visitMGATHER(SDNode *N) { |
0 |
11782 |
SDValue DAGCombiner::visitMGATHER(SDNode *N) { |
0 |
| 11783 |
MaskedGatherSDNode *MGT = cast(N); |
0 |
11783 |
MaskedGatherSDNode *MGT = cast(N); |
0 |
| 11784 |
SDValue Mask = MGT->getMask(); |
0 |
11784 |
SDValue Mask = MGT->getMask(); |
0 |
| 11785 |
SDValue Chain = MGT->getChain(); |
0 |
11785 |
SDValue Chain = MGT->getChain(); |
0 |
| 11786 |
SDValue Index = MGT->getIndex(); |
0 |
11786 |
SDValue Index = MGT->getIndex(); |
0 |
| 11787 |
SDValue Scale = MGT->getScale(); |
0 |
11787 |
SDValue Scale = MGT->getScale(); |
0 |
| 11788 |
SDValue PassThru = MGT->getPassThru(); |
0 |
11788 |
SDValue PassThru = MGT->getPassThru(); |
0 |
| 11789 |
SDValue BasePtr = MGT->getBasePtr(); |
0 |
11789 |
SDValue BasePtr = MGT->getBasePtr(); |
0 |
| 11790 |
ISD::MemIndexType IndexType = MGT->getIndexType(); |
0 |
11790 |
ISD::MemIndexType IndexType = MGT->getIndexType(); |
0 |
| 11791 |
SDLoc DL(N); |
0 |
11791 |
SDLoc DL(N); |
0 |
| 11792 |
|
--- |
11792 |
|
--- |
| 11793 |
// Zap gathers with a zero mask. |
--- |
11793 |
// Zap gathers with a zero mask. |
--- |
| 11794 |
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode())) |
0 |
11794 |
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode())) |
0 |
| 11795 |
return CombineTo(N, PassThru, MGT->getChain()); |
0 |
11795 |
return CombineTo(N, PassThru, MGT->getChain()); |
0 |
| 11796 |
|
--- |
11796 |
|
--- |
| 11797 |
if (refineUniformBase(BasePtr, Index, MGT->isIndexScaled(), DAG, DL)) { |
0 |
11797 |
if (refineUniformBase(BasePtr, Index, MGT->isIndexScaled(), DAG, DL)) { |
0 |
| 11798 |
SDValue Ops[] = {Chain, PassThru, Mask, BasePtr, Index, Scale}; |
0 |
11798 |
SDValue Ops[] = {Chain, PassThru, Mask, BasePtr, Index, Scale}; |
0 |
| 11799 |
return DAG.getMaskedGather( |
0 |
11799 |
return DAG.getMaskedGather( |
0 |
| 11800 |
DAG.getVTList(N->getValueType(0), MVT::Other), MGT->getMemoryVT(), DL, |
0 |
11800 |
DAG.getVTList(N->getValueType(0), MVT::Other), MGT->getMemoryVT(), DL, |
0 |
| 11801 |
Ops, MGT->getMemOperand(), IndexType, MGT->getExtensionType()); |
0 |
11801 |
Ops, MGT->getMemOperand(), IndexType, MGT->getExtensionType()); |
0 |
| 11802 |
} |
--- |
11802 |
} |
--- |
| 11803 |
|
--- |
11803 |
|
--- |
| 11804 |
if (refineIndexType(Index, IndexType, N->getValueType(0), DAG)) { |
0 |
11804 |
if (refineIndexType(Index, IndexType, N->getValueType(0), DAG)) { |
0 |
| 11805 |
SDValue Ops[] = {Chain, PassThru, Mask, BasePtr, Index, Scale}; |
0 |
11805 |
SDValue Ops[] = {Chain, PassThru, Mask, BasePtr, Index, Scale}; |
0 |
| 11806 |
return DAG.getMaskedGather( |
0 |
11806 |
return DAG.getMaskedGather( |
0 |
| 11807 |
DAG.getVTList(N->getValueType(0), MVT::Other), MGT->getMemoryVT(), DL, |
0 |
11807 |
DAG.getVTList(N->getValueType(0), MVT::Other), MGT->getMemoryVT(), DL, |
0 |
| 11808 |
Ops, MGT->getMemOperand(), IndexType, MGT->getExtensionType()); |
0 |
11808 |
Ops, MGT->getMemOperand(), IndexType, MGT->getExtensionType()); |
0 |
| 11809 |
} |
--- |
11809 |
} |
--- |
| 11810 |
|
--- |
11810 |
|
--- |
| 11811 |
return SDValue(); |
0 |
11811 |
return SDValue(); |
0 |
| 11812 |
} |
0 |
11812 |
} |
0 |
| 11813 |
|
--- |
11813 |
|
--- |
| 11814 |
SDValue DAGCombiner::visitMLOAD(SDNode *N) { |
0 |
11814 |
SDValue DAGCombiner::visitMLOAD(SDNode *N) { |
0 |
| 11815 |
MaskedLoadSDNode *MLD = cast(N); |
0 |
11815 |
MaskedLoadSDNode *MLD = cast(N); |
0 |
| 11816 |
SDValue Mask = MLD->getMask(); |
0 |
11816 |
SDValue Mask = MLD->getMask(); |
0 |
| 11817 |
SDLoc DL(N); |
0 |
11817 |
SDLoc DL(N); |
0 |
| 11818 |
|
--- |
11818 |
|
--- |
| 11819 |
// Zap masked loads with a zero mask. |
--- |
11819 |
// Zap masked loads with a zero mask. |
--- |
| 11820 |
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode())) |
0 |
11820 |
if (ISD::isConstantSplatVectorAllZeros(Mask.getNode())) |
0 |
| 11821 |
return CombineTo(N, MLD->getPassThru(), MLD->getChain()); |
0 |
11821 |
return CombineTo(N, MLD->getPassThru(), MLD->getChain()); |
0 |
| 11822 |
|
--- |
11822 |
|
--- |
| 11823 |
// If this is a masked load with an all ones mask, we can use a unmasked load. |
--- |
11823 |
// If this is a masked load with an all ones mask, we can use a unmasked load. |
--- |
| 11824 |
// FIXME: Can we do this for indexed, expanding, or extending loads? |
--- |
11824 |
// FIXME: Can we do this for indexed, expanding, or extending loads? |
--- |
| 11825 |
if (ISD::isConstantSplatVectorAllOnes(Mask.getNode()) && MLD->isUnindexed() && |
0 |
11825 |
if (ISD::isConstantSplatVectorAllOnes(Mask.getNode()) && MLD->isUnindexed() && |
0 |
| 11826 |
!MLD->isExpandingLoad() && MLD->getExtensionType() == ISD::NON_EXTLOAD) { |
0 |
11826 |
!MLD->isExpandingLoad() && MLD->getExtensionType() == ISD::NON_EXTLOAD) { |
0 |
| 11827 |
SDValue NewLd = DAG.getLoad( |
0 |
11827 |
SDValue NewLd = DAG.getLoad( |
0 |
| 11828 |
N->getValueType(0), SDLoc(N), MLD->getChain(), MLD->getBasePtr(), |
0 |
11828 |
N->getValueType(0), SDLoc(N), MLD->getChain(), MLD->getBasePtr(), |
0 |
| 11829 |
MLD->getPointerInfo(), MLD->getOriginalAlign(), |
0 |
11829 |
MLD->getPointerInfo(), MLD->getOriginalAlign(), |
0 |
| 11830 |
MachineMemOperand::MOLoad, MLD->getAAInfo(), MLD->getRanges()); |
0 |
11830 |
MachineMemOperand::MOLoad, MLD->getAAInfo(), MLD->getRanges()); |
0 |
| 11831 |
return CombineTo(N, NewLd, NewLd.getValue(1)); |
0 |
11831 |
return CombineTo(N, NewLd, NewLd.getValue(1)); |
0 |
| 11832 |
} |
--- |
11832 |
} |
--- |
| 11833 |
|
--- |
11833 |
|
--- |
| 11834 |
// Try transforming N to an indexed load. |
--- |
11834 |
// Try transforming N to an indexed load. |
--- |
| 11835 |
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) |
0 |
11835 |
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) |
0 |
| 11836 |
return SDValue(N, 0); |
0 |
11836 |
return SDValue(N, 0); |
0 |
| 11837 |
|
--- |
11837 |
|
--- |
| 11838 |
return SDValue(); |
0 |
11838 |
return SDValue(); |
0 |
| 11839 |
} |
0 |
11839 |
} |
0 |
| 11840 |
|
--- |
11840 |
|
--- |
| 11841 |
/// A vector select of 2 constant vectors can be simplified to math/logic to |
--- |
11841 |
/// A vector select of 2 constant vectors can be simplified to math/logic to |
--- |
| 11842 |
/// avoid a variable select instruction and possibly avoid constant loads. |
--- |
11842 |
/// avoid a variable select instruction and possibly avoid constant loads. |
--- |
| 11843 |
SDValue DAGCombiner::foldVSelectOfConstants(SDNode *N) { |
0 |
11843 |
SDValue DAGCombiner::foldVSelectOfConstants(SDNode *N) { |
0 |
| 11844 |
SDValue Cond = N->getOperand(0); |
0 |
11844 |
SDValue Cond = N->getOperand(0); |
0 |
| 11845 |
SDValue N1 = N->getOperand(1); |
0 |
11845 |
SDValue N1 = N->getOperand(1); |
0 |
| 11846 |
SDValue N2 = N->getOperand(2); |
0 |
11846 |
SDValue N2 = N->getOperand(2); |
0 |
| 11847 |
EVT VT = N->getValueType(0); |
0 |
11847 |
EVT VT = N->getValueType(0); |
0 |
| 11848 |
if (!Cond.hasOneUse() || Cond.getScalarValueSizeInBits() != 1 || |
0 |
11848 |
if (!Cond.hasOneUse() || Cond.getScalarValueSizeInBits() != 1 || |
0 |
| 11849 |
!shouldConvertSelectOfConstantsToMath(Cond, VT, TLI) || |
0 |
11849 |
!shouldConvertSelectOfConstantsToMath(Cond, VT, TLI) || |
0 |
| 11850 |
!ISD::isBuildVectorOfConstantSDNodes(N1.getNode()) || |
0 |
11850 |
!ISD::isBuildVectorOfConstantSDNodes(N1.getNode()) || |
0 |
| 11851 |
!ISD::isBuildVectorOfConstantSDNodes(N2.getNode())) |
0 |
11851 |
!ISD::isBuildVectorOfConstantSDNodes(N2.getNode())) |
0 |
| 11852 |
return SDValue(); |
0 |
11852 |
return SDValue(); |
0 |
| 11853 |
|
--- |
11853 |
|
--- |
| 11854 |
// Check if we can use the condition value to increment/decrement a single |
--- |
11854 |
// Check if we can use the condition value to increment/decrement a single |
--- |
| 11855 |
// constant value. This simplifies a select to an add and removes a constant |
--- |
11855 |
// constant value. This simplifies a select to an add and removes a constant |
--- |
| 11856 |
// load/materialization from the general case. |
--- |
11856 |
// load/materialization from the general case. |
--- |
| 11857 |
bool AllAddOne = true; |
0 |
11857 |
bool AllAddOne = true; |
0 |
| 11858 |
bool AllSubOne = true; |
0 |
11858 |
bool AllSubOne = true; |
0 |
| 11859 |
unsigned Elts = VT.getVectorNumElements(); |
0 |
11859 |
unsigned Elts = VT.getVectorNumElements(); |
0 |
| 11860 |
for (unsigned i = 0; i != Elts; ++i) { |
0 |
11860 |
for (unsigned i = 0; i != Elts; ++i) { |
0 |
| 11861 |
SDValue N1Elt = N1.getOperand(i); |
0 |
11861 |
SDValue N1Elt = N1.getOperand(i); |
0 |
| 11862 |
SDValue N2Elt = N2.getOperand(i); |
0 |
11862 |
SDValue N2Elt = N2.getOperand(i); |
0 |
| 11863 |
if (N1Elt.isUndef() || N2Elt.isUndef()) |
0 |
11863 |
if (N1Elt.isUndef() || N2Elt.isUndef()) |
0 |
| 11864 |
continue; |
0 |
11864 |
continue; |
0 |
| 11865 |
if (N1Elt.getValueType() != N2Elt.getValueType()) |
0 |
11865 |
if (N1Elt.getValueType() != N2Elt.getValueType()) |
0 |
| 11866 |
continue; |
0 |
11866 |
continue; |
0 |
| 11867 |
|
--- |
11867 |
|
--- |
| 11868 |
const APInt &C1 = cast(N1Elt)->getAPIntValue(); |
0 |
11868 |
const APInt &C1 = cast(N1Elt)->getAPIntValue(); |
0 |
| 11869 |
const APInt &C2 = cast(N2Elt)->getAPIntValue(); |
0 |
11869 |
const APInt &C2 = cast(N2Elt)->getAPIntValue(); |
0 |
| 11870 |
if (C1 != C2 + 1) |
0 |
11870 |
if (C1 != C2 + 1) |
0 |
| 11871 |
AllAddOne = false; |
0 |
11871 |
AllAddOne = false; |
0 |
| 11872 |
if (C1 != C2 - 1) |
0 |
11872 |
if (C1 != C2 - 1) |
0 |
| 11873 |
AllSubOne = false; |
0 |
11873 |
AllSubOne = false; |
0 |
| 11874 |
} |
--- |
11874 |
} |
--- |
| 11875 |
|
--- |
11875 |
|
--- |
| 11876 |
// Further simplifications for the extra-special cases where the constants are |
--- |
11876 |
// Further simplifications for the extra-special cases where the constants are |
--- |
| 11877 |
// all 0 or all -1 should be implemented as folds of these patterns. |
--- |
11877 |
// all 0 or all -1 should be implemented as folds of these patterns. |
--- |
| 11878 |
SDLoc DL(N); |
0 |
11878 |
SDLoc DL(N); |
0 |
| 11879 |
if (AllAddOne || AllSubOne) { |
0 |
11879 |
if (AllAddOne || AllSubOne) { |
0 |
| 11880 |
// vselect Cond, C+1, C --> add (zext Cond), C |
--- |
11880 |
// vselect Cond, C+1, C --> add (zext Cond), C |
--- |
| 11881 |
// vselect Cond, C-1, C --> add (sext Cond), C |
--- |
11881 |
// vselect Cond, C-1, C --> add (sext Cond), C |
--- |
| 11882 |
auto ExtendOpcode = AllAddOne ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; |
0 |
11882 |
auto ExtendOpcode = AllAddOne ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; |
0 |
| 11883 |
SDValue ExtendedCond = DAG.getNode(ExtendOpcode, DL, VT, Cond); |
0 |
11883 |
SDValue ExtendedCond = DAG.getNode(ExtendOpcode, DL, VT, Cond); |
0 |
| 11884 |
return DAG.getNode(ISD::ADD, DL, VT, ExtendedCond, N2); |
0 |
11884 |
return DAG.getNode(ISD::ADD, DL, VT, ExtendedCond, N2); |
0 |
| 11885 |
} |
--- |
11885 |
} |
--- |
| 11886 |
|
--- |
11886 |
|
--- |
| 11887 |
// select Cond, Pow2C, 0 --> (zext Cond) << log2(Pow2C) |
--- |
11887 |
// select Cond, Pow2C, 0 --> (zext Cond) << log2(Pow2C) |
--- |
| 11888 |
APInt Pow2C; |
0 |
11888 |
APInt Pow2C; |
0 |
| 11889 |
if (ISD::isConstantSplatVector(N1.getNode(), Pow2C) && Pow2C.isPowerOf2() && |
0 |
11889 |
if (ISD::isConstantSplatVector(N1.getNode(), Pow2C) && Pow2C.isPowerOf2() && |
0 |
| 11890 |
isNullOrNullSplat(N2)) { |
0 |
11890 |
isNullOrNullSplat(N2)) { |
0 |
| 11891 |
SDValue ZextCond = DAG.getZExtOrTrunc(Cond, DL, VT); |
0 |
11891 |
SDValue ZextCond = DAG.getZExtOrTrunc(Cond, DL, VT); |
0 |
| 11892 |
SDValue ShAmtC = DAG.getConstant(Pow2C.exactLogBase2(), DL, VT); |
0 |
11892 |
SDValue ShAmtC = DAG.getConstant(Pow2C.exactLogBase2(), DL, VT); |
0 |
| 11893 |
return DAG.getNode(ISD::SHL, DL, VT, ZextCond, ShAmtC); |
0 |
11893 |
return DAG.getNode(ISD::SHL, DL, VT, ZextCond, ShAmtC); |
0 |
| 11894 |
} |
--- |
11894 |
} |
--- |
| 11895 |
|
--- |
11895 |
|
--- |
| 11896 |
if (SDValue V = foldSelectOfConstantsUsingSra(N, DAG)) |
0 |
11896 |
if (SDValue V = foldSelectOfConstantsUsingSra(N, DAG)) |
0 |
| 11897 |
return V; |
0 |
11897 |
return V; |
0 |
| 11898 |
|
--- |
11898 |
|
--- |
| 11899 |
// The general case for select-of-constants: |
--- |
11899 |
// The general case for select-of-constants: |
--- |
| 11900 |
// vselect Cond, C1, C2 --> xor (and (sext Cond), (C1^C2)), C2 |
--- |
11900 |
// vselect Cond, C1, C2 --> xor (and (sext Cond), (C1^C2)), C2 |
--- |
| 11901 |
// ...but that only makes sense if a vselect is slower than 2 logic ops, so |
--- |
11901 |
// ...but that only makes sense if a vselect is slower than 2 logic ops, so |
--- |
| 11902 |
// leave that to a machine-specific pass. |
--- |
11902 |
// leave that to a machine-specific pass. |
--- |
| 11903 |
return SDValue(); |
0 |
11903 |
return SDValue(); |
0 |
| 11904 |
} |
0 |
11904 |
} |
0 |
| 11905 |
|
--- |
11905 |
|
--- |
| 11906 |
SDValue DAGCombiner::visitVSELECT(SDNode *N) { |
0 |
11906 |
SDValue DAGCombiner::visitVSELECT(SDNode *N) { |
0 |
| 11907 |
SDValue N0 = N->getOperand(0); |
0 |
11907 |
SDValue N0 = N->getOperand(0); |
0 |
| 11908 |
SDValue N1 = N->getOperand(1); |
0 |
11908 |
SDValue N1 = N->getOperand(1); |
0 |
| 11909 |
SDValue N2 = N->getOperand(2); |
0 |
11909 |
SDValue N2 = N->getOperand(2); |
0 |
| 11910 |
EVT VT = N->getValueType(0); |
0 |
11910 |
EVT VT = N->getValueType(0); |
0 |
| 11911 |
SDLoc DL(N); |
0 |
11911 |
SDLoc DL(N); |
0 |
| 11912 |
|
--- |
11912 |
|
--- |
| 11913 |
if (SDValue V = DAG.simplifySelect(N0, N1, N2)) |
0 |
11913 |
if (SDValue V = DAG.simplifySelect(N0, N1, N2)) |
0 |
| 11914 |
return V; |
0 |
11914 |
return V; |
0 |
| 11915 |
|
--- |
11915 |
|
--- |
| 11916 |
if (SDValue V = foldBoolSelectToLogic(N, DAG)) |
0 |
11916 |
if (SDValue V = foldBoolSelectToLogic(N, DAG)) |
0 |
| 11917 |
return V; |
0 |
11917 |
return V; |
0 |
| 11918 |
|
--- |
11918 |
|
--- |
| 11919 |
// vselect (not Cond), N1, N2 -> vselect Cond, N2, N1 |
--- |
11919 |
// vselect (not Cond), N1, N2 -> vselect Cond, N2, N1 |
--- |
| 11920 |
if (SDValue F = extractBooleanFlip(N0, DAG, TLI, false)) |
0 |
11920 |
if (SDValue F = extractBooleanFlip(N0, DAG, TLI, false)) |
0 |
| 11921 |
return DAG.getSelect(DL, VT, F, N2, N1); |
0 |
11921 |
return DAG.getSelect(DL, VT, F, N2, N1); |
0 |
| 11922 |
|
--- |
11922 |
|
--- |
| 11923 |
// Canonicalize integer abs. |
--- |
11923 |
// Canonicalize integer abs. |
--- |
| 11924 |
// vselect (setg[te] X, 0), X, -X -> |
--- |
11924 |
// vselect (setg[te] X, 0), X, -X -> |
--- |
| 11925 |
// vselect (setgt X, -1), X, -X -> |
--- |
11925 |
// vselect (setgt X, -1), X, -X -> |
--- |
| 11926 |
// vselect (setl[te] X, 0), -X, X -> |
--- |
11926 |
// vselect (setl[te] X, 0), -X, X -> |
--- |
| 11927 |
// Y = sra (X, size(X)-1); xor (add (X, Y), Y) |
--- |
11927 |
// Y = sra (X, size(X)-1); xor (add (X, Y), Y) |
--- |
| 11928 |
if (N0.getOpcode() == ISD::SETCC) { |
0 |
11928 |
if (N0.getOpcode() == ISD::SETCC) { |
0 |
| 11929 |
SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); |
0 |
11929 |
SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); |
0 |
| 11930 |
ISD::CondCode CC = cast(N0.getOperand(2))->get(); |
0 |
11930 |
ISD::CondCode CC = cast(N0.getOperand(2))->get(); |
0 |
| 11931 |
bool isAbs = false; |
0 |
11931 |
bool isAbs = false; |
0 |
| 11932 |
bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode()); |
0 |
11932 |
bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode()); |
0 |
| 11933 |
|
--- |
11933 |
|
--- |
| 11934 |
if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) || |
0 |
11934 |
if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) || |
0 |
| 11935 |
(ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) && |
0 |
11935 |
(ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) && |
0 |
| 11936 |
N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1)) |
0 |
11936 |
N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1)) |
0 |
| 11937 |
isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode()); |
0 |
11937 |
isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode()); |
0 |
| 11938 |
else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) && |
0 |
11938 |
else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) && |
0 |
| 11939 |
N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1)) |
0 |
11939 |
N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1)) |
0 |
| 11940 |
isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode()); |
0 |
11940 |
isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode()); |
0 |
| 11941 |
|
--- |
11941 |
|
--- |
| 11942 |
if (isAbs) { |
0 |
11942 |
if (isAbs) { |
0 |
| 11943 |
if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) |
0 |
11943 |
if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) |
0 |
| 11944 |
return DAG.getNode(ISD::ABS, DL, VT, LHS); |
0 |
11944 |
return DAG.getNode(ISD::ABS, DL, VT, LHS); |
0 |
| 11945 |
|
--- |
11945 |
|
--- |
| 11946 |
SDValue Shift = DAG.getNode(ISD::SRA, DL, VT, LHS, |
0 |
11946 |
SDValue Shift = DAG.getNode(ISD::SRA, DL, VT, LHS, |
0 |
| 11947 |
DAG.getConstant(VT.getScalarSizeInBits() - 1, |
0 |
11947 |
DAG.getConstant(VT.getScalarSizeInBits() - 1, |
0 |
| 11948 |
DL, getShiftAmountTy(VT))); |
--- |
11948 |
DL, getShiftAmountTy(VT))); |
--- |
| 11949 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift); |
0 |
11949 |
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift); |
0 |
| 11950 |
AddToWorklist(Shift.getNode()); |
0 |
11950 |
AddToWorklist(Shift.getNode()); |
0 |
| 11951 |
AddToWorklist(Add.getNode()); |
0 |
11951 |
AddToWorklist(Add.getNode()); |
0 |
| 11952 |
return DAG.getNode(ISD::XOR, DL, VT, Add, Shift); |
0 |
11952 |
return DAG.getNode(ISD::XOR, DL, VT, Add, Shift); |
0 |
| 11953 |
} |
--- |
11953 |
} |
--- |
| 11954 |
|
--- |
11954 |
|
--- |
| 11955 |
// vselect x, y (fcmp lt x, y) -> fminnum x, y |
--- |
11955 |
// vselect x, y (fcmp lt x, y) -> fminnum x, y |
--- |
| 11956 |
// vselect x, y (fcmp gt x, y) -> fmaxnum x, y |
--- |
11956 |
// vselect x, y (fcmp gt x, y) -> fmaxnum x, y |
--- |
| 11957 |
// |
--- |
11957 |
// |
--- |
| 11958 |
// This is OK if we don't care about what happens if either operand is a |
--- |
11958 |
// This is OK if we don't care about what happens if either operand is a |
--- |
| 11959 |
// NaN. |
--- |
11959 |
// NaN. |
--- |
| 11960 |
// |
--- |
11960 |
// |
--- |
| 11961 |
if (N0.hasOneUse() && isLegalToCombineMinNumMaxNum(DAG, LHS, RHS, TLI)) { |
0 |
11961 |
if (N0.hasOneUse() && isLegalToCombineMinNumMaxNum(DAG, LHS, RHS, TLI)) { |
0 |
| 11962 |
if (SDValue FMinMax = combineMinNumMaxNum(DL, VT, LHS, RHS, N1, N2, CC)) |
0 |
11962 |
if (SDValue FMinMax = combineMinNumMaxNum(DL, VT, LHS, RHS, N1, N2, CC)) |
0 |
| 11963 |
return FMinMax; |
0 |
11963 |
return FMinMax; |
0 |
| 11964 |
} |
--- |
11964 |
} |
--- |
| 11965 |
|
--- |
11965 |
|
--- |
| 11966 |
if (SDValue S = PerformMinMaxFpToSatCombine(LHS, RHS, N1, N2, CC, DAG)) |
0 |
11966 |
if (SDValue S = PerformMinMaxFpToSatCombine(LHS, RHS, N1, N2, CC, DAG)) |
0 |
| 11967 |
return S; |
0 |
11967 |
return S; |
0 |
| 11968 |
if (SDValue S = PerformUMinFpToSatCombine(LHS, RHS, N1, N2, CC, DAG)) |
0 |
11968 |
if (SDValue S = PerformUMinFpToSatCombine(LHS, RHS, N1, N2, CC, DAG)) |
0 |
| 11969 |
return S; |
0 |
11969 |
return S; |
0 |
| 11970 |
|
--- |
11970 |
|
--- |
| 11971 |
// If this select has a condition (setcc) with narrower operands than the |
--- |
11971 |
// If this select has a condition (setcc) with narrower operands than the |
--- |
| 11972 |
// select, try to widen the compare to match the select width. |
--- |
11972 |
// select, try to widen the compare to match the select width. |
--- |
| 11973 |
// TODO: This should be extended to handle any constant. |
--- |
11973 |
// TODO: This should be extended to handle any constant. |
--- |
| 11974 |
// TODO: This could be extended to handle non-loading patterns, but that |
--- |
11974 |
// TODO: This could be extended to handle non-loading patterns, but that |
--- |
| 11975 |
// requires thorough testing to avoid regressions. |
--- |
11975 |
// requires thorough testing to avoid regressions. |
--- |
| 11976 |
if (isNullOrNullSplat(RHS)) { |
0 |
11976 |
if (isNullOrNullSplat(RHS)) { |
0 |
| 11977 |
EVT NarrowVT = LHS.getValueType(); |
0 |
11977 |
EVT NarrowVT = LHS.getValueType(); |
0 |
| 11978 |
EVT WideVT = N1.getValueType().changeVectorElementTypeToInteger(); |
0 |
11978 |
EVT WideVT = N1.getValueType().changeVectorElementTypeToInteger(); |
0 |
| 11979 |
EVT SetCCVT = getSetCCResultType(LHS.getValueType()); |
0 |
11979 |
EVT SetCCVT = getSetCCResultType(LHS.getValueType()); |
0 |
| 11980 |
unsigned SetCCWidth = SetCCVT.getScalarSizeInBits(); |
0 |
11980 |
unsigned SetCCWidth = SetCCVT.getScalarSizeInBits(); |
0 |
| 11981 |
unsigned WideWidth = WideVT.getScalarSizeInBits(); |
0 |
11981 |
unsigned WideWidth = WideVT.getScalarSizeInBits(); |
0 |
| 11982 |
bool IsSigned = isSignedIntSetCC(CC); |
0 |
11982 |
bool IsSigned = isSignedIntSetCC(CC); |
0 |
| 11983 |
auto LoadExtOpcode = IsSigned ? ISD::SEXTLOAD : ISD::ZEXTLOAD; |
0 |
11983 |
auto LoadExtOpcode = IsSigned ? ISD::SEXTLOAD : ISD::ZEXTLOAD; |
0 |
| 11984 |
if (LHS.getOpcode() == ISD::LOAD && LHS.hasOneUse() && |
0 |
11984 |
if (LHS.getOpcode() == ISD::LOAD && LHS.hasOneUse() && |
0 |
| 11985 |
SetCCWidth != 1 && SetCCWidth < WideWidth && |
0 |
11985 |
SetCCWidth != 1 && SetCCWidth < WideWidth && |
0 |
| 11986 |
TLI.isLoadExtLegalOrCustom(LoadExtOpcode, WideVT, NarrowVT) && |
0 |
11986 |
TLI.isLoadExtLegalOrCustom(LoadExtOpcode, WideVT, NarrowVT) && |
0 |
| 11987 |
TLI.isOperationLegalOrCustom(ISD::SETCC, WideVT)) { |
0 |
11987 |
TLI.isOperationLegalOrCustom(ISD::SETCC, WideVT)) { |
0 |
| 11988 |
// Both compare operands can be widened for free. The LHS can use an |
--- |
11988 |
// Both compare operands can be widened for free. The LHS can use an |
--- |
| 11989 |
// extended load, and the RHS is a constant: |
--- |
11989 |
// extended load, and the RHS is a constant: |
--- |
| 11990 |
// vselect (ext (setcc load(X), C)), N1, N2 --> |
--- |
11990 |
// vselect (ext (setcc load(X), C)), N1, N2 --> |
--- |
| 11991 |
// vselect (setcc extload(X), C'), N1, N2 |
--- |
11991 |
// vselect (setcc extload(X), C'), N1, N2 |
--- |
| 11992 |
auto ExtOpcode = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; |
0 |
11992 |
auto ExtOpcode = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; |
0 |
| 11993 |
SDValue WideLHS = DAG.getNode(ExtOpcode, DL, WideVT, LHS); |
0 |
11993 |
SDValue WideLHS = DAG.getNode(ExtOpcode, DL, WideVT, LHS); |
0 |
| 11994 |
SDValue WideRHS = DAG.getNode(ExtOpcode, DL, WideVT, RHS); |
0 |
11994 |
SDValue WideRHS = DAG.getNode(ExtOpcode, DL, WideVT, RHS); |
0 |
| 11995 |
EVT WideSetCCVT = getSetCCResultType(WideVT); |
0 |
11995 |
EVT WideSetCCVT = getSetCCResultType(WideVT); |
0 |
| 11996 |
SDValue WideSetCC = DAG.getSetCC(DL, WideSetCCVT, WideLHS, WideRHS, CC); |
0 |
11996 |
SDValue WideSetCC = DAG.getSetCC(DL, WideSetCCVT, WideLHS, WideRHS, CC); |
0 |
| 11997 |
return DAG.getSelect(DL, N1.getValueType(), WideSetCC, N1, N2); |
0 |
11997 |
return DAG.getSelect(DL, N1.getValueType(), WideSetCC, N1, N2); |
0 |
| 11998 |
} |
--- |
11998 |
} |
--- |
| 11999 |
} |
--- |
11999 |
} |
--- |
| 12000 |
|
--- |
12000 |
|
--- |
| 12001 |
// Match VSELECTs with absolute difference patterns. |
--- |
12001 |
// Match VSELECTs with absolute difference patterns. |
--- |
| 12002 |
// (vselect (setcc a, b, set?gt), (sub a, b), (sub b, a)) --> (abd? a, b) |
--- |
12002 |
// (vselect (setcc a, b, set?gt), (sub a, b), (sub b, a)) --> (abd? a, b) |
--- |
| 12003 |
// (vselect (setcc a, b, set?ge), (sub a, b), (sub b, a)) --> (abd? a, b) |
--- |
12003 |
// (vselect (setcc a, b, set?ge), (sub a, b), (sub b, a)) --> (abd? a, b) |
--- |
| 12004 |
// (vselect (setcc a, b, set?lt), (sub b, a), (sub a, b)) --> (abd? a, b) |
--- |
12004 |
// (vselect (setcc a, b, set?lt), (sub b, a), (sub a, b)) --> (abd? a, b) |
--- |
| 12005 |
// (vselect (setcc a, b, set?le), (sub b, a), (sub a, b)) --> (abd? a, b) |
--- |
12005 |
// (vselect (setcc a, b, set?le), (sub b, a), (sub a, b)) --> (abd? a, b) |
--- |
| 12006 |
if (N1.getOpcode() == ISD::SUB && N2.getOpcode() == ISD::SUB && |
0 |
12006 |
if (N1.getOpcode() == ISD::SUB && N2.getOpcode() == ISD::SUB && |
0 |
| 12007 |
N1.getOperand(0) == N2.getOperand(1) && |
0 |
12007 |
N1.getOperand(0) == N2.getOperand(1) && |
0 |
| 12008 |
N1.getOperand(1) == N2.getOperand(0)) { |
0 |
12008 |
N1.getOperand(1) == N2.getOperand(0)) { |
0 |
| 12009 |
bool IsSigned = isSignedIntSetCC(CC); |
0 |
12009 |
bool IsSigned = isSignedIntSetCC(CC); |
0 |
| 12010 |
unsigned ABDOpc = IsSigned ? ISD::ABDS : ISD::ABDU; |
0 |
12010 |
unsigned ABDOpc = IsSigned ? ISD::ABDS : ISD::ABDU; |
0 |
| 12011 |
if (hasOperation(ABDOpc, VT)) { |
0 |
12011 |
if (hasOperation(ABDOpc, VT)) { |
0 |
| 12012 |
switch (CC) { |
0 |
12012 |
switch (CC) { |
0 |
| 12013 |
case ISD::SETGT: |
0 |
12013 |
case ISD::SETGT: |
0 |
| 12014 |
case ISD::SETGE: |
--- |
12014 |
case ISD::SETGE: |
--- |
| 12015 |
case ISD::SETUGT: |
--- |
12015 |
case ISD::SETUGT: |
--- |
| 12016 |
case ISD::SETUGE: |
--- |
12016 |
case ISD::SETUGE: |
--- |
| 12017 |
if (LHS == N1.getOperand(0) && RHS == N1.getOperand(1)) |
0 |
12017 |
if (LHS == N1.getOperand(0) && RHS == N1.getOperand(1)) |
0 |
| 12018 |
return DAG.getNode(ABDOpc, DL, VT, LHS, RHS); |
0 |
12018 |
return DAG.getNode(ABDOpc, DL, VT, LHS, RHS); |
0 |
| 12019 |
break; |
0 |
12019 |
break; |
0 |
| 12020 |
case ISD::SETLT: |
0 |
12020 |
case ISD::SETLT: |
0 |
| 12021 |
case ISD::SETLE: |
--- |
12021 |
case ISD::SETLE: |
--- |
| 12022 |
case ISD::SETULT: |
--- |
12022 |
case ISD::SETULT: |
--- |
| 12023 |
case ISD::SETULE: |
--- |
12023 |
case ISD::SETULE: |
--- |
| 12024 |
if (RHS == N1.getOperand(0) && LHS == N1.getOperand(1) ) |
0 |
12024 |
if (RHS == N1.getOperand(0) && LHS == N1.getOperand(1) ) |
0 |
| 12025 |
return DAG.getNode(ABDOpc, DL, VT, LHS, RHS); |
0 |
12025 |
return DAG.getNode(ABDOpc, DL, VT, LHS, RHS); |
0 |
| 12026 |
break; |
0 |
12026 |
break; |
0 |
| 12027 |
default: |
0 |
12027 |
default: |
0 |
| 12028 |
break; |
0 |
12028 |
break; |
0 |
| 12029 |
} |
--- |
12029 |
} |
--- |
| 12030 |
} |
--- |
12030 |
} |
--- |
| 12031 |
} |
--- |
12031 |
} |
--- |
| 12032 |
|
--- |
12032 |
|
--- |
| 12033 |
// Match VSELECTs into add with unsigned saturation. |
--- |
12033 |
// Match VSELECTs into add with unsigned saturation. |
--- |
| 12034 |
if (hasOperation(ISD::UADDSAT, VT)) { |
0 |
12034 |
if (hasOperation(ISD::UADDSAT, VT)) { |
0 |
| 12035 |
// Check if one of the arms of the VSELECT is vector with all bits set. |
--- |
12035 |
// Check if one of the arms of the VSELECT is vector with all bits set. |
--- |
| 12036 |
// If it's on the left side invert the predicate to simplify logic below. |
--- |
12036 |
// If it's on the left side invert the predicate to simplify logic below. |
--- |
| 12037 |
SDValue Other; |
0 |
12037 |
SDValue Other; |
0 |
| 12038 |
ISD::CondCode SatCC = CC; |
0 |
12038 |
ISD::CondCode SatCC = CC; |
0 |
| 12039 |
if (ISD::isConstantSplatVectorAllOnes(N1.getNode())) { |
0 |
12039 |
if (ISD::isConstantSplatVectorAllOnes(N1.getNode())) { |
0 |
| 12040 |
Other = N2; |
0 |
12040 |
Other = N2; |
0 |
| 12041 |
SatCC = ISD::getSetCCInverse(SatCC, VT.getScalarType()); |
0 |
12041 |
SatCC = ISD::getSetCCInverse(SatCC, VT.getScalarType()); |
0 |
| 12042 |
} else if (ISD::isConstantSplatVectorAllOnes(N2.getNode())) { |
0 |
12042 |
} else if (ISD::isConstantSplatVectorAllOnes(N2.getNode())) { |
0 |
| 12043 |
Other = N1; |
0 |
12043 |
Other = N1; |
0 |
| 12044 |
} |
--- |
12044 |
} |
--- |
| 12045 |
|
--- |
12045 |
|
--- |
| 12046 |
if (Other && Other.getOpcode() == ISD::ADD) { |
0 |
12046 |
if (Other && Other.getOpcode() == ISD::ADD) { |
0 |
| 12047 |
SDValue CondLHS = LHS, CondRHS = RHS; |
0 |
12047 |
SDValue CondLHS = LHS, CondRHS = RHS; |
0 |
| 12048 |
SDValue OpLHS = Other.getOperand(0), OpRHS = Other.getOperand(1); |
0 |
12048 |
SDValue OpLHS = Other.getOperand(0), OpRHS = Other.getOperand(1); |
0 |
| 12049 |
|
--- |
12049 |
|
--- |
| 12050 |
// Canonicalize condition operands. |
--- |
12050 |
// Canonicalize condition operands. |
--- |
| 12051 |
if (SatCC == ISD::SETUGE) { |
0 |
12051 |
if (SatCC == ISD::SETUGE) { |
0 |
| 12052 |
std::swap(CondLHS, CondRHS); |
0 |
12052 |
std::swap(CondLHS, CondRHS); |
0 |
| 12053 |
SatCC = ISD::SETULE; |
0 |
12053 |
SatCC = ISD::SETULE; |
0 |
| 12054 |
} |
--- |
12054 |
} |
--- |
| 12055 |
|
--- |
12055 |
|
--- |
| 12056 |
// We can test against either of the addition operands. |
--- |
12056 |
// We can test against either of the addition operands. |
--- |
| 12057 |
// x <= x+y ? x+y : ~0 --> uaddsat x, y |
--- |
12057 |
// x <= x+y ? x+y : ~0 --> uaddsat x, y |
--- |
| 12058 |
// x+y >= x ? x+y : ~0 --> uaddsat x, y |
--- |
12058 |
// x+y >= x ? x+y : ~0 --> uaddsat x, y |
--- |
| 12059 |
if (SatCC == ISD::SETULE && Other == CondRHS && |
0 |
12059 |
if (SatCC == ISD::SETULE && Other == CondRHS && |
0 |
| 12060 |
(OpLHS == CondLHS || OpRHS == CondLHS)) |
0 |
12060 |
(OpLHS == CondLHS || OpRHS == CondLHS)) |
0 |
| 12061 |
return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS); |
0 |
12061 |
return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS); |
0 |
| 12062 |
|
--- |
12062 |
|
--- |
| 12063 |
if (OpRHS.getOpcode() == CondRHS.getOpcode() && |
0 |
12063 |
if (OpRHS.getOpcode() == CondRHS.getOpcode() && |
0 |
| 12064 |
(OpRHS.getOpcode() == ISD::BUILD_VECTOR || |
0 |
12064 |
(OpRHS.getOpcode() == ISD::BUILD_VECTOR || |
0 |
| 12065 |
OpRHS.getOpcode() == ISD::SPLAT_VECTOR) && |
0 |
12065 |
OpRHS.getOpcode() == ISD::SPLAT_VECTOR) && |
0 |
| 12066 |
CondLHS == OpLHS) { |
0 |
12066 |
CondLHS == OpLHS) { |
0 |
| 12067 |
// If the RHS is a constant we have to reverse the const |
--- |
12067 |
// If the RHS is a constant we have to reverse the const |
--- |
| 12068 |
// canonicalization. |
--- |
12068 |
// canonicalization. |
--- |
| 12069 |
// x >= ~C ? x+C : ~0 --> uaddsat x, C |
--- |
12069 |
// x >= ~C ? x+C : ~0 --> uaddsat x, C |
--- |
| 12070 |
auto MatchUADDSAT = [](ConstantSDNode *Op, ConstantSDNode *Cond) { |
0 |
12070 |
auto MatchUADDSAT = [](ConstantSDNode *Op, ConstantSDNode *Cond) { |
0 |
| 12071 |
return Cond->getAPIntValue() == ~Op->getAPIntValue(); |
0 |
12071 |
return Cond->getAPIntValue() == ~Op->getAPIntValue(); |
0 |
| 12072 |
}; |
--- |
12072 |
}; |
--- |
| 12073 |
if (SatCC == ISD::SETULE && |
0 |
12073 |
if (SatCC == ISD::SETULE && |
0 |
| 12074 |
ISD::matchBinaryPredicate(OpRHS, CondRHS, MatchUADDSAT)) |
0 |
12074 |
ISD::matchBinaryPredicate(OpRHS, CondRHS, MatchUADDSAT)) |
0 |
| 12075 |
return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS); |
0 |
12075 |
return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS); |
0 |
| 12076 |
} |
--- |
12076 |
} |
--- |
| 12077 |
} |
--- |
12077 |
} |
--- |
| 12078 |
} |
--- |
12078 |
} |
--- |
| 12079 |
|
--- |
12079 |
|
--- |
| 12080 |
// Match VSELECTs into sub with unsigned saturation. |
--- |
12080 |
// Match VSELECTs into sub with unsigned saturation. |
--- |
| 12081 |
if (hasOperation(ISD::USUBSAT, VT)) { |
0 |
12081 |
if (hasOperation(ISD::USUBSAT, VT)) { |
0 |
| 12082 |
// Check if one of the arms of the VSELECT is a zero vector. If it's on |
--- |
12082 |
// Check if one of the arms of the VSELECT is a zero vector. If it's on |
--- |
| 12083 |
// the left side invert the predicate to simplify logic below. |
--- |
12083 |
// the left side invert the predicate to simplify logic below. |
--- |
| 12084 |
SDValue Other; |
0 |
12084 |
SDValue Other; |
0 |
| 12085 |
ISD::CondCode SatCC = CC; |
0 |
12085 |
ISD::CondCode SatCC = CC; |
0 |
| 12086 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) { |
0 |
12086 |
if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) { |
0 |
| 12087 |
Other = N2; |
0 |
12087 |
Other = N2; |
0 |
| 12088 |
SatCC = ISD::getSetCCInverse(SatCC, VT.getScalarType()); |
0 |
12088 |
SatCC = ISD::getSetCCInverse(SatCC, VT.getScalarType()); |
0 |
| 12089 |
} else if (ISD::isConstantSplatVectorAllZeros(N2.getNode())) { |
0 |
12089 |
} else if (ISD::isConstantSplatVectorAllZeros(N2.getNode())) { |
0 |
| 12090 |
Other = N1; |
0 |
12090 |
Other = N1; |
0 |
| 12091 |
} |
--- |
12091 |
} |
--- |
| 12092 |
|
--- |
12092 |
|
--- |
| 12093 |
// zext(x) >= y ? trunc(zext(x) - y) : 0 |
--- |
12093 |
// zext(x) >= y ? trunc(zext(x) - y) : 0 |
--- |
| 12094 |
// --> usubsat(trunc(zext(x)),trunc(umin(y,SatLimit))) |
--- |
12094 |
// --> usubsat(trunc(zext(x)),trunc(umin(y,SatLimit))) |
--- |
| 12095 |
// zext(x) > y ? trunc(zext(x) - y) : 0 |
--- |
12095 |
// zext(x) > y ? trunc(zext(x) - y) : 0 |
--- |
| 12096 |
// --> usubsat(trunc(zext(x)),trunc(umin(y,SatLimit))) |
--- |
12096 |
// --> usubsat(trunc(zext(x)),trunc(umin(y,SatLimit))) |
--- |
| 12097 |
if (Other && Other.getOpcode() == ISD::TRUNCATE && |
0 |
12097 |
if (Other && Other.getOpcode() == ISD::TRUNCATE && |
0 |
| 12098 |
Other.getOperand(0).getOpcode() == ISD::SUB && |
0 |
12098 |
Other.getOperand(0).getOpcode() == ISD::SUB && |
0 |
| 12099 |
(SatCC == ISD::SETUGE || SatCC == ISD::SETUGT)) { |
0 |
12099 |
(SatCC == ISD::SETUGE || SatCC == ISD::SETUGT)) { |
0 |
| 12100 |
SDValue OpLHS = Other.getOperand(0).getOperand(0); |
0 |
12100 |
SDValue OpLHS = Other.getOperand(0).getOperand(0); |
0 |
| 12101 |
SDValue OpRHS = Other.getOperand(0).getOperand(1); |
0 |
12101 |
SDValue OpRHS = Other.getOperand(0).getOperand(1); |
0 |
| 12102 |
if (LHS == OpLHS && RHS == OpRHS && LHS.getOpcode() == ISD::ZERO_EXTEND) |
0 |
12102 |
if (LHS == OpLHS && RHS == OpRHS && LHS.getOpcode() == ISD::ZERO_EXTEND) |
0 |
| 12103 |
if (SDValue R = getTruncatedUSUBSAT(VT, LHS.getValueType(), LHS, RHS, |
0 |
12103 |
if (SDValue R = getTruncatedUSUBSAT(VT, LHS.getValueType(), LHS, RHS, |
0 |
| 12104 |
DAG, DL)) |
0 |
12104 |
DAG, DL)) |
0 |
| 12105 |
return R; |
0 |
12105 |
return R; |
0 |
| 12106 |
} |
--- |
12106 |
} |
--- |
| 12107 |
|
--- |
12107 |
|
--- |
| 12108 |
if (Other && Other.getNumOperands() == 2) { |
0 |
12108 |
if (Other && Other.getNumOperands() == 2) { |
0 |
| 12109 |
SDValue CondRHS = RHS; |
0 |
12109 |
SDValue CondRHS = RHS; |
0 |
| 12110 |
SDValue OpLHS = Other.getOperand(0), OpRHS = Other.getOperand(1); |
0 |
12110 |
SDValue OpLHS = Other.getOperand(0), OpRHS = Other.getOperand(1); |
0 |
| 12111 |
|
--- |
12111 |
|
--- |
| 12112 |
if (OpLHS == LHS) { |
0 |
12112 |
if (OpLHS == LHS) { |
0 |
| 12113 |
// Look for a general sub with unsigned saturation first. |
--- |
12113 |
// Look for a general sub with unsigned saturation first. |
--- |
| 12114 |
// x >= y ? x-y : 0 --> usubsat x, y |
--- |
12114 |
// x >= y ? x-y : 0 --> usubsat x, y |
--- |
| 12115 |
// x > y ? x-y : 0 --> usubsat x, y |
--- |
12115 |
// x > y ? x-y : 0 --> usubsat x, y |
--- |
| 12116 |
if ((SatCC == ISD::SETUGE || SatCC == ISD::SETUGT) && |
0 |
12116 |
if ((SatCC == ISD::SETUGE || SatCC == ISD::SETUGT) && |
0 |
| 12117 |
Other.getOpcode() == ISD::SUB && OpRHS == CondRHS) |
0 |
12117 |
Other.getOpcode() == ISD::SUB && OpRHS == CondRHS) |
0 |
| 12118 |
return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS); |
0 |
12118 |
return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS); |
0 |
| 12119 |
|
--- |
12119 |
|
--- |
| 12120 |
if (OpRHS.getOpcode() == ISD::BUILD_VECTOR || |
0 |
12120 |
if (OpRHS.getOpcode() == ISD::BUILD_VECTOR || |
0 |
| 12121 |
OpRHS.getOpcode() == ISD::SPLAT_VECTOR) { |
0 |
12121 |
OpRHS.getOpcode() == ISD::SPLAT_VECTOR) { |
0 |
| 12122 |
if (CondRHS.getOpcode() == ISD::BUILD_VECTOR || |
0 |
12122 |
if (CondRHS.getOpcode() == ISD::BUILD_VECTOR || |
0 |
| 12123 |
CondRHS.getOpcode() == ISD::SPLAT_VECTOR) { |
0 |
12123 |
CondRHS.getOpcode() == ISD::SPLAT_VECTOR) { |
0 |
| 12124 |
// If the RHS is a constant we have to reverse the const |
--- |
12124 |
// If the RHS is a constant we have to reverse the const |
--- |
| 12125 |
// canonicalization. |
--- |
12125 |
// canonicalization. |
--- |
| 12126 |
// x > C-1 ? x+-C : 0 --> usubsat x, C |
--- |
12126 |
// x > C-1 ? x+-C : 0 --> usubsat x, C |
--- |
| 12127 |
auto MatchUSUBSAT = [](ConstantSDNode *Op, ConstantSDNode *Cond) { |
0 |
12127 |
auto MatchUSUBSAT = [](ConstantSDNode *Op, ConstantSDNode *Cond) { |
0 |
| 12128 |
return (!Op && !Cond) || |
0 |
12128 |
return (!Op && !Cond) || |
0 |
| 12129 |
(Op && Cond && |
0 |
12129 |
(Op && Cond && |
0 |
| 12130 |
Cond->getAPIntValue() == (-Op->getAPIntValue() - 1)); |
0 |
12130 |
Cond->getAPIntValue() == (-Op->getAPIntValue() - 1)); |
0 |
| 12131 |
}; |
--- |
12131 |
}; |
--- |
| 12132 |
if (SatCC == ISD::SETUGT && Other.getOpcode() == ISD::ADD && |
0 |
12132 |
if (SatCC == ISD::SETUGT && Other.getOpcode() == ISD::ADD && |
0 |
| 12133 |
ISD::matchBinaryPredicate(OpRHS, CondRHS, MatchUSUBSAT, |
0 |
12133 |
ISD::matchBinaryPredicate(OpRHS, CondRHS, MatchUSUBSAT, |
0 |
| 12134 |
/*AllowUndefs*/ true)) { |
--- |
12134 |
/*AllowUndefs*/ true)) { |
--- |
| 12135 |
OpRHS = DAG.getNegative(OpRHS, DL, VT); |
0 |
12135 |
OpRHS = DAG.getNegative(OpRHS, DL, VT); |
0 |
| 12136 |
return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS); |
0 |
12136 |
return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS); |
0 |
| 12137 |
} |
--- |
12137 |
} |
--- |
| 12138 |
|
--- |
12138 |
|
--- |
| 12139 |
// Another special case: If C was a sign bit, the sub has been |
--- |
12139 |
// Another special case: If C was a sign bit, the sub has been |
--- |
| 12140 |
// canonicalized into a xor. |
--- |
12140 |
// canonicalized into a xor. |
--- |
| 12141 |
// FIXME: Would it be better to use computeKnownBits to |
--- |
12141 |
// FIXME: Would it be better to use computeKnownBits to |
--- |
| 12142 |
// determine whether it's safe to decanonicalize the xor? |
--- |
12142 |
// determine whether it's safe to decanonicalize the xor? |
--- |
| 12143 |
// x s< 0 ? x^C : 0 --> usubsat x, C |
--- |
12143 |
// x s< 0 ? x^C : 0 --> usubsat x, C |
--- |
| 12144 |
APInt SplatValue; |
0 |
12144 |
APInt SplatValue; |
0 |
| 12145 |
if (SatCC == ISD::SETLT && Other.getOpcode() == ISD::XOR && |
0 |
12145 |
if (SatCC == ISD::SETLT && Other.getOpcode() == ISD::XOR && |
0 |
| 12146 |
ISD::isConstantSplatVector(OpRHS.getNode(), SplatValue) && |
0 |
12146 |
ISD::isConstantSplatVector(OpRHS.getNode(), SplatValue) && |
0 |
| 12147 |
ISD::isConstantSplatVectorAllZeros(CondRHS.getNode()) && |
0 |
12147 |
ISD::isConstantSplatVectorAllZeros(CondRHS.getNode()) && |
0 |
| 12148 |
SplatValue.isSignMask()) { |
0 |
12148 |
SplatValue.isSignMask()) { |
0 |
| 12149 |
// Note that we have to rebuild the RHS constant here to |
--- |
12149 |
// Note that we have to rebuild the RHS constant here to |
--- |
| 12150 |
// ensure we don't rely on particular values of undef lanes. |
--- |
12150 |
// ensure we don't rely on particular values of undef lanes. |
--- |
| 12151 |
OpRHS = DAG.getConstant(SplatValue, DL, VT); |
0 |
12151 |
OpRHS = DAG.getConstant(SplatValue, DL, VT); |
0 |
| 12152 |
return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS); |
0 |
12152 |
return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS); |
0 |
| 12153 |
} |
--- |
12153 |
} |
--- |
| 12154 |
} |
0 |
12154 |
} |
0 |
| 12155 |
} |
--- |
12155 |
} |
--- |
| 12156 |
} |
--- |
12156 |
} |
--- |
| 12157 |
} |
--- |
12157 |
} |
--- |
| 12158 |
} |
--- |
12158 |
} |
--- |
| 12159 |
} |
--- |
12159 |
} |
--- |
| 12160 |
|
--- |
12160 |
|
--- |
| 12161 |
if (SimplifySelectOps(N, N1, N2)) |
0 |
12161 |
if (SimplifySelectOps(N, N1, N2)) |
0 |
| 12162 |
return SDValue(N, 0); // Don't revisit N. |
0 |
12162 |
return SDValue(N, 0); // Don't revisit N. |
0 |
| 12163 |
|
--- |
12163 |
|
--- |
| 12164 |
// Fold (vselect all_ones, N1, N2) -> N1 |
--- |
12164 |
// Fold (vselect all_ones, N1, N2) -> N1 |
--- |
| 12165 |
if (ISD::isConstantSplatVectorAllOnes(N0.getNode())) |
0 |
12165 |
if (ISD::isConstantSplatVectorAllOnes(N0.getNode())) |
0 |
| 12166 |
return N1; |
0 |
12166 |
return N1; |
0 |
| 12167 |
// Fold (vselect all_zeros, N1, N2) -> N2 |
--- |
12167 |
// Fold (vselect all_zeros, N1, N2) -> N2 |
--- |
| 12168 |
if (ISD::isConstantSplatVectorAllZeros(N0.getNode())) |
0 |
12168 |
if (ISD::isConstantSplatVectorAllZeros(N0.getNode())) |
0 |
| 12169 |
return N2; |
0 |
12169 |
return N2; |
0 |
| 12170 |
|
--- |
12170 |
|
--- |
| 12171 |
// The ConvertSelectToConcatVector function is assuming both the above |
--- |
12171 |
// The ConvertSelectToConcatVector function is assuming both the above |
--- |
| 12172 |
// checks for (vselect (build_vector all{ones,zeros) ...) have been made |
--- |
12172 |
// checks for (vselect (build_vector all{ones,zeros) ...) have been made |
--- |
| 12173 |
// and addressed. |
--- |
12173 |
// and addressed. |
--- |
| 12174 |
if (N1.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
12174 |
if (N1.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
| 12175 |
N2.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
12175 |
N2.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
| 12176 |
ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) { |
0 |
12176 |
ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) { |
0 |
| 12177 |
if (SDValue CV = ConvertSelectToConcatVector(N, DAG)) |
0 |
12177 |
if (SDValue CV = ConvertSelectToConcatVector(N, DAG)) |
0 |
| 12178 |
return CV; |
0 |
12178 |
return CV; |
0 |
| 12179 |
} |
--- |
12179 |
} |
--- |
| 12180 |
|
--- |
12180 |
|
--- |
| 12181 |
if (SDValue V = foldVSelectOfConstants(N)) |
0 |
12181 |
if (SDValue V = foldVSelectOfConstants(N)) |
0 |
| 12182 |
return V; |
0 |
12182 |
return V; |
0 |
| 12183 |
|
--- |
12183 |
|
--- |
| 12184 |
if (hasOperation(ISD::SRA, VT)) |
0 |
12184 |
if (hasOperation(ISD::SRA, VT)) |
0 |
| 12185 |
if (SDValue V = foldVSelectToSignBitSplatMask(N, DAG)) |
0 |
12185 |
if (SDValue V = foldVSelectToSignBitSplatMask(N, DAG)) |
0 |
| 12186 |
return V; |
0 |
12186 |
return V; |
0 |
| 12187 |
|
--- |
12187 |
|
--- |
| 12188 |
if (SimplifyDemandedVectorElts(SDValue(N, 0))) |
0 |
12188 |
if (SimplifyDemandedVectorElts(SDValue(N, 0))) |
0 |
| 12189 |
return SDValue(N, 0); |
0 |
12189 |
return SDValue(N, 0); |
0 |
| 12190 |
|
--- |
12190 |
|
--- |
| 12191 |
return SDValue(); |
0 |
12191 |
return SDValue(); |
0 |
| 12192 |
} |
0 |
12192 |
} |
0 |
| 12193 |
|
--- |
12193 |
|
--- |
| 12194 |
SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { |
0 |
12194 |
SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { |
0 |
| 12195 |
SDValue N0 = N->getOperand(0); |
0 |
12195 |
SDValue N0 = N->getOperand(0); |
0 |
| 12196 |
SDValue N1 = N->getOperand(1); |
0 |
12196 |
SDValue N1 = N->getOperand(1); |
0 |
| 12197 |
SDValue N2 = N->getOperand(2); |
0 |
12197 |
SDValue N2 = N->getOperand(2); |
0 |
| 12198 |
SDValue N3 = N->getOperand(3); |
0 |
12198 |
SDValue N3 = N->getOperand(3); |
0 |
| 12199 |
SDValue N4 = N->getOperand(4); |
0 |
12199 |
SDValue N4 = N->getOperand(4); |
0 |
| 12200 |
ISD::CondCode CC = cast(N4)->get(); |
0 |
12200 |
ISD::CondCode CC = cast(N4)->get(); |
0 |
| 12201 |
|
--- |
12201 |
|
--- |
| 12202 |
// fold select_cc lhs, rhs, x, x, cc -> x |
--- |
12202 |
// fold select_cc lhs, rhs, x, x, cc -> x |
--- |
| 12203 |
if (N2 == N3) |
0 |
12203 |
if (N2 == N3) |
0 |
| 12204 |
return N2; |
0 |
12204 |
return N2; |
0 |
| 12205 |
|
--- |
12205 |
|
--- |
| 12206 |
// select_cc bool, 0, x, y, seteq -> select bool, y, x |
--- |
12206 |
// select_cc bool, 0, x, y, seteq -> select bool, y, x |
--- |
| 12207 |
if (CC == ISD::SETEQ && !LegalTypes && N0.getValueType() == MVT::i1 && |
0 |
12207 |
if (CC == ISD::SETEQ && !LegalTypes && N0.getValueType() == MVT::i1 && |
0 |
| 12208 |
isNullConstant(N1)) |
0 |
12208 |
isNullConstant(N1)) |
0 |
| 12209 |
return DAG.getSelect(SDLoc(N), N2.getValueType(), N0, N3, N2); |
0 |
12209 |
return DAG.getSelect(SDLoc(N), N2.getValueType(), N0, N3, N2); |
0 |
| 12210 |
|
--- |
12210 |
|
--- |
| 12211 |
// Determine if the condition we're dealing with is constant |
--- |
12211 |
// Determine if the condition we're dealing with is constant |
--- |
| 12212 |
if (SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()), N0, N1, |
0 |
12212 |
if (SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()), N0, N1, |
0 |
| 12213 |
CC, SDLoc(N), false)) { |
0 |
12213 |
CC, SDLoc(N), false)) { |
0 |
| 12214 |
AddToWorklist(SCC.getNode()); |
0 |
12214 |
AddToWorklist(SCC.getNode()); |
0 |
| 12215 |
|
--- |
12215 |
|
--- |
| 12216 |
// cond always true -> true val |
--- |
12216 |
// cond always true -> true val |
--- |
| 12217 |
// cond always false -> false val |
--- |
12217 |
// cond always false -> false val |
--- |
| 12218 |
if (auto *SCCC = dyn_cast(SCC.getNode())) |
0 |
12218 |
if (auto *SCCC = dyn_cast(SCC.getNode())) |
0 |
| 12219 |
return SCCC->isZero() ? N3 : N2; |
0 |
12219 |
return SCCC->isZero() ? N3 : N2; |
0 |
| 12220 |
|
--- |
12220 |
|
--- |
| 12221 |
// When the condition is UNDEF, just return the first operand. This is |
--- |
12221 |
// When the condition is UNDEF, just return the first operand. This is |
--- |
| 12222 |
// coherent the DAG creation, no setcc node is created in this case |
--- |
12222 |
// coherent the DAG creation, no setcc node is created in this case |
--- |
| 12223 |
if (SCC->isUndef()) |
0 |
12223 |
if (SCC->isUndef()) |
0 |
| 12224 |
return N2; |
0 |
12224 |
return N2; |
0 |
| 12225 |
|
--- |
12225 |
|
--- |
| 12226 |
// Fold to a simpler select_cc |
--- |
12226 |
// Fold to a simpler select_cc |
--- |
| 12227 |
if (SCC.getOpcode() == ISD::SETCC) { |
0 |
12227 |
if (SCC.getOpcode() == ISD::SETCC) { |
0 |
| 12228 |
SDValue SelectOp = DAG.getNode( |
0 |
12228 |
SDValue SelectOp = DAG.getNode( |
0 |
| 12229 |
ISD::SELECT_CC, SDLoc(N), N2.getValueType(), SCC.getOperand(0), |
0 |
12229 |
ISD::SELECT_CC, SDLoc(N), N2.getValueType(), SCC.getOperand(0), |
0 |
| 12230 |
SCC.getOperand(1), N2, N3, SCC.getOperand(2)); |
0 |
12230 |
SCC.getOperand(1), N2, N3, SCC.getOperand(2)); |
0 |
| 12231 |
SelectOp->setFlags(SCC->getFlags()); |
0 |
12231 |
SelectOp->setFlags(SCC->getFlags()); |
0 |
| 12232 |
return SelectOp; |
0 |
12232 |
return SelectOp; |
0 |
| 12233 |
} |
--- |
12233 |
} |
--- |
| 12234 |
} |
--- |
12234 |
} |
--- |
| 12235 |
|
--- |
12235 |
|
--- |
| 12236 |
// If we can fold this based on the true/false value, do so. |
--- |
12236 |
// If we can fold this based on the true/false value, do so. |
--- |
| 12237 |
if (SimplifySelectOps(N, N2, N3)) |
0 |
12237 |
if (SimplifySelectOps(N, N2, N3)) |
0 |
| 12238 |
return SDValue(N, 0); // Don't revisit N. |
0 |
12238 |
return SDValue(N, 0); // Don't revisit N. |
0 |
| 12239 |
|
--- |
12239 |
|
--- |
| 12240 |
// fold select_cc into other things, such as min/max/abs |
--- |
12240 |
// fold select_cc into other things, such as min/max/abs |
--- |
| 12241 |
return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC); |
0 |
12241 |
return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC); |
0 |
| 12242 |
} |
--- |
12242 |
} |
--- |
| 12243 |
|
--- |
12243 |
|
--- |
| 12244 |
SDValue DAGCombiner::visitSETCC(SDNode *N) { |
3 |
12244 |
SDValue DAGCombiner::visitSETCC(SDNode *N) { |
3 |
| 12245 |
// setcc is very commonly used as an argument to brcond. This pattern |
--- |
12245 |
// setcc is very commonly used as an argument to brcond. This pattern |
--- |
| 12246 |
// also lend itself to numerous combines and, as a result, it is desired |
--- |
12246 |
// also lend itself to numerous combines and, as a result, it is desired |
--- |
| 12247 |
// we keep the argument to a brcond as a setcc as much as possible. |
--- |
12247 |
// we keep the argument to a brcond as a setcc as much as possible. |
--- |
| 12248 |
bool PreferSetCC = |
--- |
12248 |
bool PreferSetCC = |
--- |
| 12249 |
N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND; |
3 |
12249 |
N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND; |
3 |
| 12250 |
|
--- |
12250 |
|
--- |
| 12251 |
ISD::CondCode Cond = cast(N->getOperand(2))->get(); |
3 |
12251 |
ISD::CondCode Cond = cast(N->getOperand(2))->get(); |
3 |
| 12252 |
EVT VT = N->getValueType(0); |
3 |
12252 |
EVT VT = N->getValueType(0); |
3 |
| 12253 |
|
--- |
12253 |
|
--- |
| 12254 |
SDValue Combined = SimplifySetCC(VT, N->getOperand(0), N->getOperand(1), Cond, |
3 |
12254 |
SDValue Combined = SimplifySetCC(VT, N->getOperand(0), N->getOperand(1), Cond, |
3 |
| 12255 |
SDLoc(N), !PreferSetCC); |
6 |
12255 |
SDLoc(N), !PreferSetCC); |
6 |
| 12256 |
|
--- |
12256 |
|
--- |
| 12257 |
if (!Combined) |
3 |
12257 |
if (!Combined) |
3 |
| 12258 |
return SDValue(); |
3 |
12258 |
return SDValue(); |
3 |
| 12259 |
|
--- |
12259 |
|
--- |
| 12260 |
// If we prefer to have a setcc, and we don't, we'll try our best to |
--- |
12260 |
// If we prefer to have a setcc, and we don't, we'll try our best to |
--- |
| 12261 |
// recreate one using rebuildSetCC. |
--- |
12261 |
// recreate one using rebuildSetCC. |
--- |
| 12262 |
if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) { |
0 |
12262 |
if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) { |
0 |
| 12263 |
SDValue NewSetCC = rebuildSetCC(Combined); |
0 |
12263 |
SDValue NewSetCC = rebuildSetCC(Combined); |
0 |
| 12264 |
|
--- |
12264 |
|
--- |
| 12265 |
// We don't have anything interesting to combine to. |
--- |
12265 |
// We don't have anything interesting to combine to. |
--- |
| 12266 |
if (NewSetCC.getNode() == N) |
0 |
12266 |
if (NewSetCC.getNode() == N) |
0 |
| 12267 |
return SDValue(); |
0 |
12267 |
return SDValue(); |
0 |
| 12268 |
|
--- |
12268 |
|
--- |
| 12269 |
if (NewSetCC) |
0 |
12269 |
if (NewSetCC) |
0 |
| 12270 |
return NewSetCC; |
0 |
12270 |
return NewSetCC; |
0 |
| 12271 |
} |
--- |
12271 |
} |
--- |
| 12272 |
|
--- |
12272 |
|
--- |
| 12273 |
return Combined; |
0 |
12273 |
return Combined; |
0 |
| 12274 |
} |
--- |
12274 |
} |
--- |
| 12275 |
|
--- |
12275 |
|
--- |
| 12276 |
SDValue DAGCombiner::visitSETCCCARRY(SDNode *N) { |
0 |
12276 |
SDValue DAGCombiner::visitSETCCCARRY(SDNode *N) { |
0 |
| 12277 |
SDValue LHS = N->getOperand(0); |
0 |
12277 |
SDValue LHS = N->getOperand(0); |
0 |
| 12278 |
SDValue RHS = N->getOperand(1); |
0 |
12278 |
SDValue RHS = N->getOperand(1); |
0 |
| 12279 |
SDValue Carry = N->getOperand(2); |
0 |
12279 |
SDValue Carry = N->getOperand(2); |
0 |
| 12280 |
SDValue Cond = N->getOperand(3); |
0 |
12280 |
SDValue Cond = N->getOperand(3); |
0 |
| 12281 |
|
--- |
12281 |
|
--- |
| 12282 |
// If Carry is false, fold to a regular SETCC. |
--- |
12282 |
// If Carry is false, fold to a regular SETCC. |
--- |
| 12283 |
if (isNullConstant(Carry)) |
0 |
12283 |
if (isNullConstant(Carry)) |
0 |
| 12284 |
return DAG.getNode(ISD::SETCC, SDLoc(N), N->getVTList(), LHS, RHS, Cond); |
0 |
12284 |
return DAG.getNode(ISD::SETCC, SDLoc(N), N->getVTList(), LHS, RHS, Cond); |
0 |
| 12285 |
|
--- |
12285 |
|
--- |
| 12286 |
return SDValue(); |
0 |
12286 |
return SDValue(); |
0 |
| 12287 |
} |
--- |
12287 |
} |
--- |
| 12288 |
|
--- |
12288 |
|
--- |
| 12289 |
/// Check if N satisfies: |
--- |
12289 |
/// Check if N satisfies: |
--- |
| 12290 |
/// N is used once. |
--- |
12290 |
/// N is used once. |
--- |
| 12291 |
/// N is a Load. |
--- |
12291 |
/// N is a Load. |
--- |
| 12292 |
/// The load is compatible with ExtOpcode. It means |
--- |
12292 |
/// The load is compatible with ExtOpcode. It means |
--- |
| 12293 |
/// If load has explicit zero/sign extension, ExpOpcode must have the same |
--- |
12293 |
/// If load has explicit zero/sign extension, ExpOpcode must have the same |
--- |
| 12294 |
/// extension. |
--- |
12294 |
/// extension. |
--- |
| 12295 |
/// Otherwise returns true. |
--- |
12295 |
/// Otherwise returns true. |
--- |
| 12296 |
static bool isCompatibleLoad(SDValue N, unsigned ExtOpcode) { |
0 |
12296 |
static bool isCompatibleLoad(SDValue N, unsigned ExtOpcode) { |
0 |
| 12297 |
if (!N.hasOneUse()) |
0 |
12297 |
if (!N.hasOneUse()) |
0 |
| 12298 |
return false; |
0 |
12298 |
return false; |
0 |
| 12299 |
|
--- |
12299 |
|
--- |
| 12300 |
if (!isa(N)) |
0 |
12300 |
if (!isa(N)) |
0 |
| 12301 |
return false; |
0 |
12301 |
return false; |
0 |
| 12302 |
|
--- |
12302 |
|
--- |
| 12303 |
LoadSDNode *Load = cast(N); |
0 |
12303 |
LoadSDNode *Load = cast(N); |
0 |
| 12304 |
ISD::LoadExtType LoadExt = Load->getExtensionType(); |
0 |
12304 |
ISD::LoadExtType LoadExt = Load->getExtensionType(); |
0 |
| 12305 |
if (LoadExt == ISD::NON_EXTLOAD || LoadExt == ISD::EXTLOAD) |
0 |
12305 |
if (LoadExt == ISD::NON_EXTLOAD || LoadExt == ISD::EXTLOAD) |
0 |
| 12306 |
return true; |
0 |
12306 |
return true; |
0 |
| 12307 |
|
--- |
12307 |
|
--- |
| 12308 |
// Now LoadExt is either SEXTLOAD or ZEXTLOAD, ExtOpcode must have the same |
--- |
12308 |
// Now LoadExt is either SEXTLOAD or ZEXTLOAD, ExtOpcode must have the same |
--- |
| 12309 |
// extension. |
--- |
12309 |
// extension. |
--- |
| 12310 |
if ((LoadExt == ISD::SEXTLOAD && ExtOpcode != ISD::SIGN_EXTEND) || |
0 |
12310 |
if ((LoadExt == ISD::SEXTLOAD && ExtOpcode != ISD::SIGN_EXTEND) || |
0 |
| 12311 |
(LoadExt == ISD::ZEXTLOAD && ExtOpcode != ISD::ZERO_EXTEND)) |
0 |
12311 |
(LoadExt == ISD::ZEXTLOAD && ExtOpcode != ISD::ZERO_EXTEND)) |
0 |
| 12312 |
return false; |
0 |
12312 |
return false; |
0 |
| 12313 |
|
--- |
12313 |
|
--- |
| 12314 |
return true; |
0 |
12314 |
return true; |
0 |
| 12315 |
} |
--- |
12315 |
} |
--- |
| 12316 |
|
--- |
12316 |
|
--- |
| 12317 |
/// Fold |
--- |
12317 |
/// Fold |
--- |
| 12318 |
/// (sext (select c, load x, load y)) -> (select c, sextload x, sextload y) |
--- |
12318 |
/// (sext (select c, load x, load y)) -> (select c, sextload x, sextload y) |
--- |
| 12319 |
/// (zext (select c, load x, load y)) -> (select c, zextload x, zextload y) |
--- |
12319 |
/// (zext (select c, load x, load y)) -> (select c, zextload x, zextload y) |
--- |
| 12320 |
/// (aext (select c, load x, load y)) -> (select c, extload x, extload y) |
--- |
12320 |
/// (aext (select c, load x, load y)) -> (select c, extload x, extload y) |
--- |
| 12321 |
/// This function is called by the DAGCombiner when visiting sext/zext/aext |
--- |
12321 |
/// This function is called by the DAGCombiner when visiting sext/zext/aext |
--- |
| 12322 |
/// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). |
--- |
12322 |
/// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). |
--- |
| 12323 |
static SDValue tryToFoldExtendSelectLoad(SDNode *N, const TargetLowering &TLI, |
0 |
12323 |
static SDValue tryToFoldExtendSelectLoad(SDNode *N, const TargetLowering &TLI, |
0 |
| 12324 |
SelectionDAG &DAG, |
--- |
12324 |
SelectionDAG &DAG, |
--- |
| 12325 |
CombineLevel Level) { |
--- |
12325 |
CombineLevel Level) { |
--- |
| 12326 |
unsigned Opcode = N->getOpcode(); |
0 |
12326 |
unsigned Opcode = N->getOpcode(); |
0 |
| 12327 |
SDValue N0 = N->getOperand(0); |
0 |
12327 |
SDValue N0 = N->getOperand(0); |
0 |
| 12328 |
EVT VT = N->getValueType(0); |
0 |
12328 |
EVT VT = N->getValueType(0); |
0 |
| 12329 |
SDLoc DL(N); |
0 |
12329 |
SDLoc DL(N); |
0 |
| 12330 |
|
--- |
12330 |
|
--- |
| 12331 |
assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND || |
0 |
12331 |
assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND || |
0 |
| 12332 |
Opcode == ISD::ANY_EXTEND) && |
--- |
12332 |
Opcode == ISD::ANY_EXTEND) && |
--- |
| 12333 |
"Expected EXTEND dag node in input!"); |
--- |
12333 |
"Expected EXTEND dag node in input!"); |
--- |
| 12334 |
|
--- |
12334 |
|
--- |
| 12335 |
if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) || |
0 |
12335 |
if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) || |
0 |
| 12336 |
!N0.hasOneUse()) |
0 |
12336 |
!N0.hasOneUse()) |
0 |
| 12337 |
return SDValue(); |
0 |
12337 |
return SDValue(); |
0 |
| 12338 |
|
--- |
12338 |
|
--- |
| 12339 |
SDValue Op1 = N0->getOperand(1); |
0 |
12339 |
SDValue Op1 = N0->getOperand(1); |
0 |
| 12340 |
SDValue Op2 = N0->getOperand(2); |
0 |
12340 |
SDValue Op2 = N0->getOperand(2); |
0 |
| 12341 |
if (!isCompatibleLoad(Op1, Opcode) || !isCompatibleLoad(Op2, Opcode)) |
0 |
12341 |
if (!isCompatibleLoad(Op1, Opcode) || !isCompatibleLoad(Op2, Opcode)) |
0 |
| 12342 |
return SDValue(); |
0 |
12342 |
return SDValue(); |
0 |
| 12343 |
|
--- |
12343 |
|
--- |
| 12344 |
auto ExtLoadOpcode = ISD::EXTLOAD; |
0 |
12344 |
auto ExtLoadOpcode = ISD::EXTLOAD; |
0 |
| 12345 |
if (Opcode == ISD::SIGN_EXTEND) |
0 |
12345 |
if (Opcode == ISD::SIGN_EXTEND) |
0 |
| 12346 |
ExtLoadOpcode = ISD::SEXTLOAD; |
0 |
12346 |
ExtLoadOpcode = ISD::SEXTLOAD; |
0 |
| 12347 |
else if (Opcode == ISD::ZERO_EXTEND) |
0 |
12347 |
else if (Opcode == ISD::ZERO_EXTEND) |
0 |
| 12348 |
ExtLoadOpcode = ISD::ZEXTLOAD; |
0 |
12348 |
ExtLoadOpcode = ISD::ZEXTLOAD; |
0 |
| 12349 |
|
--- |
12349 |
|
--- |
| 12350 |
// Illegal VSELECT may ISel fail if happen after legalization (DAG |
--- |
12350 |
// Illegal VSELECT may ISel fail if happen after legalization (DAG |
--- |
| 12351 |
// Combine2), so we should conservatively check the OperationAction. |
--- |
12351 |
// Combine2), so we should conservatively check the OperationAction. |
--- |
| 12352 |
LoadSDNode *Load1 = cast(Op1); |
0 |
12352 |
LoadSDNode *Load1 = cast(Op1); |
0 |
| 12353 |
LoadSDNode *Load2 = cast(Op2); |
0 |
12353 |
LoadSDNode *Load2 = cast(Op2); |
0 |
| 12354 |
if (!TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load1->getMemoryVT()) || |
0 |
12354 |
if (!TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load1->getMemoryVT()) || |
0 |
| 12355 |
!TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load2->getMemoryVT()) || |
0 |
12355 |
!TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load2->getMemoryVT()) || |
0 |
| 12356 |
(N0->getOpcode() == ISD::VSELECT && Level >= AfterLegalizeTypes && |
0 |
12356 |
(N0->getOpcode() == ISD::VSELECT && Level >= AfterLegalizeTypes && |
0 |
| 12357 |
TLI.getOperationAction(ISD::VSELECT, VT) != TargetLowering::Legal)) |
0 |
12357 |
TLI.getOperationAction(ISD::VSELECT, VT) != TargetLowering::Legal)) |
0 |
| 12358 |
return SDValue(); |
0 |
12358 |
return SDValue(); |
0 |
| 12359 |
|
--- |
12359 |
|
--- |
| 12360 |
SDValue Ext1 = DAG.getNode(Opcode, DL, VT, Op1); |
0 |
12360 |
SDValue Ext1 = DAG.getNode(Opcode, DL, VT, Op1); |
0 |
| 12361 |
SDValue Ext2 = DAG.getNode(Opcode, DL, VT, Op2); |
0 |
12361 |
SDValue Ext2 = DAG.getNode(Opcode, DL, VT, Op2); |
0 |
| 12362 |
return DAG.getSelect(DL, VT, N0->getOperand(0), Ext1, Ext2); |
0 |
12362 |
return DAG.getSelect(DL, VT, N0->getOperand(0), Ext1, Ext2); |
0 |
| 12363 |
} |
0 |
12363 |
} |
0 |
| 12364 |
|
--- |
12364 |
|
--- |
| 12365 |
/// Try to fold a sext/zext/aext dag node into a ConstantSDNode or |
--- |
12365 |
/// Try to fold a sext/zext/aext dag node into a ConstantSDNode or |
--- |
| 12366 |
/// a build_vector of constants. |
--- |
12366 |
/// a build_vector of constants. |
--- |
| 12367 |
/// This function is called by the DAGCombiner when visiting sext/zext/aext |
--- |
12367 |
/// This function is called by the DAGCombiner when visiting sext/zext/aext |
--- |
| 12368 |
/// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). |
--- |
12368 |
/// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). |
--- |
| 12369 |
/// Vector extends are not folded if operations are legal; this is to |
--- |
12369 |
/// Vector extends are not folded if operations are legal; this is to |
--- |
| 12370 |
/// avoid introducing illegal build_vector dag nodes. |
--- |
12370 |
/// avoid introducing illegal build_vector dag nodes. |
--- |
| 12371 |
static SDValue tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI, |
0 |
12371 |
static SDValue tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI, |
0 |
| 12372 |
SelectionDAG &DAG, bool LegalTypes) { |
--- |
12372 |
SelectionDAG &DAG, bool LegalTypes) { |
--- |
| 12373 |
unsigned Opcode = N->getOpcode(); |
0 |
12373 |
unsigned Opcode = N->getOpcode(); |
0 |
| 12374 |
SDValue N0 = N->getOperand(0); |
0 |
12374 |
SDValue N0 = N->getOperand(0); |
0 |
| 12375 |
EVT VT = N->getValueType(0); |
0 |
12375 |
EVT VT = N->getValueType(0); |
0 |
| 12376 |
SDLoc DL(N); |
0 |
12376 |
SDLoc DL(N); |
0 |
| 12377 |
|
--- |
12377 |
|
--- |
| 12378 |
assert((ISD::isExtOpcode(Opcode) || ISD::isExtVecInRegOpcode(Opcode)) && |
0 |
12378 |
assert((ISD::isExtOpcode(Opcode) || ISD::isExtVecInRegOpcode(Opcode)) && |
0 |
| 12379 |
"Expected EXTEND dag node in input!"); |
--- |
12379 |
"Expected EXTEND dag node in input!"); |
--- |
| 12380 |
|
--- |
12380 |
|
--- |
| 12381 |
// fold (sext c1) -> c1 |
--- |
12381 |
// fold (sext c1) -> c1 |
--- |
| 12382 |
// fold (zext c1) -> c1 |
--- |
12382 |
// fold (zext c1) -> c1 |
--- |
| 12383 |
// fold (aext c1) -> c1 |
--- |
12383 |
// fold (aext c1) -> c1 |
--- |
| 12384 |
if (isa(N0)) |
0 |
12384 |
if (isa(N0)) |
0 |
| 12385 |
return DAG.getNode(Opcode, DL, VT, N0); |
0 |
12385 |
return DAG.getNode(Opcode, DL, VT, N0); |
0 |
| 12386 |
|
--- |
12386 |
|
--- |
| 12387 |
// fold (sext (select cond, c1, c2)) -> (select cond, sext c1, sext c2) |
--- |
12387 |
// fold (sext (select cond, c1, c2)) -> (select cond, sext c1, sext c2) |
--- |
| 12388 |
// fold (zext (select cond, c1, c2)) -> (select cond, zext c1, zext c2) |
--- |
12388 |
// fold (zext (select cond, c1, c2)) -> (select cond, zext c1, zext c2) |
--- |
| 12389 |
// fold (aext (select cond, c1, c2)) -> (select cond, sext c1, sext c2) |
--- |
12389 |
// fold (aext (select cond, c1, c2)) -> (select cond, sext c1, sext c2) |
--- |
| 12390 |
if (N0->getOpcode() == ISD::SELECT) { |
0 |
12390 |
if (N0->getOpcode() == ISD::SELECT) { |
0 |
| 12391 |
SDValue Op1 = N0->getOperand(1); |
0 |
12391 |
SDValue Op1 = N0->getOperand(1); |
0 |
| 12392 |
SDValue Op2 = N0->getOperand(2); |
0 |
12392 |
SDValue Op2 = N0->getOperand(2); |
0 |
| 12393 |
if (isa(Op1) && isa(Op2) && |
0 |
12393 |
if (isa(Op1) && isa(Op2) && |
0 |
| 12394 |
(Opcode != ISD::ZERO_EXTEND || !TLI.isZExtFree(N0.getValueType(), VT))) { |
0 |
12394 |
(Opcode != ISD::ZERO_EXTEND || !TLI.isZExtFree(N0.getValueType(), VT))) { |
0 |
| 12395 |
// For any_extend, choose sign extension of the constants to allow a |
--- |
12395 |
// For any_extend, choose sign extension of the constants to allow a |
--- |
| 12396 |
// possible further transform to sign_extend_inreg.i.e. |
--- |
12396 |
// possible further transform to sign_extend_inreg.i.e. |
--- |
| 12397 |
// |
--- |
12397 |
// |
--- |
| 12398 |
// t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0> |
--- |
12398 |
// t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0> |
--- |
| 12399 |
// t2: i64 = any_extend t1 |
--- |
12399 |
// t2: i64 = any_extend t1 |
--- |
| 12400 |
// --> |
--- |
12400 |
// --> |
--- |
| 12401 |
// t3: i64 = select t0, Constant:i64<-1>, Constant:i64<0> |
--- |
12401 |
// t3: i64 = select t0, Constant:i64<-1>, Constant:i64<0> |
--- |
| 12402 |
// --> |
--- |
12402 |
// --> |
--- |
| 12403 |
// t4: i64 = sign_extend_inreg t3 |
--- |
12403 |
// t4: i64 = sign_extend_inreg t3 |
--- |
| 12404 |
unsigned FoldOpc = Opcode; |
0 |
12404 |
unsigned FoldOpc = Opcode; |
0 |
| 12405 |
if (FoldOpc == ISD::ANY_EXTEND) |
0 |
12405 |
if (FoldOpc == ISD::ANY_EXTEND) |
0 |
| 12406 |
FoldOpc = ISD::SIGN_EXTEND; |
0 |
12406 |
FoldOpc = ISD::SIGN_EXTEND; |
0 |
| 12407 |
return DAG.getSelect(DL, VT, N0->getOperand(0), |
0 |
12407 |
return DAG.getSelect(DL, VT, N0->getOperand(0), |
0 |
| 12408 |
DAG.getNode(FoldOpc, DL, VT, Op1), |
--- |
12408 |
DAG.getNode(FoldOpc, DL, VT, Op1), |
--- |
| 12409 |
DAG.getNode(FoldOpc, DL, VT, Op2)); |
0 |
12409 |
DAG.getNode(FoldOpc, DL, VT, Op2)); |
0 |
| 12410 |
} |
--- |
12410 |
} |
--- |
| 12411 |
} |
--- |
12411 |
} |
--- |
| 12412 |
|
--- |
12412 |
|
--- |
| 12413 |
// fold (sext (build_vector AllConstants) -> (build_vector AllConstants) |
--- |
12413 |
// fold (sext (build_vector AllConstants) -> (build_vector AllConstants) |
--- |
| 12414 |
// fold (zext (build_vector AllConstants) -> (build_vector AllConstants) |
--- |
12414 |
// fold (zext (build_vector AllConstants) -> (build_vector AllConstants) |
--- |
| 12415 |
// fold (aext (build_vector AllConstants) -> (build_vector AllConstants) |
--- |
12415 |
// fold (aext (build_vector AllConstants) -> (build_vector AllConstants) |
--- |
| 12416 |
EVT SVT = VT.getScalarType(); |
0 |
12416 |
EVT SVT = VT.getScalarType(); |
0 |
| 12417 |
if (!(VT.isVector() && (!LegalTypes || TLI.isTypeLegal(SVT)) && |
0 |
12417 |
if (!(VT.isVector() && (!LegalTypes || TLI.isTypeLegal(SVT)) && |
0 |
| 12418 |
ISD::isBuildVectorOfConstantSDNodes(N0.getNode()))) |
0 |
12418 |
ISD::isBuildVectorOfConstantSDNodes(N0.getNode()))) |
0 |
| 12419 |
return SDValue(); |
0 |
12419 |
return SDValue(); |
0 |
| 12420 |
|
--- |
12420 |
|
--- |
| 12421 |
// We can fold this node into a build_vector. |
--- |
12421 |
// We can fold this node into a build_vector. |
--- |
| 12422 |
unsigned VTBits = SVT.getSizeInBits(); |
0 |
12422 |
unsigned VTBits = SVT.getSizeInBits(); |
0 |
| 12423 |
unsigned EVTBits = N0->getValueType(0).getScalarSizeInBits(); |
0 |
12423 |
unsigned EVTBits = N0->getValueType(0).getScalarSizeInBits(); |
0 |
| 12424 |
SmallVector Elts; |
0 |
12424 |
SmallVector Elts; |
0 |
| 12425 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
12425 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
| 12426 |
|
--- |
12426 |
|
--- |
| 12427 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
12427 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
| 12428 |
SDValue Op = N0.getOperand(i); |
0 |
12428 |
SDValue Op = N0.getOperand(i); |
0 |
| 12429 |
if (Op.isUndef()) { |
0 |
12429 |
if (Op.isUndef()) { |
0 |
| 12430 |
if (Opcode == ISD::ANY_EXTEND || Opcode == ISD::ANY_EXTEND_VECTOR_INREG) |
0 |
12430 |
if (Opcode == ISD::ANY_EXTEND || Opcode == ISD::ANY_EXTEND_VECTOR_INREG) |
0 |
| 12431 |
Elts.push_back(DAG.getUNDEF(SVT)); |
0 |
12431 |
Elts.push_back(DAG.getUNDEF(SVT)); |
0 |
| 12432 |
else |
--- |
12432 |
else |
--- |
| 12433 |
Elts.push_back(DAG.getConstant(0, DL, SVT)); |
0 |
12433 |
Elts.push_back(DAG.getConstant(0, DL, SVT)); |
0 |
| 12434 |
continue; |
0 |
12434 |
continue; |
0 |
| 12435 |
} |
--- |
12435 |
} |
--- |
| 12436 |
|
--- |
12436 |
|
--- |
| 12437 |
SDLoc DL(Op); |
0 |
12437 |
SDLoc DL(Op); |
0 |
| 12438 |
// Get the constant value and if needed trunc it to the size of the type. |
--- |
12438 |
// Get the constant value and if needed trunc it to the size of the type. |
--- |
| 12439 |
// Nodes like build_vector might have constants wider than the scalar type. |
--- |
12439 |
// Nodes like build_vector might have constants wider than the scalar type. |
--- |
| 12440 |
APInt C = cast(Op)->getAPIntValue().zextOrTrunc(EVTBits); |
0 |
12440 |
APInt C = cast(Op)->getAPIntValue().zextOrTrunc(EVTBits); |
0 |
| 12441 |
if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) |
0 |
12441 |
if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) |
0 |
| 12442 |
Elts.push_back(DAG.getConstant(C.sext(VTBits), DL, SVT)); |
0 |
12442 |
Elts.push_back(DAG.getConstant(C.sext(VTBits), DL, SVT)); |
0 |
| 12443 |
else |
--- |
12443 |
else |
--- |
| 12444 |
Elts.push_back(DAG.getConstant(C.zext(VTBits), DL, SVT)); |
0 |
12444 |
Elts.push_back(DAG.getConstant(C.zext(VTBits), DL, SVT)); |
0 |
| 12445 |
} |
0 |
12445 |
} |
0 |
| 12446 |
|
--- |
12446 |
|
--- |
| 12447 |
return DAG.getBuildVector(VT, DL, Elts); |
0 |
12447 |
return DAG.getBuildVector(VT, DL, Elts); |
0 |
| 12448 |
} |
0 |
12448 |
} |
0 |
| 12449 |
|
--- |
12449 |
|
--- |
| 12450 |
// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: |
--- |
12450 |
// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: |
--- |
| 12451 |
// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" |
--- |
12451 |
// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" |
--- |
| 12452 |
// transformation. Returns true if extension are possible and the above |
--- |
12452 |
// transformation. Returns true if extension are possible and the above |
--- |
| 12453 |
// mentioned transformation is profitable. |
--- |
12453 |
// mentioned transformation is profitable. |
--- |
| 12454 |
static bool ExtendUsesToFormExtLoad(EVT VT, SDNode *N, SDValue N0, |
0 |
12454 |
static bool ExtendUsesToFormExtLoad(EVT VT, SDNode *N, SDValue N0, |
0 |
| 12455 |
unsigned ExtOpc, |
--- |
12455 |
unsigned ExtOpc, |
--- |
| 12456 |
SmallVectorImpl &ExtendNodes, |
--- |
12456 |
SmallVectorImpl &ExtendNodes, |
--- |
| 12457 |
const TargetLowering &TLI) { |
--- |
12457 |
const TargetLowering &TLI) { |
--- |
| 12458 |
bool HasCopyToRegUses = false; |
0 |
12458 |
bool HasCopyToRegUses = false; |
0 |
| 12459 |
bool isTruncFree = TLI.isTruncateFree(VT, N0.getValueType()); |
0 |
12459 |
bool isTruncFree = TLI.isTruncateFree(VT, N0.getValueType()); |
0 |
| 12460 |
for (SDNode::use_iterator UI = N0->use_begin(), UE = N0->use_end(); UI != UE; |
0 |
12460 |
for (SDNode::use_iterator UI = N0->use_begin(), UE = N0->use_end(); UI != UE; |
0 |
| 12461 |
++UI) { |
0 |
12461 |
++UI) { |
0 |
| 12462 |
SDNode *User = *UI; |
0 |
12462 |
SDNode *User = *UI; |
0 |
| 12463 |
if (User == N) |
0 |
12463 |
if (User == N) |
0 |
| 12464 |
continue; |
0 |
12464 |
continue; |
0 |
| 12465 |
if (UI.getUse().getResNo() != N0.getResNo()) |
0 |
12465 |
if (UI.getUse().getResNo() != N0.getResNo()) |
0 |
| 12466 |
continue; |
0 |
12466 |
continue; |
0 |
| 12467 |
// FIXME: Only extend SETCC N, N and SETCC N, c for now. |
--- |
12467 |
// FIXME: Only extend SETCC N, N and SETCC N, c for now. |
--- |
| 12468 |
if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { |
0 |
12468 |
if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { |
0 |
| 12469 |
ISD::CondCode CC = cast(User->getOperand(2))->get(); |
0 |
12469 |
ISD::CondCode CC = cast(User->getOperand(2))->get(); |
0 |
| 12470 |
if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) |
0 |
12470 |
if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) |
0 |
| 12471 |
// Sign bits will be lost after a zext. |
--- |
12471 |
// Sign bits will be lost after a zext. |
--- |
| 12472 |
return false; |
0 |
12472 |
return false; |
0 |
| 12473 |
bool Add = false; |
0 |
12473 |
bool Add = false; |
0 |
| 12474 |
for (unsigned i = 0; i != 2; ++i) { |
0 |
12474 |
for (unsigned i = 0; i != 2; ++i) { |
0 |
| 12475 |
SDValue UseOp = User->getOperand(i); |
0 |
12475 |
SDValue UseOp = User->getOperand(i); |
0 |
| 12476 |
if (UseOp == N0) |
0 |
12476 |
if (UseOp == N0) |
0 |
| 12477 |
continue; |
0 |
12477 |
continue; |
0 |
| 12478 |
if (!isa(UseOp)) |
0 |
12478 |
if (!isa(UseOp)) |
0 |
| 12479 |
return false; |
0 |
12479 |
return false; |
0 |
| 12480 |
Add = true; |
0 |
12480 |
Add = true; |
0 |
| 12481 |
} |
--- |
12481 |
} |
--- |
| 12482 |
if (Add) |
0 |
12482 |
if (Add) |
0 |
| 12483 |
ExtendNodes.push_back(User); |
0 |
12483 |
ExtendNodes.push_back(User); |
0 |
| 12484 |
continue; |
0 |
12484 |
continue; |
0 |
| 12485 |
} |
0 |
12485 |
} |
0 |
| 12486 |
// If truncates aren't free and there are users we can't |
--- |
12486 |
// If truncates aren't free and there are users we can't |
--- |
| 12487 |
// extend, it isn't worthwhile. |
--- |
12487 |
// extend, it isn't worthwhile. |
--- |
| 12488 |
if (!isTruncFree) |
0 |
12488 |
if (!isTruncFree) |
0 |
| 12489 |
return false; |
0 |
12489 |
return false; |
0 |
| 12490 |
// Remember if this value is live-out. |
--- |
12490 |
// Remember if this value is live-out. |
--- |
| 12491 |
if (User->getOpcode() == ISD::CopyToReg) |
0 |
12491 |
if (User->getOpcode() == ISD::CopyToReg) |
0 |
| 12492 |
HasCopyToRegUses = true; |
0 |
12492 |
HasCopyToRegUses = true; |
0 |
| 12493 |
} |
--- |
12493 |
} |
--- |
| 12494 |
|
--- |
12494 |
|
--- |
| 12495 |
if (HasCopyToRegUses) { |
0 |
12495 |
if (HasCopyToRegUses) { |
0 |
| 12496 |
bool BothLiveOut = false; |
0 |
12496 |
bool BothLiveOut = false; |
0 |
| 12497 |
for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); |
0 |
12497 |
for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); |
0 |
| 12498 |
UI != UE; ++UI) { |
0 |
12498 |
UI != UE; ++UI) { |
0 |
| 12499 |
SDUse &Use = UI.getUse(); |
0 |
12499 |
SDUse &Use = UI.getUse(); |
0 |
| 12500 |
if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { |
0 |
12500 |
if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { |
0 |
| 12501 |
BothLiveOut = true; |
0 |
12501 |
BothLiveOut = true; |
0 |
| 12502 |
break; |
0 |
12502 |
break; |
0 |
| 12503 |
} |
--- |
12503 |
} |
--- |
| 12504 |
} |
--- |
12504 |
} |
--- |
| 12505 |
if (BothLiveOut) |
0 |
12505 |
if (BothLiveOut) |
0 |
| 12506 |
// Both unextended and extended values are live out. There had better be |
--- |
12506 |
// Both unextended and extended values are live out. There had better be |
--- |
| 12507 |
// a good reason for the transformation. |
--- |
12507 |
// a good reason for the transformation. |
--- |
| 12508 |
return ExtendNodes.size(); |
0 |
12508 |
return ExtendNodes.size(); |
0 |
| 12509 |
} |
--- |
12509 |
} |
--- |
| 12510 |
return true; |
0 |
12510 |
return true; |
0 |
| 12511 |
} |
--- |
12511 |
} |
--- |
| 12512 |
|
--- |
12512 |
|
--- |
| 12513 |
void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl &SetCCs, |
0 |
12513 |
void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl &SetCCs, |
0 |
| 12514 |
SDValue OrigLoad, SDValue ExtLoad, |
--- |
12514 |
SDValue OrigLoad, SDValue ExtLoad, |
--- |
| 12515 |
ISD::NodeType ExtType) { |
--- |
12515 |
ISD::NodeType ExtType) { |
--- |
| 12516 |
// Extend SetCC uses if necessary. |
--- |
12516 |
// Extend SetCC uses if necessary. |
--- |
| 12517 |
SDLoc DL(ExtLoad); |
0 |
12517 |
SDLoc DL(ExtLoad); |
0 |
| 12518 |
for (SDNode *SetCC : SetCCs) { |
0 |
12518 |
for (SDNode *SetCC : SetCCs) { |
0 |
| 12519 |
SmallVector Ops; |
0 |
12519 |
SmallVector Ops; |
0 |
| 12520 |
|
--- |
12520 |
|
--- |
| 12521 |
for (unsigned j = 0; j != 2; ++j) { |
0 |
12521 |
for (unsigned j = 0; j != 2; ++j) { |
0 |
| 12522 |
SDValue SOp = SetCC->getOperand(j); |
0 |
12522 |
SDValue SOp = SetCC->getOperand(j); |
0 |
| 12523 |
if (SOp == OrigLoad) |
0 |
12523 |
if (SOp == OrigLoad) |
0 |
| 12524 |
Ops.push_back(ExtLoad); |
0 |
12524 |
Ops.push_back(ExtLoad); |
0 |
| 12525 |
else |
--- |
12525 |
else |
--- |
| 12526 |
Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); |
0 |
12526 |
Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); |
0 |
| 12527 |
} |
--- |
12527 |
} |
--- |
| 12528 |
|
--- |
12528 |
|
--- |
| 12529 |
Ops.push_back(SetCC->getOperand(2)); |
0 |
12529 |
Ops.push_back(SetCC->getOperand(2)); |
0 |
| 12530 |
CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops)); |
0 |
12530 |
CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops)); |
0 |
| 12531 |
} |
0 |
12531 |
} |
0 |
| 12532 |
} |
0 |
12532 |
} |
0 |
| 12533 |
|
--- |
12533 |
|
--- |
| 12534 |
// FIXME: Bring more similar combines here, common to sext/zext (maybe aext?). |
--- |
12534 |
// FIXME: Bring more similar combines here, common to sext/zext (maybe aext?). |
--- |
| 12535 |
SDValue DAGCombiner::CombineExtLoad(SDNode *N) { |
0 |
12535 |
SDValue DAGCombiner::CombineExtLoad(SDNode *N) { |
0 |
| 12536 |
SDValue N0 = N->getOperand(0); |
0 |
12536 |
SDValue N0 = N->getOperand(0); |
0 |
| 12537 |
EVT DstVT = N->getValueType(0); |
0 |
12537 |
EVT DstVT = N->getValueType(0); |
0 |
| 12538 |
EVT SrcVT = N0.getValueType(); |
0 |
12538 |
EVT SrcVT = N0.getValueType(); |
0 |
| 12539 |
|
--- |
12539 |
|
--- |
| 12540 |
assert((N->getOpcode() == ISD::SIGN_EXTEND || |
0 |
12540 |
assert((N->getOpcode() == ISD::SIGN_EXTEND || |
0 |
| 12541 |
N->getOpcode() == ISD::ZERO_EXTEND) && |
--- |
12541 |
N->getOpcode() == ISD::ZERO_EXTEND) && |
--- |
| 12542 |
"Unexpected node type (not an extend)!"); |
--- |
12542 |
"Unexpected node type (not an extend)!"); |
--- |
| 12543 |
|
--- |
12543 |
|
--- |
| 12544 |
// fold (sext (load x)) to multiple smaller sextloads; same for zext. |
--- |
12544 |
// fold (sext (load x)) to multiple smaller sextloads; same for zext. |
--- |
| 12545 |
// For example, on a target with legal v4i32, but illegal v8i32, turn: |
--- |
12545 |
// For example, on a target with legal v4i32, but illegal v8i32, turn: |
--- |
| 12546 |
// (v8i32 (sext (v8i16 (load x)))) |
--- |
12546 |
// (v8i32 (sext (v8i16 (load x)))) |
--- |
| 12547 |
// into: |
--- |
12547 |
// into: |
--- |
| 12548 |
// (v8i32 (concat_vectors (v4i32 (sextload x)), |
--- |
12548 |
// (v8i32 (concat_vectors (v4i32 (sextload x)), |
--- |
| 12549 |
// (v4i32 (sextload (x + 16))))) |
--- |
12549 |
// (v4i32 (sextload (x + 16))))) |
--- |
| 12550 |
// Where uses of the original load, i.e.: |
--- |
12550 |
// Where uses of the original load, i.e.: |
--- |
| 12551 |
// (v8i16 (load x)) |
--- |
12551 |
// (v8i16 (load x)) |
--- |
| 12552 |
// are replaced with: |
--- |
12552 |
// are replaced with: |
--- |
| 12553 |
// (v8i16 (truncate |
--- |
12553 |
// (v8i16 (truncate |
--- |
| 12554 |
// (v8i32 (concat_vectors (v4i32 (sextload x)), |
--- |
12554 |
// (v8i32 (concat_vectors (v4i32 (sextload x)), |
--- |
| 12555 |
// (v4i32 (sextload (x + 16))))))) |
--- |
12555 |
// (v4i32 (sextload (x + 16))))))) |
--- |
| 12556 |
// |
--- |
12556 |
// |
--- |
| 12557 |
// This combine is only applicable to illegal, but splittable, vectors. |
--- |
12557 |
// This combine is only applicable to illegal, but splittable, vectors. |
--- |
| 12558 |
// All legal types, and illegal non-vector types, are handled elsewhere. |
--- |
12558 |
// All legal types, and illegal non-vector types, are handled elsewhere. |
--- |
| 12559 |
// This combine is controlled by TargetLowering::isVectorLoadExtDesirable. |
--- |
12559 |
// This combine is controlled by TargetLowering::isVectorLoadExtDesirable. |
--- |
| 12560 |
// |
--- |
12560 |
// |
--- |
| 12561 |
if (N0->getOpcode() != ISD::LOAD) |
0 |
12561 |
if (N0->getOpcode() != ISD::LOAD) |
0 |
| 12562 |
return SDValue(); |
0 |
12562 |
return SDValue(); |
0 |
| 12563 |
|
--- |
12563 |
|
--- |
| 12564 |
LoadSDNode *LN0 = cast(N0); |
0 |
12564 |
LoadSDNode *LN0 = cast(N0); |
0 |
| 12565 |
|
--- |
12565 |
|
--- |
| 12566 |
if (!ISD::isNON_EXTLoad(LN0) || !ISD::isUNINDEXEDLoad(LN0) || |
0 |
12566 |
if (!ISD::isNON_EXTLoad(LN0) || !ISD::isUNINDEXEDLoad(LN0) || |
0 |
| 12567 |
!N0.hasOneUse() || !LN0->isSimple() || |
0 |
12567 |
!N0.hasOneUse() || !LN0->isSimple() || |
0 |
| 12568 |
!DstVT.isVector() || !DstVT.isPow2VectorType() || |
0 |
12568 |
!DstVT.isVector() || !DstVT.isPow2VectorType() || |
0 |
| 12569 |
!TLI.isVectorLoadExtDesirable(SDValue(N, 0))) |
0 |
12569 |
!TLI.isVectorLoadExtDesirable(SDValue(N, 0))) |
0 |
| 12570 |
return SDValue(); |
0 |
12570 |
return SDValue(); |
0 |
| 12571 |
|
--- |
12571 |
|
--- |
| 12572 |
SmallVector SetCCs; |
0 |
12572 |
SmallVector SetCCs; |
0 |
| 12573 |
if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI)) |
0 |
12573 |
if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI)) |
0 |
| 12574 |
return SDValue(); |
0 |
12574 |
return SDValue(); |
0 |
| 12575 |
|
--- |
12575 |
|
--- |
| 12576 |
ISD::LoadExtType ExtType = |
--- |
12576 |
ISD::LoadExtType ExtType = |
--- |
| 12577 |
N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD; |
0 |
12577 |
N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD; |
0 |
| 12578 |
|
--- |
12578 |
|
--- |
| 12579 |
// Try to split the vector types to get down to legal types. |
--- |
12579 |
// Try to split the vector types to get down to legal types. |
--- |
| 12580 |
EVT SplitSrcVT = SrcVT; |
0 |
12580 |
EVT SplitSrcVT = SrcVT; |
0 |
| 12581 |
EVT SplitDstVT = DstVT; |
0 |
12581 |
EVT SplitDstVT = DstVT; |
0 |
| 12582 |
while (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT) && |
0 |
12582 |
while (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT) && |
0 |
| 12583 |
SplitSrcVT.getVectorNumElements() > 1) { |
0 |
12583 |
SplitSrcVT.getVectorNumElements() > 1) { |
0 |
| 12584 |
SplitDstVT = DAG.GetSplitDestVTs(SplitDstVT).first; |
0 |
12584 |
SplitDstVT = DAG.GetSplitDestVTs(SplitDstVT).first; |
0 |
| 12585 |
SplitSrcVT = DAG.GetSplitDestVTs(SplitSrcVT).first; |
0 |
12585 |
SplitSrcVT = DAG.GetSplitDestVTs(SplitSrcVT).first; |
0 |
| 12586 |
} |
--- |
12586 |
} |
--- |
| 12587 |
|
--- |
12587 |
|
--- |
| 12588 |
if (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT)) |
0 |
12588 |
if (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT)) |
0 |
| 12589 |
return SDValue(); |
0 |
12589 |
return SDValue(); |
0 |
| 12590 |
|
--- |
12590 |
|
--- |
| 12591 |
assert(!DstVT.isScalableVector() && "Unexpected scalable vector type"); |
0 |
12591 |
assert(!DstVT.isScalableVector() && "Unexpected scalable vector type"); |
0 |
| 12592 |
|
--- |
12592 |
|
--- |
| 12593 |
SDLoc DL(N); |
0 |
12593 |
SDLoc DL(N); |
0 |
| 12594 |
const unsigned NumSplits = |
--- |
12594 |
const unsigned NumSplits = |
--- |
| 12595 |
DstVT.getVectorNumElements() / SplitDstVT.getVectorNumElements(); |
0 |
12595 |
DstVT.getVectorNumElements() / SplitDstVT.getVectorNumElements(); |
0 |
| 12596 |
const unsigned Stride = SplitSrcVT.getStoreSize(); |
0 |
12596 |
const unsigned Stride = SplitSrcVT.getStoreSize(); |
0 |
| 12597 |
SmallVector Loads; |
0 |
12597 |
SmallVector Loads; |
0 |
| 12598 |
SmallVector Chains; |
0 |
12598 |
SmallVector Chains; |
0 |
| 12599 |
|
--- |
12599 |
|
--- |
| 12600 |
SDValue BasePtr = LN0->getBasePtr(); |
0 |
12600 |
SDValue BasePtr = LN0->getBasePtr(); |
0 |
| 12601 |
for (unsigned Idx = 0; Idx < NumSplits; Idx++) { |
0 |
12601 |
for (unsigned Idx = 0; Idx < NumSplits; Idx++) { |
0 |
| 12602 |
const unsigned Offset = Idx * Stride; |
0 |
12602 |
const unsigned Offset = Idx * Stride; |
0 |
| 12603 |
const Align Align = commonAlignment(LN0->getAlign(), Offset); |
0 |
12603 |
const Align Align = commonAlignment(LN0->getAlign(), Offset); |
0 |
| 12604 |
|
--- |
12604 |
|
--- |
| 12605 |
SDValue SplitLoad = DAG.getExtLoad( |
0 |
12605 |
SDValue SplitLoad = DAG.getExtLoad( |
0 |
| 12606 |
ExtType, SDLoc(LN0), SplitDstVT, LN0->getChain(), BasePtr, |
0 |
12606 |
ExtType, SDLoc(LN0), SplitDstVT, LN0->getChain(), BasePtr, |
0 |
| 12607 |
LN0->getPointerInfo().getWithOffset(Offset), SplitSrcVT, Align, |
0 |
12607 |
LN0->getPointerInfo().getWithOffset(Offset), SplitSrcVT, Align, |
0 |
| 12608 |
LN0->getMemOperand()->getFlags(), LN0->getAAInfo()); |
0 |
12608 |
LN0->getMemOperand()->getFlags(), LN0->getAAInfo()); |
0 |
| 12609 |
|
--- |
12609 |
|
--- |
| 12610 |
BasePtr = DAG.getMemBasePlusOffset(BasePtr, TypeSize::Fixed(Stride), DL); |
0 |
12610 |
BasePtr = DAG.getMemBasePlusOffset(BasePtr, TypeSize::Fixed(Stride), DL); |
0 |
| 12611 |
|
--- |
12611 |
|
--- |
| 12612 |
Loads.push_back(SplitLoad.getValue(0)); |
0 |
12612 |
Loads.push_back(SplitLoad.getValue(0)); |
0 |
| 12613 |
Chains.push_back(SplitLoad.getValue(1)); |
0 |
12613 |
Chains.push_back(SplitLoad.getValue(1)); |
0 |
| 12614 |
} |
--- |
12614 |
} |
--- |
| 12615 |
|
--- |
12615 |
|
--- |
| 12616 |
SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); |
0 |
12616 |
SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); |
0 |
| 12617 |
SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads); |
0 |
12617 |
SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads); |
0 |
| 12618 |
|
--- |
12618 |
|
--- |
| 12619 |
// Simplify TF. |
--- |
12619 |
// Simplify TF. |
--- |
| 12620 |
AddToWorklist(NewChain.getNode()); |
0 |
12620 |
AddToWorklist(NewChain.getNode()); |
0 |
| 12621 |
|
--- |
12621 |
|
--- |
| 12622 |
CombineTo(N, NewValue); |
0 |
12622 |
CombineTo(N, NewValue); |
0 |
| 12623 |
|
--- |
12623 |
|
--- |
| 12624 |
// Replace uses of the original load (before extension) |
--- |
12624 |
// Replace uses of the original load (before extension) |
--- |
| 12625 |
// with a truncate of the concatenated sextloaded vectors. |
--- |
12625 |
// with a truncate of the concatenated sextloaded vectors. |
--- |
| 12626 |
SDValue Trunc = |
--- |
12626 |
SDValue Trunc = |
--- |
| 12627 |
DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), NewValue); |
0 |
12627 |
DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), NewValue); |
0 |
| 12628 |
ExtendSetCCUses(SetCCs, N0, NewValue, (ISD::NodeType)N->getOpcode()); |
0 |
12628 |
ExtendSetCCUses(SetCCs, N0, NewValue, (ISD::NodeType)N->getOpcode()); |
0 |
| 12629 |
CombineTo(N0.getNode(), Trunc, NewChain); |
0 |
12629 |
CombineTo(N0.getNode(), Trunc, NewChain); |
0 |
| 12630 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
12630 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 12631 |
} |
0 |
12631 |
} |
0 |
| 12632 |
|
--- |
12632 |
|
--- |
| 12633 |
// fold (zext (and/or/xor (shl/shr (load x), cst), cst)) -> |
--- |
12633 |
// fold (zext (and/or/xor (shl/shr (load x), cst), cst)) -> |
--- |
| 12634 |
// (and/or/xor (shl/shr (zextload x), (zext cst)), (zext cst)) |
--- |
12634 |
// (and/or/xor (shl/shr (zextload x), (zext cst)), (zext cst)) |
--- |
| 12635 |
SDValue DAGCombiner::CombineZExtLogicopShiftLoad(SDNode *N) { |
0 |
12635 |
SDValue DAGCombiner::CombineZExtLogicopShiftLoad(SDNode *N) { |
0 |
| 12636 |
assert(N->getOpcode() == ISD::ZERO_EXTEND); |
0 |
12636 |
assert(N->getOpcode() == ISD::ZERO_EXTEND); |
0 |
| 12637 |
EVT VT = N->getValueType(0); |
0 |
12637 |
EVT VT = N->getValueType(0); |
0 |
| 12638 |
EVT OrigVT = N->getOperand(0).getValueType(); |
0 |
12638 |
EVT OrigVT = N->getOperand(0).getValueType(); |
0 |
| 12639 |
if (TLI.isZExtFree(OrigVT, VT)) |
0 |
12639 |
if (TLI.isZExtFree(OrigVT, VT)) |
0 |
| 12640 |
return SDValue(); |
0 |
12640 |
return SDValue(); |
0 |
| 12641 |
|
--- |
12641 |
|
--- |
| 12642 |
// and/or/xor |
--- |
12642 |
// and/or/xor |
--- |
| 12643 |
SDValue N0 = N->getOperand(0); |
0 |
12643 |
SDValue N0 = N->getOperand(0); |
0 |
| 12644 |
if (!ISD::isBitwiseLogicOp(N0.getOpcode()) || |
0 |
12644 |
if (!ISD::isBitwiseLogicOp(N0.getOpcode()) || |
0 |
| 12645 |
N0.getOperand(1).getOpcode() != ISD::Constant || |
0 |
12645 |
N0.getOperand(1).getOpcode() != ISD::Constant || |
0 |
| 12646 |
(LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT))) |
0 |
12646 |
(LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT))) |
0 |
| 12647 |
return SDValue(); |
0 |
12647 |
return SDValue(); |
0 |
| 12648 |
|
--- |
12648 |
|
--- |
| 12649 |
// shl/shr |
--- |
12649 |
// shl/shr |
--- |
| 12650 |
SDValue N1 = N0->getOperand(0); |
0 |
12650 |
SDValue N1 = N0->getOperand(0); |
0 |
| 12651 |
if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) || |
0 |
12651 |
if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) || |
0 |
| 12652 |
N1.getOperand(1).getOpcode() != ISD::Constant || |
0 |
12652 |
N1.getOperand(1).getOpcode() != ISD::Constant || |
0 |
| 12653 |
(LegalOperations && !TLI.isOperationLegal(N1.getOpcode(), VT))) |
0 |
12653 |
(LegalOperations && !TLI.isOperationLegal(N1.getOpcode(), VT))) |
0 |
| 12654 |
return SDValue(); |
0 |
12654 |
return SDValue(); |
0 |
| 12655 |
|
--- |
12655 |
|
--- |
| 12656 |
// load |
--- |
12656 |
// load |
--- |
| 12657 |
if (!isa(N1.getOperand(0))) |
0 |
12657 |
if (!isa(N1.getOperand(0))) |
0 |
| 12658 |
return SDValue(); |
0 |
12658 |
return SDValue(); |
0 |
| 12659 |
LoadSDNode *Load = cast(N1.getOperand(0)); |
0 |
12659 |
LoadSDNode *Load = cast(N1.getOperand(0)); |
0 |
| 12660 |
EVT MemVT = Load->getMemoryVT(); |
0 |
12660 |
EVT MemVT = Load->getMemoryVT(); |
0 |
| 12661 |
if (!TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT) || |
0 |
12661 |
if (!TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT) || |
0 |
| 12662 |
Load->getExtensionType() == ISD::SEXTLOAD || Load->isIndexed()) |
0 |
12662 |
Load->getExtensionType() == ISD::SEXTLOAD || Load->isIndexed()) |
0 |
| 12663 |
return SDValue(); |
0 |
12663 |
return SDValue(); |
0 |
| 12664 |
|
--- |
12664 |
|
--- |
| 12665 |
|
--- |
12665 |
|
--- |
| 12666 |
// If the shift op is SHL, the logic op must be AND, otherwise the result |
--- |
12666 |
// If the shift op is SHL, the logic op must be AND, otherwise the result |
--- |
| 12667 |
// will be wrong. |
--- |
12667 |
// will be wrong. |
--- |
| 12668 |
if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND) |
0 |
12668 |
if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND) |
0 |
| 12669 |
return SDValue(); |
0 |
12669 |
return SDValue(); |
0 |
| 12670 |
|
--- |
12670 |
|
--- |
| 12671 |
if (!N0.hasOneUse() || !N1.hasOneUse()) |
0 |
12671 |
if (!N0.hasOneUse() || !N1.hasOneUse()) |
0 |
| 12672 |
return SDValue(); |
0 |
12672 |
return SDValue(); |
0 |
| 12673 |
|
--- |
12673 |
|
--- |
| 12674 |
SmallVector SetCCs; |
0 |
12674 |
SmallVector SetCCs; |
0 |
| 12675 |
if (!ExtendUsesToFormExtLoad(VT, N1.getNode(), N1.getOperand(0), |
0 |
12675 |
if (!ExtendUsesToFormExtLoad(VT, N1.getNode(), N1.getOperand(0), |
0 |
| 12676 |
ISD::ZERO_EXTEND, SetCCs, TLI)) |
--- |
12676 |
ISD::ZERO_EXTEND, SetCCs, TLI)) |
--- |
| 12677 |
return SDValue(); |
0 |
12677 |
return SDValue(); |
0 |
| 12678 |
|
--- |
12678 |
|
--- |
| 12679 |
// Actually do the transformation. |
--- |
12679 |
// Actually do the transformation. |
--- |
| 12680 |
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(Load), VT, |
0 |
12680 |
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(Load), VT, |
0 |
| 12681 |
Load->getChain(), Load->getBasePtr(), |
0 |
12681 |
Load->getChain(), Load->getBasePtr(), |
0 |
| 12682 |
Load->getMemoryVT(), Load->getMemOperand()); |
--- |
12682 |
Load->getMemoryVT(), Load->getMemOperand()); |
--- |
| 12683 |
|
--- |
12683 |
|
--- |
| 12684 |
SDLoc DL1(N1); |
0 |
12684 |
SDLoc DL1(N1); |
0 |
| 12685 |
SDValue Shift = DAG.getNode(N1.getOpcode(), DL1, VT, ExtLoad, |
0 |
12685 |
SDValue Shift = DAG.getNode(N1.getOpcode(), DL1, VT, ExtLoad, |
0 |
| 12686 |
N1.getOperand(1)); |
0 |
12686 |
N1.getOperand(1)); |
0 |
| 12687 |
|
--- |
12687 |
|
--- |
| 12688 |
APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits()); |
0 |
12688 |
APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits()); |
0 |
| 12689 |
SDLoc DL0(N0); |
0 |
12689 |
SDLoc DL0(N0); |
0 |
| 12690 |
SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift, |
0 |
12690 |
SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift, |
0 |
| 12691 |
DAG.getConstant(Mask, DL0, VT)); |
0 |
12691 |
DAG.getConstant(Mask, DL0, VT)); |
0 |
| 12692 |
|
--- |
12692 |
|
--- |
| 12693 |
ExtendSetCCUses(SetCCs, N1.getOperand(0), ExtLoad, ISD::ZERO_EXTEND); |
0 |
12693 |
ExtendSetCCUses(SetCCs, N1.getOperand(0), ExtLoad, ISD::ZERO_EXTEND); |
0 |
| 12694 |
CombineTo(N, And); |
0 |
12694 |
CombineTo(N, And); |
0 |
| 12695 |
if (SDValue(Load, 0).hasOneUse()) { |
0 |
12695 |
if (SDValue(Load, 0).hasOneUse()) { |
0 |
| 12696 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), ExtLoad.getValue(1)); |
0 |
12696 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), ExtLoad.getValue(1)); |
0 |
| 12697 |
} else { |
--- |
12697 |
} else { |
--- |
| 12698 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(Load), |
0 |
12698 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(Load), |
0 |
| 12699 |
Load->getValueType(0), ExtLoad); |
--- |
12699 |
Load->getValueType(0), ExtLoad); |
--- |
| 12700 |
CombineTo(Load, Trunc, ExtLoad.getValue(1)); |
0 |
12700 |
CombineTo(Load, Trunc, ExtLoad.getValue(1)); |
0 |
| 12701 |
} |
--- |
12701 |
} |
--- |
| 12702 |
|
--- |
12702 |
|
--- |
| 12703 |
// N0 is dead at this point. |
--- |
12703 |
// N0 is dead at this point. |
--- |
| 12704 |
recursivelyDeleteUnusedNodes(N0.getNode()); |
0 |
12704 |
recursivelyDeleteUnusedNodes(N0.getNode()); |
0 |
| 12705 |
|
--- |
12705 |
|
--- |
| 12706 |
return SDValue(N,0); // Return N so it doesn't get rechecked! |
0 |
12706 |
return SDValue(N,0); // Return N so it doesn't get rechecked! |
0 |
| 12707 |
} |
0 |
12707 |
} |
0 |
| 12708 |
|
--- |
12708 |
|
--- |
| 12709 |
/// If we're narrowing or widening the result of a vector select and the final |
--- |
12709 |
/// If we're narrowing or widening the result of a vector select and the final |
--- |
| 12710 |
/// size is the same size as a setcc (compare) feeding the select, then try to |
--- |
12710 |
/// size is the same size as a setcc (compare) feeding the select, then try to |
--- |
| 12711 |
/// apply the cast operation to the select's operands because matching vector |
--- |
12711 |
/// apply the cast operation to the select's operands because matching vector |
--- |
| 12712 |
/// sizes for a select condition and other operands should be more efficient. |
--- |
12712 |
/// sizes for a select condition and other operands should be more efficient. |
--- |
| 12713 |
SDValue DAGCombiner::matchVSelectOpSizesWithSetCC(SDNode *Cast) { |
0 |
12713 |
SDValue DAGCombiner::matchVSelectOpSizesWithSetCC(SDNode *Cast) { |
0 |
| 12714 |
unsigned CastOpcode = Cast->getOpcode(); |
0 |
12714 |
unsigned CastOpcode = Cast->getOpcode(); |
0 |
| 12715 |
assert((CastOpcode == ISD::SIGN_EXTEND || CastOpcode == ISD::ZERO_EXTEND || |
0 |
12715 |
assert((CastOpcode == ISD::SIGN_EXTEND || CastOpcode == ISD::ZERO_EXTEND || |
0 |
| 12716 |
CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND || |
--- |
12716 |
CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND || |
--- |
| 12717 |
CastOpcode == ISD::FP_ROUND) && |
--- |
12717 |
CastOpcode == ISD::FP_ROUND) && |
--- |
| 12718 |
"Unexpected opcode for vector select narrowing/widening"); |
--- |
12718 |
"Unexpected opcode for vector select narrowing/widening"); |
--- |
| 12719 |
|
--- |
12719 |
|
--- |
| 12720 |
// We only do this transform before legal ops because the pattern may be |
--- |
12720 |
// We only do this transform before legal ops because the pattern may be |
--- |
| 12721 |
// obfuscated by target-specific operations after legalization. Do not create |
--- |
12721 |
// obfuscated by target-specific operations after legalization. Do not create |
--- |
| 12722 |
// an illegal select op, however, because that may be difficult to lower. |
--- |
12722 |
// an illegal select op, however, because that may be difficult to lower. |
--- |
| 12723 |
EVT VT = Cast->getValueType(0); |
0 |
12723 |
EVT VT = Cast->getValueType(0); |
0 |
| 12724 |
if (LegalOperations || !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT)) |
0 |
12724 |
if (LegalOperations || !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT)) |
0 |
| 12725 |
return SDValue(); |
0 |
12725 |
return SDValue(); |
0 |
| 12726 |
|
--- |
12726 |
|
--- |
| 12727 |
SDValue VSel = Cast->getOperand(0); |
0 |
12727 |
SDValue VSel = Cast->getOperand(0); |
0 |
| 12728 |
if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || |
0 |
12728 |
if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || |
0 |
| 12729 |
VSel.getOperand(0).getOpcode() != ISD::SETCC) |
0 |
12729 |
VSel.getOperand(0).getOpcode() != ISD::SETCC) |
0 |
| 12730 |
return SDValue(); |
0 |
12730 |
return SDValue(); |
0 |
| 12731 |
|
--- |
12731 |
|
--- |
| 12732 |
// Does the setcc have the same vector size as the casted select? |
--- |
12732 |
// Does the setcc have the same vector size as the casted select? |
--- |
| 12733 |
SDValue SetCC = VSel.getOperand(0); |
0 |
12733 |
SDValue SetCC = VSel.getOperand(0); |
0 |
| 12734 |
EVT SetCCVT = getSetCCResultType(SetCC.getOperand(0).getValueType()); |
0 |
12734 |
EVT SetCCVT = getSetCCResultType(SetCC.getOperand(0).getValueType()); |
0 |
| 12735 |
if (SetCCVT.getSizeInBits() != VT.getSizeInBits()) |
0 |
12735 |
if (SetCCVT.getSizeInBits() != VT.getSizeInBits()) |
0 |
| 12736 |
return SDValue(); |
0 |
12736 |
return SDValue(); |
0 |
| 12737 |
|
--- |
12737 |
|
--- |
| 12738 |
// cast (vsel (setcc X), A, B) --> vsel (setcc X), (cast A), (cast B) |
--- |
12738 |
// cast (vsel (setcc X), A, B) --> vsel (setcc X), (cast A), (cast B) |
--- |
| 12739 |
SDValue A = VSel.getOperand(1); |
0 |
12739 |
SDValue A = VSel.getOperand(1); |
0 |
| 12740 |
SDValue B = VSel.getOperand(2); |
0 |
12740 |
SDValue B = VSel.getOperand(2); |
0 |
| 12741 |
SDValue CastA, CastB; |
0 |
12741 |
SDValue CastA, CastB; |
0 |
| 12742 |
SDLoc DL(Cast); |
0 |
12742 |
SDLoc DL(Cast); |
0 |
| 12743 |
if (CastOpcode == ISD::FP_ROUND) { |
0 |
12743 |
if (CastOpcode == ISD::FP_ROUND) { |
0 |
| 12744 |
// FP_ROUND (fptrunc) has an extra flag operand to pass along. |
--- |
12744 |
// FP_ROUND (fptrunc) has an extra flag operand to pass along. |
--- |
| 12745 |
CastA = DAG.getNode(CastOpcode, DL, VT, A, Cast->getOperand(1)); |
0 |
12745 |
CastA = DAG.getNode(CastOpcode, DL, VT, A, Cast->getOperand(1)); |
0 |
| 12746 |
CastB = DAG.getNode(CastOpcode, DL, VT, B, Cast->getOperand(1)); |
0 |
12746 |
CastB = DAG.getNode(CastOpcode, DL, VT, B, Cast->getOperand(1)); |
0 |
| 12747 |
} else { |
--- |
12747 |
} else { |
--- |
| 12748 |
CastA = DAG.getNode(CastOpcode, DL, VT, A); |
0 |
12748 |
CastA = DAG.getNode(CastOpcode, DL, VT, A); |
0 |
| 12749 |
CastB = DAG.getNode(CastOpcode, DL, VT, B); |
0 |
12749 |
CastB = DAG.getNode(CastOpcode, DL, VT, B); |
0 |
| 12750 |
} |
--- |
12750 |
} |
--- |
| 12751 |
return DAG.getNode(ISD::VSELECT, DL, VT, SetCC, CastA, CastB); |
0 |
12751 |
return DAG.getNode(ISD::VSELECT, DL, VT, SetCC, CastA, CastB); |
0 |
| 12752 |
} |
0 |
12752 |
} |
0 |
| 12753 |
|
--- |
12753 |
|
--- |
| 12754 |
// fold ([s|z]ext ([s|z]extload x)) -> ([s|z]ext (truncate ([s|z]extload x))) |
--- |
12754 |
// fold ([s|z]ext ([s|z]extload x)) -> ([s|z]ext (truncate ([s|z]extload x))) |
--- |
| 12755 |
// fold ([s|z]ext ( extload x)) -> ([s|z]ext (truncate ([s|z]extload x))) |
--- |
12755 |
// fold ([s|z]ext ( extload x)) -> ([s|z]ext (truncate ([s|z]extload x))) |
--- |
| 12756 |
static SDValue tryToFoldExtOfExtload(SelectionDAG &DAG, DAGCombiner &Combiner, |
0 |
12756 |
static SDValue tryToFoldExtOfExtload(SelectionDAG &DAG, DAGCombiner &Combiner, |
0 |
| 12757 |
const TargetLowering &TLI, EVT VT, |
--- |
12757 |
const TargetLowering &TLI, EVT VT, |
--- |
| 12758 |
bool LegalOperations, SDNode *N, |
--- |
12758 |
bool LegalOperations, SDNode *N, |
--- |
| 12759 |
SDValue N0, ISD::LoadExtType ExtLoadType) { |
--- |
12759 |
SDValue N0, ISD::LoadExtType ExtLoadType) { |
--- |
| 12760 |
SDNode *N0Node = N0.getNode(); |
0 |
12760 |
SDNode *N0Node = N0.getNode(); |
0 |
| 12761 |
bool isAExtLoad = (ExtLoadType == ISD::SEXTLOAD) ? ISD::isSEXTLoad(N0Node) |
0 |
12761 |
bool isAExtLoad = (ExtLoadType == ISD::SEXTLOAD) ? ISD::isSEXTLoad(N0Node) |
0 |
| 12762 |
: ISD::isZEXTLoad(N0Node); |
0 |
12762 |
: ISD::isZEXTLoad(N0Node); |
0 |
| 12763 |
if ((!isAExtLoad && !ISD::isEXTLoad(N0Node)) || |
0 |
12763 |
if ((!isAExtLoad && !ISD::isEXTLoad(N0Node)) || |
0 |
| 12764 |
!ISD::isUNINDEXEDLoad(N0Node) || !N0.hasOneUse()) |
0 |
12764 |
!ISD::isUNINDEXEDLoad(N0Node) || !N0.hasOneUse()) |
0 |
| 12765 |
return SDValue(); |
0 |
12765 |
return SDValue(); |
0 |
| 12766 |
|
--- |
12766 |
|
--- |
| 12767 |
LoadSDNode *LN0 = cast(N0); |
0 |
12767 |
LoadSDNode *LN0 = cast(N0); |
0 |
| 12768 |
EVT MemVT = LN0->getMemoryVT(); |
0 |
12768 |
EVT MemVT = LN0->getMemoryVT(); |
0 |
| 12769 |
if ((LegalOperations || !LN0->isSimple() || |
0 |
12769 |
if ((LegalOperations || !LN0->isSimple() || |
0 |
| 12770 |
VT.isVector()) && |
0 |
12770 |
VT.isVector()) && |
0 |
| 12771 |
!TLI.isLoadExtLegal(ExtLoadType, VT, MemVT)) |
0 |
12771 |
!TLI.isLoadExtLegal(ExtLoadType, VT, MemVT)) |
0 |
| 12772 |
return SDValue(); |
0 |
12772 |
return SDValue(); |
0 |
| 12773 |
|
--- |
12773 |
|
--- |
| 12774 |
SDValue ExtLoad = |
--- |
12774 |
SDValue ExtLoad = |
--- |
| 12775 |
DAG.getExtLoad(ExtLoadType, SDLoc(LN0), VT, LN0->getChain(), |
0 |
12775 |
DAG.getExtLoad(ExtLoadType, SDLoc(LN0), VT, LN0->getChain(), |
0 |
| 12776 |
LN0->getBasePtr(), MemVT, LN0->getMemOperand()); |
0 |
12776 |
LN0->getBasePtr(), MemVT, LN0->getMemOperand()); |
0 |
| 12777 |
Combiner.CombineTo(N, ExtLoad); |
0 |
12777 |
Combiner.CombineTo(N, ExtLoad); |
0 |
| 12778 |
DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1)); |
0 |
12778 |
DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1)); |
0 |
| 12779 |
if (LN0->use_empty()) |
0 |
12779 |
if (LN0->use_empty()) |
0 |
| 12780 |
Combiner.recursivelyDeleteUnusedNodes(LN0); |
0 |
12780 |
Combiner.recursivelyDeleteUnusedNodes(LN0); |
0 |
| 12781 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
12781 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 12782 |
} |
--- |
12782 |
} |
--- |
| 12783 |
|
--- |
12783 |
|
--- |
| 12784 |
// fold ([s|z]ext (load x)) -> ([s|z]ext (truncate ([s|z]extload x))) |
--- |
12784 |
// fold ([s|z]ext (load x)) -> ([s|z]ext (truncate ([s|z]extload x))) |
--- |
| 12785 |
// Only generate vector extloads when 1) they're legal, and 2) they are |
--- |
12785 |
// Only generate vector extloads when 1) they're legal, and 2) they are |
--- |
| 12786 |
// deemed desirable by the target. |
--- |
12786 |
// deemed desirable by the target. |
--- |
| 12787 |
static SDValue tryToFoldExtOfLoad(SelectionDAG &DAG, DAGCombiner &Combiner, |
0 |
12787 |
static SDValue tryToFoldExtOfLoad(SelectionDAG &DAG, DAGCombiner &Combiner, |
0 |
| 12788 |
const TargetLowering &TLI, EVT VT, |
--- |
12788 |
const TargetLowering &TLI, EVT VT, |
--- |
| 12789 |
bool LegalOperations, SDNode *N, SDValue N0, |
--- |
12789 |
bool LegalOperations, SDNode *N, SDValue N0, |
--- |
| 12790 |
ISD::LoadExtType ExtLoadType, |
--- |
12790 |
ISD::LoadExtType ExtLoadType, |
--- |
| 12791 |
ISD::NodeType ExtOpc) { |
--- |
12791 |
ISD::NodeType ExtOpc) { |
--- |
| 12792 |
// TODO: isFixedLengthVector() should be removed and any negative effects on |
--- |
12792 |
// TODO: isFixedLengthVector() should be removed and any negative effects on |
--- |
| 12793 |
// code generation being the result of that target's implementation of |
--- |
12793 |
// code generation being the result of that target's implementation of |
--- |
| 12794 |
// isVectorLoadExtDesirable(). |
--- |
12794 |
// isVectorLoadExtDesirable(). |
--- |
| 12795 |
if (!ISD::isNON_EXTLoad(N0.getNode()) || |
0 |
12795 |
if (!ISD::isNON_EXTLoad(N0.getNode()) || |
0 |
| 12796 |
!ISD::isUNINDEXEDLoad(N0.getNode()) || |
0 |
12796 |
!ISD::isUNINDEXEDLoad(N0.getNode()) || |
0 |
| 12797 |
((LegalOperations || VT.isFixedLengthVector() || |
0 |
12797 |
((LegalOperations || VT.isFixedLengthVector() || |
0 |
| 12798 |
!cast(N0)->isSimple()) && |
0 |
12798 |
!cast(N0)->isSimple()) && |
0 |
| 12799 |
!TLI.isLoadExtLegal(ExtLoadType, VT, N0.getValueType()))) |
0 |
12799 |
!TLI.isLoadExtLegal(ExtLoadType, VT, N0.getValueType()))) |
0 |
| 12800 |
return {}; |
0 |
12800 |
return {}; |
0 |
| 12801 |
|
--- |
12801 |
|
--- |
| 12802 |
bool DoXform = true; |
0 |
12802 |
bool DoXform = true; |
0 |
| 12803 |
SmallVector SetCCs; |
0 |
12803 |
SmallVector SetCCs; |
0 |
| 12804 |
if (!N0.hasOneUse()) |
0 |
12804 |
if (!N0.hasOneUse()) |
0 |
| 12805 |
DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI); |
0 |
12805 |
DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI); |
0 |
| 12806 |
if (VT.isVector()) |
0 |
12806 |
if (VT.isVector()) |
0 |
| 12807 |
DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0)); |
0 |
12807 |
DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0)); |
0 |
| 12808 |
if (!DoXform) |
0 |
12808 |
if (!DoXform) |
0 |
| 12809 |
return {}; |
0 |
12809 |
return {}; |
0 |
| 12810 |
|
--- |
12810 |
|
--- |
| 12811 |
LoadSDNode *LN0 = cast(N0); |
0 |
12811 |
LoadSDNode *LN0 = cast(N0); |
0 |
| 12812 |
SDValue ExtLoad = DAG.getExtLoad(ExtLoadType, SDLoc(LN0), VT, LN0->getChain(), |
0 |
12812 |
SDValue ExtLoad = DAG.getExtLoad(ExtLoadType, SDLoc(LN0), VT, LN0->getChain(), |
0 |
| 12813 |
LN0->getBasePtr(), N0.getValueType(), |
0 |
12813 |
LN0->getBasePtr(), N0.getValueType(), |
0 |
| 12814 |
LN0->getMemOperand()); |
--- |
12814 |
LN0->getMemOperand()); |
--- |
| 12815 |
Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc); |
0 |
12815 |
Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc); |
0 |
| 12816 |
// If the load value is used only by N, replace it via CombineTo N. |
--- |
12816 |
// If the load value is used only by N, replace it via CombineTo N. |
--- |
| 12817 |
bool NoReplaceTrunc = SDValue(LN0, 0).hasOneUse(); |
0 |
12817 |
bool NoReplaceTrunc = SDValue(LN0, 0).hasOneUse(); |
0 |
| 12818 |
Combiner.CombineTo(N, ExtLoad); |
0 |
12818 |
Combiner.CombineTo(N, ExtLoad); |
0 |
| 12819 |
if (NoReplaceTrunc) { |
0 |
12819 |
if (NoReplaceTrunc) { |
0 |
| 12820 |
DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1)); |
0 |
12820 |
DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1)); |
0 |
| 12821 |
Combiner.recursivelyDeleteUnusedNodes(LN0); |
0 |
12821 |
Combiner.recursivelyDeleteUnusedNodes(LN0); |
0 |
| 12822 |
} else { |
--- |
12822 |
} else { |
--- |
| 12823 |
SDValue Trunc = |
--- |
12823 |
SDValue Trunc = |
--- |
| 12824 |
DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), ExtLoad); |
0 |
12824 |
DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), ExtLoad); |
0 |
| 12825 |
Combiner.CombineTo(LN0, Trunc, ExtLoad.getValue(1)); |
0 |
12825 |
Combiner.CombineTo(LN0, Trunc, ExtLoad.getValue(1)); |
0 |
| 12826 |
} |
--- |
12826 |
} |
--- |
| 12827 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
12827 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 12828 |
} |
0 |
12828 |
} |
0 |
| 12829 |
|
--- |
12829 |
|
--- |
| 12830 |
static SDValue tryToFoldExtOfMaskedLoad(SelectionDAG &DAG, |
0 |
12830 |
static SDValue tryToFoldExtOfMaskedLoad(SelectionDAG &DAG, |
0 |
| 12831 |
const TargetLowering &TLI, EVT VT, |
--- |
12831 |
const TargetLowering &TLI, EVT VT, |
--- |
| 12832 |
SDNode *N, SDValue N0, |
--- |
12832 |
SDNode *N, SDValue N0, |
--- |
| 12833 |
ISD::LoadExtType ExtLoadType, |
--- |
12833 |
ISD::LoadExtType ExtLoadType, |
--- |
| 12834 |
ISD::NodeType ExtOpc) { |
--- |
12834 |
ISD::NodeType ExtOpc) { |
--- |
| 12835 |
if (!N0.hasOneUse()) |
0 |
12835 |
if (!N0.hasOneUse()) |
0 |
| 12836 |
return SDValue(); |
0 |
12836 |
return SDValue(); |
0 |
| 12837 |
|
--- |
12837 |
|
--- |
| 12838 |
MaskedLoadSDNode *Ld = dyn_cast(N0); |
0 |
12838 |
MaskedLoadSDNode *Ld = dyn_cast(N0); |
0 |
| 12839 |
if (!Ld || Ld->getExtensionType() != ISD::NON_EXTLOAD) |
0 |
12839 |
if (!Ld || Ld->getExtensionType() != ISD::NON_EXTLOAD) |
0 |
| 12840 |
return SDValue(); |
0 |
12840 |
return SDValue(); |
0 |
| 12841 |
|
--- |
12841 |
|
--- |
| 12842 |
if (!TLI.isLoadExtLegalOrCustom(ExtLoadType, VT, Ld->getValueType(0))) |
0 |
12842 |
if (!TLI.isLoadExtLegalOrCustom(ExtLoadType, VT, Ld->getValueType(0))) |
0 |
| 12843 |
return SDValue(); |
0 |
12843 |
return SDValue(); |
0 |
| 12844 |
|
--- |
12844 |
|
--- |
| 12845 |
if (!TLI.isVectorLoadExtDesirable(SDValue(N, 0))) |
0 |
12845 |
if (!TLI.isVectorLoadExtDesirable(SDValue(N, 0))) |
0 |
| 12846 |
return SDValue(); |
0 |
12846 |
return SDValue(); |
0 |
| 12847 |
|
--- |
12847 |
|
--- |
| 12848 |
SDLoc dl(Ld); |
0 |
12848 |
SDLoc dl(Ld); |
0 |
| 12849 |
SDValue PassThru = DAG.getNode(ExtOpc, dl, VT, Ld->getPassThru()); |
0 |
12849 |
SDValue PassThru = DAG.getNode(ExtOpc, dl, VT, Ld->getPassThru()); |
0 |
| 12850 |
SDValue NewLoad = DAG.getMaskedLoad( |
0 |
12850 |
SDValue NewLoad = DAG.getMaskedLoad( |
0 |
| 12851 |
VT, dl, Ld->getChain(), Ld->getBasePtr(), Ld->getOffset(), Ld->getMask(), |
0 |
12851 |
VT, dl, Ld->getChain(), Ld->getBasePtr(), Ld->getOffset(), Ld->getMask(), |
0 |
| 12852 |
PassThru, Ld->getMemoryVT(), Ld->getMemOperand(), Ld->getAddressingMode(), |
--- |
12852 |
PassThru, Ld->getMemoryVT(), Ld->getMemOperand(), Ld->getAddressingMode(), |
--- |
| 12853 |
ExtLoadType, Ld->isExpandingLoad()); |
0 |
12853 |
ExtLoadType, Ld->isExpandingLoad()); |
0 |
| 12854 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), SDValue(NewLoad.getNode(), 1)); |
0 |
12854 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), SDValue(NewLoad.getNode(), 1)); |
0 |
| 12855 |
return NewLoad; |
0 |
12855 |
return NewLoad; |
0 |
| 12856 |
} |
0 |
12856 |
} |
0 |
| 12857 |
|
--- |
12857 |
|
--- |
| 12858 |
static SDValue foldExtendedSignBitTest(SDNode *N, SelectionDAG &DAG, |
0 |
12858 |
static SDValue foldExtendedSignBitTest(SDNode *N, SelectionDAG &DAG, |
0 |
| 12859 |
bool LegalOperations) { |
--- |
12859 |
bool LegalOperations) { |
--- |
| 12860 |
assert((N->getOpcode() == ISD::SIGN_EXTEND || |
0 |
12860 |
assert((N->getOpcode() == ISD::SIGN_EXTEND || |
0 |
| 12861 |
N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext"); |
--- |
12861 |
N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext"); |
--- |
| 12862 |
|
--- |
12862 |
|
--- |
| 12863 |
SDValue SetCC = N->getOperand(0); |
0 |
12863 |
SDValue SetCC = N->getOperand(0); |
0 |
| 12864 |
if (LegalOperations || SetCC.getOpcode() != ISD::SETCC || |
0 |
12864 |
if (LegalOperations || SetCC.getOpcode() != ISD::SETCC || |
0 |
| 12865 |
!SetCC.hasOneUse() || SetCC.getValueType() != MVT::i1) |
0 |
12865 |
!SetCC.hasOneUse() || SetCC.getValueType() != MVT::i1) |
0 |
| 12866 |
return SDValue(); |
0 |
12866 |
return SDValue(); |
0 |
| 12867 |
|
--- |
12867 |
|
--- |
| 12868 |
SDValue X = SetCC.getOperand(0); |
0 |
12868 |
SDValue X = SetCC.getOperand(0); |
0 |
| 12869 |
SDValue Ones = SetCC.getOperand(1); |
0 |
12869 |
SDValue Ones = SetCC.getOperand(1); |
0 |
| 12870 |
ISD::CondCode CC = cast(SetCC.getOperand(2))->get(); |
0 |
12870 |
ISD::CondCode CC = cast(SetCC.getOperand(2))->get(); |
0 |
| 12871 |
EVT VT = N->getValueType(0); |
0 |
12871 |
EVT VT = N->getValueType(0); |
0 |
| 12872 |
EVT XVT = X.getValueType(); |
0 |
12872 |
EVT XVT = X.getValueType(); |
0 |
| 12873 |
// setge X, C is canonicalized to setgt, so we do not need to match that |
--- |
12873 |
// setge X, C is canonicalized to setgt, so we do not need to match that |
--- |
| 12874 |
// pattern. The setlt sibling is folded in SimplifySelectCC() because it does |
--- |
12874 |
// pattern. The setlt sibling is folded in SimplifySelectCC() because it does |
--- |
| 12875 |
// not require the 'not' op. |
--- |
12875 |
// not require the 'not' op. |
--- |
| 12876 |
if (CC == ISD::SETGT && isAllOnesConstant(Ones) && VT == XVT) { |
0 |
12876 |
if (CC == ISD::SETGT && isAllOnesConstant(Ones) && VT == XVT) { |
0 |
| 12877 |
// Invert and smear/shift the sign bit: |
--- |
12877 |
// Invert and smear/shift the sign bit: |
--- |
| 12878 |
// sext i1 (setgt iN X, -1) --> sra (not X), (N - 1) |
--- |
12878 |
// sext i1 (setgt iN X, -1) --> sra (not X), (N - 1) |
--- |
| 12879 |
// zext i1 (setgt iN X, -1) --> srl (not X), (N - 1) |
--- |
12879 |
// zext i1 (setgt iN X, -1) --> srl (not X), (N - 1) |
--- |
| 12880 |
SDLoc DL(N); |
0 |
12880 |
SDLoc DL(N); |
0 |
| 12881 |
unsigned ShCt = VT.getSizeInBits() - 1; |
0 |
12881 |
unsigned ShCt = VT.getSizeInBits() - 1; |
0 |
| 12882 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
12882 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 12883 |
if (!TLI.shouldAvoidTransformToShift(VT, ShCt)) { |
0 |
12883 |
if (!TLI.shouldAvoidTransformToShift(VT, ShCt)) { |
0 |
| 12884 |
SDValue NotX = DAG.getNOT(DL, X, VT); |
0 |
12884 |
SDValue NotX = DAG.getNOT(DL, X, VT); |
0 |
| 12885 |
SDValue ShiftAmount = DAG.getConstant(ShCt, DL, VT); |
0 |
12885 |
SDValue ShiftAmount = DAG.getConstant(ShCt, DL, VT); |
0 |
| 12886 |
auto ShiftOpcode = |
--- |
12886 |
auto ShiftOpcode = |
--- |
| 12887 |
N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; |
0 |
12887 |
N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; |
0 |
| 12888 |
return DAG.getNode(ShiftOpcode, DL, VT, NotX, ShiftAmount); |
0 |
12888 |
return DAG.getNode(ShiftOpcode, DL, VT, NotX, ShiftAmount); |
0 |
| 12889 |
} |
--- |
12889 |
} |
--- |
| 12890 |
} |
0 |
12890 |
} |
0 |
| 12891 |
return SDValue(); |
0 |
12891 |
return SDValue(); |
0 |
| 12892 |
} |
--- |
12892 |
} |
--- |
| 12893 |
|
--- |
12893 |
|
--- |
| 12894 |
SDValue DAGCombiner::foldSextSetcc(SDNode *N) { |
0 |
12894 |
SDValue DAGCombiner::foldSextSetcc(SDNode *N) { |
0 |
| 12895 |
SDValue N0 = N->getOperand(0); |
0 |
12895 |
SDValue N0 = N->getOperand(0); |
0 |
| 12896 |
if (N0.getOpcode() != ISD::SETCC) |
0 |
12896 |
if (N0.getOpcode() != ISD::SETCC) |
0 |
| 12897 |
return SDValue(); |
0 |
12897 |
return SDValue(); |
0 |
| 12898 |
|
--- |
12898 |
|
--- |
| 12899 |
SDValue N00 = N0.getOperand(0); |
0 |
12899 |
SDValue N00 = N0.getOperand(0); |
0 |
| 12900 |
SDValue N01 = N0.getOperand(1); |
0 |
12900 |
SDValue N01 = N0.getOperand(1); |
0 |
| 12901 |
ISD::CondCode CC = cast(N0.getOperand(2))->get(); |
0 |
12901 |
ISD::CondCode CC = cast(N0.getOperand(2))->get(); |
0 |
| 12902 |
EVT VT = N->getValueType(0); |
0 |
12902 |
EVT VT = N->getValueType(0); |
0 |
| 12903 |
EVT N00VT = N00.getValueType(); |
0 |
12903 |
EVT N00VT = N00.getValueType(); |
0 |
| 12904 |
SDLoc DL(N); |
0 |
12904 |
SDLoc DL(N); |
0 |
| 12905 |
|
--- |
12905 |
|
--- |
| 12906 |
// Propagate fast-math-flags. |
--- |
12906 |
// Propagate fast-math-flags. |
--- |
| 12907 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags()); |
0 |
12907 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags()); |
0 |
| 12908 |
|
--- |
12908 |
|
--- |
| 12909 |
// On some architectures (such as SSE/NEON/etc) the SETCC result type is |
--- |
12909 |
// On some architectures (such as SSE/NEON/etc) the SETCC result type is |
--- |
| 12910 |
// the same size as the compared operands. Try to optimize sext(setcc()) |
--- |
12910 |
// the same size as the compared operands. Try to optimize sext(setcc()) |
--- |
| 12911 |
// if this is the case. |
--- |
12911 |
// if this is the case. |
--- |
| 12912 |
if (VT.isVector() && !LegalOperations && |
0 |
12912 |
if (VT.isVector() && !LegalOperations && |
0 |
| 12913 |
TLI.getBooleanContents(N00VT) == |
0 |
12913 |
TLI.getBooleanContents(N00VT) == |
0 |
| 12914 |
TargetLowering::ZeroOrNegativeOneBooleanContent) { |
--- |
12914 |
TargetLowering::ZeroOrNegativeOneBooleanContent) { |
--- |
| 12915 |
EVT SVT = getSetCCResultType(N00VT); |
0 |
12915 |
EVT SVT = getSetCCResultType(N00VT); |
0 |
| 12916 |
|
--- |
12916 |
|
--- |
| 12917 |
// If we already have the desired type, don't change it. |
--- |
12917 |
// If we already have the desired type, don't change it. |
--- |
| 12918 |
if (SVT != N0.getValueType()) { |
0 |
12918 |
if (SVT != N0.getValueType()) { |
0 |
| 12919 |
// We know that the # elements of the results is the same as the |
--- |
12919 |
// We know that the # elements of the results is the same as the |
--- |
| 12920 |
// # elements of the compare (and the # elements of the compare result |
--- |
12920 |
// # elements of the compare (and the # elements of the compare result |
--- |
| 12921 |
// for that matter). Check to see that they are the same size. If so, |
--- |
12921 |
// for that matter). Check to see that they are the same size. If so, |
--- |
| 12922 |
// we know that the element size of the sext'd result matches the |
--- |
12922 |
// we know that the element size of the sext'd result matches the |
--- |
| 12923 |
// element size of the compare operands. |
--- |
12923 |
// element size of the compare operands. |
--- |
| 12924 |
if (VT.getSizeInBits() == SVT.getSizeInBits()) |
0 |
12924 |
if (VT.getSizeInBits() == SVT.getSizeInBits()) |
0 |
| 12925 |
return DAG.getSetCC(DL, VT, N00, N01, CC); |
0 |
12925 |
return DAG.getSetCC(DL, VT, N00, N01, CC); |
0 |
| 12926 |
|
--- |
12926 |
|
--- |
| 12927 |
// If the desired elements are smaller or larger than the source |
--- |
12927 |
// If the desired elements are smaller or larger than the source |
--- |
| 12928 |
// elements, we can use a matching integer vector type and then |
--- |
12928 |
// elements, we can use a matching integer vector type and then |
--- |
| 12929 |
// truncate/sign extend. |
--- |
12929 |
// truncate/sign extend. |
--- |
| 12930 |
EVT MatchingVecType = N00VT.changeVectorElementTypeToInteger(); |
0 |
12930 |
EVT MatchingVecType = N00VT.changeVectorElementTypeToInteger(); |
0 |
| 12931 |
if (SVT == MatchingVecType) { |
0 |
12931 |
if (SVT == MatchingVecType) { |
0 |
| 12932 |
SDValue VsetCC = DAG.getSetCC(DL, MatchingVecType, N00, N01, CC); |
0 |
12932 |
SDValue VsetCC = DAG.getSetCC(DL, MatchingVecType, N00, N01, CC); |
0 |
| 12933 |
return DAG.getSExtOrTrunc(VsetCC, DL, VT); |
0 |
12933 |
return DAG.getSExtOrTrunc(VsetCC, DL, VT); |
0 |
| 12934 |
} |
--- |
12934 |
} |
--- |
| 12935 |
} |
--- |
12935 |
} |
--- |
| 12936 |
|
--- |
12936 |
|
--- |
| 12937 |
// Try to eliminate the sext of a setcc by zexting the compare operands. |
--- |
12937 |
// Try to eliminate the sext of a setcc by zexting the compare operands. |
--- |
| 12938 |
if (N0.hasOneUse() && TLI.isOperationLegalOrCustom(ISD::SETCC, VT) && |
0 |
12938 |
if (N0.hasOneUse() && TLI.isOperationLegalOrCustom(ISD::SETCC, VT) && |
0 |
| 12939 |
!TLI.isOperationLegalOrCustom(ISD::SETCC, SVT)) { |
0 |
12939 |
!TLI.isOperationLegalOrCustom(ISD::SETCC, SVT)) { |
0 |
| 12940 |
bool IsSignedCmp = ISD::isSignedIntSetCC(CC); |
0 |
12940 |
bool IsSignedCmp = ISD::isSignedIntSetCC(CC); |
0 |
| 12941 |
unsigned LoadOpcode = IsSignedCmp ? ISD::SEXTLOAD : ISD::ZEXTLOAD; |
0 |
12941 |
unsigned LoadOpcode = IsSignedCmp ? ISD::SEXTLOAD : ISD::ZEXTLOAD; |
0 |
| 12942 |
unsigned ExtOpcode = IsSignedCmp ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; |
0 |
12942 |
unsigned ExtOpcode = IsSignedCmp ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; |
0 |
| 12943 |
|
--- |
12943 |
|
--- |
| 12944 |
// We have an unsupported narrow vector compare op that would be legal |
--- |
12944 |
// We have an unsupported narrow vector compare op that would be legal |
--- |
| 12945 |
// if extended to the destination type. See if the compare operands |
--- |
12945 |
// if extended to the destination type. See if the compare operands |
--- |
| 12946 |
// can be freely extended to the destination type. |
--- |
12946 |
// can be freely extended to the destination type. |
--- |
| 12947 |
auto IsFreeToExtend = [&](SDValue V) { |
0 |
12947 |
auto IsFreeToExtend = [&](SDValue V) { |
0 |
| 12948 |
if (isConstantOrConstantVector(V, /*NoOpaques*/ true)) |
0 |
12948 |
if (isConstantOrConstantVector(V, /*NoOpaques*/ true)) |
0 |
| 12949 |
return true; |
0 |
12949 |
return true; |
0 |
| 12950 |
// Match a simple, non-extended load that can be converted to a |
--- |
12950 |
// Match a simple, non-extended load that can be converted to a |
--- |
| 12951 |
// legal {z/s}ext-load. |
--- |
12951 |
// legal {z/s}ext-load. |
--- |
| 12952 |
// TODO: Allow widening of an existing {z/s}ext-load? |
--- |
12952 |
// TODO: Allow widening of an existing {z/s}ext-load? |
--- |
| 12953 |
if (!(ISD::isNON_EXTLoad(V.getNode()) && |
0 |
12953 |
if (!(ISD::isNON_EXTLoad(V.getNode()) && |
0 |
| 12954 |
ISD::isUNINDEXEDLoad(V.getNode()) && |
0 |
12954 |
ISD::isUNINDEXEDLoad(V.getNode()) && |
0 |
| 12955 |
cast(V)->isSimple() && |
0 |
12955 |
cast(V)->isSimple() && |
0 |
| 12956 |
TLI.isLoadExtLegal(LoadOpcode, VT, V.getValueType()))) |
0 |
12956 |
TLI.isLoadExtLegal(LoadOpcode, VT, V.getValueType()))) |
0 |
| 12957 |
return false; |
0 |
12957 |
return false; |
0 |
| 12958 |
|
--- |
12958 |
|
--- |
| 12959 |
// Non-chain users of this value must either be the setcc in this |
--- |
12959 |
// Non-chain users of this value must either be the setcc in this |
--- |
| 12960 |
// sequence or extends that can be folded into the new {z/s}ext-load. |
--- |
12960 |
// sequence or extends that can be folded into the new {z/s}ext-load. |
--- |
| 12961 |
for (SDNode::use_iterator UI = V->use_begin(), UE = V->use_end(); |
0 |
12961 |
for (SDNode::use_iterator UI = V->use_begin(), UE = V->use_end(); |
0 |
| 12962 |
UI != UE; ++UI) { |
0 |
12962 |
UI != UE; ++UI) { |
0 |
| 12963 |
// Skip uses of the chain and the setcc. |
--- |
12963 |
// Skip uses of the chain and the setcc. |
--- |
| 12964 |
SDNode *User = *UI; |
0 |
12964 |
SDNode *User = *UI; |
0 |
| 12965 |
if (UI.getUse().getResNo() != 0 || User == N0.getNode()) |
0 |
12965 |
if (UI.getUse().getResNo() != 0 || User == N0.getNode()) |
0 |
| 12966 |
continue; |
0 |
12966 |
continue; |
0 |
| 12967 |
// Extra users must have exactly the same cast we are about to create. |
--- |
12967 |
// Extra users must have exactly the same cast we are about to create. |
--- |
| 12968 |
// TODO: This restriction could be eased if ExtendUsesToFormExtLoad() |
--- |
12968 |
// TODO: This restriction could be eased if ExtendUsesToFormExtLoad() |
--- |
| 12969 |
// is enhanced similarly. |
--- |
12969 |
// is enhanced similarly. |
--- |
| 12970 |
if (User->getOpcode() != ExtOpcode || User->getValueType(0) != VT) |
0 |
12970 |
if (User->getOpcode() != ExtOpcode || User->getValueType(0) != VT) |
0 |
| 12971 |
return false; |
0 |
12971 |
return false; |
0 |
| 12972 |
} |
--- |
12972 |
} |
--- |
| 12973 |
return true; |
0 |
12973 |
return true; |
0 |
| 12974 |
}; |
0 |
12974 |
}; |
0 |
| 12975 |
|
--- |
12975 |
|
--- |
| 12976 |
if (IsFreeToExtend(N00) && IsFreeToExtend(N01)) { |
0 |
12976 |
if (IsFreeToExtend(N00) && IsFreeToExtend(N01)) { |
0 |
| 12977 |
SDValue Ext0 = DAG.getNode(ExtOpcode, DL, VT, N00); |
0 |
12977 |
SDValue Ext0 = DAG.getNode(ExtOpcode, DL, VT, N00); |
0 |
| 12978 |
SDValue Ext1 = DAG.getNode(ExtOpcode, DL, VT, N01); |
0 |
12978 |
SDValue Ext1 = DAG.getNode(ExtOpcode, DL, VT, N01); |
0 |
| 12979 |
return DAG.getSetCC(DL, VT, Ext0, Ext1, CC); |
0 |
12979 |
return DAG.getSetCC(DL, VT, Ext0, Ext1, CC); |
0 |
| 12980 |
} |
--- |
12980 |
} |
--- |
| 12981 |
} |
--- |
12981 |
} |
--- |
| 12982 |
} |
--- |
12982 |
} |
--- |
| 12983 |
|
--- |
12983 |
|
--- |
| 12984 |
// sext(setcc x, y, cc) -> (select (setcc x, y, cc), T, 0) |
--- |
12984 |
// sext(setcc x, y, cc) -> (select (setcc x, y, cc), T, 0) |
--- |
| 12985 |
// Here, T can be 1 or -1, depending on the type of the setcc and |
--- |
12985 |
// Here, T can be 1 or -1, depending on the type of the setcc and |
--- |
| 12986 |
// getBooleanContents(). |
--- |
12986 |
// getBooleanContents(). |
--- |
| 12987 |
unsigned SetCCWidth = N0.getScalarValueSizeInBits(); |
0 |
12987 |
unsigned SetCCWidth = N0.getScalarValueSizeInBits(); |
0 |
| 12988 |
|
--- |
12988 |
|
--- |
| 12989 |
// To determine the "true" side of the select, we need to know the high bit |
--- |
12989 |
// To determine the "true" side of the select, we need to know the high bit |
--- |
| 12990 |
// of the value returned by the setcc if it evaluates to true. |
--- |
12990 |
// of the value returned by the setcc if it evaluates to true. |
--- |
| 12991 |
// If the type of the setcc is i1, then the true case of the select is just |
--- |
12991 |
// If the type of the setcc is i1, then the true case of the select is just |
--- |
| 12992 |
// sext(i1 1), that is, -1. |
--- |
12992 |
// sext(i1 1), that is, -1. |
--- |
| 12993 |
// If the type of the setcc is larger (say, i8) then the value of the high |
--- |
12993 |
// If the type of the setcc is larger (say, i8) then the value of the high |
--- |
| 12994 |
// bit depends on getBooleanContents(), so ask TLI for a real "true" value |
--- |
12994 |
// bit depends on getBooleanContents(), so ask TLI for a real "true" value |
--- |
| 12995 |
// of the appropriate width. |
--- |
12995 |
// of the appropriate width. |
--- |
| 12996 |
SDValue ExtTrueVal = (SetCCWidth == 1) |
--- |
12996 |
SDValue ExtTrueVal = (SetCCWidth == 1) |
--- |
| 12997 |
? DAG.getAllOnesConstant(DL, VT) |
0 |
12997 |
? DAG.getAllOnesConstant(DL, VT) |
0 |
| 12998 |
: DAG.getBoolConstant(true, DL, VT, N00VT); |
0 |
12998 |
: DAG.getBoolConstant(true, DL, VT, N00VT); |
0 |
| 12999 |
SDValue Zero = DAG.getConstant(0, DL, VT); |
0 |
12999 |
SDValue Zero = DAG.getConstant(0, DL, VT); |
0 |
| 13000 |
if (SDValue SCC = SimplifySelectCC(DL, N00, N01, ExtTrueVal, Zero, CC, true)) |
0 |
13000 |
if (SDValue SCC = SimplifySelectCC(DL, N00, N01, ExtTrueVal, Zero, CC, true)) |
0 |
| 13001 |
return SCC; |
0 |
13001 |
return SCC; |
0 |
| 13002 |
|
--- |
13002 |
|
--- |
| 13003 |
if (!VT.isVector() && !shouldConvertSelectOfConstantsToMath(N0, VT, TLI)) { |
0 |
13003 |
if (!VT.isVector() && !shouldConvertSelectOfConstantsToMath(N0, VT, TLI)) { |
0 |
| 13004 |
EVT SetCCVT = getSetCCResultType(N00VT); |
0 |
13004 |
EVT SetCCVT = getSetCCResultType(N00VT); |
0 |
| 13005 |
// Don't do this transform for i1 because there's a select transform |
--- |
13005 |
// Don't do this transform for i1 because there's a select transform |
--- |
| 13006 |
// that would reverse it. |
--- |
13006 |
// that would reverse it. |
--- |
| 13007 |
// TODO: We should not do this transform at all without a target hook |
--- |
13007 |
// TODO: We should not do this transform at all without a target hook |
--- |
| 13008 |
// because a sext is likely cheaper than a select? |
--- |
13008 |
// because a sext is likely cheaper than a select? |
--- |
| 13009 |
if (SetCCVT.getScalarSizeInBits() != 1 && |
0 |
13009 |
if (SetCCVT.getScalarSizeInBits() != 1 && |
0 |
| 13010 |
(!LegalOperations || TLI.isOperationLegal(ISD::SETCC, N00VT))) { |
0 |
13010 |
(!LegalOperations || TLI.isOperationLegal(ISD::SETCC, N00VT))) { |
0 |
| 13011 |
SDValue SetCC = DAG.getSetCC(DL, SetCCVT, N00, N01, CC); |
0 |
13011 |
SDValue SetCC = DAG.getSetCC(DL, SetCCVT, N00, N01, CC); |
0 |
| 13012 |
return DAG.getSelect(DL, VT, SetCC, ExtTrueVal, Zero); |
0 |
13012 |
return DAG.getSelect(DL, VT, SetCC, ExtTrueVal, Zero); |
0 |
| 13013 |
} |
--- |
13013 |
} |
--- |
| 13014 |
} |
--- |
13014 |
} |
--- |
| 13015 |
|
--- |
13015 |
|
--- |
| 13016 |
return SDValue(); |
0 |
13016 |
return SDValue(); |
0 |
| 13017 |
} |
0 |
13017 |
} |
0 |
| 13018 |
|
--- |
13018 |
|
--- |
| 13019 |
SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { |
0 |
13019 |
SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { |
0 |
| 13020 |
SDValue N0 = N->getOperand(0); |
0 |
13020 |
SDValue N0 = N->getOperand(0); |
0 |
| 13021 |
EVT VT = N->getValueType(0); |
0 |
13021 |
EVT VT = N->getValueType(0); |
0 |
| 13022 |
SDLoc DL(N); |
0 |
13022 |
SDLoc DL(N); |
0 |
| 13023 |
|
--- |
13023 |
|
--- |
| 13024 |
if (VT.isVector()) |
0 |
13024 |
if (VT.isVector()) |
0 |
| 13025 |
if (SDValue FoldedVOp = SimplifyVCastOp(N, DL)) |
0 |
13025 |
if (SDValue FoldedVOp = SimplifyVCastOp(N, DL)) |
0 |
| 13026 |
return FoldedVOp; |
0 |
13026 |
return FoldedVOp; |
0 |
| 13027 |
|
--- |
13027 |
|
--- |
| 13028 |
// sext(undef) = 0 because the top bit will all be the same. |
--- |
13028 |
// sext(undef) = 0 because the top bit will all be the same. |
--- |
| 13029 |
if (N0.isUndef()) |
0 |
13029 |
if (N0.isUndef()) |
0 |
| 13030 |
return DAG.getConstant(0, DL, VT); |
0 |
13030 |
return DAG.getConstant(0, DL, VT); |
0 |
| 13031 |
|
--- |
13031 |
|
--- |
| 13032 |
if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes)) |
0 |
13032 |
if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes)) |
0 |
| 13033 |
return Res; |
0 |
13033 |
return Res; |
0 |
| 13034 |
|
--- |
13034 |
|
--- |
| 13035 |
// fold (sext (sext x)) -> (sext x) |
--- |
13035 |
// fold (sext (sext x)) -> (sext x) |
--- |
| 13036 |
// fold (sext (aext x)) -> (sext x) |
--- |
13036 |
// fold (sext (aext x)) -> (sext x) |
--- |
| 13037 |
if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) |
0 |
13037 |
if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) |
0 |
| 13038 |
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N0.getOperand(0)); |
0 |
13038 |
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N0.getOperand(0)); |
0 |
| 13039 |
|
--- |
13039 |
|
--- |
| 13040 |
// fold (sext (aext_extend_vector_inreg x)) -> (sext_extend_vector_inreg x) |
--- |
13040 |
// fold (sext (aext_extend_vector_inreg x)) -> (sext_extend_vector_inreg x) |
--- |
| 13041 |
// fold (sext (sext_extend_vector_inreg x)) -> (sext_extend_vector_inreg x) |
--- |
13041 |
// fold (sext (sext_extend_vector_inreg x)) -> (sext_extend_vector_inreg x) |
--- |
| 13042 |
if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || |
0 |
13042 |
if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || |
0 |
| 13043 |
N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) |
0 |
13043 |
N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) |
0 |
| 13044 |
return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, |
0 |
13044 |
return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, |
0 |
| 13045 |
N0.getOperand(0)); |
0 |
13045 |
N0.getOperand(0)); |
0 |
| 13046 |
|
--- |
13046 |
|
--- |
| 13047 |
// fold (sext (sext_inreg x)) -> (sext (trunc x)) |
--- |
13047 |
// fold (sext (sext_inreg x)) -> (sext (trunc x)) |
--- |
| 13048 |
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { |
0 |
13048 |
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { |
0 |
| 13049 |
SDValue N00 = N0.getOperand(0); |
0 |
13049 |
SDValue N00 = N0.getOperand(0); |
0 |
| 13050 |
EVT ExtVT = cast(N0->getOperand(1))->getVT(); |
0 |
13050 |
EVT ExtVT = cast(N0->getOperand(1))->getVT(); |
0 |
| 13051 |
if (N00.getOpcode() == ISD::TRUNCATE && |
0 |
13051 |
if (N00.getOpcode() == ISD::TRUNCATE && |
0 |
| 13052 |
(!LegalTypes || TLI.isTypeLegal(ExtVT))) { |
0 |
13052 |
(!LegalTypes || TLI.isTypeLegal(ExtVT))) { |
0 |
| 13053 |
SDValue T = DAG.getNode(ISD::TRUNCATE, DL, ExtVT, N00.getOperand(0)); |
0 |
13053 |
SDValue T = DAG.getNode(ISD::TRUNCATE, DL, ExtVT, N00.getOperand(0)); |
0 |
| 13054 |
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, T); |
0 |
13054 |
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, T); |
0 |
| 13055 |
} |
--- |
13055 |
} |
--- |
| 13056 |
} |
--- |
13056 |
} |
--- |
| 13057 |
|
--- |
13057 |
|
--- |
| 13058 |
if (N0.getOpcode() == ISD::TRUNCATE) { |
0 |
13058 |
if (N0.getOpcode() == ISD::TRUNCATE) { |
0 |
| 13059 |
// fold (sext (truncate (load x))) -> (sext (smaller load x)) |
--- |
13059 |
// fold (sext (truncate (load x))) -> (sext (smaller load x)) |
--- |
| 13060 |
// fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) |
--- |
13060 |
// fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) |
--- |
| 13061 |
if (SDValue NarrowLoad = reduceLoadWidth(N0.getNode())) { |
0 |
13061 |
if (SDValue NarrowLoad = reduceLoadWidth(N0.getNode())) { |
0 |
| 13062 |
SDNode *oye = N0.getOperand(0).getNode(); |
0 |
13062 |
SDNode *oye = N0.getOperand(0).getNode(); |
0 |
| 13063 |
if (NarrowLoad.getNode() != N0.getNode()) { |
0 |
13063 |
if (NarrowLoad.getNode() != N0.getNode()) { |
0 |
| 13064 |
CombineTo(N0.getNode(), NarrowLoad); |
0 |
13064 |
CombineTo(N0.getNode(), NarrowLoad); |
0 |
| 13065 |
// CombineTo deleted the truncate, if needed, but not what's under it. |
--- |
13065 |
// CombineTo deleted the truncate, if needed, but not what's under it. |
--- |
| 13066 |
AddToWorklist(oye); |
0 |
13066 |
AddToWorklist(oye); |
0 |
| 13067 |
} |
--- |
13067 |
} |
--- |
| 13068 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
13068 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 13069 |
} |
--- |
13069 |
} |
--- |
| 13070 |
|
--- |
13070 |
|
--- |
| 13071 |
// See if the value being truncated is already sign extended. If so, just |
--- |
13071 |
// See if the value being truncated is already sign extended. If so, just |
--- |
| 13072 |
// eliminate the trunc/sext pair. |
--- |
13072 |
// eliminate the trunc/sext pair. |
--- |
| 13073 |
SDValue Op = N0.getOperand(0); |
0 |
13073 |
SDValue Op = N0.getOperand(0); |
0 |
| 13074 |
unsigned OpBits = Op.getScalarValueSizeInBits(); |
0 |
13074 |
unsigned OpBits = Op.getScalarValueSizeInBits(); |
0 |
| 13075 |
unsigned MidBits = N0.getScalarValueSizeInBits(); |
0 |
13075 |
unsigned MidBits = N0.getScalarValueSizeInBits(); |
0 |
| 13076 |
unsigned DestBits = VT.getScalarSizeInBits(); |
0 |
13076 |
unsigned DestBits = VT.getScalarSizeInBits(); |
0 |
| 13077 |
unsigned NumSignBits = DAG.ComputeNumSignBits(Op); |
0 |
13077 |
unsigned NumSignBits = DAG.ComputeNumSignBits(Op); |
0 |
| 13078 |
|
--- |
13078 |
|
--- |
| 13079 |
if (OpBits == DestBits) { |
0 |
13079 |
if (OpBits == DestBits) { |
0 |
| 13080 |
// Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign |
--- |
13080 |
// Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign |
--- |
| 13081 |
// bits, it is already ready. |
--- |
13081 |
// bits, it is already ready. |
--- |
| 13082 |
if (NumSignBits > DestBits-MidBits) |
0 |
13082 |
if (NumSignBits > DestBits-MidBits) |
0 |
| 13083 |
return Op; |
0 |
13083 |
return Op; |
0 |
| 13084 |
} else if (OpBits < DestBits) { |
0 |
13084 |
} else if (OpBits < DestBits) { |
0 |
| 13085 |
// Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign |
--- |
13085 |
// Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign |
--- |
| 13086 |
// bits, just sext from i32. |
--- |
13086 |
// bits, just sext from i32. |
--- |
| 13087 |
if (NumSignBits > OpBits-MidBits) |
0 |
13087 |
if (NumSignBits > OpBits-MidBits) |
0 |
| 13088 |
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op); |
0 |
13088 |
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op); |
0 |
| 13089 |
} else { |
--- |
13089 |
} else { |
--- |
| 13090 |
// Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign |
--- |
13090 |
// Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign |
--- |
| 13091 |
// bits, just truncate to i32. |
--- |
13091 |
// bits, just truncate to i32. |
--- |
| 13092 |
if (NumSignBits > OpBits-MidBits) |
0 |
13092 |
if (NumSignBits > OpBits-MidBits) |
0 |
| 13093 |
return DAG.getNode(ISD::TRUNCATE, DL, VT, Op); |
0 |
13093 |
return DAG.getNode(ISD::TRUNCATE, DL, VT, Op); |
0 |
| 13094 |
} |
--- |
13094 |
} |
--- |
| 13095 |
|
--- |
13095 |
|
--- |
| 13096 |
// fold (sext (truncate x)) -> (sextinreg x). |
--- |
13096 |
// fold (sext (truncate x)) -> (sextinreg x). |
--- |
| 13097 |
if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, |
0 |
13097 |
if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, |
0 |
| 13098 |
N0.getValueType())) { |
--- |
13098 |
N0.getValueType())) { |
--- |
| 13099 |
if (OpBits < DestBits) |
0 |
13099 |
if (OpBits < DestBits) |
0 |
| 13100 |
Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op); |
0 |
13100 |
Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op); |
0 |
| 13101 |
else if (OpBits > DestBits) |
0 |
13101 |
else if (OpBits > DestBits) |
0 |
| 13102 |
Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op); |
0 |
13102 |
Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op); |
0 |
| 13103 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Op, |
0 |
13103 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Op, |
0 |
| 13104 |
DAG.getValueType(N0.getValueType())); |
0 |
13104 |
DAG.getValueType(N0.getValueType())); |
0 |
| 13105 |
} |
--- |
13105 |
} |
--- |
| 13106 |
} |
--- |
13106 |
} |
--- |
| 13107 |
|
--- |
13107 |
|
--- |
| 13108 |
// Try to simplify (sext (load x)). |
--- |
13108 |
// Try to simplify (sext (load x)). |
--- |
| 13109 |
if (SDValue foldedExt = |
0 |
13109 |
if (SDValue foldedExt = |
0 |
| 13110 |
tryToFoldExtOfLoad(DAG, *this, TLI, VT, LegalOperations, N, N0, |
0 |
13110 |
tryToFoldExtOfLoad(DAG, *this, TLI, VT, LegalOperations, N, N0, |
0 |
| 13111 |
ISD::SEXTLOAD, ISD::SIGN_EXTEND)) |
0 |
13111 |
ISD::SEXTLOAD, ISD::SIGN_EXTEND)) |
0 |
| 13112 |
return foldedExt; |
0 |
13112 |
return foldedExt; |
0 |
| 13113 |
|
--- |
13113 |
|
--- |
| 13114 |
if (SDValue foldedExt = |
0 |
13114 |
if (SDValue foldedExt = |
0 |
| 13115 |
tryToFoldExtOfMaskedLoad(DAG, TLI, VT, N, N0, ISD::SEXTLOAD, |
0 |
13115 |
tryToFoldExtOfMaskedLoad(DAG, TLI, VT, N, N0, ISD::SEXTLOAD, |
0 |
| 13116 |
ISD::SIGN_EXTEND)) |
0 |
13116 |
ISD::SIGN_EXTEND)) |
0 |
| 13117 |
return foldedExt; |
0 |
13117 |
return foldedExt; |
0 |
| 13118 |
|
--- |
13118 |
|
--- |
| 13119 |
// fold (sext (load x)) to multiple smaller sextloads. |
--- |
13119 |
// fold (sext (load x)) to multiple smaller sextloads. |
--- |
| 13120 |
// Only on illegal but splittable vectors. |
--- |
13120 |
// Only on illegal but splittable vectors. |
--- |
| 13121 |
if (SDValue ExtLoad = CombineExtLoad(N)) |
0 |
13121 |
if (SDValue ExtLoad = CombineExtLoad(N)) |
0 |
| 13122 |
return ExtLoad; |
0 |
13122 |
return ExtLoad; |
0 |
| 13123 |
|
--- |
13123 |
|
--- |
| 13124 |
// Try to simplify (sext (sextload x)). |
--- |
13124 |
// Try to simplify (sext (sextload x)). |
--- |
| 13125 |
if (SDValue foldedExt = tryToFoldExtOfExtload( |
0 |
13125 |
if (SDValue foldedExt = tryToFoldExtOfExtload( |
0 |
| 13126 |
DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::SEXTLOAD)) |
0 |
13126 |
DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::SEXTLOAD)) |
0 |
| 13127 |
return foldedExt; |
0 |
13127 |
return foldedExt; |
0 |
| 13128 |
|
--- |
13128 |
|
--- |
| 13129 |
// fold (sext (and/or/xor (load x), cst)) -> |
--- |
13129 |
// fold (sext (and/or/xor (load x), cst)) -> |
--- |
| 13130 |
// (and/or/xor (sextload x), (sext cst)) |
--- |
13130 |
// (and/or/xor (sextload x), (sext cst)) |
--- |
| 13131 |
if (ISD::isBitwiseLogicOp(N0.getOpcode()) && |
0 |
13131 |
if (ISD::isBitwiseLogicOp(N0.getOpcode()) && |
0 |
| 13132 |
isa(N0.getOperand(0)) && |
0 |
13132 |
isa(N0.getOperand(0)) && |
0 |
| 13133 |
N0.getOperand(1).getOpcode() == ISD::Constant && |
0 |
13133 |
N0.getOperand(1).getOpcode() == ISD::Constant && |
0 |
| 13134 |
(!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { |
0 |
13134 |
(!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { |
0 |
| 13135 |
LoadSDNode *LN00 = cast(N0.getOperand(0)); |
0 |
13135 |
LoadSDNode *LN00 = cast(N0.getOperand(0)); |
0 |
| 13136 |
EVT MemVT = LN00->getMemoryVT(); |
0 |
13136 |
EVT MemVT = LN00->getMemoryVT(); |
0 |
| 13137 |
if (TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, MemVT) && |
0 |
13137 |
if (TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, MemVT) && |
0 |
| 13138 |
LN00->getExtensionType() != ISD::ZEXTLOAD && LN00->isUnindexed()) { |
0 |
13138 |
LN00->getExtensionType() != ISD::ZEXTLOAD && LN00->isUnindexed()) { |
0 |
| 13139 |
SmallVector SetCCs; |
0 |
13139 |
SmallVector SetCCs; |
0 |
| 13140 |
bool DoXform = ExtendUsesToFormExtLoad(VT, N0.getNode(), N0.getOperand(0), |
0 |
13140 |
bool DoXform = ExtendUsesToFormExtLoad(VT, N0.getNode(), N0.getOperand(0), |
0 |
| 13141 |
ISD::SIGN_EXTEND, SetCCs, TLI); |
--- |
13141 |
ISD::SIGN_EXTEND, SetCCs, TLI); |
--- |
| 13142 |
if (DoXform) { |
0 |
13142 |
if (DoXform) { |
0 |
| 13143 |
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN00), VT, |
0 |
13143 |
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN00), VT, |
0 |
| 13144 |
LN00->getChain(), LN00->getBasePtr(), |
0 |
13144 |
LN00->getChain(), LN00->getBasePtr(), |
0 |
| 13145 |
LN00->getMemoryVT(), |
--- |
13145 |
LN00->getMemoryVT(), |
--- |
| 13146 |
LN00->getMemOperand()); |
--- |
13146 |
LN00->getMemOperand()); |
--- |
| 13147 |
APInt Mask = N0.getConstantOperandAPInt(1).sext(VT.getSizeInBits()); |
0 |
13147 |
APInt Mask = N0.getConstantOperandAPInt(1).sext(VT.getSizeInBits()); |
0 |
| 13148 |
SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, |
0 |
13148 |
SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, |
0 |
| 13149 |
ExtLoad, DAG.getConstant(Mask, DL, VT)); |
0 |
13149 |
ExtLoad, DAG.getConstant(Mask, DL, VT)); |
0 |
| 13150 |
ExtendSetCCUses(SetCCs, N0.getOperand(0), ExtLoad, ISD::SIGN_EXTEND); |
0 |
13150 |
ExtendSetCCUses(SetCCs, N0.getOperand(0), ExtLoad, ISD::SIGN_EXTEND); |
0 |
| 13151 |
bool NoReplaceTruncAnd = !N0.hasOneUse(); |
0 |
13151 |
bool NoReplaceTruncAnd = !N0.hasOneUse(); |
0 |
| 13152 |
bool NoReplaceTrunc = SDValue(LN00, 0).hasOneUse(); |
0 |
13152 |
bool NoReplaceTrunc = SDValue(LN00, 0).hasOneUse(); |
0 |
| 13153 |
CombineTo(N, And); |
0 |
13153 |
CombineTo(N, And); |
0 |
| 13154 |
// If N0 has multiple uses, change other uses as well. |
--- |
13154 |
// If N0 has multiple uses, change other uses as well. |
--- |
| 13155 |
if (NoReplaceTruncAnd) { |
0 |
13155 |
if (NoReplaceTruncAnd) { |
0 |
| 13156 |
SDValue TruncAnd = |
--- |
13156 |
SDValue TruncAnd = |
--- |
| 13157 |
DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), And); |
0 |
13157 |
DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), And); |
0 |
| 13158 |
CombineTo(N0.getNode(), TruncAnd); |
0 |
13158 |
CombineTo(N0.getNode(), TruncAnd); |
0 |
| 13159 |
} |
--- |
13159 |
} |
--- |
| 13160 |
if (NoReplaceTrunc) { |
0 |
13160 |
if (NoReplaceTrunc) { |
0 |
| 13161 |
DAG.ReplaceAllUsesOfValueWith(SDValue(LN00, 1), ExtLoad.getValue(1)); |
0 |
13161 |
DAG.ReplaceAllUsesOfValueWith(SDValue(LN00, 1), ExtLoad.getValue(1)); |
0 |
| 13162 |
} else { |
--- |
13162 |
} else { |
--- |
| 13163 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(LN00), |
0 |
13163 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(LN00), |
0 |
| 13164 |
LN00->getValueType(0), ExtLoad); |
--- |
13164 |
LN00->getValueType(0), ExtLoad); |
--- |
| 13165 |
CombineTo(LN00, Trunc, ExtLoad.getValue(1)); |
0 |
13165 |
CombineTo(LN00, Trunc, ExtLoad.getValue(1)); |
0 |
| 13166 |
} |
--- |
13166 |
} |
--- |
| 13167 |
return SDValue(N,0); // Return N so it doesn't get rechecked! |
0 |
13167 |
return SDValue(N,0); // Return N so it doesn't get rechecked! |
0 |
| 13168 |
} |
0 |
13168 |
} |
0 |
| 13169 |
} |
0 |
13169 |
} |
0 |
| 13170 |
} |
--- |
13170 |
} |
--- |
| 13171 |
|
--- |
13171 |
|
--- |
| 13172 |
if (SDValue V = foldExtendedSignBitTest(N, DAG, LegalOperations)) |
0 |
13172 |
if (SDValue V = foldExtendedSignBitTest(N, DAG, LegalOperations)) |
0 |
| 13173 |
return V; |
0 |
13173 |
return V; |
0 |
| 13174 |
|
--- |
13174 |
|
--- |
| 13175 |
if (SDValue V = foldSextSetcc(N)) |
0 |
13175 |
if (SDValue V = foldSextSetcc(N)) |
0 |
| 13176 |
return V; |
0 |
13176 |
return V; |
0 |
| 13177 |
|
--- |
13177 |
|
--- |
| 13178 |
// fold (sext x) -> (zext x) if the sign bit is known zero. |
--- |
13178 |
// fold (sext x) -> (zext x) if the sign bit is known zero. |
--- |
| 13179 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && |
0 |
13179 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && |
0 |
| 13180 |
DAG.SignBitIsZero(N0)) |
0 |
13180 |
DAG.SignBitIsZero(N0)) |
0 |
| 13181 |
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0); |
0 |
13181 |
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0); |
0 |
| 13182 |
|
--- |
13182 |
|
--- |
| 13183 |
if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N)) |
0 |
13183 |
if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N)) |
0 |
| 13184 |
return NewVSel; |
0 |
13184 |
return NewVSel; |
0 |
| 13185 |
|
--- |
13185 |
|
--- |
| 13186 |
// Eliminate this sign extend by doing a negation in the destination type: |
--- |
13186 |
// Eliminate this sign extend by doing a negation in the destination type: |
--- |
| 13187 |
// sext i32 (0 - (zext i8 X to i32)) to i64 --> 0 - (zext i8 X to i64) |
--- |
13187 |
// sext i32 (0 - (zext i8 X to i32)) to i64 --> 0 - (zext i8 X to i64) |
--- |
| 13188 |
if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && |
0 |
13188 |
if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() && |
0 |
| 13189 |
isNullOrNullSplat(N0.getOperand(0)) && |
0 |
13189 |
isNullOrNullSplat(N0.getOperand(0)) && |
0 |
| 13190 |
N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND && |
0 |
13190 |
N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND && |
0 |
| 13191 |
TLI.isOperationLegalOrCustom(ISD::SUB, VT)) { |
0 |
13191 |
TLI.isOperationLegalOrCustom(ISD::SUB, VT)) { |
0 |
| 13192 |
SDValue Zext = DAG.getZExtOrTrunc(N0.getOperand(1).getOperand(0), DL, VT); |
0 |
13192 |
SDValue Zext = DAG.getZExtOrTrunc(N0.getOperand(1).getOperand(0), DL, VT); |
0 |
| 13193 |
return DAG.getNegative(Zext, DL, VT); |
0 |
13193 |
return DAG.getNegative(Zext, DL, VT); |
0 |
| 13194 |
} |
--- |
13194 |
} |
--- |
| 13195 |
// Eliminate this sign extend by doing a decrement in the destination type: |
--- |
13195 |
// Eliminate this sign extend by doing a decrement in the destination type: |
--- |
| 13196 |
// sext i32 ((zext i8 X to i32) + (-1)) to i64 --> (zext i8 X to i64) + (-1) |
--- |
13196 |
// sext i32 ((zext i8 X to i32) + (-1)) to i64 --> (zext i8 X to i64) + (-1) |
--- |
| 13197 |
if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && |
0 |
13197 |
if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && |
0 |
| 13198 |
isAllOnesOrAllOnesSplat(N0.getOperand(1)) && |
0 |
13198 |
isAllOnesOrAllOnesSplat(N0.getOperand(1)) && |
0 |
| 13199 |
N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && |
0 |
13199 |
N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && |
0 |
| 13200 |
TLI.isOperationLegalOrCustom(ISD::ADD, VT)) { |
0 |
13200 |
TLI.isOperationLegalOrCustom(ISD::ADD, VT)) { |
0 |
| 13201 |
SDValue Zext = DAG.getZExtOrTrunc(N0.getOperand(0).getOperand(0), DL, VT); |
0 |
13201 |
SDValue Zext = DAG.getZExtOrTrunc(N0.getOperand(0).getOperand(0), DL, VT); |
0 |
| 13202 |
return DAG.getNode(ISD::ADD, DL, VT, Zext, DAG.getAllOnesConstant(DL, VT)); |
0 |
13202 |
return DAG.getNode(ISD::ADD, DL, VT, Zext, DAG.getAllOnesConstant(DL, VT)); |
0 |
| 13203 |
} |
--- |
13203 |
} |
--- |
| 13204 |
|
--- |
13204 |
|
--- |
| 13205 |
// fold sext (not i1 X) -> add (zext i1 X), -1 |
--- |
13205 |
// fold sext (not i1 X) -> add (zext i1 X), -1 |
--- |
| 13206 |
// TODO: This could be extended to handle bool vectors. |
--- |
13206 |
// TODO: This could be extended to handle bool vectors. |
--- |
| 13207 |
if (N0.getValueType() == MVT::i1 && isBitwiseNot(N0) && N0.hasOneUse() && |
0 |
13207 |
if (N0.getValueType() == MVT::i1 && isBitwiseNot(N0) && N0.hasOneUse() && |
0 |
| 13208 |
(!LegalOperations || (TLI.isOperationLegal(ISD::ZERO_EXTEND, VT) && |
0 |
13208 |
(!LegalOperations || (TLI.isOperationLegal(ISD::ZERO_EXTEND, VT) && |
0 |
| 13209 |
TLI.isOperationLegal(ISD::ADD, VT)))) { |
0 |
13209 |
TLI.isOperationLegal(ISD::ADD, VT)))) { |
0 |
| 13210 |
// If we can eliminate the 'not', the sext form should be better |
--- |
13210 |
// If we can eliminate the 'not', the sext form should be better |
--- |
| 13211 |
if (SDValue NewXor = visitXOR(N0.getNode())) { |
0 |
13211 |
if (SDValue NewXor = visitXOR(N0.getNode())) { |
0 |
| 13212 |
// Returning N0 is a form of in-visit replacement that may have |
--- |
13212 |
// Returning N0 is a form of in-visit replacement that may have |
--- |
| 13213 |
// invalidated N0. |
--- |
13213 |
// invalidated N0. |
--- |
| 13214 |
if (NewXor.getNode() == N0.getNode()) { |
0 |
13214 |
if (NewXor.getNode() == N0.getNode()) { |
0 |
| 13215 |
// Return SDValue here as the xor should have already been replaced in |
--- |
13215 |
// Return SDValue here as the xor should have already been replaced in |
--- |
| 13216 |
// this sext. |
--- |
13216 |
// this sext. |
--- |
| 13217 |
return SDValue(); |
0 |
13217 |
return SDValue(); |
0 |
| 13218 |
} |
--- |
13218 |
} |
--- |
| 13219 |
|
--- |
13219 |
|
--- |
| 13220 |
// Return a new sext with the new xor. |
--- |
13220 |
// Return a new sext with the new xor. |
--- |
| 13221 |
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, NewXor); |
0 |
13221 |
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, NewXor); |
0 |
| 13222 |
} |
--- |
13222 |
} |
--- |
| 13223 |
|
--- |
13223 |
|
--- |
| 13224 |
SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); |
0 |
13224 |
SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); |
0 |
| 13225 |
return DAG.getNode(ISD::ADD, DL, VT, Zext, DAG.getAllOnesConstant(DL, VT)); |
0 |
13225 |
return DAG.getNode(ISD::ADD, DL, VT, Zext, DAG.getAllOnesConstant(DL, VT)); |
0 |
| 13226 |
} |
--- |
13226 |
} |
--- |
| 13227 |
|
--- |
13227 |
|
--- |
| 13228 |
if (SDValue Res = tryToFoldExtendSelectLoad(N, TLI, DAG, Level)) |
0 |
13228 |
if (SDValue Res = tryToFoldExtendSelectLoad(N, TLI, DAG, Level)) |
0 |
| 13229 |
return Res; |
0 |
13229 |
return Res; |
0 |
| 13230 |
|
--- |
13230 |
|
--- |
| 13231 |
return SDValue(); |
0 |
13231 |
return SDValue(); |
0 |
| 13232 |
} |
0 |
13232 |
} |
0 |
| 13233 |
|
--- |
13233 |
|
--- |
| 13234 |
/// Given an extending node with a pop-count operand, if the target does not |
--- |
13234 |
/// Given an extending node with a pop-count operand, if the target does not |
--- |
| 13235 |
/// support a pop-count in the narrow source type but does support it in the |
--- |
13235 |
/// support a pop-count in the narrow source type but does support it in the |
--- |
| 13236 |
/// destination type, widen the pop-count to the destination type. |
--- |
13236 |
/// destination type, widen the pop-count to the destination type. |
--- |
| 13237 |
static SDValue widenCtPop(SDNode *Extend, SelectionDAG &DAG) { |
0 |
13237 |
static SDValue widenCtPop(SDNode *Extend, SelectionDAG &DAG) { |
0 |
| 13238 |
assert((Extend->getOpcode() == ISD::ZERO_EXTEND || |
0 |
13238 |
assert((Extend->getOpcode() == ISD::ZERO_EXTEND || |
0 |
| 13239 |
Extend->getOpcode() == ISD::ANY_EXTEND) && "Expected extend op"); |
--- |
13239 |
Extend->getOpcode() == ISD::ANY_EXTEND) && "Expected extend op"); |
--- |
| 13240 |
|
--- |
13240 |
|
--- |
| 13241 |
SDValue CtPop = Extend->getOperand(0); |
0 |
13241 |
SDValue CtPop = Extend->getOperand(0); |
0 |
| 13242 |
if (CtPop.getOpcode() != ISD::CTPOP || !CtPop.hasOneUse()) |
0 |
13242 |
if (CtPop.getOpcode() != ISD::CTPOP || !CtPop.hasOneUse()) |
0 |
| 13243 |
return SDValue(); |
0 |
13243 |
return SDValue(); |
0 |
| 13244 |
|
--- |
13244 |
|
--- |
| 13245 |
EVT VT = Extend->getValueType(0); |
0 |
13245 |
EVT VT = Extend->getValueType(0); |
0 |
| 13246 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
13246 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 13247 |
if (TLI.isOperationLegalOrCustom(ISD::CTPOP, CtPop.getValueType()) || |
0 |
13247 |
if (TLI.isOperationLegalOrCustom(ISD::CTPOP, CtPop.getValueType()) || |
0 |
| 13248 |
!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT)) |
0 |
13248 |
!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT)) |
0 |
| 13249 |
return SDValue(); |
0 |
13249 |
return SDValue(); |
0 |
| 13250 |
|
--- |
13250 |
|
--- |
| 13251 |
// zext (ctpop X) --> ctpop (zext X) |
--- |
13251 |
// zext (ctpop X) --> ctpop (zext X) |
--- |
| 13252 |
SDLoc DL(Extend); |
0 |
13252 |
SDLoc DL(Extend); |
0 |
| 13253 |
SDValue NewZext = DAG.getZExtOrTrunc(CtPop.getOperand(0), DL, VT); |
0 |
13253 |
SDValue NewZext = DAG.getZExtOrTrunc(CtPop.getOperand(0), DL, VT); |
0 |
| 13254 |
return DAG.getNode(ISD::CTPOP, DL, VT, NewZext); |
0 |
13254 |
return DAG.getNode(ISD::CTPOP, DL, VT, NewZext); |
0 |
| 13255 |
} |
0 |
13255 |
} |
0 |
| 13256 |
|
--- |
13256 |
|
--- |
| 13257 |
// If we have (zext (abs X)) where X is a type that will be promoted by type |
--- |
13257 |
// If we have (zext (abs X)) where X is a type that will be promoted by type |
--- |
| 13258 |
// legalization, convert to (abs (sext X)). But don't extend past a legal type. |
--- |
13258 |
// legalization, convert to (abs (sext X)). But don't extend past a legal type. |
--- |
| 13259 |
static SDValue widenAbs(SDNode *Extend, SelectionDAG &DAG) { |
0 |
13259 |
static SDValue widenAbs(SDNode *Extend, SelectionDAG &DAG) { |
0 |
| 13260 |
assert(Extend->getOpcode() == ISD::ZERO_EXTEND && "Expected zero extend."); |
0 |
13260 |
assert(Extend->getOpcode() == ISD::ZERO_EXTEND && "Expected zero extend."); |
0 |
| 13261 |
|
--- |
13261 |
|
--- |
| 13262 |
EVT VT = Extend->getValueType(0); |
0 |
13262 |
EVT VT = Extend->getValueType(0); |
0 |
| 13263 |
if (VT.isVector()) |
0 |
13263 |
if (VT.isVector()) |
0 |
| 13264 |
return SDValue(); |
0 |
13264 |
return SDValue(); |
0 |
| 13265 |
|
--- |
13265 |
|
--- |
| 13266 |
SDValue Abs = Extend->getOperand(0); |
0 |
13266 |
SDValue Abs = Extend->getOperand(0); |
0 |
| 13267 |
if (Abs.getOpcode() != ISD::ABS || !Abs.hasOneUse()) |
0 |
13267 |
if (Abs.getOpcode() != ISD::ABS || !Abs.hasOneUse()) |
0 |
| 13268 |
return SDValue(); |
0 |
13268 |
return SDValue(); |
0 |
| 13269 |
|
--- |
13269 |
|
--- |
| 13270 |
EVT AbsVT = Abs.getValueType(); |
0 |
13270 |
EVT AbsVT = Abs.getValueType(); |
0 |
| 13271 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
13271 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 13272 |
if (TLI.getTypeAction(*DAG.getContext(), AbsVT) != |
0 |
13272 |
if (TLI.getTypeAction(*DAG.getContext(), AbsVT) != |
0 |
| 13273 |
TargetLowering::TypePromoteInteger) |
--- |
13273 |
TargetLowering::TypePromoteInteger) |
--- |
| 13274 |
return SDValue(); |
0 |
13274 |
return SDValue(); |
0 |
| 13275 |
|
--- |
13275 |
|
--- |
| 13276 |
EVT LegalVT = TLI.getTypeToTransformTo(*DAG.getContext(), AbsVT); |
0 |
13276 |
EVT LegalVT = TLI.getTypeToTransformTo(*DAG.getContext(), AbsVT); |
0 |
| 13277 |
|
--- |
13277 |
|
--- |
| 13278 |
SDValue SExt = |
--- |
13278 |
SDValue SExt = |
--- |
| 13279 |
DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Abs), LegalVT, Abs.getOperand(0)); |
0 |
13279 |
DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Abs), LegalVT, Abs.getOperand(0)); |
0 |
| 13280 |
SDValue NewAbs = DAG.getNode(ISD::ABS, SDLoc(Abs), LegalVT, SExt); |
0 |
13280 |
SDValue NewAbs = DAG.getNode(ISD::ABS, SDLoc(Abs), LegalVT, SExt); |
0 |
| 13281 |
return DAG.getZExtOrTrunc(NewAbs, SDLoc(Extend), VT); |
0 |
13281 |
return DAG.getZExtOrTrunc(NewAbs, SDLoc(Extend), VT); |
0 |
| 13282 |
} |
--- |
13282 |
} |
--- |
| 13283 |
|
--- |
13283 |
|
--- |
| 13284 |
SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { |
0 |
13284 |
SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { |
0 |
| 13285 |
SDValue N0 = N->getOperand(0); |
0 |
13285 |
SDValue N0 = N->getOperand(0); |
0 |
| 13286 |
EVT VT = N->getValueType(0); |
0 |
13286 |
EVT VT = N->getValueType(0); |
0 |
| 13287 |
SDLoc DL(N); |
0 |
13287 |
SDLoc DL(N); |
0 |
| 13288 |
|
--- |
13288 |
|
--- |
| 13289 |
if (VT.isVector()) |
0 |
13289 |
if (VT.isVector()) |
0 |
| 13290 |
if (SDValue FoldedVOp = SimplifyVCastOp(N, DL)) |
0 |
13290 |
if (SDValue FoldedVOp = SimplifyVCastOp(N, DL)) |
0 |
| 13291 |
return FoldedVOp; |
0 |
13291 |
return FoldedVOp; |
0 |
| 13292 |
|
--- |
13292 |
|
--- |
| 13293 |
// zext(undef) = 0 |
--- |
13293 |
// zext(undef) = 0 |
--- |
| 13294 |
if (N0.isUndef()) |
0 |
13294 |
if (N0.isUndef()) |
0 |
| 13295 |
return DAG.getConstant(0, DL, VT); |
0 |
13295 |
return DAG.getConstant(0, DL, VT); |
0 |
| 13296 |
|
--- |
13296 |
|
--- |
| 13297 |
if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes)) |
0 |
13297 |
if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes)) |
0 |
| 13298 |
return Res; |
0 |
13298 |
return Res; |
0 |
| 13299 |
|
--- |
13299 |
|
--- |
| 13300 |
// fold (zext (zext x)) -> (zext x) |
--- |
13300 |
// fold (zext (zext x)) -> (zext x) |
--- |
| 13301 |
// fold (zext (aext x)) -> (zext x) |
--- |
13301 |
// fold (zext (aext x)) -> (zext x) |
--- |
| 13302 |
if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) |
0 |
13302 |
if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) |
0 |
| 13303 |
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); |
0 |
13303 |
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); |
0 |
| 13304 |
|
--- |
13304 |
|
--- |
| 13305 |
// fold (zext (aext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x) |
--- |
13305 |
// fold (zext (aext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x) |
--- |
| 13306 |
// fold (zext (zext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x) |
--- |
13306 |
// fold (zext (zext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x) |
--- |
| 13307 |
if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || |
0 |
13307 |
if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || |
0 |
| 13308 |
N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) |
0 |
13308 |
N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) |
0 |
| 13309 |
return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(N), VT, |
0 |
13309 |
return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(N), VT, |
0 |
| 13310 |
N0.getOperand(0)); |
0 |
13310 |
N0.getOperand(0)); |
0 |
| 13311 |
|
--- |
13311 |
|
--- |
| 13312 |
// fold (zext (truncate x)) -> (zext x) or |
--- |
13312 |
// fold (zext (truncate x)) -> (zext x) or |
--- |
| 13313 |
// (zext (truncate x)) -> (truncate x) |
--- |
13313 |
// (zext (truncate x)) -> (truncate x) |
--- |
| 13314 |
// This is valid when the truncated bits of x are already zero. |
--- |
13314 |
// This is valid when the truncated bits of x are already zero. |
--- |
| 13315 |
SDValue Op; |
0 |
13315 |
SDValue Op; |
0 |
| 13316 |
KnownBits Known; |
0 |
13316 |
KnownBits Known; |
0 |
| 13317 |
if (isTruncateOf(DAG, N0, Op, Known)) { |
0 |
13317 |
if (isTruncateOf(DAG, N0, Op, Known)) { |
0 |
| 13318 |
APInt TruncatedBits = |
--- |
13318 |
APInt TruncatedBits = |
--- |
| 13319 |
(Op.getScalarValueSizeInBits() == N0.getScalarValueSizeInBits()) ? |
0 |
13319 |
(Op.getScalarValueSizeInBits() == N0.getScalarValueSizeInBits()) ? |
0 |
| 13320 |
APInt(Op.getScalarValueSizeInBits(), 0) : |
0 |
13320 |
APInt(Op.getScalarValueSizeInBits(), 0) : |
0 |
| 13321 |
APInt::getBitsSet(Op.getScalarValueSizeInBits(), |
0 |
13321 |
APInt::getBitsSet(Op.getScalarValueSizeInBits(), |
0 |
| 13322 |
N0.getScalarValueSizeInBits(), |
0 |
13322 |
N0.getScalarValueSizeInBits(), |
0 |
| 13323 |
std::min(Op.getScalarValueSizeInBits(), |
0 |
13323 |
std::min(Op.getScalarValueSizeInBits(), |
0 |
| 13324 |
VT.getScalarSizeInBits())); |
0 |
13324 |
VT.getScalarSizeInBits())); |
0 |
| 13325 |
if (TruncatedBits.isSubsetOf(Known.Zero)) |
0 |
13325 |
if (TruncatedBits.isSubsetOf(Known.Zero)) |
0 |
| 13326 |
return DAG.getZExtOrTrunc(Op, DL, VT); |
0 |
13326 |
return DAG.getZExtOrTrunc(Op, DL, VT); |
0 |
| 13327 |
} |
0 |
13327 |
} |
0 |
| 13328 |
|
--- |
13328 |
|
--- |
| 13329 |
// fold (zext (truncate x)) -> (and x, mask) |
--- |
13329 |
// fold (zext (truncate x)) -> (and x, mask) |
--- |
| 13330 |
if (N0.getOpcode() == ISD::TRUNCATE) { |
0 |
13330 |
if (N0.getOpcode() == ISD::TRUNCATE) { |
0 |
| 13331 |
// fold (zext (truncate (load x))) -> (zext (smaller load x)) |
--- |
13331 |
// fold (zext (truncate (load x))) -> (zext (smaller load x)) |
--- |
| 13332 |
// fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) |
--- |
13332 |
// fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) |
--- |
| 13333 |
if (SDValue NarrowLoad = reduceLoadWidth(N0.getNode())) { |
0 |
13333 |
if (SDValue NarrowLoad = reduceLoadWidth(N0.getNode())) { |
0 |
| 13334 |
SDNode *oye = N0.getOperand(0).getNode(); |
0 |
13334 |
SDNode *oye = N0.getOperand(0).getNode(); |
0 |
| 13335 |
if (NarrowLoad.getNode() != N0.getNode()) { |
0 |
13335 |
if (NarrowLoad.getNode() != N0.getNode()) { |
0 |
| 13336 |
CombineTo(N0.getNode(), NarrowLoad); |
0 |
13336 |
CombineTo(N0.getNode(), NarrowLoad); |
0 |
| 13337 |
// CombineTo deleted the truncate, if needed, but not what's under it. |
--- |
13337 |
// CombineTo deleted the truncate, if needed, but not what's under it. |
--- |
| 13338 |
AddToWorklist(oye); |
0 |
13338 |
AddToWorklist(oye); |
0 |
| 13339 |
} |
--- |
13339 |
} |
--- |
| 13340 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
13340 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 13341 |
} |
--- |
13341 |
} |
--- |
| 13342 |
|
--- |
13342 |
|
--- |
| 13343 |
EVT SrcVT = N0.getOperand(0).getValueType(); |
0 |
13343 |
EVT SrcVT = N0.getOperand(0).getValueType(); |
0 |
| 13344 |
EVT MinVT = N0.getValueType(); |
0 |
13344 |
EVT MinVT = N0.getValueType(); |
0 |
| 13345 |
|
--- |
13345 |
|
--- |
| 13346 |
// Try to mask before the extension to avoid having to generate a larger mask, |
--- |
13346 |
// Try to mask before the extension to avoid having to generate a larger mask, |
--- |
| 13347 |
// possibly over several sub-vectors. |
--- |
13347 |
// possibly over several sub-vectors. |
--- |
| 13348 |
if (SrcVT.bitsLT(VT) && VT.isVector()) { |
0 |
13348 |
if (SrcVT.bitsLT(VT) && VT.isVector()) { |
0 |
| 13349 |
if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) && |
0 |
13349 |
if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) && |
0 |
| 13350 |
TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) { |
0 |
13350 |
TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) { |
0 |
| 13351 |
SDValue Op = N0.getOperand(0); |
0 |
13351 |
SDValue Op = N0.getOperand(0); |
0 |
| 13352 |
Op = DAG.getZeroExtendInReg(Op, DL, MinVT); |
0 |
13352 |
Op = DAG.getZeroExtendInReg(Op, DL, MinVT); |
0 |
| 13353 |
AddToWorklist(Op.getNode()); |
0 |
13353 |
AddToWorklist(Op.getNode()); |
0 |
| 13354 |
SDValue ZExtOrTrunc = DAG.getZExtOrTrunc(Op, DL, VT); |
0 |
13354 |
SDValue ZExtOrTrunc = DAG.getZExtOrTrunc(Op, DL, VT); |
0 |
| 13355 |
// Transfer the debug info; the new node is equivalent to N0. |
--- |
13355 |
// Transfer the debug info; the new node is equivalent to N0. |
--- |
| 13356 |
DAG.transferDbgValues(N0, ZExtOrTrunc); |
0 |
13356 |
DAG.transferDbgValues(N0, ZExtOrTrunc); |
0 |
| 13357 |
return ZExtOrTrunc; |
0 |
13357 |
return ZExtOrTrunc; |
0 |
| 13358 |
} |
--- |
13358 |
} |
--- |
| 13359 |
} |
--- |
13359 |
} |
--- |
| 13360 |
|
--- |
13360 |
|
--- |
| 13361 |
if (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) { |
0 |
13361 |
if (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) { |
0 |
| 13362 |
SDValue Op = DAG.getAnyExtOrTrunc(N0.getOperand(0), DL, VT); |
0 |
13362 |
SDValue Op = DAG.getAnyExtOrTrunc(N0.getOperand(0), DL, VT); |
0 |
| 13363 |
AddToWorklist(Op.getNode()); |
0 |
13363 |
AddToWorklist(Op.getNode()); |
0 |
| 13364 |
SDValue And = DAG.getZeroExtendInReg(Op, DL, MinVT); |
0 |
13364 |
SDValue And = DAG.getZeroExtendInReg(Op, DL, MinVT); |
0 |
| 13365 |
// We may safely transfer the debug info describing the truncate node over |
--- |
13365 |
// We may safely transfer the debug info describing the truncate node over |
--- |
| 13366 |
// to the equivalent and operation. |
--- |
13366 |
// to the equivalent and operation. |
--- |
| 13367 |
DAG.transferDbgValues(N0, And); |
0 |
13367 |
DAG.transferDbgValues(N0, And); |
0 |
| 13368 |
return And; |
0 |
13368 |
return And; |
0 |
| 13369 |
} |
--- |
13369 |
} |
--- |
| 13370 |
} |
--- |
13370 |
} |
--- |
| 13371 |
|
--- |
13371 |
|
--- |
| 13372 |
// Fold (zext (and (trunc x), cst)) -> (and x, cst), |
--- |
13372 |
// Fold (zext (and (trunc x), cst)) -> (and x, cst), |
--- |
| 13373 |
// if either of the casts is not free. |
--- |
13373 |
// if either of the casts is not free. |
--- |
| 13374 |
if (N0.getOpcode() == ISD::AND && |
0 |
13374 |
if (N0.getOpcode() == ISD::AND && |
0 |
| 13375 |
N0.getOperand(0).getOpcode() == ISD::TRUNCATE && |
0 |
13375 |
N0.getOperand(0).getOpcode() == ISD::TRUNCATE && |
0 |
| 13376 |
N0.getOperand(1).getOpcode() == ISD::Constant && |
0 |
13376 |
N0.getOperand(1).getOpcode() == ISD::Constant && |
0 |
| 13377 |
(!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), |
0 |
13377 |
(!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), |
0 |
| 13378 |
N0.getValueType()) || |
0 |
13378 |
N0.getValueType()) || |
0 |
| 13379 |
!TLI.isZExtFree(N0.getValueType(), VT))) { |
0 |
13379 |
!TLI.isZExtFree(N0.getValueType(), VT))) { |
0 |
| 13380 |
SDValue X = N0.getOperand(0).getOperand(0); |
0 |
13380 |
SDValue X = N0.getOperand(0).getOperand(0); |
0 |
| 13381 |
X = DAG.getAnyExtOrTrunc(X, SDLoc(X), VT); |
0 |
13381 |
X = DAG.getAnyExtOrTrunc(X, SDLoc(X), VT); |
0 |
| 13382 |
APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits()); |
0 |
13382 |
APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits()); |
0 |
| 13383 |
return DAG.getNode(ISD::AND, DL, VT, |
0 |
13383 |
return DAG.getNode(ISD::AND, DL, VT, |
0 |
| 13384 |
X, DAG.getConstant(Mask, DL, VT)); |
0 |
13384 |
X, DAG.getConstant(Mask, DL, VT)); |
0 |
| 13385 |
} |
0 |
13385 |
} |
0 |
| 13386 |
|
--- |
13386 |
|
--- |
| 13387 |
// Try to simplify (zext (load x)). |
--- |
13387 |
// Try to simplify (zext (load x)). |
--- |
| 13388 |
if (SDValue foldedExt = |
0 |
13388 |
if (SDValue foldedExt = |
0 |
| 13389 |
tryToFoldExtOfLoad(DAG, *this, TLI, VT, LegalOperations, N, N0, |
0 |
13389 |
tryToFoldExtOfLoad(DAG, *this, TLI, VT, LegalOperations, N, N0, |
0 |
| 13390 |
ISD::ZEXTLOAD, ISD::ZERO_EXTEND)) |
0 |
13390 |
ISD::ZEXTLOAD, ISD::ZERO_EXTEND)) |
0 |
| 13391 |
return foldedExt; |
0 |
13391 |
return foldedExt; |
0 |
| 13392 |
|
--- |
13392 |
|
--- |
| 13393 |
if (SDValue foldedExt = |
0 |
13393 |
if (SDValue foldedExt = |
0 |
| 13394 |
tryToFoldExtOfMaskedLoad(DAG, TLI, VT, N, N0, ISD::ZEXTLOAD, |
0 |
13394 |
tryToFoldExtOfMaskedLoad(DAG, TLI, VT, N, N0, ISD::ZEXTLOAD, |
0 |
| 13395 |
ISD::ZERO_EXTEND)) |
0 |
13395 |
ISD::ZERO_EXTEND)) |
0 |
| 13396 |
return foldedExt; |
0 |
13396 |
return foldedExt; |
0 |
| 13397 |
|
--- |
13397 |
|
--- |
| 13398 |
// fold (zext (load x)) to multiple smaller zextloads. |
--- |
13398 |
// fold (zext (load x)) to multiple smaller zextloads. |
--- |
| 13399 |
// Only on illegal but splittable vectors. |
--- |
13399 |
// Only on illegal but splittable vectors. |
--- |
| 13400 |
if (SDValue ExtLoad = CombineExtLoad(N)) |
0 |
13400 |
if (SDValue ExtLoad = CombineExtLoad(N)) |
0 |
| 13401 |
return ExtLoad; |
0 |
13401 |
return ExtLoad; |
0 |
| 13402 |
|
--- |
13402 |
|
--- |
| 13403 |
// fold (zext (and/or/xor (load x), cst)) -> |
--- |
13403 |
// fold (zext (and/or/xor (load x), cst)) -> |
--- |
| 13404 |
// (and/or/xor (zextload x), (zext cst)) |
--- |
13404 |
// (and/or/xor (zextload x), (zext cst)) |
--- |
| 13405 |
// Unless (and (load x) cst) will match as a zextload already and has |
--- |
13405 |
// Unless (and (load x) cst) will match as a zextload already and has |
--- |
| 13406 |
// additional users. |
--- |
13406 |
// additional users. |
--- |
| 13407 |
if (ISD::isBitwiseLogicOp(N0.getOpcode()) && |
0 |
13407 |
if (ISD::isBitwiseLogicOp(N0.getOpcode()) && |
0 |
| 13408 |
isa(N0.getOperand(0)) && |
0 |
13408 |
isa(N0.getOperand(0)) && |
0 |
| 13409 |
N0.getOperand(1).getOpcode() == ISD::Constant && |
0 |
13409 |
N0.getOperand(1).getOpcode() == ISD::Constant && |
0 |
| 13410 |
(!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { |
0 |
13410 |
(!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { |
0 |
| 13411 |
LoadSDNode *LN00 = cast(N0.getOperand(0)); |
0 |
13411 |
LoadSDNode *LN00 = cast(N0.getOperand(0)); |
0 |
| 13412 |
EVT MemVT = LN00->getMemoryVT(); |
0 |
13412 |
EVT MemVT = LN00->getMemoryVT(); |
0 |
| 13413 |
if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT) && |
0 |
13413 |
if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT) && |
0 |
| 13414 |
LN00->getExtensionType() != ISD::SEXTLOAD && LN00->isUnindexed()) { |
0 |
13414 |
LN00->getExtensionType() != ISD::SEXTLOAD && LN00->isUnindexed()) { |
0 |
| 13415 |
bool DoXform = true; |
0 |
13415 |
bool DoXform = true; |
0 |
| 13416 |
SmallVector SetCCs; |
0 |
13416 |
SmallVector SetCCs; |
0 |
| 13417 |
if (!N0.hasOneUse()) { |
0 |
13417 |
if (!N0.hasOneUse()) { |
0 |
| 13418 |
if (N0.getOpcode() == ISD::AND) { |
0 |
13418 |
if (N0.getOpcode() == ISD::AND) { |
0 |
| 13419 |
auto *AndC = cast(N0.getOperand(1)); |
0 |
13419 |
auto *AndC = cast(N0.getOperand(1)); |
0 |
| 13420 |
EVT LoadResultTy = AndC->getValueType(0); |
0 |
13420 |
EVT LoadResultTy = AndC->getValueType(0); |
0 |
| 13421 |
EVT ExtVT; |
0 |
13421 |
EVT ExtVT; |
0 |
| 13422 |
if (isAndLoadExtLoad(AndC, LN00, LoadResultTy, ExtVT)) |
0 |
13422 |
if (isAndLoadExtLoad(AndC, LN00, LoadResultTy, ExtVT)) |
0 |
| 13423 |
DoXform = false; |
0 |
13423 |
DoXform = false; |
0 |
| 13424 |
} |
--- |
13424 |
} |
--- |
| 13425 |
} |
--- |
13425 |
} |
--- |
| 13426 |
if (DoXform) |
0 |
13426 |
if (DoXform) |
0 |
| 13427 |
DoXform = ExtendUsesToFormExtLoad(VT, N0.getNode(), N0.getOperand(0), |
0 |
13427 |
DoXform = ExtendUsesToFormExtLoad(VT, N0.getNode(), N0.getOperand(0), |
0 |
| 13428 |
ISD::ZERO_EXTEND, SetCCs, TLI); |
--- |
13428 |
ISD::ZERO_EXTEND, SetCCs, TLI); |
--- |
| 13429 |
if (DoXform) { |
0 |
13429 |
if (DoXform) { |
0 |
| 13430 |
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN00), VT, |
0 |
13430 |
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN00), VT, |
0 |
| 13431 |
LN00->getChain(), LN00->getBasePtr(), |
0 |
13431 |
LN00->getChain(), LN00->getBasePtr(), |
0 |
| 13432 |
LN00->getMemoryVT(), |
--- |
13432 |
LN00->getMemoryVT(), |
--- |
| 13433 |
LN00->getMemOperand()); |
--- |
13433 |
LN00->getMemOperand()); |
--- |
| 13434 |
APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits()); |
0 |
13434 |
APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits()); |
0 |
| 13435 |
SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, |
0 |
13435 |
SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, |
0 |
| 13436 |
ExtLoad, DAG.getConstant(Mask, DL, VT)); |
0 |
13436 |
ExtLoad, DAG.getConstant(Mask, DL, VT)); |
0 |
| 13437 |
ExtendSetCCUses(SetCCs, N0.getOperand(0), ExtLoad, ISD::ZERO_EXTEND); |
0 |
13437 |
ExtendSetCCUses(SetCCs, N0.getOperand(0), ExtLoad, ISD::ZERO_EXTEND); |
0 |
| 13438 |
bool NoReplaceTruncAnd = !N0.hasOneUse(); |
0 |
13438 |
bool NoReplaceTruncAnd = !N0.hasOneUse(); |
0 |
| 13439 |
bool NoReplaceTrunc = SDValue(LN00, 0).hasOneUse(); |
0 |
13439 |
bool NoReplaceTrunc = SDValue(LN00, 0).hasOneUse(); |
0 |
| 13440 |
CombineTo(N, And); |
0 |
13440 |
CombineTo(N, And); |
0 |
| 13441 |
// If N0 has multiple uses, change other uses as well. |
--- |
13441 |
// If N0 has multiple uses, change other uses as well. |
--- |
| 13442 |
if (NoReplaceTruncAnd) { |
0 |
13442 |
if (NoReplaceTruncAnd) { |
0 |
| 13443 |
SDValue TruncAnd = |
--- |
13443 |
SDValue TruncAnd = |
--- |
| 13444 |
DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), And); |
0 |
13444 |
DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), And); |
0 |
| 13445 |
CombineTo(N0.getNode(), TruncAnd); |
0 |
13445 |
CombineTo(N0.getNode(), TruncAnd); |
0 |
| 13446 |
} |
--- |
13446 |
} |
--- |
| 13447 |
if (NoReplaceTrunc) { |
0 |
13447 |
if (NoReplaceTrunc) { |
0 |
| 13448 |
DAG.ReplaceAllUsesOfValueWith(SDValue(LN00, 1), ExtLoad.getValue(1)); |
0 |
13448 |
DAG.ReplaceAllUsesOfValueWith(SDValue(LN00, 1), ExtLoad.getValue(1)); |
0 |
| 13449 |
} else { |
--- |
13449 |
} else { |
--- |
| 13450 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(LN00), |
0 |
13450 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(LN00), |
0 |
| 13451 |
LN00->getValueType(0), ExtLoad); |
--- |
13451 |
LN00->getValueType(0), ExtLoad); |
--- |
| 13452 |
CombineTo(LN00, Trunc, ExtLoad.getValue(1)); |
0 |
13452 |
CombineTo(LN00, Trunc, ExtLoad.getValue(1)); |
0 |
| 13453 |
} |
--- |
13453 |
} |
--- |
| 13454 |
return SDValue(N,0); // Return N so it doesn't get rechecked! |
0 |
13454 |
return SDValue(N,0); // Return N so it doesn't get rechecked! |
0 |
| 13455 |
} |
0 |
13455 |
} |
0 |
| 13456 |
} |
0 |
13456 |
} |
0 |
| 13457 |
} |
--- |
13457 |
} |
--- |
| 13458 |
|
--- |
13458 |
|
--- |
| 13459 |
// fold (zext (and/or/xor (shl/shr (load x), cst), cst)) -> |
--- |
13459 |
// fold (zext (and/or/xor (shl/shr (load x), cst), cst)) -> |
--- |
| 13460 |
// (and/or/xor (shl/shr (zextload x), (zext cst)), (zext cst)) |
--- |
13460 |
// (and/or/xor (shl/shr (zextload x), (zext cst)), (zext cst)) |
--- |
| 13461 |
if (SDValue ZExtLoad = CombineZExtLogicopShiftLoad(N)) |
0 |
13461 |
if (SDValue ZExtLoad = CombineZExtLogicopShiftLoad(N)) |
0 |
| 13462 |
return ZExtLoad; |
0 |
13462 |
return ZExtLoad; |
0 |
| 13463 |
|
--- |
13463 |
|
--- |
| 13464 |
// Try to simplify (zext (zextload x)). |
--- |
13464 |
// Try to simplify (zext (zextload x)). |
--- |
| 13465 |
if (SDValue foldedExt = tryToFoldExtOfExtload( |
0 |
13465 |
if (SDValue foldedExt = tryToFoldExtOfExtload( |
0 |
| 13466 |
DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::ZEXTLOAD)) |
0 |
13466 |
DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::ZEXTLOAD)) |
0 |
| 13467 |
return foldedExt; |
0 |
13467 |
return foldedExt; |
0 |
| 13468 |
|
--- |
13468 |
|
--- |
| 13469 |
if (SDValue V = foldExtendedSignBitTest(N, DAG, LegalOperations)) |
0 |
13469 |
if (SDValue V = foldExtendedSignBitTest(N, DAG, LegalOperations)) |
0 |
| 13470 |
return V; |
0 |
13470 |
return V; |
0 |
| 13471 |
|
--- |
13471 |
|
--- |
| 13472 |
if (N0.getOpcode() == ISD::SETCC) { |
0 |
13472 |
if (N0.getOpcode() == ISD::SETCC) { |
0 |
| 13473 |
// Propagate fast-math-flags. |
--- |
13473 |
// Propagate fast-math-flags. |
--- |
| 13474 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags()); |
0 |
13474 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags()); |
0 |
| 13475 |
|
--- |
13475 |
|
--- |
| 13476 |
// Only do this before legalize for now. |
--- |
13476 |
// Only do this before legalize for now. |
--- |
| 13477 |
if (!LegalOperations && VT.isVector() && |
0 |
13477 |
if (!LegalOperations && VT.isVector() && |
0 |
| 13478 |
N0.getValueType().getVectorElementType() == MVT::i1) { |
0 |
13478 |
N0.getValueType().getVectorElementType() == MVT::i1) { |
0 |
| 13479 |
EVT N00VT = N0.getOperand(0).getValueType(); |
0 |
13479 |
EVT N00VT = N0.getOperand(0).getValueType(); |
0 |
| 13480 |
if (getSetCCResultType(N00VT) == N0.getValueType()) |
0 |
13480 |
if (getSetCCResultType(N00VT) == N0.getValueType()) |
0 |
| 13481 |
return SDValue(); |
0 |
13481 |
return SDValue(); |
0 |
| 13482 |
|
--- |
13482 |
|
--- |
| 13483 |
// We know that the # elements of the results is the same as the # |
--- |
13483 |
// We know that the # elements of the results is the same as the # |
--- |
| 13484 |
// elements of the compare (and the # elements of the compare result for |
--- |
13484 |
// elements of the compare (and the # elements of the compare result for |
--- |
| 13485 |
// that matter). Check to see that they are the same size. If so, we know |
--- |
13485 |
// that matter). Check to see that they are the same size. If so, we know |
--- |
| 13486 |
// that the element size of the sext'd result matches the element size of |
--- |
13486 |
// that the element size of the sext'd result matches the element size of |
--- |
| 13487 |
// the compare operands. |
--- |
13487 |
// the compare operands. |
--- |
| 13488 |
if (VT.getSizeInBits() == N00VT.getSizeInBits()) { |
0 |
13488 |
if (VT.getSizeInBits() == N00VT.getSizeInBits()) { |
0 |
| 13489 |
// zext(setcc) -> zext_in_reg(vsetcc) for vectors. |
--- |
13489 |
// zext(setcc) -> zext_in_reg(vsetcc) for vectors. |
--- |
| 13490 |
SDValue VSetCC = DAG.getNode(ISD::SETCC, DL, VT, N0.getOperand(0), |
0 |
13490 |
SDValue VSetCC = DAG.getNode(ISD::SETCC, DL, VT, N0.getOperand(0), |
0 |
| 13491 |
N0.getOperand(1), N0.getOperand(2)); |
0 |
13491 |
N0.getOperand(1), N0.getOperand(2)); |
0 |
| 13492 |
return DAG.getZeroExtendInReg(VSetCC, DL, N0.getValueType()); |
0 |
13492 |
return DAG.getZeroExtendInReg(VSetCC, DL, N0.getValueType()); |
0 |
| 13493 |
} |
--- |
13493 |
} |
--- |
| 13494 |
|
--- |
13494 |
|
--- |
| 13495 |
// If the desired elements are smaller or larger than the source |
--- |
13495 |
// If the desired elements are smaller or larger than the source |
--- |
| 13496 |
// elements we can use a matching integer vector type and then |
--- |
13496 |
// elements we can use a matching integer vector type and then |
--- |
| 13497 |
// truncate/any extend followed by zext_in_reg. |
--- |
13497 |
// truncate/any extend followed by zext_in_reg. |
--- |
| 13498 |
EVT MatchingVectorType = N00VT.changeVectorElementTypeToInteger(); |
0 |
13498 |
EVT MatchingVectorType = N00VT.changeVectorElementTypeToInteger(); |
0 |
| 13499 |
SDValue VsetCC = |
--- |
13499 |
SDValue VsetCC = |
--- |
| 13500 |
DAG.getNode(ISD::SETCC, DL, MatchingVectorType, N0.getOperand(0), |
0 |
13500 |
DAG.getNode(ISD::SETCC, DL, MatchingVectorType, N0.getOperand(0), |
0 |
| 13501 |
N0.getOperand(1), N0.getOperand(2)); |
0 |
13501 |
N0.getOperand(1), N0.getOperand(2)); |
0 |
| 13502 |
return DAG.getZeroExtendInReg(DAG.getAnyExtOrTrunc(VsetCC, DL, VT), DL, |
0 |
13502 |
return DAG.getZeroExtendInReg(DAG.getAnyExtOrTrunc(VsetCC, DL, VT), DL, |
0 |
| 13503 |
N0.getValueType()); |
0 |
13503 |
N0.getValueType()); |
0 |
| 13504 |
} |
--- |
13504 |
} |
--- |
| 13505 |
|
--- |
13505 |
|
--- |
| 13506 |
// zext(setcc x,y,cc) -> zext(select x, y, true, false, cc) |
--- |
13506 |
// zext(setcc x,y,cc) -> zext(select x, y, true, false, cc) |
--- |
| 13507 |
EVT N0VT = N0.getValueType(); |
0 |
13507 |
EVT N0VT = N0.getValueType(); |
0 |
| 13508 |
EVT N00VT = N0.getOperand(0).getValueType(); |
0 |
13508 |
EVT N00VT = N0.getOperand(0).getValueType(); |
0 |
| 13509 |
if (SDValue SCC = SimplifySelectCC( |
0 |
13509 |
if (SDValue SCC = SimplifySelectCC( |
0 |
| 13510 |
DL, N0.getOperand(0), N0.getOperand(1), |
0 |
13510 |
DL, N0.getOperand(0), N0.getOperand(1), |
0 |
| 13511 |
DAG.getBoolConstant(true, DL, N0VT, N00VT), |
0 |
13511 |
DAG.getBoolConstant(true, DL, N0VT, N00VT), |
0 |
| 13512 |
DAG.getBoolConstant(false, DL, N0VT, N00VT), |
0 |
13512 |
DAG.getBoolConstant(false, DL, N0VT, N00VT), |
0 |
| 13513 |
cast(N0.getOperand(2))->get(), true)) |
0 |
13513 |
cast(N0.getOperand(2))->get(), true)) |
0 |
| 13514 |
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, SCC); |
0 |
13514 |
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, SCC); |
0 |
| 13515 |
} |
0 |
13515 |
} |
0 |
| 13516 |
|
--- |
13516 |
|
--- |
| 13517 |
// (zext (shl (zext x), cst)) -> (shl (zext x), cst) |
--- |
13517 |
// (zext (shl (zext x), cst)) -> (shl (zext x), cst) |
--- |
| 13518 |
if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && |
0 |
13518 |
if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && |
0 |
| 13519 |
!TLI.isZExtFree(N0, VT)) { |
0 |
13519 |
!TLI.isZExtFree(N0, VT)) { |
0 |
| 13520 |
SDValue ShVal = N0.getOperand(0); |
0 |
13520 |
SDValue ShVal = N0.getOperand(0); |
0 |
| 13521 |
SDValue ShAmt = N0.getOperand(1); |
0 |
13521 |
SDValue ShAmt = N0.getOperand(1); |
0 |
| 13522 |
if (auto *ShAmtC = dyn_cast(ShAmt)) { |
0 |
13522 |
if (auto *ShAmtC = dyn_cast(ShAmt)) { |
0 |
| 13523 |
if (ShVal.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse()) { |
0 |
13523 |
if (ShVal.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse()) { |
0 |
| 13524 |
if (N0.getOpcode() == ISD::SHL) { |
0 |
13524 |
if (N0.getOpcode() == ISD::SHL) { |
0 |
| 13525 |
// If the original shl may be shifting out bits, do not perform this |
--- |
13525 |
// If the original shl may be shifting out bits, do not perform this |
--- |
| 13526 |
// transformation. |
--- |
13526 |
// transformation. |
--- |
| 13527 |
// TODO: Add MaskedValueIsZero check. |
--- |
13527 |
// TODO: Add MaskedValueIsZero check. |
--- |
| 13528 |
unsigned KnownZeroBits = ShVal.getValueSizeInBits() - |
0 |
13528 |
unsigned KnownZeroBits = ShVal.getValueSizeInBits() - |
0 |
| 13529 |
ShVal.getOperand(0).getValueSizeInBits(); |
0 |
13529 |
ShVal.getOperand(0).getValueSizeInBits(); |
0 |
| 13530 |
if (ShAmtC->getAPIntValue().ugt(KnownZeroBits)) |
0 |
13530 |
if (ShAmtC->getAPIntValue().ugt(KnownZeroBits)) |
0 |
| 13531 |
return SDValue(); |
0 |
13531 |
return SDValue(); |
0 |
| 13532 |
} |
--- |
13532 |
} |
--- |
| 13533 |
|
--- |
13533 |
|
--- |
| 13534 |
// Ensure that the shift amount is wide enough for the shifted value. |
--- |
13534 |
// Ensure that the shift amount is wide enough for the shifted value. |
--- |
| 13535 |
if (Log2_32_Ceil(VT.getSizeInBits()) > ShAmt.getValueSizeInBits()) |
0 |
13535 |
if (Log2_32_Ceil(VT.getSizeInBits()) > ShAmt.getValueSizeInBits()) |
0 |
| 13536 |
ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); |
0 |
13536 |
ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); |
0 |
| 13537 |
|
--- |
13537 |
|
--- |
| 13538 |
return DAG.getNode(N0.getOpcode(), DL, VT, |
0 |
13538 |
return DAG.getNode(N0.getOpcode(), DL, VT, |
0 |
| 13539 |
DAG.getNode(ISD::ZERO_EXTEND, DL, VT, ShVal), ShAmt); |
0 |
13539 |
DAG.getNode(ISD::ZERO_EXTEND, DL, VT, ShVal), ShAmt); |
0 |
| 13540 |
} |
--- |
13540 |
} |
--- |
| 13541 |
} |
--- |
13541 |
} |
--- |
| 13542 |
} |
--- |
13542 |
} |
--- |
| 13543 |
|
--- |
13543 |
|
--- |
| 13544 |
if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N)) |
0 |
13544 |
if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N)) |
0 |
| 13545 |
return NewVSel; |
0 |
13545 |
return NewVSel; |
0 |
| 13546 |
|
--- |
13546 |
|
--- |
| 13547 |
if (SDValue NewCtPop = widenCtPop(N, DAG)) |
0 |
13547 |
if (SDValue NewCtPop = widenCtPop(N, DAG)) |
0 |
| 13548 |
return NewCtPop; |
0 |
13548 |
return NewCtPop; |
0 |
| 13549 |
|
--- |
13549 |
|
--- |
| 13550 |
if (SDValue V = widenAbs(N, DAG)) |
0 |
13550 |
if (SDValue V = widenAbs(N, DAG)) |
0 |
| 13551 |
return V; |
0 |
13551 |
return V; |
0 |
| 13552 |
|
--- |
13552 |
|
--- |
| 13553 |
if (SDValue Res = tryToFoldExtendSelectLoad(N, TLI, DAG, Level)) |
0 |
13553 |
if (SDValue Res = tryToFoldExtendSelectLoad(N, TLI, DAG, Level)) |
0 |
| 13554 |
return Res; |
0 |
13554 |
return Res; |
0 |
| 13555 |
|
--- |
13555 |
|
--- |
| 13556 |
return SDValue(); |
0 |
13556 |
return SDValue(); |
0 |
| 13557 |
} |
0 |
13557 |
} |
0 |
| 13558 |
|
--- |
13558 |
|
--- |
| 13559 |
SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { |
0 |
13559 |
SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { |
0 |
| 13560 |
SDValue N0 = N->getOperand(0); |
0 |
13560 |
SDValue N0 = N->getOperand(0); |
0 |
| 13561 |
EVT VT = N->getValueType(0); |
0 |
13561 |
EVT VT = N->getValueType(0); |
0 |
| 13562 |
|
--- |
13562 |
|
--- |
| 13563 |
// aext(undef) = undef |
--- |
13563 |
// aext(undef) = undef |
--- |
| 13564 |
if (N0.isUndef()) |
0 |
13564 |
if (N0.isUndef()) |
0 |
| 13565 |
return DAG.getUNDEF(VT); |
0 |
13565 |
return DAG.getUNDEF(VT); |
0 |
| 13566 |
|
--- |
13566 |
|
--- |
| 13567 |
if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes)) |
0 |
13567 |
if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes)) |
0 |
| 13568 |
return Res; |
0 |
13568 |
return Res; |
0 |
| 13569 |
|
--- |
13569 |
|
--- |
| 13570 |
// fold (aext (aext x)) -> (aext x) |
--- |
13570 |
// fold (aext (aext x)) -> (aext x) |
--- |
| 13571 |
// fold (aext (zext x)) -> (zext x) |
--- |
13571 |
// fold (aext (zext x)) -> (zext x) |
--- |
| 13572 |
// fold (aext (sext x)) -> (sext x) |
--- |
13572 |
// fold (aext (sext x)) -> (sext x) |
--- |
| 13573 |
if (N0.getOpcode() == ISD::ANY_EXTEND || |
0 |
13573 |
if (N0.getOpcode() == ISD::ANY_EXTEND || |
0 |
| 13574 |
N0.getOpcode() == ISD::ZERO_EXTEND || |
0 |
13574 |
N0.getOpcode() == ISD::ZERO_EXTEND || |
0 |
| 13575 |
N0.getOpcode() == ISD::SIGN_EXTEND) |
0 |
13575 |
N0.getOpcode() == ISD::SIGN_EXTEND) |
0 |
| 13576 |
return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); |
0 |
13576 |
return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); |
0 |
| 13577 |
|
--- |
13577 |
|
--- |
| 13578 |
// fold (aext (aext_extend_vector_inreg x)) -> (aext_extend_vector_inreg x) |
--- |
13578 |
// fold (aext (aext_extend_vector_inreg x)) -> (aext_extend_vector_inreg x) |
--- |
| 13579 |
// fold (aext (zext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x) |
--- |
13579 |
// fold (aext (zext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x) |
--- |
| 13580 |
// fold (aext (sext_extend_vector_inreg x)) -> (sext_extend_vector_inreg x) |
--- |
13580 |
// fold (aext (sext_extend_vector_inreg x)) -> (sext_extend_vector_inreg x) |
--- |
| 13581 |
if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || |
0 |
13581 |
if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || |
0 |
| 13582 |
N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG || |
0 |
13582 |
N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG || |
0 |
| 13583 |
N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) |
0 |
13583 |
N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) |
0 |
| 13584 |
return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); |
0 |
13584 |
return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); |
0 |
| 13585 |
|
--- |
13585 |
|
--- |
| 13586 |
// fold (aext (truncate (load x))) -> (aext (smaller load x)) |
--- |
13586 |
// fold (aext (truncate (load x))) -> (aext (smaller load x)) |
--- |
| 13587 |
// fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) |
--- |
13587 |
// fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) |
--- |
| 13588 |
if (N0.getOpcode() == ISD::TRUNCATE) { |
0 |
13588 |
if (N0.getOpcode() == ISD::TRUNCATE) { |
0 |
| 13589 |
if (SDValue NarrowLoad = reduceLoadWidth(N0.getNode())) { |
0 |
13589 |
if (SDValue NarrowLoad = reduceLoadWidth(N0.getNode())) { |
0 |
| 13590 |
SDNode *oye = N0.getOperand(0).getNode(); |
0 |
13590 |
SDNode *oye = N0.getOperand(0).getNode(); |
0 |
| 13591 |
if (NarrowLoad.getNode() != N0.getNode()) { |
0 |
13591 |
if (NarrowLoad.getNode() != N0.getNode()) { |
0 |
| 13592 |
CombineTo(N0.getNode(), NarrowLoad); |
0 |
13592 |
CombineTo(N0.getNode(), NarrowLoad); |
0 |
| 13593 |
// CombineTo deleted the truncate, if needed, but not what's under it. |
--- |
13593 |
// CombineTo deleted the truncate, if needed, but not what's under it. |
--- |
| 13594 |
AddToWorklist(oye); |
0 |
13594 |
AddToWorklist(oye); |
0 |
| 13595 |
} |
--- |
13595 |
} |
--- |
| 13596 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
13596 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 13597 |
} |
--- |
13597 |
} |
--- |
| 13598 |
} |
--- |
13598 |
} |
--- |
| 13599 |
|
--- |
13599 |
|
--- |
| 13600 |
// fold (aext (truncate x)) |
--- |
13600 |
// fold (aext (truncate x)) |
--- |
| 13601 |
if (N0.getOpcode() == ISD::TRUNCATE) |
0 |
13601 |
if (N0.getOpcode() == ISD::TRUNCATE) |
0 |
| 13602 |
return DAG.getAnyExtOrTrunc(N0.getOperand(0), SDLoc(N), VT); |
0 |
13602 |
return DAG.getAnyExtOrTrunc(N0.getOperand(0), SDLoc(N), VT); |
0 |
| 13603 |
|
--- |
13603 |
|
--- |
| 13604 |
// Fold (aext (and (trunc x), cst)) -> (and x, cst) |
--- |
13604 |
// Fold (aext (and (trunc x), cst)) -> (and x, cst) |
--- |
| 13605 |
// if the trunc is not free. |
--- |
13605 |
// if the trunc is not free. |
--- |
| 13606 |
if (N0.getOpcode() == ISD::AND && |
0 |
13606 |
if (N0.getOpcode() == ISD::AND && |
0 |
| 13607 |
N0.getOperand(0).getOpcode() == ISD::TRUNCATE && |
0 |
13607 |
N0.getOperand(0).getOpcode() == ISD::TRUNCATE && |
0 |
| 13608 |
N0.getOperand(1).getOpcode() == ISD::Constant && |
0 |
13608 |
N0.getOperand(1).getOpcode() == ISD::Constant && |
0 |
| 13609 |
!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), |
0 |
13609 |
!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), |
0 |
| 13610 |
N0.getValueType())) { |
--- |
13610 |
N0.getValueType())) { |
--- |
| 13611 |
SDLoc DL(N); |
0 |
13611 |
SDLoc DL(N); |
0 |
| 13612 |
SDValue X = DAG.getAnyExtOrTrunc(N0.getOperand(0).getOperand(0), DL, VT); |
0 |
13612 |
SDValue X = DAG.getAnyExtOrTrunc(N0.getOperand(0).getOperand(0), DL, VT); |
0 |
| 13613 |
SDValue Y = DAG.getNode(ISD::ANY_EXTEND, DL, VT, N0.getOperand(1)); |
0 |
13613 |
SDValue Y = DAG.getNode(ISD::ANY_EXTEND, DL, VT, N0.getOperand(1)); |
0 |
| 13614 |
assert(isa(Y) && "Expected constant to be folded!"); |
0 |
13614 |
assert(isa(Y) && "Expected constant to be folded!"); |
0 |
| 13615 |
return DAG.getNode(ISD::AND, DL, VT, X, Y); |
0 |
13615 |
return DAG.getNode(ISD::AND, DL, VT, X, Y); |
0 |
| 13616 |
} |
0 |
13616 |
} |
0 |
| 13617 |
|
--- |
13617 |
|
--- |
| 13618 |
// fold (aext (load x)) -> (aext (truncate (extload x))) |
--- |
13618 |
// fold (aext (load x)) -> (aext (truncate (extload x))) |
--- |
| 13619 |
// None of the supported targets knows how to perform load and any_ext |
--- |
13619 |
// None of the supported targets knows how to perform load and any_ext |
--- |
| 13620 |
// on vectors in one instruction, so attempt to fold to zext instead. |
--- |
13620 |
// on vectors in one instruction, so attempt to fold to zext instead. |
--- |
| 13621 |
if (VT.isVector()) { |
0 |
13621 |
if (VT.isVector()) { |
0 |
| 13622 |
// Try to simplify (zext (load x)). |
--- |
13622 |
// Try to simplify (zext (load x)). |
--- |
| 13623 |
if (SDValue foldedExt = |
0 |
13623 |
if (SDValue foldedExt = |
0 |
| 13624 |
tryToFoldExtOfLoad(DAG, *this, TLI, VT, LegalOperations, N, N0, |
0 |
13624 |
tryToFoldExtOfLoad(DAG, *this, TLI, VT, LegalOperations, N, N0, |
0 |
| 13625 |
ISD::ZEXTLOAD, ISD::ZERO_EXTEND)) |
0 |
13625 |
ISD::ZEXTLOAD, ISD::ZERO_EXTEND)) |
0 |
| 13626 |
return foldedExt; |
0 |
13626 |
return foldedExt; |
0 |
| 13627 |
} else if (ISD::isNON_EXTLoad(N0.getNode()) && |
0 |
13627 |
} else if (ISD::isNON_EXTLoad(N0.getNode()) && |
0 |
| 13628 |
ISD::isUNINDEXEDLoad(N0.getNode()) && |
0 |
13628 |
ISD::isUNINDEXEDLoad(N0.getNode()) && |
0 |
| 13629 |
TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) { |
0 |
13629 |
TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) { |
0 |
| 13630 |
bool DoXform = true; |
0 |
13630 |
bool DoXform = true; |
0 |
| 13631 |
SmallVector SetCCs; |
0 |
13631 |
SmallVector SetCCs; |
0 |
| 13632 |
if (!N0.hasOneUse()) |
0 |
13632 |
if (!N0.hasOneUse()) |
0 |
| 13633 |
DoXform = |
--- |
13633 |
DoXform = |
--- |
| 13634 |
ExtendUsesToFormExtLoad(VT, N, N0, ISD::ANY_EXTEND, SetCCs, TLI); |
0 |
13634 |
ExtendUsesToFormExtLoad(VT, N, N0, ISD::ANY_EXTEND, SetCCs, TLI); |
0 |
| 13635 |
if (DoXform) { |
0 |
13635 |
if (DoXform) { |
0 |
| 13636 |
LoadSDNode *LN0 = cast(N0); |
0 |
13636 |
LoadSDNode *LN0 = cast(N0); |
0 |
| 13637 |
SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, |
0 |
13637 |
SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, |
0 |
| 13638 |
LN0->getChain(), LN0->getBasePtr(), |
0 |
13638 |
LN0->getChain(), LN0->getBasePtr(), |
0 |
| 13639 |
N0.getValueType(), LN0->getMemOperand()); |
--- |
13639 |
N0.getValueType(), LN0->getMemOperand()); |
--- |
| 13640 |
ExtendSetCCUses(SetCCs, N0, ExtLoad, ISD::ANY_EXTEND); |
0 |
13640 |
ExtendSetCCUses(SetCCs, N0, ExtLoad, ISD::ANY_EXTEND); |
0 |
| 13641 |
// If the load value is used only by N, replace it via CombineTo N. |
--- |
13641 |
// If the load value is used only by N, replace it via CombineTo N. |
--- |
| 13642 |
bool NoReplaceTrunc = N0.hasOneUse(); |
0 |
13642 |
bool NoReplaceTrunc = N0.hasOneUse(); |
0 |
| 13643 |
CombineTo(N, ExtLoad); |
0 |
13643 |
CombineTo(N, ExtLoad); |
0 |
| 13644 |
if (NoReplaceTrunc) { |
0 |
13644 |
if (NoReplaceTrunc) { |
0 |
| 13645 |
DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1)); |
0 |
13645 |
DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1)); |
0 |
| 13646 |
recursivelyDeleteUnusedNodes(LN0); |
0 |
13646 |
recursivelyDeleteUnusedNodes(LN0); |
0 |
| 13647 |
} else { |
--- |
13647 |
} else { |
--- |
| 13648 |
SDValue Trunc = |
--- |
13648 |
SDValue Trunc = |
--- |
| 13649 |
DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), ExtLoad); |
0 |
13649 |
DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), ExtLoad); |
0 |
| 13650 |
CombineTo(LN0, Trunc, ExtLoad.getValue(1)); |
0 |
13650 |
CombineTo(LN0, Trunc, ExtLoad.getValue(1)); |
0 |
| 13651 |
} |
--- |
13651 |
} |
--- |
| 13652 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
13652 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 13653 |
} |
--- |
13653 |
} |
--- |
| 13654 |
} |
0 |
13654 |
} |
0 |
| 13655 |
|
--- |
13655 |
|
--- |
| 13656 |
// fold (aext (zextload x)) -> (aext (truncate (zextload x))) |
--- |
13656 |
// fold (aext (zextload x)) -> (aext (truncate (zextload x))) |
--- |
| 13657 |
// fold (aext (sextload x)) -> (aext (truncate (sextload x))) |
--- |
13657 |
// fold (aext (sextload x)) -> (aext (truncate (sextload x))) |
--- |
| 13658 |
// fold (aext ( extload x)) -> (aext (truncate (extload x))) |
--- |
13658 |
// fold (aext ( extload x)) -> (aext (truncate (extload x))) |
--- |
| 13659 |
if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.getNode()) && |
0 |
13659 |
if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.getNode()) && |
0 |
| 13660 |
ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { |
0 |
13660 |
ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { |
0 |
| 13661 |
LoadSDNode *LN0 = cast(N0); |
0 |
13661 |
LoadSDNode *LN0 = cast(N0); |
0 |
| 13662 |
ISD::LoadExtType ExtType = LN0->getExtensionType(); |
0 |
13662 |
ISD::LoadExtType ExtType = LN0->getExtensionType(); |
0 |
| 13663 |
EVT MemVT = LN0->getMemoryVT(); |
0 |
13663 |
EVT MemVT = LN0->getMemoryVT(); |
0 |
| 13664 |
if (!LegalOperations || TLI.isLoadExtLegal(ExtType, VT, MemVT)) { |
0 |
13664 |
if (!LegalOperations || TLI.isLoadExtLegal(ExtType, VT, MemVT)) { |
0 |
| 13665 |
SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLoc(N), |
0 |
13665 |
SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLoc(N), |
0 |
| 13666 |
VT, LN0->getChain(), LN0->getBasePtr(), |
0 |
13666 |
VT, LN0->getChain(), LN0->getBasePtr(), |
0 |
| 13667 |
MemVT, LN0->getMemOperand()); |
--- |
13667 |
MemVT, LN0->getMemOperand()); |
--- |
| 13668 |
CombineTo(N, ExtLoad); |
0 |
13668 |
CombineTo(N, ExtLoad); |
0 |
| 13669 |
DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1)); |
0 |
13669 |
DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1)); |
0 |
| 13670 |
recursivelyDeleteUnusedNodes(LN0); |
0 |
13670 |
recursivelyDeleteUnusedNodes(LN0); |
0 |
| 13671 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
13671 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 13672 |
} |
--- |
13672 |
} |
--- |
| 13673 |
} |
--- |
13673 |
} |
--- |
| 13674 |
|
--- |
13674 |
|
--- |
| 13675 |
if (N0.getOpcode() == ISD::SETCC) { |
0 |
13675 |
if (N0.getOpcode() == ISD::SETCC) { |
0 |
| 13676 |
// Propagate fast-math-flags. |
--- |
13676 |
// Propagate fast-math-flags. |
--- |
| 13677 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags()); |
0 |
13677 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags()); |
0 |
| 13678 |
|
--- |
13678 |
|
--- |
| 13679 |
// For vectors: |
--- |
13679 |
// For vectors: |
--- |
| 13680 |
// aext(setcc) -> vsetcc |
--- |
13680 |
// aext(setcc) -> vsetcc |
--- |
| 13681 |
// aext(setcc) -> truncate(vsetcc) |
--- |
13681 |
// aext(setcc) -> truncate(vsetcc) |
--- |
| 13682 |
// aext(setcc) -> aext(vsetcc) |
--- |
13682 |
// aext(setcc) -> aext(vsetcc) |
--- |
| 13683 |
// Only do this before legalize for now. |
--- |
13683 |
// Only do this before legalize for now. |
--- |
| 13684 |
if (VT.isVector() && !LegalOperations) { |
0 |
13684 |
if (VT.isVector() && !LegalOperations) { |
0 |
| 13685 |
EVT N00VT = N0.getOperand(0).getValueType(); |
0 |
13685 |
EVT N00VT = N0.getOperand(0).getValueType(); |
0 |
| 13686 |
if (getSetCCResultType(N00VT) == N0.getValueType()) |
0 |
13686 |
if (getSetCCResultType(N00VT) == N0.getValueType()) |
0 |
| 13687 |
return SDValue(); |
0 |
13687 |
return SDValue(); |
0 |
| 13688 |
|
--- |
13688 |
|
--- |
| 13689 |
// We know that the # elements of the results is the same as the |
--- |
13689 |
// We know that the # elements of the results is the same as the |
--- |
| 13690 |
// # elements of the compare (and the # elements of the compare result |
--- |
13690 |
// # elements of the compare (and the # elements of the compare result |
--- |
| 13691 |
// for that matter). Check to see that they are the same size. If so, |
--- |
13691 |
// for that matter). Check to see that they are the same size. If so, |
--- |
| 13692 |
// we know that the element size of the sext'd result matches the |
--- |
13692 |
// we know that the element size of the sext'd result matches the |
--- |
| 13693 |
// element size of the compare operands. |
--- |
13693 |
// element size of the compare operands. |
--- |
| 13694 |
if (VT.getSizeInBits() == N00VT.getSizeInBits()) |
0 |
13694 |
if (VT.getSizeInBits() == N00VT.getSizeInBits()) |
0 |
| 13695 |
return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0), |
0 |
13695 |
return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0), |
0 |
| 13696 |
N0.getOperand(1), |
0 |
13696 |
N0.getOperand(1), |
0 |
| 13697 |
cast(N0.getOperand(2))->get()); |
0 |
13697 |
cast(N0.getOperand(2))->get()); |
0 |
| 13698 |
|
--- |
13698 |
|
--- |
| 13699 |
// If the desired elements are smaller or larger than the source |
--- |
13699 |
// If the desired elements are smaller or larger than the source |
--- |
| 13700 |
// elements we can use a matching integer vector type and then |
--- |
13700 |
// elements we can use a matching integer vector type and then |
--- |
| 13701 |
// truncate/any extend |
--- |
13701 |
// truncate/any extend |
--- |
| 13702 |
EVT MatchingVectorType = N00VT.changeVectorElementTypeToInteger(); |
0 |
13702 |
EVT MatchingVectorType = N00VT.changeVectorElementTypeToInteger(); |
0 |
| 13703 |
SDValue VsetCC = |
--- |
13703 |
SDValue VsetCC = |
--- |
| 13704 |
DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0), |
0 |
13704 |
DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0), |
0 |
| 13705 |
N0.getOperand(1), |
0 |
13705 |
N0.getOperand(1), |
0 |
| 13706 |
cast(N0.getOperand(2))->get()); |
--- |
13706 |
cast(N0.getOperand(2))->get()); |
--- |
| 13707 |
return DAG.getAnyExtOrTrunc(VsetCC, SDLoc(N), VT); |
0 |
13707 |
return DAG.getAnyExtOrTrunc(VsetCC, SDLoc(N), VT); |
0 |
| 13708 |
} |
--- |
13708 |
} |
--- |
| 13709 |
|
--- |
13709 |
|
--- |
| 13710 |
// aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc |
--- |
13710 |
// aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc |
--- |
| 13711 |
SDLoc DL(N); |
0 |
13711 |
SDLoc DL(N); |
0 |
| 13712 |
if (SDValue SCC = SimplifySelectCC( |
0 |
13712 |
if (SDValue SCC = SimplifySelectCC( |
0 |
| 13713 |
DL, N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, DL, VT), |
0 |
13713 |
DL, N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, DL, VT), |
0 |
| 13714 |
DAG.getConstant(0, DL, VT), |
0 |
13714 |
DAG.getConstant(0, DL, VT), |
0 |
| 13715 |
cast(N0.getOperand(2))->get(), true)) |
0 |
13715 |
cast(N0.getOperand(2))->get(), true)) |
0 |
| 13716 |
return SCC; |
0 |
13716 |
return SCC; |
0 |
| 13717 |
} |
0 |
13717 |
} |
0 |
| 13718 |
|
--- |
13718 |
|
--- |
| 13719 |
if (SDValue NewCtPop = widenCtPop(N, DAG)) |
0 |
13719 |
if (SDValue NewCtPop = widenCtPop(N, DAG)) |
0 |
| 13720 |
return NewCtPop; |
0 |
13720 |
return NewCtPop; |
0 |
| 13721 |
|
--- |
13721 |
|
--- |
| 13722 |
if (SDValue Res = tryToFoldExtendSelectLoad(N, TLI, DAG, Level)) |
0 |
13722 |
if (SDValue Res = tryToFoldExtendSelectLoad(N, TLI, DAG, Level)) |
0 |
| 13723 |
return Res; |
0 |
13723 |
return Res; |
0 |
| 13724 |
|
--- |
13724 |
|
--- |
| 13725 |
return SDValue(); |
0 |
13725 |
return SDValue(); |
0 |
| 13726 |
} |
--- |
13726 |
} |
--- |
| 13727 |
|
--- |
13727 |
|
--- |
| 13728 |
SDValue DAGCombiner::visitAssertExt(SDNode *N) { |
0 |
13728 |
SDValue DAGCombiner::visitAssertExt(SDNode *N) { |
0 |
| 13729 |
unsigned Opcode = N->getOpcode(); |
0 |
13729 |
unsigned Opcode = N->getOpcode(); |
0 |
| 13730 |
SDValue N0 = N->getOperand(0); |
0 |
13730 |
SDValue N0 = N->getOperand(0); |
0 |
| 13731 |
SDValue N1 = N->getOperand(1); |
0 |
13731 |
SDValue N1 = N->getOperand(1); |
0 |
| 13732 |
EVT AssertVT = cast(N1)->getVT(); |
0 |
13732 |
EVT AssertVT = cast(N1)->getVT(); |
0 |
| 13733 |
|
--- |
13733 |
|
--- |
| 13734 |
// fold (assert?ext (assert?ext x, vt), vt) -> (assert?ext x, vt) |
--- |
13734 |
// fold (assert?ext (assert?ext x, vt), vt) -> (assert?ext x, vt) |
--- |
| 13735 |
if (N0.getOpcode() == Opcode && |
0 |
13735 |
if (N0.getOpcode() == Opcode && |
0 |
| 13736 |
AssertVT == cast(N0.getOperand(1))->getVT()) |
0 |
13736 |
AssertVT == cast(N0.getOperand(1))->getVT()) |
0 |
| 13737 |
return N0; |
0 |
13737 |
return N0; |
0 |
| 13738 |
|
--- |
13738 |
|
--- |
| 13739 |
if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && |
0 |
13739 |
if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && |
0 |
| 13740 |
N0.getOperand(0).getOpcode() == Opcode) { |
0 |
13740 |
N0.getOperand(0).getOpcode() == Opcode) { |
0 |
| 13741 |
// We have an assert, truncate, assert sandwich. Make one stronger assert |
--- |
13741 |
// We have an assert, truncate, assert sandwich. Make one stronger assert |
--- |
| 13742 |
// by asserting on the smallest asserted type to the larger source type. |
--- |
13742 |
// by asserting on the smallest asserted type to the larger source type. |
--- |
| 13743 |
// This eliminates the later assert: |
--- |
13743 |
// This eliminates the later assert: |
--- |
| 13744 |
// assert (trunc (assert X, i8) to iN), i1 --> trunc (assert X, i1) to iN |
--- |
13744 |
// assert (trunc (assert X, i8) to iN), i1 --> trunc (assert X, i1) to iN |
--- |
| 13745 |
// assert (trunc (assert X, i1) to iN), i8 --> trunc (assert X, i1) to iN |
--- |
13745 |
// assert (trunc (assert X, i1) to iN), i8 --> trunc (assert X, i1) to iN |
--- |
| 13746 |
SDLoc DL(N); |
0 |
13746 |
SDLoc DL(N); |
0 |
| 13747 |
SDValue BigA = N0.getOperand(0); |
0 |
13747 |
SDValue BigA = N0.getOperand(0); |
0 |
| 13748 |
EVT BigA_AssertVT = cast(BigA.getOperand(1))->getVT(); |
0 |
13748 |
EVT BigA_AssertVT = cast(BigA.getOperand(1))->getVT(); |
0 |
| 13749 |
EVT MinAssertVT = AssertVT.bitsLT(BigA_AssertVT) ? AssertVT : BigA_AssertVT; |
0 |
13749 |
EVT MinAssertVT = AssertVT.bitsLT(BigA_AssertVT) ? AssertVT : BigA_AssertVT; |
0 |
| 13750 |
SDValue MinAssertVTVal = DAG.getValueType(MinAssertVT); |
0 |
13750 |
SDValue MinAssertVTVal = DAG.getValueType(MinAssertVT); |
0 |
| 13751 |
SDValue NewAssert = DAG.getNode(Opcode, DL, BigA.getValueType(), |
0 |
13751 |
SDValue NewAssert = DAG.getNode(Opcode, DL, BigA.getValueType(), |
0 |
| 13752 |
BigA.getOperand(0), MinAssertVTVal); |
0 |
13752 |
BigA.getOperand(0), MinAssertVTVal); |
0 |
| 13753 |
return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewAssert); |
0 |
13753 |
return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewAssert); |
0 |
| 13754 |
} |
0 |
13754 |
} |
0 |
| 13755 |
|
--- |
13755 |
|
--- |
| 13756 |
// If we have (AssertZext (truncate (AssertSext X, iX)), iY) and Y is smaller |
--- |
13756 |
// If we have (AssertZext (truncate (AssertSext X, iX)), iY) and Y is smaller |
--- |
| 13757 |
// than X. Just move the AssertZext in front of the truncate and drop the |
--- |
13757 |
// than X. Just move the AssertZext in front of the truncate and drop the |
--- |
| 13758 |
// AssertSExt. |
--- |
13758 |
// AssertSExt. |
--- |
| 13759 |
if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && |
0 |
13759 |
if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && |
0 |
| 13760 |
N0.getOperand(0).getOpcode() == ISD::AssertSext && |
0 |
13760 |
N0.getOperand(0).getOpcode() == ISD::AssertSext && |
0 |
| 13761 |
Opcode == ISD::AssertZext) { |
--- |
13761 |
Opcode == ISD::AssertZext) { |
--- |
| 13762 |
SDValue BigA = N0.getOperand(0); |
0 |
13762 |
SDValue BigA = N0.getOperand(0); |
0 |
| 13763 |
EVT BigA_AssertVT = cast(BigA.getOperand(1))->getVT(); |
0 |
13763 |
EVT BigA_AssertVT = cast(BigA.getOperand(1))->getVT(); |
0 |
| 13764 |
if (AssertVT.bitsLT(BigA_AssertVT)) { |
0 |
13764 |
if (AssertVT.bitsLT(BigA_AssertVT)) { |
0 |
| 13765 |
SDLoc DL(N); |
0 |
13765 |
SDLoc DL(N); |
0 |
| 13766 |
SDValue NewAssert = DAG.getNode(Opcode, DL, BigA.getValueType(), |
0 |
13766 |
SDValue NewAssert = DAG.getNode(Opcode, DL, BigA.getValueType(), |
0 |
| 13767 |
BigA.getOperand(0), N1); |
0 |
13767 |
BigA.getOperand(0), N1); |
0 |
| 13768 |
return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewAssert); |
0 |
13768 |
return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewAssert); |
0 |
| 13769 |
} |
0 |
13769 |
} |
0 |
| 13770 |
} |
--- |
13770 |
} |
--- |
| 13771 |
|
--- |
13771 |
|
--- |
| 13772 |
return SDValue(); |
0 |
13772 |
return SDValue(); |
0 |
| 13773 |
} |
--- |
13773 |
} |
--- |
| 13774 |
|
--- |
13774 |
|
--- |
| 13775 |
SDValue DAGCombiner::visitAssertAlign(SDNode *N) { |
0 |
13775 |
SDValue DAGCombiner::visitAssertAlign(SDNode *N) { |
0 |
| 13776 |
SDLoc DL(N); |
0 |
13776 |
SDLoc DL(N); |
0 |
| 13777 |
|
--- |
13777 |
|
--- |
| 13778 |
Align AL = cast(N)->getAlign(); |
0 |
13778 |
Align AL = cast(N)->getAlign(); |
0 |
| 13779 |
SDValue N0 = N->getOperand(0); |
0 |
13779 |
SDValue N0 = N->getOperand(0); |
0 |
| 13780 |
|
--- |
13780 |
|
--- |
| 13781 |
// Fold (assertalign (assertalign x, AL0), AL1) -> |
--- |
13781 |
// Fold (assertalign (assertalign x, AL0), AL1) -> |
--- |
| 13782 |
// (assertalign x, max(AL0, AL1)) |
--- |
13782 |
// (assertalign x, max(AL0, AL1)) |
--- |
| 13783 |
if (auto *AAN = dyn_cast(N0)) |
0 |
13783 |
if (auto *AAN = dyn_cast(N0)) |
0 |
| 13784 |
return DAG.getAssertAlign(DL, N0.getOperand(0), |
0 |
13784 |
return DAG.getAssertAlign(DL, N0.getOperand(0), |
0 |
| 13785 |
std::max(AL, AAN->getAlign())); |
0 |
13785 |
std::max(AL, AAN->getAlign())); |
0 |
| 13786 |
|
--- |
13786 |
|
--- |
| 13787 |
// In rare cases, there are trivial arithmetic ops in source operands. Sink |
--- |
13787 |
// In rare cases, there are trivial arithmetic ops in source operands. Sink |
--- |
| 13788 |
// this assert down to source operands so that those arithmetic ops could be |
--- |
13788 |
// this assert down to source operands so that those arithmetic ops could be |
--- |
| 13789 |
// exposed to the DAG combining. |
--- |
13789 |
// exposed to the DAG combining. |
--- |
| 13790 |
switch (N0.getOpcode()) { |
0 |
13790 |
switch (N0.getOpcode()) { |
0 |
| 13791 |
default: |
0 |
13791 |
default: |
0 |
| 13792 |
break; |
0 |
13792 |
break; |
0 |
| 13793 |
case ISD::ADD: |
0 |
13793 |
case ISD::ADD: |
0 |
| 13794 |
case ISD::SUB: { |
--- |
13794 |
case ISD::SUB: { |
--- |
| 13795 |
unsigned AlignShift = Log2(AL); |
0 |
13795 |
unsigned AlignShift = Log2(AL); |
0 |
| 13796 |
SDValue LHS = N0.getOperand(0); |
0 |
13796 |
SDValue LHS = N0.getOperand(0); |
0 |
| 13797 |
SDValue RHS = N0.getOperand(1); |
0 |
13797 |
SDValue RHS = N0.getOperand(1); |
0 |
| 13798 |
unsigned LHSAlignShift = DAG.computeKnownBits(LHS).countMinTrailingZeros(); |
0 |
13798 |
unsigned LHSAlignShift = DAG.computeKnownBits(LHS).countMinTrailingZeros(); |
0 |
| 13799 |
unsigned RHSAlignShift = DAG.computeKnownBits(RHS).countMinTrailingZeros(); |
0 |
13799 |
unsigned RHSAlignShift = DAG.computeKnownBits(RHS).countMinTrailingZeros(); |
0 |
| 13800 |
if (LHSAlignShift >= AlignShift || RHSAlignShift >= AlignShift) { |
0 |
13800 |
if (LHSAlignShift >= AlignShift || RHSAlignShift >= AlignShift) { |
0 |
| 13801 |
if (LHSAlignShift < AlignShift) |
0 |
13801 |
if (LHSAlignShift < AlignShift) |
0 |
| 13802 |
LHS = DAG.getAssertAlign(DL, LHS, AL); |
0 |
13802 |
LHS = DAG.getAssertAlign(DL, LHS, AL); |
0 |
| 13803 |
if (RHSAlignShift < AlignShift) |
0 |
13803 |
if (RHSAlignShift < AlignShift) |
0 |
| 13804 |
RHS = DAG.getAssertAlign(DL, RHS, AL); |
0 |
13804 |
RHS = DAG.getAssertAlign(DL, RHS, AL); |
0 |
| 13805 |
return DAG.getNode(N0.getOpcode(), DL, N0.getValueType(), LHS, RHS); |
0 |
13805 |
return DAG.getNode(N0.getOpcode(), DL, N0.getValueType(), LHS, RHS); |
0 |
| 13806 |
} |
--- |
13806 |
} |
--- |
| 13807 |
break; |
0 |
13807 |
break; |
0 |
| 13808 |
} |
--- |
13808 |
} |
--- |
| 13809 |
} |
--- |
13809 |
} |
--- |
| 13810 |
|
--- |
13810 |
|
--- |
| 13811 |
return SDValue(); |
0 |
13811 |
return SDValue(); |
0 |
| 13812 |
} |
0 |
13812 |
} |
0 |
| 13813 |
|
--- |
13813 |
|
--- |
| 13814 |
/// If the result of a load is shifted/masked/truncated to an effectively |
--- |
13814 |
/// If the result of a load is shifted/masked/truncated to an effectively |
--- |
| 13815 |
/// narrower type, try to transform the load to a narrower type and/or |
--- |
13815 |
/// narrower type, try to transform the load to a narrower type and/or |
--- |
| 13816 |
/// use an extending load. |
--- |
13816 |
/// use an extending load. |
--- |
| 13817 |
SDValue DAGCombiner::reduceLoadWidth(SDNode *N) { |
0 |
13817 |
SDValue DAGCombiner::reduceLoadWidth(SDNode *N) { |
0 |
| 13818 |
unsigned Opc = N->getOpcode(); |
0 |
13818 |
unsigned Opc = N->getOpcode(); |
0 |
| 13819 |
|
--- |
13819 |
|
--- |
| 13820 |
ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; |
0 |
13820 |
ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; |
0 |
| 13821 |
SDValue N0 = N->getOperand(0); |
0 |
13821 |
SDValue N0 = N->getOperand(0); |
0 |
| 13822 |
EVT VT = N->getValueType(0); |
0 |
13822 |
EVT VT = N->getValueType(0); |
0 |
| 13823 |
EVT ExtVT = VT; |
0 |
13823 |
EVT ExtVT = VT; |
0 |
| 13824 |
|
--- |
13824 |
|
--- |
| 13825 |
// This transformation isn't valid for vector loads. |
--- |
13825 |
// This transformation isn't valid for vector loads. |
--- |
| 13826 |
if (VT.isVector()) |
0 |
13826 |
if (VT.isVector()) |
0 |
| 13827 |
return SDValue(); |
0 |
13827 |
return SDValue(); |
0 |
| 13828 |
|
--- |
13828 |
|
--- |
| 13829 |
// The ShAmt variable is used to indicate that we've consumed a right |
--- |
13829 |
// The ShAmt variable is used to indicate that we've consumed a right |
--- |
| 13830 |
// shift. I.e. we want to narrow the width of the load by skipping to load the |
--- |
13830 |
// shift. I.e. we want to narrow the width of the load by skipping to load the |
--- |
| 13831 |
// ShAmt least significant bits. |
--- |
13831 |
// ShAmt least significant bits. |
--- |
| 13832 |
unsigned ShAmt = 0; |
0 |
13832 |
unsigned ShAmt = 0; |
0 |
| 13833 |
// A special case is when the least significant bits from the load are masked |
--- |
13833 |
// A special case is when the least significant bits from the load are masked |
--- |
| 13834 |
// away, but using an AND rather than a right shift. HasShiftedOffset is used |
--- |
13834 |
// away, but using an AND rather than a right shift. HasShiftedOffset is used |
--- |
| 13835 |
// to indicate that the narrowed load should be left-shifted ShAmt bits to get |
--- |
13835 |
// to indicate that the narrowed load should be left-shifted ShAmt bits to get |
--- |
| 13836 |
// the result. |
--- |
13836 |
// the result. |
--- |
| 13837 |
bool HasShiftedOffset = false; |
0 |
13837 |
bool HasShiftedOffset = false; |
0 |
| 13838 |
// Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then |
--- |
13838 |
// Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then |
--- |
| 13839 |
// extended to VT. |
--- |
13839 |
// extended to VT. |
--- |
| 13840 |
if (Opc == ISD::SIGN_EXTEND_INREG) { |
0 |
13840 |
if (Opc == ISD::SIGN_EXTEND_INREG) { |
0 |
| 13841 |
ExtType = ISD::SEXTLOAD; |
0 |
13841 |
ExtType = ISD::SEXTLOAD; |
0 |
| 13842 |
ExtVT = cast(N->getOperand(1))->getVT(); |
0 |
13842 |
ExtVT = cast(N->getOperand(1))->getVT(); |
0 |
| 13843 |
} else if (Opc == ISD::SRL || Opc == ISD::SRA) { |
0 |
13843 |
} else if (Opc == ISD::SRL || Opc == ISD::SRA) { |
0 |
| 13844 |
// Another special-case: SRL/SRA is basically zero/sign-extending a narrower |
--- |
13844 |
// Another special-case: SRL/SRA is basically zero/sign-extending a narrower |
--- |
| 13845 |
// value, or it may be shifting a higher subword, half or byte into the |
--- |
13845 |
// value, or it may be shifting a higher subword, half or byte into the |
--- |
| 13846 |
// lowest bits. |
--- |
13846 |
// lowest bits. |
--- |
| 13847 |
|
--- |
13847 |
|
--- |
| 13848 |
// Only handle shift with constant shift amount, and the shiftee must be a |
--- |
13848 |
// Only handle shift with constant shift amount, and the shiftee must be a |
--- |
| 13849 |
// load. |
--- |
13849 |
// load. |
--- |
| 13850 |
auto *LN = dyn_cast(N0); |
0 |
13850 |
auto *LN = dyn_cast(N0); |
0 |
| 13851 |
auto *N1C = dyn_cast(N->getOperand(1)); |
0 |
13851 |
auto *N1C = dyn_cast(N->getOperand(1)); |
0 |
| 13852 |
if (!N1C || !LN) |
0 |
13852 |
if (!N1C || !LN) |
0 |
| 13853 |
return SDValue(); |
0 |
13853 |
return SDValue(); |
0 |
| 13854 |
// If the shift amount is larger than the memory type then we're not |
--- |
13854 |
// If the shift amount is larger than the memory type then we're not |
--- |
| 13855 |
// accessing any of the loaded bytes. |
--- |
13855 |
// accessing any of the loaded bytes. |
--- |
| 13856 |
ShAmt = N1C->getZExtValue(); |
0 |
13856 |
ShAmt = N1C->getZExtValue(); |
0 |
| 13857 |
uint64_t MemoryWidth = LN->getMemoryVT().getScalarSizeInBits(); |
0 |
13857 |
uint64_t MemoryWidth = LN->getMemoryVT().getScalarSizeInBits(); |
0 |
| 13858 |
if (MemoryWidth <= ShAmt) |
0 |
13858 |
if (MemoryWidth <= ShAmt) |
0 |
| 13859 |
return SDValue(); |
0 |
13859 |
return SDValue(); |
0 |
| 13860 |
// Attempt to fold away the SRL by using ZEXTLOAD and SRA by using SEXTLOAD. |
--- |
13860 |
// Attempt to fold away the SRL by using ZEXTLOAD and SRA by using SEXTLOAD. |
--- |
| 13861 |
ExtType = Opc == ISD::SRL ? ISD::ZEXTLOAD : ISD::SEXTLOAD; |
0 |
13861 |
ExtType = Opc == ISD::SRL ? ISD::ZEXTLOAD : ISD::SEXTLOAD; |
0 |
| 13862 |
ExtVT = EVT::getIntegerVT(*DAG.getContext(), MemoryWidth - ShAmt); |
0 |
13862 |
ExtVT = EVT::getIntegerVT(*DAG.getContext(), MemoryWidth - ShAmt); |
0 |
| 13863 |
// If original load is a SEXTLOAD then we can't simply replace it by a |
--- |
13863 |
// If original load is a SEXTLOAD then we can't simply replace it by a |
--- |
| 13864 |
// ZEXTLOAD (we could potentially replace it by a more narrow SEXTLOAD |
--- |
13864 |
// ZEXTLOAD (we could potentially replace it by a more narrow SEXTLOAD |
--- |
| 13865 |
// followed by a ZEXT, but that is not handled at the moment). Similarly if |
--- |
13865 |
// followed by a ZEXT, but that is not handled at the moment). Similarly if |
--- |
| 13866 |
// the original load is a ZEXTLOAD and we want to use a SEXTLOAD. |
--- |
13866 |
// the original load is a ZEXTLOAD and we want to use a SEXTLOAD. |
--- |
| 13867 |
if ((LN->getExtensionType() == ISD::SEXTLOAD || |
0 |
13867 |
if ((LN->getExtensionType() == ISD::SEXTLOAD || |
0 |
| 13868 |
LN->getExtensionType() == ISD::ZEXTLOAD) && |
0 |
13868 |
LN->getExtensionType() == ISD::ZEXTLOAD) && |
0 |
| 13869 |
LN->getExtensionType() != ExtType) |
0 |
13869 |
LN->getExtensionType() != ExtType) |
0 |
| 13870 |
return SDValue(); |
0 |
13870 |
return SDValue(); |
0 |
| 13871 |
} else if (Opc == ISD::AND) { |
0 |
13871 |
} else if (Opc == ISD::AND) { |
0 |
| 13872 |
// An AND with a constant mask is the same as a truncate + zero-extend. |
--- |
13872 |
// An AND with a constant mask is the same as a truncate + zero-extend. |
--- |
| 13873 |
auto AndC = dyn_cast(N->getOperand(1)); |
0 |
13873 |
auto AndC = dyn_cast(N->getOperand(1)); |
0 |
| 13874 |
if (!AndC) |
0 |
13874 |
if (!AndC) |
0 |
| 13875 |
return SDValue(); |
0 |
13875 |
return SDValue(); |
0 |
| 13876 |
|
--- |
13876 |
|
--- |
| 13877 |
const APInt &Mask = AndC->getAPIntValue(); |
0 |
13877 |
const APInt &Mask = AndC->getAPIntValue(); |
0 |
| 13878 |
unsigned ActiveBits = 0; |
0 |
13878 |
unsigned ActiveBits = 0; |
0 |
| 13879 |
if (Mask.isMask()) { |
0 |
13879 |
if (Mask.isMask()) { |
0 |
| 13880 |
ActiveBits = Mask.countr_one(); |
0 |
13880 |
ActiveBits = Mask.countr_one(); |
0 |
| 13881 |
} else if (Mask.isShiftedMask(ShAmt, ActiveBits)) { |
0 |
13881 |
} else if (Mask.isShiftedMask(ShAmt, ActiveBits)) { |
0 |
| 13882 |
HasShiftedOffset = true; |
0 |
13882 |
HasShiftedOffset = true; |
0 |
| 13883 |
} else { |
--- |
13883 |
} else { |
--- |
| 13884 |
return SDValue(); |
0 |
13884 |
return SDValue(); |
0 |
| 13885 |
} |
--- |
13885 |
} |
--- |
| 13886 |
|
--- |
13886 |
|
--- |
| 13887 |
ExtType = ISD::ZEXTLOAD; |
0 |
13887 |
ExtType = ISD::ZEXTLOAD; |
0 |
| 13888 |
ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); |
0 |
13888 |
ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); |
0 |
| 13889 |
} |
--- |
13889 |
} |
--- |
| 13890 |
|
--- |
13890 |
|
--- |
| 13891 |
// In case Opc==SRL we've already prepared ExtVT/ExtType/ShAmt based on doing |
--- |
13891 |
// In case Opc==SRL we've already prepared ExtVT/ExtType/ShAmt based on doing |
--- |
| 13892 |
// a right shift. Here we redo some of those checks, to possibly adjust the |
--- |
13892 |
// a right shift. Here we redo some of those checks, to possibly adjust the |
--- |
| 13893 |
// ExtVT even further based on "a masking AND". We could also end up here for |
--- |
13893 |
// ExtVT even further based on "a masking AND". We could also end up here for |
--- |
| 13894 |
// other reasons (e.g. based on Opc==TRUNCATE) and that is why some checks |
--- |
13894 |
// other reasons (e.g. based on Opc==TRUNCATE) and that is why some checks |
--- |
| 13895 |
// need to be done here as well. |
--- |
13895 |
// need to be done here as well. |
--- |
| 13896 |
if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) { |
0 |
13896 |
if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) { |
0 |
| 13897 |
SDValue SRL = Opc == ISD::SRL ? SDValue(N, 0) : N0; |
0 |
13897 |
SDValue SRL = Opc == ISD::SRL ? SDValue(N, 0) : N0; |
0 |
| 13898 |
// Bail out when the SRL has more than one use. This is done for historical |
--- |
13898 |
// Bail out when the SRL has more than one use. This is done for historical |
--- |
| 13899 |
// (undocumented) reasons. Maybe intent was to guard the AND-masking below |
--- |
13899 |
// (undocumented) reasons. Maybe intent was to guard the AND-masking below |
--- |
| 13900 |
// check below? And maybe it could be non-profitable to do the transform in |
--- |
13900 |
// check below? And maybe it could be non-profitable to do the transform in |
--- |
| 13901 |
// case the SRL has multiple uses and we get here with Opc!=ISD::SRL? |
--- |
13901 |
// case the SRL has multiple uses and we get here with Opc!=ISD::SRL? |
--- |
| 13902 |
// FIXME: Can't we just skip this check for the Opc==ISD::SRL case. |
--- |
13902 |
// FIXME: Can't we just skip this check for the Opc==ISD::SRL case. |
--- |
| 13903 |
if (!SRL.hasOneUse()) |
0 |
13903 |
if (!SRL.hasOneUse()) |
0 |
| 13904 |
return SDValue(); |
0 |
13904 |
return SDValue(); |
0 |
| 13905 |
|
--- |
13905 |
|
--- |
| 13906 |
// Only handle shift with constant shift amount, and the shiftee must be a |
--- |
13906 |
// Only handle shift with constant shift amount, and the shiftee must be a |
--- |
| 13907 |
// load. |
--- |
13907 |
// load. |
--- |
| 13908 |
auto *LN = dyn_cast(SRL.getOperand(0)); |
0 |
13908 |
auto *LN = dyn_cast(SRL.getOperand(0)); |
0 |
| 13909 |
auto *SRL1C = dyn_cast(SRL.getOperand(1)); |
0 |
13909 |
auto *SRL1C = dyn_cast(SRL.getOperand(1)); |
0 |
| 13910 |
if (!SRL1C || !LN) |
0 |
13910 |
if (!SRL1C || !LN) |
0 |
| 13911 |
return SDValue(); |
0 |
13911 |
return SDValue(); |
0 |
| 13912 |
|
--- |
13912 |
|
--- |
| 13913 |
// If the shift amount is larger than the input type then we're not |
--- |
13913 |
// If the shift amount is larger than the input type then we're not |
--- |
| 13914 |
// accessing any of the loaded bytes. If the load was a zextload/extload |
--- |
13914 |
// accessing any of the loaded bytes. If the load was a zextload/extload |
--- |
| 13915 |
// then the result of the shift+trunc is zero/undef (handled elsewhere). |
--- |
13915 |
// then the result of the shift+trunc is zero/undef (handled elsewhere). |
--- |
| 13916 |
ShAmt = SRL1C->getZExtValue(); |
0 |
13916 |
ShAmt = SRL1C->getZExtValue(); |
0 |
| 13917 |
uint64_t MemoryWidth = LN->getMemoryVT().getSizeInBits(); |
0 |
13917 |
uint64_t MemoryWidth = LN->getMemoryVT().getSizeInBits(); |
0 |
| 13918 |
if (ShAmt >= MemoryWidth) |
0 |
13918 |
if (ShAmt >= MemoryWidth) |
0 |
| 13919 |
return SDValue(); |
0 |
13919 |
return SDValue(); |
0 |
| 13920 |
|
--- |
13920 |
|
--- |
| 13921 |
// Because a SRL must be assumed to *need* to zero-extend the high bits |
--- |
13921 |
// Because a SRL must be assumed to *need* to zero-extend the high bits |
--- |
| 13922 |
// (as opposed to anyext the high bits), we can't combine the zextload |
--- |
13922 |
// (as opposed to anyext the high bits), we can't combine the zextload |
--- |
| 13923 |
// lowering of SRL and an sextload. |
--- |
13923 |
// lowering of SRL and an sextload. |
--- |
| 13924 |
if (LN->getExtensionType() == ISD::SEXTLOAD) |
0 |
13924 |
if (LN->getExtensionType() == ISD::SEXTLOAD) |
0 |
| 13925 |
return SDValue(); |
0 |
13925 |
return SDValue(); |
0 |
| 13926 |
|
--- |
13926 |
|
--- |
| 13927 |
// Avoid reading outside the memory accessed by the original load (could |
--- |
13927 |
// Avoid reading outside the memory accessed by the original load (could |
--- |
| 13928 |
// happened if we only adjust the load base pointer by ShAmt). Instead we |
--- |
13928 |
// happened if we only adjust the load base pointer by ShAmt). Instead we |
--- |
| 13929 |
// try to narrow the load even further. The typical scenario here is: |
--- |
13929 |
// try to narrow the load even further. The typical scenario here is: |
--- |
| 13930 |
// (i64 (truncate (i96 (srl (load x), 64)))) -> |
--- |
13930 |
// (i64 (truncate (i96 (srl (load x), 64)))) -> |
--- |
| 13931 |
// (i64 (truncate (i96 (zextload (load i32 + offset) from i32)))) |
--- |
13931 |
// (i64 (truncate (i96 (zextload (load i32 + offset) from i32)))) |
--- |
| 13932 |
if (ExtVT.getScalarSizeInBits() > MemoryWidth - ShAmt) { |
0 |
13932 |
if (ExtVT.getScalarSizeInBits() > MemoryWidth - ShAmt) { |
0 |
| 13933 |
// Don't replace sextload by zextload. |
--- |
13933 |
// Don't replace sextload by zextload. |
--- |
| 13934 |
if (ExtType == ISD::SEXTLOAD) |
0 |
13934 |
if (ExtType == ISD::SEXTLOAD) |
0 |
| 13935 |
return SDValue(); |
0 |
13935 |
return SDValue(); |
0 |
| 13936 |
// Narrow the load. |
--- |
13936 |
// Narrow the load. |
--- |
| 13937 |
ExtType = ISD::ZEXTLOAD; |
0 |
13937 |
ExtType = ISD::ZEXTLOAD; |
0 |
| 13938 |
ExtVT = EVT::getIntegerVT(*DAG.getContext(), MemoryWidth - ShAmt); |
0 |
13938 |
ExtVT = EVT::getIntegerVT(*DAG.getContext(), MemoryWidth - ShAmt); |
0 |
| 13939 |
} |
--- |
13939 |
} |
--- |
| 13940 |
|
--- |
13940 |
|
--- |
| 13941 |
// If the SRL is only used by a masking AND, we may be able to adjust |
--- |
13941 |
// If the SRL is only used by a masking AND, we may be able to adjust |
--- |
| 13942 |
// the ExtVT to make the AND redundant. |
--- |
13942 |
// the ExtVT to make the AND redundant. |
--- |
| 13943 |
SDNode *Mask = *(SRL->use_begin()); |
0 |
13943 |
SDNode *Mask = *(SRL->use_begin()); |
0 |
| 13944 |
if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND && |
0 |
13944 |
if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND && |
0 |
| 13945 |
isa(Mask->getOperand(1))) { |
0 |
13945 |
isa(Mask->getOperand(1))) { |
0 |
| 13946 |
const APInt& ShiftMask = Mask->getConstantOperandAPInt(1); |
0 |
13946 |
const APInt& ShiftMask = Mask->getConstantOperandAPInt(1); |
0 |
| 13947 |
if (ShiftMask.isMask()) { |
0 |
13947 |
if (ShiftMask.isMask()) { |
0 |
| 13948 |
EVT MaskedVT = |
--- |
13948 |
EVT MaskedVT = |
--- |
| 13949 |
EVT::getIntegerVT(*DAG.getContext(), ShiftMask.countr_one()); |
0 |
13949 |
EVT::getIntegerVT(*DAG.getContext(), ShiftMask.countr_one()); |
0 |
| 13950 |
// If the mask is smaller, recompute the type. |
--- |
13950 |
// If the mask is smaller, recompute the type. |
--- |
| 13951 |
if ((ExtVT.getScalarSizeInBits() > MaskedVT.getScalarSizeInBits()) && |
0 |
13951 |
if ((ExtVT.getScalarSizeInBits() > MaskedVT.getScalarSizeInBits()) && |
0 |
| 13952 |
TLI.isLoadExtLegal(ExtType, SRL.getValueType(), MaskedVT)) |
0 |
13952 |
TLI.isLoadExtLegal(ExtType, SRL.getValueType(), MaskedVT)) |
0 |
| 13953 |
ExtVT = MaskedVT; |
0 |
13953 |
ExtVT = MaskedVT; |
0 |
| 13954 |
} |
--- |
13954 |
} |
--- |
| 13955 |
} |
--- |
13955 |
} |
--- |
| 13956 |
|
--- |
13956 |
|
--- |
| 13957 |
N0 = SRL.getOperand(0); |
0 |
13957 |
N0 = SRL.getOperand(0); |
0 |
| 13958 |
} |
--- |
13958 |
} |
--- |
| 13959 |
|
--- |
13959 |
|
--- |
| 13960 |
// If the load is shifted left (and the result isn't shifted back right), we |
--- |
13960 |
// If the load is shifted left (and the result isn't shifted back right), we |
--- |
| 13961 |
// can fold a truncate through the shift. The typical scenario is that N |
--- |
13961 |
// can fold a truncate through the shift. The typical scenario is that N |
--- |
| 13962 |
// points at a TRUNCATE here so the attempted fold is: |
--- |
13962 |
// points at a TRUNCATE here so the attempted fold is: |
--- |
| 13963 |
// (truncate (shl (load x), c))) -> (shl (narrow load x), c) |
--- |
13963 |
// (truncate (shl (load x), c))) -> (shl (narrow load x), c) |
--- |
| 13964 |
// ShLeftAmt will indicate how much a narrowed load should be shifted left. |
--- |
13964 |
// ShLeftAmt will indicate how much a narrowed load should be shifted left. |
--- |
| 13965 |
unsigned ShLeftAmt = 0; |
0 |
13965 |
unsigned ShLeftAmt = 0; |
0 |
| 13966 |
if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && |
0 |
13966 |
if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && |
0 |
| 13967 |
ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { |
0 |
13967 |
ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { |
0 |
| 13968 |
if (ConstantSDNode *N01 = dyn_cast(N0.getOperand(1))) { |
0 |
13968 |
if (ConstantSDNode *N01 = dyn_cast(N0.getOperand(1))) { |
0 |
| 13969 |
ShLeftAmt = N01->getZExtValue(); |
0 |
13969 |
ShLeftAmt = N01->getZExtValue(); |
0 |
| 13970 |
N0 = N0.getOperand(0); |
0 |
13970 |
N0 = N0.getOperand(0); |
0 |
| 13971 |
} |
--- |
13971 |
} |
--- |
| 13972 |
} |
--- |
13972 |
} |
--- |
| 13973 |
|
--- |
13973 |
|
--- |
| 13974 |
// If we haven't found a load, we can't narrow it. |
--- |
13974 |
// If we haven't found a load, we can't narrow it. |
--- |
| 13975 |
if (!isa(N0)) |
0 |
13975 |
if (!isa(N0)) |
0 |
| 13976 |
return SDValue(); |
0 |
13976 |
return SDValue(); |
0 |
| 13977 |
|
--- |
13977 |
|
--- |
| 13978 |
LoadSDNode *LN0 = cast(N0); |
0 |
13978 |
LoadSDNode *LN0 = cast(N0); |
0 |
| 13979 |
// Reducing the width of a volatile load is illegal. For atomics, we may be |
--- |
13979 |
// Reducing the width of a volatile load is illegal. For atomics, we may be |
--- |
| 13980 |
// able to reduce the width provided we never widen again. (see D66309) |
--- |
13980 |
// able to reduce the width provided we never widen again. (see D66309) |
--- |
| 13981 |
if (!LN0->isSimple() || |
0 |
13981 |
if (!LN0->isSimple() || |
0 |
| 13982 |
!isLegalNarrowLdSt(LN0, ExtType, ExtVT, ShAmt)) |
0 |
13982 |
!isLegalNarrowLdSt(LN0, ExtType, ExtVT, ShAmt)) |
0 |
| 13983 |
return SDValue(); |
0 |
13983 |
return SDValue(); |
0 |
| 13984 |
|
--- |
13984 |
|
--- |
| 13985 |
auto AdjustBigEndianShift = [&](unsigned ShAmt) { |
0 |
13985 |
auto AdjustBigEndianShift = [&](unsigned ShAmt) { |
0 |
| 13986 |
unsigned LVTStoreBits = |
--- |
13986 |
unsigned LVTStoreBits = |
--- |
| 13987 |
LN0->getMemoryVT().getStoreSizeInBits().getFixedValue(); |
0 |
13987 |
LN0->getMemoryVT().getStoreSizeInBits().getFixedValue(); |
0 |
| 13988 |
unsigned EVTStoreBits = ExtVT.getStoreSizeInBits().getFixedValue(); |
0 |
13988 |
unsigned EVTStoreBits = ExtVT.getStoreSizeInBits().getFixedValue(); |
0 |
| 13989 |
return LVTStoreBits - EVTStoreBits - ShAmt; |
0 |
13989 |
return LVTStoreBits - EVTStoreBits - ShAmt; |
0 |
| 13990 |
}; |
0 |
13990 |
}; |
0 |
| 13991 |
|
--- |
13991 |
|
--- |
| 13992 |
// We need to adjust the pointer to the load by ShAmt bits in order to load |
--- |
13992 |
// We need to adjust the pointer to the load by ShAmt bits in order to load |
--- |
| 13993 |
// the correct bytes. |
--- |
13993 |
// the correct bytes. |
--- |
| 13994 |
unsigned PtrAdjustmentInBits = |
--- |
13994 |
unsigned PtrAdjustmentInBits = |
--- |
| 13995 |
DAG.getDataLayout().isBigEndian() ? AdjustBigEndianShift(ShAmt) : ShAmt; |
0 |
13995 |
DAG.getDataLayout().isBigEndian() ? AdjustBigEndianShift(ShAmt) : ShAmt; |
0 |
| 13996 |
|
--- |
13996 |
|
--- |
| 13997 |
uint64_t PtrOff = PtrAdjustmentInBits / 8; |
0 |
13997 |
uint64_t PtrOff = PtrAdjustmentInBits / 8; |
0 |
| 13998 |
Align NewAlign = commonAlignment(LN0->getAlign(), PtrOff); |
0 |
13998 |
Align NewAlign = commonAlignment(LN0->getAlign(), PtrOff); |
0 |
| 13999 |
SDLoc DL(LN0); |
0 |
13999 |
SDLoc DL(LN0); |
0 |
| 14000 |
// The original load itself didn't wrap, so an offset within it doesn't. |
--- |
14000 |
// The original load itself didn't wrap, so an offset within it doesn't. |
--- |
| 14001 |
SDNodeFlags Flags; |
0 |
14001 |
SDNodeFlags Flags; |
0 |
| 14002 |
Flags.setNoUnsignedWrap(true); |
0 |
14002 |
Flags.setNoUnsignedWrap(true); |
0 |
| 14003 |
SDValue NewPtr = DAG.getMemBasePlusOffset(LN0->getBasePtr(), |
0 |
14003 |
SDValue NewPtr = DAG.getMemBasePlusOffset(LN0->getBasePtr(), |
0 |
| 14004 |
TypeSize::Fixed(PtrOff), DL, Flags); |
--- |
14004 |
TypeSize::Fixed(PtrOff), DL, Flags); |
--- |
| 14005 |
AddToWorklist(NewPtr.getNode()); |
0 |
14005 |
AddToWorklist(NewPtr.getNode()); |
0 |
| 14006 |
|
--- |
14006 |
|
--- |
| 14007 |
SDValue Load; |
0 |
14007 |
SDValue Load; |
0 |
| 14008 |
if (ExtType == ISD::NON_EXTLOAD) |
0 |
14008 |
if (ExtType == ISD::NON_EXTLOAD) |
0 |
| 14009 |
Load = DAG.getLoad(VT, DL, LN0->getChain(), NewPtr, |
0 |
14009 |
Load = DAG.getLoad(VT, DL, LN0->getChain(), NewPtr, |
0 |
| 14010 |
LN0->getPointerInfo().getWithOffset(PtrOff), NewAlign, |
0 |
14010 |
LN0->getPointerInfo().getWithOffset(PtrOff), NewAlign, |
0 |
| 14011 |
LN0->getMemOperand()->getFlags(), LN0->getAAInfo()); |
0 |
14011 |
LN0->getMemOperand()->getFlags(), LN0->getAAInfo()); |
0 |
| 14012 |
else |
--- |
14012 |
else |
--- |
| 14013 |
Load = DAG.getExtLoad(ExtType, DL, VT, LN0->getChain(), NewPtr, |
0 |
14013 |
Load = DAG.getExtLoad(ExtType, DL, VT, LN0->getChain(), NewPtr, |
0 |
| 14014 |
LN0->getPointerInfo().getWithOffset(PtrOff), ExtVT, |
0 |
14014 |
LN0->getPointerInfo().getWithOffset(PtrOff), ExtVT, |
0 |
| 14015 |
NewAlign, LN0->getMemOperand()->getFlags(), |
0 |
14015 |
NewAlign, LN0->getMemOperand()->getFlags(), |
0 |
| 14016 |
LN0->getAAInfo()); |
0 |
14016 |
LN0->getAAInfo()); |
0 |
| 14017 |
|
--- |
14017 |
|
--- |
| 14018 |
// Replace the old load's chain with the new load's chain. |
--- |
14018 |
// Replace the old load's chain with the new load's chain. |
--- |
| 14019 |
WorklistRemover DeadNodes(*this); |
0 |
14019 |
WorklistRemover DeadNodes(*this); |
0 |
| 14020 |
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); |
0 |
14020 |
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); |
0 |
| 14021 |
|
--- |
14021 |
|
--- |
| 14022 |
// Shift the result left, if we've swallowed a left shift. |
--- |
14022 |
// Shift the result left, if we've swallowed a left shift. |
--- |
| 14023 |
SDValue Result = Load; |
0 |
14023 |
SDValue Result = Load; |
0 |
| 14024 |
if (ShLeftAmt != 0) { |
0 |
14024 |
if (ShLeftAmt != 0) { |
0 |
| 14025 |
EVT ShImmTy = getShiftAmountTy(Result.getValueType()); |
0 |
14025 |
EVT ShImmTy = getShiftAmountTy(Result.getValueType()); |
0 |
| 14026 |
if (!isUIntN(ShImmTy.getScalarSizeInBits(), ShLeftAmt)) |
0 |
14026 |
if (!isUIntN(ShImmTy.getScalarSizeInBits(), ShLeftAmt)) |
0 |
| 14027 |
ShImmTy = VT; |
0 |
14027 |
ShImmTy = VT; |
0 |
| 14028 |
// If the shift amount is as large as the result size (but, presumably, |
--- |
14028 |
// If the shift amount is as large as the result size (but, presumably, |
--- |
| 14029 |
// no larger than the source) then the useful bits of the result are |
--- |
14029 |
// no larger than the source) then the useful bits of the result are |
--- |
| 14030 |
// zero; we can't simply return the shortened shift, because the result |
--- |
14030 |
// zero; we can't simply return the shortened shift, because the result |
--- |
| 14031 |
// of that operation is undefined. |
--- |
14031 |
// of that operation is undefined. |
--- |
| 14032 |
if (ShLeftAmt >= VT.getScalarSizeInBits()) |
0 |
14032 |
if (ShLeftAmt >= VT.getScalarSizeInBits()) |
0 |
| 14033 |
Result = DAG.getConstant(0, DL, VT); |
0 |
14033 |
Result = DAG.getConstant(0, DL, VT); |
0 |
| 14034 |
else |
--- |
14034 |
else |
--- |
| 14035 |
Result = DAG.getNode(ISD::SHL, DL, VT, |
0 |
14035 |
Result = DAG.getNode(ISD::SHL, DL, VT, |
0 |
| 14036 |
Result, DAG.getConstant(ShLeftAmt, DL, ShImmTy)); |
0 |
14036 |
Result, DAG.getConstant(ShLeftAmt, DL, ShImmTy)); |
0 |
| 14037 |
} |
--- |
14037 |
} |
--- |
| 14038 |
|
--- |
14038 |
|
--- |
| 14039 |
if (HasShiftedOffset) { |
0 |
14039 |
if (HasShiftedOffset) { |
0 |
| 14040 |
// We're using a shifted mask, so the load now has an offset. This means |
--- |
14040 |
// We're using a shifted mask, so the load now has an offset. This means |
--- |
| 14041 |
// that data has been loaded into the lower bytes than it would have been |
--- |
14041 |
// that data has been loaded into the lower bytes than it would have been |
--- |
| 14042 |
// before, so we need to shl the loaded data into the correct position in the |
--- |
14042 |
// before, so we need to shl the loaded data into the correct position in the |
--- |
| 14043 |
// register. |
--- |
14043 |
// register. |
--- |
| 14044 |
SDValue ShiftC = DAG.getConstant(ShAmt, DL, VT); |
0 |
14044 |
SDValue ShiftC = DAG.getConstant(ShAmt, DL, VT); |
0 |
| 14045 |
Result = DAG.getNode(ISD::SHL, DL, VT, Result, ShiftC); |
0 |
14045 |
Result = DAG.getNode(ISD::SHL, DL, VT, Result, ShiftC); |
0 |
| 14046 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); |
0 |
14046 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); |
0 |
| 14047 |
} |
--- |
14047 |
} |
--- |
| 14048 |
|
--- |
14048 |
|
--- |
| 14049 |
// Return the new loaded value. |
--- |
14049 |
// Return the new loaded value. |
--- |
| 14050 |
return Result; |
0 |
14050 |
return Result; |
0 |
| 14051 |
} |
0 |
14051 |
} |
0 |
| 14052 |
|
--- |
14052 |
|
--- |
| 14053 |
SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { |
0 |
14053 |
SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { |
0 |
| 14054 |
SDValue N0 = N->getOperand(0); |
0 |
14054 |
SDValue N0 = N->getOperand(0); |
0 |
| 14055 |
SDValue N1 = N->getOperand(1); |
0 |
14055 |
SDValue N1 = N->getOperand(1); |
0 |
| 14056 |
EVT VT = N->getValueType(0); |
0 |
14056 |
EVT VT = N->getValueType(0); |
0 |
| 14057 |
EVT ExtVT = cast(N1)->getVT(); |
0 |
14057 |
EVT ExtVT = cast(N1)->getVT(); |
0 |
| 14058 |
unsigned VTBits = VT.getScalarSizeInBits(); |
0 |
14058 |
unsigned VTBits = VT.getScalarSizeInBits(); |
0 |
| 14059 |
unsigned ExtVTBits = ExtVT.getScalarSizeInBits(); |
0 |
14059 |
unsigned ExtVTBits = ExtVT.getScalarSizeInBits(); |
0 |
| 14060 |
|
--- |
14060 |
|
--- |
| 14061 |
// sext_vector_inreg(undef) = 0 because the top bit will all be the same. |
--- |
14061 |
// sext_vector_inreg(undef) = 0 because the top bit will all be the same. |
--- |
| 14062 |
if (N0.isUndef()) |
0 |
14062 |
if (N0.isUndef()) |
0 |
| 14063 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
14063 |
return DAG.getConstant(0, SDLoc(N), VT); |
0 |
| 14064 |
|
--- |
14064 |
|
--- |
| 14065 |
// fold (sext_in_reg c1) -> c1 |
--- |
14065 |
// fold (sext_in_reg c1) -> c1 |
--- |
| 14066 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
14066 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) |
0 |
| 14067 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1); |
0 |
14067 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1); |
0 |
| 14068 |
|
--- |
14068 |
|
--- |
| 14069 |
// If the input is already sign extended, just drop the extension. |
--- |
14069 |
// If the input is already sign extended, just drop the extension. |
--- |
| 14070 |
if (ExtVTBits >= DAG.ComputeMaxSignificantBits(N0)) |
0 |
14070 |
if (ExtVTBits >= DAG.ComputeMaxSignificantBits(N0)) |
0 |
| 14071 |
return N0; |
0 |
14071 |
return N0; |
0 |
| 14072 |
|
--- |
14072 |
|
--- |
| 14073 |
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 |
--- |
14073 |
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 |
--- |
| 14074 |
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && |
0 |
14074 |
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && |
0 |
| 14075 |
ExtVT.bitsLT(cast(N0.getOperand(1))->getVT())) |
0 |
14075 |
ExtVT.bitsLT(cast(N0.getOperand(1))->getVT())) |
0 |
| 14076 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0.getOperand(0), |
0 |
14076 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0.getOperand(0), |
0 |
| 14077 |
N1); |
0 |
14077 |
N1); |
0 |
| 14078 |
|
--- |
14078 |
|
--- |
| 14079 |
// fold (sext_in_reg (sext x)) -> (sext x) |
--- |
14079 |
// fold (sext_in_reg (sext x)) -> (sext x) |
--- |
| 14080 |
// fold (sext_in_reg (aext x)) -> (sext x) |
--- |
14080 |
// fold (sext_in_reg (aext x)) -> (sext x) |
--- |
| 14081 |
// if x is small enough or if we know that x has more than 1 sign bit and the |
--- |
14081 |
// if x is small enough or if we know that x has more than 1 sign bit and the |
--- |
| 14082 |
// sign_extend_inreg is extending from one of them. |
--- |
14082 |
// sign_extend_inreg is extending from one of them. |
--- |
| 14083 |
if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { |
0 |
14083 |
if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { |
0 |
| 14084 |
SDValue N00 = N0.getOperand(0); |
0 |
14084 |
SDValue N00 = N0.getOperand(0); |
0 |
| 14085 |
unsigned N00Bits = N00.getScalarValueSizeInBits(); |
0 |
14085 |
unsigned N00Bits = N00.getScalarValueSizeInBits(); |
0 |
| 14086 |
if ((N00Bits <= ExtVTBits || |
0 |
14086 |
if ((N00Bits <= ExtVTBits || |
0 |
| 14087 |
DAG.ComputeMaxSignificantBits(N00) <= ExtVTBits) && |
0 |
14087 |
DAG.ComputeMaxSignificantBits(N00) <= ExtVTBits) && |
0 |
| 14088 |
(!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) |
0 |
14088 |
(!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) |
0 |
| 14089 |
return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00); |
0 |
14089 |
return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00); |
0 |
| 14090 |
} |
--- |
14090 |
} |
--- |
| 14091 |
|
--- |
14091 |
|
--- |
| 14092 |
// fold (sext_in_reg (*_extend_vector_inreg x)) -> (sext_vector_inreg x) |
--- |
14092 |
// fold (sext_in_reg (*_extend_vector_inreg x)) -> (sext_vector_inreg x) |
--- |
| 14093 |
// if x is small enough or if we know that x has more than 1 sign bit and the |
--- |
14093 |
// if x is small enough or if we know that x has more than 1 sign bit and the |
--- |
| 14094 |
// sign_extend_inreg is extending from one of them. |
--- |
14094 |
// sign_extend_inreg is extending from one of them. |
--- |
| 14095 |
if (ISD::isExtVecInRegOpcode(N0.getOpcode())) { |
0 |
14095 |
if (ISD::isExtVecInRegOpcode(N0.getOpcode())) { |
0 |
| 14096 |
SDValue N00 = N0.getOperand(0); |
0 |
14096 |
SDValue N00 = N0.getOperand(0); |
0 |
| 14097 |
unsigned N00Bits = N00.getScalarValueSizeInBits(); |
0 |
14097 |
unsigned N00Bits = N00.getScalarValueSizeInBits(); |
0 |
| 14098 |
unsigned DstElts = N0.getValueType().getVectorMinNumElements(); |
0 |
14098 |
unsigned DstElts = N0.getValueType().getVectorMinNumElements(); |
0 |
| 14099 |
unsigned SrcElts = N00.getValueType().getVectorMinNumElements(); |
0 |
14099 |
unsigned SrcElts = N00.getValueType().getVectorMinNumElements(); |
0 |
| 14100 |
bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; |
0 |
14100 |
bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; |
0 |
| 14101 |
APInt DemandedSrcElts = APInt::getLowBitsSet(SrcElts, DstElts); |
0 |
14101 |
APInt DemandedSrcElts = APInt::getLowBitsSet(SrcElts, DstElts); |
0 |
| 14102 |
if ((N00Bits == ExtVTBits || |
0 |
14102 |
if ((N00Bits == ExtVTBits || |
0 |
| 14103 |
(!IsZext && (N00Bits < ExtVTBits || |
0 |
14103 |
(!IsZext && (N00Bits < ExtVTBits || |
0 |
| 14104 |
DAG.ComputeMaxSignificantBits(N00) <= ExtVTBits))) && |
0 |
14104 |
DAG.ComputeMaxSignificantBits(N00) <= ExtVTBits))) && |
0 |
| 14105 |
(!LegalOperations || |
0 |
14105 |
(!LegalOperations || |
0 |
| 14106 |
TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT))) |
0 |
14106 |
TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT))) |
0 |
| 14107 |
return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, N00); |
0 |
14107 |
return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, N00); |
0 |
| 14108 |
} |
0 |
14108 |
} |
0 |
| 14109 |
|
--- |
14109 |
|
--- |
| 14110 |
// fold (sext_in_reg (zext x)) -> (sext x) |
--- |
14110 |
// fold (sext_in_reg (zext x)) -> (sext x) |
--- |
| 14111 |
// iff we are extending the source sign bit. |
--- |
14111 |
// iff we are extending the source sign bit. |
--- |
| 14112 |
if (N0.getOpcode() == ISD::ZERO_EXTEND) { |
0 |
14112 |
if (N0.getOpcode() == ISD::ZERO_EXTEND) { |
0 |
| 14113 |
SDValue N00 = N0.getOperand(0); |
0 |
14113 |
SDValue N00 = N0.getOperand(0); |
0 |
| 14114 |
if (N00.getScalarValueSizeInBits() == ExtVTBits && |
0 |
14114 |
if (N00.getScalarValueSizeInBits() == ExtVTBits && |
0 |
| 14115 |
(!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) |
0 |
14115 |
(!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) |
0 |
| 14116 |
return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00); |
0 |
14116 |
return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00); |
0 |
| 14117 |
} |
--- |
14117 |
} |
--- |
| 14118 |
|
--- |
14118 |
|
--- |
| 14119 |
// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. |
--- |
14119 |
// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. |
--- |
| 14120 |
if (DAG.MaskedValueIsZero(N0, APInt::getOneBitSet(VTBits, ExtVTBits - 1))) |
0 |
14120 |
if (DAG.MaskedValueIsZero(N0, APInt::getOneBitSet(VTBits, ExtVTBits - 1))) |
0 |
| 14121 |
return DAG.getZeroExtendInReg(N0, SDLoc(N), ExtVT); |
0 |
14121 |
return DAG.getZeroExtendInReg(N0, SDLoc(N), ExtVT); |
0 |
| 14122 |
|
--- |
14122 |
|
--- |
| 14123 |
// fold operands of sext_in_reg based on knowledge that the top bits are not |
--- |
14123 |
// fold operands of sext_in_reg based on knowledge that the top bits are not |
--- |
| 14124 |
// demanded. |
--- |
14124 |
// demanded. |
--- |
| 14125 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
14125 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
| 14126 |
return SDValue(N, 0); |
0 |
14126 |
return SDValue(N, 0); |
0 |
| 14127 |
|
--- |
14127 |
|
--- |
| 14128 |
// fold (sext_in_reg (load x)) -> (smaller sextload x) |
--- |
14128 |
// fold (sext_in_reg (load x)) -> (smaller sextload x) |
--- |
| 14129 |
// fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) |
--- |
14129 |
// fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) |
--- |
| 14130 |
if (SDValue NarrowLoad = reduceLoadWidth(N)) |
0 |
14130 |
if (SDValue NarrowLoad = reduceLoadWidth(N)) |
0 |
| 14131 |
return NarrowLoad; |
0 |
14131 |
return NarrowLoad; |
0 |
| 14132 |
|
--- |
14132 |
|
--- |
| 14133 |
// fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) |
--- |
14133 |
// fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) |
--- |
| 14134 |
// fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. |
--- |
14134 |
// fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. |
--- |
| 14135 |
// We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. |
--- |
14135 |
// We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. |
--- |
| 14136 |
if (N0.getOpcode() == ISD::SRL) { |
0 |
14136 |
if (N0.getOpcode() == ISD::SRL) { |
0 |
| 14137 |
if (auto *ShAmt = dyn_cast(N0.getOperand(1))) |
0 |
14137 |
if (auto *ShAmt = dyn_cast(N0.getOperand(1))) |
0 |
| 14138 |
if (ShAmt->getAPIntValue().ule(VTBits - ExtVTBits)) { |
0 |
14138 |
if (ShAmt->getAPIntValue().ule(VTBits - ExtVTBits)) { |
0 |
| 14139 |
// We can turn this into an SRA iff the input to the SRL is already sign |
--- |
14139 |
// We can turn this into an SRA iff the input to the SRL is already sign |
--- |
| 14140 |
// extended enough. |
--- |
14140 |
// extended enough. |
--- |
| 14141 |
unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); |
0 |
14141 |
unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); |
0 |
| 14142 |
if (((VTBits - ExtVTBits) - ShAmt->getZExtValue()) < InSignBits) |
0 |
14142 |
if (((VTBits - ExtVTBits) - ShAmt->getZExtValue()) < InSignBits) |
0 |
| 14143 |
return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0), |
0 |
14143 |
return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0), |
0 |
| 14144 |
N0.getOperand(1)); |
0 |
14144 |
N0.getOperand(1)); |
0 |
| 14145 |
} |
--- |
14145 |
} |
--- |
| 14146 |
} |
--- |
14146 |
} |
--- |
| 14147 |
|
--- |
14147 |
|
--- |
| 14148 |
// fold (sext_inreg (extload x)) -> (sextload x) |
--- |
14148 |
// fold (sext_inreg (extload x)) -> (sextload x) |
--- |
| 14149 |
// If sextload is not supported by target, we can only do the combine when |
--- |
14149 |
// If sextload is not supported by target, we can only do the combine when |
--- |
| 14150 |
// load has one use. Doing otherwise can block folding the extload with other |
--- |
14150 |
// load has one use. Doing otherwise can block folding the extload with other |
--- |
| 14151 |
// extends that the target does support. |
--- |
14151 |
// extends that the target does support. |
--- |
| 14152 |
if (ISD::isEXTLoad(N0.getNode()) && |
0 |
14152 |
if (ISD::isEXTLoad(N0.getNode()) && |
0 |
| 14153 |
ISD::isUNINDEXEDLoad(N0.getNode()) && |
0 |
14153 |
ISD::isUNINDEXEDLoad(N0.getNode()) && |
0 |
| 14154 |
ExtVT == cast(N0)->getMemoryVT() && |
0 |
14154 |
ExtVT == cast(N0)->getMemoryVT() && |
0 |
| 14155 |
((!LegalOperations && cast(N0)->isSimple() && |
0 |
14155 |
((!LegalOperations && cast(N0)->isSimple() && |
0 |
| 14156 |
N0.hasOneUse()) || |
0 |
14156 |
N0.hasOneUse()) || |
0 |
| 14157 |
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, ExtVT))) { |
0 |
14157 |
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, ExtVT))) { |
0 |
| 14158 |
LoadSDNode *LN0 = cast(N0); |
0 |
14158 |
LoadSDNode *LN0 = cast(N0); |
0 |
| 14159 |
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, |
0 |
14159 |
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, |
0 |
| 14160 |
LN0->getChain(), |
0 |
14160 |
LN0->getChain(), |
0 |
| 14161 |
LN0->getBasePtr(), ExtVT, |
0 |
14161 |
LN0->getBasePtr(), ExtVT, |
0 |
| 14162 |
LN0->getMemOperand()); |
--- |
14162 |
LN0->getMemOperand()); |
--- |
| 14163 |
CombineTo(N, ExtLoad); |
0 |
14163 |
CombineTo(N, ExtLoad); |
0 |
| 14164 |
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); |
0 |
14164 |
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); |
0 |
| 14165 |
AddToWorklist(ExtLoad.getNode()); |
0 |
14165 |
AddToWorklist(ExtLoad.getNode()); |
0 |
| 14166 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
14166 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 14167 |
} |
--- |
14167 |
} |
--- |
| 14168 |
|
--- |
14168 |
|
--- |
| 14169 |
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use |
--- |
14169 |
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use |
--- |
| 14170 |
if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && |
0 |
14170 |
if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && |
0 |
| 14171 |
N0.hasOneUse() && |
0 |
14171 |
N0.hasOneUse() && |
0 |
| 14172 |
ExtVT == cast(N0)->getMemoryVT() && |
0 |
14172 |
ExtVT == cast(N0)->getMemoryVT() && |
0 |
| 14173 |
((!LegalOperations && cast(N0)->isSimple()) && |
0 |
14173 |
((!LegalOperations && cast(N0)->isSimple()) && |
0 |
| 14174 |
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, ExtVT))) { |
0 |
14174 |
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, ExtVT))) { |
0 |
| 14175 |
LoadSDNode *LN0 = cast(N0); |
0 |
14175 |
LoadSDNode *LN0 = cast(N0); |
0 |
| 14176 |
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, |
0 |
14176 |
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, |
0 |
| 14177 |
LN0->getChain(), |
0 |
14177 |
LN0->getChain(), |
0 |
| 14178 |
LN0->getBasePtr(), ExtVT, |
0 |
14178 |
LN0->getBasePtr(), ExtVT, |
0 |
| 14179 |
LN0->getMemOperand()); |
--- |
14179 |
LN0->getMemOperand()); |
--- |
| 14180 |
CombineTo(N, ExtLoad); |
0 |
14180 |
CombineTo(N, ExtLoad); |
0 |
| 14181 |
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); |
0 |
14181 |
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); |
0 |
| 14182 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
14182 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 14183 |
} |
--- |
14183 |
} |
--- |
| 14184 |
|
--- |
14184 |
|
--- |
| 14185 |
// fold (sext_inreg (masked_load x)) -> (sext_masked_load x) |
--- |
14185 |
// fold (sext_inreg (masked_load x)) -> (sext_masked_load x) |
--- |
| 14186 |
// ignore it if the masked load is already sign extended |
--- |
14186 |
// ignore it if the masked load is already sign extended |
--- |
| 14187 |
if (MaskedLoadSDNode *Ld = dyn_cast(N0)) { |
0 |
14187 |
if (MaskedLoadSDNode *Ld = dyn_cast(N0)) { |
0 |
| 14188 |
if (ExtVT == Ld->getMemoryVT() && N0.hasOneUse() && |
0 |
14188 |
if (ExtVT == Ld->getMemoryVT() && N0.hasOneUse() && |
0 |
| 14189 |
Ld->getExtensionType() != ISD::LoadExtType::NON_EXTLOAD && |
0 |
14189 |
Ld->getExtensionType() != ISD::LoadExtType::NON_EXTLOAD && |
0 |
| 14190 |
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, ExtVT)) { |
0 |
14190 |
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, ExtVT)) { |
0 |
| 14191 |
SDValue ExtMaskedLoad = DAG.getMaskedLoad( |
0 |
14191 |
SDValue ExtMaskedLoad = DAG.getMaskedLoad( |
0 |
| 14192 |
VT, SDLoc(N), Ld->getChain(), Ld->getBasePtr(), Ld->getOffset(), |
0 |
14192 |
VT, SDLoc(N), Ld->getChain(), Ld->getBasePtr(), Ld->getOffset(), |
0 |
| 14193 |
Ld->getMask(), Ld->getPassThru(), ExtVT, Ld->getMemOperand(), |
0 |
14193 |
Ld->getMask(), Ld->getPassThru(), ExtVT, Ld->getMemOperand(), |
0 |
| 14194 |
Ld->getAddressingMode(), ISD::SEXTLOAD, Ld->isExpandingLoad()); |
0 |
14194 |
Ld->getAddressingMode(), ISD::SEXTLOAD, Ld->isExpandingLoad()); |
0 |
| 14195 |
CombineTo(N, ExtMaskedLoad); |
0 |
14195 |
CombineTo(N, ExtMaskedLoad); |
0 |
| 14196 |
CombineTo(N0.getNode(), ExtMaskedLoad, ExtMaskedLoad.getValue(1)); |
0 |
14196 |
CombineTo(N0.getNode(), ExtMaskedLoad, ExtMaskedLoad.getValue(1)); |
0 |
| 14197 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
14197 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 14198 |
} |
--- |
14198 |
} |
--- |
| 14199 |
} |
--- |
14199 |
} |
--- |
| 14200 |
|
--- |
14200 |
|
--- |
| 14201 |
// fold (sext_inreg (masked_gather x)) -> (sext_masked_gather x) |
--- |
14201 |
// fold (sext_inreg (masked_gather x)) -> (sext_masked_gather x) |
--- |
| 14202 |
if (auto *GN0 = dyn_cast(N0)) { |
0 |
14202 |
if (auto *GN0 = dyn_cast(N0)) { |
0 |
| 14203 |
if (SDValue(GN0, 0).hasOneUse() && |
0 |
14203 |
if (SDValue(GN0, 0).hasOneUse() && |
0 |
| 14204 |
ExtVT == GN0->getMemoryVT() && |
0 |
14204 |
ExtVT == GN0->getMemoryVT() && |
0 |
| 14205 |
TLI.isVectorLoadExtDesirable(SDValue(SDValue(GN0, 0)))) { |
0 |
14205 |
TLI.isVectorLoadExtDesirable(SDValue(SDValue(GN0, 0)))) { |
0 |
| 14206 |
SDValue Ops[] = {GN0->getChain(), GN0->getPassThru(), GN0->getMask(), |
0 |
14206 |
SDValue Ops[] = {GN0->getChain(), GN0->getPassThru(), GN0->getMask(), |
0 |
| 14207 |
GN0->getBasePtr(), GN0->getIndex(), GN0->getScale()}; |
0 |
14207 |
GN0->getBasePtr(), GN0->getIndex(), GN0->getScale()}; |
0 |
| 14208 |
|
--- |
14208 |
|
--- |
| 14209 |
SDValue ExtLoad = DAG.getMaskedGather( |
0 |
14209 |
SDValue ExtLoad = DAG.getMaskedGather( |
0 |
| 14210 |
DAG.getVTList(VT, MVT::Other), ExtVT, SDLoc(N), Ops, |
0 |
14210 |
DAG.getVTList(VT, MVT::Other), ExtVT, SDLoc(N), Ops, |
0 |
| 14211 |
GN0->getMemOperand(), GN0->getIndexType(), ISD::SEXTLOAD); |
--- |
14211 |
GN0->getMemOperand(), GN0->getIndexType(), ISD::SEXTLOAD); |
--- |
| 14212 |
|
--- |
14212 |
|
--- |
| 14213 |
CombineTo(N, ExtLoad); |
0 |
14213 |
CombineTo(N, ExtLoad); |
0 |
| 14214 |
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); |
0 |
14214 |
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); |
0 |
| 14215 |
AddToWorklist(ExtLoad.getNode()); |
0 |
14215 |
AddToWorklist(ExtLoad.getNode()); |
0 |
| 14216 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
14216 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 14217 |
} |
--- |
14217 |
} |
--- |
| 14218 |
} |
--- |
14218 |
} |
--- |
| 14219 |
|
--- |
14219 |
|
--- |
| 14220 |
// Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) |
--- |
14220 |
// Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) |
--- |
| 14221 |
if (ExtVTBits <= 16 && N0.getOpcode() == ISD::OR) { |
0 |
14221 |
if (ExtVTBits <= 16 && N0.getOpcode() == ISD::OR) { |
0 |
| 14222 |
if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), |
0 |
14222 |
if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), |
0 |
| 14223 |
N0.getOperand(1), false)) |
0 |
14223 |
N0.getOperand(1), false)) |
0 |
| 14224 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, BSwap, N1); |
0 |
14224 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, BSwap, N1); |
0 |
| 14225 |
} |
--- |
14225 |
} |
--- |
| 14226 |
|
--- |
14226 |
|
--- |
| 14227 |
// Fold (iM_signext_inreg |
--- |
14227 |
// Fold (iM_signext_inreg |
--- |
| 14228 |
// (extract_subvector (zext|anyext|sext iN_v to _) _) |
--- |
14228 |
// (extract_subvector (zext|anyext|sext iN_v to _) _) |
--- |
| 14229 |
// from iN) |
--- |
14229 |
// from iN) |
--- |
| 14230 |
// -> (extract_subvector (signext iN_v to iM)) |
--- |
14230 |
// -> (extract_subvector (signext iN_v to iM)) |
--- |
| 14231 |
if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && |
0 |
14231 |
if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && |
0 |
| 14232 |
ISD::isExtOpcode(N0.getOperand(0).getOpcode())) { |
0 |
14232 |
ISD::isExtOpcode(N0.getOperand(0).getOpcode())) { |
0 |
| 14233 |
SDValue InnerExt = N0.getOperand(0); |
0 |
14233 |
SDValue InnerExt = N0.getOperand(0); |
0 |
| 14234 |
EVT InnerExtVT = InnerExt->getValueType(0); |
0 |
14234 |
EVT InnerExtVT = InnerExt->getValueType(0); |
0 |
| 14235 |
SDValue Extendee = InnerExt->getOperand(0); |
0 |
14235 |
SDValue Extendee = InnerExt->getOperand(0); |
0 |
| 14236 |
|
--- |
14236 |
|
--- |
| 14237 |
if (ExtVTBits == Extendee.getValueType().getScalarSizeInBits() && |
0 |
14237 |
if (ExtVTBits == Extendee.getValueType().getScalarSizeInBits() && |
0 |
| 14238 |
(!LegalOperations || |
0 |
14238 |
(!LegalOperations || |
0 |
| 14239 |
TLI.isOperationLegal(ISD::SIGN_EXTEND, InnerExtVT))) { |
0 |
14239 |
TLI.isOperationLegal(ISD::SIGN_EXTEND, InnerExtVT))) { |
0 |
| 14240 |
SDValue SignExtExtendee = |
--- |
14240 |
SDValue SignExtExtendee = |
--- |
| 14241 |
DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), InnerExtVT, Extendee); |
0 |
14241 |
DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), InnerExtVT, Extendee); |
0 |
| 14242 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), VT, SignExtExtendee, |
0 |
14242 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), VT, SignExtExtendee, |
0 |
| 14243 |
N0.getOperand(1)); |
0 |
14243 |
N0.getOperand(1)); |
0 |
| 14244 |
} |
--- |
14244 |
} |
--- |
| 14245 |
} |
--- |
14245 |
} |
--- |
| 14246 |
|
--- |
14246 |
|
--- |
| 14247 |
return SDValue(); |
0 |
14247 |
return SDValue(); |
0 |
| 14248 |
} |
--- |
14248 |
} |
--- |
| 14249 |
|
--- |
14249 |
|
--- |
| 14250 |
static SDValue |
--- |
14250 |
static SDValue |
--- |
| 14251 |
foldExtendVectorInregToExtendOfSubvector(SDNode *N, const TargetLowering &TLI, |
0 |
14251 |
foldExtendVectorInregToExtendOfSubvector(SDNode *N, const TargetLowering &TLI, |
0 |
| 14252 |
SelectionDAG &DAG, |
--- |
14252 |
SelectionDAG &DAG, |
--- |
| 14253 |
bool LegalOperations) { |
--- |
14253 |
bool LegalOperations) { |
--- |
| 14254 |
unsigned InregOpcode = N->getOpcode(); |
0 |
14254 |
unsigned InregOpcode = N->getOpcode(); |
0 |
| 14255 |
unsigned Opcode = DAG.getOpcode_EXTEND(InregOpcode); |
0 |
14255 |
unsigned Opcode = DAG.getOpcode_EXTEND(InregOpcode); |
0 |
| 14256 |
|
--- |
14256 |
|
--- |
| 14257 |
SDValue Src = N->getOperand(0); |
0 |
14257 |
SDValue Src = N->getOperand(0); |
0 |
| 14258 |
EVT VT = N->getValueType(0); |
0 |
14258 |
EVT VT = N->getValueType(0); |
0 |
| 14259 |
EVT SrcVT = EVT::getVectorVT(*DAG.getContext(), |
0 |
14259 |
EVT SrcVT = EVT::getVectorVT(*DAG.getContext(), |
0 |
| 14260 |
Src.getValueType().getVectorElementType(), |
0 |
14260 |
Src.getValueType().getVectorElementType(), |
0 |
| 14261 |
VT.getVectorElementCount()); |
--- |
14261 |
VT.getVectorElementCount()); |
--- |
| 14262 |
|
--- |
14262 |
|
--- |
| 14263 |
assert(ISD::isExtVecInRegOpcode(InregOpcode) && |
0 |
14263 |
assert(ISD::isExtVecInRegOpcode(InregOpcode) && |
0 |
| 14264 |
"Expected EXTEND_VECTOR_INREG dag node in input!"); |
--- |
14264 |
"Expected EXTEND_VECTOR_INREG dag node in input!"); |
--- |
| 14265 |
|
--- |
14265 |
|
--- |
| 14266 |
// Profitability check: our operand must be an one-use CONCAT_VECTORS. |
--- |
14266 |
// Profitability check: our operand must be an one-use CONCAT_VECTORS. |
--- |
| 14267 |
// FIXME: one-use check may be overly restrictive |
--- |
14267 |
// FIXME: one-use check may be overly restrictive |
--- |
| 14268 |
if (!Src.hasOneUse() || Src.getOpcode() != ISD::CONCAT_VECTORS) |
0 |
14268 |
if (!Src.hasOneUse() || Src.getOpcode() != ISD::CONCAT_VECTORS) |
0 |
| 14269 |
return SDValue(); |
0 |
14269 |
return SDValue(); |
0 |
| 14270 |
|
--- |
14270 |
|
--- |
| 14271 |
// Profitability check: we must be extending exactly one of it's operands. |
--- |
14271 |
// Profitability check: we must be extending exactly one of it's operands. |
--- |
| 14272 |
// FIXME: this is probably overly restrictive. |
--- |
14272 |
// FIXME: this is probably overly restrictive. |
--- |
| 14273 |
Src = Src.getOperand(0); |
0 |
14273 |
Src = Src.getOperand(0); |
0 |
| 14274 |
if (Src.getValueType() != SrcVT) |
0 |
14274 |
if (Src.getValueType() != SrcVT) |
0 |
| 14275 |
return SDValue(); |
0 |
14275 |
return SDValue(); |
0 |
| 14276 |
|
--- |
14276 |
|
--- |
| 14277 |
if (LegalOperations && !TLI.isOperationLegal(Opcode, VT)) |
0 |
14277 |
if (LegalOperations && !TLI.isOperationLegal(Opcode, VT)) |
0 |
| 14278 |
return SDValue(); |
0 |
14278 |
return SDValue(); |
0 |
| 14279 |
|
--- |
14279 |
|
--- |
| 14280 |
return DAG.getNode(Opcode, SDLoc(N), VT, Src); |
0 |
14280 |
return DAG.getNode(Opcode, SDLoc(N), VT, Src); |
0 |
| 14281 |
} |
--- |
14281 |
} |
--- |
| 14282 |
|
--- |
14282 |
|
--- |
| 14283 |
SDValue DAGCombiner::visitEXTEND_VECTOR_INREG(SDNode *N) { |
0 |
14283 |
SDValue DAGCombiner::visitEXTEND_VECTOR_INREG(SDNode *N) { |
0 |
| 14284 |
SDValue N0 = N->getOperand(0); |
0 |
14284 |
SDValue N0 = N->getOperand(0); |
0 |
| 14285 |
EVT VT = N->getValueType(0); |
0 |
14285 |
EVT VT = N->getValueType(0); |
0 |
| 14286 |
|
--- |
14286 |
|
--- |
| 14287 |
if (N0.isUndef()) { |
0 |
14287 |
if (N0.isUndef()) { |
0 |
| 14288 |
// aext_vector_inreg(undef) = undef because the top bits are undefined. |
--- |
14288 |
// aext_vector_inreg(undef) = undef because the top bits are undefined. |
--- |
| 14289 |
// {s/z}ext_vector_inreg(undef) = 0 because the top bits must be the same. |
--- |
14289 |
// {s/z}ext_vector_inreg(undef) = 0 because the top bits must be the same. |
--- |
| 14290 |
return N->getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG |
0 |
14290 |
return N->getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG |
0 |
| 14291 |
? DAG.getUNDEF(VT) |
0 |
14291 |
? DAG.getUNDEF(VT) |
0 |
| 14292 |
: DAG.getConstant(0, SDLoc(N), VT); |
0 |
14292 |
: DAG.getConstant(0, SDLoc(N), VT); |
0 |
| 14293 |
} |
--- |
14293 |
} |
--- |
| 14294 |
|
--- |
14294 |
|
--- |
| 14295 |
if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes)) |
0 |
14295 |
if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes)) |
0 |
| 14296 |
return Res; |
0 |
14296 |
return Res; |
0 |
| 14297 |
|
--- |
14297 |
|
--- |
| 14298 |
if (SimplifyDemandedVectorElts(SDValue(N, 0))) |
0 |
14298 |
if (SimplifyDemandedVectorElts(SDValue(N, 0))) |
0 |
| 14299 |
return SDValue(N, 0); |
0 |
14299 |
return SDValue(N, 0); |
0 |
| 14300 |
|
--- |
14300 |
|
--- |
| 14301 |
if (SDValue R = foldExtendVectorInregToExtendOfSubvector(N, TLI, DAG, |
0 |
14301 |
if (SDValue R = foldExtendVectorInregToExtendOfSubvector(N, TLI, DAG, |
0 |
| 14302 |
LegalOperations)) |
0 |
14302 |
LegalOperations)) |
0 |
| 14303 |
return R; |
0 |
14303 |
return R; |
0 |
| 14304 |
|
--- |
14304 |
|
--- |
| 14305 |
return SDValue(); |
0 |
14305 |
return SDValue(); |
0 |
| 14306 |
} |
--- |
14306 |
} |
--- |
| 14307 |
|
--- |
14307 |
|
--- |
| 14308 |
SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { |
0 |
14308 |
SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { |
0 |
| 14309 |
SDValue N0 = N->getOperand(0); |
0 |
14309 |
SDValue N0 = N->getOperand(0); |
0 |
| 14310 |
EVT VT = N->getValueType(0); |
0 |
14310 |
EVT VT = N->getValueType(0); |
0 |
| 14311 |
EVT SrcVT = N0.getValueType(); |
0 |
14311 |
EVT SrcVT = N0.getValueType(); |
0 |
| 14312 |
bool isLE = DAG.getDataLayout().isLittleEndian(); |
0 |
14312 |
bool isLE = DAG.getDataLayout().isLittleEndian(); |
0 |
| 14313 |
|
--- |
14313 |
|
--- |
| 14314 |
// noop truncate |
--- |
14314 |
// noop truncate |
--- |
| 14315 |
if (SrcVT == VT) |
0 |
14315 |
if (SrcVT == VT) |
0 |
| 14316 |
return N0; |
0 |
14316 |
return N0; |
0 |
| 14317 |
|
--- |
14317 |
|
--- |
| 14318 |
// fold (truncate (truncate x)) -> (truncate x) |
--- |
14318 |
// fold (truncate (truncate x)) -> (truncate x) |
--- |
| 14319 |
if (N0.getOpcode() == ISD::TRUNCATE) |
0 |
14319 |
if (N0.getOpcode() == ISD::TRUNCATE) |
0 |
| 14320 |
return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0)); |
0 |
14320 |
return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0)); |
0 |
| 14321 |
|
--- |
14321 |
|
--- |
| 14322 |
// fold (truncate c1) -> c1 |
--- |
14322 |
// fold (truncate c1) -> c1 |
--- |
| 14323 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::TRUNCATE, SDLoc(N), VT, {N0})) |
0 |
14323 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::TRUNCATE, SDLoc(N), VT, {N0})) |
0 |
| 14324 |
return C; |
0 |
14324 |
return C; |
0 |
| 14325 |
|
--- |
14325 |
|
--- |
| 14326 |
// fold (truncate (ext x)) -> (ext x) or (truncate x) or x |
--- |
14326 |
// fold (truncate (ext x)) -> (ext x) or (truncate x) or x |
--- |
| 14327 |
if (N0.getOpcode() == ISD::ZERO_EXTEND || |
0 |
14327 |
if (N0.getOpcode() == ISD::ZERO_EXTEND || |
0 |
| 14328 |
N0.getOpcode() == ISD::SIGN_EXTEND || |
0 |
14328 |
N0.getOpcode() == ISD::SIGN_EXTEND || |
0 |
| 14329 |
N0.getOpcode() == ISD::ANY_EXTEND) { |
0 |
14329 |
N0.getOpcode() == ISD::ANY_EXTEND) { |
0 |
| 14330 |
// if the source is smaller than the dest, we still need an extend. |
--- |
14330 |
// if the source is smaller than the dest, we still need an extend. |
--- |
| 14331 |
if (N0.getOperand(0).getValueType().bitsLT(VT)) |
0 |
14331 |
if (N0.getOperand(0).getValueType().bitsLT(VT)) |
0 |
| 14332 |
return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); |
0 |
14332 |
return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); |
0 |
| 14333 |
// if the source is larger than the dest, than we just need the truncate. |
--- |
14333 |
// if the source is larger than the dest, than we just need the truncate. |
--- |
| 14334 |
if (N0.getOperand(0).getValueType().bitsGT(VT)) |
0 |
14334 |
if (N0.getOperand(0).getValueType().bitsGT(VT)) |
0 |
| 14335 |
return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0)); |
0 |
14335 |
return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0)); |
0 |
| 14336 |
// if the source and dest are the same type, we can drop both the extend |
--- |
14336 |
// if the source and dest are the same type, we can drop both the extend |
--- |
| 14337 |
// and the truncate. |
--- |
14337 |
// and the truncate. |
--- |
| 14338 |
return N0.getOperand(0); |
0 |
14338 |
return N0.getOperand(0); |
0 |
| 14339 |
} |
--- |
14339 |
} |
--- |
| 14340 |
|
--- |
14340 |
|
--- |
| 14341 |
// Try to narrow a truncate-of-sext_in_reg to the destination type: |
--- |
14341 |
// Try to narrow a truncate-of-sext_in_reg to the destination type: |
--- |
| 14342 |
// trunc (sign_ext_inreg X, iM) to iN --> sign_ext_inreg (trunc X to iN), iM |
--- |
14342 |
// trunc (sign_ext_inreg X, iM) to iN --> sign_ext_inreg (trunc X to iN), iM |
--- |
| 14343 |
if (!LegalTypes && N0.getOpcode() == ISD::SIGN_EXTEND_INREG && |
0 |
14343 |
if (!LegalTypes && N0.getOpcode() == ISD::SIGN_EXTEND_INREG && |
0 |
| 14344 |
N0.hasOneUse()) { |
0 |
14344 |
N0.hasOneUse()) { |
0 |
| 14345 |
SDValue X = N0.getOperand(0); |
0 |
14345 |
SDValue X = N0.getOperand(0); |
0 |
| 14346 |
SDValue ExtVal = N0.getOperand(1); |
0 |
14346 |
SDValue ExtVal = N0.getOperand(1); |
0 |
| 14347 |
EVT ExtVT = cast(ExtVal)->getVT(); |
0 |
14347 |
EVT ExtVT = cast(ExtVal)->getVT(); |
0 |
| 14348 |
if (ExtVT.bitsLT(VT)) { |
0 |
14348 |
if (ExtVT.bitsLT(VT)) { |
0 |
| 14349 |
SDValue TrX = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X); |
0 |
14349 |
SDValue TrX = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X); |
0 |
| 14350 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, TrX, ExtVal); |
0 |
14350 |
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, TrX, ExtVal); |
0 |
| 14351 |
} |
--- |
14351 |
} |
--- |
| 14352 |
} |
--- |
14352 |
} |
--- |
| 14353 |
|
--- |
14353 |
|
--- |
| 14354 |
// If this is anyext(trunc), don't fold it, allow ourselves to be folded. |
--- |
14354 |
// If this is anyext(trunc), don't fold it, allow ourselves to be folded. |
--- |
| 14355 |
if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ANY_EXTEND)) |
0 |
14355 |
if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ANY_EXTEND)) |
0 |
| 14356 |
return SDValue(); |
0 |
14356 |
return SDValue(); |
0 |
| 14357 |
|
--- |
14357 |
|
--- |
| 14358 |
// Fold extract-and-trunc into a narrow extract. For example: |
--- |
14358 |
// Fold extract-and-trunc into a narrow extract. For example: |
--- |
| 14359 |
// i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) |
--- |
14359 |
// i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) |
--- |
| 14360 |
// i32 y = TRUNCATE(i64 x) |
--- |
14360 |
// i32 y = TRUNCATE(i64 x) |
--- |
| 14361 |
// -- becomes -- |
--- |
14361 |
// -- becomes -- |
--- |
| 14362 |
// v16i8 b = BITCAST (v2i64 val) |
--- |
14362 |
// v16i8 b = BITCAST (v2i64 val) |
--- |
| 14363 |
// i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) |
--- |
14363 |
// i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) |
--- |
| 14364 |
// |
--- |
14364 |
// |
--- |
| 14365 |
// Note: We only run this optimization after type legalization (which often |
--- |
14365 |
// Note: We only run this optimization after type legalization (which often |
--- |
| 14366 |
// creates this pattern) and before operation legalization after which |
--- |
14366 |
// creates this pattern) and before operation legalization after which |
--- |
| 14367 |
// we need to be more careful about the vector instructions that we generate. |
--- |
14367 |
// we need to be more careful about the vector instructions that we generate. |
--- |
| 14368 |
if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
0 |
14368 |
if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
0 |
| 14369 |
LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) { |
0 |
14369 |
LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) { |
0 |
| 14370 |
EVT VecTy = N0.getOperand(0).getValueType(); |
0 |
14370 |
EVT VecTy = N0.getOperand(0).getValueType(); |
0 |
| 14371 |
EVT ExTy = N0.getValueType(); |
0 |
14371 |
EVT ExTy = N0.getValueType(); |
0 |
| 14372 |
EVT TrTy = N->getValueType(0); |
0 |
14372 |
EVT TrTy = N->getValueType(0); |
0 |
| 14373 |
|
--- |
14373 |
|
--- |
| 14374 |
auto EltCnt = VecTy.getVectorElementCount(); |
0 |
14374 |
auto EltCnt = VecTy.getVectorElementCount(); |
0 |
| 14375 |
unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); |
0 |
14375 |
unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); |
0 |
| 14376 |
auto NewEltCnt = EltCnt * SizeRatio; |
0 |
14376 |
auto NewEltCnt = EltCnt * SizeRatio; |
0 |
| 14377 |
|
--- |
14377 |
|
--- |
| 14378 |
EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, NewEltCnt); |
0 |
14378 |
EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, NewEltCnt); |
0 |
| 14379 |
assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); |
0 |
14379 |
assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); |
0 |
| 14380 |
|
--- |
14380 |
|
--- |
| 14381 |
SDValue EltNo = N0->getOperand(1); |
0 |
14381 |
SDValue EltNo = N0->getOperand(1); |
0 |
| 14382 |
if (isa(EltNo) && isTypeLegal(NVT)) { |
0 |
14382 |
if (isa(EltNo) && isTypeLegal(NVT)) { |
0 |
| 14383 |
int Elt = cast(EltNo)->getZExtValue(); |
0 |
14383 |
int Elt = cast(EltNo)->getZExtValue(); |
0 |
| 14384 |
int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); |
0 |
14384 |
int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); |
0 |
| 14385 |
|
--- |
14385 |
|
--- |
| 14386 |
SDLoc DL(N); |
0 |
14386 |
SDLoc DL(N); |
0 |
| 14387 |
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, TrTy, |
0 |
14387 |
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, TrTy, |
0 |
| 14388 |
DAG.getBitcast(NVT, N0.getOperand(0)), |
0 |
14388 |
DAG.getBitcast(NVT, N0.getOperand(0)), |
0 |
| 14389 |
DAG.getVectorIdxConstant(Index, DL)); |
0 |
14389 |
DAG.getVectorIdxConstant(Index, DL)); |
0 |
| 14390 |
} |
0 |
14390 |
} |
0 |
| 14391 |
} |
--- |
14391 |
} |
--- |
| 14392 |
|
--- |
14392 |
|
--- |
| 14393 |
// trunc (select c, a, b) -> select c, (trunc a), (trunc b) |
--- |
14393 |
// trunc (select c, a, b) -> select c, (trunc a), (trunc b) |
--- |
| 14394 |
if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) { |
0 |
14394 |
if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) { |
0 |
| 14395 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) && |
0 |
14395 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) && |
0 |
| 14396 |
TLI.isTruncateFree(SrcVT, VT)) { |
0 |
14396 |
TLI.isTruncateFree(SrcVT, VT)) { |
0 |
| 14397 |
SDLoc SL(N0); |
0 |
14397 |
SDLoc SL(N0); |
0 |
| 14398 |
SDValue Cond = N0.getOperand(0); |
0 |
14398 |
SDValue Cond = N0.getOperand(0); |
0 |
| 14399 |
SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1)); |
0 |
14399 |
SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1)); |
0 |
| 14400 |
SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2)); |
0 |
14400 |
SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2)); |
0 |
| 14401 |
return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1); |
0 |
14401 |
return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1); |
0 |
| 14402 |
} |
0 |
14402 |
} |
0 |
| 14403 |
} |
--- |
14403 |
} |
--- |
| 14404 |
|
--- |
14404 |
|
--- |
| 14405 |
// trunc (shl x, K) -> shl (trunc x), K => K < VT.getScalarSizeInBits() |
--- |
14405 |
// trunc (shl x, K) -> shl (trunc x), K => K < VT.getScalarSizeInBits() |
--- |
| 14406 |
if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() && |
0 |
14406 |
if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() && |
0 |
| 14407 |
(!LegalOperations || TLI.isOperationLegal(ISD::SHL, VT)) && |
0 |
14407 |
(!LegalOperations || TLI.isOperationLegal(ISD::SHL, VT)) && |
0 |
| 14408 |
TLI.isTypeDesirableForOp(ISD::SHL, VT)) { |
0 |
14408 |
TLI.isTypeDesirableForOp(ISD::SHL, VT)) { |
0 |
| 14409 |
SDValue Amt = N0.getOperand(1); |
0 |
14409 |
SDValue Amt = N0.getOperand(1); |
0 |
| 14410 |
KnownBits Known = DAG.computeKnownBits(Amt); |
0 |
14410 |
KnownBits Known = DAG.computeKnownBits(Amt); |
0 |
| 14411 |
unsigned Size = VT.getScalarSizeInBits(); |
0 |
14411 |
unsigned Size = VT.getScalarSizeInBits(); |
0 |
| 14412 |
if (Known.countMaxActiveBits() <= Log2_32(Size)) { |
0 |
14412 |
if (Known.countMaxActiveBits() <= Log2_32(Size)) { |
0 |
| 14413 |
SDLoc SL(N); |
0 |
14413 |
SDLoc SL(N); |
0 |
| 14414 |
EVT AmtVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); |
0 |
14414 |
EVT AmtVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); |
0 |
| 14415 |
|
--- |
14415 |
|
--- |
| 14416 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(0)); |
0 |
14416 |
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(0)); |
0 |
| 14417 |
if (AmtVT != Amt.getValueType()) { |
0 |
14417 |
if (AmtVT != Amt.getValueType()) { |
0 |
| 14418 |
Amt = DAG.getZExtOrTrunc(Amt, SL, AmtVT); |
0 |
14418 |
Amt = DAG.getZExtOrTrunc(Amt, SL, AmtVT); |
0 |
| 14419 |
AddToWorklist(Amt.getNode()); |
0 |
14419 |
AddToWorklist(Amt.getNode()); |
0 |
| 14420 |
} |
--- |
14420 |
} |
--- |
| 14421 |
return DAG.getNode(ISD::SHL, SL, VT, Trunc, Amt); |
0 |
14421 |
return DAG.getNode(ISD::SHL, SL, VT, Trunc, Amt); |
0 |
| 14422 |
} |
0 |
14422 |
} |
0 |
| 14423 |
} |
0 |
14423 |
} |
0 |
| 14424 |
|
--- |
14424 |
|
--- |
| 14425 |
if (SDValue V = foldSubToUSubSat(VT, N0.getNode())) |
0 |
14425 |
if (SDValue V = foldSubToUSubSat(VT, N0.getNode())) |
0 |
| 14426 |
return V; |
0 |
14426 |
return V; |
0 |
| 14427 |
|
--- |
14427 |
|
--- |
| 14428 |
if (SDValue ABD = foldABSToABD(N)) |
0 |
14428 |
if (SDValue ABD = foldABSToABD(N)) |
0 |
| 14429 |
return ABD; |
0 |
14429 |
return ABD; |
0 |
| 14430 |
|
--- |
14430 |
|
--- |
| 14431 |
// Attempt to pre-truncate BUILD_VECTOR sources. |
--- |
14431 |
// Attempt to pre-truncate BUILD_VECTOR sources. |
--- |
| 14432 |
if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations && |
0 |
14432 |
if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations && |
0 |
| 14433 |
TLI.isTruncateFree(SrcVT.getScalarType(), VT.getScalarType()) && |
0 |
14433 |
TLI.isTruncateFree(SrcVT.getScalarType(), VT.getScalarType()) && |
0 |
| 14434 |
// Avoid creating illegal types if running after type legalizer. |
--- |
14434 |
// Avoid creating illegal types if running after type legalizer. |
--- |
| 14435 |
(!LegalTypes || TLI.isTypeLegal(VT.getScalarType()))) { |
0 |
14435 |
(!LegalTypes || TLI.isTypeLegal(VT.getScalarType()))) { |
0 |
| 14436 |
SDLoc DL(N); |
0 |
14436 |
SDLoc DL(N); |
0 |
| 14437 |
EVT SVT = VT.getScalarType(); |
0 |
14437 |
EVT SVT = VT.getScalarType(); |
0 |
| 14438 |
SmallVector TruncOps; |
0 |
14438 |
SmallVector TruncOps; |
0 |
| 14439 |
for (const SDValue &Op : N0->op_values()) { |
0 |
14439 |
for (const SDValue &Op : N0->op_values()) { |
0 |
| 14440 |
SDValue TruncOp = DAG.getNode(ISD::TRUNCATE, DL, SVT, Op); |
0 |
14440 |
SDValue TruncOp = DAG.getNode(ISD::TRUNCATE, DL, SVT, Op); |
0 |
| 14441 |
TruncOps.push_back(TruncOp); |
0 |
14441 |
TruncOps.push_back(TruncOp); |
0 |
| 14442 |
} |
--- |
14442 |
} |
--- |
| 14443 |
return DAG.getBuildVector(VT, DL, TruncOps); |
0 |
14443 |
return DAG.getBuildVector(VT, DL, TruncOps); |
0 |
| 14444 |
} |
0 |
14444 |
} |
0 |
| 14445 |
|
--- |
14445 |
|
--- |
| 14446 |
// Fold a series of buildvector, bitcast, and truncate if possible. |
--- |
14446 |
// Fold a series of buildvector, bitcast, and truncate if possible. |
--- |
| 14447 |
// For example fold |
--- |
14447 |
// For example fold |
--- |
| 14448 |
// (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to |
--- |
14448 |
// (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to |
--- |
| 14449 |
// (2xi32 (buildvector x, y)). |
--- |
14449 |
// (2xi32 (buildvector x, y)). |
--- |
| 14450 |
if (Level == AfterLegalizeVectorOps && VT.isVector() && |
0 |
14450 |
if (Level == AfterLegalizeVectorOps && VT.isVector() && |
0 |
| 14451 |
N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && |
0 |
14451 |
N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && |
0 |
| 14452 |
N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && |
0 |
14452 |
N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && |
0 |
| 14453 |
N0.getOperand(0).hasOneUse()) { |
0 |
14453 |
N0.getOperand(0).hasOneUse()) { |
0 |
| 14454 |
SDValue BuildVect = N0.getOperand(0); |
0 |
14454 |
SDValue BuildVect = N0.getOperand(0); |
0 |
| 14455 |
EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType(); |
0 |
14455 |
EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType(); |
0 |
| 14456 |
EVT TruncVecEltTy = VT.getVectorElementType(); |
0 |
14456 |
EVT TruncVecEltTy = VT.getVectorElementType(); |
0 |
| 14457 |
|
--- |
14457 |
|
--- |
| 14458 |
// Check that the element types match. |
--- |
14458 |
// Check that the element types match. |
--- |
| 14459 |
if (BuildVectEltTy == TruncVecEltTy) { |
0 |
14459 |
if (BuildVectEltTy == TruncVecEltTy) { |
0 |
| 14460 |
// Now we only need to compute the offset of the truncated elements. |
--- |
14460 |
// Now we only need to compute the offset of the truncated elements. |
--- |
| 14461 |
unsigned BuildVecNumElts = BuildVect.getNumOperands(); |
0 |
14461 |
unsigned BuildVecNumElts = BuildVect.getNumOperands(); |
0 |
| 14462 |
unsigned TruncVecNumElts = VT.getVectorNumElements(); |
0 |
14462 |
unsigned TruncVecNumElts = VT.getVectorNumElements(); |
0 |
| 14463 |
unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts; |
0 |
14463 |
unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts; |
0 |
| 14464 |
|
--- |
14464 |
|
--- |
| 14465 |
assert((BuildVecNumElts % TruncVecNumElts) == 0 && |
0 |
14465 |
assert((BuildVecNumElts % TruncVecNumElts) == 0 && |
0 |
| 14466 |
"Invalid number of elements"); |
--- |
14466 |
"Invalid number of elements"); |
--- |
| 14467 |
|
--- |
14467 |
|
--- |
| 14468 |
SmallVector Opnds; |
0 |
14468 |
SmallVector Opnds; |
0 |
| 14469 |
for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset) |
0 |
14469 |
for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset) |
0 |
| 14470 |
Opnds.push_back(BuildVect.getOperand(i)); |
0 |
14470 |
Opnds.push_back(BuildVect.getOperand(i)); |
0 |
| 14471 |
|
--- |
14471 |
|
--- |
| 14472 |
return DAG.getBuildVector(VT, SDLoc(N), Opnds); |
0 |
14472 |
return DAG.getBuildVector(VT, SDLoc(N), Opnds); |
0 |
| 14473 |
} |
0 |
14473 |
} |
0 |
| 14474 |
} |
--- |
14474 |
} |
--- |
| 14475 |
|
--- |
14475 |
|
--- |
| 14476 |
// fold (truncate (load x)) -> (smaller load x) |
--- |
14476 |
// fold (truncate (load x)) -> (smaller load x) |
--- |
| 14477 |
// fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) |
--- |
14477 |
// fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) |
--- |
| 14478 |
if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { |
0 |
14478 |
if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { |
0 |
| 14479 |
if (SDValue Reduced = reduceLoadWidth(N)) |
0 |
14479 |
if (SDValue Reduced = reduceLoadWidth(N)) |
0 |
| 14480 |
return Reduced; |
0 |
14480 |
return Reduced; |
0 |
| 14481 |
|
--- |
14481 |
|
--- |
| 14482 |
// Handle the case where the load remains an extending load even |
--- |
14482 |
// Handle the case where the load remains an extending load even |
--- |
| 14483 |
// after truncation. |
--- |
14483 |
// after truncation. |
--- |
| 14484 |
if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) { |
0 |
14484 |
if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) { |
0 |
| 14485 |
LoadSDNode *LN0 = cast(N0); |
0 |
14485 |
LoadSDNode *LN0 = cast(N0); |
0 |
| 14486 |
if (LN0->isSimple() && LN0->getMemoryVT().bitsLT(VT)) { |
0 |
14486 |
if (LN0->isSimple() && LN0->getMemoryVT().bitsLT(VT)) { |
0 |
| 14487 |
SDValue NewLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(LN0), |
0 |
14487 |
SDValue NewLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(LN0), |
0 |
| 14488 |
VT, LN0->getChain(), LN0->getBasePtr(), |
0 |
14488 |
VT, LN0->getChain(), LN0->getBasePtr(), |
0 |
| 14489 |
LN0->getMemoryVT(), |
--- |
14489 |
LN0->getMemoryVT(), |
--- |
| 14490 |
LN0->getMemOperand()); |
--- |
14490 |
LN0->getMemOperand()); |
--- |
| 14491 |
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1)); |
0 |
14491 |
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1)); |
0 |
| 14492 |
return NewLoad; |
0 |
14492 |
return NewLoad; |
0 |
| 14493 |
} |
--- |
14493 |
} |
--- |
| 14494 |
} |
--- |
14494 |
} |
--- |
| 14495 |
} |
--- |
14495 |
} |
--- |
| 14496 |
|
--- |
14496 |
|
--- |
| 14497 |
// fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)), |
--- |
14497 |
// fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)), |
--- |
| 14498 |
// where ... are all 'undef'. |
--- |
14498 |
// where ... are all 'undef'. |
--- |
| 14499 |
if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { |
0 |
14499 |
if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { |
0 |
| 14500 |
SmallVector VTs; |
0 |
14500 |
SmallVector VTs; |
0 |
| 14501 |
SDValue V; |
0 |
14501 |
SDValue V; |
0 |
| 14502 |
unsigned Idx = 0; |
0 |
14502 |
unsigned Idx = 0; |
0 |
| 14503 |
unsigned NumDefs = 0; |
0 |
14503 |
unsigned NumDefs = 0; |
0 |
| 14504 |
|
--- |
14504 |
|
--- |
| 14505 |
for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { |
0 |
14505 |
for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { |
0 |
| 14506 |
SDValue X = N0.getOperand(i); |
0 |
14506 |
SDValue X = N0.getOperand(i); |
0 |
| 14507 |
if (!X.isUndef()) { |
0 |
14507 |
if (!X.isUndef()) { |
0 |
| 14508 |
V = X; |
0 |
14508 |
V = X; |
0 |
| 14509 |
Idx = i; |
0 |
14509 |
Idx = i; |
0 |
| 14510 |
NumDefs++; |
0 |
14510 |
NumDefs++; |
0 |
| 14511 |
} |
--- |
14511 |
} |
--- |
| 14512 |
// Stop if more than one members are non-undef. |
--- |
14512 |
// Stop if more than one members are non-undef. |
--- |
| 14513 |
if (NumDefs > 1) |
0 |
14513 |
if (NumDefs > 1) |
0 |
| 14514 |
break; |
0 |
14514 |
break; |
0 |
| 14515 |
|
--- |
14515 |
|
--- |
| 14516 |
VTs.push_back(EVT::getVectorVT(*DAG.getContext(), |
0 |
14516 |
VTs.push_back(EVT::getVectorVT(*DAG.getContext(), |
0 |
| 14517 |
VT.getVectorElementType(), |
--- |
14517 |
VT.getVectorElementType(), |
--- |
| 14518 |
X.getValueType().getVectorElementCount())); |
0 |
14518 |
X.getValueType().getVectorElementCount())); |
0 |
| 14519 |
} |
--- |
14519 |
} |
--- |
| 14520 |
|
--- |
14520 |
|
--- |
| 14521 |
if (NumDefs == 0) |
0 |
14521 |
if (NumDefs == 0) |
0 |
| 14522 |
return DAG.getUNDEF(VT); |
0 |
14522 |
return DAG.getUNDEF(VT); |
0 |
| 14523 |
|
--- |
14523 |
|
--- |
| 14524 |
if (NumDefs == 1) { |
0 |
14524 |
if (NumDefs == 1) { |
0 |
| 14525 |
assert(V.getNode() && "The single defined operand is empty!"); |
0 |
14525 |
assert(V.getNode() && "The single defined operand is empty!"); |
0 |
| 14526 |
SmallVector Opnds; |
0 |
14526 |
SmallVector Opnds; |
0 |
| 14527 |
for (unsigned i = 0, e = VTs.size(); i != e; ++i) { |
0 |
14527 |
for (unsigned i = 0, e = VTs.size(); i != e; ++i) { |
0 |
| 14528 |
if (i != Idx) { |
0 |
14528 |
if (i != Idx) { |
0 |
| 14529 |
Opnds.push_back(DAG.getUNDEF(VTs[i])); |
0 |
14529 |
Opnds.push_back(DAG.getUNDEF(VTs[i])); |
0 |
| 14530 |
continue; |
0 |
14530 |
continue; |
0 |
| 14531 |
} |
--- |
14531 |
} |
--- |
| 14532 |
SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V); |
0 |
14532 |
SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V); |
0 |
| 14533 |
AddToWorklist(NV.getNode()); |
0 |
14533 |
AddToWorklist(NV.getNode()); |
0 |
| 14534 |
Opnds.push_back(NV); |
0 |
14534 |
Opnds.push_back(NV); |
0 |
| 14535 |
} |
--- |
14535 |
} |
--- |
| 14536 |
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds); |
0 |
14536 |
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds); |
0 |
| 14537 |
} |
0 |
14537 |
} |
0 |
| 14538 |
} |
0 |
14538 |
} |
0 |
| 14539 |
|
--- |
14539 |
|
--- |
| 14540 |
// Fold truncate of a bitcast of a vector to an extract of the low vector |
--- |
14540 |
// Fold truncate of a bitcast of a vector to an extract of the low vector |
--- |
| 14541 |
// element. |
--- |
14541 |
// element. |
--- |
| 14542 |
// |
--- |
14542 |
// |
--- |
| 14543 |
// e.g. trunc (i64 (bitcast v2i32:x)) -> extract_vector_elt v2i32:x, idx |
--- |
14543 |
// e.g. trunc (i64 (bitcast v2i32:x)) -> extract_vector_elt v2i32:x, idx |
--- |
| 14544 |
if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) { |
0 |
14544 |
if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) { |
0 |
| 14545 |
SDValue VecSrc = N0.getOperand(0); |
0 |
14545 |
SDValue VecSrc = N0.getOperand(0); |
0 |
| 14546 |
EVT VecSrcVT = VecSrc.getValueType(); |
0 |
14546 |
EVT VecSrcVT = VecSrc.getValueType(); |
0 |
| 14547 |
if (VecSrcVT.isVector() && VecSrcVT.getScalarType() == VT && |
0 |
14547 |
if (VecSrcVT.isVector() && VecSrcVT.getScalarType() == VT && |
0 |
| 14548 |
(!LegalOperations || |
0 |
14548 |
(!LegalOperations || |
0 |
| 14549 |
TLI.isOperationLegal(ISD::EXTRACT_VECTOR_ELT, VecSrcVT))) { |
0 |
14549 |
TLI.isOperationLegal(ISD::EXTRACT_VECTOR_ELT, VecSrcVT))) { |
0 |
| 14550 |
SDLoc SL(N); |
0 |
14550 |
SDLoc SL(N); |
0 |
| 14551 |
|
--- |
14551 |
|
--- |
| 14552 |
unsigned Idx = isLE ? 0 : VecSrcVT.getVectorNumElements() - 1; |
0 |
14552 |
unsigned Idx = isLE ? 0 : VecSrcVT.getVectorNumElements() - 1; |
0 |
| 14553 |
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, VT, VecSrc, |
0 |
14553 |
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, VT, VecSrc, |
0 |
| 14554 |
DAG.getVectorIdxConstant(Idx, SL)); |
0 |
14554 |
DAG.getVectorIdxConstant(Idx, SL)); |
0 |
| 14555 |
} |
0 |
14555 |
} |
0 |
| 14556 |
} |
--- |
14556 |
} |
--- |
| 14557 |
|
--- |
14557 |
|
--- |
| 14558 |
// Simplify the operands using demanded-bits information. |
--- |
14558 |
// Simplify the operands using demanded-bits information. |
--- |
| 14559 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
14559 |
if (SimplifyDemandedBits(SDValue(N, 0))) |
0 |
| 14560 |
return SDValue(N, 0); |
0 |
14560 |
return SDValue(N, 0); |
0 |
| 14561 |
|
--- |
14561 |
|
--- |
| 14562 |
// fold (truncate (extract_subvector(ext x))) -> |
--- |
14562 |
// fold (truncate (extract_subvector(ext x))) -> |
--- |
| 14563 |
// (extract_subvector x) |
--- |
14563 |
// (extract_subvector x) |
--- |
| 14564 |
// TODO: This can be generalized to cover cases where the truncate and extract |
--- |
14564 |
// TODO: This can be generalized to cover cases where the truncate and extract |
--- |
| 14565 |
// do not fully cancel each other out. |
--- |
14565 |
// do not fully cancel each other out. |
--- |
| 14566 |
if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { |
0 |
14566 |
if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { |
0 |
| 14567 |
SDValue N00 = N0.getOperand(0); |
0 |
14567 |
SDValue N00 = N0.getOperand(0); |
0 |
| 14568 |
if (N00.getOpcode() == ISD::SIGN_EXTEND || |
0 |
14568 |
if (N00.getOpcode() == ISD::SIGN_EXTEND || |
0 |
| 14569 |
N00.getOpcode() == ISD::ZERO_EXTEND || |
0 |
14569 |
N00.getOpcode() == ISD::ZERO_EXTEND || |
0 |
| 14570 |
N00.getOpcode() == ISD::ANY_EXTEND) { |
0 |
14570 |
N00.getOpcode() == ISD::ANY_EXTEND) { |
0 |
| 14571 |
if (N00.getOperand(0)->getValueType(0).getVectorElementType() == |
0 |
14571 |
if (N00.getOperand(0)->getValueType(0).getVectorElementType() == |
0 |
| 14572 |
VT.getVectorElementType()) |
--- |
14572 |
VT.getVectorElementType()) |
--- |
| 14573 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N0->getOperand(0)), VT, |
0 |
14573 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N0->getOperand(0)), VT, |
0 |
| 14574 |
N00.getOperand(0), N0.getOperand(1)); |
0 |
14574 |
N00.getOperand(0), N0.getOperand(1)); |
0 |
| 14575 |
} |
--- |
14575 |
} |
--- |
| 14576 |
} |
--- |
14576 |
} |
--- |
| 14577 |
|
--- |
14577 |
|
--- |
| 14578 |
if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N)) |
0 |
14578 |
if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N)) |
0 |
| 14579 |
return NewVSel; |
0 |
14579 |
return NewVSel; |
0 |
| 14580 |
|
--- |
14580 |
|
--- |
| 14581 |
// Narrow a suitable binary operation with a non-opaque constant operand by |
--- |
14581 |
// Narrow a suitable binary operation with a non-opaque constant operand by |
--- |
| 14582 |
// moving it ahead of the truncate. This is limited to pre-legalization |
--- |
14582 |
// moving it ahead of the truncate. This is limited to pre-legalization |
--- |
| 14583 |
// because targets may prefer a wider type during later combines and invert |
--- |
14583 |
// because targets may prefer a wider type during later combines and invert |
--- |
| 14584 |
// this transform. |
--- |
14584 |
// this transform. |
--- |
| 14585 |
switch (N0.getOpcode()) { |
0 |
14585 |
switch (N0.getOpcode()) { |
0 |
| 14586 |
case ISD::ADD: |
0 |
14586 |
case ISD::ADD: |
0 |
| 14587 |
case ISD::SUB: |
--- |
14587 |
case ISD::SUB: |
--- |
| 14588 |
case ISD::MUL: |
--- |
14588 |
case ISD::MUL: |
--- |
| 14589 |
case ISD::AND: |
--- |
14589 |
case ISD::AND: |
--- |
| 14590 |
case ISD::OR: |
--- |
14590 |
case ISD::OR: |
--- |
| 14591 |
case ISD::XOR: |
--- |
14591 |
case ISD::XOR: |
--- |
| 14592 |
if (!LegalOperations && N0.hasOneUse() && |
0 |
14592 |
if (!LegalOperations && N0.hasOneUse() && |
0 |
| 14593 |
(isConstantOrConstantVector(N0.getOperand(0), true) || |
0 |
14593 |
(isConstantOrConstantVector(N0.getOperand(0), true) || |
0 |
| 14594 |
isConstantOrConstantVector(N0.getOperand(1), true))) { |
0 |
14594 |
isConstantOrConstantVector(N0.getOperand(1), true))) { |
0 |
| 14595 |
// TODO: We already restricted this to pre-legalization, but for vectors |
--- |
14595 |
// TODO: We already restricted this to pre-legalization, but for vectors |
--- |
| 14596 |
// we are extra cautious to not create an unsupported operation. |
--- |
14596 |
// we are extra cautious to not create an unsupported operation. |
--- |
| 14597 |
// Target-specific changes are likely needed to avoid regressions here. |
--- |
14597 |
// Target-specific changes are likely needed to avoid regressions here. |
--- |
| 14598 |
if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) { |
0 |
14598 |
if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) { |
0 |
| 14599 |
SDLoc DL(N); |
0 |
14599 |
SDLoc DL(N); |
0 |
| 14600 |
SDValue NarrowL = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0)); |
0 |
14600 |
SDValue NarrowL = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0)); |
0 |
| 14601 |
SDValue NarrowR = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(1)); |
0 |
14601 |
SDValue NarrowR = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(1)); |
0 |
| 14602 |
return DAG.getNode(N0.getOpcode(), DL, VT, NarrowL, NarrowR); |
0 |
14602 |
return DAG.getNode(N0.getOpcode(), DL, VT, NarrowL, NarrowR); |
0 |
| 14603 |
} |
0 |
14603 |
} |
0 |
| 14604 |
} |
--- |
14604 |
} |
--- |
| 14605 |
break; |
0 |
14605 |
break; |
0 |
| 14606 |
case ISD::ADDE: |
0 |
14606 |
case ISD::ADDE: |
0 |
| 14607 |
case ISD::UADDO_CARRY: |
--- |
14607 |
case ISD::UADDO_CARRY: |
--- |
| 14608 |
// (trunc adde(X, Y, Carry)) -> (adde trunc(X), trunc(Y), Carry) |
--- |
14608 |
// (trunc adde(X, Y, Carry)) -> (adde trunc(X), trunc(Y), Carry) |
--- |
| 14609 |
// (trunc uaddo_carry(X, Y, Carry)) -> |
--- |
14609 |
// (trunc uaddo_carry(X, Y, Carry)) -> |
--- |
| 14610 |
// (uaddo_carry trunc(X), trunc(Y), Carry) |
--- |
14610 |
// (uaddo_carry trunc(X), trunc(Y), Carry) |
--- |
| 14611 |
// When the adde's carry is not used. |
--- |
14611 |
// When the adde's carry is not used. |
--- |
| 14612 |
// We only do for uaddo_carry before legalize operation |
--- |
14612 |
// We only do for uaddo_carry before legalize operation |
--- |
| 14613 |
if (((!LegalOperations && N0.getOpcode() == ISD::UADDO_CARRY) || |
0 |
14613 |
if (((!LegalOperations && N0.getOpcode() == ISD::UADDO_CARRY) || |
0 |
| 14614 |
TLI.isOperationLegal(N0.getOpcode(), VT)) && |
0 |
14614 |
TLI.isOperationLegal(N0.getOpcode(), VT)) && |
0 |
| 14615 |
N0.hasOneUse() && !N0->hasAnyUseOfValue(1)) { |
0 |
14615 |
N0.hasOneUse() && !N0->hasAnyUseOfValue(1)) { |
0 |
| 14616 |
SDLoc DL(N); |
0 |
14616 |
SDLoc DL(N); |
0 |
| 14617 |
SDValue X = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0)); |
0 |
14617 |
SDValue X = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0)); |
0 |
| 14618 |
SDValue Y = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(1)); |
0 |
14618 |
SDValue Y = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(1)); |
0 |
| 14619 |
SDVTList VTs = DAG.getVTList(VT, N0->getValueType(1)); |
0 |
14619 |
SDVTList VTs = DAG.getVTList(VT, N0->getValueType(1)); |
0 |
| 14620 |
return DAG.getNode(N0.getOpcode(), DL, VTs, X, Y, N0.getOperand(2)); |
0 |
14620 |
return DAG.getNode(N0.getOpcode(), DL, VTs, X, Y, N0.getOperand(2)); |
0 |
| 14621 |
} |
0 |
14621 |
} |
0 |
| 14622 |
break; |
0 |
14622 |
break; |
0 |
| 14623 |
case ISD::USUBSAT: |
0 |
14623 |
case ISD::USUBSAT: |
0 |
| 14624 |
// Truncate the USUBSAT only if LHS is a known zero-extension, its not |
--- |
14624 |
// Truncate the USUBSAT only if LHS is a known zero-extension, its not |
--- |
| 14625 |
// enough to know that the upper bits are zero we must ensure that we don't |
--- |
14625 |
// enough to know that the upper bits are zero we must ensure that we don't |
--- |
| 14626 |
// introduce an extra truncate. |
--- |
14626 |
// introduce an extra truncate. |
--- |
| 14627 |
if (!LegalOperations && N0.hasOneUse() && |
0 |
14627 |
if (!LegalOperations && N0.hasOneUse() && |
0 |
| 14628 |
N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && |
0 |
14628 |
N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && |
0 |
| 14629 |
N0.getOperand(0).getOperand(0).getScalarValueSizeInBits() <= |
0 |
14629 |
N0.getOperand(0).getOperand(0).getScalarValueSizeInBits() <= |
0 |
| 14630 |
VT.getScalarSizeInBits() && |
0 |
14630 |
VT.getScalarSizeInBits() && |
0 |
| 14631 |
hasOperation(N0.getOpcode(), VT)) { |
0 |
14631 |
hasOperation(N0.getOpcode(), VT)) { |
0 |
| 14632 |
return getTruncatedUSUBSAT(VT, SrcVT, N0.getOperand(0), N0.getOperand(1), |
0 |
14632 |
return getTruncatedUSUBSAT(VT, SrcVT, N0.getOperand(0), N0.getOperand(1), |
0 |
| 14633 |
DAG, SDLoc(N)); |
0 |
14633 |
DAG, SDLoc(N)); |
0 |
| 14634 |
} |
--- |
14634 |
} |
--- |
| 14635 |
break; |
0 |
14635 |
break; |
0 |
| 14636 |
} |
--- |
14636 |
} |
--- |
| 14637 |
|
--- |
14637 |
|
--- |
| 14638 |
return SDValue(); |
0 |
14638 |
return SDValue(); |
0 |
| 14639 |
} |
--- |
14639 |
} |
--- |
| 14640 |
|
--- |
14640 |
|
--- |
| 14641 |
static SDNode *getBuildPairElt(SDNode *N, unsigned i) { |
0 |
14641 |
static SDNode *getBuildPairElt(SDNode *N, unsigned i) { |
0 |
| 14642 |
SDValue Elt = N->getOperand(i); |
0 |
14642 |
SDValue Elt = N->getOperand(i); |
0 |
| 14643 |
if (Elt.getOpcode() != ISD::MERGE_VALUES) |
0 |
14643 |
if (Elt.getOpcode() != ISD::MERGE_VALUES) |
0 |
| 14644 |
return Elt.getNode(); |
0 |
14644 |
return Elt.getNode(); |
0 |
| 14645 |
return Elt.getOperand(Elt.getResNo()).getNode(); |
0 |
14645 |
return Elt.getOperand(Elt.getResNo()).getNode(); |
0 |
| 14646 |
} |
--- |
14646 |
} |
--- |
| 14647 |
|
--- |
14647 |
|
--- |
| 14648 |
/// build_pair (load, load) -> load |
--- |
14648 |
/// build_pair (load, load) -> load |
--- |
| 14649 |
/// if load locations are consecutive. |
--- |
14649 |
/// if load locations are consecutive. |
--- |
| 14650 |
SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { |
0 |
14650 |
SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { |
0 |
| 14651 |
assert(N->getOpcode() == ISD::BUILD_PAIR); |
0 |
14651 |
assert(N->getOpcode() == ISD::BUILD_PAIR); |
0 |
| 14652 |
|
--- |
14652 |
|
--- |
| 14653 |
auto *LD1 = dyn_cast(getBuildPairElt(N, 0)); |
0 |
14653 |
auto *LD1 = dyn_cast(getBuildPairElt(N, 0)); |
0 |
| 14654 |
auto *LD2 = dyn_cast(getBuildPairElt(N, 1)); |
0 |
14654 |
auto *LD2 = dyn_cast(getBuildPairElt(N, 1)); |
0 |
| 14655 |
|
--- |
14655 |
|
--- |
| 14656 |
// A BUILD_PAIR is always having the least significant part in elt 0 and the |
--- |
14656 |
// A BUILD_PAIR is always having the least significant part in elt 0 and the |
--- |
| 14657 |
// most significant part in elt 1. So when combining into one large load, we |
--- |
14657 |
// most significant part in elt 1. So when combining into one large load, we |
--- |
| 14658 |
// need to consider the endianness. |
--- |
14658 |
// need to consider the endianness. |
--- |
| 14659 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
14659 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
| 14660 |
std::swap(LD1, LD2); |
0 |
14660 |
std::swap(LD1, LD2); |
0 |
| 14661 |
|
--- |
14661 |
|
--- |
| 14662 |
if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !ISD::isNON_EXTLoad(LD2) || |
0 |
14662 |
if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !ISD::isNON_EXTLoad(LD2) || |
0 |
| 14663 |
!LD1->hasOneUse() || !LD2->hasOneUse() || |
0 |
14663 |
!LD1->hasOneUse() || !LD2->hasOneUse() || |
0 |
| 14664 |
LD1->getAddressSpace() != LD2->getAddressSpace()) |
0 |
14664 |
LD1->getAddressSpace() != LD2->getAddressSpace()) |
0 |
| 14665 |
return SDValue(); |
0 |
14665 |
return SDValue(); |
0 |
| 14666 |
|
--- |
14666 |
|
--- |
| 14667 |
unsigned LD1Fast = 0; |
0 |
14667 |
unsigned LD1Fast = 0; |
0 |
| 14668 |
EVT LD1VT = LD1->getValueType(0); |
0 |
14668 |
EVT LD1VT = LD1->getValueType(0); |
0 |
| 14669 |
unsigned LD1Bytes = LD1VT.getStoreSize(); |
0 |
14669 |
unsigned LD1Bytes = LD1VT.getStoreSize(); |
0 |
| 14670 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) && |
0 |
14670 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) && |
0 |
| 14671 |
DAG.areNonVolatileConsecutiveLoads(LD2, LD1, LD1Bytes, 1) && |
0 |
14671 |
DAG.areNonVolatileConsecutiveLoads(LD2, LD1, LD1Bytes, 1) && |
0 |
| 14672 |
TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, |
0 |
14672 |
TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, |
0 |
| 14673 |
*LD1->getMemOperand(), &LD1Fast) && LD1Fast) |
0 |
14673 |
*LD1->getMemOperand(), &LD1Fast) && LD1Fast) |
0 |
| 14674 |
return DAG.getLoad(VT, SDLoc(N), LD1->getChain(), LD1->getBasePtr(), |
0 |
14674 |
return DAG.getLoad(VT, SDLoc(N), LD1->getChain(), LD1->getBasePtr(), |
0 |
| 14675 |
LD1->getPointerInfo(), LD1->getAlign()); |
0 |
14675 |
LD1->getPointerInfo(), LD1->getAlign()); |
0 |
| 14676 |
|
--- |
14676 |
|
--- |
| 14677 |
return SDValue(); |
0 |
14677 |
return SDValue(); |
0 |
| 14678 |
} |
--- |
14678 |
} |
--- |
| 14679 |
|
--- |
14679 |
|
--- |
| 14680 |
static unsigned getPPCf128HiElementSelector(const SelectionDAG &DAG) { |
0 |
14680 |
static unsigned getPPCf128HiElementSelector(const SelectionDAG &DAG) { |
0 |
| 14681 |
// On little-endian machines, bitcasting from ppcf128 to i128 does swap the Hi |
--- |
14681 |
// On little-endian machines, bitcasting from ppcf128 to i128 does swap the Hi |
--- |
| 14682 |
// and Lo parts; on big-endian machines it doesn't. |
--- |
14682 |
// and Lo parts; on big-endian machines it doesn't. |
--- |
| 14683 |
return DAG.getDataLayout().isBigEndian() ? 1 : 0; |
0 |
14683 |
return DAG.getDataLayout().isBigEndian() ? 1 : 0; |
0 |
| 14684 |
} |
--- |
14684 |
} |
--- |
| 14685 |
|
--- |
14685 |
|
--- |
| 14686 |
SDValue DAGCombiner::foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG, |
0 |
14686 |
SDValue DAGCombiner::foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG, |
0 |
| 14687 |
const TargetLowering &TLI) { |
--- |
14687 |
const TargetLowering &TLI) { |
--- |
| 14688 |
// If this is not a bitcast to an FP type or if the target doesn't have |
--- |
14688 |
// If this is not a bitcast to an FP type or if the target doesn't have |
--- |
| 14689 |
// IEEE754-compliant FP logic, we're done. |
--- |
14689 |
// IEEE754-compliant FP logic, we're done. |
--- |
| 14690 |
EVT VT = N->getValueType(0); |
0 |
14690 |
EVT VT = N->getValueType(0); |
0 |
| 14691 |
SDValue N0 = N->getOperand(0); |
0 |
14691 |
SDValue N0 = N->getOperand(0); |
0 |
| 14692 |
EVT SourceVT = N0.getValueType(); |
0 |
14692 |
EVT SourceVT = N0.getValueType(); |
0 |
| 14693 |
|
--- |
14693 |
|
--- |
| 14694 |
if (!VT.isFloatingPoint()) |
0 |
14694 |
if (!VT.isFloatingPoint()) |
0 |
| 14695 |
return SDValue(); |
0 |
14695 |
return SDValue(); |
0 |
| 14696 |
|
--- |
14696 |
|
--- |
| 14697 |
// TODO: Handle cases where the integer constant is a different scalar |
--- |
14697 |
// TODO: Handle cases where the integer constant is a different scalar |
--- |
| 14698 |
// bitwidth to the FP. |
--- |
14698 |
// bitwidth to the FP. |
--- |
| 14699 |
if (VT.getScalarSizeInBits() != SourceVT.getScalarSizeInBits()) |
0 |
14699 |
if (VT.getScalarSizeInBits() != SourceVT.getScalarSizeInBits()) |
0 |
| 14700 |
return SDValue(); |
0 |
14700 |
return SDValue(); |
0 |
| 14701 |
|
--- |
14701 |
|
--- |
| 14702 |
unsigned FPOpcode; |
--- |
14702 |
unsigned FPOpcode; |
--- |
| 14703 |
APInt SignMask; |
0 |
14703 |
APInt SignMask; |
0 |
| 14704 |
switch (N0.getOpcode()) { |
0 |
14704 |
switch (N0.getOpcode()) { |
0 |
| 14705 |
case ISD::AND: |
0 |
14705 |
case ISD::AND: |
0 |
| 14706 |
FPOpcode = ISD::FABS; |
0 |
14706 |
FPOpcode = ISD::FABS; |
0 |
| 14707 |
SignMask = ~APInt::getSignMask(SourceVT.getScalarSizeInBits()); |
0 |
14707 |
SignMask = ~APInt::getSignMask(SourceVT.getScalarSizeInBits()); |
0 |
| 14708 |
break; |
0 |
14708 |
break; |
0 |
| 14709 |
case ISD::XOR: |
0 |
14709 |
case ISD::XOR: |
0 |
| 14710 |
FPOpcode = ISD::FNEG; |
0 |
14710 |
FPOpcode = ISD::FNEG; |
0 |
| 14711 |
SignMask = APInt::getSignMask(SourceVT.getScalarSizeInBits()); |
0 |
14711 |
SignMask = APInt::getSignMask(SourceVT.getScalarSizeInBits()); |
0 |
| 14712 |
break; |
0 |
14712 |
break; |
0 |
| 14713 |
case ISD::OR: |
0 |
14713 |
case ISD::OR: |
0 |
| 14714 |
FPOpcode = ISD::FABS; |
0 |
14714 |
FPOpcode = ISD::FABS; |
0 |
| 14715 |
SignMask = APInt::getSignMask(SourceVT.getScalarSizeInBits()); |
0 |
14715 |
SignMask = APInt::getSignMask(SourceVT.getScalarSizeInBits()); |
0 |
| 14716 |
break; |
0 |
14716 |
break; |
0 |
| 14717 |
default: |
0 |
14717 |
default: |
0 |
| 14718 |
return SDValue(); |
0 |
14718 |
return SDValue(); |
0 |
| 14719 |
} |
--- |
14719 |
} |
--- |
| 14720 |
|
--- |
14720 |
|
--- |
| 14721 |
if (LegalOperations && !TLI.isOperationLegal(FPOpcode, VT)) |
0 |
14721 |
if (LegalOperations && !TLI.isOperationLegal(FPOpcode, VT)) |
0 |
| 14722 |
return SDValue(); |
0 |
14722 |
return SDValue(); |
0 |
| 14723 |
|
--- |
14723 |
|
--- |
| 14724 |
// This needs to be the inverse of logic in foldSignChangeInBitcast. |
--- |
14724 |
// This needs to be the inverse of logic in foldSignChangeInBitcast. |
--- |
| 14725 |
// FIXME: I don't think looking for bitcast intrinsically makes sense, but |
--- |
14725 |
// FIXME: I don't think looking for bitcast intrinsically makes sense, but |
--- |
| 14726 |
// removing this would require more changes. |
--- |
14726 |
// removing this would require more changes. |
--- |
| 14727 |
auto IsBitCastOrFree = [&TLI, FPOpcode](SDValue Op, EVT VT) { |
0 |
14727 |
auto IsBitCastOrFree = [&TLI, FPOpcode](SDValue Op, EVT VT) { |
0 |
| 14728 |
if (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).getValueType() == VT) |
0 |
14728 |
if (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).getValueType() == VT) |
0 |
| 14729 |
return true; |
0 |
14729 |
return true; |
0 |
| 14730 |
|
--- |
14730 |
|
--- |
| 14731 |
return FPOpcode == ISD::FABS ? TLI.isFAbsFree(VT) : TLI.isFNegFree(VT); |
0 |
14731 |
return FPOpcode == ISD::FABS ? TLI.isFAbsFree(VT) : TLI.isFNegFree(VT); |
0 |
| 14732 |
}; |
0 |
14732 |
}; |
0 |
| 14733 |
|
--- |
14733 |
|
--- |
| 14734 |
// Fold (bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X |
--- |
14734 |
// Fold (bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X |
--- |
| 14735 |
// Fold (bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X |
--- |
14735 |
// Fold (bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X |
--- |
| 14736 |
// Fold (bitcast int (or (bitcast fp X to int), 0x8000...) to fp) -> |
--- |
14736 |
// Fold (bitcast int (or (bitcast fp X to int), 0x8000...) to fp) -> |
--- |
| 14737 |
// fneg (fabs X) |
--- |
14737 |
// fneg (fabs X) |
--- |
| 14738 |
SDValue LogicOp0 = N0.getOperand(0); |
0 |
14738 |
SDValue LogicOp0 = N0.getOperand(0); |
0 |
| 14739 |
ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1), true); |
0 |
14739 |
ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1), true); |
0 |
| 14740 |
if (LogicOp1 && LogicOp1->getAPIntValue() == SignMask && |
0 |
14740 |
if (LogicOp1 && LogicOp1->getAPIntValue() == SignMask && |
0 |
| 14741 |
IsBitCastOrFree(LogicOp0, VT)) { |
0 |
14741 |
IsBitCastOrFree(LogicOp0, VT)) { |
0 |
| 14742 |
SDValue CastOp0 = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, LogicOp0); |
0 |
14742 |
SDValue CastOp0 = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, LogicOp0); |
0 |
| 14743 |
SDValue FPOp = DAG.getNode(FPOpcode, SDLoc(N), VT, CastOp0); |
0 |
14743 |
SDValue FPOp = DAG.getNode(FPOpcode, SDLoc(N), VT, CastOp0); |
0 |
| 14744 |
NumFPLogicOpsConv++; |
0 |
14744 |
NumFPLogicOpsConv++; |
0 |
| 14745 |
if (N0.getOpcode() == ISD::OR) |
0 |
14745 |
if (N0.getOpcode() == ISD::OR) |
0 |
| 14746 |
return DAG.getNode(ISD::FNEG, SDLoc(N), VT, FPOp); |
0 |
14746 |
return DAG.getNode(ISD::FNEG, SDLoc(N), VT, FPOp); |
0 |
| 14747 |
return FPOp; |
0 |
14747 |
return FPOp; |
0 |
| 14748 |
} |
--- |
14748 |
} |
--- |
| 14749 |
|
--- |
14749 |
|
--- |
| 14750 |
return SDValue(); |
0 |
14750 |
return SDValue(); |
0 |
| 14751 |
} |
0 |
14751 |
} |
0 |
| 14752 |
|
--- |
14752 |
|
--- |
| 14753 |
SDValue DAGCombiner::visitBITCAST(SDNode *N) { |
0 |
14753 |
SDValue DAGCombiner::visitBITCAST(SDNode *N) { |
0 |
| 14754 |
SDValue N0 = N->getOperand(0); |
0 |
14754 |
SDValue N0 = N->getOperand(0); |
0 |
| 14755 |
EVT VT = N->getValueType(0); |
0 |
14755 |
EVT VT = N->getValueType(0); |
0 |
| 14756 |
|
--- |
14756 |
|
--- |
| 14757 |
if (N0.isUndef()) |
0 |
14757 |
if (N0.isUndef()) |
0 |
| 14758 |
return DAG.getUNDEF(VT); |
0 |
14758 |
return DAG.getUNDEF(VT); |
0 |
| 14759 |
|
--- |
14759 |
|
--- |
| 14760 |
// If the input is a BUILD_VECTOR with all constant elements, fold this now. |
--- |
14760 |
// If the input is a BUILD_VECTOR with all constant elements, fold this now. |
--- |
| 14761 |
// Only do this before legalize types, unless both types are integer and the |
--- |
14761 |
// Only do this before legalize types, unless both types are integer and the |
--- |
| 14762 |
// scalar type is legal. Only do this before legalize ops, since the target |
--- |
14762 |
// scalar type is legal. Only do this before legalize ops, since the target |
--- |
| 14763 |
// maybe depending on the bitcast. |
--- |
14763 |
// maybe depending on the bitcast. |
--- |
| 14764 |
// First check to see if this is all constant. |
--- |
14764 |
// First check to see if this is all constant. |
--- |
| 14765 |
// TODO: Support FP bitcasts after legalize types. |
--- |
14765 |
// TODO: Support FP bitcasts after legalize types. |
--- |
| 14766 |
if (VT.isVector() && |
0 |
14766 |
if (VT.isVector() && |
0 |
| 14767 |
(!LegalTypes || |
0 |
14767 |
(!LegalTypes || |
0 |
| 14768 |
(!LegalOperations && VT.isInteger() && N0.getValueType().isInteger() && |
0 |
14768 |
(!LegalOperations && VT.isInteger() && N0.getValueType().isInteger() && |
0 |
| 14769 |
TLI.isTypeLegal(VT.getVectorElementType()))) && |
0 |
14769 |
TLI.isTypeLegal(VT.getVectorElementType()))) && |
0 |
| 14770 |
N0.getOpcode() == ISD::BUILD_VECTOR && N0->hasOneUse() && |
0 |
14770 |
N0.getOpcode() == ISD::BUILD_VECTOR && N0->hasOneUse() && |
0 |
| 14771 |
cast(N0)->isConstant()) |
0 |
14771 |
cast(N0)->isConstant()) |
0 |
| 14772 |
return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), |
0 |
14772 |
return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), |
0 |
| 14773 |
VT.getVectorElementType()); |
0 |
14773 |
VT.getVectorElementType()); |
0 |
| 14774 |
|
--- |
14774 |
|
--- |
| 14775 |
// If the input is a constant, let getNode fold it. |
--- |
14775 |
// If the input is a constant, let getNode fold it. |
--- |
| 14776 |
if (isIntOrFPConstant(N0)) { |
0 |
14776 |
if (isIntOrFPConstant(N0)) { |
0 |
| 14777 |
// If we can't allow illegal operations, we need to check that this is just |
--- |
14777 |
// If we can't allow illegal operations, we need to check that this is just |
--- |
| 14778 |
// a fp -> int or int -> conversion and that the resulting operation will |
--- |
14778 |
// a fp -> int or int -> conversion and that the resulting operation will |
--- |
| 14779 |
// be legal. |
--- |
14779 |
// be legal. |
--- |
| 14780 |
if (!LegalOperations || |
0 |
14780 |
if (!LegalOperations || |
0 |
| 14781 |
(isa(N0) && VT.isFloatingPoint() && !VT.isVector() && |
0 |
14781 |
(isa(N0) && VT.isFloatingPoint() && !VT.isVector() && |
0 |
| 14782 |
TLI.isOperationLegal(ISD::ConstantFP, VT)) || |
0 |
14782 |
TLI.isOperationLegal(ISD::ConstantFP, VT)) || |
0 |
| 14783 |
(isa(N0) && VT.isInteger() && !VT.isVector() && |
0 |
14783 |
(isa(N0) && VT.isInteger() && !VT.isVector() && |
0 |
| 14784 |
TLI.isOperationLegal(ISD::Constant, VT))) { |
0 |
14784 |
TLI.isOperationLegal(ISD::Constant, VT))) { |
0 |
| 14785 |
SDValue C = DAG.getBitcast(VT, N0); |
0 |
14785 |
SDValue C = DAG.getBitcast(VT, N0); |
0 |
| 14786 |
if (C.getNode() != N) |
0 |
14786 |
if (C.getNode() != N) |
0 |
| 14787 |
return C; |
0 |
14787 |
return C; |
0 |
| 14788 |
} |
--- |
14788 |
} |
--- |
| 14789 |
} |
--- |
14789 |
} |
--- |
| 14790 |
|
--- |
14790 |
|
--- |
| 14791 |
// (conv (conv x, t1), t2) -> (conv x, t2) |
--- |
14791 |
// (conv (conv x, t1), t2) -> (conv x, t2) |
--- |
| 14792 |
if (N0.getOpcode() == ISD::BITCAST) |
0 |
14792 |
if (N0.getOpcode() == ISD::BITCAST) |
0 |
| 14793 |
return DAG.getBitcast(VT, N0.getOperand(0)); |
0 |
14793 |
return DAG.getBitcast(VT, N0.getOperand(0)); |
0 |
| 14794 |
|
--- |
14794 |
|
--- |
| 14795 |
// fold (conv (logicop (conv x), (c))) -> (logicop x, (conv c)) |
--- |
14795 |
// fold (conv (logicop (conv x), (c))) -> (logicop x, (conv c)) |
--- |
| 14796 |
// iff the current bitwise logicop type isn't legal |
--- |
14796 |
// iff the current bitwise logicop type isn't legal |
--- |
| 14797 |
if (ISD::isBitwiseLogicOp(N0.getOpcode()) && VT.isInteger() && |
0 |
14797 |
if (ISD::isBitwiseLogicOp(N0.getOpcode()) && VT.isInteger() && |
0 |
| 14798 |
!TLI.isTypeLegal(N0.getOperand(0).getValueType())) { |
0 |
14798 |
!TLI.isTypeLegal(N0.getOperand(0).getValueType())) { |
0 |
| 14799 |
auto IsFreeBitcast = [VT](SDValue V) { |
0 |
14799 |
auto IsFreeBitcast = [VT](SDValue V) { |
0 |
| 14800 |
return (V.getOpcode() == ISD::BITCAST && |
0 |
14800 |
return (V.getOpcode() == ISD::BITCAST && |
0 |
| 14801 |
V.getOperand(0).getValueType() == VT) || |
0 |
14801 |
V.getOperand(0).getValueType() == VT) || |
0 |
| 14802 |
(ISD::isBuildVectorOfConstantSDNodes(V.getNode()) && |
0 |
14802 |
(ISD::isBuildVectorOfConstantSDNodes(V.getNode()) && |
0 |
| 14803 |
V->hasOneUse()); |
0 |
14803 |
V->hasOneUse()); |
0 |
| 14804 |
}; |
0 |
14804 |
}; |
0 |
| 14805 |
if (IsFreeBitcast(N0.getOperand(0)) && IsFreeBitcast(N0.getOperand(1))) |
0 |
14805 |
if (IsFreeBitcast(N0.getOperand(0)) && IsFreeBitcast(N0.getOperand(1))) |
0 |
| 14806 |
return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, |
0 |
14806 |
return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, |
0 |
| 14807 |
DAG.getBitcast(VT, N0.getOperand(0)), |
0 |
14807 |
DAG.getBitcast(VT, N0.getOperand(0)), |
0 |
| 14808 |
DAG.getBitcast(VT, N0.getOperand(1))); |
0 |
14808 |
DAG.getBitcast(VT, N0.getOperand(1))); |
0 |
| 14809 |
} |
--- |
14809 |
} |
--- |
| 14810 |
|
--- |
14810 |
|
--- |
| 14811 |
// fold (conv (load x)) -> (load (conv*)x) |
--- |
14811 |
// fold (conv (load x)) -> (load (conv*)x) |
--- |
| 14812 |
// If the resultant load doesn't need a higher alignment than the original! |
--- |
14812 |
// If the resultant load doesn't need a higher alignment than the original! |
--- |
| 14813 |
if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && |
0 |
14813 |
if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && |
0 |
| 14814 |
// Do not remove the cast if the types differ in endian layout. |
--- |
14814 |
// Do not remove the cast if the types differ in endian layout. |
--- |
| 14815 |
TLI.hasBigEndianPartOrdering(N0.getValueType(), DAG.getDataLayout()) == |
0 |
14815 |
TLI.hasBigEndianPartOrdering(N0.getValueType(), DAG.getDataLayout()) == |
0 |
| 14816 |
TLI.hasBigEndianPartOrdering(VT, DAG.getDataLayout()) && |
0 |
14816 |
TLI.hasBigEndianPartOrdering(VT, DAG.getDataLayout()) && |
0 |
| 14817 |
// If the load is volatile, we only want to change the load type if the |
--- |
14817 |
// If the load is volatile, we only want to change the load type if the |
--- |
| 14818 |
// resulting load is legal. Otherwise we might increase the number of |
--- |
14818 |
// resulting load is legal. Otherwise we might increase the number of |
--- |
| 14819 |
// memory accesses. We don't care if the original type was legal or not |
--- |
14819 |
// memory accesses. We don't care if the original type was legal or not |
--- |
| 14820 |
// as we assume software couldn't rely on the number of accesses of an |
--- |
14820 |
// as we assume software couldn't rely on the number of accesses of an |
--- |
| 14821 |
// illegal type. |
--- |
14821 |
// illegal type. |
--- |
| 14822 |
((!LegalOperations && cast(N0)->isSimple()) || |
0 |
14822 |
((!LegalOperations && cast(N0)->isSimple()) || |
0 |
| 14823 |
TLI.isOperationLegal(ISD::LOAD, VT))) { |
0 |
14823 |
TLI.isOperationLegal(ISD::LOAD, VT))) { |
0 |
| 14824 |
LoadSDNode *LN0 = cast(N0); |
0 |
14824 |
LoadSDNode *LN0 = cast(N0); |
0 |
| 14825 |
|
--- |
14825 |
|
--- |
| 14826 |
if (TLI.isLoadBitCastBeneficial(N0.getValueType(), VT, DAG, |
0 |
14826 |
if (TLI.isLoadBitCastBeneficial(N0.getValueType(), VT, DAG, |
0 |
| 14827 |
*LN0->getMemOperand())) { |
0 |
14827 |
*LN0->getMemOperand())) { |
0 |
| 14828 |
SDValue Load = |
--- |
14828 |
SDValue Load = |
--- |
| 14829 |
DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(), |
0 |
14829 |
DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(), |
0 |
| 14830 |
LN0->getPointerInfo(), LN0->getAlign(), |
0 |
14830 |
LN0->getPointerInfo(), LN0->getAlign(), |
0 |
| 14831 |
LN0->getMemOperand()->getFlags(), LN0->getAAInfo()); |
0 |
14831 |
LN0->getMemOperand()->getFlags(), LN0->getAAInfo()); |
0 |
| 14832 |
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); |
0 |
14832 |
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); |
0 |
| 14833 |
return Load; |
0 |
14833 |
return Load; |
0 |
| 14834 |
} |
--- |
14834 |
} |
--- |
| 14835 |
} |
--- |
14835 |
} |
--- |
| 14836 |
|
--- |
14836 |
|
--- |
| 14837 |
if (SDValue V = foldBitcastedFPLogic(N, DAG, TLI)) |
0 |
14837 |
if (SDValue V = foldBitcastedFPLogic(N, DAG, TLI)) |
0 |
| 14838 |
return V; |
0 |
14838 |
return V; |
0 |
| 14839 |
|
--- |
14839 |
|
--- |
| 14840 |
// fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) |
--- |
14840 |
// fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) |
--- |
| 14841 |
// fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) |
--- |
14841 |
// fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) |
--- |
| 14842 |
// |
--- |
14842 |
// |
--- |
| 14843 |
// For ppc_fp128: |
--- |
14843 |
// For ppc_fp128: |
--- |
| 14844 |
// fold (bitcast (fneg x)) -> |
--- |
14844 |
// fold (bitcast (fneg x)) -> |
--- |
| 14845 |
// flipbit = signbit |
--- |
14845 |
// flipbit = signbit |
--- |
| 14846 |
// (xor (bitcast x) (build_pair flipbit, flipbit)) |
--- |
14846 |
// (xor (bitcast x) (build_pair flipbit, flipbit)) |
--- |
| 14847 |
// |
--- |
14847 |
// |
--- |
| 14848 |
// fold (bitcast (fabs x)) -> |
--- |
14848 |
// fold (bitcast (fabs x)) -> |
--- |
| 14849 |
// flipbit = (and (extract_element (bitcast x), 0), signbit) |
--- |
14849 |
// flipbit = (and (extract_element (bitcast x), 0), signbit) |
--- |
| 14850 |
// (xor (bitcast x) (build_pair flipbit, flipbit)) |
--- |
14850 |
// (xor (bitcast x) (build_pair flipbit, flipbit)) |
--- |
| 14851 |
// This often reduces constant pool loads. |
--- |
14851 |
// This often reduces constant pool loads. |
--- |
| 14852 |
if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || |
0 |
14852 |
if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || |
0 |
| 14853 |
(N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && |
0 |
14853 |
(N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && |
0 |
| 14854 |
N0->hasOneUse() && VT.isInteger() && !VT.isVector() && |
0 |
14854 |
N0->hasOneUse() && VT.isInteger() && !VT.isVector() && |
0 |
| 14855 |
!N0.getValueType().isVector()) { |
0 |
14855 |
!N0.getValueType().isVector()) { |
0 |
| 14856 |
SDValue NewConv = DAG.getBitcast(VT, N0.getOperand(0)); |
0 |
14856 |
SDValue NewConv = DAG.getBitcast(VT, N0.getOperand(0)); |
0 |
| 14857 |
AddToWorklist(NewConv.getNode()); |
0 |
14857 |
AddToWorklist(NewConv.getNode()); |
0 |
| 14858 |
|
--- |
14858 |
|
--- |
| 14859 |
SDLoc DL(N); |
0 |
14859 |
SDLoc DL(N); |
0 |
| 14860 |
if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) { |
0 |
14860 |
if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) { |
0 |
| 14861 |
assert(VT.getSizeInBits() == 128); |
0 |
14861 |
assert(VT.getSizeInBits() == 128); |
0 |
| 14862 |
SDValue SignBit = DAG.getConstant( |
0 |
14862 |
SDValue SignBit = DAG.getConstant( |
0 |
| 14863 |
APInt::getSignMask(VT.getSizeInBits() / 2), SDLoc(N0), MVT::i64); |
0 |
14863 |
APInt::getSignMask(VT.getSizeInBits() / 2), SDLoc(N0), MVT::i64); |
0 |
| 14864 |
SDValue FlipBit; |
0 |
14864 |
SDValue FlipBit; |
0 |
| 14865 |
if (N0.getOpcode() == ISD::FNEG) { |
0 |
14865 |
if (N0.getOpcode() == ISD::FNEG) { |
0 |
| 14866 |
FlipBit = SignBit; |
0 |
14866 |
FlipBit = SignBit; |
0 |
| 14867 |
AddToWorklist(FlipBit.getNode()); |
0 |
14867 |
AddToWorklist(FlipBit.getNode()); |
0 |
| 14868 |
} else { |
--- |
14868 |
} else { |
--- |
| 14869 |
assert(N0.getOpcode() == ISD::FABS); |
0 |
14869 |
assert(N0.getOpcode() == ISD::FABS); |
0 |
| 14870 |
SDValue Hi = |
--- |
14870 |
SDValue Hi = |
--- |
| 14871 |
DAG.getNode(ISD::EXTRACT_ELEMENT, SDLoc(NewConv), MVT::i64, NewConv, |
0 |
14871 |
DAG.getNode(ISD::EXTRACT_ELEMENT, SDLoc(NewConv), MVT::i64, NewConv, |
0 |
| 14872 |
DAG.getIntPtrConstant(getPPCf128HiElementSelector(DAG), |
0 |
14872 |
DAG.getIntPtrConstant(getPPCf128HiElementSelector(DAG), |
0 |
| 14873 |
SDLoc(NewConv))); |
0 |
14873 |
SDLoc(NewConv))); |
0 |
| 14874 |
AddToWorklist(Hi.getNode()); |
0 |
14874 |
AddToWorklist(Hi.getNode()); |
0 |
| 14875 |
FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit); |
0 |
14875 |
FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit); |
0 |
| 14876 |
AddToWorklist(FlipBit.getNode()); |
0 |
14876 |
AddToWorklist(FlipBit.getNode()); |
0 |
| 14877 |
} |
--- |
14877 |
} |
--- |
| 14878 |
SDValue FlipBits = |
--- |
14878 |
SDValue FlipBits = |
--- |
| 14879 |
DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); |
0 |
14879 |
DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); |
0 |
| 14880 |
AddToWorklist(FlipBits.getNode()); |
0 |
14880 |
AddToWorklist(FlipBits.getNode()); |
0 |
| 14881 |
return DAG.getNode(ISD::XOR, DL, VT, NewConv, FlipBits); |
0 |
14881 |
return DAG.getNode(ISD::XOR, DL, VT, NewConv, FlipBits); |
0 |
| 14882 |
} |
--- |
14882 |
} |
--- |
| 14883 |
APInt SignBit = APInt::getSignMask(VT.getSizeInBits()); |
0 |
14883 |
APInt SignBit = APInt::getSignMask(VT.getSizeInBits()); |
0 |
| 14884 |
if (N0.getOpcode() == ISD::FNEG) |
0 |
14884 |
if (N0.getOpcode() == ISD::FNEG) |
0 |
| 14885 |
return DAG.getNode(ISD::XOR, DL, VT, |
0 |
14885 |
return DAG.getNode(ISD::XOR, DL, VT, |
0 |
| 14886 |
NewConv, DAG.getConstant(SignBit, DL, VT)); |
0 |
14886 |
NewConv, DAG.getConstant(SignBit, DL, VT)); |
0 |
| 14887 |
assert(N0.getOpcode() == ISD::FABS); |
0 |
14887 |
assert(N0.getOpcode() == ISD::FABS); |
0 |
| 14888 |
return DAG.getNode(ISD::AND, DL, VT, |
0 |
14888 |
return DAG.getNode(ISD::AND, DL, VT, |
0 |
| 14889 |
NewConv, DAG.getConstant(~SignBit, DL, VT)); |
0 |
14889 |
NewConv, DAG.getConstant(~SignBit, DL, VT)); |
0 |
| 14890 |
} |
0 |
14890 |
} |
0 |
| 14891 |
|
--- |
14891 |
|
--- |
| 14892 |
// fold (bitconvert (fcopysign cst, x)) -> |
--- |
14892 |
// fold (bitconvert (fcopysign cst, x)) -> |
--- |
| 14893 |
// (or (and (bitconvert x), sign), (and cst, (not sign))) |
--- |
14893 |
// (or (and (bitconvert x), sign), (and cst, (not sign))) |
--- |
| 14894 |
// Note that we don't handle (copysign x, cst) because this can always be |
--- |
14894 |
// Note that we don't handle (copysign x, cst) because this can always be |
--- |
| 14895 |
// folded to an fneg or fabs. |
--- |
14895 |
// folded to an fneg or fabs. |
--- |
| 14896 |
// |
--- |
14896 |
// |
--- |
| 14897 |
// For ppc_fp128: |
--- |
14897 |
// For ppc_fp128: |
--- |
| 14898 |
// fold (bitcast (fcopysign cst, x)) -> |
--- |
14898 |
// fold (bitcast (fcopysign cst, x)) -> |
--- |
| 14899 |
// flipbit = (and (extract_element |
--- |
14899 |
// flipbit = (and (extract_element |
--- |
| 14900 |
// (xor (bitcast cst), (bitcast x)), 0), |
--- |
14900 |
// (xor (bitcast cst), (bitcast x)), 0), |
--- |
| 14901 |
// signbit) |
--- |
14901 |
// signbit) |
--- |
| 14902 |
// (xor (bitcast cst) (build_pair flipbit, flipbit)) |
--- |
14902 |
// (xor (bitcast cst) (build_pair flipbit, flipbit)) |
--- |
| 14903 |
if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() && |
0 |
14903 |
if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() && |
0 |
| 14904 |
isa(N0.getOperand(0)) && VT.isInteger() && |
0 |
14904 |
isa(N0.getOperand(0)) && VT.isInteger() && |
0 |
| 14905 |
!VT.isVector()) { |
0 |
14905 |
!VT.isVector()) { |
0 |
| 14906 |
unsigned OrigXWidth = N0.getOperand(1).getValueSizeInBits(); |
0 |
14906 |
unsigned OrigXWidth = N0.getOperand(1).getValueSizeInBits(); |
0 |
| 14907 |
EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); |
0 |
14907 |
EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); |
0 |
| 14908 |
if (isTypeLegal(IntXVT)) { |
0 |
14908 |
if (isTypeLegal(IntXVT)) { |
0 |
| 14909 |
SDValue X = DAG.getBitcast(IntXVT, N0.getOperand(1)); |
0 |
14909 |
SDValue X = DAG.getBitcast(IntXVT, N0.getOperand(1)); |
0 |
| 14910 |
AddToWorklist(X.getNode()); |
0 |
14910 |
AddToWorklist(X.getNode()); |
0 |
| 14911 |
|
--- |
14911 |
|
--- |
| 14912 |
// If X has a different width than the result/lhs, sext it or truncate it. |
--- |
14912 |
// If X has a different width than the result/lhs, sext it or truncate it. |
--- |
| 14913 |
unsigned VTWidth = VT.getSizeInBits(); |
0 |
14913 |
unsigned VTWidth = VT.getSizeInBits(); |
0 |
| 14914 |
if (OrigXWidth < VTWidth) { |
0 |
14914 |
if (OrigXWidth < VTWidth) { |
0 |
| 14915 |
X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X); |
0 |
14915 |
X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X); |
0 |
| 14916 |
AddToWorklist(X.getNode()); |
0 |
14916 |
AddToWorklist(X.getNode()); |
0 |
| 14917 |
} else if (OrigXWidth > VTWidth) { |
0 |
14917 |
} else if (OrigXWidth > VTWidth) { |
0 |
| 14918 |
// To get the sign bit in the right place, we have to shift it right |
--- |
14918 |
// To get the sign bit in the right place, we have to shift it right |
--- |
| 14919 |
// before truncating. |
--- |
14919 |
// before truncating. |
--- |
| 14920 |
SDLoc DL(X); |
0 |
14920 |
SDLoc DL(X); |
0 |
| 14921 |
X = DAG.getNode(ISD::SRL, DL, |
0 |
14921 |
X = DAG.getNode(ISD::SRL, DL, |
0 |
| 14922 |
X.getValueType(), X, |
--- |
14922 |
X.getValueType(), X, |
--- |
| 14923 |
DAG.getConstant(OrigXWidth-VTWidth, DL, |
0 |
14923 |
DAG.getConstant(OrigXWidth-VTWidth, DL, |
0 |
| 14924 |
X.getValueType())); |
--- |
14924 |
X.getValueType())); |
--- |
| 14925 |
AddToWorklist(X.getNode()); |
0 |
14925 |
AddToWorklist(X.getNode()); |
0 |
| 14926 |
X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X); |
0 |
14926 |
X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X); |
0 |
| 14927 |
AddToWorklist(X.getNode()); |
0 |
14927 |
AddToWorklist(X.getNode()); |
0 |
| 14928 |
} |
0 |
14928 |
} |
0 |
| 14929 |
|
--- |
14929 |
|
--- |
| 14930 |
if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) { |
0 |
14930 |
if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) { |
0 |
| 14931 |
APInt SignBit = APInt::getSignMask(VT.getSizeInBits() / 2); |
0 |
14931 |
APInt SignBit = APInt::getSignMask(VT.getSizeInBits() / 2); |
0 |
| 14932 |
SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0)); |
0 |
14932 |
SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0)); |
0 |
| 14933 |
AddToWorklist(Cst.getNode()); |
0 |
14933 |
AddToWorklist(Cst.getNode()); |
0 |
| 14934 |
SDValue X = DAG.getBitcast(VT, N0.getOperand(1)); |
0 |
14934 |
SDValue X = DAG.getBitcast(VT, N0.getOperand(1)); |
0 |
| 14935 |
AddToWorklist(X.getNode()); |
0 |
14935 |
AddToWorklist(X.getNode()); |
0 |
| 14936 |
SDValue XorResult = DAG.getNode(ISD::XOR, SDLoc(N0), VT, Cst, X); |
0 |
14936 |
SDValue XorResult = DAG.getNode(ISD::XOR, SDLoc(N0), VT, Cst, X); |
0 |
| 14937 |
AddToWorklist(XorResult.getNode()); |
0 |
14937 |
AddToWorklist(XorResult.getNode()); |
0 |
| 14938 |
SDValue XorResult64 = DAG.getNode( |
0 |
14938 |
SDValue XorResult64 = DAG.getNode( |
0 |
| 14939 |
ISD::EXTRACT_ELEMENT, SDLoc(XorResult), MVT::i64, XorResult, |
0 |
14939 |
ISD::EXTRACT_ELEMENT, SDLoc(XorResult), MVT::i64, XorResult, |
0 |
| 14940 |
DAG.getIntPtrConstant(getPPCf128HiElementSelector(DAG), |
0 |
14940 |
DAG.getIntPtrConstant(getPPCf128HiElementSelector(DAG), |
0 |
| 14941 |
SDLoc(XorResult))); |
0 |
14941 |
SDLoc(XorResult))); |
0 |
| 14942 |
AddToWorklist(XorResult64.getNode()); |
0 |
14942 |
AddToWorklist(XorResult64.getNode()); |
0 |
| 14943 |
SDValue FlipBit = |
--- |
14943 |
SDValue FlipBit = |
--- |
| 14944 |
DAG.getNode(ISD::AND, SDLoc(XorResult64), MVT::i64, XorResult64, |
0 |
14944 |
DAG.getNode(ISD::AND, SDLoc(XorResult64), MVT::i64, XorResult64, |
0 |
| 14945 |
DAG.getConstant(SignBit, SDLoc(XorResult64), MVT::i64)); |
0 |
14945 |
DAG.getConstant(SignBit, SDLoc(XorResult64), MVT::i64)); |
0 |
| 14946 |
AddToWorklist(FlipBit.getNode()); |
0 |
14946 |
AddToWorklist(FlipBit.getNode()); |
0 |
| 14947 |
SDValue FlipBits = |
--- |
14947 |
SDValue FlipBits = |
--- |
| 14948 |
DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); |
0 |
14948 |
DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); |
0 |
| 14949 |
AddToWorklist(FlipBits.getNode()); |
0 |
14949 |
AddToWorklist(FlipBits.getNode()); |
0 |
| 14950 |
return DAG.getNode(ISD::XOR, SDLoc(N), VT, Cst, FlipBits); |
0 |
14950 |
return DAG.getNode(ISD::XOR, SDLoc(N), VT, Cst, FlipBits); |
0 |
| 14951 |
} |
0 |
14951 |
} |
0 |
| 14952 |
APInt SignBit = APInt::getSignMask(VT.getSizeInBits()); |
0 |
14952 |
APInt SignBit = APInt::getSignMask(VT.getSizeInBits()); |
0 |
| 14953 |
X = DAG.getNode(ISD::AND, SDLoc(X), VT, |
0 |
14953 |
X = DAG.getNode(ISD::AND, SDLoc(X), VT, |
0 |
| 14954 |
X, DAG.getConstant(SignBit, SDLoc(X), VT)); |
0 |
14954 |
X, DAG.getConstant(SignBit, SDLoc(X), VT)); |
0 |
| 14955 |
AddToWorklist(X.getNode()); |
0 |
14955 |
AddToWorklist(X.getNode()); |
0 |
| 14956 |
|
--- |
14956 |
|
--- |
| 14957 |
SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0)); |
0 |
14957 |
SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0)); |
0 |
| 14958 |
Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT, |
0 |
14958 |
Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT, |
0 |
| 14959 |
Cst, DAG.getConstant(~SignBit, SDLoc(Cst), VT)); |
0 |
14959 |
Cst, DAG.getConstant(~SignBit, SDLoc(Cst), VT)); |
0 |
| 14960 |
AddToWorklist(Cst.getNode()); |
0 |
14960 |
AddToWorklist(Cst.getNode()); |
0 |
| 14961 |
|
--- |
14961 |
|
--- |
| 14962 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst); |
0 |
14962 |
return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst); |
0 |
| 14963 |
} |
0 |
14963 |
} |
0 |
| 14964 |
} |
--- |
14964 |
} |
--- |
| 14965 |
|
--- |
14965 |
|
--- |
| 14966 |
// bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. |
--- |
14966 |
// bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. |
--- |
| 14967 |
if (N0.getOpcode() == ISD::BUILD_PAIR) |
0 |
14967 |
if (N0.getOpcode() == ISD::BUILD_PAIR) |
0 |
| 14968 |
if (SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT)) |
0 |
14968 |
if (SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT)) |
0 |
| 14969 |
return CombineLD; |
0 |
14969 |
return CombineLD; |
0 |
| 14970 |
|
--- |
14970 |
|
--- |
| 14971 |
// Remove double bitcasts from shuffles - this is often a legacy of |
--- |
14971 |
// Remove double bitcasts from shuffles - this is often a legacy of |
--- |
| 14972 |
// XformToShuffleWithZero being used to combine bitmaskings (of |
--- |
14972 |
// XformToShuffleWithZero being used to combine bitmaskings (of |
--- |
| 14973 |
// float vectors bitcast to integer vectors) into shuffles. |
--- |
14973 |
// float vectors bitcast to integer vectors) into shuffles. |
--- |
| 14974 |
// bitcast(shuffle(bitcast(s0),bitcast(s1))) -> shuffle(s0,s1) |
--- |
14974 |
// bitcast(shuffle(bitcast(s0),bitcast(s1))) -> shuffle(s0,s1) |
--- |
| 14975 |
if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT) && VT.isVector() && |
0 |
14975 |
if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT) && VT.isVector() && |
0 |
| 14976 |
N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && |
0 |
14976 |
N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && |
0 |
| 14977 |
VT.getVectorNumElements() >= N0.getValueType().getVectorNumElements() && |
0 |
14977 |
VT.getVectorNumElements() >= N0.getValueType().getVectorNumElements() && |
0 |
| 14978 |
!(VT.getVectorNumElements() % N0.getValueType().getVectorNumElements())) { |
0 |
14978 |
!(VT.getVectorNumElements() % N0.getValueType().getVectorNumElements())) { |
0 |
| 14979 |
ShuffleVectorSDNode *SVN = cast(N0); |
0 |
14979 |
ShuffleVectorSDNode *SVN = cast(N0); |
0 |
| 14980 |
|
--- |
14980 |
|
--- |
| 14981 |
// If operands are a bitcast, peek through if it casts the original VT. |
--- |
14981 |
// If operands are a bitcast, peek through if it casts the original VT. |
--- |
| 14982 |
// If operands are a constant, just bitcast back to original VT. |
--- |
14982 |
// If operands are a constant, just bitcast back to original VT. |
--- |
| 14983 |
auto PeekThroughBitcast = [&](SDValue Op) { |
0 |
14983 |
auto PeekThroughBitcast = [&](SDValue Op) { |
0 |
| 14984 |
if (Op.getOpcode() == ISD::BITCAST && |
0 |
14984 |
if (Op.getOpcode() == ISD::BITCAST && |
0 |
| 14985 |
Op.getOperand(0).getValueType() == VT) |
0 |
14985 |
Op.getOperand(0).getValueType() == VT) |
0 |
| 14986 |
return SDValue(Op.getOperand(0)); |
0 |
14986 |
return SDValue(Op.getOperand(0)); |
0 |
| 14987 |
if (Op.isUndef() || isAnyConstantBuildVector(Op)) |
0 |
14987 |
if (Op.isUndef() || isAnyConstantBuildVector(Op)) |
0 |
| 14988 |
return DAG.getBitcast(VT, Op); |
0 |
14988 |
return DAG.getBitcast(VT, Op); |
0 |
| 14989 |
return SDValue(); |
0 |
14989 |
return SDValue(); |
0 |
| 14990 |
}; |
0 |
14990 |
}; |
0 |
| 14991 |
|
--- |
14991 |
|
--- |
| 14992 |
// FIXME: If either input vector is bitcast, try to convert the shuffle to |
--- |
14992 |
// FIXME: If either input vector is bitcast, try to convert the shuffle to |
--- |
| 14993 |
// the result type of this bitcast. This would eliminate at least one |
--- |
14993 |
// the result type of this bitcast. This would eliminate at least one |
--- |
| 14994 |
// bitcast. See the transform in InstCombine. |
--- |
14994 |
// bitcast. See the transform in InstCombine. |
--- |
| 14995 |
SDValue SV0 = PeekThroughBitcast(N0->getOperand(0)); |
0 |
14995 |
SDValue SV0 = PeekThroughBitcast(N0->getOperand(0)); |
0 |
| 14996 |
SDValue SV1 = PeekThroughBitcast(N0->getOperand(1)); |
0 |
14996 |
SDValue SV1 = PeekThroughBitcast(N0->getOperand(1)); |
0 |
| 14997 |
if (!(SV0 && SV1)) |
0 |
14997 |
if (!(SV0 && SV1)) |
0 |
| 14998 |
return SDValue(); |
0 |
14998 |
return SDValue(); |
0 |
| 14999 |
|
--- |
14999 |
|
--- |
| 15000 |
int MaskScale = |
--- |
15000 |
int MaskScale = |
--- |
| 15001 |
VT.getVectorNumElements() / N0.getValueType().getVectorNumElements(); |
0 |
15001 |
VT.getVectorNumElements() / N0.getValueType().getVectorNumElements(); |
0 |
| 15002 |
SmallVector NewMask; |
0 |
15002 |
SmallVector NewMask; |
0 |
| 15003 |
for (int M : SVN->getMask()) |
0 |
15003 |
for (int M : SVN->getMask()) |
0 |
| 15004 |
for (int i = 0; i != MaskScale; ++i) |
0 |
15004 |
for (int i = 0; i != MaskScale; ++i) |
0 |
| 15005 |
NewMask.push_back(M < 0 ? -1 : M * MaskScale + i); |
0 |
15005 |
NewMask.push_back(M < 0 ? -1 : M * MaskScale + i); |
0 |
| 15006 |
|
--- |
15006 |
|
--- |
| 15007 |
SDValue LegalShuffle = |
--- |
15007 |
SDValue LegalShuffle = |
--- |
| 15008 |
TLI.buildLegalVectorShuffle(VT, SDLoc(N), SV0, SV1, NewMask, DAG); |
0 |
15008 |
TLI.buildLegalVectorShuffle(VT, SDLoc(N), SV0, SV1, NewMask, DAG); |
0 |
| 15009 |
if (LegalShuffle) |
0 |
15009 |
if (LegalShuffle) |
0 |
| 15010 |
return LegalShuffle; |
0 |
15010 |
return LegalShuffle; |
0 |
| 15011 |
} |
0 |
15011 |
} |
0 |
| 15012 |
|
--- |
15012 |
|
--- |
| 15013 |
return SDValue(); |
0 |
15013 |
return SDValue(); |
0 |
| 15014 |
} |
--- |
15014 |
} |
--- |
| 15015 |
|
--- |
15015 |
|
--- |
| 15016 |
SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { |
0 |
15016 |
SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { |
0 |
| 15017 |
EVT VT = N->getValueType(0); |
0 |
15017 |
EVT VT = N->getValueType(0); |
0 |
| 15018 |
return CombineConsecutiveLoads(N, VT); |
0 |
15018 |
return CombineConsecutiveLoads(N, VT); |
0 |
| 15019 |
} |
--- |
15019 |
} |
--- |
| 15020 |
|
--- |
15020 |
|
--- |
| 15021 |
SDValue DAGCombiner::visitFREEZE(SDNode *N) { |
0 |
15021 |
SDValue DAGCombiner::visitFREEZE(SDNode *N) { |
0 |
| 15022 |
SDValue N0 = N->getOperand(0); |
0 |
15022 |
SDValue N0 = N->getOperand(0); |
0 |
| 15023 |
|
--- |
15023 |
|
--- |
| 15024 |
if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, /*PoisonOnly*/ false)) |
0 |
15024 |
if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, /*PoisonOnly*/ false)) |
0 |
| 15025 |
return N0; |
0 |
15025 |
return N0; |
0 |
| 15026 |
|
--- |
15026 |
|
--- |
| 15027 |
// Fold freeze(op(x, ...)) -> op(freeze(x), ...). |
--- |
15027 |
// Fold freeze(op(x, ...)) -> op(freeze(x), ...). |
--- |
| 15028 |
// Try to push freeze through instructions that propagate but don't produce |
--- |
15028 |
// Try to push freeze through instructions that propagate but don't produce |
--- |
| 15029 |
// poison as far as possible. If an operand of freeze follows three |
--- |
15029 |
// poison as far as possible. If an operand of freeze follows three |
--- |
| 15030 |
// conditions 1) one-use, 2) does not produce poison, and 3) has all but one |
--- |
15030 |
// conditions 1) one-use, 2) does not produce poison, and 3) has all but one |
--- |
| 15031 |
// guaranteed-non-poison operands (or is a BUILD_VECTOR or similar) then push |
--- |
15031 |
// guaranteed-non-poison operands (or is a BUILD_VECTOR or similar) then push |
--- |
| 15032 |
// the freeze through to the operands that are not guaranteed non-poison. |
--- |
15032 |
// the freeze through to the operands that are not guaranteed non-poison. |
--- |
| 15033 |
// NOTE: we will strip poison-generating flags, so ignore them here. |
--- |
15033 |
// NOTE: we will strip poison-generating flags, so ignore them here. |
--- |
| 15034 |
if (DAG.canCreateUndefOrPoison(N0, /*PoisonOnly*/ false, |
0 |
15034 |
if (DAG.canCreateUndefOrPoison(N0, /*PoisonOnly*/ false, |
0 |
| 15035 |
/*ConsiderFlags*/ false) || |
0 |
15035 |
/*ConsiderFlags*/ false) || |
0 |
| 15036 |
N0->getNumValues() != 1 || !N0->hasOneUse()) |
0 |
15036 |
N0->getNumValues() != 1 || !N0->hasOneUse()) |
0 |
| 15037 |
return SDValue(); |
0 |
15037 |
return SDValue(); |
0 |
| 15038 |
|
--- |
15038 |
|
--- |
| 15039 |
bool AllowMultipleMaybePoisonOperands = N0.getOpcode() == ISD::BUILD_VECTOR || |
0 |
15039 |
bool AllowMultipleMaybePoisonOperands = N0.getOpcode() == ISD::BUILD_VECTOR || |
0 |
| 15040 |
N0.getOpcode() == ISD::BUILD_PAIR || |
0 |
15040 |
N0.getOpcode() == ISD::BUILD_PAIR || |
0 |
| 15041 |
N0.getOpcode() == ISD::CONCAT_VECTORS; |
0 |
15041 |
N0.getOpcode() == ISD::CONCAT_VECTORS; |
0 |
| 15042 |
|
--- |
15042 |
|
--- |
| 15043 |
SmallSetVector MaybePoisonOperands; |
0 |
15043 |
SmallSetVector MaybePoisonOperands; |
0 |
| 15044 |
for (SDValue Op : N0->ops()) { |
0 |
15044 |
for (SDValue Op : N0->ops()) { |
0 |
| 15045 |
if (DAG.isGuaranteedNotToBeUndefOrPoison(Op, /*PoisonOnly*/ false, |
0 |
15045 |
if (DAG.isGuaranteedNotToBeUndefOrPoison(Op, /*PoisonOnly*/ false, |
0 |
| 15046 |
/*Depth*/ 1)) |
--- |
15046 |
/*Depth*/ 1)) |
--- |
| 15047 |
continue; |
0 |
15047 |
continue; |
0 |
| 15048 |
bool HadMaybePoisonOperands = !MaybePoisonOperands.empty(); |
0 |
15048 |
bool HadMaybePoisonOperands = !MaybePoisonOperands.empty(); |
0 |
| 15049 |
bool IsNewMaybePoisonOperand = MaybePoisonOperands.insert(Op); |
0 |
15049 |
bool IsNewMaybePoisonOperand = MaybePoisonOperands.insert(Op); |
0 |
| 15050 |
if (!HadMaybePoisonOperands) |
0 |
15050 |
if (!HadMaybePoisonOperands) |
0 |
| 15051 |
continue; |
0 |
15051 |
continue; |
0 |
| 15052 |
if (IsNewMaybePoisonOperand && !AllowMultipleMaybePoisonOperands) { |
0 |
15052 |
if (IsNewMaybePoisonOperand && !AllowMultipleMaybePoisonOperands) { |
0 |
| 15053 |
// Multiple maybe-poison ops when not allowed - bail out. |
--- |
15053 |
// Multiple maybe-poison ops when not allowed - bail out. |
--- |
| 15054 |
return SDValue(); |
0 |
15054 |
return SDValue(); |
0 |
| 15055 |
} |
--- |
15055 |
} |
--- |
| 15056 |
} |
--- |
15056 |
} |
--- |
| 15057 |
// NOTE: the whole op may be not guaranteed to not be undef or poison because |
--- |
15057 |
// NOTE: the whole op may be not guaranteed to not be undef or poison because |
--- |
| 15058 |
// it could create undef or poison due to it's poison-generating flags. |
--- |
15058 |
// it could create undef or poison due to it's poison-generating flags. |
--- |
| 15059 |
// So not finding any maybe-poison operands is fine. |
--- |
15059 |
// So not finding any maybe-poison operands is fine. |
--- |
| 15060 |
|
--- |
15060 |
|
--- |
| 15061 |
for (SDValue MaybePoisonOperand : MaybePoisonOperands) { |
0 |
15061 |
for (SDValue MaybePoisonOperand : MaybePoisonOperands) { |
0 |
| 15062 |
// Don't replace every single UNDEF everywhere with frozen UNDEF, though. |
--- |
15062 |
// Don't replace every single UNDEF everywhere with frozen UNDEF, though. |
--- |
| 15063 |
if (MaybePoisonOperand.getOpcode() == ISD::UNDEF) |
0 |
15063 |
if (MaybePoisonOperand.getOpcode() == ISD::UNDEF) |
0 |
| 15064 |
continue; |
0 |
15064 |
continue; |
0 |
| 15065 |
// First, freeze each offending operand. |
--- |
15065 |
// First, freeze each offending operand. |
--- |
| 15066 |
SDValue FrozenMaybePoisonOperand = DAG.getFreeze(MaybePoisonOperand); |
0 |
15066 |
SDValue FrozenMaybePoisonOperand = DAG.getFreeze(MaybePoisonOperand); |
0 |
| 15067 |
// Then, change all other uses of unfrozen operand to use frozen operand. |
--- |
15067 |
// Then, change all other uses of unfrozen operand to use frozen operand. |
--- |
| 15068 |
DAG.ReplaceAllUsesOfValueWith(MaybePoisonOperand, FrozenMaybePoisonOperand); |
0 |
15068 |
DAG.ReplaceAllUsesOfValueWith(MaybePoisonOperand, FrozenMaybePoisonOperand); |
0 |
| 15069 |
if (FrozenMaybePoisonOperand.getOpcode() == ISD::FREEZE && |
0 |
15069 |
if (FrozenMaybePoisonOperand.getOpcode() == ISD::FREEZE && |
0 |
| 15070 |
FrozenMaybePoisonOperand.getOperand(0) == FrozenMaybePoisonOperand) { |
0 |
15070 |
FrozenMaybePoisonOperand.getOperand(0) == FrozenMaybePoisonOperand) { |
0 |
| 15071 |
// But, that also updated the use in the freeze we just created, thus |
--- |
15071 |
// But, that also updated the use in the freeze we just created, thus |
--- |
| 15072 |
// creating a cycle in a DAG. Let's undo that by mutating the freeze. |
--- |
15072 |
// creating a cycle in a DAG. Let's undo that by mutating the freeze. |
--- |
| 15073 |
DAG.UpdateNodeOperands(FrozenMaybePoisonOperand.getNode(), |
0 |
15073 |
DAG.UpdateNodeOperands(FrozenMaybePoisonOperand.getNode(), |
0 |
| 15074 |
MaybePoisonOperand); |
--- |
15074 |
MaybePoisonOperand); |
--- |
| 15075 |
} |
--- |
15075 |
} |
--- |
| 15076 |
} |
--- |
15076 |
} |
--- |
| 15077 |
|
--- |
15077 |
|
--- |
| 15078 |
// This node has been merged with another. |
--- |
15078 |
// This node has been merged with another. |
--- |
| 15079 |
if (N->getOpcode() == ISD::DELETED_NODE) |
0 |
15079 |
if (N->getOpcode() == ISD::DELETED_NODE) |
0 |
| 15080 |
return SDValue(N, 0); |
0 |
15080 |
return SDValue(N, 0); |
0 |
| 15081 |
|
--- |
15081 |
|
--- |
| 15082 |
// The whole node may have been updated, so the value we were holding |
--- |
15082 |
// The whole node may have been updated, so the value we were holding |
--- |
| 15083 |
// may no longer be valid. Re-fetch the operand we're `freeze`ing. |
--- |
15083 |
// may no longer be valid. Re-fetch the operand we're `freeze`ing. |
--- |
| 15084 |
N0 = N->getOperand(0); |
0 |
15084 |
N0 = N->getOperand(0); |
0 |
| 15085 |
|
--- |
15085 |
|
--- |
| 15086 |
// Finally, recreate the node, it's operands were updated to use |
--- |
15086 |
// Finally, recreate the node, it's operands were updated to use |
--- |
| 15087 |
// frozen operands, so we just need to use it's "original" operands. |
--- |
15087 |
// frozen operands, so we just need to use it's "original" operands. |
--- |
| 15088 |
SmallVector Ops(N0->op_begin(), N0->op_end()); |
0 |
15088 |
SmallVector Ops(N0->op_begin(), N0->op_end()); |
0 |
| 15089 |
// Special-handle ISD::UNDEF, each single one of them can be it's own thing. |
--- |
15089 |
// Special-handle ISD::UNDEF, each single one of them can be it's own thing. |
--- |
| 15090 |
for (SDValue &Op : Ops) { |
0 |
15090 |
for (SDValue &Op : Ops) { |
0 |
| 15091 |
if (Op.getOpcode() == ISD::UNDEF) |
0 |
15091 |
if (Op.getOpcode() == ISD::UNDEF) |
0 |
| 15092 |
Op = DAG.getFreeze(Op); |
0 |
15092 |
Op = DAG.getFreeze(Op); |
0 |
| 15093 |
} |
--- |
15093 |
} |
--- |
| 15094 |
// NOTE: this strips poison generating flags. |
--- |
15094 |
// NOTE: this strips poison generating flags. |
--- |
| 15095 |
SDValue R = DAG.getNode(N0.getOpcode(), SDLoc(N0), N0->getVTList(), Ops); |
0 |
15095 |
SDValue R = DAG.getNode(N0.getOpcode(), SDLoc(N0), N0->getVTList(), Ops); |
0 |
| 15096 |
assert(DAG.isGuaranteedNotToBeUndefOrPoison(R, /*PoisonOnly*/ false) && |
0 |
15096 |
assert(DAG.isGuaranteedNotToBeUndefOrPoison(R, /*PoisonOnly*/ false) && |
0 |
| 15097 |
"Can't create node that may be undef/poison!"); |
--- |
15097 |
"Can't create node that may be undef/poison!"); |
--- |
| 15098 |
return R; |
0 |
15098 |
return R; |
0 |
| 15099 |
} |
0 |
15099 |
} |
0 |
| 15100 |
|
--- |
15100 |
|
--- |
| 15101 |
/// We know that BV is a build_vector node with Constant, ConstantFP or Undef |
--- |
15101 |
/// We know that BV is a build_vector node with Constant, ConstantFP or Undef |
--- |
| 15102 |
/// operands. DstEltVT indicates the destination element value type. |
--- |
15102 |
/// operands. DstEltVT indicates the destination element value type. |
--- |
| 15103 |
SDValue DAGCombiner:: |
0 |
15103 |
SDValue DAGCombiner:: |
0 |
| 15104 |
ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { |
--- |
15104 |
ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { |
--- |
| 15105 |
EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); |
0 |
15105 |
EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); |
0 |
| 15106 |
|
--- |
15106 |
|
--- |
| 15107 |
// If this is already the right type, we're done. |
--- |
15107 |
// If this is already the right type, we're done. |
--- |
| 15108 |
if (SrcEltVT == DstEltVT) return SDValue(BV, 0); |
0 |
15108 |
if (SrcEltVT == DstEltVT) return SDValue(BV, 0); |
0 |
| 15109 |
|
--- |
15109 |
|
--- |
| 15110 |
unsigned SrcBitSize = SrcEltVT.getSizeInBits(); |
0 |
15110 |
unsigned SrcBitSize = SrcEltVT.getSizeInBits(); |
0 |
| 15111 |
unsigned DstBitSize = DstEltVT.getSizeInBits(); |
0 |
15111 |
unsigned DstBitSize = DstEltVT.getSizeInBits(); |
0 |
| 15112 |
|
--- |
15112 |
|
--- |
| 15113 |
// If this is a conversion of N elements of one type to N elements of another |
--- |
15113 |
// If this is a conversion of N elements of one type to N elements of another |
--- |
| 15114 |
// type, convert each element. This handles FP<->INT cases. |
--- |
15114 |
// type, convert each element. This handles FP<->INT cases. |
--- |
| 15115 |
if (SrcBitSize == DstBitSize) { |
0 |
15115 |
if (SrcBitSize == DstBitSize) { |
0 |
| 15116 |
SmallVector Ops; |
0 |
15116 |
SmallVector Ops; |
0 |
| 15117 |
for (SDValue Op : BV->op_values()) { |
0 |
15117 |
for (SDValue Op : BV->op_values()) { |
0 |
| 15118 |
// If the vector element type is not legal, the BUILD_VECTOR operands |
--- |
15118 |
// If the vector element type is not legal, the BUILD_VECTOR operands |
--- |
| 15119 |
// are promoted and implicitly truncated. Make that explicit here. |
--- |
15119 |
// are promoted and implicitly truncated. Make that explicit here. |
--- |
| 15120 |
if (Op.getValueType() != SrcEltVT) |
0 |
15120 |
if (Op.getValueType() != SrcEltVT) |
0 |
| 15121 |
Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op); |
0 |
15121 |
Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op); |
0 |
| 15122 |
Ops.push_back(DAG.getBitcast(DstEltVT, Op)); |
0 |
15122 |
Ops.push_back(DAG.getBitcast(DstEltVT, Op)); |
0 |
| 15123 |
AddToWorklist(Ops.back().getNode()); |
0 |
15123 |
AddToWorklist(Ops.back().getNode()); |
0 |
| 15124 |
} |
--- |
15124 |
} |
--- |
| 15125 |
EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, |
0 |
15125 |
EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, |
0 |
| 15126 |
BV->getValueType(0).getVectorNumElements()); |
0 |
15126 |
BV->getValueType(0).getVectorNumElements()); |
0 |
| 15127 |
return DAG.getBuildVector(VT, SDLoc(BV), Ops); |
0 |
15127 |
return DAG.getBuildVector(VT, SDLoc(BV), Ops); |
0 |
| 15128 |
} |
0 |
15128 |
} |
0 |
| 15129 |
|
--- |
15129 |
|
--- |
| 15130 |
// Otherwise, we're growing or shrinking the elements. To avoid having to |
--- |
15130 |
// Otherwise, we're growing or shrinking the elements. To avoid having to |
--- |
| 15131 |
// handle annoying details of growing/shrinking FP values, we convert them to |
--- |
15131 |
// handle annoying details of growing/shrinking FP values, we convert them to |
--- |
| 15132 |
// int first. |
--- |
15132 |
// int first. |
--- |
| 15133 |
if (SrcEltVT.isFloatingPoint()) { |
0 |
15133 |
if (SrcEltVT.isFloatingPoint()) { |
0 |
| 15134 |
// Convert the input float vector to a int vector where the elements are the |
--- |
15134 |
// Convert the input float vector to a int vector where the elements are the |
--- |
| 15135 |
// same sizes. |
--- |
15135 |
// same sizes. |
--- |
| 15136 |
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); |
0 |
15136 |
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); |
0 |
| 15137 |
BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); |
0 |
15137 |
BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); |
0 |
| 15138 |
SrcEltVT = IntVT; |
0 |
15138 |
SrcEltVT = IntVT; |
0 |
| 15139 |
} |
--- |
15139 |
} |
--- |
| 15140 |
|
--- |
15140 |
|
--- |
| 15141 |
// Now we know the input is an integer vector. If the output is a FP type, |
--- |
15141 |
// Now we know the input is an integer vector. If the output is a FP type, |
--- |
| 15142 |
// convert to integer first, then to FP of the right size. |
--- |
15142 |
// convert to integer first, then to FP of the right size. |
--- |
| 15143 |
if (DstEltVT.isFloatingPoint()) { |
0 |
15143 |
if (DstEltVT.isFloatingPoint()) { |
0 |
| 15144 |
EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); |
0 |
15144 |
EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); |
0 |
| 15145 |
SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); |
0 |
15145 |
SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); |
0 |
| 15146 |
|
--- |
15146 |
|
--- |
| 15147 |
// Next, convert to FP elements of the same size. |
--- |
15147 |
// Next, convert to FP elements of the same size. |
--- |
| 15148 |
return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); |
0 |
15148 |
return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); |
0 |
| 15149 |
} |
--- |
15149 |
} |
--- |
| 15150 |
|
--- |
15150 |
|
--- |
| 15151 |
// Okay, we know the src/dst types are both integers of differing types. |
--- |
15151 |
// Okay, we know the src/dst types are both integers of differing types. |
--- |
| 15152 |
assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); |
0 |
15152 |
assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); |
0 |
| 15153 |
|
--- |
15153 |
|
--- |
| 15154 |
// TODO: Should ConstantFoldBITCASTofBUILD_VECTOR always take a |
--- |
15154 |
// TODO: Should ConstantFoldBITCASTofBUILD_VECTOR always take a |
--- |
| 15155 |
// BuildVectorSDNode? |
--- |
15155 |
// BuildVectorSDNode? |
--- |
| 15156 |
auto *BVN = cast(BV); |
0 |
15156 |
auto *BVN = cast(BV); |
0 |
| 15157 |
|
--- |
15157 |
|
--- |
| 15158 |
// Extract the constant raw bit data. |
--- |
15158 |
// Extract the constant raw bit data. |
--- |
| 15159 |
BitVector UndefElements; |
0 |
15159 |
BitVector UndefElements; |
0 |
| 15160 |
SmallVector RawBits; |
0 |
15160 |
SmallVector RawBits; |
0 |
| 15161 |
bool IsLE = DAG.getDataLayout().isLittleEndian(); |
0 |
15161 |
bool IsLE = DAG.getDataLayout().isLittleEndian(); |
0 |
| 15162 |
if (!BVN->getConstantRawBits(IsLE, DstBitSize, RawBits, UndefElements)) |
0 |
15162 |
if (!BVN->getConstantRawBits(IsLE, DstBitSize, RawBits, UndefElements)) |
0 |
| 15163 |
return SDValue(); |
0 |
15163 |
return SDValue(); |
0 |
| 15164 |
|
--- |
15164 |
|
--- |
| 15165 |
SDLoc DL(BV); |
0 |
15165 |
SDLoc DL(BV); |
0 |
| 15166 |
SmallVector Ops; |
0 |
15166 |
SmallVector Ops; |
0 |
| 15167 |
for (unsigned I = 0, E = RawBits.size(); I != E; ++I) { |
0 |
15167 |
for (unsigned I = 0, E = RawBits.size(); I != E; ++I) { |
0 |
| 15168 |
if (UndefElements[I]) |
0 |
15168 |
if (UndefElements[I]) |
0 |
| 15169 |
Ops.push_back(DAG.getUNDEF(DstEltVT)); |
0 |
15169 |
Ops.push_back(DAG.getUNDEF(DstEltVT)); |
0 |
| 15170 |
else |
--- |
15170 |
else |
--- |
| 15171 |
Ops.push_back(DAG.getConstant(RawBits[I], DL, DstEltVT)); |
0 |
15171 |
Ops.push_back(DAG.getConstant(RawBits[I], DL, DstEltVT)); |
0 |
| 15172 |
} |
--- |
15172 |
} |
--- |
| 15173 |
|
--- |
15173 |
|
--- |
| 15174 |
EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); |
0 |
15174 |
EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); |
0 |
| 15175 |
return DAG.getBuildVector(VT, DL, Ops); |
0 |
15175 |
return DAG.getBuildVector(VT, DL, Ops); |
0 |
| 15176 |
} |
0 |
15176 |
} |
0 |
| 15177 |
|
--- |
15177 |
|
--- |
| 15178 |
// Returns true if floating point contraction is allowed on the FMUL-SDValue |
--- |
15178 |
// Returns true if floating point contraction is allowed on the FMUL-SDValue |
--- |
| 15179 |
// `N` |
--- |
15179 |
// `N` |
--- |
| 15180 |
static bool isContractableFMUL(const TargetOptions &Options, SDValue N) { |
0 |
15180 |
static bool isContractableFMUL(const TargetOptions &Options, SDValue N) { |
0 |
| 15181 |
assert(N.getOpcode() == ISD::FMUL); |
0 |
15181 |
assert(N.getOpcode() == ISD::FMUL); |
0 |
| 15182 |
|
--- |
15182 |
|
--- |
| 15183 |
return Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath || |
0 |
15183 |
return Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath || |
0 |
| 15184 |
N->getFlags().hasAllowContract(); |
0 |
15184 |
N->getFlags().hasAllowContract(); |
0 |
| 15185 |
} |
--- |
15185 |
} |
--- |
| 15186 |
|
--- |
15186 |
|
--- |
| 15187 |
// Returns true if `N` can assume no infinities involved in its computation. |
--- |
15187 |
// Returns true if `N` can assume no infinities involved in its computation. |
--- |
| 15188 |
static bool hasNoInfs(const TargetOptions &Options, SDValue N) { |
0 |
15188 |
static bool hasNoInfs(const TargetOptions &Options, SDValue N) { |
0 |
| 15189 |
return Options.NoInfsFPMath || N->getFlags().hasNoInfs(); |
0 |
15189 |
return Options.NoInfsFPMath || N->getFlags().hasNoInfs(); |
0 |
| 15190 |
} |
--- |
15190 |
} |
--- |
| 15191 |
|
--- |
15191 |
|
--- |
| 15192 |
/// Try to perform FMA combining on a given FADD node. |
--- |
15192 |
/// Try to perform FMA combining on a given FADD node. |
--- |
| 15193 |
template |
--- |
15193 |
template |
--- |
| 15194 |
SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) { |
0 |
15194 |
SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) { |
0 |
| 15195 |
SDValue N0 = N->getOperand(0); |
0 |
15195 |
SDValue N0 = N->getOperand(0); |
0 |
| 15196 |
SDValue N1 = N->getOperand(1); |
0 |
15196 |
SDValue N1 = N->getOperand(1); |
0 |
| 15197 |
EVT VT = N->getValueType(0); |
0 |
15197 |
EVT VT = N->getValueType(0); |
0 |
| 15198 |
SDLoc SL(N); |
0 |
15198 |
SDLoc SL(N); |
0 |
| 15199 |
MatchContextClass matcher(DAG, TLI, N); |
0 |
15199 |
MatchContextClass matcher(DAG, TLI, N); |
0 |
| 15200 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
15200 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
| 15201 |
|
--- |
15201 |
|
--- |
| 15202 |
bool UseVP = std::is_same_v; |
0 |
15202 |
bool UseVP = std::is_same_v; |
0 |
| 15203 |
|
--- |
15203 |
|
--- |
| 15204 |
// Floating-point multiply-add with intermediate rounding. |
--- |
15204 |
// Floating-point multiply-add with intermediate rounding. |
--- |
| 15205 |
// FIXME: Make isFMADLegal have specific behavior when using VPMatchContext. |
--- |
15205 |
// FIXME: Make isFMADLegal have specific behavior when using VPMatchContext. |
--- |
| 15206 |
// FIXME: Add VP_FMAD opcode. |
--- |
15206 |
// FIXME: Add VP_FMAD opcode. |
--- |
| 15207 |
bool HasFMAD = !UseVP && (LegalOperations && TLI.isFMADLegal(DAG, N)); |
0 |
15207 |
bool HasFMAD = !UseVP && (LegalOperations && TLI.isFMADLegal(DAG, N)); |
0 |
| 15208 |
|
--- |
15208 |
|
--- |
| 15209 |
// Floating-point multiply-add without intermediate rounding. |
--- |
15209 |
// Floating-point multiply-add without intermediate rounding. |
--- |
| 15210 |
bool HasFMA = |
0 |
15210 |
bool HasFMA = |
0 |
| 15211 |
TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT) && |
0 |
15211 |
TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT) && |
0 |
| 15212 |
(!LegalOperations || matcher.isOperationLegalOrCustom(ISD::FMA, VT)); |
0 |
15212 |
(!LegalOperations || matcher.isOperationLegalOrCustom(ISD::FMA, VT)); |
0 |
| 15213 |
|
--- |
15213 |
|
--- |
| 15214 |
// No valid opcode, do not combine. |
--- |
15214 |
// No valid opcode, do not combine. |
--- |
| 15215 |
if (!HasFMAD && !HasFMA) |
0 |
15215 |
if (!HasFMAD && !HasFMA) |
0 |
| 15216 |
return SDValue(); |
0 |
15216 |
return SDValue(); |
0 |
| 15217 |
|
--- |
15217 |
|
--- |
| 15218 |
bool CanReassociate = |
0 |
15218 |
bool CanReassociate = |
0 |
| 15219 |
Options.UnsafeFPMath || N->getFlags().hasAllowReassociation(); |
0 |
15219 |
Options.UnsafeFPMath || N->getFlags().hasAllowReassociation(); |
0 |
| 15220 |
bool AllowFusionGlobally = (Options.AllowFPOpFusion == FPOpFusion::Fast || |
0 |
15220 |
bool AllowFusionGlobally = (Options.AllowFPOpFusion == FPOpFusion::Fast || |
0 |
| 15221 |
Options.UnsafeFPMath || HasFMAD); |
0 |
15221 |
Options.UnsafeFPMath || HasFMAD); |
0 |
| 15222 |
// If the addition is not contractable, do not combine. |
--- |
15222 |
// If the addition is not contractable, do not combine. |
--- |
| 15223 |
if (!AllowFusionGlobally && !N->getFlags().hasAllowContract()) |
0 |
15223 |
if (!AllowFusionGlobally && !N->getFlags().hasAllowContract()) |
0 |
| 15224 |
return SDValue(); |
0 |
15224 |
return SDValue(); |
0 |
| 15225 |
|
--- |
15225 |
|
--- |
| 15226 |
// Folding fadd (fmul x, y), (fmul x, y) -> fma x, y, (fmul x, y) is never |
--- |
15226 |
// Folding fadd (fmul x, y), (fmul x, y) -> fma x, y, (fmul x, y) is never |
--- |
| 15227 |
// beneficial. It does not reduce latency. It increases register pressure. It |
--- |
15227 |
// beneficial. It does not reduce latency. It increases register pressure. It |
--- |
| 15228 |
// replaces an fadd with an fma which is a more complex instruction, so is |
--- |
15228 |
// replaces an fadd with an fma which is a more complex instruction, so is |
--- |
| 15229 |
// likely to have a larger encoding, use more functional units, etc. |
--- |
15229 |
// likely to have a larger encoding, use more functional units, etc. |
--- |
| 15230 |
if (N0 == N1) |
0 |
15230 |
if (N0 == N1) |
0 |
| 15231 |
return SDValue(); |
0 |
15231 |
return SDValue(); |
0 |
| 15232 |
|
--- |
15232 |
|
--- |
| 15233 |
if (TLI.generateFMAsInMachineCombiner(VT, OptLevel)) |
0 |
15233 |
if (TLI.generateFMAsInMachineCombiner(VT, OptLevel)) |
0 |
| 15234 |
return SDValue(); |
0 |
15234 |
return SDValue(); |
0 |
| 15235 |
|
--- |
15235 |
|
--- |
| 15236 |
// Always prefer FMAD to FMA for precision. |
--- |
15236 |
// Always prefer FMAD to FMA for precision. |
--- |
| 15237 |
unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; |
0 |
15237 |
unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; |
0 |
| 15238 |
bool Aggressive = TLI.enableAggressiveFMAFusion(VT); |
0 |
15238 |
bool Aggressive = TLI.enableAggressiveFMAFusion(VT); |
0 |
| 15239 |
|
--- |
15239 |
|
--- |
| 15240 |
auto isFusedOp = [&](SDValue N) { |
0 |
15240 |
auto isFusedOp = [&](SDValue N) { |
0 |
| 15241 |
return matcher.match(N, ISD::FMA) || matcher.match(N, ISD::FMAD); |
0 |
15241 |
return matcher.match(N, ISD::FMA) || matcher.match(N, ISD::FMAD); |
0 |
| 15242 |
}; |
--- |
15242 |
}; |
--- |
| 15243 |
|
--- |
15243 |
|
--- |
| 15244 |
// Is the node an FMUL and contractable either due to global flags or |
--- |
15244 |
// Is the node an FMUL and contractable either due to global flags or |
--- |
| 15245 |
// SDNodeFlags. |
--- |
15245 |
// SDNodeFlags. |
--- |
| 15246 |
auto isContractableFMUL = [AllowFusionGlobally, &matcher](SDValue N) { |
0 |
15246 |
auto isContractableFMUL = [AllowFusionGlobally, &matcher](SDValue N) { |
0 |
| 15247 |
if (!matcher.match(N, ISD::FMUL)) |
0 |
15247 |
if (!matcher.match(N, ISD::FMUL)) |
0 |
| 15248 |
return false; |
0 |
15248 |
return false; |
0 |
| 15249 |
return AllowFusionGlobally || N->getFlags().hasAllowContract(); |
0 |
15249 |
return AllowFusionGlobally || N->getFlags().hasAllowContract(); |
0 |
| 15250 |
}; |
--- |
15250 |
}; |
--- |
| 15251 |
// If we have two choices trying to fold (fadd (fmul u, v), (fmul x, y)), |
--- |
15251 |
// If we have two choices trying to fold (fadd (fmul u, v), (fmul x, y)), |
--- |
| 15252 |
// prefer to fold the multiply with fewer uses. |
--- |
15252 |
// prefer to fold the multiply with fewer uses. |
--- |
| 15253 |
if (Aggressive && isContractableFMUL(N0) && isContractableFMUL(N1)) { |
0 |
15253 |
if (Aggressive && isContractableFMUL(N0) && isContractableFMUL(N1)) { |
0 |
| 15254 |
if (N0->use_size() > N1->use_size()) |
0 |
15254 |
if (N0->use_size() > N1->use_size()) |
0 |
| 15255 |
std::swap(N0, N1); |
0 |
15255 |
std::swap(N0, N1); |
0 |
| 15256 |
} |
--- |
15256 |
} |
--- |
| 15257 |
|
--- |
15257 |
|
--- |
| 15258 |
// fold (fadd (fmul x, y), z) -> (fma x, y, z) |
--- |
15258 |
// fold (fadd (fmul x, y), z) -> (fma x, y, z) |
--- |
| 15259 |
if (isContractableFMUL(N0) && (Aggressive || N0->hasOneUse())) { |
0 |
15259 |
if (isContractableFMUL(N0) && (Aggressive || N0->hasOneUse())) { |
0 |
| 15260 |
return matcher.getNode(PreferredFusedOpcode, SL, VT, N0.getOperand(0), |
0 |
15260 |
return matcher.getNode(PreferredFusedOpcode, SL, VT, N0.getOperand(0), |
0 |
| 15261 |
N0.getOperand(1), N1); |
0 |
15261 |
N0.getOperand(1), N1); |
0 |
| 15262 |
} |
--- |
15262 |
} |
--- |
| 15263 |
|
--- |
15263 |
|
--- |
| 15264 |
// fold (fadd x, (fmul y, z)) -> (fma y, z, x) |
--- |
15264 |
// fold (fadd x, (fmul y, z)) -> (fma y, z, x) |
--- |
| 15265 |
// Note: Commutes FADD operands. |
--- |
15265 |
// Note: Commutes FADD operands. |
--- |
| 15266 |
if (isContractableFMUL(N1) && (Aggressive || N1->hasOneUse())) { |
0 |
15266 |
if (isContractableFMUL(N1) && (Aggressive || N1->hasOneUse())) { |
0 |
| 15267 |
return matcher.getNode(PreferredFusedOpcode, SL, VT, N1.getOperand(0), |
0 |
15267 |
return matcher.getNode(PreferredFusedOpcode, SL, VT, N1.getOperand(0), |
0 |
| 15268 |
N1.getOperand(1), N0); |
0 |
15268 |
N1.getOperand(1), N0); |
0 |
| 15269 |
} |
--- |
15269 |
} |
--- |
| 15270 |
|
--- |
15270 |
|
--- |
| 15271 |
// fadd (fma A, B, (fmul C, D)), E --> fma A, B, (fma C, D, E) |
--- |
15271 |
// fadd (fma A, B, (fmul C, D)), E --> fma A, B, (fma C, D, E) |
--- |
| 15272 |
// fadd E, (fma A, B, (fmul C, D)) --> fma A, B, (fma C, D, E) |
--- |
15272 |
// fadd E, (fma A, B, (fmul C, D)) --> fma A, B, (fma C, D, E) |
--- |
| 15273 |
// This also works with nested fma instructions: |
--- |
15273 |
// This also works with nested fma instructions: |
--- |
| 15274 |
// fadd (fma A, B, (fma (C, D, (fmul (E, F))))), G --> |
--- |
15274 |
// fadd (fma A, B, (fma (C, D, (fmul (E, F))))), G --> |
--- |
| 15275 |
// fma A, B, (fma C, D, fma (E, F, G)) |
--- |
15275 |
// fma A, B, (fma C, D, fma (E, F, G)) |
--- |
| 15276 |
// fadd (G, (fma A, B, (fma (C, D, (fmul (E, F)))))) --> |
--- |
15276 |
// fadd (G, (fma A, B, (fma (C, D, (fmul (E, F)))))) --> |
--- |
| 15277 |
// fma A, B, (fma C, D, fma (E, F, G)). |
--- |
15277 |
// fma A, B, (fma C, D, fma (E, F, G)). |
--- |
| 15278 |
// This requires reassociation because it changes the order of operations. |
--- |
15278 |
// This requires reassociation because it changes the order of operations. |
--- |
| 15279 |
if (CanReassociate) { |
0 |
15279 |
if (CanReassociate) { |
0 |
| 15280 |
SDValue FMA, E; |
0 |
15280 |
SDValue FMA, E; |
0 |
| 15281 |
if (isFusedOp(N0) && N0.hasOneUse()) { |
0 |
15281 |
if (isFusedOp(N0) && N0.hasOneUse()) { |
0 |
| 15282 |
FMA = N0; |
0 |
15282 |
FMA = N0; |
0 |
| 15283 |
E = N1; |
0 |
15283 |
E = N1; |
0 |
| 15284 |
} else if (isFusedOp(N1) && N1.hasOneUse()) { |
0 |
15284 |
} else if (isFusedOp(N1) && N1.hasOneUse()) { |
0 |
| 15285 |
FMA = N1; |
0 |
15285 |
FMA = N1; |
0 |
| 15286 |
E = N0; |
0 |
15286 |
E = N0; |
0 |
| 15287 |
} |
--- |
15287 |
} |
--- |
| 15288 |
|
--- |
15288 |
|
--- |
| 15289 |
SDValue TmpFMA = FMA; |
0 |
15289 |
SDValue TmpFMA = FMA; |
0 |
| 15290 |
while (E && isFusedOp(TmpFMA) && TmpFMA.hasOneUse()) { |
0 |
15290 |
while (E && isFusedOp(TmpFMA) && TmpFMA.hasOneUse()) { |
0 |
| 15291 |
SDValue FMul = TmpFMA->getOperand(2); |
0 |
15291 |
SDValue FMul = TmpFMA->getOperand(2); |
0 |
| 15292 |
if (matcher.match(FMul, ISD::FMUL) && FMul.hasOneUse()) { |
0 |
15292 |
if (matcher.match(FMul, ISD::FMUL) && FMul.hasOneUse()) { |
0 |
| 15293 |
SDValue C = FMul.getOperand(0); |
0 |
15293 |
SDValue C = FMul.getOperand(0); |
0 |
| 15294 |
SDValue D = FMul.getOperand(1); |
0 |
15294 |
SDValue D = FMul.getOperand(1); |
0 |
| 15295 |
SDValue CDE = matcher.getNode(PreferredFusedOpcode, SL, VT, C, D, E); |
0 |
15295 |
SDValue CDE = matcher.getNode(PreferredFusedOpcode, SL, VT, C, D, E); |
0 |
| 15296 |
DAG.ReplaceAllUsesOfValueWith(FMul, CDE); |
0 |
15296 |
DAG.ReplaceAllUsesOfValueWith(FMul, CDE); |
0 |
| 15297 |
// Replacing the inner FMul could cause the outer FMA to be simplified |
--- |
15297 |
// Replacing the inner FMul could cause the outer FMA to be simplified |
--- |
| 15298 |
// away. |
--- |
15298 |
// away. |
--- |
| 15299 |
return FMA.getOpcode() == ISD::DELETED_NODE ? SDValue() : FMA; |
0 |
15299 |
return FMA.getOpcode() == ISD::DELETED_NODE ? SDValue() : FMA; |
0 |
| 15300 |
} |
--- |
15300 |
} |
--- |
| 15301 |
|
--- |
15301 |
|
--- |
| 15302 |
TmpFMA = TmpFMA->getOperand(2); |
0 |
15302 |
TmpFMA = TmpFMA->getOperand(2); |
0 |
| 15303 |
} |
--- |
15303 |
} |
--- |
| 15304 |
} |
--- |
15304 |
} |
--- |
| 15305 |
|
--- |
15305 |
|
--- |
| 15306 |
// Look through FP_EXTEND nodes to do more combining. |
--- |
15306 |
// Look through FP_EXTEND nodes to do more combining. |
--- |
| 15307 |
|
--- |
15307 |
|
--- |
| 15308 |
// fold (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) |
--- |
15308 |
// fold (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) |
--- |
| 15309 |
if (matcher.match(N0, ISD::FP_EXTEND)) { |
0 |
15309 |
if (matcher.match(N0, ISD::FP_EXTEND)) { |
0 |
| 15310 |
SDValue N00 = N0.getOperand(0); |
0 |
15310 |
SDValue N00 = N0.getOperand(0); |
0 |
| 15311 |
if (isContractableFMUL(N00) && |
0 |
15311 |
if (isContractableFMUL(N00) && |
0 |
| 15312 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15312 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15313 |
N00.getValueType())) { |
--- |
15313 |
N00.getValueType())) { |
--- |
| 15314 |
return matcher.getNode( |
0 |
15314 |
return matcher.getNode( |
0 |
| 15315 |
PreferredFusedOpcode, SL, VT, |
--- |
15315 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15316 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)), |
0 |
15316 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)), |
0 |
| 15317 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)), N1); |
0 |
15317 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)), N1); |
0 |
| 15318 |
} |
--- |
15318 |
} |
--- |
| 15319 |
} |
--- |
15319 |
} |
--- |
| 15320 |
|
--- |
15320 |
|
--- |
| 15321 |
// fold (fadd x, (fpext (fmul y, z))) -> (fma (fpext y), (fpext z), x) |
--- |
15321 |
// fold (fadd x, (fpext (fmul y, z))) -> (fma (fpext y), (fpext z), x) |
--- |
| 15322 |
// Note: Commutes FADD operands. |
--- |
15322 |
// Note: Commutes FADD operands. |
--- |
| 15323 |
if (matcher.match(N1, ISD::FP_EXTEND)) { |
0 |
15323 |
if (matcher.match(N1, ISD::FP_EXTEND)) { |
0 |
| 15324 |
SDValue N10 = N1.getOperand(0); |
0 |
15324 |
SDValue N10 = N1.getOperand(0); |
0 |
| 15325 |
if (isContractableFMUL(N10) && |
0 |
15325 |
if (isContractableFMUL(N10) && |
0 |
| 15326 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15326 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15327 |
N10.getValueType())) { |
--- |
15327 |
N10.getValueType())) { |
--- |
| 15328 |
return matcher.getNode( |
0 |
15328 |
return matcher.getNode( |
0 |
| 15329 |
PreferredFusedOpcode, SL, VT, |
--- |
15329 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15330 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(0)), |
0 |
15330 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(0)), |
0 |
| 15331 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(1)), N0); |
0 |
15331 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(1)), N0); |
0 |
| 15332 |
} |
--- |
15332 |
} |
--- |
| 15333 |
} |
--- |
15333 |
} |
--- |
| 15334 |
|
--- |
15334 |
|
--- |
| 15335 |
// More folding opportunities when target permits. |
--- |
15335 |
// More folding opportunities when target permits. |
--- |
| 15336 |
if (Aggressive) { |
0 |
15336 |
if (Aggressive) { |
0 |
| 15337 |
// fold (fadd (fma x, y, (fpext (fmul u, v))), z) |
--- |
15337 |
// fold (fadd (fma x, y, (fpext (fmul u, v))), z) |
--- |
| 15338 |
// -> (fma x, y, (fma (fpext u), (fpext v), z)) |
--- |
15338 |
// -> (fma x, y, (fma (fpext u), (fpext v), z)) |
--- |
| 15339 |
auto FoldFAddFMAFPExtFMul = [&](SDValue X, SDValue Y, SDValue U, SDValue V, |
0 |
15339 |
auto FoldFAddFMAFPExtFMul = [&](SDValue X, SDValue Y, SDValue U, SDValue V, |
0 |
| 15340 |
SDValue Z) { |
--- |
15340 |
SDValue Z) { |
--- |
| 15341 |
return matcher.getNode( |
0 |
15341 |
return matcher.getNode( |
0 |
| 15342 |
PreferredFusedOpcode, SL, VT, X, Y, |
--- |
15342 |
PreferredFusedOpcode, SL, VT, X, Y, |
--- |
| 15343 |
matcher.getNode(PreferredFusedOpcode, SL, VT, |
0 |
15343 |
matcher.getNode(PreferredFusedOpcode, SL, VT, |
0 |
| 15344 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, U), |
0 |
15344 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, U), |
0 |
| 15345 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, V), Z)); |
0 |
15345 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, V), Z)); |
0 |
| 15346 |
}; |
--- |
15346 |
}; |
--- |
| 15347 |
if (isFusedOp(N0)) { |
0 |
15347 |
if (isFusedOp(N0)) { |
0 |
| 15348 |
SDValue N02 = N0.getOperand(2); |
0 |
15348 |
SDValue N02 = N0.getOperand(2); |
0 |
| 15349 |
if (matcher.match(N02, ISD::FP_EXTEND)) { |
0 |
15349 |
if (matcher.match(N02, ISD::FP_EXTEND)) { |
0 |
| 15350 |
SDValue N020 = N02.getOperand(0); |
0 |
15350 |
SDValue N020 = N02.getOperand(0); |
0 |
| 15351 |
if (isContractableFMUL(N020) && |
0 |
15351 |
if (isContractableFMUL(N020) && |
0 |
| 15352 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15352 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15353 |
N020.getValueType())) { |
--- |
15353 |
N020.getValueType())) { |
--- |
| 15354 |
return FoldFAddFMAFPExtFMul(N0.getOperand(0), N0.getOperand(1), |
0 |
15354 |
return FoldFAddFMAFPExtFMul(N0.getOperand(0), N0.getOperand(1), |
0 |
| 15355 |
N020.getOperand(0), N020.getOperand(1), |
0 |
15355 |
N020.getOperand(0), N020.getOperand(1), |
0 |
| 15356 |
N1); |
0 |
15356 |
N1); |
0 |
| 15357 |
} |
--- |
15357 |
} |
--- |
| 15358 |
} |
--- |
15358 |
} |
--- |
| 15359 |
} |
--- |
15359 |
} |
--- |
| 15360 |
|
--- |
15360 |
|
--- |
| 15361 |
// fold (fadd (fpext (fma x, y, (fmul u, v))), z) |
--- |
15361 |
// fold (fadd (fpext (fma x, y, (fmul u, v))), z) |
--- |
| 15362 |
// -> (fma (fpext x), (fpext y), (fma (fpext u), (fpext v), z)) |
--- |
15362 |
// -> (fma (fpext x), (fpext y), (fma (fpext u), (fpext v), z)) |
--- |
| 15363 |
// FIXME: This turns two single-precision and one double-precision |
--- |
15363 |
// FIXME: This turns two single-precision and one double-precision |
--- |
| 15364 |
// operation into two double-precision operations, which might not be |
--- |
15364 |
// operation into two double-precision operations, which might not be |
--- |
| 15365 |
// interesting for all targets, especially GPUs. |
--- |
15365 |
// interesting for all targets, especially GPUs. |
--- |
| 15366 |
auto FoldFAddFPExtFMAFMul = [&](SDValue X, SDValue Y, SDValue U, SDValue V, |
0 |
15366 |
auto FoldFAddFPExtFMAFMul = [&](SDValue X, SDValue Y, SDValue U, SDValue V, |
0 |
| 15367 |
SDValue Z) { |
--- |
15367 |
SDValue Z) { |
--- |
| 15368 |
return matcher.getNode( |
0 |
15368 |
return matcher.getNode( |
0 |
| 15369 |
PreferredFusedOpcode, SL, VT, |
--- |
15369 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15370 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, X), |
0 |
15370 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, X), |
0 |
| 15371 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, Y), |
0 |
15371 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, Y), |
0 |
| 15372 |
matcher.getNode(PreferredFusedOpcode, SL, VT, |
0 |
15372 |
matcher.getNode(PreferredFusedOpcode, SL, VT, |
0 |
| 15373 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, U), |
0 |
15373 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, U), |
0 |
| 15374 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, V), Z)); |
0 |
15374 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, V), Z)); |
0 |
| 15375 |
}; |
--- |
15375 |
}; |
--- |
| 15376 |
if (N0.getOpcode() == ISD::FP_EXTEND) { |
0 |
15376 |
if (N0.getOpcode() == ISD::FP_EXTEND) { |
0 |
| 15377 |
SDValue N00 = N0.getOperand(0); |
0 |
15377 |
SDValue N00 = N0.getOperand(0); |
0 |
| 15378 |
if (isFusedOp(N00)) { |
0 |
15378 |
if (isFusedOp(N00)) { |
0 |
| 15379 |
SDValue N002 = N00.getOperand(2); |
0 |
15379 |
SDValue N002 = N00.getOperand(2); |
0 |
| 15380 |
if (isContractableFMUL(N002) && |
0 |
15380 |
if (isContractableFMUL(N002) && |
0 |
| 15381 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15381 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15382 |
N00.getValueType())) { |
--- |
15382 |
N00.getValueType())) { |
--- |
| 15383 |
return FoldFAddFPExtFMAFMul(N00.getOperand(0), N00.getOperand(1), |
0 |
15383 |
return FoldFAddFPExtFMAFMul(N00.getOperand(0), N00.getOperand(1), |
0 |
| 15384 |
N002.getOperand(0), N002.getOperand(1), |
0 |
15384 |
N002.getOperand(0), N002.getOperand(1), |
0 |
| 15385 |
N1); |
0 |
15385 |
N1); |
0 |
| 15386 |
} |
--- |
15386 |
} |
--- |
| 15387 |
} |
--- |
15387 |
} |
--- |
| 15388 |
} |
--- |
15388 |
} |
--- |
| 15389 |
|
--- |
15389 |
|
--- |
| 15390 |
// fold (fadd x, (fma y, z, (fpext (fmul u, v))) |
--- |
15390 |
// fold (fadd x, (fma y, z, (fpext (fmul u, v))) |
--- |
| 15391 |
// -> (fma y, z, (fma (fpext u), (fpext v), x)) |
--- |
15391 |
// -> (fma y, z, (fma (fpext u), (fpext v), x)) |
--- |
| 15392 |
if (isFusedOp(N1)) { |
0 |
15392 |
if (isFusedOp(N1)) { |
0 |
| 15393 |
SDValue N12 = N1.getOperand(2); |
0 |
15393 |
SDValue N12 = N1.getOperand(2); |
0 |
| 15394 |
if (N12.getOpcode() == ISD::FP_EXTEND) { |
0 |
15394 |
if (N12.getOpcode() == ISD::FP_EXTEND) { |
0 |
| 15395 |
SDValue N120 = N12.getOperand(0); |
0 |
15395 |
SDValue N120 = N12.getOperand(0); |
0 |
| 15396 |
if (isContractableFMUL(N120) && |
0 |
15396 |
if (isContractableFMUL(N120) && |
0 |
| 15397 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15397 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15398 |
N120.getValueType())) { |
--- |
15398 |
N120.getValueType())) { |
--- |
| 15399 |
return FoldFAddFMAFPExtFMul(N1.getOperand(0), N1.getOperand(1), |
0 |
15399 |
return FoldFAddFMAFPExtFMul(N1.getOperand(0), N1.getOperand(1), |
0 |
| 15400 |
N120.getOperand(0), N120.getOperand(1), |
0 |
15400 |
N120.getOperand(0), N120.getOperand(1), |
0 |
| 15401 |
N0); |
0 |
15401 |
N0); |
0 |
| 15402 |
} |
--- |
15402 |
} |
--- |
| 15403 |
} |
--- |
15403 |
} |
--- |
| 15404 |
} |
--- |
15404 |
} |
--- |
| 15405 |
|
--- |
15405 |
|
--- |
| 15406 |
// fold (fadd x, (fpext (fma y, z, (fmul u, v))) |
--- |
15406 |
// fold (fadd x, (fpext (fma y, z, (fmul u, v))) |
--- |
| 15407 |
// -> (fma (fpext y), (fpext z), (fma (fpext u), (fpext v), x)) |
--- |
15407 |
// -> (fma (fpext y), (fpext z), (fma (fpext u), (fpext v), x)) |
--- |
| 15408 |
// FIXME: This turns two single-precision and one double-precision |
--- |
15408 |
// FIXME: This turns two single-precision and one double-precision |
--- |
| 15409 |
// operation into two double-precision operations, which might not be |
--- |
15409 |
// operation into two double-precision operations, which might not be |
--- |
| 15410 |
// interesting for all targets, especially GPUs. |
--- |
15410 |
// interesting for all targets, especially GPUs. |
--- |
| 15411 |
if (N1.getOpcode() == ISD::FP_EXTEND) { |
0 |
15411 |
if (N1.getOpcode() == ISD::FP_EXTEND) { |
0 |
| 15412 |
SDValue N10 = N1.getOperand(0); |
0 |
15412 |
SDValue N10 = N1.getOperand(0); |
0 |
| 15413 |
if (isFusedOp(N10)) { |
0 |
15413 |
if (isFusedOp(N10)) { |
0 |
| 15414 |
SDValue N102 = N10.getOperand(2); |
0 |
15414 |
SDValue N102 = N10.getOperand(2); |
0 |
| 15415 |
if (isContractableFMUL(N102) && |
0 |
15415 |
if (isContractableFMUL(N102) && |
0 |
| 15416 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15416 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15417 |
N10.getValueType())) { |
--- |
15417 |
N10.getValueType())) { |
--- |
| 15418 |
return FoldFAddFPExtFMAFMul(N10.getOperand(0), N10.getOperand(1), |
0 |
15418 |
return FoldFAddFPExtFMAFMul(N10.getOperand(0), N10.getOperand(1), |
0 |
| 15419 |
N102.getOperand(0), N102.getOperand(1), |
0 |
15419 |
N102.getOperand(0), N102.getOperand(1), |
0 |
| 15420 |
N0); |
0 |
15420 |
N0); |
0 |
| 15421 |
} |
--- |
15421 |
} |
--- |
| 15422 |
} |
--- |
15422 |
} |
--- |
| 15423 |
} |
--- |
15423 |
} |
--- |
| 15424 |
} |
--- |
15424 |
} |
--- |
| 15425 |
|
--- |
15425 |
|
--- |
| 15426 |
return SDValue(); |
0 |
15426 |
return SDValue(); |
0 |
| 15427 |
} |
0 |
15427 |
} |
0 |
| 15428 |
|
--- |
15428 |
|
--- |
| 15429 |
/// Try to perform FMA combining on a given FSUB node. |
--- |
15429 |
/// Try to perform FMA combining on a given FSUB node. |
--- |
| 15430 |
template |
--- |
15430 |
template |
--- |
| 15431 |
SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) { |
0 |
15431 |
SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) { |
0 |
| 15432 |
SDValue N0 = N->getOperand(0); |
0 |
15432 |
SDValue N0 = N->getOperand(0); |
0 |
| 15433 |
SDValue N1 = N->getOperand(1); |
0 |
15433 |
SDValue N1 = N->getOperand(1); |
0 |
| 15434 |
EVT VT = N->getValueType(0); |
0 |
15434 |
EVT VT = N->getValueType(0); |
0 |
| 15435 |
SDLoc SL(N); |
0 |
15435 |
SDLoc SL(N); |
0 |
| 15436 |
MatchContextClass matcher(DAG, TLI, N); |
0 |
15436 |
MatchContextClass matcher(DAG, TLI, N); |
0 |
| 15437 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
15437 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
| 15438 |
|
--- |
15438 |
|
--- |
| 15439 |
bool UseVP = std::is_same_v; |
0 |
15439 |
bool UseVP = std::is_same_v; |
0 |
| 15440 |
|
--- |
15440 |
|
--- |
| 15441 |
// Floating-point multiply-add with intermediate rounding. |
--- |
15441 |
// Floating-point multiply-add with intermediate rounding. |
--- |
| 15442 |
// FIXME: Make isFMADLegal have specific behavior when using VPMatchContext. |
--- |
15442 |
// FIXME: Make isFMADLegal have specific behavior when using VPMatchContext. |
--- |
| 15443 |
// FIXME: Add VP_FMAD opcode. |
--- |
15443 |
// FIXME: Add VP_FMAD opcode. |
--- |
| 15444 |
bool HasFMAD = !UseVP && (LegalOperations && TLI.isFMADLegal(DAG, N)); |
0 |
15444 |
bool HasFMAD = !UseVP && (LegalOperations && TLI.isFMADLegal(DAG, N)); |
0 |
| 15445 |
|
--- |
15445 |
|
--- |
| 15446 |
// Floating-point multiply-add without intermediate rounding. |
--- |
15446 |
// Floating-point multiply-add without intermediate rounding. |
--- |
| 15447 |
bool HasFMA = |
0 |
15447 |
bool HasFMA = |
0 |
| 15448 |
TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT) && |
0 |
15448 |
TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT) && |
0 |
| 15449 |
(!LegalOperations || matcher.isOperationLegalOrCustom(ISD::FMA, VT)); |
0 |
15449 |
(!LegalOperations || matcher.isOperationLegalOrCustom(ISD::FMA, VT)); |
0 |
| 15450 |
|
--- |
15450 |
|
--- |
| 15451 |
// No valid opcode, do not combine. |
--- |
15451 |
// No valid opcode, do not combine. |
--- |
| 15452 |
if (!HasFMAD && !HasFMA) |
0 |
15452 |
if (!HasFMAD && !HasFMA) |
0 |
| 15453 |
return SDValue(); |
0 |
15453 |
return SDValue(); |
0 |
| 15454 |
|
--- |
15454 |
|
--- |
| 15455 |
const SDNodeFlags Flags = N->getFlags(); |
0 |
15455 |
const SDNodeFlags Flags = N->getFlags(); |
0 |
| 15456 |
bool AllowFusionGlobally = (Options.AllowFPOpFusion == FPOpFusion::Fast || |
0 |
15456 |
bool AllowFusionGlobally = (Options.AllowFPOpFusion == FPOpFusion::Fast || |
0 |
| 15457 |
Options.UnsafeFPMath || HasFMAD); |
0 |
15457 |
Options.UnsafeFPMath || HasFMAD); |
0 |
| 15458 |
|
--- |
15458 |
|
--- |
| 15459 |
// If the subtraction is not contractable, do not combine. |
--- |
15459 |
// If the subtraction is not contractable, do not combine. |
--- |
| 15460 |
if (!AllowFusionGlobally && !N->getFlags().hasAllowContract()) |
0 |
15460 |
if (!AllowFusionGlobally && !N->getFlags().hasAllowContract()) |
0 |
| 15461 |
return SDValue(); |
0 |
15461 |
return SDValue(); |
0 |
| 15462 |
|
--- |
15462 |
|
--- |
| 15463 |
if (TLI.generateFMAsInMachineCombiner(VT, OptLevel)) |
0 |
15463 |
if (TLI.generateFMAsInMachineCombiner(VT, OptLevel)) |
0 |
| 15464 |
return SDValue(); |
0 |
15464 |
return SDValue(); |
0 |
| 15465 |
|
--- |
15465 |
|
--- |
| 15466 |
// Always prefer FMAD to FMA for precision. |
--- |
15466 |
// Always prefer FMAD to FMA for precision. |
--- |
| 15467 |
unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; |
0 |
15467 |
unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; |
0 |
| 15468 |
bool Aggressive = TLI.enableAggressiveFMAFusion(VT); |
0 |
15468 |
bool Aggressive = TLI.enableAggressiveFMAFusion(VT); |
0 |
| 15469 |
bool NoSignedZero = Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros(); |
0 |
15469 |
bool NoSignedZero = Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros(); |
0 |
| 15470 |
|
--- |
15470 |
|
--- |
| 15471 |
// Is the node an FMUL and contractable either due to global flags or |
--- |
15471 |
// Is the node an FMUL and contractable either due to global flags or |
--- |
| 15472 |
// SDNodeFlags. |
--- |
15472 |
// SDNodeFlags. |
--- |
| 15473 |
auto isContractableFMUL = [AllowFusionGlobally, &matcher](SDValue N) { |
0 |
15473 |
auto isContractableFMUL = [AllowFusionGlobally, &matcher](SDValue N) { |
0 |
| 15474 |
if (!matcher.match(N, ISD::FMUL)) |
0 |
15474 |
if (!matcher.match(N, ISD::FMUL)) |
0 |
| 15475 |
return false; |
0 |
15475 |
return false; |
0 |
| 15476 |
return AllowFusionGlobally || N->getFlags().hasAllowContract(); |
0 |
15476 |
return AllowFusionGlobally || N->getFlags().hasAllowContract(); |
0 |
| 15477 |
}; |
--- |
15477 |
}; |
--- |
| 15478 |
|
--- |
15478 |
|
--- |
| 15479 |
// fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) |
--- |
15479 |
// fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) |
--- |
| 15480 |
auto tryToFoldXYSubZ = [&](SDValue XY, SDValue Z) { |
0 |
15480 |
auto tryToFoldXYSubZ = [&](SDValue XY, SDValue Z) { |
0 |
| 15481 |
if (isContractableFMUL(XY) && (Aggressive || XY->hasOneUse())) { |
0 |
15481 |
if (isContractableFMUL(XY) && (Aggressive || XY->hasOneUse())) { |
0 |
| 15482 |
return matcher.getNode(PreferredFusedOpcode, SL, VT, XY.getOperand(0), |
0 |
15482 |
return matcher.getNode(PreferredFusedOpcode, SL, VT, XY.getOperand(0), |
0 |
| 15483 |
XY.getOperand(1), |
0 |
15483 |
XY.getOperand(1), |
0 |
| 15484 |
matcher.getNode(ISD::FNEG, SL, VT, Z)); |
0 |
15484 |
matcher.getNode(ISD::FNEG, SL, VT, Z)); |
0 |
| 15485 |
} |
--- |
15485 |
} |
--- |
| 15486 |
return SDValue(); |
0 |
15486 |
return SDValue(); |
0 |
| 15487 |
}; |
--- |
15487 |
}; |
--- |
| 15488 |
|
--- |
15488 |
|
--- |
| 15489 |
// fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) |
--- |
15489 |
// fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) |
--- |
| 15490 |
// Note: Commutes FSUB operands. |
--- |
15490 |
// Note: Commutes FSUB operands. |
--- |
| 15491 |
auto tryToFoldXSubYZ = [&](SDValue X, SDValue YZ) { |
0 |
15491 |
auto tryToFoldXSubYZ = [&](SDValue X, SDValue YZ) { |
0 |
| 15492 |
if (isContractableFMUL(YZ) && (Aggressive || YZ->hasOneUse())) { |
0 |
15492 |
if (isContractableFMUL(YZ) && (Aggressive || YZ->hasOneUse())) { |
0 |
| 15493 |
return matcher.getNode( |
0 |
15493 |
return matcher.getNode( |
0 |
| 15494 |
PreferredFusedOpcode, SL, VT, |
--- |
15494 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15495 |
matcher.getNode(ISD::FNEG, SL, VT, YZ.getOperand(0)), |
0 |
15495 |
matcher.getNode(ISD::FNEG, SL, VT, YZ.getOperand(0)), |
0 |
| 15496 |
YZ.getOperand(1), X); |
0 |
15496 |
YZ.getOperand(1), X); |
0 |
| 15497 |
} |
--- |
15497 |
} |
--- |
| 15498 |
return SDValue(); |
0 |
15498 |
return SDValue(); |
0 |
| 15499 |
}; |
--- |
15499 |
}; |
--- |
| 15500 |
|
--- |
15500 |
|
--- |
| 15501 |
// If we have two choices trying to fold (fsub (fmul u, v), (fmul x, y)), |
--- |
15501 |
// If we have two choices trying to fold (fsub (fmul u, v), (fmul x, y)), |
--- |
| 15502 |
// prefer to fold the multiply with fewer uses. |
--- |
15502 |
// prefer to fold the multiply with fewer uses. |
--- |
| 15503 |
if (isContractableFMUL(N0) && isContractableFMUL(N1) && |
0 |
15503 |
if (isContractableFMUL(N0) && isContractableFMUL(N1) && |
0 |
| 15504 |
(N0->use_size() > N1->use_size())) { |
0 |
15504 |
(N0->use_size() > N1->use_size())) { |
0 |
| 15505 |
// fold (fsub (fmul a, b), (fmul c, d)) -> (fma (fneg c), d, (fmul a, b)) |
--- |
15505 |
// fold (fsub (fmul a, b), (fmul c, d)) -> (fma (fneg c), d, (fmul a, b)) |
--- |
| 15506 |
if (SDValue V = tryToFoldXSubYZ(N0, N1)) |
0 |
15506 |
if (SDValue V = tryToFoldXSubYZ(N0, N1)) |
0 |
| 15507 |
return V; |
0 |
15507 |
return V; |
0 |
| 15508 |
// fold (fsub (fmul a, b), (fmul c, d)) -> (fma a, b, (fneg (fmul c, d))) |
--- |
15508 |
// fold (fsub (fmul a, b), (fmul c, d)) -> (fma a, b, (fneg (fmul c, d))) |
--- |
| 15509 |
if (SDValue V = tryToFoldXYSubZ(N0, N1)) |
0 |
15509 |
if (SDValue V = tryToFoldXYSubZ(N0, N1)) |
0 |
| 15510 |
return V; |
0 |
15510 |
return V; |
0 |
| 15511 |
} else { |
--- |
15511 |
} else { |
--- |
| 15512 |
// fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) |
--- |
15512 |
// fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) |
--- |
| 15513 |
if (SDValue V = tryToFoldXYSubZ(N0, N1)) |
0 |
15513 |
if (SDValue V = tryToFoldXYSubZ(N0, N1)) |
0 |
| 15514 |
return V; |
0 |
15514 |
return V; |
0 |
| 15515 |
// fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) |
--- |
15515 |
// fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) |
--- |
| 15516 |
if (SDValue V = tryToFoldXSubYZ(N0, N1)) |
0 |
15516 |
if (SDValue V = tryToFoldXSubYZ(N0, N1)) |
0 |
| 15517 |
return V; |
0 |
15517 |
return V; |
0 |
| 15518 |
} |
--- |
15518 |
} |
--- |
| 15519 |
|
--- |
15519 |
|
--- |
| 15520 |
// fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) |
--- |
15520 |
// fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) |
--- |
| 15521 |
if (matcher.match(N0, ISD::FNEG) && isContractableFMUL(N0.getOperand(0)) && |
0 |
15521 |
if (matcher.match(N0, ISD::FNEG) && isContractableFMUL(N0.getOperand(0)) && |
0 |
| 15522 |
(Aggressive || (N0->hasOneUse() && N0.getOperand(0).hasOneUse()))) { |
0 |
15522 |
(Aggressive || (N0->hasOneUse() && N0.getOperand(0).hasOneUse()))) { |
0 |
| 15523 |
SDValue N00 = N0.getOperand(0).getOperand(0); |
0 |
15523 |
SDValue N00 = N0.getOperand(0).getOperand(0); |
0 |
| 15524 |
SDValue N01 = N0.getOperand(0).getOperand(1); |
0 |
15524 |
SDValue N01 = N0.getOperand(0).getOperand(1); |
0 |
| 15525 |
return matcher.getNode(PreferredFusedOpcode, SL, VT, |
0 |
15525 |
return matcher.getNode(PreferredFusedOpcode, SL, VT, |
0 |
| 15526 |
matcher.getNode(ISD::FNEG, SL, VT, N00), N01, |
0 |
15526 |
matcher.getNode(ISD::FNEG, SL, VT, N00), N01, |
0 |
| 15527 |
matcher.getNode(ISD::FNEG, SL, VT, N1)); |
0 |
15527 |
matcher.getNode(ISD::FNEG, SL, VT, N1)); |
0 |
| 15528 |
} |
--- |
15528 |
} |
--- |
| 15529 |
|
--- |
15529 |
|
--- |
| 15530 |
// Look through FP_EXTEND nodes to do more combining. |
--- |
15530 |
// Look through FP_EXTEND nodes to do more combining. |
--- |
| 15531 |
|
--- |
15531 |
|
--- |
| 15532 |
// fold (fsub (fpext (fmul x, y)), z) |
--- |
15532 |
// fold (fsub (fpext (fmul x, y)), z) |
--- |
| 15533 |
// -> (fma (fpext x), (fpext y), (fneg z)) |
--- |
15533 |
// -> (fma (fpext x), (fpext y), (fneg z)) |
--- |
| 15534 |
if (matcher.match(N0, ISD::FP_EXTEND)) { |
0 |
15534 |
if (matcher.match(N0, ISD::FP_EXTEND)) { |
0 |
| 15535 |
SDValue N00 = N0.getOperand(0); |
0 |
15535 |
SDValue N00 = N0.getOperand(0); |
0 |
| 15536 |
if (isContractableFMUL(N00) && |
0 |
15536 |
if (isContractableFMUL(N00) && |
0 |
| 15537 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15537 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15538 |
N00.getValueType())) { |
--- |
15538 |
N00.getValueType())) { |
--- |
| 15539 |
return matcher.getNode( |
0 |
15539 |
return matcher.getNode( |
0 |
| 15540 |
PreferredFusedOpcode, SL, VT, |
--- |
15540 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15541 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)), |
0 |
15541 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)), |
0 |
| 15542 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)), |
0 |
15542 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)), |
0 |
| 15543 |
matcher.getNode(ISD::FNEG, SL, VT, N1)); |
0 |
15543 |
matcher.getNode(ISD::FNEG, SL, VT, N1)); |
0 |
| 15544 |
} |
--- |
15544 |
} |
--- |
| 15545 |
} |
--- |
15545 |
} |
--- |
| 15546 |
|
--- |
15546 |
|
--- |
| 15547 |
// fold (fsub x, (fpext (fmul y, z))) |
--- |
15547 |
// fold (fsub x, (fpext (fmul y, z))) |
--- |
| 15548 |
// -> (fma (fneg (fpext y)), (fpext z), x) |
--- |
15548 |
// -> (fma (fneg (fpext y)), (fpext z), x) |
--- |
| 15549 |
// Note: Commutes FSUB operands. |
--- |
15549 |
// Note: Commutes FSUB operands. |
--- |
| 15550 |
if (matcher.match(N1, ISD::FP_EXTEND)) { |
0 |
15550 |
if (matcher.match(N1, ISD::FP_EXTEND)) { |
0 |
| 15551 |
SDValue N10 = N1.getOperand(0); |
0 |
15551 |
SDValue N10 = N1.getOperand(0); |
0 |
| 15552 |
if (isContractableFMUL(N10) && |
0 |
15552 |
if (isContractableFMUL(N10) && |
0 |
| 15553 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15553 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15554 |
N10.getValueType())) { |
--- |
15554 |
N10.getValueType())) { |
--- |
| 15555 |
return matcher.getNode( |
0 |
15555 |
return matcher.getNode( |
0 |
| 15556 |
PreferredFusedOpcode, SL, VT, |
--- |
15556 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15557 |
matcher.getNode( |
0 |
15557 |
matcher.getNode( |
0 |
| 15558 |
ISD::FNEG, SL, VT, |
0 |
15558 |
ISD::FNEG, SL, VT, |
0 |
| 15559 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(0))), |
0 |
15559 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(0))), |
0 |
| 15560 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(1)), N0); |
0 |
15560 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(1)), N0); |
0 |
| 15561 |
} |
--- |
15561 |
} |
--- |
| 15562 |
} |
--- |
15562 |
} |
--- |
| 15563 |
|
--- |
15563 |
|
--- |
| 15564 |
// fold (fsub (fpext (fneg (fmul, x, y))), z) |
--- |
15564 |
// fold (fsub (fpext (fneg (fmul, x, y))), z) |
--- |
| 15565 |
// -> (fneg (fma (fpext x), (fpext y), z)) |
--- |
15565 |
// -> (fneg (fma (fpext x), (fpext y), z)) |
--- |
| 15566 |
// Note: This could be removed with appropriate canonicalization of the |
--- |
15566 |
// Note: This could be removed with appropriate canonicalization of the |
--- |
| 15567 |
// input expression into (fneg (fadd (fpext (fmul, x, y)), z). However, the |
--- |
15567 |
// input expression into (fneg (fadd (fpext (fmul, x, y)), z). However, the |
--- |
| 15568 |
// orthogonal flags -fp-contract=fast and -enable-unsafe-fp-math prevent |
--- |
15568 |
// orthogonal flags -fp-contract=fast and -enable-unsafe-fp-math prevent |
--- |
| 15569 |
// from implementing the canonicalization in visitFSUB. |
--- |
15569 |
// from implementing the canonicalization in visitFSUB. |
--- |
| 15570 |
if (matcher.match(N0, ISD::FP_EXTEND)) { |
0 |
15570 |
if (matcher.match(N0, ISD::FP_EXTEND)) { |
0 |
| 15571 |
SDValue N00 = N0.getOperand(0); |
0 |
15571 |
SDValue N00 = N0.getOperand(0); |
0 |
| 15572 |
if (matcher.match(N00, ISD::FNEG)) { |
0 |
15572 |
if (matcher.match(N00, ISD::FNEG)) { |
0 |
| 15573 |
SDValue N000 = N00.getOperand(0); |
0 |
15573 |
SDValue N000 = N00.getOperand(0); |
0 |
| 15574 |
if (isContractableFMUL(N000) && |
0 |
15574 |
if (isContractableFMUL(N000) && |
0 |
| 15575 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15575 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15576 |
N00.getValueType())) { |
--- |
15576 |
N00.getValueType())) { |
--- |
| 15577 |
return matcher.getNode( |
0 |
15577 |
return matcher.getNode( |
0 |
| 15578 |
ISD::FNEG, SL, VT, |
0 |
15578 |
ISD::FNEG, SL, VT, |
0 |
| 15579 |
matcher.getNode( |
0 |
15579 |
matcher.getNode( |
0 |
| 15580 |
PreferredFusedOpcode, SL, VT, |
--- |
15580 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15581 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N000.getOperand(0)), |
0 |
15581 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N000.getOperand(0)), |
0 |
| 15582 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N000.getOperand(1)), |
0 |
15582 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N000.getOperand(1)), |
0 |
| 15583 |
N1)); |
0 |
15583 |
N1)); |
0 |
| 15584 |
} |
--- |
15584 |
} |
--- |
| 15585 |
} |
--- |
15585 |
} |
--- |
| 15586 |
} |
--- |
15586 |
} |
--- |
| 15587 |
|
--- |
15587 |
|
--- |
| 15588 |
// fold (fsub (fneg (fpext (fmul, x, y))), z) |
--- |
15588 |
// fold (fsub (fneg (fpext (fmul, x, y))), z) |
--- |
| 15589 |
// -> (fneg (fma (fpext x)), (fpext y), z) |
--- |
15589 |
// -> (fneg (fma (fpext x)), (fpext y), z) |
--- |
| 15590 |
// Note: This could be removed with appropriate canonicalization of the |
--- |
15590 |
// Note: This could be removed with appropriate canonicalization of the |
--- |
| 15591 |
// input expression into (fneg (fadd (fpext (fmul, x, y)), z). However, the |
--- |
15591 |
// input expression into (fneg (fadd (fpext (fmul, x, y)), z). However, the |
--- |
| 15592 |
// orthogonal flags -fp-contract=fast and -enable-unsafe-fp-math prevent |
--- |
15592 |
// orthogonal flags -fp-contract=fast and -enable-unsafe-fp-math prevent |
--- |
| 15593 |
// from implementing the canonicalization in visitFSUB. |
--- |
15593 |
// from implementing the canonicalization in visitFSUB. |
--- |
| 15594 |
if (matcher.match(N0, ISD::FNEG)) { |
0 |
15594 |
if (matcher.match(N0, ISD::FNEG)) { |
0 |
| 15595 |
SDValue N00 = N0.getOperand(0); |
0 |
15595 |
SDValue N00 = N0.getOperand(0); |
0 |
| 15596 |
if (matcher.match(N00, ISD::FP_EXTEND)) { |
0 |
15596 |
if (matcher.match(N00, ISD::FP_EXTEND)) { |
0 |
| 15597 |
SDValue N000 = N00.getOperand(0); |
0 |
15597 |
SDValue N000 = N00.getOperand(0); |
0 |
| 15598 |
if (isContractableFMUL(N000) && |
0 |
15598 |
if (isContractableFMUL(N000) && |
0 |
| 15599 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15599 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15600 |
N000.getValueType())) { |
--- |
15600 |
N000.getValueType())) { |
--- |
| 15601 |
return matcher.getNode( |
0 |
15601 |
return matcher.getNode( |
0 |
| 15602 |
ISD::FNEG, SL, VT, |
0 |
15602 |
ISD::FNEG, SL, VT, |
0 |
| 15603 |
matcher.getNode( |
0 |
15603 |
matcher.getNode( |
0 |
| 15604 |
PreferredFusedOpcode, SL, VT, |
--- |
15604 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15605 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N000.getOperand(0)), |
0 |
15605 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N000.getOperand(0)), |
0 |
| 15606 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N000.getOperand(1)), |
0 |
15606 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N000.getOperand(1)), |
0 |
| 15607 |
N1)); |
0 |
15607 |
N1)); |
0 |
| 15608 |
} |
--- |
15608 |
} |
--- |
| 15609 |
} |
--- |
15609 |
} |
--- |
| 15610 |
} |
--- |
15610 |
} |
--- |
| 15611 |
|
--- |
15611 |
|
--- |
| 15612 |
auto isReassociable = [&Options](SDNode *N) { |
0 |
15612 |
auto isReassociable = [&Options](SDNode *N) { |
0 |
| 15613 |
return Options.UnsafeFPMath || N->getFlags().hasAllowReassociation(); |
0 |
15613 |
return Options.UnsafeFPMath || N->getFlags().hasAllowReassociation(); |
0 |
| 15614 |
}; |
--- |
15614 |
}; |
--- |
| 15615 |
|
--- |
15615 |
|
--- |
| 15616 |
auto isContractableAndReassociableFMUL = [&isContractableFMUL, |
0 |
15616 |
auto isContractableAndReassociableFMUL = [&isContractableFMUL, |
0 |
| 15617 |
&isReassociable](SDValue N) { |
--- |
15617 |
&isReassociable](SDValue N) { |
--- |
| 15618 |
return isContractableFMUL(N) && isReassociable(N.getNode()); |
0 |
15618 |
return isContractableFMUL(N) && isReassociable(N.getNode()); |
0 |
| 15619 |
}; |
--- |
15619 |
}; |
--- |
| 15620 |
|
--- |
15620 |
|
--- |
| 15621 |
auto isFusedOp = [&](SDValue N) { |
0 |
15621 |
auto isFusedOp = [&](SDValue N) { |
0 |
| 15622 |
return matcher.match(N, ISD::FMA) || matcher.match(N, ISD::FMAD); |
0 |
15622 |
return matcher.match(N, ISD::FMA) || matcher.match(N, ISD::FMAD); |
0 |
| 15623 |
}; |
--- |
15623 |
}; |
--- |
| 15624 |
|
--- |
15624 |
|
--- |
| 15625 |
// More folding opportunities when target permits. |
--- |
15625 |
// More folding opportunities when target permits. |
--- |
| 15626 |
if (Aggressive && isReassociable(N)) { |
0 |
15626 |
if (Aggressive && isReassociable(N)) { |
0 |
| 15627 |
bool CanFuse = Options.UnsafeFPMath || N->getFlags().hasAllowContract(); |
0 |
15627 |
bool CanFuse = Options.UnsafeFPMath || N->getFlags().hasAllowContract(); |
0 |
| 15628 |
// fold (fsub (fma x, y, (fmul u, v)), z) |
--- |
15628 |
// fold (fsub (fma x, y, (fmul u, v)), z) |
--- |
| 15629 |
// -> (fma x, y (fma u, v, (fneg z))) |
--- |
15629 |
// -> (fma x, y (fma u, v, (fneg z))) |
--- |
| 15630 |
if (CanFuse && isFusedOp(N0) && |
0 |
15630 |
if (CanFuse && isFusedOp(N0) && |
0 |
| 15631 |
isContractableAndReassociableFMUL(N0.getOperand(2)) && |
0 |
15631 |
isContractableAndReassociableFMUL(N0.getOperand(2)) && |
0 |
| 15632 |
N0->hasOneUse() && N0.getOperand(2)->hasOneUse()) { |
0 |
15632 |
N0->hasOneUse() && N0.getOperand(2)->hasOneUse()) { |
0 |
| 15633 |
return matcher.getNode( |
0 |
15633 |
return matcher.getNode( |
0 |
| 15634 |
PreferredFusedOpcode, SL, VT, N0.getOperand(0), N0.getOperand(1), |
0 |
15634 |
PreferredFusedOpcode, SL, VT, N0.getOperand(0), N0.getOperand(1), |
0 |
| 15635 |
matcher.getNode(PreferredFusedOpcode, SL, VT, |
0 |
15635 |
matcher.getNode(PreferredFusedOpcode, SL, VT, |
0 |
| 15636 |
N0.getOperand(2).getOperand(0), |
0 |
15636 |
N0.getOperand(2).getOperand(0), |
0 |
| 15637 |
N0.getOperand(2).getOperand(1), |
0 |
15637 |
N0.getOperand(2).getOperand(1), |
0 |
| 15638 |
matcher.getNode(ISD::FNEG, SL, VT, N1))); |
0 |
15638 |
matcher.getNode(ISD::FNEG, SL, VT, N1))); |
0 |
| 15639 |
} |
--- |
15639 |
} |
--- |
| 15640 |
|
--- |
15640 |
|
--- |
| 15641 |
// fold (fsub x, (fma y, z, (fmul u, v))) |
--- |
15641 |
// fold (fsub x, (fma y, z, (fmul u, v))) |
--- |
| 15642 |
// -> (fma (fneg y), z, (fma (fneg u), v, x)) |
--- |
15642 |
// -> (fma (fneg y), z, (fma (fneg u), v, x)) |
--- |
| 15643 |
if (CanFuse && isFusedOp(N1) && |
0 |
15643 |
if (CanFuse && isFusedOp(N1) && |
0 |
| 15644 |
isContractableAndReassociableFMUL(N1.getOperand(2)) && |
0 |
15644 |
isContractableAndReassociableFMUL(N1.getOperand(2)) && |
0 |
| 15645 |
N1->hasOneUse() && NoSignedZero) { |
0 |
15645 |
N1->hasOneUse() && NoSignedZero) { |
0 |
| 15646 |
SDValue N20 = N1.getOperand(2).getOperand(0); |
0 |
15646 |
SDValue N20 = N1.getOperand(2).getOperand(0); |
0 |
| 15647 |
SDValue N21 = N1.getOperand(2).getOperand(1); |
0 |
15647 |
SDValue N21 = N1.getOperand(2).getOperand(1); |
0 |
| 15648 |
return matcher.getNode( |
0 |
15648 |
return matcher.getNode( |
0 |
| 15649 |
PreferredFusedOpcode, SL, VT, |
--- |
15649 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15650 |
matcher.getNode(ISD::FNEG, SL, VT, N1.getOperand(0)), |
0 |
15650 |
matcher.getNode(ISD::FNEG, SL, VT, N1.getOperand(0)), |
0 |
| 15651 |
N1.getOperand(1), |
0 |
15651 |
N1.getOperand(1), |
0 |
| 15652 |
matcher.getNode(PreferredFusedOpcode, SL, VT, |
0 |
15652 |
matcher.getNode(PreferredFusedOpcode, SL, VT, |
0 |
| 15653 |
matcher.getNode(ISD::FNEG, SL, VT, N20), N21, N0)); |
0 |
15653 |
matcher.getNode(ISD::FNEG, SL, VT, N20), N21, N0)); |
0 |
| 15654 |
} |
--- |
15654 |
} |
--- |
| 15655 |
|
--- |
15655 |
|
--- |
| 15656 |
// fold (fsub (fma x, y, (fpext (fmul u, v))), z) |
--- |
15656 |
// fold (fsub (fma x, y, (fpext (fmul u, v))), z) |
--- |
| 15657 |
// -> (fma x, y (fma (fpext u), (fpext v), (fneg z))) |
--- |
15657 |
// -> (fma x, y (fma (fpext u), (fpext v), (fneg z))) |
--- |
| 15658 |
if (isFusedOp(N0) && N0->hasOneUse()) { |
0 |
15658 |
if (isFusedOp(N0) && N0->hasOneUse()) { |
0 |
| 15659 |
SDValue N02 = N0.getOperand(2); |
0 |
15659 |
SDValue N02 = N0.getOperand(2); |
0 |
| 15660 |
if (matcher.match(N02, ISD::FP_EXTEND)) { |
0 |
15660 |
if (matcher.match(N02, ISD::FP_EXTEND)) { |
0 |
| 15661 |
SDValue N020 = N02.getOperand(0); |
0 |
15661 |
SDValue N020 = N02.getOperand(0); |
0 |
| 15662 |
if (isContractableAndReassociableFMUL(N020) && |
0 |
15662 |
if (isContractableAndReassociableFMUL(N020) && |
0 |
| 15663 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15663 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15664 |
N020.getValueType())) { |
--- |
15664 |
N020.getValueType())) { |
--- |
| 15665 |
return matcher.getNode( |
0 |
15665 |
return matcher.getNode( |
0 |
| 15666 |
PreferredFusedOpcode, SL, VT, N0.getOperand(0), N0.getOperand(1), |
0 |
15666 |
PreferredFusedOpcode, SL, VT, N0.getOperand(0), N0.getOperand(1), |
0 |
| 15667 |
matcher.getNode( |
0 |
15667 |
matcher.getNode( |
0 |
| 15668 |
PreferredFusedOpcode, SL, VT, |
--- |
15668 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15669 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N020.getOperand(0)), |
0 |
15669 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N020.getOperand(0)), |
0 |
| 15670 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N020.getOperand(1)), |
0 |
15670 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N020.getOperand(1)), |
0 |
| 15671 |
matcher.getNode(ISD::FNEG, SL, VT, N1))); |
0 |
15671 |
matcher.getNode(ISD::FNEG, SL, VT, N1))); |
0 |
| 15672 |
} |
--- |
15672 |
} |
--- |
| 15673 |
} |
--- |
15673 |
} |
--- |
| 15674 |
} |
--- |
15674 |
} |
--- |
| 15675 |
|
--- |
15675 |
|
--- |
| 15676 |
// fold (fsub (fpext (fma x, y, (fmul u, v))), z) |
--- |
15676 |
// fold (fsub (fpext (fma x, y, (fmul u, v))), z) |
--- |
| 15677 |
// -> (fma (fpext x), (fpext y), |
--- |
15677 |
// -> (fma (fpext x), (fpext y), |
--- |
| 15678 |
// (fma (fpext u), (fpext v), (fneg z))) |
--- |
15678 |
// (fma (fpext u), (fpext v), (fneg z))) |
--- |
| 15679 |
// FIXME: This turns two single-precision and one double-precision |
--- |
15679 |
// FIXME: This turns two single-precision and one double-precision |
--- |
| 15680 |
// operation into two double-precision operations, which might not be |
--- |
15680 |
// operation into two double-precision operations, which might not be |
--- |
| 15681 |
// interesting for all targets, especially GPUs. |
--- |
15681 |
// interesting for all targets, especially GPUs. |
--- |
| 15682 |
if (matcher.match(N0, ISD::FP_EXTEND)) { |
0 |
15682 |
if (matcher.match(N0, ISD::FP_EXTEND)) { |
0 |
| 15683 |
SDValue N00 = N0.getOperand(0); |
0 |
15683 |
SDValue N00 = N0.getOperand(0); |
0 |
| 15684 |
if (isFusedOp(N00)) { |
0 |
15684 |
if (isFusedOp(N00)) { |
0 |
| 15685 |
SDValue N002 = N00.getOperand(2); |
0 |
15685 |
SDValue N002 = N00.getOperand(2); |
0 |
| 15686 |
if (isContractableAndReassociableFMUL(N002) && |
0 |
15686 |
if (isContractableAndReassociableFMUL(N002) && |
0 |
| 15687 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15687 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15688 |
N00.getValueType())) { |
--- |
15688 |
N00.getValueType())) { |
--- |
| 15689 |
return matcher.getNode( |
0 |
15689 |
return matcher.getNode( |
0 |
| 15690 |
PreferredFusedOpcode, SL, VT, |
--- |
15690 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15691 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)), |
0 |
15691 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)), |
0 |
| 15692 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)), |
0 |
15692 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)), |
0 |
| 15693 |
matcher.getNode( |
0 |
15693 |
matcher.getNode( |
0 |
| 15694 |
PreferredFusedOpcode, SL, VT, |
--- |
15694 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15695 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N002.getOperand(0)), |
0 |
15695 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N002.getOperand(0)), |
0 |
| 15696 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N002.getOperand(1)), |
0 |
15696 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N002.getOperand(1)), |
0 |
| 15697 |
matcher.getNode(ISD::FNEG, SL, VT, N1))); |
0 |
15697 |
matcher.getNode(ISD::FNEG, SL, VT, N1))); |
0 |
| 15698 |
} |
--- |
15698 |
} |
--- |
| 15699 |
} |
--- |
15699 |
} |
--- |
| 15700 |
} |
--- |
15700 |
} |
--- |
| 15701 |
|
--- |
15701 |
|
--- |
| 15702 |
// fold (fsub x, (fma y, z, (fpext (fmul u, v)))) |
--- |
15702 |
// fold (fsub x, (fma y, z, (fpext (fmul u, v)))) |
--- |
| 15703 |
// -> (fma (fneg y), z, (fma (fneg (fpext u)), (fpext v), x)) |
--- |
15703 |
// -> (fma (fneg y), z, (fma (fneg (fpext u)), (fpext v), x)) |
--- |
| 15704 |
if (isFusedOp(N1) && matcher.match(N1.getOperand(2), ISD::FP_EXTEND) && |
0 |
15704 |
if (isFusedOp(N1) && matcher.match(N1.getOperand(2), ISD::FP_EXTEND) && |
0 |
| 15705 |
N1->hasOneUse()) { |
0 |
15705 |
N1->hasOneUse()) { |
0 |
| 15706 |
SDValue N120 = N1.getOperand(2).getOperand(0); |
0 |
15706 |
SDValue N120 = N1.getOperand(2).getOperand(0); |
0 |
| 15707 |
if (isContractableAndReassociableFMUL(N120) && |
0 |
15707 |
if (isContractableAndReassociableFMUL(N120) && |
0 |
| 15708 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15708 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15709 |
N120.getValueType())) { |
--- |
15709 |
N120.getValueType())) { |
--- |
| 15710 |
SDValue N1200 = N120.getOperand(0); |
0 |
15710 |
SDValue N1200 = N120.getOperand(0); |
0 |
| 15711 |
SDValue N1201 = N120.getOperand(1); |
0 |
15711 |
SDValue N1201 = N120.getOperand(1); |
0 |
| 15712 |
return matcher.getNode( |
0 |
15712 |
return matcher.getNode( |
0 |
| 15713 |
PreferredFusedOpcode, SL, VT, |
--- |
15713 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15714 |
matcher.getNode(ISD::FNEG, SL, VT, N1.getOperand(0)), |
0 |
15714 |
matcher.getNode(ISD::FNEG, SL, VT, N1.getOperand(0)), |
0 |
| 15715 |
N1.getOperand(1), |
0 |
15715 |
N1.getOperand(1), |
0 |
| 15716 |
matcher.getNode( |
0 |
15716 |
matcher.getNode( |
0 |
| 15717 |
PreferredFusedOpcode, SL, VT, |
--- |
15717 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15718 |
matcher.getNode(ISD::FNEG, SL, VT, |
0 |
15718 |
matcher.getNode(ISD::FNEG, SL, VT, |
0 |
| 15719 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N1200)), |
0 |
15719 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N1200)), |
0 |
| 15720 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N1201), N0)); |
0 |
15720 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N1201), N0)); |
0 |
| 15721 |
} |
--- |
15721 |
} |
--- |
| 15722 |
} |
--- |
15722 |
} |
--- |
| 15723 |
|
--- |
15723 |
|
--- |
| 15724 |
// fold (fsub x, (fpext (fma y, z, (fmul u, v)))) |
--- |
15724 |
// fold (fsub x, (fpext (fma y, z, (fmul u, v)))) |
--- |
| 15725 |
// -> (fma (fneg (fpext y)), (fpext z), |
--- |
15725 |
// -> (fma (fneg (fpext y)), (fpext z), |
--- |
| 15726 |
// (fma (fneg (fpext u)), (fpext v), x)) |
--- |
15726 |
// (fma (fneg (fpext u)), (fpext v), x)) |
--- |
| 15727 |
// FIXME: This turns two single-precision and one double-precision |
--- |
15727 |
// FIXME: This turns two single-precision and one double-precision |
--- |
| 15728 |
// operation into two double-precision operations, which might not be |
--- |
15728 |
// operation into two double-precision operations, which might not be |
--- |
| 15729 |
// interesting for all targets, especially GPUs. |
--- |
15729 |
// interesting for all targets, especially GPUs. |
--- |
| 15730 |
if (matcher.match(N1, ISD::FP_EXTEND) && isFusedOp(N1.getOperand(0))) { |
0 |
15730 |
if (matcher.match(N1, ISD::FP_EXTEND) && isFusedOp(N1.getOperand(0))) { |
0 |
| 15731 |
SDValue CvtSrc = N1.getOperand(0); |
0 |
15731 |
SDValue CvtSrc = N1.getOperand(0); |
0 |
| 15732 |
SDValue N100 = CvtSrc.getOperand(0); |
0 |
15732 |
SDValue N100 = CvtSrc.getOperand(0); |
0 |
| 15733 |
SDValue N101 = CvtSrc.getOperand(1); |
0 |
15733 |
SDValue N101 = CvtSrc.getOperand(1); |
0 |
| 15734 |
SDValue N102 = CvtSrc.getOperand(2); |
0 |
15734 |
SDValue N102 = CvtSrc.getOperand(2); |
0 |
| 15735 |
if (isContractableAndReassociableFMUL(N102) && |
0 |
15735 |
if (isContractableAndReassociableFMUL(N102) && |
0 |
| 15736 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
15736 |
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT, |
0 |
| 15737 |
CvtSrc.getValueType())) { |
--- |
15737 |
CvtSrc.getValueType())) { |
--- |
| 15738 |
SDValue N1020 = N102.getOperand(0); |
0 |
15738 |
SDValue N1020 = N102.getOperand(0); |
0 |
| 15739 |
SDValue N1021 = N102.getOperand(1); |
0 |
15739 |
SDValue N1021 = N102.getOperand(1); |
0 |
| 15740 |
return matcher.getNode( |
0 |
15740 |
return matcher.getNode( |
0 |
| 15741 |
PreferredFusedOpcode, SL, VT, |
--- |
15741 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15742 |
matcher.getNode(ISD::FNEG, SL, VT, |
0 |
15742 |
matcher.getNode(ISD::FNEG, SL, VT, |
0 |
| 15743 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N100)), |
0 |
15743 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N100)), |
0 |
| 15744 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N101), |
0 |
15744 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N101), |
0 |
| 15745 |
matcher.getNode( |
0 |
15745 |
matcher.getNode( |
0 |
| 15746 |
PreferredFusedOpcode, SL, VT, |
--- |
15746 |
PreferredFusedOpcode, SL, VT, |
--- |
| 15747 |
matcher.getNode(ISD::FNEG, SL, VT, |
0 |
15747 |
matcher.getNode(ISD::FNEG, SL, VT, |
0 |
| 15748 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N1020)), |
0 |
15748 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N1020)), |
0 |
| 15749 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N1021), N0)); |
0 |
15749 |
matcher.getNode(ISD::FP_EXTEND, SL, VT, N1021), N0)); |
0 |
| 15750 |
} |
--- |
15750 |
} |
--- |
| 15751 |
} |
--- |
15751 |
} |
--- |
| 15752 |
} |
--- |
15752 |
} |
--- |
| 15753 |
|
--- |
15753 |
|
--- |
| 15754 |
return SDValue(); |
0 |
15754 |
return SDValue(); |
0 |
| 15755 |
} |
0 |
15755 |
} |
0 |
| 15756 |
|
--- |
15756 |
|
--- |
| 15757 |
/// Try to perform FMA combining on a given FMUL node based on the distributive |
--- |
15757 |
/// Try to perform FMA combining on a given FMUL node based on the distributive |
--- |
| 15758 |
/// law x * (y + 1) = x * y + x and variants thereof (commuted versions, |
--- |
15758 |
/// law x * (y + 1) = x * y + x and variants thereof (commuted versions, |
--- |
| 15759 |
/// subtraction instead of addition). |
--- |
15759 |
/// subtraction instead of addition). |
--- |
| 15760 |
SDValue DAGCombiner::visitFMULForFMADistributiveCombine(SDNode *N) { |
0 |
15760 |
SDValue DAGCombiner::visitFMULForFMADistributiveCombine(SDNode *N) { |
0 |
| 15761 |
SDValue N0 = N->getOperand(0); |
0 |
15761 |
SDValue N0 = N->getOperand(0); |
0 |
| 15762 |
SDValue N1 = N->getOperand(1); |
0 |
15762 |
SDValue N1 = N->getOperand(1); |
0 |
| 15763 |
EVT VT = N->getValueType(0); |
0 |
15763 |
EVT VT = N->getValueType(0); |
0 |
| 15764 |
SDLoc SL(N); |
0 |
15764 |
SDLoc SL(N); |
0 |
| 15765 |
|
--- |
15765 |
|
--- |
| 15766 |
assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation"); |
0 |
15766 |
assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation"); |
0 |
| 15767 |
|
--- |
15767 |
|
--- |
| 15768 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
15768 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
| 15769 |
|
--- |
15769 |
|
--- |
| 15770 |
// The transforms below are incorrect when x == 0 and y == inf, because the |
--- |
15770 |
// The transforms below are incorrect when x == 0 and y == inf, because the |
--- |
| 15771 |
// intermediate multiplication produces a nan. |
--- |
15771 |
// intermediate multiplication produces a nan. |
--- |
| 15772 |
SDValue FAdd = N0.getOpcode() == ISD::FADD ? N0 : N1; |
0 |
15772 |
SDValue FAdd = N0.getOpcode() == ISD::FADD ? N0 : N1; |
0 |
| 15773 |
if (!hasNoInfs(Options, FAdd)) |
0 |
15773 |
if (!hasNoInfs(Options, FAdd)) |
0 |
| 15774 |
return SDValue(); |
0 |
15774 |
return SDValue(); |
0 |
| 15775 |
|
--- |
15775 |
|
--- |
| 15776 |
// Floating-point multiply-add without intermediate rounding. |
--- |
15776 |
// Floating-point multiply-add without intermediate rounding. |
--- |
| 15777 |
bool HasFMA = |
--- |
15777 |
bool HasFMA = |
--- |
| 15778 |
isContractableFMUL(Options, SDValue(N, 0)) && |
0 |
15778 |
isContractableFMUL(Options, SDValue(N, 0)) && |
0 |
| 15779 |
TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT) && |
0 |
15779 |
TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT) && |
0 |
| 15780 |
(!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT)); |
0 |
15780 |
(!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT)); |
0 |
| 15781 |
|
--- |
15781 |
|
--- |
| 15782 |
// Floating-point multiply-add with intermediate rounding. This can result |
--- |
15782 |
// Floating-point multiply-add with intermediate rounding. This can result |
--- |
| 15783 |
// in a less precise result due to the changed rounding order. |
--- |
15783 |
// in a less precise result due to the changed rounding order. |
--- |
| 15784 |
bool HasFMAD = Options.UnsafeFPMath && |
0 |
15784 |
bool HasFMAD = Options.UnsafeFPMath && |
0 |
| 15785 |
(LegalOperations && TLI.isFMADLegal(DAG, N)); |
0 |
15785 |
(LegalOperations && TLI.isFMADLegal(DAG, N)); |
0 |
| 15786 |
|
--- |
15786 |
|
--- |
| 15787 |
// No valid opcode, do not combine. |
--- |
15787 |
// No valid opcode, do not combine. |
--- |
| 15788 |
if (!HasFMAD && !HasFMA) |
0 |
15788 |
if (!HasFMAD && !HasFMA) |
0 |
| 15789 |
return SDValue(); |
0 |
15789 |
return SDValue(); |
0 |
| 15790 |
|
--- |
15790 |
|
--- |
| 15791 |
// Always prefer FMAD to FMA for precision. |
--- |
15791 |
// Always prefer FMAD to FMA for precision. |
--- |
| 15792 |
unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; |
0 |
15792 |
unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; |
0 |
| 15793 |
bool Aggressive = TLI.enableAggressiveFMAFusion(VT); |
0 |
15793 |
bool Aggressive = TLI.enableAggressiveFMAFusion(VT); |
0 |
| 15794 |
|
--- |
15794 |
|
--- |
| 15795 |
// fold (fmul (fadd x0, +1.0), y) -> (fma x0, y, y) |
--- |
15795 |
// fold (fmul (fadd x0, +1.0), y) -> (fma x0, y, y) |
--- |
| 15796 |
// fold (fmul (fadd x0, -1.0), y) -> (fma x0, y, (fneg y)) |
--- |
15796 |
// fold (fmul (fadd x0, -1.0), y) -> (fma x0, y, (fneg y)) |
--- |
| 15797 |
auto FuseFADD = [&](SDValue X, SDValue Y) { |
0 |
15797 |
auto FuseFADD = [&](SDValue X, SDValue Y) { |
0 |
| 15798 |
if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { |
0 |
15798 |
if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { |
0 |
| 15799 |
if (auto *C = isConstOrConstSplatFP(X.getOperand(1), true)) { |
0 |
15799 |
if (auto *C = isConstOrConstSplatFP(X.getOperand(1), true)) { |
0 |
| 15800 |
if (C->isExactlyValue(+1.0)) |
0 |
15800 |
if (C->isExactlyValue(+1.0)) |
0 |
| 15801 |
return DAG.getNode(PreferredFusedOpcode, SL, VT, X.getOperand(0), Y, |
0 |
15801 |
return DAG.getNode(PreferredFusedOpcode, SL, VT, X.getOperand(0), Y, |
0 |
| 15802 |
Y); |
0 |
15802 |
Y); |
0 |
| 15803 |
if (C->isExactlyValue(-1.0)) |
0 |
15803 |
if (C->isExactlyValue(-1.0)) |
0 |
| 15804 |
return DAG.getNode(PreferredFusedOpcode, SL, VT, X.getOperand(0), Y, |
0 |
15804 |
return DAG.getNode(PreferredFusedOpcode, SL, VT, X.getOperand(0), Y, |
0 |
| 15805 |
DAG.getNode(ISD::FNEG, SL, VT, Y)); |
0 |
15805 |
DAG.getNode(ISD::FNEG, SL, VT, Y)); |
0 |
| 15806 |
} |
--- |
15806 |
} |
--- |
| 15807 |
} |
--- |
15807 |
} |
--- |
| 15808 |
return SDValue(); |
0 |
15808 |
return SDValue(); |
0 |
| 15809 |
}; |
0 |
15809 |
}; |
0 |
| 15810 |
|
--- |
15810 |
|
--- |
| 15811 |
if (SDValue FMA = FuseFADD(N0, N1)) |
0 |
15811 |
if (SDValue FMA = FuseFADD(N0, N1)) |
0 |
| 15812 |
return FMA; |
0 |
15812 |
return FMA; |
0 |
| 15813 |
if (SDValue FMA = FuseFADD(N1, N0)) |
0 |
15813 |
if (SDValue FMA = FuseFADD(N1, N0)) |
0 |
| 15814 |
return FMA; |
0 |
15814 |
return FMA; |
0 |
| 15815 |
|
--- |
15815 |
|
--- |
| 15816 |
// fold (fmul (fsub +1.0, x1), y) -> (fma (fneg x1), y, y) |
--- |
15816 |
// fold (fmul (fsub +1.0, x1), y) -> (fma (fneg x1), y, y) |
--- |
| 15817 |
// fold (fmul (fsub -1.0, x1), y) -> (fma (fneg x1), y, (fneg y)) |
--- |
15817 |
// fold (fmul (fsub -1.0, x1), y) -> (fma (fneg x1), y, (fneg y)) |
--- |
| 15818 |
// fold (fmul (fsub x0, +1.0), y) -> (fma x0, y, (fneg y)) |
--- |
15818 |
// fold (fmul (fsub x0, +1.0), y) -> (fma x0, y, (fneg y)) |
--- |
| 15819 |
// fold (fmul (fsub x0, -1.0), y) -> (fma x0, y, y) |
--- |
15819 |
// fold (fmul (fsub x0, -1.0), y) -> (fma x0, y, y) |
--- |
| 15820 |
auto FuseFSUB = [&](SDValue X, SDValue Y) { |
0 |
15820 |
auto FuseFSUB = [&](SDValue X, SDValue Y) { |
0 |
| 15821 |
if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) { |
0 |
15821 |
if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) { |
0 |
| 15822 |
if (auto *C0 = isConstOrConstSplatFP(X.getOperand(0), true)) { |
0 |
15822 |
if (auto *C0 = isConstOrConstSplatFP(X.getOperand(0), true)) { |
0 |
| 15823 |
if (C0->isExactlyValue(+1.0)) |
0 |
15823 |
if (C0->isExactlyValue(+1.0)) |
0 |
| 15824 |
return DAG.getNode(PreferredFusedOpcode, SL, VT, |
0 |
15824 |
return DAG.getNode(PreferredFusedOpcode, SL, VT, |
0 |
| 15825 |
DAG.getNode(ISD::FNEG, SL, VT, X.getOperand(1)), Y, |
0 |
15825 |
DAG.getNode(ISD::FNEG, SL, VT, X.getOperand(1)), Y, |
0 |
| 15826 |
Y); |
0 |
15826 |
Y); |
0 |
| 15827 |
if (C0->isExactlyValue(-1.0)) |
0 |
15827 |
if (C0->isExactlyValue(-1.0)) |
0 |
| 15828 |
return DAG.getNode(PreferredFusedOpcode, SL, VT, |
0 |
15828 |
return DAG.getNode(PreferredFusedOpcode, SL, VT, |
0 |
| 15829 |
DAG.getNode(ISD::FNEG, SL, VT, X.getOperand(1)), Y, |
0 |
15829 |
DAG.getNode(ISD::FNEG, SL, VT, X.getOperand(1)), Y, |
0 |
| 15830 |
DAG.getNode(ISD::FNEG, SL, VT, Y)); |
0 |
15830 |
DAG.getNode(ISD::FNEG, SL, VT, Y)); |
0 |
| 15831 |
} |
--- |
15831 |
} |
--- |
| 15832 |
if (auto *C1 = isConstOrConstSplatFP(X.getOperand(1), true)) { |
0 |
15832 |
if (auto *C1 = isConstOrConstSplatFP(X.getOperand(1), true)) { |
0 |
| 15833 |
if (C1->isExactlyValue(+1.0)) |
0 |
15833 |
if (C1->isExactlyValue(+1.0)) |
0 |
| 15834 |
return DAG.getNode(PreferredFusedOpcode, SL, VT, X.getOperand(0), Y, |
0 |
15834 |
return DAG.getNode(PreferredFusedOpcode, SL, VT, X.getOperand(0), Y, |
0 |
| 15835 |
DAG.getNode(ISD::FNEG, SL, VT, Y)); |
0 |
15835 |
DAG.getNode(ISD::FNEG, SL, VT, Y)); |
0 |
| 15836 |
if (C1->isExactlyValue(-1.0)) |
0 |
15836 |
if (C1->isExactlyValue(-1.0)) |
0 |
| 15837 |
return DAG.getNode(PreferredFusedOpcode, SL, VT, X.getOperand(0), Y, |
0 |
15837 |
return DAG.getNode(PreferredFusedOpcode, SL, VT, X.getOperand(0), Y, |
0 |
| 15838 |
Y); |
0 |
15838 |
Y); |
0 |
| 15839 |
} |
--- |
15839 |
} |
--- |
| 15840 |
} |
--- |
15840 |
} |
--- |
| 15841 |
return SDValue(); |
0 |
15841 |
return SDValue(); |
0 |
| 15842 |
}; |
0 |
15842 |
}; |
0 |
| 15843 |
|
--- |
15843 |
|
--- |
| 15844 |
if (SDValue FMA = FuseFSUB(N0, N1)) |
0 |
15844 |
if (SDValue FMA = FuseFSUB(N0, N1)) |
0 |
| 15845 |
return FMA; |
0 |
15845 |
return FMA; |
0 |
| 15846 |
if (SDValue FMA = FuseFSUB(N1, N0)) |
0 |
15846 |
if (SDValue FMA = FuseFSUB(N1, N0)) |
0 |
| 15847 |
return FMA; |
0 |
15847 |
return FMA; |
0 |
| 15848 |
|
--- |
15848 |
|
--- |
| 15849 |
return SDValue(); |
0 |
15849 |
return SDValue(); |
0 |
| 15850 |
} |
0 |
15850 |
} |
0 |
| 15851 |
|
--- |
15851 |
|
--- |
| 15852 |
SDValue DAGCombiner::visitVP_FADD(SDNode *N) { |
0 |
15852 |
SDValue DAGCombiner::visitVP_FADD(SDNode *N) { |
0 |
| 15853 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
15853 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
| 15854 |
|
--- |
15854 |
|
--- |
| 15855 |
// FADD -> FMA combines: |
--- |
15855 |
// FADD -> FMA combines: |
--- |
| 15856 |
if (SDValue Fused = visitFADDForFMACombine(N)) { |
0 |
15856 |
if (SDValue Fused = visitFADDForFMACombine(N)) { |
0 |
| 15857 |
AddToWorklist(Fused.getNode()); |
0 |
15857 |
AddToWorklist(Fused.getNode()); |
0 |
| 15858 |
return Fused; |
0 |
15858 |
return Fused; |
0 |
| 15859 |
} |
--- |
15859 |
} |
--- |
| 15860 |
return SDValue(); |
0 |
15860 |
return SDValue(); |
0 |
| 15861 |
} |
0 |
15861 |
} |
0 |
| 15862 |
|
--- |
15862 |
|
--- |
| 15863 |
SDValue DAGCombiner::visitFADD(SDNode *N) { |
0 |
15863 |
SDValue DAGCombiner::visitFADD(SDNode *N) { |
0 |
| 15864 |
SDValue N0 = N->getOperand(0); |
0 |
15864 |
SDValue N0 = N->getOperand(0); |
0 |
| 15865 |
SDValue N1 = N->getOperand(1); |
0 |
15865 |
SDValue N1 = N->getOperand(1); |
0 |
| 15866 |
SDNode *N0CFP = DAG.isConstantFPBuildVectorOrConstantFP(N0); |
0 |
15866 |
SDNode *N0CFP = DAG.isConstantFPBuildVectorOrConstantFP(N0); |
0 |
| 15867 |
SDNode *N1CFP = DAG.isConstantFPBuildVectorOrConstantFP(N1); |
0 |
15867 |
SDNode *N1CFP = DAG.isConstantFPBuildVectorOrConstantFP(N1); |
0 |
| 15868 |
EVT VT = N->getValueType(0); |
0 |
15868 |
EVT VT = N->getValueType(0); |
0 |
| 15869 |
SDLoc DL(N); |
0 |
15869 |
SDLoc DL(N); |
0 |
| 15870 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
15870 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
| 15871 |
SDNodeFlags Flags = N->getFlags(); |
0 |
15871 |
SDNodeFlags Flags = N->getFlags(); |
0 |
| 15872 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
15872 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
| 15873 |
|
--- |
15873 |
|
--- |
| 15874 |
if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) |
0 |
15874 |
if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) |
0 |
| 15875 |
return R; |
0 |
15875 |
return R; |
0 |
| 15876 |
|
--- |
15876 |
|
--- |
| 15877 |
// fold (fadd c1, c2) -> c1 + c2 |
--- |
15877 |
// fold (fadd c1, c2) -> c1 + c2 |
--- |
| 15878 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FADD, DL, VT, {N0, N1})) |
0 |
15878 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FADD, DL, VT, {N0, N1})) |
0 |
| 15879 |
return C; |
0 |
15879 |
return C; |
0 |
| 15880 |
|
--- |
15880 |
|
--- |
| 15881 |
// canonicalize constant to RHS |
--- |
15881 |
// canonicalize constant to RHS |
--- |
| 15882 |
if (N0CFP && !N1CFP) |
0 |
15882 |
if (N0CFP && !N1CFP) |
0 |
| 15883 |
return DAG.getNode(ISD::FADD, DL, VT, N1, N0); |
0 |
15883 |
return DAG.getNode(ISD::FADD, DL, VT, N1, N0); |
0 |
| 15884 |
|
--- |
15884 |
|
--- |
| 15885 |
// fold vector ops |
--- |
15885 |
// fold vector ops |
--- |
| 15886 |
if (VT.isVector()) |
0 |
15886 |
if (VT.isVector()) |
0 |
| 15887 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
15887 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 15888 |
return FoldedVOp; |
0 |
15888 |
return FoldedVOp; |
0 |
| 15889 |
|
--- |
15889 |
|
--- |
| 15890 |
// N0 + -0.0 --> N0 (also allowed with +0.0 and fast-math) |
--- |
15890 |
// N0 + -0.0 --> N0 (also allowed with +0.0 and fast-math) |
--- |
| 15891 |
ConstantFPSDNode *N1C = isConstOrConstSplatFP(N1, true); |
0 |
15891 |
ConstantFPSDNode *N1C = isConstOrConstSplatFP(N1, true); |
0 |
| 15892 |
if (N1C && N1C->isZero()) |
0 |
15892 |
if (N1C && N1C->isZero()) |
0 |
| 15893 |
if (N1C->isNegative() || Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) |
0 |
15893 |
if (N1C->isNegative() || Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) |
0 |
| 15894 |
return N0; |
0 |
15894 |
return N0; |
0 |
| 15895 |
|
--- |
15895 |
|
--- |
| 15896 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
15896 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 15897 |
return NewSel; |
0 |
15897 |
return NewSel; |
0 |
| 15898 |
|
--- |
15898 |
|
--- |
| 15899 |
// fold (fadd A, (fneg B)) -> (fsub A, B) |
--- |
15899 |
// fold (fadd A, (fneg B)) -> (fsub A, B) |
--- |
| 15900 |
if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) |
0 |
15900 |
if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) |
0 |
| 15901 |
if (SDValue NegN1 = TLI.getCheaperNegatedExpression( |
0 |
15901 |
if (SDValue NegN1 = TLI.getCheaperNegatedExpression( |
0 |
| 15902 |
N1, DAG, LegalOperations, ForCodeSize)) |
0 |
15902 |
N1, DAG, LegalOperations, ForCodeSize)) |
0 |
| 15903 |
return DAG.getNode(ISD::FSUB, DL, VT, N0, NegN1); |
0 |
15903 |
return DAG.getNode(ISD::FSUB, DL, VT, N0, NegN1); |
0 |
| 15904 |
|
--- |
15904 |
|
--- |
| 15905 |
// fold (fadd (fneg A), B) -> (fsub B, A) |
--- |
15905 |
// fold (fadd (fneg A), B) -> (fsub B, A) |
--- |
| 15906 |
if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) |
0 |
15906 |
if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) |
0 |
| 15907 |
if (SDValue NegN0 = TLI.getCheaperNegatedExpression( |
0 |
15907 |
if (SDValue NegN0 = TLI.getCheaperNegatedExpression( |
0 |
| 15908 |
N0, DAG, LegalOperations, ForCodeSize)) |
0 |
15908 |
N0, DAG, LegalOperations, ForCodeSize)) |
0 |
| 15909 |
return DAG.getNode(ISD::FSUB, DL, VT, N1, NegN0); |
0 |
15909 |
return DAG.getNode(ISD::FSUB, DL, VT, N1, NegN0); |
0 |
| 15910 |
|
--- |
15910 |
|
--- |
| 15911 |
auto isFMulNegTwo = [](SDValue FMul) { |
0 |
15911 |
auto isFMulNegTwo = [](SDValue FMul) { |
0 |
| 15912 |
if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL) |
0 |
15912 |
if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL) |
0 |
| 15913 |
return false; |
0 |
15913 |
return false; |
0 |
| 15914 |
auto *C = isConstOrConstSplatFP(FMul.getOperand(1), true); |
0 |
15914 |
auto *C = isConstOrConstSplatFP(FMul.getOperand(1), true); |
0 |
| 15915 |
return C && C->isExactlyValue(-2.0); |
0 |
15915 |
return C && C->isExactlyValue(-2.0); |
0 |
| 15916 |
}; |
--- |
15916 |
}; |
--- |
| 15917 |
|
--- |
15917 |
|
--- |
| 15918 |
// fadd (fmul B, -2.0), A --> fsub A, (fadd B, B) |
--- |
15918 |
// fadd (fmul B, -2.0), A --> fsub A, (fadd B, B) |
--- |
| 15919 |
if (isFMulNegTwo(N0)) { |
0 |
15919 |
if (isFMulNegTwo(N0)) { |
0 |
| 15920 |
SDValue B = N0.getOperand(0); |
0 |
15920 |
SDValue B = N0.getOperand(0); |
0 |
| 15921 |
SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B); |
0 |
15921 |
SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B); |
0 |
| 15922 |
return DAG.getNode(ISD::FSUB, DL, VT, N1, Add); |
0 |
15922 |
return DAG.getNode(ISD::FSUB, DL, VT, N1, Add); |
0 |
| 15923 |
} |
--- |
15923 |
} |
--- |
| 15924 |
// fadd A, (fmul B, -2.0) --> fsub A, (fadd B, B) |
--- |
15924 |
// fadd A, (fmul B, -2.0) --> fsub A, (fadd B, B) |
--- |
| 15925 |
if (isFMulNegTwo(N1)) { |
0 |
15925 |
if (isFMulNegTwo(N1)) { |
0 |
| 15926 |
SDValue B = N1.getOperand(0); |
0 |
15926 |
SDValue B = N1.getOperand(0); |
0 |
| 15927 |
SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B); |
0 |
15927 |
SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B); |
0 |
| 15928 |
return DAG.getNode(ISD::FSUB, DL, VT, N0, Add); |
0 |
15928 |
return DAG.getNode(ISD::FSUB, DL, VT, N0, Add); |
0 |
| 15929 |
} |
--- |
15929 |
} |
--- |
| 15930 |
|
--- |
15930 |
|
--- |
| 15931 |
// No FP constant should be created after legalization as Instruction |
--- |
15931 |
// No FP constant should be created after legalization as Instruction |
--- |
| 15932 |
// Selection pass has a hard time dealing with FP constants. |
--- |
15932 |
// Selection pass has a hard time dealing with FP constants. |
--- |
| 15933 |
bool AllowNewConst = (Level < AfterLegalizeDAG); |
0 |
15933 |
bool AllowNewConst = (Level < AfterLegalizeDAG); |
0 |
| 15934 |
|
--- |
15934 |
|
--- |
| 15935 |
// If nnan is enabled, fold lots of things. |
--- |
15935 |
// If nnan is enabled, fold lots of things. |
--- |
| 15936 |
if ((Options.NoNaNsFPMath || Flags.hasNoNaNs()) && AllowNewConst) { |
0 |
15936 |
if ((Options.NoNaNsFPMath || Flags.hasNoNaNs()) && AllowNewConst) { |
0 |
| 15937 |
// If allowed, fold (fadd (fneg x), x) -> 0.0 |
--- |
15937 |
// If allowed, fold (fadd (fneg x), x) -> 0.0 |
--- |
| 15938 |
if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) |
0 |
15938 |
if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) |
0 |
| 15939 |
return DAG.getConstantFP(0.0, DL, VT); |
0 |
15939 |
return DAG.getConstantFP(0.0, DL, VT); |
0 |
| 15940 |
|
--- |
15940 |
|
--- |
| 15941 |
// If allowed, fold (fadd x, (fneg x)) -> 0.0 |
--- |
15941 |
// If allowed, fold (fadd x, (fneg x)) -> 0.0 |
--- |
| 15942 |
if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) |
0 |
15942 |
if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) |
0 |
| 15943 |
return DAG.getConstantFP(0.0, DL, VT); |
0 |
15943 |
return DAG.getConstantFP(0.0, DL, VT); |
0 |
| 15944 |
} |
--- |
15944 |
} |
--- |
| 15945 |
|
--- |
15945 |
|
--- |
| 15946 |
// If 'unsafe math' or reassoc and nsz, fold lots of things. |
--- |
15946 |
// If 'unsafe math' or reassoc and nsz, fold lots of things. |
--- |
| 15947 |
// TODO: break out portions of the transformations below for which Unsafe is |
--- |
15947 |
// TODO: break out portions of the transformations below for which Unsafe is |
--- |
| 15948 |
// considered and which do not require both nsz and reassoc |
--- |
15948 |
// considered and which do not require both nsz and reassoc |
--- |
| 15949 |
if (((Options.UnsafeFPMath && Options.NoSignedZerosFPMath) || |
0 |
15949 |
if (((Options.UnsafeFPMath && Options.NoSignedZerosFPMath) || |
0 |
| 15950 |
(Flags.hasAllowReassociation() && Flags.hasNoSignedZeros())) && |
0 |
15950 |
(Flags.hasAllowReassociation() && Flags.hasNoSignedZeros())) && |
0 |
| 15951 |
AllowNewConst) { |
--- |
15951 |
AllowNewConst) { |
--- |
| 15952 |
// fadd (fadd x, c1), c2 -> fadd x, c1 + c2 |
--- |
15952 |
// fadd (fadd x, c1), c2 -> fadd x, c1 + c2 |
--- |
| 15953 |
if (N1CFP && N0.getOpcode() == ISD::FADD && |
0 |
15953 |
if (N1CFP && N0.getOpcode() == ISD::FADD && |
0 |
| 15954 |
DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(1))) { |
0 |
15954 |
DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(1))) { |
0 |
| 15955 |
SDValue NewC = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), N1); |
0 |
15955 |
SDValue NewC = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), N1); |
0 |
| 15956 |
return DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(0), NewC); |
0 |
15956 |
return DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(0), NewC); |
0 |
| 15957 |
} |
--- |
15957 |
} |
--- |
| 15958 |
|
--- |
15958 |
|
--- |
| 15959 |
// We can fold chains of FADD's of the same value into multiplications. |
--- |
15959 |
// We can fold chains of FADD's of the same value into multiplications. |
--- |
| 15960 |
// This transform is not safe in general because we are reducing the number |
--- |
15960 |
// This transform is not safe in general because we are reducing the number |
--- |
| 15961 |
// of rounding steps. |
--- |
15961 |
// of rounding steps. |
--- |
| 15962 |
if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) { |
0 |
15962 |
if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) { |
0 |
| 15963 |
if (N0.getOpcode() == ISD::FMUL) { |
0 |
15963 |
if (N0.getOpcode() == ISD::FMUL) { |
0 |
| 15964 |
SDNode *CFP00 = |
--- |
15964 |
SDNode *CFP00 = |
--- |
| 15965 |
DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(0)); |
0 |
15965 |
DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(0)); |
0 |
| 15966 |
SDNode *CFP01 = |
--- |
15966 |
SDNode *CFP01 = |
--- |
| 15967 |
DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(1)); |
0 |
15967 |
DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(1)); |
0 |
| 15968 |
|
--- |
15968 |
|
--- |
| 15969 |
// (fadd (fmul x, c), x) -> (fmul x, c+1) |
--- |
15969 |
// (fadd (fmul x, c), x) -> (fmul x, c+1) |
--- |
| 15970 |
if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { |
0 |
15970 |
if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { |
0 |
| 15971 |
SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), |
0 |
15971 |
SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), |
0 |
| 15972 |
DAG.getConstantFP(1.0, DL, VT)); |
0 |
15972 |
DAG.getConstantFP(1.0, DL, VT)); |
0 |
| 15973 |
return DAG.getNode(ISD::FMUL, DL, VT, N1, NewCFP); |
0 |
15973 |
return DAG.getNode(ISD::FMUL, DL, VT, N1, NewCFP); |
0 |
| 15974 |
} |
--- |
15974 |
} |
--- |
| 15975 |
|
--- |
15975 |
|
--- |
| 15976 |
// (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2) |
--- |
15976 |
// (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2) |
--- |
| 15977 |
if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && |
0 |
15977 |
if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && |
0 |
| 15978 |
N1.getOperand(0) == N1.getOperand(1) && |
0 |
15978 |
N1.getOperand(0) == N1.getOperand(1) && |
0 |
| 15979 |
N0.getOperand(0) == N1.getOperand(0)) { |
0 |
15979 |
N0.getOperand(0) == N1.getOperand(0)) { |
0 |
| 15980 |
SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), |
0 |
15980 |
SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), |
0 |
| 15981 |
DAG.getConstantFP(2.0, DL, VT)); |
0 |
15981 |
DAG.getConstantFP(2.0, DL, VT)); |
0 |
| 15982 |
return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), NewCFP); |
0 |
15982 |
return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), NewCFP); |
0 |
| 15983 |
} |
--- |
15983 |
} |
--- |
| 15984 |
} |
--- |
15984 |
} |
--- |
| 15985 |
|
--- |
15985 |
|
--- |
| 15986 |
if (N1.getOpcode() == ISD::FMUL) { |
0 |
15986 |
if (N1.getOpcode() == ISD::FMUL) { |
0 |
| 15987 |
SDNode *CFP10 = |
--- |
15987 |
SDNode *CFP10 = |
--- |
| 15988 |
DAG.isConstantFPBuildVectorOrConstantFP(N1.getOperand(0)); |
0 |
15988 |
DAG.isConstantFPBuildVectorOrConstantFP(N1.getOperand(0)); |
0 |
| 15989 |
SDNode *CFP11 = |
--- |
15989 |
SDNode *CFP11 = |
--- |
| 15990 |
DAG.isConstantFPBuildVectorOrConstantFP(N1.getOperand(1)); |
0 |
15990 |
DAG.isConstantFPBuildVectorOrConstantFP(N1.getOperand(1)); |
0 |
| 15991 |
|
--- |
15991 |
|
--- |
| 15992 |
// (fadd x, (fmul x, c)) -> (fmul x, c+1) |
--- |
15992 |
// (fadd x, (fmul x, c)) -> (fmul x, c+1) |
--- |
| 15993 |
if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { |
0 |
15993 |
if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { |
0 |
| 15994 |
SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N1.getOperand(1), |
0 |
15994 |
SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N1.getOperand(1), |
0 |
| 15995 |
DAG.getConstantFP(1.0, DL, VT)); |
0 |
15995 |
DAG.getConstantFP(1.0, DL, VT)); |
0 |
| 15996 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, NewCFP); |
0 |
15996 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, NewCFP); |
0 |
| 15997 |
} |
--- |
15997 |
} |
--- |
| 15998 |
|
--- |
15998 |
|
--- |
| 15999 |
// (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2) |
--- |
15999 |
// (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2) |
--- |
| 16000 |
if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD && |
0 |
16000 |
if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD && |
0 |
| 16001 |
N0.getOperand(0) == N0.getOperand(1) && |
0 |
16001 |
N0.getOperand(0) == N0.getOperand(1) && |
0 |
| 16002 |
N1.getOperand(0) == N0.getOperand(0)) { |
0 |
16002 |
N1.getOperand(0) == N0.getOperand(0)) { |
0 |
| 16003 |
SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N1.getOperand(1), |
0 |
16003 |
SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N1.getOperand(1), |
0 |
| 16004 |
DAG.getConstantFP(2.0, DL, VT)); |
0 |
16004 |
DAG.getConstantFP(2.0, DL, VT)); |
0 |
| 16005 |
return DAG.getNode(ISD::FMUL, DL, VT, N1.getOperand(0), NewCFP); |
0 |
16005 |
return DAG.getNode(ISD::FMUL, DL, VT, N1.getOperand(0), NewCFP); |
0 |
| 16006 |
} |
--- |
16006 |
} |
--- |
| 16007 |
} |
--- |
16007 |
} |
--- |
| 16008 |
|
--- |
16008 |
|
--- |
| 16009 |
if (N0.getOpcode() == ISD::FADD) { |
0 |
16009 |
if (N0.getOpcode() == ISD::FADD) { |
0 |
| 16010 |
SDNode *CFP00 = |
--- |
16010 |
SDNode *CFP00 = |
--- |
| 16011 |
DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(0)); |
0 |
16011 |
DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(0)); |
0 |
| 16012 |
// (fadd (fadd x, x), x) -> (fmul x, 3.0) |
--- |
16012 |
// (fadd (fadd x, x), x) -> (fmul x, 3.0) |
--- |
| 16013 |
if (!CFP00 && N0.getOperand(0) == N0.getOperand(1) && |
0 |
16013 |
if (!CFP00 && N0.getOperand(0) == N0.getOperand(1) && |
0 |
| 16014 |
(N0.getOperand(0) == N1)) { |
0 |
16014 |
(N0.getOperand(0) == N1)) { |
0 |
| 16015 |
return DAG.getNode(ISD::FMUL, DL, VT, N1, |
0 |
16015 |
return DAG.getNode(ISD::FMUL, DL, VT, N1, |
0 |
| 16016 |
DAG.getConstantFP(3.0, DL, VT)); |
0 |
16016 |
DAG.getConstantFP(3.0, DL, VT)); |
0 |
| 16017 |
} |
--- |
16017 |
} |
--- |
| 16018 |
} |
--- |
16018 |
} |
--- |
| 16019 |
|
--- |
16019 |
|
--- |
| 16020 |
if (N1.getOpcode() == ISD::FADD) { |
0 |
16020 |
if (N1.getOpcode() == ISD::FADD) { |
0 |
| 16021 |
SDNode *CFP10 = |
--- |
16021 |
SDNode *CFP10 = |
--- |
| 16022 |
DAG.isConstantFPBuildVectorOrConstantFP(N1.getOperand(0)); |
0 |
16022 |
DAG.isConstantFPBuildVectorOrConstantFP(N1.getOperand(0)); |
0 |
| 16023 |
// (fadd x, (fadd x, x)) -> (fmul x, 3.0) |
--- |
16023 |
// (fadd x, (fadd x, x)) -> (fmul x, 3.0) |
--- |
| 16024 |
if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) && |
0 |
16024 |
if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) && |
0 |
| 16025 |
N1.getOperand(0) == N0) { |
0 |
16025 |
N1.getOperand(0) == N0) { |
0 |
| 16026 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, |
0 |
16026 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, |
0 |
| 16027 |
DAG.getConstantFP(3.0, DL, VT)); |
0 |
16027 |
DAG.getConstantFP(3.0, DL, VT)); |
0 |
| 16028 |
} |
--- |
16028 |
} |
--- |
| 16029 |
} |
--- |
16029 |
} |
--- |
| 16030 |
|
--- |
16030 |
|
--- |
| 16031 |
// (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0) |
--- |
16031 |
// (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0) |
--- |
| 16032 |
if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && |
0 |
16032 |
if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && |
0 |
| 16033 |
N0.getOperand(0) == N0.getOperand(1) && |
0 |
16033 |
N0.getOperand(0) == N0.getOperand(1) && |
0 |
| 16034 |
N1.getOperand(0) == N1.getOperand(1) && |
0 |
16034 |
N1.getOperand(0) == N1.getOperand(1) && |
0 |
| 16035 |
N0.getOperand(0) == N1.getOperand(0)) { |
0 |
16035 |
N0.getOperand(0) == N1.getOperand(0)) { |
0 |
| 16036 |
return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), |
0 |
16036 |
return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), |
0 |
| 16037 |
DAG.getConstantFP(4.0, DL, VT)); |
0 |
16037 |
DAG.getConstantFP(4.0, DL, VT)); |
0 |
| 16038 |
} |
--- |
16038 |
} |
--- |
| 16039 |
} |
--- |
16039 |
} |
--- |
| 16040 |
|
--- |
16040 |
|
--- |
| 16041 |
// Fold fadd(vecreduce(x), vecreduce(y)) -> vecreduce(fadd(x, y)) |
--- |
16041 |
// Fold fadd(vecreduce(x), vecreduce(y)) -> vecreduce(fadd(x, y)) |
--- |
| 16042 |
if (SDValue SD = reassociateReduction(ISD::VECREDUCE_FADD, ISD::FADD, DL, |
0 |
16042 |
if (SDValue SD = reassociateReduction(ISD::VECREDUCE_FADD, ISD::FADD, DL, |
0 |
| 16043 |
VT, N0, N1, Flags)) |
0 |
16043 |
VT, N0, N1, Flags)) |
0 |
| 16044 |
return SD; |
0 |
16044 |
return SD; |
0 |
| 16045 |
} // enable-unsafe-fp-math |
--- |
16045 |
} // enable-unsafe-fp-math |
--- |
| 16046 |
|
--- |
16046 |
|
--- |
| 16047 |
// FADD -> FMA combines: |
--- |
16047 |
// FADD -> FMA combines: |
--- |
| 16048 |
if (SDValue Fused = visitFADDForFMACombine(N)) { |
0 |
16048 |
if (SDValue Fused = visitFADDForFMACombine(N)) { |
0 |
| 16049 |
AddToWorklist(Fused.getNode()); |
0 |
16049 |
AddToWorklist(Fused.getNode()); |
0 |
| 16050 |
return Fused; |
0 |
16050 |
return Fused; |
0 |
| 16051 |
} |
--- |
16051 |
} |
--- |
| 16052 |
return SDValue(); |
0 |
16052 |
return SDValue(); |
0 |
| 16053 |
} |
0 |
16053 |
} |
0 |
| 16054 |
|
--- |
16054 |
|
--- |
| 16055 |
SDValue DAGCombiner::visitSTRICT_FADD(SDNode *N) { |
0 |
16055 |
SDValue DAGCombiner::visitSTRICT_FADD(SDNode *N) { |
0 |
| 16056 |
SDValue Chain = N->getOperand(0); |
0 |
16056 |
SDValue Chain = N->getOperand(0); |
0 |
| 16057 |
SDValue N0 = N->getOperand(1); |
0 |
16057 |
SDValue N0 = N->getOperand(1); |
0 |
| 16058 |
SDValue N1 = N->getOperand(2); |
0 |
16058 |
SDValue N1 = N->getOperand(2); |
0 |
| 16059 |
EVT VT = N->getValueType(0); |
0 |
16059 |
EVT VT = N->getValueType(0); |
0 |
| 16060 |
EVT ChainVT = N->getValueType(1); |
0 |
16060 |
EVT ChainVT = N->getValueType(1); |
0 |
| 16061 |
SDLoc DL(N); |
0 |
16061 |
SDLoc DL(N); |
0 |
| 16062 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
16062 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
| 16063 |
|
--- |
16063 |
|
--- |
| 16064 |
// fold (strict_fadd A, (fneg B)) -> (strict_fsub A, B) |
--- |
16064 |
// fold (strict_fadd A, (fneg B)) -> (strict_fsub A, B) |
--- |
| 16065 |
if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::STRICT_FSUB, VT)) |
0 |
16065 |
if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::STRICT_FSUB, VT)) |
0 |
| 16066 |
if (SDValue NegN1 = TLI.getCheaperNegatedExpression( |
0 |
16066 |
if (SDValue NegN1 = TLI.getCheaperNegatedExpression( |
0 |
| 16067 |
N1, DAG, LegalOperations, ForCodeSize)) { |
0 |
16067 |
N1, DAG, LegalOperations, ForCodeSize)) { |
0 |
| 16068 |
return DAG.getNode(ISD::STRICT_FSUB, DL, DAG.getVTList(VT, ChainVT), |
0 |
16068 |
return DAG.getNode(ISD::STRICT_FSUB, DL, DAG.getVTList(VT, ChainVT), |
0 |
| 16069 |
{Chain, N0, NegN1}); |
0 |
16069 |
{Chain, N0, NegN1}); |
0 |
| 16070 |
} |
--- |
16070 |
} |
--- |
| 16071 |
|
--- |
16071 |
|
--- |
| 16072 |
// fold (strict_fadd (fneg A), B) -> (strict_fsub B, A) |
--- |
16072 |
// fold (strict_fadd (fneg A), B) -> (strict_fsub B, A) |
--- |
| 16073 |
if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::STRICT_FSUB, VT)) |
0 |
16073 |
if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::STRICT_FSUB, VT)) |
0 |
| 16074 |
if (SDValue NegN0 = TLI.getCheaperNegatedExpression( |
0 |
16074 |
if (SDValue NegN0 = TLI.getCheaperNegatedExpression( |
0 |
| 16075 |
N0, DAG, LegalOperations, ForCodeSize)) { |
0 |
16075 |
N0, DAG, LegalOperations, ForCodeSize)) { |
0 |
| 16076 |
return DAG.getNode(ISD::STRICT_FSUB, DL, DAG.getVTList(VT, ChainVT), |
0 |
16076 |
return DAG.getNode(ISD::STRICT_FSUB, DL, DAG.getVTList(VT, ChainVT), |
0 |
| 16077 |
{Chain, N1, NegN0}); |
0 |
16077 |
{Chain, N1, NegN0}); |
0 |
| 16078 |
} |
--- |
16078 |
} |
--- |
| 16079 |
return SDValue(); |
0 |
16079 |
return SDValue(); |
0 |
| 16080 |
} |
0 |
16080 |
} |
0 |
| 16081 |
|
--- |
16081 |
|
--- |
| 16082 |
SDValue DAGCombiner::visitFSUB(SDNode *N) { |
0 |
16082 |
SDValue DAGCombiner::visitFSUB(SDNode *N) { |
0 |
| 16083 |
SDValue N0 = N->getOperand(0); |
0 |
16083 |
SDValue N0 = N->getOperand(0); |
0 |
| 16084 |
SDValue N1 = N->getOperand(1); |
0 |
16084 |
SDValue N1 = N->getOperand(1); |
0 |
| 16085 |
ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, true); |
0 |
16085 |
ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, true); |
0 |
| 16086 |
ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1, true); |
0 |
16086 |
ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1, true); |
0 |
| 16087 |
EVT VT = N->getValueType(0); |
0 |
16087 |
EVT VT = N->getValueType(0); |
0 |
| 16088 |
SDLoc DL(N); |
0 |
16088 |
SDLoc DL(N); |
0 |
| 16089 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
16089 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
| 16090 |
const SDNodeFlags Flags = N->getFlags(); |
0 |
16090 |
const SDNodeFlags Flags = N->getFlags(); |
0 |
| 16091 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
16091 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
| 16092 |
|
--- |
16092 |
|
--- |
| 16093 |
if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) |
0 |
16093 |
if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) |
0 |
| 16094 |
return R; |
0 |
16094 |
return R; |
0 |
| 16095 |
|
--- |
16095 |
|
--- |
| 16096 |
// fold (fsub c1, c2) -> c1-c2 |
--- |
16096 |
// fold (fsub c1, c2) -> c1-c2 |
--- |
| 16097 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FSUB, DL, VT, {N0, N1})) |
0 |
16097 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FSUB, DL, VT, {N0, N1})) |
0 |
| 16098 |
return C; |
0 |
16098 |
return C; |
0 |
| 16099 |
|
--- |
16099 |
|
--- |
| 16100 |
// fold vector ops |
--- |
16100 |
// fold vector ops |
--- |
| 16101 |
if (VT.isVector()) |
0 |
16101 |
if (VT.isVector()) |
0 |
| 16102 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
16102 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 16103 |
return FoldedVOp; |
0 |
16103 |
return FoldedVOp; |
0 |
| 16104 |
|
--- |
16104 |
|
--- |
| 16105 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
16105 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 16106 |
return NewSel; |
0 |
16106 |
return NewSel; |
0 |
| 16107 |
|
--- |
16107 |
|
--- |
| 16108 |
// (fsub A, 0) -> A |
--- |
16108 |
// (fsub A, 0) -> A |
--- |
| 16109 |
if (N1CFP && N1CFP->isZero()) { |
0 |
16109 |
if (N1CFP && N1CFP->isZero()) { |
0 |
| 16110 |
if (!N1CFP->isNegative() || Options.NoSignedZerosFPMath || |
0 |
16110 |
if (!N1CFP->isNegative() || Options.NoSignedZerosFPMath || |
0 |
| 16111 |
Flags.hasNoSignedZeros()) { |
0 |
16111 |
Flags.hasNoSignedZeros()) { |
0 |
| 16112 |
return N0; |
0 |
16112 |
return N0; |
0 |
| 16113 |
} |
--- |
16113 |
} |
--- |
| 16114 |
} |
--- |
16114 |
} |
--- |
| 16115 |
|
--- |
16115 |
|
--- |
| 16116 |
if (N0 == N1) { |
0 |
16116 |
if (N0 == N1) { |
0 |
| 16117 |
// (fsub x, x) -> 0.0 |
--- |
16117 |
// (fsub x, x) -> 0.0 |
--- |
| 16118 |
if (Options.NoNaNsFPMath || Flags.hasNoNaNs()) |
0 |
16118 |
if (Options.NoNaNsFPMath || Flags.hasNoNaNs()) |
0 |
| 16119 |
return DAG.getConstantFP(0.0f, DL, VT); |
0 |
16119 |
return DAG.getConstantFP(0.0f, DL, VT); |
0 |
| 16120 |
} |
--- |
16120 |
} |
--- |
| 16121 |
|
--- |
16121 |
|
--- |
| 16122 |
// (fsub -0.0, N1) -> -N1 |
--- |
16122 |
// (fsub -0.0, N1) -> -N1 |
--- |
| 16123 |
if (N0CFP && N0CFP->isZero()) { |
0 |
16123 |
if (N0CFP && N0CFP->isZero()) { |
0 |
| 16124 |
if (N0CFP->isNegative() || |
0 |
16124 |
if (N0CFP->isNegative() || |
0 |
| 16125 |
(Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros())) { |
0 |
16125 |
(Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros())) { |
0 |
| 16126 |
// We cannot replace an FSUB(+-0.0,X) with FNEG(X) when denormals are |
--- |
16126 |
// We cannot replace an FSUB(+-0.0,X) with FNEG(X) when denormals are |
--- |
| 16127 |
// flushed to zero, unless all users treat denorms as zero (DAZ). |
--- |
16127 |
// flushed to zero, unless all users treat denorms as zero (DAZ). |
--- |
| 16128 |
// FIXME: This transform will change the sign of a NaN and the behavior |
--- |
16128 |
// FIXME: This transform will change the sign of a NaN and the behavior |
--- |
| 16129 |
// of a signaling NaN. It is only valid when a NoNaN flag is present. |
--- |
16129 |
// of a signaling NaN. It is only valid when a NoNaN flag is present. |
--- |
| 16130 |
DenormalMode DenormMode = DAG.getDenormalMode(VT); |
0 |
16130 |
DenormalMode DenormMode = DAG.getDenormalMode(VT); |
0 |
| 16131 |
if (DenormMode == DenormalMode::getIEEE()) { |
0 |
16131 |
if (DenormMode == DenormalMode::getIEEE()) { |
0 |
| 16132 |
if (SDValue NegN1 = |
0 |
16132 |
if (SDValue NegN1 = |
0 |
| 16133 |
TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize)) |
0 |
16133 |
TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize)) |
0 |
| 16134 |
return NegN1; |
0 |
16134 |
return NegN1; |
0 |
| 16135 |
if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) |
0 |
16135 |
if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) |
0 |
| 16136 |
return DAG.getNode(ISD::FNEG, DL, VT, N1); |
0 |
16136 |
return DAG.getNode(ISD::FNEG, DL, VT, N1); |
0 |
| 16137 |
} |
--- |
16137 |
} |
--- |
| 16138 |
} |
--- |
16138 |
} |
--- |
| 16139 |
} |
--- |
16139 |
} |
--- |
| 16140 |
|
--- |
16140 |
|
--- |
| 16141 |
if (((Options.UnsafeFPMath && Options.NoSignedZerosFPMath) || |
0 |
16141 |
if (((Options.UnsafeFPMath && Options.NoSignedZerosFPMath) || |
0 |
| 16142 |
(Flags.hasAllowReassociation() && Flags.hasNoSignedZeros())) && |
0 |
16142 |
(Flags.hasAllowReassociation() && Flags.hasNoSignedZeros())) && |
0 |
| 16143 |
N1.getOpcode() == ISD::FADD) { |
0 |
16143 |
N1.getOpcode() == ISD::FADD) { |
0 |
| 16144 |
// X - (X + Y) -> -Y |
--- |
16144 |
// X - (X + Y) -> -Y |
--- |
| 16145 |
if (N0 == N1->getOperand(0)) |
0 |
16145 |
if (N0 == N1->getOperand(0)) |
0 |
| 16146 |
return DAG.getNode(ISD::FNEG, DL, VT, N1->getOperand(1)); |
0 |
16146 |
return DAG.getNode(ISD::FNEG, DL, VT, N1->getOperand(1)); |
0 |
| 16147 |
// X - (Y + X) -> -Y |
--- |
16147 |
// X - (Y + X) -> -Y |
--- |
| 16148 |
if (N0 == N1->getOperand(1)) |
0 |
16148 |
if (N0 == N1->getOperand(1)) |
0 |
| 16149 |
return DAG.getNode(ISD::FNEG, DL, VT, N1->getOperand(0)); |
0 |
16149 |
return DAG.getNode(ISD::FNEG, DL, VT, N1->getOperand(0)); |
0 |
| 16150 |
} |
--- |
16150 |
} |
--- |
| 16151 |
|
--- |
16151 |
|
--- |
| 16152 |
// fold (fsub A, (fneg B)) -> (fadd A, B) |
--- |
16152 |
// fold (fsub A, (fneg B)) -> (fadd A, B) |
--- |
| 16153 |
if (SDValue NegN1 = |
0 |
16153 |
if (SDValue NegN1 = |
0 |
| 16154 |
TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize)) |
0 |
16154 |
TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize)) |
0 |
| 16155 |
return DAG.getNode(ISD::FADD, DL, VT, N0, NegN1); |
0 |
16155 |
return DAG.getNode(ISD::FADD, DL, VT, N0, NegN1); |
0 |
| 16156 |
|
--- |
16156 |
|
--- |
| 16157 |
// FSUB -> FMA combines: |
--- |
16157 |
// FSUB -> FMA combines: |
--- |
| 16158 |
if (SDValue Fused = visitFSUBForFMACombine(N)) { |
0 |
16158 |
if (SDValue Fused = visitFSUBForFMACombine(N)) { |
0 |
| 16159 |
AddToWorklist(Fused.getNode()); |
0 |
16159 |
AddToWorklist(Fused.getNode()); |
0 |
| 16160 |
return Fused; |
0 |
16160 |
return Fused; |
0 |
| 16161 |
} |
--- |
16161 |
} |
--- |
| 16162 |
|
--- |
16162 |
|
--- |
| 16163 |
return SDValue(); |
0 |
16163 |
return SDValue(); |
0 |
| 16164 |
} |
0 |
16164 |
} |
0 |
| 16165 |
|
--- |
16165 |
|
--- |
| 16166 |
SDValue DAGCombiner::visitFMUL(SDNode *N) { |
0 |
16166 |
SDValue DAGCombiner::visitFMUL(SDNode *N) { |
0 |
| 16167 |
SDValue N0 = N->getOperand(0); |
0 |
16167 |
SDValue N0 = N->getOperand(0); |
0 |
| 16168 |
SDValue N1 = N->getOperand(1); |
0 |
16168 |
SDValue N1 = N->getOperand(1); |
0 |
| 16169 |
ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1, true); |
0 |
16169 |
ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1, true); |
0 |
| 16170 |
EVT VT = N->getValueType(0); |
0 |
16170 |
EVT VT = N->getValueType(0); |
0 |
| 16171 |
SDLoc DL(N); |
0 |
16171 |
SDLoc DL(N); |
0 |
| 16172 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
16172 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
| 16173 |
const SDNodeFlags Flags = N->getFlags(); |
0 |
16173 |
const SDNodeFlags Flags = N->getFlags(); |
0 |
| 16174 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
16174 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
| 16175 |
|
--- |
16175 |
|
--- |
| 16176 |
if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) |
0 |
16176 |
if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) |
0 |
| 16177 |
return R; |
0 |
16177 |
return R; |
0 |
| 16178 |
|
--- |
16178 |
|
--- |
| 16179 |
// fold (fmul c1, c2) -> c1*c2 |
--- |
16179 |
// fold (fmul c1, c2) -> c1*c2 |
--- |
| 16180 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FMUL, DL, VT, {N0, N1})) |
0 |
16180 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FMUL, DL, VT, {N0, N1})) |
0 |
| 16181 |
return C; |
0 |
16181 |
return C; |
0 |
| 16182 |
|
--- |
16182 |
|
--- |
| 16183 |
// canonicalize constant to RHS |
--- |
16183 |
// canonicalize constant to RHS |
--- |
| 16184 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0) && |
0 |
16184 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0) && |
0 |
| 16185 |
!DAG.isConstantFPBuildVectorOrConstantFP(N1)) |
0 |
16185 |
!DAG.isConstantFPBuildVectorOrConstantFP(N1)) |
0 |
| 16186 |
return DAG.getNode(ISD::FMUL, DL, VT, N1, N0); |
0 |
16186 |
return DAG.getNode(ISD::FMUL, DL, VT, N1, N0); |
0 |
| 16187 |
|
--- |
16187 |
|
--- |
| 16188 |
// fold vector ops |
--- |
16188 |
// fold vector ops |
--- |
| 16189 |
if (VT.isVector()) |
0 |
16189 |
if (VT.isVector()) |
0 |
| 16190 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
16190 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 16191 |
return FoldedVOp; |
0 |
16191 |
return FoldedVOp; |
0 |
| 16192 |
|
--- |
16192 |
|
--- |
| 16193 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
16193 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 16194 |
return NewSel; |
0 |
16194 |
return NewSel; |
0 |
| 16195 |
|
--- |
16195 |
|
--- |
| 16196 |
if (Options.UnsafeFPMath || Flags.hasAllowReassociation()) { |
0 |
16196 |
if (Options.UnsafeFPMath || Flags.hasAllowReassociation()) { |
0 |
| 16197 |
// fmul (fmul X, C1), C2 -> fmul X, C1 * C2 |
--- |
16197 |
// fmul (fmul X, C1), C2 -> fmul X, C1 * C2 |
--- |
| 16198 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N1) && |
0 |
16198 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N1) && |
0 |
| 16199 |
N0.getOpcode() == ISD::FMUL) { |
0 |
16199 |
N0.getOpcode() == ISD::FMUL) { |
0 |
| 16200 |
SDValue N00 = N0.getOperand(0); |
0 |
16200 |
SDValue N00 = N0.getOperand(0); |
0 |
| 16201 |
SDValue N01 = N0.getOperand(1); |
0 |
16201 |
SDValue N01 = N0.getOperand(1); |
0 |
| 16202 |
// Avoid an infinite loop by making sure that N00 is not a constant |
--- |
16202 |
// Avoid an infinite loop by making sure that N00 is not a constant |
--- |
| 16203 |
// (the inner multiply has not been constant folded yet). |
--- |
16203 |
// (the inner multiply has not been constant folded yet). |
--- |
| 16204 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N01) && |
0 |
16204 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N01) && |
0 |
| 16205 |
!DAG.isConstantFPBuildVectorOrConstantFP(N00)) { |
0 |
16205 |
!DAG.isConstantFPBuildVectorOrConstantFP(N00)) { |
0 |
| 16206 |
SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, N01, N1); |
0 |
16206 |
SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, N01, N1); |
0 |
| 16207 |
return DAG.getNode(ISD::FMUL, DL, VT, N00, MulConsts); |
0 |
16207 |
return DAG.getNode(ISD::FMUL, DL, VT, N00, MulConsts); |
0 |
| 16208 |
} |
--- |
16208 |
} |
--- |
| 16209 |
} |
--- |
16209 |
} |
--- |
| 16210 |
|
--- |
16210 |
|
--- |
| 16211 |
// Match a special-case: we convert X * 2.0 into fadd. |
--- |
16211 |
// Match a special-case: we convert X * 2.0 into fadd. |
--- |
| 16212 |
// fmul (fadd X, X), C -> fmul X, 2.0 * C |
--- |
16212 |
// fmul (fadd X, X), C -> fmul X, 2.0 * C |
--- |
| 16213 |
if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() && |
0 |
16213 |
if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() && |
0 |
| 16214 |
N0.getOperand(0) == N0.getOperand(1)) { |
0 |
16214 |
N0.getOperand(0) == N0.getOperand(1)) { |
0 |
| 16215 |
const SDValue Two = DAG.getConstantFP(2.0, DL, VT); |
0 |
16215 |
const SDValue Two = DAG.getConstantFP(2.0, DL, VT); |
0 |
| 16216 |
SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, Two, N1); |
0 |
16216 |
SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, Two, N1); |
0 |
| 16217 |
return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), MulConsts); |
0 |
16217 |
return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), MulConsts); |
0 |
| 16218 |
} |
--- |
16218 |
} |
--- |
| 16219 |
|
--- |
16219 |
|
--- |
| 16220 |
// Fold fmul(vecreduce(x), vecreduce(y)) -> vecreduce(fmul(x, y)) |
--- |
16220 |
// Fold fmul(vecreduce(x), vecreduce(y)) -> vecreduce(fmul(x, y)) |
--- |
| 16221 |
if (SDValue SD = reassociateReduction(ISD::VECREDUCE_FMUL, ISD::FMUL, DL, |
0 |
16221 |
if (SDValue SD = reassociateReduction(ISD::VECREDUCE_FMUL, ISD::FMUL, DL, |
0 |
| 16222 |
VT, N0, N1, Flags)) |
0 |
16222 |
VT, N0, N1, Flags)) |
0 |
| 16223 |
return SD; |
0 |
16223 |
return SD; |
0 |
| 16224 |
} |
--- |
16224 |
} |
--- |
| 16225 |
|
--- |
16225 |
|
--- |
| 16226 |
// fold (fmul X, 2.0) -> (fadd X, X) |
--- |
16226 |
// fold (fmul X, 2.0) -> (fadd X, X) |
--- |
| 16227 |
if (N1CFP && N1CFP->isExactlyValue(+2.0)) |
0 |
16227 |
if (N1CFP && N1CFP->isExactlyValue(+2.0)) |
0 |
| 16228 |
return DAG.getNode(ISD::FADD, DL, VT, N0, N0); |
0 |
16228 |
return DAG.getNode(ISD::FADD, DL, VT, N0, N0); |
0 |
| 16229 |
|
--- |
16229 |
|
--- |
| 16230 |
// fold (fmul X, -1.0) -> (fsub -0.0, X) |
--- |
16230 |
// fold (fmul X, -1.0) -> (fsub -0.0, X) |
--- |
| 16231 |
if (N1CFP && N1CFP->isExactlyValue(-1.0)) { |
0 |
16231 |
if (N1CFP && N1CFP->isExactlyValue(-1.0)) { |
0 |
| 16232 |
if (!LegalOperations || TLI.isOperationLegal(ISD::FSUB, VT)) { |
0 |
16232 |
if (!LegalOperations || TLI.isOperationLegal(ISD::FSUB, VT)) { |
0 |
| 16233 |
return DAG.getNode(ISD::FSUB, DL, VT, |
0 |
16233 |
return DAG.getNode(ISD::FSUB, DL, VT, |
0 |
| 16234 |
DAG.getConstantFP(-0.0, DL, VT), N0, Flags); |
0 |
16234 |
DAG.getConstantFP(-0.0, DL, VT), N0, Flags); |
0 |
| 16235 |
} |
--- |
16235 |
} |
--- |
| 16236 |
} |
--- |
16236 |
} |
--- |
| 16237 |
|
--- |
16237 |
|
--- |
| 16238 |
// -N0 * -N1 --> N0 * N1 |
--- |
16238 |
// -N0 * -N1 --> N0 * N1 |
--- |
| 16239 |
TargetLowering::NegatibleCost CostN0 = |
0 |
16239 |
TargetLowering::NegatibleCost CostN0 = |
0 |
| 16240 |
TargetLowering::NegatibleCost::Expensive; |
--- |
16240 |
TargetLowering::NegatibleCost::Expensive; |
--- |
| 16241 |
TargetLowering::NegatibleCost CostN1 = |
0 |
16241 |
TargetLowering::NegatibleCost CostN1 = |
0 |
| 16242 |
TargetLowering::NegatibleCost::Expensive; |
--- |
16242 |
TargetLowering::NegatibleCost::Expensive; |
--- |
| 16243 |
SDValue NegN0 = |
--- |
16243 |
SDValue NegN0 = |
--- |
| 16244 |
TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize, CostN0); |
0 |
16244 |
TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize, CostN0); |
0 |
| 16245 |
if (NegN0) { |
0 |
16245 |
if (NegN0) { |
0 |
| 16246 |
HandleSDNode NegN0Handle(NegN0); |
0 |
16246 |
HandleSDNode NegN0Handle(NegN0); |
0 |
| 16247 |
SDValue NegN1 = |
--- |
16247 |
SDValue NegN1 = |
--- |
| 16248 |
TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize, CostN1); |
0 |
16248 |
TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize, CostN1); |
0 |
| 16249 |
if (NegN1 && (CostN0 == TargetLowering::NegatibleCost::Cheaper || |
0 |
16249 |
if (NegN1 && (CostN0 == TargetLowering::NegatibleCost::Cheaper || |
0 |
| 16250 |
CostN1 == TargetLowering::NegatibleCost::Cheaper)) |
0 |
16250 |
CostN1 == TargetLowering::NegatibleCost::Cheaper)) |
0 |
| 16251 |
return DAG.getNode(ISD::FMUL, DL, VT, NegN0, NegN1); |
0 |
16251 |
return DAG.getNode(ISD::FMUL, DL, VT, NegN0, NegN1); |
0 |
| 16252 |
} |
0 |
16252 |
} |
0 |
| 16253 |
|
--- |
16253 |
|
--- |
| 16254 |
// fold (fmul X, (select (fcmp X > 0.0), -1.0, 1.0)) -> (fneg (fabs X)) |
--- |
16254 |
// fold (fmul X, (select (fcmp X > 0.0), -1.0, 1.0)) -> (fneg (fabs X)) |
--- |
| 16255 |
// fold (fmul X, (select (fcmp X > 0.0), 1.0, -1.0)) -> (fabs X) |
--- |
16255 |
// fold (fmul X, (select (fcmp X > 0.0), 1.0, -1.0)) -> (fabs X) |
--- |
| 16256 |
if (Flags.hasNoNaNs() && Flags.hasNoSignedZeros() && |
0 |
16256 |
if (Flags.hasNoNaNs() && Flags.hasNoSignedZeros() && |
0 |
| 16257 |
(N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) && |
0 |
16257 |
(N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) && |
0 |
| 16258 |
TLI.isOperationLegal(ISD::FABS, VT)) { |
0 |
16258 |
TLI.isOperationLegal(ISD::FABS, VT)) { |
0 |
| 16259 |
SDValue Select = N0, X = N1; |
0 |
16259 |
SDValue Select = N0, X = N1; |
0 |
| 16260 |
if (Select.getOpcode() != ISD::SELECT) |
0 |
16260 |
if (Select.getOpcode() != ISD::SELECT) |
0 |
| 16261 |
std::swap(Select, X); |
0 |
16261 |
std::swap(Select, X); |
0 |
| 16262 |
|
--- |
16262 |
|
--- |
| 16263 |
SDValue Cond = Select.getOperand(0); |
0 |
16263 |
SDValue Cond = Select.getOperand(0); |
0 |
| 16264 |
auto TrueOpnd = dyn_cast(Select.getOperand(1)); |
0 |
16264 |
auto TrueOpnd = dyn_cast(Select.getOperand(1)); |
0 |
| 16265 |
auto FalseOpnd = dyn_cast(Select.getOperand(2)); |
0 |
16265 |
auto FalseOpnd = dyn_cast(Select.getOperand(2)); |
0 |
| 16266 |
|
--- |
16266 |
|
--- |
| 16267 |
if (TrueOpnd && FalseOpnd && |
0 |
16267 |
if (TrueOpnd && FalseOpnd && |
0 |
| 16268 |
Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == X && |
0 |
16268 |
Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == X && |
0 |
| 16269 |
isa(Cond.getOperand(1)) && |
0 |
16269 |
isa(Cond.getOperand(1)) && |
0 |
| 16270 |
cast(Cond.getOperand(1))->isExactlyValue(0.0)) { |
0 |
16270 |
cast(Cond.getOperand(1))->isExactlyValue(0.0)) { |
0 |
| 16271 |
ISD::CondCode CC = cast(Cond.getOperand(2))->get(); |
0 |
16271 |
ISD::CondCode CC = cast(Cond.getOperand(2))->get(); |
0 |
| 16272 |
switch (CC) { |
0 |
16272 |
switch (CC) { |
0 |
| 16273 |
default: break; |
0 |
16273 |
default: break; |
0 |
| 16274 |
case ISD::SETOLT: |
0 |
16274 |
case ISD::SETOLT: |
0 |
| 16275 |
case ISD::SETULT: |
--- |
16275 |
case ISD::SETULT: |
--- |
| 16276 |
case ISD::SETOLE: |
--- |
16276 |
case ISD::SETOLE: |
--- |
| 16277 |
case ISD::SETULE: |
--- |
16277 |
case ISD::SETULE: |
--- |
| 16278 |
case ISD::SETLT: |
--- |
16278 |
case ISD::SETLT: |
--- |
| 16279 |
case ISD::SETLE: |
--- |
16279 |
case ISD::SETLE: |
--- |
| 16280 |
std::swap(TrueOpnd, FalseOpnd); |
0 |
16280 |
std::swap(TrueOpnd, FalseOpnd); |
0 |
| 16281 |
[[fallthrough]]; |
--- |
16281 |
[[fallthrough]]; |
--- |
| 16282 |
case ISD::SETOGT: |
0 |
16282 |
case ISD::SETOGT: |
0 |
| 16283 |
case ISD::SETUGT: |
--- |
16283 |
case ISD::SETUGT: |
--- |
| 16284 |
case ISD::SETOGE: |
--- |
16284 |
case ISD::SETOGE: |
--- |
| 16285 |
case ISD::SETUGE: |
--- |
16285 |
case ISD::SETUGE: |
--- |
| 16286 |
case ISD::SETGT: |
--- |
16286 |
case ISD::SETGT: |
--- |
| 16287 |
case ISD::SETGE: |
--- |
16287 |
case ISD::SETGE: |
--- |
| 16288 |
if (TrueOpnd->isExactlyValue(-1.0) && FalseOpnd->isExactlyValue(1.0) && |
0 |
16288 |
if (TrueOpnd->isExactlyValue(-1.0) && FalseOpnd->isExactlyValue(1.0) && |
0 |
| 16289 |
TLI.isOperationLegal(ISD::FNEG, VT)) |
0 |
16289 |
TLI.isOperationLegal(ISD::FNEG, VT)) |
0 |
| 16290 |
return DAG.getNode(ISD::FNEG, DL, VT, |
0 |
16290 |
return DAG.getNode(ISD::FNEG, DL, VT, |
0 |
| 16291 |
DAG.getNode(ISD::FABS, DL, VT, X)); |
0 |
16291 |
DAG.getNode(ISD::FABS, DL, VT, X)); |
0 |
| 16292 |
if (TrueOpnd->isExactlyValue(1.0) && FalseOpnd->isExactlyValue(-1.0)) |
0 |
16292 |
if (TrueOpnd->isExactlyValue(1.0) && FalseOpnd->isExactlyValue(-1.0)) |
0 |
| 16293 |
return DAG.getNode(ISD::FABS, DL, VT, X); |
0 |
16293 |
return DAG.getNode(ISD::FABS, DL, VT, X); |
0 |
| 16294 |
|
--- |
16294 |
|
--- |
| 16295 |
break; |
0 |
16295 |
break; |
0 |
| 16296 |
} |
--- |
16296 |
} |
--- |
| 16297 |
} |
--- |
16297 |
} |
--- |
| 16298 |
} |
--- |
16298 |
} |
--- |
| 16299 |
|
--- |
16299 |
|
--- |
| 16300 |
// FMUL -> FMA combines: |
--- |
16300 |
// FMUL -> FMA combines: |
--- |
| 16301 |
if (SDValue Fused = visitFMULForFMADistributiveCombine(N)) { |
0 |
16301 |
if (SDValue Fused = visitFMULForFMADistributiveCombine(N)) { |
0 |
| 16302 |
AddToWorklist(Fused.getNode()); |
0 |
16302 |
AddToWorklist(Fused.getNode()); |
0 |
| 16303 |
return Fused; |
0 |
16303 |
return Fused; |
0 |
| 16304 |
} |
--- |
16304 |
} |
--- |
| 16305 |
|
--- |
16305 |
|
--- |
| 16306 |
return SDValue(); |
0 |
16306 |
return SDValue(); |
0 |
| 16307 |
} |
0 |
16307 |
} |
0 |
| 16308 |
|
--- |
16308 |
|
--- |
| 16309 |
template SDValue DAGCombiner::visitFMA(SDNode *N) { |
0 |
16309 |
template SDValue DAGCombiner::visitFMA(SDNode *N) { |
0 |
| 16310 |
SDValue N0 = N->getOperand(0); |
0 |
16310 |
SDValue N0 = N->getOperand(0); |
0 |
| 16311 |
SDValue N1 = N->getOperand(1); |
0 |
16311 |
SDValue N1 = N->getOperand(1); |
0 |
| 16312 |
SDValue N2 = N->getOperand(2); |
0 |
16312 |
SDValue N2 = N->getOperand(2); |
0 |
| 16313 |
ConstantFPSDNode *N0CFP = dyn_cast(N0); |
0 |
16313 |
ConstantFPSDNode *N0CFP = dyn_cast(N0); |
0 |
| 16314 |
ConstantFPSDNode *N1CFP = dyn_cast(N1); |
0 |
16314 |
ConstantFPSDNode *N1CFP = dyn_cast(N1); |
0 |
| 16315 |
EVT VT = N->getValueType(0); |
0 |
16315 |
EVT VT = N->getValueType(0); |
0 |
| 16316 |
SDLoc DL(N); |
0 |
16316 |
SDLoc DL(N); |
0 |
| 16317 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
16317 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
| 16318 |
// FMA nodes have flags that propagate to the created nodes. |
--- |
16318 |
// FMA nodes have flags that propagate to the created nodes. |
--- |
| 16319 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
16319 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
| 16320 |
MatchContextClass matcher(DAG, TLI, N); |
0 |
16320 |
MatchContextClass matcher(DAG, TLI, N); |
0 |
| 16321 |
|
--- |
16321 |
|
--- |
| 16322 |
bool CanReassociate = |
0 |
16322 |
bool CanReassociate = |
0 |
| 16323 |
Options.UnsafeFPMath || N->getFlags().hasAllowReassociation(); |
0 |
16323 |
Options.UnsafeFPMath || N->getFlags().hasAllowReassociation(); |
0 |
| 16324 |
|
--- |
16324 |
|
--- |
| 16325 |
// Constant fold FMA. |
--- |
16325 |
// Constant fold FMA. |
--- |
| 16326 |
if (isa(N0) && |
0 |
16326 |
if (isa(N0) && |
0 |
| 16327 |
isa(N1) && |
0 |
16327 |
isa(N1) && |
0 |
| 16328 |
isa(N2)) { |
0 |
16328 |
isa(N2)) { |
0 |
| 16329 |
return matcher.getNode(ISD::FMA, DL, VT, N0, N1, N2); |
0 |
16329 |
return matcher.getNode(ISD::FMA, DL, VT, N0, N1, N2); |
0 |
| 16330 |
} |
--- |
16330 |
} |
--- |
| 16331 |
|
--- |
16331 |
|
--- |
| 16332 |
// (-N0 * -N1) + N2 --> (N0 * N1) + N2 |
--- |
16332 |
// (-N0 * -N1) + N2 --> (N0 * N1) + N2 |
--- |
| 16333 |
TargetLowering::NegatibleCost CostN0 = |
0 |
16333 |
TargetLowering::NegatibleCost CostN0 = |
0 |
| 16334 |
TargetLowering::NegatibleCost::Expensive; |
--- |
16334 |
TargetLowering::NegatibleCost::Expensive; |
--- |
| 16335 |
TargetLowering::NegatibleCost CostN1 = |
0 |
16335 |
TargetLowering::NegatibleCost CostN1 = |
0 |
| 16336 |
TargetLowering::NegatibleCost::Expensive; |
--- |
16336 |
TargetLowering::NegatibleCost::Expensive; |
--- |
| 16337 |
SDValue NegN0 = |
--- |
16337 |
SDValue NegN0 = |
--- |
| 16338 |
TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize, CostN0); |
0 |
16338 |
TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize, CostN0); |
0 |
| 16339 |
if (NegN0) { |
0 |
16339 |
if (NegN0) { |
0 |
| 16340 |
HandleSDNode NegN0Handle(NegN0); |
0 |
16340 |
HandleSDNode NegN0Handle(NegN0); |
0 |
| 16341 |
SDValue NegN1 = |
--- |
16341 |
SDValue NegN1 = |
--- |
| 16342 |
TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize, CostN1); |
0 |
16342 |
TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize, CostN1); |
0 |
| 16343 |
if (NegN1 && (CostN0 == TargetLowering::NegatibleCost::Cheaper || |
0 |
16343 |
if (NegN1 && (CostN0 == TargetLowering::NegatibleCost::Cheaper || |
0 |
| 16344 |
CostN1 == TargetLowering::NegatibleCost::Cheaper)) |
0 |
16344 |
CostN1 == TargetLowering::NegatibleCost::Cheaper)) |
0 |
| 16345 |
return matcher.getNode(ISD::FMA, DL, VT, NegN0, NegN1, N2); |
0 |
16345 |
return matcher.getNode(ISD::FMA, DL, VT, NegN0, NegN1, N2); |
0 |
| 16346 |
} |
0 |
16346 |
} |
0 |
| 16347 |
|
--- |
16347 |
|
--- |
| 16348 |
// FIXME: use fast math flags instead of Options.UnsafeFPMath |
--- |
16348 |
// FIXME: use fast math flags instead of Options.UnsafeFPMath |
--- |
| 16349 |
if (Options.UnsafeFPMath) { |
0 |
16349 |
if (Options.UnsafeFPMath) { |
0 |
| 16350 |
if (N0CFP && N0CFP->isZero()) |
0 |
16350 |
if (N0CFP && N0CFP->isZero()) |
0 |
| 16351 |
return N2; |
0 |
16351 |
return N2; |
0 |
| 16352 |
if (N1CFP && N1CFP->isZero()) |
0 |
16352 |
if (N1CFP && N1CFP->isZero()) |
0 |
| 16353 |
return N2; |
0 |
16353 |
return N2; |
0 |
| 16354 |
} |
--- |
16354 |
} |
--- |
| 16355 |
|
--- |
16355 |
|
--- |
| 16356 |
// FIXME: Support splat of constant. |
--- |
16356 |
// FIXME: Support splat of constant. |
--- |
| 16357 |
if (N0CFP && N0CFP->isExactlyValue(1.0)) |
0 |
16357 |
if (N0CFP && N0CFP->isExactlyValue(1.0)) |
0 |
| 16358 |
return matcher.getNode(ISD::FADD, SDLoc(N), VT, N1, N2); |
0 |
16358 |
return matcher.getNode(ISD::FADD, SDLoc(N), VT, N1, N2); |
0 |
| 16359 |
if (N1CFP && N1CFP->isExactlyValue(1.0)) |
0 |
16359 |
if (N1CFP && N1CFP->isExactlyValue(1.0)) |
0 |
| 16360 |
return matcher.getNode(ISD::FADD, SDLoc(N), VT, N0, N2); |
0 |
16360 |
return matcher.getNode(ISD::FADD, SDLoc(N), VT, N0, N2); |
0 |
| 16361 |
|
--- |
16361 |
|
--- |
| 16362 |
// Canonicalize (fma c, x, y) -> (fma x, c, y) |
--- |
16362 |
// Canonicalize (fma c, x, y) -> (fma x, c, y) |
--- |
| 16363 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0) && |
0 |
16363 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0) && |
0 |
| 16364 |
!DAG.isConstantFPBuildVectorOrConstantFP(N1)) |
0 |
16364 |
!DAG.isConstantFPBuildVectorOrConstantFP(N1)) |
0 |
| 16365 |
return matcher.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2); |
0 |
16365 |
return matcher.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2); |
0 |
| 16366 |
|
--- |
16366 |
|
--- |
| 16367 |
if (CanReassociate) { |
0 |
16367 |
if (CanReassociate) { |
0 |
| 16368 |
// (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) |
--- |
16368 |
// (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) |
--- |
| 16369 |
if (matcher.match(N2, ISD::FMUL) && N0 == N2.getOperand(0) && |
0 |
16369 |
if (matcher.match(N2, ISD::FMUL) && N0 == N2.getOperand(0) && |
0 |
| 16370 |
DAG.isConstantFPBuildVectorOrConstantFP(N1) && |
0 |
16370 |
DAG.isConstantFPBuildVectorOrConstantFP(N1) && |
0 |
| 16371 |
DAG.isConstantFPBuildVectorOrConstantFP(N2.getOperand(1))) { |
0 |
16371 |
DAG.isConstantFPBuildVectorOrConstantFP(N2.getOperand(1))) { |
0 |
| 16372 |
return matcher.getNode( |
0 |
16372 |
return matcher.getNode( |
0 |
| 16373 |
ISD::FMUL, DL, VT, N0, |
0 |
16373 |
ISD::FMUL, DL, VT, N0, |
0 |
| 16374 |
matcher.getNode(ISD::FADD, DL, VT, N1, N2.getOperand(1))); |
0 |
16374 |
matcher.getNode(ISD::FADD, DL, VT, N1, N2.getOperand(1))); |
0 |
| 16375 |
} |
--- |
16375 |
} |
--- |
| 16376 |
|
--- |
16376 |
|
--- |
| 16377 |
// (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) |
--- |
16377 |
// (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) |
--- |
| 16378 |
if (matcher.match(N0, ISD::FMUL) && |
0 |
16378 |
if (matcher.match(N0, ISD::FMUL) && |
0 |
| 16379 |
DAG.isConstantFPBuildVectorOrConstantFP(N1) && |
0 |
16379 |
DAG.isConstantFPBuildVectorOrConstantFP(N1) && |
0 |
| 16380 |
DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(1))) { |
0 |
16380 |
DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(1))) { |
0 |
| 16381 |
return matcher.getNode( |
0 |
16381 |
return matcher.getNode( |
0 |
| 16382 |
ISD::FMA, DL, VT, N0.getOperand(0), |
0 |
16382 |
ISD::FMA, DL, VT, N0.getOperand(0), |
0 |
| 16383 |
matcher.getNode(ISD::FMUL, DL, VT, N1, N0.getOperand(1)), N2); |
0 |
16383 |
matcher.getNode(ISD::FMUL, DL, VT, N1, N0.getOperand(1)), N2); |
0 |
| 16384 |
} |
--- |
16384 |
} |
--- |
| 16385 |
} |
--- |
16385 |
} |
--- |
| 16386 |
|
--- |
16386 |
|
--- |
| 16387 |
// (fma x, -1, y) -> (fadd (fneg x), y) |
--- |
16387 |
// (fma x, -1, y) -> (fadd (fneg x), y) |
--- |
| 16388 |
// FIXME: Support splat of constant. |
--- |
16388 |
// FIXME: Support splat of constant. |
--- |
| 16389 |
if (N1CFP) { |
0 |
16389 |
if (N1CFP) { |
0 |
| 16390 |
if (N1CFP->isExactlyValue(1.0)) |
0 |
16390 |
if (N1CFP->isExactlyValue(1.0)) |
0 |
| 16391 |
return matcher.getNode(ISD::FADD, DL, VT, N0, N2); |
0 |
16391 |
return matcher.getNode(ISD::FADD, DL, VT, N0, N2); |
0 |
| 16392 |
|
--- |
16392 |
|
--- |
| 16393 |
if (N1CFP->isExactlyValue(-1.0) && |
0 |
16393 |
if (N1CFP->isExactlyValue(-1.0) && |
0 |
| 16394 |
(!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { |
0 |
16394 |
(!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { |
0 |
| 16395 |
SDValue RHSNeg = matcher.getNode(ISD::FNEG, DL, VT, N0); |
0 |
16395 |
SDValue RHSNeg = matcher.getNode(ISD::FNEG, DL, VT, N0); |
0 |
| 16396 |
AddToWorklist(RHSNeg.getNode()); |
0 |
16396 |
AddToWorklist(RHSNeg.getNode()); |
0 |
| 16397 |
return matcher.getNode(ISD::FADD, DL, VT, N2, RHSNeg); |
0 |
16397 |
return matcher.getNode(ISD::FADD, DL, VT, N2, RHSNeg); |
0 |
| 16398 |
} |
--- |
16398 |
} |
--- |
| 16399 |
|
--- |
16399 |
|
--- |
| 16400 |
// fma (fneg x), K, y -> fma x -K, y |
--- |
16400 |
// fma (fneg x), K, y -> fma x -K, y |
--- |
| 16401 |
if (matcher.match(N0, ISD::FNEG) && |
0 |
16401 |
if (matcher.match(N0, ISD::FNEG) && |
0 |
| 16402 |
(TLI.isOperationLegal(ISD::ConstantFP, VT) || |
0 |
16402 |
(TLI.isOperationLegal(ISD::ConstantFP, VT) || |
0 |
| 16403 |
(N1.hasOneUse() && |
0 |
16403 |
(N1.hasOneUse() && |
0 |
| 16404 |
!TLI.isFPImmLegal(N1CFP->getValueAPF(), VT, ForCodeSize)))) { |
0 |
16404 |
!TLI.isFPImmLegal(N1CFP->getValueAPF(), VT, ForCodeSize)))) { |
0 |
| 16405 |
return matcher.getNode(ISD::FMA, DL, VT, N0.getOperand(0), |
0 |
16405 |
return matcher.getNode(ISD::FMA, DL, VT, N0.getOperand(0), |
0 |
| 16406 |
matcher.getNode(ISD::FNEG, DL, VT, N1), N2); |
0 |
16406 |
matcher.getNode(ISD::FNEG, DL, VT, N1), N2); |
0 |
| 16407 |
} |
--- |
16407 |
} |
--- |
| 16408 |
} |
--- |
16408 |
} |
--- |
| 16409 |
|
--- |
16409 |
|
--- |
| 16410 |
// FIXME: Support splat of constant. |
--- |
16410 |
// FIXME: Support splat of constant. |
--- |
| 16411 |
if (CanReassociate) { |
0 |
16411 |
if (CanReassociate) { |
0 |
| 16412 |
// (fma x, c, x) -> (fmul x, (c+1)) |
--- |
16412 |
// (fma x, c, x) -> (fmul x, (c+1)) |
--- |
| 16413 |
if (N1CFP && N0 == N2) { |
0 |
16413 |
if (N1CFP && N0 == N2) { |
0 |
| 16414 |
return matcher.getNode(ISD::FMUL, DL, VT, N0, |
0 |
16414 |
return matcher.getNode(ISD::FMUL, DL, VT, N0, |
0 |
| 16415 |
matcher.getNode(ISD::FADD, DL, VT, N1, |
0 |
16415 |
matcher.getNode(ISD::FADD, DL, VT, N1, |
0 |
| 16416 |
DAG.getConstantFP(1.0, DL, VT))); |
0 |
16416 |
DAG.getConstantFP(1.0, DL, VT))); |
0 |
| 16417 |
} |
--- |
16417 |
} |
--- |
| 16418 |
|
--- |
16418 |
|
--- |
| 16419 |
// (fma x, c, (fneg x)) -> (fmul x, (c-1)) |
--- |
16419 |
// (fma x, c, (fneg x)) -> (fmul x, (c-1)) |
--- |
| 16420 |
if (N1CFP && matcher.match(N2, ISD::FNEG) && N2.getOperand(0) == N0) { |
0 |
16420 |
if (N1CFP && matcher.match(N2, ISD::FNEG) && N2.getOperand(0) == N0) { |
0 |
| 16421 |
return matcher.getNode(ISD::FMUL, DL, VT, N0, |
0 |
16421 |
return matcher.getNode(ISD::FMUL, DL, VT, N0, |
0 |
| 16422 |
matcher.getNode(ISD::FADD, DL, VT, N1, |
0 |
16422 |
matcher.getNode(ISD::FADD, DL, VT, N1, |
0 |
| 16423 |
DAG.getConstantFP(-1.0, DL, VT))); |
0 |
16423 |
DAG.getConstantFP(-1.0, DL, VT))); |
0 |
| 16424 |
} |
--- |
16424 |
} |
--- |
| 16425 |
} |
--- |
16425 |
} |
--- |
| 16426 |
|
--- |
16426 |
|
--- |
| 16427 |
// fold ((fma (fneg X), Y, (fneg Z)) -> fneg (fma X, Y, Z)) |
--- |
16427 |
// fold ((fma (fneg X), Y, (fneg Z)) -> fneg (fma X, Y, Z)) |
--- |
| 16428 |
// fold ((fma X, (fneg Y), (fneg Z)) -> fneg (fma X, Y, Z)) |
--- |
16428 |
// fold ((fma X, (fneg Y), (fneg Z)) -> fneg (fma X, Y, Z)) |
--- |
| 16429 |
if (!TLI.isFNegFree(VT)) |
0 |
16429 |
if (!TLI.isFNegFree(VT)) |
0 |
| 16430 |
if (SDValue Neg = TLI.getCheaperNegatedExpression( |
0 |
16430 |
if (SDValue Neg = TLI.getCheaperNegatedExpression( |
0 |
| 16431 |
SDValue(N, 0), DAG, LegalOperations, ForCodeSize)) |
0 |
16431 |
SDValue(N, 0), DAG, LegalOperations, ForCodeSize)) |
0 |
| 16432 |
return matcher.getNode(ISD::FNEG, DL, VT, Neg); |
0 |
16432 |
return matcher.getNode(ISD::FNEG, DL, VT, Neg); |
0 |
| 16433 |
return SDValue(); |
0 |
16433 |
return SDValue(); |
0 |
| 16434 |
} |
0 |
16434 |
} |
0 |
| 16435 |
|
--- |
16435 |
|
--- |
| 16436 |
// Combine multiple FDIVs with the same divisor into multiple FMULs by the |
--- |
16436 |
// Combine multiple FDIVs with the same divisor into multiple FMULs by the |
--- |
| 16437 |
// reciprocal. |
--- |
16437 |
// reciprocal. |
--- |
| 16438 |
// E.g., (a / D; b / D;) -> (recip = 1.0 / D; a * recip; b * recip) |
--- |
16438 |
// E.g., (a / D; b / D;) -> (recip = 1.0 / D; a * recip; b * recip) |
--- |
| 16439 |
// Notice that this is not always beneficial. One reason is different targets |
--- |
16439 |
// Notice that this is not always beneficial. One reason is different targets |
--- |
| 16440 |
// may have different costs for FDIV and FMUL, so sometimes the cost of two |
--- |
16440 |
// may have different costs for FDIV and FMUL, so sometimes the cost of two |
--- |
| 16441 |
// FDIVs may be lower than the cost of one FDIV and two FMULs. Another reason |
--- |
16441 |
// FDIVs may be lower than the cost of one FDIV and two FMULs. Another reason |
--- |
| 16442 |
// is the critical path is increased from "one FDIV" to "one FDIV + one FMUL". |
--- |
16442 |
// is the critical path is increased from "one FDIV" to "one FDIV + one FMUL". |
--- |
| 16443 |
SDValue DAGCombiner::combineRepeatedFPDivisors(SDNode *N) { |
0 |
16443 |
SDValue DAGCombiner::combineRepeatedFPDivisors(SDNode *N) { |
0 |
| 16444 |
// TODO: Limit this transform based on optsize/minsize - it always creates at |
--- |
16444 |
// TODO: Limit this transform based on optsize/minsize - it always creates at |
--- |
| 16445 |
// least 1 extra instruction. But the perf win may be substantial enough |
--- |
16445 |
// least 1 extra instruction. But the perf win may be substantial enough |
--- |
| 16446 |
// that only minsize should restrict this. |
--- |
16446 |
// that only minsize should restrict this. |
--- |
| 16447 |
bool UnsafeMath = DAG.getTarget().Options.UnsafeFPMath; |
0 |
16447 |
bool UnsafeMath = DAG.getTarget().Options.UnsafeFPMath; |
0 |
| 16448 |
const SDNodeFlags Flags = N->getFlags(); |
0 |
16448 |
const SDNodeFlags Flags = N->getFlags(); |
0 |
| 16449 |
if (LegalDAG || (!UnsafeMath && !Flags.hasAllowReciprocal())) |
0 |
16449 |
if (LegalDAG || (!UnsafeMath && !Flags.hasAllowReciprocal())) |
0 |
| 16450 |
return SDValue(); |
0 |
16450 |
return SDValue(); |
0 |
| 16451 |
|
--- |
16451 |
|
--- |
| 16452 |
// Skip if current node is a reciprocal/fneg-reciprocal. |
--- |
16452 |
// Skip if current node is a reciprocal/fneg-reciprocal. |
--- |
| 16453 |
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); |
0 |
16453 |
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); |
0 |
| 16454 |
ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, /* AllowUndefs */ true); |
0 |
16454 |
ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, /* AllowUndefs */ true); |
0 |
| 16455 |
if (N0CFP && (N0CFP->isExactlyValue(1.0) || N0CFP->isExactlyValue(-1.0))) |
0 |
16455 |
if (N0CFP && (N0CFP->isExactlyValue(1.0) || N0CFP->isExactlyValue(-1.0))) |
0 |
| 16456 |
return SDValue(); |
0 |
16456 |
return SDValue(); |
0 |
| 16457 |
|
--- |
16457 |
|
--- |
| 16458 |
// Exit early if the target does not want this transform or if there can't |
--- |
16458 |
// Exit early if the target does not want this transform or if there can't |
--- |
| 16459 |
// possibly be enough uses of the divisor to make the transform worthwhile. |
--- |
16459 |
// possibly be enough uses of the divisor to make the transform worthwhile. |
--- |
| 16460 |
unsigned MinUses = TLI.combineRepeatedFPDivisors(); |
0 |
16460 |
unsigned MinUses = TLI.combineRepeatedFPDivisors(); |
0 |
| 16461 |
|
--- |
16461 |
|
--- |
| 16462 |
// For splat vectors, scale the number of uses by the splat factor. If we can |
--- |
16462 |
// For splat vectors, scale the number of uses by the splat factor. If we can |
--- |
| 16463 |
// convert the division into a scalar op, that will likely be much faster. |
--- |
16463 |
// convert the division into a scalar op, that will likely be much faster. |
--- |
| 16464 |
unsigned NumElts = 1; |
0 |
16464 |
unsigned NumElts = 1; |
0 |
| 16465 |
EVT VT = N->getValueType(0); |
0 |
16465 |
EVT VT = N->getValueType(0); |
0 |
| 16466 |
if (VT.isVector() && DAG.isSplatValue(N1)) |
0 |
16466 |
if (VT.isVector() && DAG.isSplatValue(N1)) |
0 |
| 16467 |
NumElts = VT.getVectorMinNumElements(); |
0 |
16467 |
NumElts = VT.getVectorMinNumElements(); |
0 |
| 16468 |
|
--- |
16468 |
|
--- |
| 16469 |
if (!MinUses || (N1->use_size() * NumElts) < MinUses) |
0 |
16469 |
if (!MinUses || (N1->use_size() * NumElts) < MinUses) |
0 |
| 16470 |
return SDValue(); |
0 |
16470 |
return SDValue(); |
0 |
| 16471 |
|
--- |
16471 |
|
--- |
| 16472 |
// Find all FDIV users of the same divisor. |
--- |
16472 |
// Find all FDIV users of the same divisor. |
--- |
| 16473 |
// Use a set because duplicates may be present in the user list. |
--- |
16473 |
// Use a set because duplicates may be present in the user list. |
--- |
| 16474 |
SetVector Users; |
0 |
16474 |
SetVector Users; |
0 |
| 16475 |
for (auto *U : N1->uses()) { |
0 |
16475 |
for (auto *U : N1->uses()) { |
0 |
| 16476 |
if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) { |
0 |
16476 |
if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) { |
0 |
| 16477 |
// Skip X/sqrt(X) that has not been simplified to sqrt(X) yet. |
--- |
16477 |
// Skip X/sqrt(X) that has not been simplified to sqrt(X) yet. |
--- |
| 16478 |
if (U->getOperand(1).getOpcode() == ISD::FSQRT && |
0 |
16478 |
if (U->getOperand(1).getOpcode() == ISD::FSQRT && |
0 |
| 16479 |
U->getOperand(0) == U->getOperand(1).getOperand(0) && |
0 |
16479 |
U->getOperand(0) == U->getOperand(1).getOperand(0) && |
0 |
| 16480 |
U->getFlags().hasAllowReassociation() && |
0 |
16480 |
U->getFlags().hasAllowReassociation() && |
0 |
| 16481 |
U->getFlags().hasNoSignedZeros()) |
0 |
16481 |
U->getFlags().hasNoSignedZeros()) |
0 |
| 16482 |
continue; |
0 |
16482 |
continue; |
0 |
| 16483 |
|
--- |
16483 |
|
--- |
| 16484 |
// This division is eligible for optimization only if global unsafe math |
--- |
16484 |
// This division is eligible for optimization only if global unsafe math |
--- |
| 16485 |
// is enabled or if this division allows reciprocal formation. |
--- |
16485 |
// is enabled or if this division allows reciprocal formation. |
--- |
| 16486 |
if (UnsafeMath || U->getFlags().hasAllowReciprocal()) |
0 |
16486 |
if (UnsafeMath || U->getFlags().hasAllowReciprocal()) |
0 |
| 16487 |
Users.insert(U); |
0 |
16487 |
Users.insert(U); |
0 |
| 16488 |
} |
--- |
16488 |
} |
--- |
| 16489 |
} |
--- |
16489 |
} |
--- |
| 16490 |
|
--- |
16490 |
|
--- |
| 16491 |
// Now that we have the actual number of divisor uses, make sure it meets |
--- |
16491 |
// Now that we have the actual number of divisor uses, make sure it meets |
--- |
| 16492 |
// the minimum threshold specified by the target. |
--- |
16492 |
// the minimum threshold specified by the target. |
--- |
| 16493 |
if ((Users.size() * NumElts) < MinUses) |
0 |
16493 |
if ((Users.size() * NumElts) < MinUses) |
0 |
| 16494 |
return SDValue(); |
0 |
16494 |
return SDValue(); |
0 |
| 16495 |
|
--- |
16495 |
|
--- |
| 16496 |
SDLoc DL(N); |
0 |
16496 |
SDLoc DL(N); |
0 |
| 16497 |
SDValue FPOne = DAG.getConstantFP(1.0, DL, VT); |
0 |
16497 |
SDValue FPOne = DAG.getConstantFP(1.0, DL, VT); |
0 |
| 16498 |
SDValue Reciprocal = DAG.getNode(ISD::FDIV, DL, VT, FPOne, N1, Flags); |
0 |
16498 |
SDValue Reciprocal = DAG.getNode(ISD::FDIV, DL, VT, FPOne, N1, Flags); |
0 |
| 16499 |
|
--- |
16499 |
|
--- |
| 16500 |
// Dividend / Divisor -> Dividend * Reciprocal |
--- |
16500 |
// Dividend / Divisor -> Dividend * Reciprocal |
--- |
| 16501 |
for (auto *U : Users) { |
0 |
16501 |
for (auto *U : Users) { |
0 |
| 16502 |
SDValue Dividend = U->getOperand(0); |
0 |
16502 |
SDValue Dividend = U->getOperand(0); |
0 |
| 16503 |
if (Dividend != FPOne) { |
0 |
16503 |
if (Dividend != FPOne) { |
0 |
| 16504 |
SDValue NewNode = DAG.getNode(ISD::FMUL, SDLoc(U), VT, Dividend, |
0 |
16504 |
SDValue NewNode = DAG.getNode(ISD::FMUL, SDLoc(U), VT, Dividend, |
0 |
| 16505 |
Reciprocal, Flags); |
--- |
16505 |
Reciprocal, Flags); |
--- |
| 16506 |
CombineTo(U, NewNode); |
0 |
16506 |
CombineTo(U, NewNode); |
0 |
| 16507 |
} else if (U != Reciprocal.getNode()) { |
0 |
16507 |
} else if (U != Reciprocal.getNode()) { |
0 |
| 16508 |
// In the absence of fast-math-flags, this user node is always the |
--- |
16508 |
// In the absence of fast-math-flags, this user node is always the |
--- |
| 16509 |
// same node as Reciprocal, but with FMF they may be different nodes. |
--- |
16509 |
// same node as Reciprocal, but with FMF they may be different nodes. |
--- |
| 16510 |
CombineTo(U, Reciprocal); |
0 |
16510 |
CombineTo(U, Reciprocal); |
0 |
| 16511 |
} |
--- |
16511 |
} |
--- |
| 16512 |
} |
--- |
16512 |
} |
--- |
| 16513 |
return SDValue(N, 0); // N was replaced. |
0 |
16513 |
return SDValue(N, 0); // N was replaced. |
0 |
| 16514 |
} |
0 |
16514 |
} |
0 |
| 16515 |
|
--- |
16515 |
|
--- |
| 16516 |
SDValue DAGCombiner::visitFDIV(SDNode *N) { |
0 |
16516 |
SDValue DAGCombiner::visitFDIV(SDNode *N) { |
0 |
| 16517 |
SDValue N0 = N->getOperand(0); |
0 |
16517 |
SDValue N0 = N->getOperand(0); |
0 |
| 16518 |
SDValue N1 = N->getOperand(1); |
0 |
16518 |
SDValue N1 = N->getOperand(1); |
0 |
| 16519 |
EVT VT = N->getValueType(0); |
0 |
16519 |
EVT VT = N->getValueType(0); |
0 |
| 16520 |
SDLoc DL(N); |
0 |
16520 |
SDLoc DL(N); |
0 |
| 16521 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
16521 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
| 16522 |
SDNodeFlags Flags = N->getFlags(); |
0 |
16522 |
SDNodeFlags Flags = N->getFlags(); |
0 |
| 16523 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
16523 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
| 16524 |
|
--- |
16524 |
|
--- |
| 16525 |
if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) |
0 |
16525 |
if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) |
0 |
| 16526 |
return R; |
0 |
16526 |
return R; |
0 |
| 16527 |
|
--- |
16527 |
|
--- |
| 16528 |
// fold (fdiv c1, c2) -> c1/c2 |
--- |
16528 |
// fold (fdiv c1, c2) -> c1/c2 |
--- |
| 16529 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FDIV, DL, VT, {N0, N1})) |
0 |
16529 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FDIV, DL, VT, {N0, N1})) |
0 |
| 16530 |
return C; |
0 |
16530 |
return C; |
0 |
| 16531 |
|
--- |
16531 |
|
--- |
| 16532 |
// fold vector ops |
--- |
16532 |
// fold vector ops |
--- |
| 16533 |
if (VT.isVector()) |
0 |
16533 |
if (VT.isVector()) |
0 |
| 16534 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
16534 |
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL)) |
0 |
| 16535 |
return FoldedVOp; |
0 |
16535 |
return FoldedVOp; |
0 |
| 16536 |
|
--- |
16536 |
|
--- |
| 16537 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
16537 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 16538 |
return NewSel; |
0 |
16538 |
return NewSel; |
0 |
| 16539 |
|
--- |
16539 |
|
--- |
| 16540 |
if (SDValue V = combineRepeatedFPDivisors(N)) |
0 |
16540 |
if (SDValue V = combineRepeatedFPDivisors(N)) |
0 |
| 16541 |
return V; |
0 |
16541 |
return V; |
0 |
| 16542 |
|
--- |
16542 |
|
--- |
| 16543 |
if (Options.UnsafeFPMath || Flags.hasAllowReciprocal()) { |
0 |
16543 |
if (Options.UnsafeFPMath || Flags.hasAllowReciprocal()) { |
0 |
| 16544 |
// fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. |
--- |
16544 |
// fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. |
--- |
| 16545 |
if (auto *N1CFP = dyn_cast(N1)) { |
0 |
16545 |
if (auto *N1CFP = dyn_cast(N1)) { |
0 |
| 16546 |
// Compute the reciprocal 1.0 / c2. |
--- |
16546 |
// Compute the reciprocal 1.0 / c2. |
--- |
| 16547 |
const APFloat &N1APF = N1CFP->getValueAPF(); |
0 |
16547 |
const APFloat &N1APF = N1CFP->getValueAPF(); |
0 |
| 16548 |
APFloat Recip(N1APF.getSemantics(), 1); // 1.0 |
0 |
16548 |
APFloat Recip(N1APF.getSemantics(), 1); // 1.0 |
0 |
| 16549 |
APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); |
0 |
16549 |
APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); |
0 |
| 16550 |
// Only do the transform if the reciprocal is a legal fp immediate that |
--- |
16550 |
// Only do the transform if the reciprocal is a legal fp immediate that |
--- |
| 16551 |
// isn't too nasty (eg NaN, denormal, ...). |
--- |
16551 |
// isn't too nasty (eg NaN, denormal, ...). |
--- |
| 16552 |
if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty |
0 |
16552 |
if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty |
0 |
| 16553 |
(!LegalOperations || |
0 |
16553 |
(!LegalOperations || |
0 |
| 16554 |
// FIXME: custom lowering of ConstantFP might fail (see e.g. ARM |
--- |
16554 |
// FIXME: custom lowering of ConstantFP might fail (see e.g. ARM |
--- |
| 16555 |
// backend)... we should handle this gracefully after Legalize. |
--- |
16555 |
// backend)... we should handle this gracefully after Legalize. |
--- |
| 16556 |
// TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT) || |
--- |
16556 |
// TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT) || |
--- |
| 16557 |
TLI.isOperationLegal(ISD::ConstantFP, VT) || |
0 |
16557 |
TLI.isOperationLegal(ISD::ConstantFP, VT) || |
0 |
| 16558 |
TLI.isFPImmLegal(Recip, VT, ForCodeSize))) |
0 |
16558 |
TLI.isFPImmLegal(Recip, VT, ForCodeSize))) |
0 |
| 16559 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, |
0 |
16559 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, |
0 |
| 16560 |
DAG.getConstantFP(Recip, DL, VT)); |
0 |
16560 |
DAG.getConstantFP(Recip, DL, VT)); |
0 |
| 16561 |
} |
0 |
16561 |
} |
0 |
| 16562 |
|
--- |
16562 |
|
--- |
| 16563 |
// If this FDIV is part of a reciprocal square root, it may be folded |
--- |
16563 |
// If this FDIV is part of a reciprocal square root, it may be folded |
--- |
| 16564 |
// into a target-specific square root estimate instruction. |
--- |
16564 |
// into a target-specific square root estimate instruction. |
--- |
| 16565 |
if (N1.getOpcode() == ISD::FSQRT) { |
0 |
16565 |
if (N1.getOpcode() == ISD::FSQRT) { |
0 |
| 16566 |
if (SDValue RV = buildRsqrtEstimate(N1.getOperand(0), Flags)) |
0 |
16566 |
if (SDValue RV = buildRsqrtEstimate(N1.getOperand(0), Flags)) |
0 |
| 16567 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, RV); |
0 |
16567 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, RV); |
0 |
| 16568 |
} else if (N1.getOpcode() == ISD::FP_EXTEND && |
0 |
16568 |
} else if (N1.getOpcode() == ISD::FP_EXTEND && |
0 |
| 16569 |
N1.getOperand(0).getOpcode() == ISD::FSQRT) { |
0 |
16569 |
N1.getOperand(0).getOpcode() == ISD::FSQRT) { |
0 |
| 16570 |
if (SDValue RV = |
0 |
16570 |
if (SDValue RV = |
0 |
| 16571 |
buildRsqrtEstimate(N1.getOperand(0).getOperand(0), Flags)) { |
0 |
16571 |
buildRsqrtEstimate(N1.getOperand(0).getOperand(0), Flags)) { |
0 |
| 16572 |
RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N1), VT, RV); |
0 |
16572 |
RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N1), VT, RV); |
0 |
| 16573 |
AddToWorklist(RV.getNode()); |
0 |
16573 |
AddToWorklist(RV.getNode()); |
0 |
| 16574 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, RV); |
0 |
16574 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, RV); |
0 |
| 16575 |
} |
--- |
16575 |
} |
--- |
| 16576 |
} else if (N1.getOpcode() == ISD::FP_ROUND && |
0 |
16576 |
} else if (N1.getOpcode() == ISD::FP_ROUND && |
0 |
| 16577 |
N1.getOperand(0).getOpcode() == ISD::FSQRT) { |
0 |
16577 |
N1.getOperand(0).getOpcode() == ISD::FSQRT) { |
0 |
| 16578 |
if (SDValue RV = |
0 |
16578 |
if (SDValue RV = |
0 |
| 16579 |
buildRsqrtEstimate(N1.getOperand(0).getOperand(0), Flags)) { |
0 |
16579 |
buildRsqrtEstimate(N1.getOperand(0).getOperand(0), Flags)) { |
0 |
| 16580 |
RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1)); |
0 |
16580 |
RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1)); |
0 |
| 16581 |
AddToWorklist(RV.getNode()); |
0 |
16581 |
AddToWorklist(RV.getNode()); |
0 |
| 16582 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, RV); |
0 |
16582 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, RV); |
0 |
| 16583 |
} |
--- |
16583 |
} |
--- |
| 16584 |
} else if (N1.getOpcode() == ISD::FMUL) { |
0 |
16584 |
} else if (N1.getOpcode() == ISD::FMUL) { |
0 |
| 16585 |
// Look through an FMUL. Even though this won't remove the FDIV directly, |
--- |
16585 |
// Look through an FMUL. Even though this won't remove the FDIV directly, |
--- |
| 16586 |
// it's still worthwhile to get rid of the FSQRT if possible. |
--- |
16586 |
// it's still worthwhile to get rid of the FSQRT if possible. |
--- |
| 16587 |
SDValue Sqrt, Y; |
0 |
16587 |
SDValue Sqrt, Y; |
0 |
| 16588 |
if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { |
0 |
16588 |
if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { |
0 |
| 16589 |
Sqrt = N1.getOperand(0); |
0 |
16589 |
Sqrt = N1.getOperand(0); |
0 |
| 16590 |
Y = N1.getOperand(1); |
0 |
16590 |
Y = N1.getOperand(1); |
0 |
| 16591 |
} else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { |
0 |
16591 |
} else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { |
0 |
| 16592 |
Sqrt = N1.getOperand(1); |
0 |
16592 |
Sqrt = N1.getOperand(1); |
0 |
| 16593 |
Y = N1.getOperand(0); |
0 |
16593 |
Y = N1.getOperand(0); |
0 |
| 16594 |
} |
--- |
16594 |
} |
--- |
| 16595 |
if (Sqrt.getNode()) { |
0 |
16595 |
if (Sqrt.getNode()) { |
0 |
| 16596 |
// If the other multiply operand is known positive, pull it into the |
--- |
16596 |
// If the other multiply operand is known positive, pull it into the |
--- |
| 16597 |
// sqrt. That will eliminate the division if we convert to an estimate. |
--- |
16597 |
// sqrt. That will eliminate the division if we convert to an estimate. |
--- |
| 16598 |
if (Flags.hasAllowReassociation() && N1.hasOneUse() && |
0 |
16598 |
if (Flags.hasAllowReassociation() && N1.hasOneUse() && |
0 |
| 16599 |
N1->getFlags().hasAllowReassociation() && Sqrt.hasOneUse()) { |
0 |
16599 |
N1->getFlags().hasAllowReassociation() && Sqrt.hasOneUse()) { |
0 |
| 16600 |
SDValue A; |
0 |
16600 |
SDValue A; |
0 |
| 16601 |
if (Y.getOpcode() == ISD::FABS && Y.hasOneUse()) |
0 |
16601 |
if (Y.getOpcode() == ISD::FABS && Y.hasOneUse()) |
0 |
| 16602 |
A = Y.getOperand(0); |
0 |
16602 |
A = Y.getOperand(0); |
0 |
| 16603 |
else if (Y == Sqrt.getOperand(0)) |
0 |
16603 |
else if (Y == Sqrt.getOperand(0)) |
0 |
| 16604 |
A = Y; |
0 |
16604 |
A = Y; |
0 |
| 16605 |
if (A) { |
0 |
16605 |
if (A) { |
0 |
| 16606 |
// X / (fabs(A) * sqrt(Z)) --> X / sqrt(A*A*Z) --> X * rsqrt(A*A*Z) |
--- |
16606 |
// X / (fabs(A) * sqrt(Z)) --> X / sqrt(A*A*Z) --> X * rsqrt(A*A*Z) |
--- |
| 16607 |
// X / (A * sqrt(A)) --> X / sqrt(A*A*A) --> X * rsqrt(A*A*A) |
--- |
16607 |
// X / (A * sqrt(A)) --> X / sqrt(A*A*A) --> X * rsqrt(A*A*A) |
--- |
| 16608 |
SDValue AA = DAG.getNode(ISD::FMUL, DL, VT, A, A); |
0 |
16608 |
SDValue AA = DAG.getNode(ISD::FMUL, DL, VT, A, A); |
0 |
| 16609 |
SDValue AAZ = |
--- |
16609 |
SDValue AAZ = |
--- |
| 16610 |
DAG.getNode(ISD::FMUL, DL, VT, AA, Sqrt.getOperand(0)); |
0 |
16610 |
DAG.getNode(ISD::FMUL, DL, VT, AA, Sqrt.getOperand(0)); |
0 |
| 16611 |
if (SDValue Rsqrt = buildRsqrtEstimate(AAZ, Flags)) |
0 |
16611 |
if (SDValue Rsqrt = buildRsqrtEstimate(AAZ, Flags)) |
0 |
| 16612 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, Rsqrt); |
0 |
16612 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, Rsqrt); |
0 |
| 16613 |
|
--- |
16613 |
|
--- |
| 16614 |
// Estimate creation failed. Clean up speculatively created nodes. |
--- |
16614 |
// Estimate creation failed. Clean up speculatively created nodes. |
--- |
| 16615 |
recursivelyDeleteUnusedNodes(AAZ.getNode()); |
0 |
16615 |
recursivelyDeleteUnusedNodes(AAZ.getNode()); |
0 |
| 16616 |
} |
--- |
16616 |
} |
--- |
| 16617 |
} |
--- |
16617 |
} |
--- |
| 16618 |
|
--- |
16618 |
|
--- |
| 16619 |
// We found a FSQRT, so try to make this fold: |
--- |
16619 |
// We found a FSQRT, so try to make this fold: |
--- |
| 16620 |
// X / (Y * sqrt(Z)) -> X * (rsqrt(Z) / Y) |
--- |
16620 |
// X / (Y * sqrt(Z)) -> X * (rsqrt(Z) / Y) |
--- |
| 16621 |
if (SDValue Rsqrt = buildRsqrtEstimate(Sqrt.getOperand(0), Flags)) { |
0 |
16621 |
if (SDValue Rsqrt = buildRsqrtEstimate(Sqrt.getOperand(0), Flags)) { |
0 |
| 16622 |
SDValue Div = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, Rsqrt, Y); |
0 |
16622 |
SDValue Div = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, Rsqrt, Y); |
0 |
| 16623 |
AddToWorklist(Div.getNode()); |
0 |
16623 |
AddToWorklist(Div.getNode()); |
0 |
| 16624 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, Div); |
0 |
16624 |
return DAG.getNode(ISD::FMUL, DL, VT, N0, Div); |
0 |
| 16625 |
} |
--- |
16625 |
} |
--- |
| 16626 |
} |
--- |
16626 |
} |
--- |
| 16627 |
} |
--- |
16627 |
} |
--- |
| 16628 |
|
--- |
16628 |
|
--- |
| 16629 |
// Fold into a reciprocal estimate and multiply instead of a real divide. |
--- |
16629 |
// Fold into a reciprocal estimate and multiply instead of a real divide. |
--- |
| 16630 |
if (Options.NoInfsFPMath || Flags.hasNoInfs()) |
0 |
16630 |
if (Options.NoInfsFPMath || Flags.hasNoInfs()) |
0 |
| 16631 |
if (SDValue RV = BuildDivEstimate(N0, N1, Flags)) |
0 |
16631 |
if (SDValue RV = BuildDivEstimate(N0, N1, Flags)) |
0 |
| 16632 |
return RV; |
0 |
16632 |
return RV; |
0 |
| 16633 |
} |
--- |
16633 |
} |
--- |
| 16634 |
|
--- |
16634 |
|
--- |
| 16635 |
// Fold X/Sqrt(X) -> Sqrt(X) |
--- |
16635 |
// Fold X/Sqrt(X) -> Sqrt(X) |
--- |
| 16636 |
if ((Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && |
0 |
16636 |
if ((Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) && |
0 |
| 16637 |
(Options.UnsafeFPMath || Flags.hasAllowReassociation())) |
0 |
16637 |
(Options.UnsafeFPMath || Flags.hasAllowReassociation())) |
0 |
| 16638 |
if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0)) |
0 |
16638 |
if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0)) |
0 |
| 16639 |
return N1; |
0 |
16639 |
return N1; |
0 |
| 16640 |
|
--- |
16640 |
|
--- |
| 16641 |
// (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) |
--- |
16641 |
// (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) |
--- |
| 16642 |
TargetLowering::NegatibleCost CostN0 = |
0 |
16642 |
TargetLowering::NegatibleCost CostN0 = |
0 |
| 16643 |
TargetLowering::NegatibleCost::Expensive; |
--- |
16643 |
TargetLowering::NegatibleCost::Expensive; |
--- |
| 16644 |
TargetLowering::NegatibleCost CostN1 = |
0 |
16644 |
TargetLowering::NegatibleCost CostN1 = |
0 |
| 16645 |
TargetLowering::NegatibleCost::Expensive; |
--- |
16645 |
TargetLowering::NegatibleCost::Expensive; |
--- |
| 16646 |
SDValue NegN0 = |
--- |
16646 |
SDValue NegN0 = |
--- |
| 16647 |
TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize, CostN0); |
0 |
16647 |
TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize, CostN0); |
0 |
| 16648 |
if (NegN0) { |
0 |
16648 |
if (NegN0) { |
0 |
| 16649 |
HandleSDNode NegN0Handle(NegN0); |
0 |
16649 |
HandleSDNode NegN0Handle(NegN0); |
0 |
| 16650 |
SDValue NegN1 = |
--- |
16650 |
SDValue NegN1 = |
--- |
| 16651 |
TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize, CostN1); |
0 |
16651 |
TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize, CostN1); |
0 |
| 16652 |
if (NegN1 && (CostN0 == TargetLowering::NegatibleCost::Cheaper || |
0 |
16652 |
if (NegN1 && (CostN0 == TargetLowering::NegatibleCost::Cheaper || |
0 |
| 16653 |
CostN1 == TargetLowering::NegatibleCost::Cheaper)) |
0 |
16653 |
CostN1 == TargetLowering::NegatibleCost::Cheaper)) |
0 |
| 16654 |
return DAG.getNode(ISD::FDIV, SDLoc(N), VT, NegN0, NegN1); |
0 |
16654 |
return DAG.getNode(ISD::FDIV, SDLoc(N), VT, NegN0, NegN1); |
0 |
| 16655 |
} |
0 |
16655 |
} |
0 |
| 16656 |
|
--- |
16656 |
|
--- |
| 16657 |
return SDValue(); |
0 |
16657 |
return SDValue(); |
0 |
| 16658 |
} |
0 |
16658 |
} |
0 |
| 16659 |
|
--- |
16659 |
|
--- |
| 16660 |
SDValue DAGCombiner::visitFREM(SDNode *N) { |
0 |
16660 |
SDValue DAGCombiner::visitFREM(SDNode *N) { |
0 |
| 16661 |
SDValue N0 = N->getOperand(0); |
0 |
16661 |
SDValue N0 = N->getOperand(0); |
0 |
| 16662 |
SDValue N1 = N->getOperand(1); |
0 |
16662 |
SDValue N1 = N->getOperand(1); |
0 |
| 16663 |
EVT VT = N->getValueType(0); |
0 |
16663 |
EVT VT = N->getValueType(0); |
0 |
| 16664 |
SDNodeFlags Flags = N->getFlags(); |
0 |
16664 |
SDNodeFlags Flags = N->getFlags(); |
0 |
| 16665 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
16665 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
| 16666 |
|
--- |
16666 |
|
--- |
| 16667 |
if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) |
0 |
16667 |
if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) |
0 |
| 16668 |
return R; |
0 |
16668 |
return R; |
0 |
| 16669 |
|
--- |
16669 |
|
--- |
| 16670 |
// fold (frem c1, c2) -> fmod(c1,c2) |
--- |
16670 |
// fold (frem c1, c2) -> fmod(c1,c2) |
--- |
| 16671 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FREM, SDLoc(N), VT, {N0, N1})) |
0 |
16671 |
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FREM, SDLoc(N), VT, {N0, N1})) |
0 |
| 16672 |
return C; |
0 |
16672 |
return C; |
0 |
| 16673 |
|
--- |
16673 |
|
--- |
| 16674 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
16674 |
if (SDValue NewSel = foldBinOpIntoSelect(N)) |
0 |
| 16675 |
return NewSel; |
0 |
16675 |
return NewSel; |
0 |
| 16676 |
|
--- |
16676 |
|
--- |
| 16677 |
return SDValue(); |
0 |
16677 |
return SDValue(); |
0 |
| 16678 |
} |
0 |
16678 |
} |
0 |
| 16679 |
|
--- |
16679 |
|
--- |
| 16680 |
SDValue DAGCombiner::visitFSQRT(SDNode *N) { |
0 |
16680 |
SDValue DAGCombiner::visitFSQRT(SDNode *N) { |
0 |
| 16681 |
SDNodeFlags Flags = N->getFlags(); |
0 |
16681 |
SDNodeFlags Flags = N->getFlags(); |
0 |
| 16682 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
16682 |
const TargetOptions &Options = DAG.getTarget().Options; |
0 |
| 16683 |
|
--- |
16683 |
|
--- |
| 16684 |
// Require 'ninf' flag since sqrt(+Inf) = +Inf, but the estimation goes as: |
--- |
16684 |
// Require 'ninf' flag since sqrt(+Inf) = +Inf, but the estimation goes as: |
--- |
| 16685 |
// sqrt(+Inf) == rsqrt(+Inf) * +Inf = 0 * +Inf = NaN |
--- |
16685 |
// sqrt(+Inf) == rsqrt(+Inf) * +Inf = 0 * +Inf = NaN |
--- |
| 16686 |
if (!Flags.hasApproximateFuncs() || |
0 |
16686 |
if (!Flags.hasApproximateFuncs() || |
0 |
| 16687 |
(!Options.NoInfsFPMath && !Flags.hasNoInfs())) |
0 |
16687 |
(!Options.NoInfsFPMath && !Flags.hasNoInfs())) |
0 |
| 16688 |
return SDValue(); |
0 |
16688 |
return SDValue(); |
0 |
| 16689 |
|
--- |
16689 |
|
--- |
| 16690 |
SDValue N0 = N->getOperand(0); |
0 |
16690 |
SDValue N0 = N->getOperand(0); |
0 |
| 16691 |
if (TLI.isFsqrtCheap(N0, DAG)) |
0 |
16691 |
if (TLI.isFsqrtCheap(N0, DAG)) |
0 |
| 16692 |
return SDValue(); |
0 |
16692 |
return SDValue(); |
0 |
| 16693 |
|
--- |
16693 |
|
--- |
| 16694 |
// FSQRT nodes have flags that propagate to the created nodes. |
--- |
16694 |
// FSQRT nodes have flags that propagate to the created nodes. |
--- |
| 16695 |
// TODO: If this is N0/sqrt(N0), and we reach this node before trying to |
--- |
16695 |
// TODO: If this is N0/sqrt(N0), and we reach this node before trying to |
--- |
| 16696 |
// transform the fdiv, we may produce a sub-optimal estimate sequence |
--- |
16696 |
// transform the fdiv, we may produce a sub-optimal estimate sequence |
--- |
| 16697 |
// because the reciprocal calculation may not have to filter out a |
--- |
16697 |
// because the reciprocal calculation may not have to filter out a |
--- |
| 16698 |
// 0.0 input. |
--- |
16698 |
// 0.0 input. |
--- |
| 16699 |
return buildSqrtEstimate(N0, Flags); |
0 |
16699 |
return buildSqrtEstimate(N0, Flags); |
0 |
| 16700 |
} |
--- |
16700 |
} |
--- |
| 16701 |
|
--- |
16701 |
|
--- |
| 16702 |
/// copysign(x, fp_extend(y)) -> copysign(x, y) |
--- |
16702 |
/// copysign(x, fp_extend(y)) -> copysign(x, y) |
--- |
| 16703 |
/// copysign(x, fp_round(y)) -> copysign(x, y) |
--- |
16703 |
/// copysign(x, fp_round(y)) -> copysign(x, y) |
--- |
| 16704 |
/// Operands to the functions are the type of X and Y respectively. |
--- |
16704 |
/// Operands to the functions are the type of X and Y respectively. |
--- |
| 16705 |
static inline bool CanCombineFCOPYSIGN_EXTEND_ROUND(EVT XTy, EVT YTy) { |
0 |
16705 |
static inline bool CanCombineFCOPYSIGN_EXTEND_ROUND(EVT XTy, EVT YTy) { |
0 |
| 16706 |
// Always fold no-op FP casts. |
--- |
16706 |
// Always fold no-op FP casts. |
--- |
| 16707 |
if (XTy == YTy) |
0 |
16707 |
if (XTy == YTy) |
0 |
| 16708 |
return true; |
0 |
16708 |
return true; |
0 |
| 16709 |
|
--- |
16709 |
|
--- |
| 16710 |
// Do not optimize out type conversion of f128 type yet. |
--- |
16710 |
// Do not optimize out type conversion of f128 type yet. |
--- |
| 16711 |
// For some targets like x86_64, configuration is changed to keep one f128 |
--- |
16711 |
// For some targets like x86_64, configuration is changed to keep one f128 |
--- |
| 16712 |
// value in one SSE register, but instruction selection cannot handle |
--- |
16712 |
// value in one SSE register, but instruction selection cannot handle |
--- |
| 16713 |
// FCOPYSIGN on SSE registers yet. |
--- |
16713 |
// FCOPYSIGN on SSE registers yet. |
--- |
| 16714 |
if (YTy == MVT::f128) |
0 |
16714 |
if (YTy == MVT::f128) |
0 |
| 16715 |
return false; |
0 |
16715 |
return false; |
0 |
| 16716 |
|
--- |
16716 |
|
--- |
| 16717 |
return !YTy.isVector() || EnableVectorFCopySignExtendRound; |
0 |
16717 |
return !YTy.isVector() || EnableVectorFCopySignExtendRound; |
0 |
| 16718 |
} |
--- |
16718 |
} |
--- |
| 16719 |
|
--- |
16719 |
|
--- |
| 16720 |
static inline bool CanCombineFCOPYSIGN_EXTEND_ROUND(SDNode *N) { |
0 |
16720 |
static inline bool CanCombineFCOPYSIGN_EXTEND_ROUND(SDNode *N) { |
0 |
| 16721 |
SDValue N1 = N->getOperand(1); |
0 |
16721 |
SDValue N1 = N->getOperand(1); |
0 |
| 16722 |
if (N1.getOpcode() != ISD::FP_EXTEND && |
0 |
16722 |
if (N1.getOpcode() != ISD::FP_EXTEND && |
0 |
| 16723 |
N1.getOpcode() != ISD::FP_ROUND) |
0 |
16723 |
N1.getOpcode() != ISD::FP_ROUND) |
0 |
| 16724 |
return false; |
0 |
16724 |
return false; |
0 |
| 16725 |
EVT N1VT = N1->getValueType(0); |
0 |
16725 |
EVT N1VT = N1->getValueType(0); |
0 |
| 16726 |
EVT N1Op0VT = N1->getOperand(0).getValueType(); |
0 |
16726 |
EVT N1Op0VT = N1->getOperand(0).getValueType(); |
0 |
| 16727 |
return CanCombineFCOPYSIGN_EXTEND_ROUND(N1VT, N1Op0VT); |
0 |
16727 |
return CanCombineFCOPYSIGN_EXTEND_ROUND(N1VT, N1Op0VT); |
0 |
| 16728 |
} |
--- |
16728 |
} |
--- |
| 16729 |
|
--- |
16729 |
|
--- |
| 16730 |
SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { |
0 |
16730 |
SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { |
0 |
| 16731 |
SDValue N0 = N->getOperand(0); |
0 |
16731 |
SDValue N0 = N->getOperand(0); |
0 |
| 16732 |
SDValue N1 = N->getOperand(1); |
0 |
16732 |
SDValue N1 = N->getOperand(1); |
0 |
| 16733 |
EVT VT = N->getValueType(0); |
0 |
16733 |
EVT VT = N->getValueType(0); |
0 |
| 16734 |
|
--- |
16734 |
|
--- |
| 16735 |
// fold (fcopysign c1, c2) -> fcopysign(c1,c2) |
--- |
16735 |
// fold (fcopysign c1, c2) -> fcopysign(c1,c2) |
--- |
| 16736 |
if (SDValue C = |
0 |
16736 |
if (SDValue C = |
0 |
| 16737 |
DAG.FoldConstantArithmetic(ISD::FCOPYSIGN, SDLoc(N), VT, {N0, N1})) |
0 |
16737 |
DAG.FoldConstantArithmetic(ISD::FCOPYSIGN, SDLoc(N), VT, {N0, N1})) |
0 |
| 16738 |
return C; |
0 |
16738 |
return C; |
0 |
| 16739 |
|
--- |
16739 |
|
--- |
| 16740 |
if (ConstantFPSDNode *N1C = isConstOrConstSplatFP(N->getOperand(1))) { |
0 |
16740 |
if (ConstantFPSDNode *N1C = isConstOrConstSplatFP(N->getOperand(1))) { |
0 |
| 16741 |
const APFloat &V = N1C->getValueAPF(); |
0 |
16741 |
const APFloat &V = N1C->getValueAPF(); |
0 |
| 16742 |
// copysign(x, c1) -> fabs(x) iff ispos(c1) |
--- |
16742 |
// copysign(x, c1) -> fabs(x) iff ispos(c1) |
--- |
| 16743 |
// copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) |
--- |
16743 |
// copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) |
--- |
| 16744 |
if (!V.isNegative()) { |
0 |
16744 |
if (!V.isNegative()) { |
0 |
| 16745 |
if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) |
0 |
16745 |
if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) |
0 |
| 16746 |
return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); |
0 |
16746 |
return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); |
0 |
| 16747 |
} else { |
--- |
16747 |
} else { |
--- |
| 16748 |
if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) |
0 |
16748 |
if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) |
0 |
| 16749 |
return DAG.getNode(ISD::FNEG, SDLoc(N), VT, |
0 |
16749 |
return DAG.getNode(ISD::FNEG, SDLoc(N), VT, |
0 |
| 16750 |
DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0)); |
0 |
16750 |
DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0)); |
0 |
| 16751 |
} |
--- |
16751 |
} |
--- |
| 16752 |
} |
--- |
16752 |
} |
--- |
| 16753 |
|
--- |
16753 |
|
--- |
| 16754 |
// copysign(fabs(x), y) -> copysign(x, y) |
--- |
16754 |
// copysign(fabs(x), y) -> copysign(x, y) |
--- |
| 16755 |
// copysign(fneg(x), y) -> copysign(x, y) |
--- |
16755 |
// copysign(fneg(x), y) -> copysign(x, y) |
--- |
| 16756 |
// copysign(copysign(x,z), y) -> copysign(x, y) |
--- |
16756 |
// copysign(copysign(x,z), y) -> copysign(x, y) |
--- |
| 16757 |
if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || |
0 |
16757 |
if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || |
0 |
| 16758 |
N0.getOpcode() == ISD::FCOPYSIGN) |
0 |
16758 |
N0.getOpcode() == ISD::FCOPYSIGN) |
0 |
| 16759 |
return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0.getOperand(0), N1); |
0 |
16759 |
return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0.getOperand(0), N1); |
0 |
| 16760 |
|
--- |
16760 |
|
--- |
| 16761 |
// copysign(x, abs(y)) -> abs(x) |
--- |
16761 |
// copysign(x, abs(y)) -> abs(x) |
--- |
| 16762 |
if (N1.getOpcode() == ISD::FABS) |
0 |
16762 |
if (N1.getOpcode() == ISD::FABS) |
0 |
| 16763 |
return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); |
0 |
16763 |
return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); |
0 |
| 16764 |
|
--- |
16764 |
|
--- |
| 16765 |
// copysign(x, copysign(y,z)) -> copysign(x, z) |
--- |
16765 |
// copysign(x, copysign(y,z)) -> copysign(x, z) |
--- |
| 16766 |
if (N1.getOpcode() == ISD::FCOPYSIGN) |
0 |
16766 |
if (N1.getOpcode() == ISD::FCOPYSIGN) |
0 |
| 16767 |
return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(1)); |
0 |
16767 |
return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(1)); |
0 |
| 16768 |
|
--- |
16768 |
|
--- |
| 16769 |
// copysign(x, fp_extend(y)) -> copysign(x, y) |
--- |
16769 |
// copysign(x, fp_extend(y)) -> copysign(x, y) |
--- |
| 16770 |
// copysign(x, fp_round(y)) -> copysign(x, y) |
--- |
16770 |
// copysign(x, fp_round(y)) -> copysign(x, y) |
--- |
| 16771 |
if (CanCombineFCOPYSIGN_EXTEND_ROUND(N)) |
0 |
16771 |
if (CanCombineFCOPYSIGN_EXTEND_ROUND(N)) |
0 |
| 16772 |
return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(0)); |
0 |
16772 |
return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(0)); |
0 |
| 16773 |
|
--- |
16773 |
|
--- |
| 16774 |
return SDValue(); |
0 |
16774 |
return SDValue(); |
0 |
| 16775 |
} |
--- |
16775 |
} |
--- |
| 16776 |
|
--- |
16776 |
|
--- |
| 16777 |
SDValue DAGCombiner::visitFPOW(SDNode *N) { |
0 |
16777 |
SDValue DAGCombiner::visitFPOW(SDNode *N) { |
0 |
| 16778 |
ConstantFPSDNode *ExponentC = isConstOrConstSplatFP(N->getOperand(1)); |
0 |
16778 |
ConstantFPSDNode *ExponentC = isConstOrConstSplatFP(N->getOperand(1)); |
0 |
| 16779 |
if (!ExponentC) |
0 |
16779 |
if (!ExponentC) |
0 |
| 16780 |
return SDValue(); |
0 |
16780 |
return SDValue(); |
0 |
| 16781 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
16781 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
| 16782 |
|
--- |
16782 |
|
--- |
| 16783 |
// Try to convert x ** (1/3) into cube root. |
--- |
16783 |
// Try to convert x ** (1/3) into cube root. |
--- |
| 16784 |
// TODO: Handle the various flavors of long double. |
--- |
16784 |
// TODO: Handle the various flavors of long double. |
--- |
| 16785 |
// TODO: Since we're approximating, we don't need an exact 1/3 exponent. |
--- |
16785 |
// TODO: Since we're approximating, we don't need an exact 1/3 exponent. |
--- |
| 16786 |
// Some range near 1/3 should be fine. |
--- |
16786 |
// Some range near 1/3 should be fine. |
--- |
| 16787 |
EVT VT = N->getValueType(0); |
0 |
16787 |
EVT VT = N->getValueType(0); |
0 |
| 16788 |
if ((VT == MVT::f32 && ExponentC->getValueAPF().isExactlyValue(1.0f/3.0f)) || |
0 |
16788 |
if ((VT == MVT::f32 && ExponentC->getValueAPF().isExactlyValue(1.0f/3.0f)) || |
0 |
| 16789 |
(VT == MVT::f64 && ExponentC->getValueAPF().isExactlyValue(1.0/3.0))) { |
0 |
16789 |
(VT == MVT::f64 && ExponentC->getValueAPF().isExactlyValue(1.0/3.0))) { |
0 |
| 16790 |
// pow(-0.0, 1/3) = +0.0; cbrt(-0.0) = -0.0. |
--- |
16790 |
// pow(-0.0, 1/3) = +0.0; cbrt(-0.0) = -0.0. |
--- |
| 16791 |
// pow(-inf, 1/3) = +inf; cbrt(-inf) = -inf. |
--- |
16791 |
// pow(-inf, 1/3) = +inf; cbrt(-inf) = -inf. |
--- |
| 16792 |
// pow(-val, 1/3) = nan; cbrt(-val) = -num. |
--- |
16792 |
// pow(-val, 1/3) = nan; cbrt(-val) = -num. |
--- |
| 16793 |
// For regular numbers, rounding may cause the results to differ. |
--- |
16793 |
// For regular numbers, rounding may cause the results to differ. |
--- |
| 16794 |
// Therefore, we require { nsz ninf nnan afn } for this transform. |
--- |
16794 |
// Therefore, we require { nsz ninf nnan afn } for this transform. |
--- |
| 16795 |
// TODO: We could select out the special cases if we don't have nsz/ninf. |
--- |
16795 |
// TODO: We could select out the special cases if we don't have nsz/ninf. |
--- |
| 16796 |
SDNodeFlags Flags = N->getFlags(); |
0 |
16796 |
SDNodeFlags Flags = N->getFlags(); |
0 |
| 16797 |
if (!Flags.hasNoSignedZeros() || !Flags.hasNoInfs() || !Flags.hasNoNaNs() || |
0 |
16797 |
if (!Flags.hasNoSignedZeros() || !Flags.hasNoInfs() || !Flags.hasNoNaNs() || |
0 |
| 16798 |
!Flags.hasApproximateFuncs()) |
0 |
16798 |
!Flags.hasApproximateFuncs()) |
0 |
| 16799 |
return SDValue(); |
0 |
16799 |
return SDValue(); |
0 |
| 16800 |
|
--- |
16800 |
|
--- |
| 16801 |
// Do not create a cbrt() libcall if the target does not have it, and do not |
--- |
16801 |
// Do not create a cbrt() libcall if the target does not have it, and do not |
--- |
| 16802 |
// turn a pow that has lowering support into a cbrt() libcall. |
--- |
16802 |
// turn a pow that has lowering support into a cbrt() libcall. |
--- |
| 16803 |
if (!DAG.getLibInfo().has(LibFunc_cbrt) || |
0 |
16803 |
if (!DAG.getLibInfo().has(LibFunc_cbrt) || |
0 |
| 16804 |
(!DAG.getTargetLoweringInfo().isOperationExpand(ISD::FPOW, VT) && |
0 |
16804 |
(!DAG.getTargetLoweringInfo().isOperationExpand(ISD::FPOW, VT) && |
0 |
| 16805 |
DAG.getTargetLoweringInfo().isOperationExpand(ISD::FCBRT, VT))) |
0 |
16805 |
DAG.getTargetLoweringInfo().isOperationExpand(ISD::FCBRT, VT))) |
0 |
| 16806 |
return SDValue(); |
0 |
16806 |
return SDValue(); |
0 |
| 16807 |
|
--- |
16807 |
|
--- |
| 16808 |
return DAG.getNode(ISD::FCBRT, SDLoc(N), VT, N->getOperand(0)); |
0 |
16808 |
return DAG.getNode(ISD::FCBRT, SDLoc(N), VT, N->getOperand(0)); |
0 |
| 16809 |
} |
--- |
16809 |
} |
--- |
| 16810 |
|
--- |
16810 |
|
--- |
| 16811 |
// Try to convert x ** (1/4) and x ** (3/4) into square roots. |
--- |
16811 |
// Try to convert x ** (1/4) and x ** (3/4) into square roots. |
--- |
| 16812 |
// x ** (1/2) is canonicalized to sqrt, so we do not bother with that case. |
--- |
16812 |
// x ** (1/2) is canonicalized to sqrt, so we do not bother with that case. |
--- |
| 16813 |
// TODO: This could be extended (using a target hook) to handle smaller |
--- |
16813 |
// TODO: This could be extended (using a target hook) to handle smaller |
--- |
| 16814 |
// power-of-2 fractional exponents. |
--- |
16814 |
// power-of-2 fractional exponents. |
--- |
| 16815 |
bool ExponentIs025 = ExponentC->getValueAPF().isExactlyValue(0.25); |
0 |
16815 |
bool ExponentIs025 = ExponentC->getValueAPF().isExactlyValue(0.25); |
0 |
| 16816 |
bool ExponentIs075 = ExponentC->getValueAPF().isExactlyValue(0.75); |
0 |
16816 |
bool ExponentIs075 = ExponentC->getValueAPF().isExactlyValue(0.75); |
0 |
| 16817 |
if (ExponentIs025 || ExponentIs075) { |
0 |
16817 |
if (ExponentIs025 || ExponentIs075) { |
0 |
| 16818 |
// pow(-0.0, 0.25) = +0.0; sqrt(sqrt(-0.0)) = -0.0. |
--- |
16818 |
// pow(-0.0, 0.25) = +0.0; sqrt(sqrt(-0.0)) = -0.0. |
--- |
| 16819 |
// pow(-inf, 0.25) = +inf; sqrt(sqrt(-inf)) = NaN. |
--- |
16819 |
// pow(-inf, 0.25) = +inf; sqrt(sqrt(-inf)) = NaN. |
--- |
| 16820 |
// pow(-0.0, 0.75) = +0.0; sqrt(-0.0) * sqrt(sqrt(-0.0)) = +0.0. |
--- |
16820 |
// pow(-0.0, 0.75) = +0.0; sqrt(-0.0) * sqrt(sqrt(-0.0)) = +0.0. |
--- |
| 16821 |
// pow(-inf, 0.75) = +inf; sqrt(-inf) * sqrt(sqrt(-inf)) = NaN. |
--- |
16821 |
// pow(-inf, 0.75) = +inf; sqrt(-inf) * sqrt(sqrt(-inf)) = NaN. |
--- |
| 16822 |
// For regular numbers, rounding may cause the results to differ. |
--- |
16822 |
// For regular numbers, rounding may cause the results to differ. |
--- |
| 16823 |
// Therefore, we require { nsz ninf afn } for this transform. |
--- |
16823 |
// Therefore, we require { nsz ninf afn } for this transform. |
--- |
| 16824 |
// TODO: We could select out the special cases if we don't have nsz/ninf. |
--- |
16824 |
// TODO: We could select out the special cases if we don't have nsz/ninf. |
--- |
| 16825 |
SDNodeFlags Flags = N->getFlags(); |
0 |
16825 |
SDNodeFlags Flags = N->getFlags(); |
0 |
| 16826 |
|
--- |
16826 |
|
--- |
| 16827 |
// We only need no signed zeros for the 0.25 case. |
--- |
16827 |
// We only need no signed zeros for the 0.25 case. |
--- |
| 16828 |
if ((!Flags.hasNoSignedZeros() && ExponentIs025) || !Flags.hasNoInfs() || |
0 |
16828 |
if ((!Flags.hasNoSignedZeros() && ExponentIs025) || !Flags.hasNoInfs() || |
0 |
| 16829 |
!Flags.hasApproximateFuncs()) |
0 |
16829 |
!Flags.hasApproximateFuncs()) |
0 |
| 16830 |
return SDValue(); |
0 |
16830 |
return SDValue(); |
0 |
| 16831 |
|
--- |
16831 |
|
--- |
| 16832 |
// Don't double the number of libcalls. We are trying to inline fast code. |
--- |
16832 |
// Don't double the number of libcalls. We are trying to inline fast code. |
--- |
| 16833 |
if (!DAG.getTargetLoweringInfo().isOperationLegalOrCustom(ISD::FSQRT, VT)) |
0 |
16833 |
if (!DAG.getTargetLoweringInfo().isOperationLegalOrCustom(ISD::FSQRT, VT)) |
0 |
| 16834 |
return SDValue(); |
0 |
16834 |
return SDValue(); |
0 |
| 16835 |
|
--- |
16835 |
|
--- |
| 16836 |
// Assume that libcalls are the smallest code. |
--- |
16836 |
// Assume that libcalls are the smallest code. |
--- |
| 16837 |
// TODO: This restriction should probably be lifted for vectors. |
--- |
16837 |
// TODO: This restriction should probably be lifted for vectors. |
--- |
| 16838 |
if (ForCodeSize) |
0 |
16838 |
if (ForCodeSize) |
0 |
| 16839 |
return SDValue(); |
0 |
16839 |
return SDValue(); |
0 |
| 16840 |
|
--- |
16840 |
|
--- |
| 16841 |
// pow(X, 0.25) --> sqrt(sqrt(X)) |
--- |
16841 |
// pow(X, 0.25) --> sqrt(sqrt(X)) |
--- |
| 16842 |
SDLoc DL(N); |
0 |
16842 |
SDLoc DL(N); |
0 |
| 16843 |
SDValue Sqrt = DAG.getNode(ISD::FSQRT, DL, VT, N->getOperand(0)); |
0 |
16843 |
SDValue Sqrt = DAG.getNode(ISD::FSQRT, DL, VT, N->getOperand(0)); |
0 |
| 16844 |
SDValue SqrtSqrt = DAG.getNode(ISD::FSQRT, DL, VT, Sqrt); |
0 |
16844 |
SDValue SqrtSqrt = DAG.getNode(ISD::FSQRT, DL, VT, Sqrt); |
0 |
| 16845 |
if (ExponentIs025) |
0 |
16845 |
if (ExponentIs025) |
0 |
| 16846 |
return SqrtSqrt; |
0 |
16846 |
return SqrtSqrt; |
0 |
| 16847 |
// pow(X, 0.75) --> sqrt(X) * sqrt(sqrt(X)) |
--- |
16847 |
// pow(X, 0.75) --> sqrt(X) * sqrt(sqrt(X)) |
--- |
| 16848 |
return DAG.getNode(ISD::FMUL, DL, VT, Sqrt, SqrtSqrt); |
0 |
16848 |
return DAG.getNode(ISD::FMUL, DL, VT, Sqrt, SqrtSqrt); |
0 |
| 16849 |
} |
0 |
16849 |
} |
0 |
| 16850 |
|
--- |
16850 |
|
--- |
| 16851 |
return SDValue(); |
0 |
16851 |
return SDValue(); |
0 |
| 16852 |
} |
0 |
16852 |
} |
0 |
| 16853 |
|
--- |
16853 |
|
--- |
| 16854 |
static SDValue foldFPToIntToFP(SDNode *N, SelectionDAG &DAG, |
0 |
16854 |
static SDValue foldFPToIntToFP(SDNode *N, SelectionDAG &DAG, |
0 |
| 16855 |
const TargetLowering &TLI) { |
--- |
16855 |
const TargetLowering &TLI) { |
--- |
| 16856 |
// We only do this if the target has legal ftrunc. Otherwise, we'd likely be |
--- |
16856 |
// We only do this if the target has legal ftrunc. Otherwise, we'd likely be |
--- |
| 16857 |
// replacing casts with a libcall. We also must be allowed to ignore -0.0 |
--- |
16857 |
// replacing casts with a libcall. We also must be allowed to ignore -0.0 |
--- |
| 16858 |
// because FTRUNC will return -0.0 for (-1.0, -0.0), but using integer |
--- |
16858 |
// because FTRUNC will return -0.0 for (-1.0, -0.0), but using integer |
--- |
| 16859 |
// conversions would return +0.0. |
--- |
16859 |
// conversions would return +0.0. |
--- |
| 16860 |
// FIXME: We should be able to use node-level FMF here. |
--- |
16860 |
// FIXME: We should be able to use node-level FMF here. |
--- |
| 16861 |
// TODO: If strict math, should we use FABS (+ range check for signed cast)? |
--- |
16861 |
// TODO: If strict math, should we use FABS (+ range check for signed cast)? |
--- |
| 16862 |
EVT VT = N->getValueType(0); |
0 |
16862 |
EVT VT = N->getValueType(0); |
0 |
| 16863 |
if (!TLI.isOperationLegal(ISD::FTRUNC, VT) || |
0 |
16863 |
if (!TLI.isOperationLegal(ISD::FTRUNC, VT) || |
0 |
| 16864 |
!DAG.getTarget().Options.NoSignedZerosFPMath) |
0 |
16864 |
!DAG.getTarget().Options.NoSignedZerosFPMath) |
0 |
| 16865 |
return SDValue(); |
0 |
16865 |
return SDValue(); |
0 |
| 16866 |
|
--- |
16866 |
|
--- |
| 16867 |
// fptosi/fptoui round towards zero, so converting from FP to integer and |
--- |
16867 |
// fptosi/fptoui round towards zero, so converting from FP to integer and |
--- |
| 16868 |
// back is the same as an 'ftrunc': [us]itofp (fpto[us]i X) --> ftrunc X |
--- |
16868 |
// back is the same as an 'ftrunc': [us]itofp (fpto[us]i X) --> ftrunc X |
--- |
| 16869 |
SDValue N0 = N->getOperand(0); |
0 |
16869 |
SDValue N0 = N->getOperand(0); |
0 |
| 16870 |
if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT && |
0 |
16870 |
if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT && |
0 |
| 16871 |
N0.getOperand(0).getValueType() == VT) |
0 |
16871 |
N0.getOperand(0).getValueType() == VT) |
0 |
| 16872 |
return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0)); |
0 |
16872 |
return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0)); |
0 |
| 16873 |
|
--- |
16873 |
|
--- |
| 16874 |
if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT && |
0 |
16874 |
if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT && |
0 |
| 16875 |
N0.getOperand(0).getValueType() == VT) |
0 |
16875 |
N0.getOperand(0).getValueType() == VT) |
0 |
| 16876 |
return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0)); |
0 |
16876 |
return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0)); |
0 |
| 16877 |
|
--- |
16877 |
|
--- |
| 16878 |
return SDValue(); |
0 |
16878 |
return SDValue(); |
0 |
| 16879 |
} |
--- |
16879 |
} |
--- |
| 16880 |
|
--- |
16880 |
|
--- |
| 16881 |
SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { |
0 |
16881 |
SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { |
0 |
| 16882 |
SDValue N0 = N->getOperand(0); |
0 |
16882 |
SDValue N0 = N->getOperand(0); |
0 |
| 16883 |
EVT VT = N->getValueType(0); |
0 |
16883 |
EVT VT = N->getValueType(0); |
0 |
| 16884 |
EVT OpVT = N0.getValueType(); |
0 |
16884 |
EVT OpVT = N0.getValueType(); |
0 |
| 16885 |
|
--- |
16885 |
|
--- |
| 16886 |
// [us]itofp(undef) = 0, because the result value is bounded. |
--- |
16886 |
// [us]itofp(undef) = 0, because the result value is bounded. |
--- |
| 16887 |
if (N0.isUndef()) |
0 |
16887 |
if (N0.isUndef()) |
0 |
| 16888 |
return DAG.getConstantFP(0.0, SDLoc(N), VT); |
0 |
16888 |
return DAG.getConstantFP(0.0, SDLoc(N), VT); |
0 |
| 16889 |
|
--- |
16889 |
|
--- |
| 16890 |
// fold (sint_to_fp c1) -> c1fp |
--- |
16890 |
// fold (sint_to_fp c1) -> c1fp |
--- |
| 16891 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
16891 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 16892 |
// ...but only if the target supports immediate floating-point values |
--- |
16892 |
// ...but only if the target supports immediate floating-point values |
--- |
| 16893 |
(!LegalOperations || |
0 |
16893 |
(!LegalOperations || |
0 |
| 16894 |
TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) |
0 |
16894 |
TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) |
0 |
| 16895 |
return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); |
0 |
16895 |
return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); |
0 |
| 16896 |
|
--- |
16896 |
|
--- |
| 16897 |
// If the input is a legal type, and SINT_TO_FP is not legal on this target, |
--- |
16897 |
// If the input is a legal type, and SINT_TO_FP is not legal on this target, |
--- |
| 16898 |
// but UINT_TO_FP is legal on this target, try to convert. |
--- |
16898 |
// but UINT_TO_FP is legal on this target, try to convert. |
--- |
| 16899 |
if (!hasOperation(ISD::SINT_TO_FP, OpVT) && |
0 |
16899 |
if (!hasOperation(ISD::SINT_TO_FP, OpVT) && |
0 |
| 16900 |
hasOperation(ISD::UINT_TO_FP, OpVT)) { |
0 |
16900 |
hasOperation(ISD::UINT_TO_FP, OpVT)) { |
0 |
| 16901 |
// If the sign bit is known to be zero, we can change this to UINT_TO_FP. |
--- |
16901 |
// If the sign bit is known to be zero, we can change this to UINT_TO_FP. |
--- |
| 16902 |
if (DAG.SignBitIsZero(N0)) |
0 |
16902 |
if (DAG.SignBitIsZero(N0)) |
0 |
| 16903 |
return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); |
0 |
16903 |
return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); |
0 |
| 16904 |
} |
--- |
16904 |
} |
--- |
| 16905 |
|
--- |
16905 |
|
--- |
| 16906 |
// The next optimizations are desirable only if SELECT_CC can be lowered. |
--- |
16906 |
// The next optimizations are desirable only if SELECT_CC can be lowered. |
--- |
| 16907 |
// fold (sint_to_fp (setcc x, y, cc)) -> (select (setcc x, y, cc), -1.0, 0.0) |
--- |
16907 |
// fold (sint_to_fp (setcc x, y, cc)) -> (select (setcc x, y, cc), -1.0, 0.0) |
--- |
| 16908 |
if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && |
0 |
16908 |
if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && |
0 |
| 16909 |
!VT.isVector() && |
0 |
16909 |
!VT.isVector() && |
0 |
| 16910 |
(!LegalOperations || TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) { |
0 |
16910 |
(!LegalOperations || TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) { |
0 |
| 16911 |
SDLoc DL(N); |
0 |
16911 |
SDLoc DL(N); |
0 |
| 16912 |
return DAG.getSelect(DL, VT, N0, DAG.getConstantFP(-1.0, DL, VT), |
0 |
16912 |
return DAG.getSelect(DL, VT, N0, DAG.getConstantFP(-1.0, DL, VT), |
0 |
| 16913 |
DAG.getConstantFP(0.0, DL, VT)); |
0 |
16913 |
DAG.getConstantFP(0.0, DL, VT)); |
0 |
| 16914 |
} |
0 |
16914 |
} |
0 |
| 16915 |
|
--- |
16915 |
|
--- |
| 16916 |
// fold (sint_to_fp (zext (setcc x, y, cc))) -> |
--- |
16916 |
// fold (sint_to_fp (zext (setcc x, y, cc))) -> |
--- |
| 16917 |
// (select (setcc x, y, cc), 1.0, 0.0) |
--- |
16917 |
// (select (setcc x, y, cc), 1.0, 0.0) |
--- |
| 16918 |
if (N0.getOpcode() == ISD::ZERO_EXTEND && |
0 |
16918 |
if (N0.getOpcode() == ISD::ZERO_EXTEND && |
0 |
| 16919 |
N0.getOperand(0).getOpcode() == ISD::SETCC && !VT.isVector() && |
0 |
16919 |
N0.getOperand(0).getOpcode() == ISD::SETCC && !VT.isVector() && |
0 |
| 16920 |
(!LegalOperations || TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) { |
0 |
16920 |
(!LegalOperations || TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) { |
0 |
| 16921 |
SDLoc DL(N); |
0 |
16921 |
SDLoc DL(N); |
0 |
| 16922 |
return DAG.getSelect(DL, VT, N0.getOperand(0), |
0 |
16922 |
return DAG.getSelect(DL, VT, N0.getOperand(0), |
0 |
| 16923 |
DAG.getConstantFP(1.0, DL, VT), |
0 |
16923 |
DAG.getConstantFP(1.0, DL, VT), |
0 |
| 16924 |
DAG.getConstantFP(0.0, DL, VT)); |
0 |
16924 |
DAG.getConstantFP(0.0, DL, VT)); |
0 |
| 16925 |
} |
0 |
16925 |
} |
0 |
| 16926 |
|
--- |
16926 |
|
--- |
| 16927 |
if (SDValue FTrunc = foldFPToIntToFP(N, DAG, TLI)) |
0 |
16927 |
if (SDValue FTrunc = foldFPToIntToFP(N, DAG, TLI)) |
0 |
| 16928 |
return FTrunc; |
0 |
16928 |
return FTrunc; |
0 |
| 16929 |
|
--- |
16929 |
|
--- |
| 16930 |
return SDValue(); |
0 |
16930 |
return SDValue(); |
0 |
| 16931 |
} |
--- |
16931 |
} |
--- |
| 16932 |
|
--- |
16932 |
|
--- |
| 16933 |
SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { |
0 |
16933 |
SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { |
0 |
| 16934 |
SDValue N0 = N->getOperand(0); |
0 |
16934 |
SDValue N0 = N->getOperand(0); |
0 |
| 16935 |
EVT VT = N->getValueType(0); |
0 |
16935 |
EVT VT = N->getValueType(0); |
0 |
| 16936 |
EVT OpVT = N0.getValueType(); |
0 |
16936 |
EVT OpVT = N0.getValueType(); |
0 |
| 16937 |
|
--- |
16937 |
|
--- |
| 16938 |
// [us]itofp(undef) = 0, because the result value is bounded. |
--- |
16938 |
// [us]itofp(undef) = 0, because the result value is bounded. |
--- |
| 16939 |
if (N0.isUndef()) |
0 |
16939 |
if (N0.isUndef()) |
0 |
| 16940 |
return DAG.getConstantFP(0.0, SDLoc(N), VT); |
0 |
16940 |
return DAG.getConstantFP(0.0, SDLoc(N), VT); |
0 |
| 16941 |
|
--- |
16941 |
|
--- |
| 16942 |
// fold (uint_to_fp c1) -> c1fp |
--- |
16942 |
// fold (uint_to_fp c1) -> c1fp |
--- |
| 16943 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
16943 |
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && |
0 |
| 16944 |
// ...but only if the target supports immediate floating-point values |
--- |
16944 |
// ...but only if the target supports immediate floating-point values |
--- |
| 16945 |
(!LegalOperations || |
0 |
16945 |
(!LegalOperations || |
0 |
| 16946 |
TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) |
0 |
16946 |
TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) |
0 |
| 16947 |
return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); |
0 |
16947 |
return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); |
0 |
| 16948 |
|
--- |
16948 |
|
--- |
| 16949 |
// If the input is a legal type, and UINT_TO_FP is not legal on this target, |
--- |
16949 |
// If the input is a legal type, and UINT_TO_FP is not legal on this target, |
--- |
| 16950 |
// but SINT_TO_FP is legal on this target, try to convert. |
--- |
16950 |
// but SINT_TO_FP is legal on this target, try to convert. |
--- |
| 16951 |
if (!hasOperation(ISD::UINT_TO_FP, OpVT) && |
0 |
16951 |
if (!hasOperation(ISD::UINT_TO_FP, OpVT) && |
0 |
| 16952 |
hasOperation(ISD::SINT_TO_FP, OpVT)) { |
0 |
16952 |
hasOperation(ISD::SINT_TO_FP, OpVT)) { |
0 |
| 16953 |
// If the sign bit is known to be zero, we can change this to SINT_TO_FP. |
--- |
16953 |
// If the sign bit is known to be zero, we can change this to SINT_TO_FP. |
--- |
| 16954 |
if (DAG.SignBitIsZero(N0)) |
0 |
16954 |
if (DAG.SignBitIsZero(N0)) |
0 |
| 16955 |
return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); |
0 |
16955 |
return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); |
0 |
| 16956 |
} |
--- |
16956 |
} |
--- |
| 16957 |
|
--- |
16957 |
|
--- |
| 16958 |
// fold (uint_to_fp (setcc x, y, cc)) -> (select (setcc x, y, cc), 1.0, 0.0) |
--- |
16958 |
// fold (uint_to_fp (setcc x, y, cc)) -> (select (setcc x, y, cc), 1.0, 0.0) |
--- |
| 16959 |
if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && |
0 |
16959 |
if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && |
0 |
| 16960 |
(!LegalOperations || TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) { |
0 |
16960 |
(!LegalOperations || TLI.isOperationLegalOrCustom(ISD::ConstantFP, VT))) { |
0 |
| 16961 |
SDLoc DL(N); |
0 |
16961 |
SDLoc DL(N); |
0 |
| 16962 |
return DAG.getSelect(DL, VT, N0, DAG.getConstantFP(1.0, DL, VT), |
0 |
16962 |
return DAG.getSelect(DL, VT, N0, DAG.getConstantFP(1.0, DL, VT), |
0 |
| 16963 |
DAG.getConstantFP(0.0, DL, VT)); |
0 |
16963 |
DAG.getConstantFP(0.0, DL, VT)); |
0 |
| 16964 |
} |
0 |
16964 |
} |
0 |
| 16965 |
|
--- |
16965 |
|
--- |
| 16966 |
if (SDValue FTrunc = foldFPToIntToFP(N, DAG, TLI)) |
0 |
16966 |
if (SDValue FTrunc = foldFPToIntToFP(N, DAG, TLI)) |
0 |
| 16967 |
return FTrunc; |
0 |
16967 |
return FTrunc; |
0 |
| 16968 |
|
--- |
16968 |
|
--- |
| 16969 |
return SDValue(); |
0 |
16969 |
return SDValue(); |
0 |
| 16970 |
} |
--- |
16970 |
} |
--- |
| 16971 |
|
--- |
16971 |
|
--- |
| 16972 |
// Fold (fp_to_{s/u}int ({s/u}int_to_fpx)) -> zext x, sext x, trunc x, or x |
--- |
16972 |
// Fold (fp_to_{s/u}int ({s/u}int_to_fpx)) -> zext x, sext x, trunc x, or x |
--- |
| 16973 |
static SDValue FoldIntToFPToInt(SDNode *N, SelectionDAG &DAG) { |
0 |
16973 |
static SDValue FoldIntToFPToInt(SDNode *N, SelectionDAG &DAG) { |
0 |
| 16974 |
SDValue N0 = N->getOperand(0); |
0 |
16974 |
SDValue N0 = N->getOperand(0); |
0 |
| 16975 |
EVT VT = N->getValueType(0); |
0 |
16975 |
EVT VT = N->getValueType(0); |
0 |
| 16976 |
|
--- |
16976 |
|
--- |
| 16977 |
if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) |
0 |
16977 |
if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) |
0 |
| 16978 |
return SDValue(); |
0 |
16978 |
return SDValue(); |
0 |
| 16979 |
|
--- |
16979 |
|
--- |
| 16980 |
SDValue Src = N0.getOperand(0); |
0 |
16980 |
SDValue Src = N0.getOperand(0); |
0 |
| 16981 |
EVT SrcVT = Src.getValueType(); |
0 |
16981 |
EVT SrcVT = Src.getValueType(); |
0 |
| 16982 |
bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP; |
0 |
16982 |
bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP; |
0 |
| 16983 |
bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT; |
0 |
16983 |
bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT; |
0 |
| 16984 |
|
--- |
16984 |
|
--- |
| 16985 |
// We can safely assume the conversion won't overflow the output range, |
--- |
16985 |
// We can safely assume the conversion won't overflow the output range, |
--- |
| 16986 |
// because (for example) (uint8_t)18293.f is undefined behavior. |
--- |
16986 |
// because (for example) (uint8_t)18293.f is undefined behavior. |
--- |
| 16987 |
|
--- |
16987 |
|
--- |
| 16988 |
// Since we can assume the conversion won't overflow, our decision as to |
--- |
16988 |
// Since we can assume the conversion won't overflow, our decision as to |
--- |
| 16989 |
// whether the input will fit in the float should depend on the minimum |
--- |
16989 |
// whether the input will fit in the float should depend on the minimum |
--- |
| 16990 |
// of the input range and output range. |
--- |
16990 |
// of the input range and output range. |
--- |
| 16991 |
|
--- |
16991 |
|
--- |
| 16992 |
// This means this is also safe for a signed input and unsigned output, since |
--- |
16992 |
// This means this is also safe for a signed input and unsigned output, since |
--- |
| 16993 |
// a negative input would lead to undefined behavior. |
--- |
16993 |
// a negative input would lead to undefined behavior. |
--- |
| 16994 |
unsigned InputSize = (int)SrcVT.getScalarSizeInBits() - IsInputSigned; |
0 |
16994 |
unsigned InputSize = (int)SrcVT.getScalarSizeInBits() - IsInputSigned; |
0 |
| 16995 |
unsigned OutputSize = (int)VT.getScalarSizeInBits(); |
0 |
16995 |
unsigned OutputSize = (int)VT.getScalarSizeInBits(); |
0 |
| 16996 |
unsigned ActualSize = std::min(InputSize, OutputSize); |
0 |
16996 |
unsigned ActualSize = std::min(InputSize, OutputSize); |
0 |
| 16997 |
const fltSemantics &sem = DAG.EVTToAPFloatSemantics(N0.getValueType()); |
0 |
16997 |
const fltSemantics &sem = DAG.EVTToAPFloatSemantics(N0.getValueType()); |
0 |
| 16998 |
|
--- |
16998 |
|
--- |
| 16999 |
// We can only fold away the float conversion if the input range can be |
--- |
16999 |
// We can only fold away the float conversion if the input range can be |
--- |
| 17000 |
// represented exactly in the float range. |
--- |
17000 |
// represented exactly in the float range. |
--- |
| 17001 |
if (APFloat::semanticsPrecision(sem) >= ActualSize) { |
0 |
17001 |
if (APFloat::semanticsPrecision(sem) >= ActualSize) { |
0 |
| 17002 |
if (VT.getScalarSizeInBits() > SrcVT.getScalarSizeInBits()) { |
0 |
17002 |
if (VT.getScalarSizeInBits() > SrcVT.getScalarSizeInBits()) { |
0 |
| 17003 |
unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND |
0 |
17003 |
unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND |
0 |
| 17004 |
: ISD::ZERO_EXTEND; |
--- |
17004 |
: ISD::ZERO_EXTEND; |
--- |
| 17005 |
return DAG.getNode(ExtOp, SDLoc(N), VT, Src); |
0 |
17005 |
return DAG.getNode(ExtOp, SDLoc(N), VT, Src); |
0 |
| 17006 |
} |
--- |
17006 |
} |
--- |
| 17007 |
if (VT.getScalarSizeInBits() < SrcVT.getScalarSizeInBits()) |
0 |
17007 |
if (VT.getScalarSizeInBits() < SrcVT.getScalarSizeInBits()) |
0 |
| 17008 |
return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Src); |
0 |
17008 |
return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Src); |
0 |
| 17009 |
return DAG.getBitcast(VT, Src); |
0 |
17009 |
return DAG.getBitcast(VT, Src); |
0 |
| 17010 |
} |
--- |
17010 |
} |
--- |
| 17011 |
return SDValue(); |
0 |
17011 |
return SDValue(); |
0 |
| 17012 |
} |
--- |
17012 |
} |
--- |
| 17013 |
|
--- |
17013 |
|
--- |
| 17014 |
SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { |
0 |
17014 |
SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { |
0 |
| 17015 |
SDValue N0 = N->getOperand(0); |
0 |
17015 |
SDValue N0 = N->getOperand(0); |
0 |
| 17016 |
EVT VT = N->getValueType(0); |
0 |
17016 |
EVT VT = N->getValueType(0); |
0 |
| 17017 |
|
--- |
17017 |
|
--- |
| 17018 |
// fold (fp_to_sint undef) -> undef |
--- |
17018 |
// fold (fp_to_sint undef) -> undef |
--- |
| 17019 |
if (N0.isUndef()) |
0 |
17019 |
if (N0.isUndef()) |
0 |
| 17020 |
return DAG.getUNDEF(VT); |
0 |
17020 |
return DAG.getUNDEF(VT); |
0 |
| 17021 |
|
--- |
17021 |
|
--- |
| 17022 |
// fold (fp_to_sint c1fp) -> c1 |
--- |
17022 |
// fold (fp_to_sint c1fp) -> c1 |
--- |
| 17023 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
17023 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
| 17024 |
return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0); |
0 |
17024 |
return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0); |
0 |
| 17025 |
|
--- |
17025 |
|
--- |
| 17026 |
return FoldIntToFPToInt(N, DAG); |
0 |
17026 |
return FoldIntToFPToInt(N, DAG); |
0 |
| 17027 |
} |
--- |
17027 |
} |
--- |
| 17028 |
|
--- |
17028 |
|
--- |
| 17029 |
SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { |
0 |
17029 |
SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { |
0 |
| 17030 |
SDValue N0 = N->getOperand(0); |
0 |
17030 |
SDValue N0 = N->getOperand(0); |
0 |
| 17031 |
EVT VT = N->getValueType(0); |
0 |
17031 |
EVT VT = N->getValueType(0); |
0 |
| 17032 |
|
--- |
17032 |
|
--- |
| 17033 |
// fold (fp_to_uint undef) -> undef |
--- |
17033 |
// fold (fp_to_uint undef) -> undef |
--- |
| 17034 |
if (N0.isUndef()) |
0 |
17034 |
if (N0.isUndef()) |
0 |
| 17035 |
return DAG.getUNDEF(VT); |
0 |
17035 |
return DAG.getUNDEF(VT); |
0 |
| 17036 |
|
--- |
17036 |
|
--- |
| 17037 |
// fold (fp_to_uint c1fp) -> c1 |
--- |
17037 |
// fold (fp_to_uint c1fp) -> c1 |
--- |
| 17038 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
17038 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
| 17039 |
return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0); |
0 |
17039 |
return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0); |
0 |
| 17040 |
|
--- |
17040 |
|
--- |
| 17041 |
return FoldIntToFPToInt(N, DAG); |
0 |
17041 |
return FoldIntToFPToInt(N, DAG); |
0 |
| 17042 |
} |
--- |
17042 |
} |
--- |
| 17043 |
|
--- |
17043 |
|
--- |
| 17044 |
SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { |
0 |
17044 |
SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { |
0 |
| 17045 |
SDValue N0 = N->getOperand(0); |
0 |
17045 |
SDValue N0 = N->getOperand(0); |
0 |
| 17046 |
SDValue N1 = N->getOperand(1); |
0 |
17046 |
SDValue N1 = N->getOperand(1); |
0 |
| 17047 |
EVT VT = N->getValueType(0); |
0 |
17047 |
EVT VT = N->getValueType(0); |
0 |
| 17048 |
|
--- |
17048 |
|
--- |
| 17049 |
// fold (fp_round c1fp) -> c1fp |
--- |
17049 |
// fold (fp_round c1fp) -> c1fp |
--- |
| 17050 |
if (SDValue C = |
0 |
17050 |
if (SDValue C = |
0 |
| 17051 |
DAG.FoldConstantArithmetic(ISD::FP_ROUND, SDLoc(N), VT, {N0, N1})) |
0 |
17051 |
DAG.FoldConstantArithmetic(ISD::FP_ROUND, SDLoc(N), VT, {N0, N1})) |
0 |
| 17052 |
return C; |
0 |
17052 |
return C; |
0 |
| 17053 |
|
--- |
17053 |
|
--- |
| 17054 |
// fold (fp_round (fp_extend x)) -> x |
--- |
17054 |
// fold (fp_round (fp_extend x)) -> x |
--- |
| 17055 |
if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) |
0 |
17055 |
if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) |
0 |
| 17056 |
return N0.getOperand(0); |
0 |
17056 |
return N0.getOperand(0); |
0 |
| 17057 |
|
--- |
17057 |
|
--- |
| 17058 |
// fold (fp_round (fp_round x)) -> (fp_round x) |
--- |
17058 |
// fold (fp_round (fp_round x)) -> (fp_round x) |
--- |
| 17059 |
if (N0.getOpcode() == ISD::FP_ROUND) { |
0 |
17059 |
if (N0.getOpcode() == ISD::FP_ROUND) { |
0 |
| 17060 |
const bool NIsTrunc = N->getConstantOperandVal(1) == 1; |
0 |
17060 |
const bool NIsTrunc = N->getConstantOperandVal(1) == 1; |
0 |
| 17061 |
const bool N0IsTrunc = N0.getConstantOperandVal(1) == 1; |
0 |
17061 |
const bool N0IsTrunc = N0.getConstantOperandVal(1) == 1; |
0 |
| 17062 |
|
--- |
17062 |
|
--- |
| 17063 |
// Avoid folding legal fp_rounds into non-legal ones. |
--- |
17063 |
// Avoid folding legal fp_rounds into non-legal ones. |
--- |
| 17064 |
if (!hasOperation(ISD::FP_ROUND, VT)) |
0 |
17064 |
if (!hasOperation(ISD::FP_ROUND, VT)) |
0 |
| 17065 |
return SDValue(); |
0 |
17065 |
return SDValue(); |
0 |
| 17066 |
|
--- |
17066 |
|
--- |
| 17067 |
// Skip this folding if it results in an fp_round from f80 to f16. |
--- |
17067 |
// Skip this folding if it results in an fp_round from f80 to f16. |
--- |
| 17068 |
// |
--- |
17068 |
// |
--- |
| 17069 |
// f80 to f16 always generates an expensive (and as yet, unimplemented) |
--- |
17069 |
// f80 to f16 always generates an expensive (and as yet, unimplemented) |
--- |
| 17070 |
// libcall to __truncxfhf2 instead of selecting native f16 conversion |
--- |
17070 |
// libcall to __truncxfhf2 instead of selecting native f16 conversion |
--- |
| 17071 |
// instructions from f32 or f64. Moreover, the first (value-preserving) |
--- |
17071 |
// instructions from f32 or f64. Moreover, the first (value-preserving) |
--- |
| 17072 |
// fp_round from f80 to either f32 or f64 may become a NOP in platforms like |
--- |
17072 |
// fp_round from f80 to either f32 or f64 may become a NOP in platforms like |
--- |
| 17073 |
// x86. |
--- |
17073 |
// x86. |
--- |
| 17074 |
if (N0.getOperand(0).getValueType() == MVT::f80 && VT == MVT::f16) |
0 |
17074 |
if (N0.getOperand(0).getValueType() == MVT::f80 && VT == MVT::f16) |
0 |
| 17075 |
return SDValue(); |
0 |
17075 |
return SDValue(); |
0 |
| 17076 |
|
--- |
17076 |
|
--- |
| 17077 |
// If the first fp_round isn't a value preserving truncation, it might |
--- |
17077 |
// If the first fp_round isn't a value preserving truncation, it might |
--- |
| 17078 |
// introduce a tie in the second fp_round, that wouldn't occur in the |
--- |
17078 |
// introduce a tie in the second fp_round, that wouldn't occur in the |
--- |
| 17079 |
// single-step fp_round we want to fold to. |
--- |
17079 |
// single-step fp_round we want to fold to. |
--- |
| 17080 |
// In other words, double rounding isn't the same as rounding. |
--- |
17080 |
// In other words, double rounding isn't the same as rounding. |
--- |
| 17081 |
// Also, this is a value preserving truncation iff both fp_round's are. |
--- |
17081 |
// Also, this is a value preserving truncation iff both fp_round's are. |
--- |
| 17082 |
if (DAG.getTarget().Options.UnsafeFPMath || N0IsTrunc) { |
0 |
17082 |
if (DAG.getTarget().Options.UnsafeFPMath || N0IsTrunc) { |
0 |
| 17083 |
SDLoc DL(N); |
0 |
17083 |
SDLoc DL(N); |
0 |
| 17084 |
return DAG.getNode( |
0 |
17084 |
return DAG.getNode( |
0 |
| 17085 |
ISD::FP_ROUND, DL, VT, N0.getOperand(0), |
0 |
17085 |
ISD::FP_ROUND, DL, VT, N0.getOperand(0), |
0 |
| 17086 |
DAG.getIntPtrConstant(NIsTrunc && N0IsTrunc, DL, /*isTarget=*/true)); |
0 |
17086 |
DAG.getIntPtrConstant(NIsTrunc && N0IsTrunc, DL, /*isTarget=*/true)); |
0 |
| 17087 |
} |
0 |
17087 |
} |
0 |
| 17088 |
} |
--- |
17088 |
} |
--- |
| 17089 |
|
--- |
17089 |
|
--- |
| 17090 |
// fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) |
--- |
17090 |
// fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) |
--- |
| 17091 |
// Note: From a legality perspective, this is a two step transform. First, |
--- |
17091 |
// Note: From a legality perspective, this is a two step transform. First, |
--- |
| 17092 |
// we duplicate the fp_round to the arguments of the copysign, then we |
--- |
17092 |
// we duplicate the fp_round to the arguments of the copysign, then we |
--- |
| 17093 |
// eliminate the fp_round on Y. The second step requires an additional |
--- |
17093 |
// eliminate the fp_round on Y. The second step requires an additional |
--- |
| 17094 |
// predicate to match the implementation above. |
--- |
17094 |
// predicate to match the implementation above. |
--- |
| 17095 |
if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() && |
0 |
17095 |
if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() && |
0 |
| 17096 |
CanCombineFCOPYSIGN_EXTEND_ROUND(VT, |
0 |
17096 |
CanCombineFCOPYSIGN_EXTEND_ROUND(VT, |
0 |
| 17097 |
N0.getValueType())) { |
--- |
17097 |
N0.getValueType())) { |
--- |
| 17098 |
SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT, |
0 |
17098 |
SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT, |
0 |
| 17099 |
N0.getOperand(0), N1); |
0 |
17099 |
N0.getOperand(0), N1); |
0 |
| 17100 |
AddToWorklist(Tmp.getNode()); |
0 |
17100 |
AddToWorklist(Tmp.getNode()); |
0 |
| 17101 |
return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, |
0 |
17101 |
return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, |
0 |
| 17102 |
Tmp, N0.getOperand(1)); |
0 |
17102 |
Tmp, N0.getOperand(1)); |
0 |
| 17103 |
} |
--- |
17103 |
} |
--- |
| 17104 |
|
--- |
17104 |
|
--- |
| 17105 |
if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N)) |
0 |
17105 |
if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N)) |
0 |
| 17106 |
return NewVSel; |
0 |
17106 |
return NewVSel; |
0 |
| 17107 |
|
--- |
17107 |
|
--- |
| 17108 |
return SDValue(); |
0 |
17108 |
return SDValue(); |
0 |
| 17109 |
} |
--- |
17109 |
} |
--- |
| 17110 |
|
--- |
17110 |
|
--- |
| 17111 |
SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { |
0 |
17111 |
SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { |
0 |
| 17112 |
SDValue N0 = N->getOperand(0); |
0 |
17112 |
SDValue N0 = N->getOperand(0); |
0 |
| 17113 |
EVT VT = N->getValueType(0); |
0 |
17113 |
EVT VT = N->getValueType(0); |
0 |
| 17114 |
|
--- |
17114 |
|
--- |
| 17115 |
if (VT.isVector()) |
0 |
17115 |
if (VT.isVector()) |
0 |
| 17116 |
if (SDValue FoldedVOp = SimplifyVCastOp(N, SDLoc(N))) |
0 |
17116 |
if (SDValue FoldedVOp = SimplifyVCastOp(N, SDLoc(N))) |
0 |
| 17117 |
return FoldedVOp; |
0 |
17117 |
return FoldedVOp; |
0 |
| 17118 |
|
--- |
17118 |
|
--- |
| 17119 |
// If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. |
--- |
17119 |
// If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. |
--- |
| 17120 |
if (N->hasOneUse() && |
0 |
17120 |
if (N->hasOneUse() && |
0 |
| 17121 |
N->use_begin()->getOpcode() == ISD::FP_ROUND) |
0 |
17121 |
N->use_begin()->getOpcode() == ISD::FP_ROUND) |
0 |
| 17122 |
return SDValue(); |
0 |
17122 |
return SDValue(); |
0 |
| 17123 |
|
--- |
17123 |
|
--- |
| 17124 |
// fold (fp_extend c1fp) -> c1fp |
--- |
17124 |
// fold (fp_extend c1fp) -> c1fp |
--- |
| 17125 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
17125 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
| 17126 |
return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0); |
0 |
17126 |
return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0); |
0 |
| 17127 |
|
--- |
17127 |
|
--- |
| 17128 |
// fold (fp_extend (fp16_to_fp op)) -> (fp16_to_fp op) |
--- |
17128 |
// fold (fp_extend (fp16_to_fp op)) -> (fp16_to_fp op) |
--- |
| 17129 |
if (N0.getOpcode() == ISD::FP16_TO_FP && |
0 |
17129 |
if (N0.getOpcode() == ISD::FP16_TO_FP && |
0 |
| 17130 |
TLI.getOperationAction(ISD::FP16_TO_FP, VT) == TargetLowering::Legal) |
0 |
17130 |
TLI.getOperationAction(ISD::FP16_TO_FP, VT) == TargetLowering::Legal) |
0 |
| 17131 |
return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), VT, N0.getOperand(0)); |
0 |
17131 |
return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), VT, N0.getOperand(0)); |
0 |
| 17132 |
|
--- |
17132 |
|
--- |
| 17133 |
// Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the |
--- |
17133 |
// Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the |
--- |
| 17134 |
// value of X. |
--- |
17134 |
// value of X. |
--- |
| 17135 |
if (N0.getOpcode() == ISD::FP_ROUND |
0 |
17135 |
if (N0.getOpcode() == ISD::FP_ROUND |
0 |
| 17136 |
&& N0.getConstantOperandVal(1) == 1) { |
0 |
17136 |
&& N0.getConstantOperandVal(1) == 1) { |
0 |
| 17137 |
SDValue In = N0.getOperand(0); |
0 |
17137 |
SDValue In = N0.getOperand(0); |
0 |
| 17138 |
if (In.getValueType() == VT) return In; |
0 |
17138 |
if (In.getValueType() == VT) return In; |
0 |
| 17139 |
if (VT.bitsLT(In.getValueType())) |
0 |
17139 |
if (VT.bitsLT(In.getValueType())) |
0 |
| 17140 |
return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, |
0 |
17140 |
return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, |
0 |
| 17141 |
In, N0.getOperand(1)); |
0 |
17141 |
In, N0.getOperand(1)); |
0 |
| 17142 |
return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In); |
0 |
17142 |
return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In); |
0 |
| 17143 |
} |
--- |
17143 |
} |
--- |
| 17144 |
|
--- |
17144 |
|
--- |
| 17145 |
// fold (fpext (load x)) -> (fpext (fptrunc (extload x))) |
--- |
17145 |
// fold (fpext (load x)) -> (fpext (fptrunc (extload x))) |
--- |
| 17146 |
if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && |
0 |
17146 |
if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && |
0 |
| 17147 |
TLI.isLoadExtLegalOrCustom(ISD::EXTLOAD, VT, N0.getValueType())) { |
0 |
17147 |
TLI.isLoadExtLegalOrCustom(ISD::EXTLOAD, VT, N0.getValueType())) { |
0 |
| 17148 |
LoadSDNode *LN0 = cast(N0); |
0 |
17148 |
LoadSDNode *LN0 = cast(N0); |
0 |
| 17149 |
SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, |
0 |
17149 |
SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, |
0 |
| 17150 |
LN0->getChain(), |
0 |
17150 |
LN0->getChain(), |
0 |
| 17151 |
LN0->getBasePtr(), N0.getValueType(), |
0 |
17151 |
LN0->getBasePtr(), N0.getValueType(), |
0 |
| 17152 |
LN0->getMemOperand()); |
--- |
17152 |
LN0->getMemOperand()); |
--- |
| 17153 |
CombineTo(N, ExtLoad); |
0 |
17153 |
CombineTo(N, ExtLoad); |
0 |
| 17154 |
CombineTo( |
0 |
17154 |
CombineTo( |
0 |
| 17155 |
N0.getNode(), |
--- |
17155 |
N0.getNode(), |
--- |
| 17156 |
DAG.getNode(ISD::FP_ROUND, SDLoc(N0), N0.getValueType(), ExtLoad, |
0 |
17156 |
DAG.getNode(ISD::FP_ROUND, SDLoc(N0), N0.getValueType(), ExtLoad, |
0 |
| 17157 |
DAG.getIntPtrConstant(1, SDLoc(N0), /*isTarget=*/true)), |
0 |
17157 |
DAG.getIntPtrConstant(1, SDLoc(N0), /*isTarget=*/true)), |
0 |
| 17158 |
ExtLoad.getValue(1)); |
--- |
17158 |
ExtLoad.getValue(1)); |
--- |
| 17159 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
17159 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 17160 |
} |
--- |
17160 |
} |
--- |
| 17161 |
|
--- |
17161 |
|
--- |
| 17162 |
if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N)) |
0 |
17162 |
if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N)) |
0 |
| 17163 |
return NewVSel; |
0 |
17163 |
return NewVSel; |
0 |
| 17164 |
|
--- |
17164 |
|
--- |
| 17165 |
return SDValue(); |
0 |
17165 |
return SDValue(); |
0 |
| 17166 |
} |
--- |
17166 |
} |
--- |
| 17167 |
|
--- |
17167 |
|
--- |
| 17168 |
SDValue DAGCombiner::visitFCEIL(SDNode *N) { |
0 |
17168 |
SDValue DAGCombiner::visitFCEIL(SDNode *N) { |
0 |
| 17169 |
SDValue N0 = N->getOperand(0); |
0 |
17169 |
SDValue N0 = N->getOperand(0); |
0 |
| 17170 |
EVT VT = N->getValueType(0); |
0 |
17170 |
EVT VT = N->getValueType(0); |
0 |
| 17171 |
|
--- |
17171 |
|
--- |
| 17172 |
// fold (fceil c1) -> fceil(c1) |
--- |
17172 |
// fold (fceil c1) -> fceil(c1) |
--- |
| 17173 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
17173 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
| 17174 |
return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0); |
0 |
17174 |
return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0); |
0 |
| 17175 |
|
--- |
17175 |
|
--- |
| 17176 |
return SDValue(); |
0 |
17176 |
return SDValue(); |
0 |
| 17177 |
} |
--- |
17177 |
} |
--- |
| 17178 |
|
--- |
17178 |
|
--- |
| 17179 |
SDValue DAGCombiner::visitFTRUNC(SDNode *N) { |
0 |
17179 |
SDValue DAGCombiner::visitFTRUNC(SDNode *N) { |
0 |
| 17180 |
SDValue N0 = N->getOperand(0); |
0 |
17180 |
SDValue N0 = N->getOperand(0); |
0 |
| 17181 |
EVT VT = N->getValueType(0); |
0 |
17181 |
EVT VT = N->getValueType(0); |
0 |
| 17182 |
|
--- |
17182 |
|
--- |
| 17183 |
// fold (ftrunc c1) -> ftrunc(c1) |
--- |
17183 |
// fold (ftrunc c1) -> ftrunc(c1) |
--- |
| 17184 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
17184 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
| 17185 |
return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0); |
0 |
17185 |
return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0); |
0 |
| 17186 |
|
--- |
17186 |
|
--- |
| 17187 |
// fold ftrunc (known rounded int x) -> x |
--- |
17187 |
// fold ftrunc (known rounded int x) -> x |
--- |
| 17188 |
// ftrunc is a part of fptosi/fptoui expansion on some targets, so this is |
--- |
17188 |
// ftrunc is a part of fptosi/fptoui expansion on some targets, so this is |
--- |
| 17189 |
// likely to be generated to extract integer from a rounded floating value. |
--- |
17189 |
// likely to be generated to extract integer from a rounded floating value. |
--- |
| 17190 |
switch (N0.getOpcode()) { |
0 |
17190 |
switch (N0.getOpcode()) { |
0 |
| 17191 |
default: break; |
0 |
17191 |
default: break; |
0 |
| 17192 |
case ISD::FRINT: |
0 |
17192 |
case ISD::FRINT: |
0 |
| 17193 |
case ISD::FTRUNC: |
--- |
17193 |
case ISD::FTRUNC: |
--- |
| 17194 |
case ISD::FNEARBYINT: |
--- |
17194 |
case ISD::FNEARBYINT: |
--- |
| 17195 |
case ISD::FFLOOR: |
--- |
17195 |
case ISD::FFLOOR: |
--- |
| 17196 |
case ISD::FCEIL: |
--- |
17196 |
case ISD::FCEIL: |
--- |
| 17197 |
return N0; |
0 |
17197 |
return N0; |
0 |
| 17198 |
} |
--- |
17198 |
} |
--- |
| 17199 |
|
--- |
17199 |
|
--- |
| 17200 |
return SDValue(); |
0 |
17200 |
return SDValue(); |
0 |
| 17201 |
} |
--- |
17201 |
} |
--- |
| 17202 |
|
--- |
17202 |
|
--- |
| 17203 |
SDValue DAGCombiner::visitFFREXP(SDNode *N) { |
0 |
17203 |
SDValue DAGCombiner::visitFFREXP(SDNode *N) { |
0 |
| 17204 |
SDValue N0 = N->getOperand(0); |
0 |
17204 |
SDValue N0 = N->getOperand(0); |
0 |
| 17205 |
|
--- |
17205 |
|
--- |
| 17206 |
// fold (ffrexp c1) -> ffrexp(c1) |
--- |
17206 |
// fold (ffrexp c1) -> ffrexp(c1) |
--- |
| 17207 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
17207 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
| 17208 |
return DAG.getNode(ISD::FFREXP, SDLoc(N), N->getVTList(), N0); |
0 |
17208 |
return DAG.getNode(ISD::FFREXP, SDLoc(N), N->getVTList(), N0); |
0 |
| 17209 |
return SDValue(); |
0 |
17209 |
return SDValue(); |
0 |
| 17210 |
} |
--- |
17210 |
} |
--- |
| 17211 |
|
--- |
17211 |
|
--- |
| 17212 |
SDValue DAGCombiner::visitFFLOOR(SDNode *N) { |
0 |
17212 |
SDValue DAGCombiner::visitFFLOOR(SDNode *N) { |
0 |
| 17213 |
SDValue N0 = N->getOperand(0); |
0 |
17213 |
SDValue N0 = N->getOperand(0); |
0 |
| 17214 |
EVT VT = N->getValueType(0); |
0 |
17214 |
EVT VT = N->getValueType(0); |
0 |
| 17215 |
|
--- |
17215 |
|
--- |
| 17216 |
// fold (ffloor c1) -> ffloor(c1) |
--- |
17216 |
// fold (ffloor c1) -> ffloor(c1) |
--- |
| 17217 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
17217 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
| 17218 |
return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0); |
0 |
17218 |
return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0); |
0 |
| 17219 |
|
--- |
17219 |
|
--- |
| 17220 |
return SDValue(); |
0 |
17220 |
return SDValue(); |
0 |
| 17221 |
} |
--- |
17221 |
} |
--- |
| 17222 |
|
--- |
17222 |
|
--- |
| 17223 |
SDValue DAGCombiner::visitFNEG(SDNode *N) { |
0 |
17223 |
SDValue DAGCombiner::visitFNEG(SDNode *N) { |
0 |
| 17224 |
SDValue N0 = N->getOperand(0); |
0 |
17224 |
SDValue N0 = N->getOperand(0); |
0 |
| 17225 |
EVT VT = N->getValueType(0); |
0 |
17225 |
EVT VT = N->getValueType(0); |
0 |
| 17226 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
17226 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
| 17227 |
|
--- |
17227 |
|
--- |
| 17228 |
// Constant fold FNEG. |
--- |
17228 |
// Constant fold FNEG. |
--- |
| 17229 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
17229 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
| 17230 |
return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0); |
0 |
17230 |
return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0); |
0 |
| 17231 |
|
--- |
17231 |
|
--- |
| 17232 |
if (SDValue NegN0 = |
0 |
17232 |
if (SDValue NegN0 = |
0 |
| 17233 |
TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize)) |
0 |
17233 |
TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize)) |
0 |
| 17234 |
return NegN0; |
0 |
17234 |
return NegN0; |
0 |
| 17235 |
|
--- |
17235 |
|
--- |
| 17236 |
// -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 |
--- |
17236 |
// -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 |
--- |
| 17237 |
// FIXME: This is duplicated in getNegatibleCost, but getNegatibleCost doesn't |
--- |
17237 |
// FIXME: This is duplicated in getNegatibleCost, but getNegatibleCost doesn't |
--- |
| 17238 |
// know it was called from a context with a nsz flag if the input fsub does |
--- |
17238 |
// know it was called from a context with a nsz flag if the input fsub does |
--- |
| 17239 |
// not. |
--- |
17239 |
// not. |
--- |
| 17240 |
if (N0.getOpcode() == ISD::FSUB && |
0 |
17240 |
if (N0.getOpcode() == ISD::FSUB && |
0 |
| 17241 |
(DAG.getTarget().Options.NoSignedZerosFPMath || |
0 |
17241 |
(DAG.getTarget().Options.NoSignedZerosFPMath || |
0 |
| 17242 |
N->getFlags().hasNoSignedZeros()) && N0.hasOneUse()) { |
0 |
17242 |
N->getFlags().hasNoSignedZeros()) && N0.hasOneUse()) { |
0 |
| 17243 |
return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0.getOperand(1), |
0 |
17243 |
return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0.getOperand(1), |
0 |
| 17244 |
N0.getOperand(0)); |
0 |
17244 |
N0.getOperand(0)); |
0 |
| 17245 |
} |
--- |
17245 |
} |
--- |
| 17246 |
|
--- |
17246 |
|
--- |
| 17247 |
if (SDValue Cast = foldSignChangeInBitcast(N)) |
0 |
17247 |
if (SDValue Cast = foldSignChangeInBitcast(N)) |
0 |
| 17248 |
return Cast; |
0 |
17248 |
return Cast; |
0 |
| 17249 |
|
--- |
17249 |
|
--- |
| 17250 |
return SDValue(); |
0 |
17250 |
return SDValue(); |
0 |
| 17251 |
} |
0 |
17251 |
} |
0 |
| 17252 |
|
--- |
17252 |
|
--- |
| 17253 |
SDValue DAGCombiner::visitFMinMax(SDNode *N) { |
0 |
17253 |
SDValue DAGCombiner::visitFMinMax(SDNode *N) { |
0 |
| 17254 |
SDValue N0 = N->getOperand(0); |
0 |
17254 |
SDValue N0 = N->getOperand(0); |
0 |
| 17255 |
SDValue N1 = N->getOperand(1); |
0 |
17255 |
SDValue N1 = N->getOperand(1); |
0 |
| 17256 |
EVT VT = N->getValueType(0); |
0 |
17256 |
EVT VT = N->getValueType(0); |
0 |
| 17257 |
const SDNodeFlags Flags = N->getFlags(); |
0 |
17257 |
const SDNodeFlags Flags = N->getFlags(); |
0 |
| 17258 |
unsigned Opc = N->getOpcode(); |
0 |
17258 |
unsigned Opc = N->getOpcode(); |
0 |
| 17259 |
bool PropagatesNaN = Opc == ISD::FMINIMUM || Opc == ISD::FMAXIMUM; |
0 |
17259 |
bool PropagatesNaN = Opc == ISD::FMINIMUM || Opc == ISD::FMAXIMUM; |
0 |
| 17260 |
bool IsMin = Opc == ISD::FMINNUM || Opc == ISD::FMINIMUM; |
0 |
17260 |
bool IsMin = Opc == ISD::FMINNUM || Opc == ISD::FMINIMUM; |
0 |
| 17261 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
17261 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
| 17262 |
|
--- |
17262 |
|
--- |
| 17263 |
// Constant fold. |
--- |
17263 |
// Constant fold. |
--- |
| 17264 |
if (SDValue C = DAG.FoldConstantArithmetic(Opc, SDLoc(N), VT, {N0, N1})) |
0 |
17264 |
if (SDValue C = DAG.FoldConstantArithmetic(Opc, SDLoc(N), VT, {N0, N1})) |
0 |
| 17265 |
return C; |
0 |
17265 |
return C; |
0 |
| 17266 |
|
--- |
17266 |
|
--- |
| 17267 |
// Canonicalize to constant on RHS. |
--- |
17267 |
// Canonicalize to constant on RHS. |
--- |
| 17268 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0) && |
0 |
17268 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0) && |
0 |
| 17269 |
!DAG.isConstantFPBuildVectorOrConstantFP(N1)) |
0 |
17269 |
!DAG.isConstantFPBuildVectorOrConstantFP(N1)) |
0 |
| 17270 |
return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0); |
0 |
17270 |
return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0); |
0 |
| 17271 |
|
--- |
17271 |
|
--- |
| 17272 |
if (const ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1)) { |
0 |
17272 |
if (const ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1)) { |
0 |
| 17273 |
const APFloat &AF = N1CFP->getValueAPF(); |
0 |
17273 |
const APFloat &AF = N1CFP->getValueAPF(); |
0 |
| 17274 |
|
--- |
17274 |
|
--- |
| 17275 |
// minnum(X, nan) -> X |
--- |
17275 |
// minnum(X, nan) -> X |
--- |
| 17276 |
// maxnum(X, nan) -> X |
--- |
17276 |
// maxnum(X, nan) -> X |
--- |
| 17277 |
// minimum(X, nan) -> nan |
--- |
17277 |
// minimum(X, nan) -> nan |
--- |
| 17278 |
// maximum(X, nan) -> nan |
--- |
17278 |
// maximum(X, nan) -> nan |
--- |
| 17279 |
if (AF.isNaN()) |
0 |
17279 |
if (AF.isNaN()) |
0 |
| 17280 |
return PropagatesNaN ? N->getOperand(1) : N->getOperand(0); |
0 |
17280 |
return PropagatesNaN ? N->getOperand(1) : N->getOperand(0); |
0 |
| 17281 |
|
--- |
17281 |
|
--- |
| 17282 |
// In the following folds, inf can be replaced with the largest finite |
--- |
17282 |
// In the following folds, inf can be replaced with the largest finite |
--- |
| 17283 |
// float, if the ninf flag is set. |
--- |
17283 |
// float, if the ninf flag is set. |
--- |
| 17284 |
if (AF.isInfinity() || (Flags.hasNoInfs() && AF.isLargest())) { |
0 |
17284 |
if (AF.isInfinity() || (Flags.hasNoInfs() && AF.isLargest())) { |
0 |
| 17285 |
// minnum(X, -inf) -> -inf |
--- |
17285 |
// minnum(X, -inf) -> -inf |
--- |
| 17286 |
// maxnum(X, +inf) -> +inf |
--- |
17286 |
// maxnum(X, +inf) -> +inf |
--- |
| 17287 |
// minimum(X, -inf) -> -inf if nnan |
--- |
17287 |
// minimum(X, -inf) -> -inf if nnan |
--- |
| 17288 |
// maximum(X, +inf) -> +inf if nnan |
--- |
17288 |
// maximum(X, +inf) -> +inf if nnan |
--- |
| 17289 |
if (IsMin == AF.isNegative() && (!PropagatesNaN || Flags.hasNoNaNs())) |
0 |
17289 |
if (IsMin == AF.isNegative() && (!PropagatesNaN || Flags.hasNoNaNs())) |
0 |
| 17290 |
return N->getOperand(1); |
0 |
17290 |
return N->getOperand(1); |
0 |
| 17291 |
|
--- |
17291 |
|
--- |
| 17292 |
// minnum(X, +inf) -> X if nnan |
--- |
17292 |
// minnum(X, +inf) -> X if nnan |
--- |
| 17293 |
// maxnum(X, -inf) -> X if nnan |
--- |
17293 |
// maxnum(X, -inf) -> X if nnan |
--- |
| 17294 |
// minimum(X, +inf) -> X |
--- |
17294 |
// minimum(X, +inf) -> X |
--- |
| 17295 |
// maximum(X, -inf) -> X |
--- |
17295 |
// maximum(X, -inf) -> X |
--- |
| 17296 |
if (IsMin != AF.isNegative() && (PropagatesNaN || Flags.hasNoNaNs())) |
0 |
17296 |
if (IsMin != AF.isNegative() && (PropagatesNaN || Flags.hasNoNaNs())) |
0 |
| 17297 |
return N->getOperand(0); |
0 |
17297 |
return N->getOperand(0); |
0 |
| 17298 |
} |
--- |
17298 |
} |
--- |
| 17299 |
} |
--- |
17299 |
} |
--- |
| 17300 |
|
--- |
17300 |
|
--- |
| 17301 |
if (SDValue SD = reassociateReduction( |
0 |
17301 |
if (SDValue SD = reassociateReduction( |
0 |
| 17302 |
PropagatesNaN |
--- |
17302 |
PropagatesNaN |
--- |
| 17303 |
? (IsMin ? ISD::VECREDUCE_FMINIMUM : ISD::VECREDUCE_FMAXIMUM) |
0 |
17303 |
? (IsMin ? ISD::VECREDUCE_FMINIMUM : ISD::VECREDUCE_FMAXIMUM) |
0 |
| 17304 |
: (IsMin ? ISD::VECREDUCE_FMIN : ISD::VECREDUCE_FMAX), |
--- |
17304 |
: (IsMin ? ISD::VECREDUCE_FMIN : ISD::VECREDUCE_FMAX), |
--- |
| 17305 |
Opc, SDLoc(N), VT, N0, N1, Flags)) |
0 |
17305 |
Opc, SDLoc(N), VT, N0, N1, Flags)) |
0 |
| 17306 |
return SD; |
0 |
17306 |
return SD; |
0 |
| 17307 |
|
--- |
17307 |
|
--- |
| 17308 |
return SDValue(); |
0 |
17308 |
return SDValue(); |
0 |
| 17309 |
} |
0 |
17309 |
} |
0 |
| 17310 |
|
--- |
17310 |
|
--- |
| 17311 |
SDValue DAGCombiner::visitFABS(SDNode *N) { |
0 |
17311 |
SDValue DAGCombiner::visitFABS(SDNode *N) { |
0 |
| 17312 |
SDValue N0 = N->getOperand(0); |
0 |
17312 |
SDValue N0 = N->getOperand(0); |
0 |
| 17313 |
EVT VT = N->getValueType(0); |
0 |
17313 |
EVT VT = N->getValueType(0); |
0 |
| 17314 |
|
--- |
17314 |
|
--- |
| 17315 |
// fold (fabs c1) -> fabs(c1) |
--- |
17315 |
// fold (fabs c1) -> fabs(c1) |
--- |
| 17316 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
17316 |
if (DAG.isConstantFPBuildVectorOrConstantFP(N0)) |
0 |
| 17317 |
return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); |
0 |
17317 |
return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); |
0 |
| 17318 |
|
--- |
17318 |
|
--- |
| 17319 |
// fold (fabs (fabs x)) -> (fabs x) |
--- |
17319 |
// fold (fabs (fabs x)) -> (fabs x) |
--- |
| 17320 |
if (N0.getOpcode() == ISD::FABS) |
0 |
17320 |
if (N0.getOpcode() == ISD::FABS) |
0 |
| 17321 |
return N->getOperand(0); |
0 |
17321 |
return N->getOperand(0); |
0 |
| 17322 |
|
--- |
17322 |
|
--- |
| 17323 |
// fold (fabs (fneg x)) -> (fabs x) |
--- |
17323 |
// fold (fabs (fneg x)) -> (fabs x) |
--- |
| 17324 |
// fold (fabs (fcopysign x, y)) -> (fabs x) |
--- |
17324 |
// fold (fabs (fcopysign x, y)) -> (fabs x) |
--- |
| 17325 |
if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) |
0 |
17325 |
if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) |
0 |
| 17326 |
return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0)); |
0 |
17326 |
return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0)); |
0 |
| 17327 |
|
--- |
17327 |
|
--- |
| 17328 |
if (SDValue Cast = foldSignChangeInBitcast(N)) |
0 |
17328 |
if (SDValue Cast = foldSignChangeInBitcast(N)) |
0 |
| 17329 |
return Cast; |
0 |
17329 |
return Cast; |
0 |
| 17330 |
|
--- |
17330 |
|
--- |
| 17331 |
return SDValue(); |
0 |
17331 |
return SDValue(); |
0 |
| 17332 |
} |
--- |
17332 |
} |
--- |
| 17333 |
|
--- |
17333 |
|
--- |
| 17334 |
SDValue DAGCombiner::visitBRCOND(SDNode *N) { |
4 |
17334 |
SDValue DAGCombiner::visitBRCOND(SDNode *N) { |
4 |
| 17335 |
SDValue Chain = N->getOperand(0); |
4 |
17335 |
SDValue Chain = N->getOperand(0); |
4 |
| 17336 |
SDValue N1 = N->getOperand(1); |
4 |
17336 |
SDValue N1 = N->getOperand(1); |
4 |
| 17337 |
SDValue N2 = N->getOperand(2); |
4 |
17337 |
SDValue N2 = N->getOperand(2); |
4 |
| 17338 |
|
--- |
17338 |
|
--- |
| 17339 |
// BRCOND(FREEZE(cond)) is equivalent to BRCOND(cond) (both are |
--- |
17339 |
// BRCOND(FREEZE(cond)) is equivalent to BRCOND(cond) (both are |
--- |
| 17340 |
// nondeterministic jumps). |
--- |
17340 |
// nondeterministic jumps). |
--- |
| 17341 |
if (N1->getOpcode() == ISD::FREEZE && N1.hasOneUse()) { |
4 |
17341 |
if (N1->getOpcode() == ISD::FREEZE && N1.hasOneUse()) { |
4 |
| 17342 |
return DAG.getNode(ISD::BRCOND, SDLoc(N), MVT::Other, Chain, |
0 |
17342 |
return DAG.getNode(ISD::BRCOND, SDLoc(N), MVT::Other, Chain, |
0 |
| 17343 |
N1->getOperand(0), N2); |
0 |
17343 |
N1->getOperand(0), N2); |
0 |
| 17344 |
} |
--- |
17344 |
} |
--- |
| 17345 |
|
--- |
17345 |
|
--- |
| 17346 |
// Variant of the previous fold where there is a SETCC in between: |
--- |
17346 |
// Variant of the previous fold where there is a SETCC in between: |
--- |
| 17347 |
// BRCOND(SETCC(FREEZE(X), CONST, Cond)) |
--- |
17347 |
// BRCOND(SETCC(FREEZE(X), CONST, Cond)) |
--- |
| 17348 |
// => |
--- |
17348 |
// => |
--- |
| 17349 |
// BRCOND(FREEZE(SETCC(X, CONST, Cond))) |
--- |
17349 |
// BRCOND(FREEZE(SETCC(X, CONST, Cond))) |
--- |
| 17350 |
// => |
--- |
17350 |
// => |
--- |
| 17351 |
// BRCOND(SETCC(X, CONST, Cond)) |
--- |
17351 |
// BRCOND(SETCC(X, CONST, Cond)) |
--- |
| 17352 |
// This is correct if FREEZE(X) has one use and SETCC(FREEZE(X), CONST, Cond) |
--- |
17352 |
// This is correct if FREEZE(X) has one use and SETCC(FREEZE(X), CONST, Cond) |
--- |
| 17353 |
// isn't equivalent to true or false. |
--- |
17353 |
// isn't equivalent to true or false. |
--- |
| 17354 |
// For example, SETCC(FREEZE(X), -128, SETULT) cannot be folded to |
--- |
17354 |
// For example, SETCC(FREEZE(X), -128, SETULT) cannot be folded to |
--- |
| 17355 |
// FREEZE(SETCC(X, -128, SETULT)) because X can be poison. |
--- |
17355 |
// FREEZE(SETCC(X, -128, SETULT)) because X can be poison. |
--- |
| 17356 |
if (N1->getOpcode() == ISD::SETCC && N1.hasOneUse()) { |
4 |
17356 |
if (N1->getOpcode() == ISD::SETCC && N1.hasOneUse()) { |
4 |
| 17357 |
SDValue S0 = N1->getOperand(0), S1 = N1->getOperand(1); |
3 |
17357 |
SDValue S0 = N1->getOperand(0), S1 = N1->getOperand(1); |
3 |
| 17358 |
ISD::CondCode Cond = cast(N1->getOperand(2))->get(); |
3 |
17358 |
ISD::CondCode Cond = cast(N1->getOperand(2))->get(); |
3 |
| 17359 |
ConstantSDNode *S0C = dyn_cast(S0); |
3 |
17359 |
ConstantSDNode *S0C = dyn_cast(S0); |
3 |
| 17360 |
ConstantSDNode *S1C = dyn_cast(S1); |
3 |
17360 |
ConstantSDNode *S1C = dyn_cast(S1); |
3 |
| 17361 |
bool Updated = false; |
3 |
17361 |
bool Updated = false; |
3 |
| 17362 |
|
--- |
17362 |
|
--- |
| 17363 |
// Is 'X Cond C' always true or false? |
--- |
17363 |
// Is 'X Cond C' always true or false? |
--- |
| 17364 |
auto IsAlwaysTrueOrFalse = [](ISD::CondCode Cond, ConstantSDNode *C) { |
0 |
17364 |
auto IsAlwaysTrueOrFalse = [](ISD::CondCode Cond, ConstantSDNode *C) { |
0 |
| 17365 |
bool False = (Cond == ISD::SETULT && C->isZero()) || |
0 |
17365 |
bool False = (Cond == ISD::SETULT && C->isZero()) || |
0 |
| 17366 |
(Cond == ISD::SETLT && C->isMinSignedValue()) || |
0 |
17366 |
(Cond == ISD::SETLT && C->isMinSignedValue()) || |
0 |
| 17367 |
(Cond == ISD::SETUGT && C->isAllOnes()) || |
0 |
17367 |
(Cond == ISD::SETUGT && C->isAllOnes()) || |
0 |
| 17368 |
(Cond == ISD::SETGT && C->isMaxSignedValue()); |
0 |
17368 |
(Cond == ISD::SETGT && C->isMaxSignedValue()); |
0 |
| 17369 |
bool True = (Cond == ISD::SETULE && C->isAllOnes()) || |
0 |
17369 |
bool True = (Cond == ISD::SETULE && C->isAllOnes()) || |
0 |
| 17370 |
(Cond == ISD::SETLE && C->isMaxSignedValue()) || |
0 |
17370 |
(Cond == ISD::SETLE && C->isMaxSignedValue()) || |
0 |
| 17371 |
(Cond == ISD::SETUGE && C->isZero()) || |
0 |
17371 |
(Cond == ISD::SETUGE && C->isZero()) || |
0 |
| 17372 |
(Cond == ISD::SETGE && C->isMinSignedValue()); |
0 |
17372 |
(Cond == ISD::SETGE && C->isMinSignedValue()); |
0 |
| 17373 |
return True || False; |
0 |
17373 |
return True || False; |
0 |
| 17374 |
}; |
--- |
17374 |
}; |
--- |
| 17375 |
|
--- |
17375 |
|
--- |
| 17376 |
if (S0->getOpcode() == ISD::FREEZE && S0.hasOneUse() && S1C) { |
3 |
17376 |
if (S0->getOpcode() == ISD::FREEZE && S0.hasOneUse() && S1C) { |
3 |
| 17377 |
if (!IsAlwaysTrueOrFalse(Cond, S1C)) { |
0 |
17377 |
if (!IsAlwaysTrueOrFalse(Cond, S1C)) { |
0 |
| 17378 |
S0 = S0->getOperand(0); |
0 |
17378 |
S0 = S0->getOperand(0); |
0 |
| 17379 |
Updated = true; |
0 |
17379 |
Updated = true; |
0 |
| 17380 |
} |
--- |
17380 |
} |
--- |
| 17381 |
} |
--- |
17381 |
} |
--- |
| 17382 |
if (S1->getOpcode() == ISD::FREEZE && S1.hasOneUse() && S0C) { |
3 |
17382 |
if (S1->getOpcode() == ISD::FREEZE && S1.hasOneUse() && S0C) { |
3 |
| 17383 |
if (!IsAlwaysTrueOrFalse(ISD::getSetCCSwappedOperands(Cond), S0C)) { |
0 |
17383 |
if (!IsAlwaysTrueOrFalse(ISD::getSetCCSwappedOperands(Cond), S0C)) { |
0 |
| 17384 |
S1 = S1->getOperand(0); |
0 |
17384 |
S1 = S1->getOperand(0); |
0 |
| 17385 |
Updated = true; |
0 |
17385 |
Updated = true; |
0 |
| 17386 |
} |
--- |
17386 |
} |
--- |
| 17387 |
} |
--- |
17387 |
} |
--- |
| 17388 |
|
--- |
17388 |
|
--- |
| 17389 |
if (Updated) |
3 |
17389 |
if (Updated) |
3 |
| 17390 |
return DAG.getNode( |
0 |
17390 |
return DAG.getNode( |
0 |
| 17391 |
ISD::BRCOND, SDLoc(N), MVT::Other, Chain, |
0 |
17391 |
ISD::BRCOND, SDLoc(N), MVT::Other, Chain, |
0 |
| 17392 |
DAG.getSetCC(SDLoc(N1), N1->getValueType(0), S0, S1, Cond), N2); |
0 |
17392 |
DAG.getSetCC(SDLoc(N1), N1->getValueType(0), S0, S1, Cond), N2); |
0 |
| 17393 |
} |
--- |
17393 |
} |
--- |
| 17394 |
|
--- |
17394 |
|
--- |
| 17395 |
// If N is a constant we could fold this into a fallthrough or unconditional |
--- |
17395 |
// If N is a constant we could fold this into a fallthrough or unconditional |
--- |
| 17396 |
// branch. However that doesn't happen very often in normal code, because |
--- |
17396 |
// branch. However that doesn't happen very often in normal code, because |
--- |
| 17397 |
// Instcombine/SimplifyCFG should have handled the available opportunities. |
--- |
17397 |
// Instcombine/SimplifyCFG should have handled the available opportunities. |
--- |
| 17398 |
// If we did this folding here, it would be necessary to update the |
--- |
17398 |
// If we did this folding here, it would be necessary to update the |
--- |
| 17399 |
// MachineBasicBlock CFG, which is awkward. |
--- |
17399 |
// MachineBasicBlock CFG, which is awkward. |
--- |
| 17400 |
|
--- |
17400 |
|
--- |
| 17401 |
// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal |
--- |
17401 |
// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal |
--- |
| 17402 |
// on the target. |
--- |
17402 |
// on the target. |
--- |
| 17403 |
if (N1.getOpcode() == ISD::SETCC && |
7 |
17403 |
if (N1.getOpcode() == ISD::SETCC && |
7 |
| 17404 |
TLI.isOperationLegalOrCustom(ISD::BR_CC, |
3 |
17404 |
TLI.isOperationLegalOrCustom(ISD::BR_CC, |
3 |
| 17405 |
N1.getOperand(0).getValueType())) { |
3 |
17405 |
N1.getOperand(0).getValueType())) { |
3 |
| 17406 |
return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, |
0 |
17406 |
return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, |
0 |
| 17407 |
Chain, N1.getOperand(2), |
0 |
17407 |
Chain, N1.getOperand(2), |
0 |
| 17408 |
N1.getOperand(0), N1.getOperand(1), N2); |
0 |
17408 |
N1.getOperand(0), N1.getOperand(1), N2); |
0 |
| 17409 |
} |
--- |
17409 |
} |
--- |
| 17410 |
|
--- |
17410 |
|
--- |
| 17411 |
if (N1.hasOneUse()) { |
4 |
17411 |
if (N1.hasOneUse()) { |
4 |
| 17412 |
// rebuildSetCC calls visitXor which may change the Chain when there is a |
--- |
17412 |
// rebuildSetCC calls visitXor which may change the Chain when there is a |
--- |
| 17413 |
// STRICT_FSETCC/STRICT_FSETCCS involved. Use a handle to track changes. |
--- |
17413 |
// STRICT_FSETCC/STRICT_FSETCCS involved. Use a handle to track changes. |
--- |
| 17414 |
HandleSDNode ChainHandle(Chain); |
4 |
17414 |
HandleSDNode ChainHandle(Chain); |
4 |
| 17415 |
if (SDValue NewN1 = rebuildSetCC(N1)) |
4 |
17415 |
if (SDValue NewN1 = rebuildSetCC(N1)) |
4 |
| 17416 |
return DAG.getNode(ISD::BRCOND, SDLoc(N), MVT::Other, |
2 |
17416 |
return DAG.getNode(ISD::BRCOND, SDLoc(N), MVT::Other, |
2 |
| 17417 |
ChainHandle.getValue(), NewN1, N2); |
2 |
17417 |
ChainHandle.getValue(), NewN1, N2); |
2 |
| 17418 |
} |
4 |
17418 |
} |
4 |
| 17419 |
|
--- |
17419 |
|
--- |
| 17420 |
return SDValue(); |
3 |
17420 |
return SDValue(); |
3 |
| 17421 |
} |
--- |
17421 |
} |
--- |
| 17422 |
|
--- |
17422 |
|
--- |
| 17423 |
SDValue DAGCombiner::rebuildSetCC(SDValue N) { |
4 |
17423 |
SDValue DAGCombiner::rebuildSetCC(SDValue N) { |
4 |
| 17424 |
if (N.getOpcode() == ISD::SRL || |
8 |
17424 |
if (N.getOpcode() == ISD::SRL || |
8 |
| 17425 |
(N.getOpcode() == ISD::TRUNCATE && |
4 |
17425 |
(N.getOpcode() == ISD::TRUNCATE && |
4 |
| 17426 |
(N.getOperand(0).hasOneUse() && |
0 |
17426 |
(N.getOperand(0).hasOneUse() && |
0 |
| 17427 |
N.getOperand(0).getOpcode() == ISD::SRL))) { |
0 |
17427 |
N.getOperand(0).getOpcode() == ISD::SRL))) { |
0 |
| 17428 |
// Look pass the truncate. |
--- |
17428 |
// Look pass the truncate. |
--- |
| 17429 |
if (N.getOpcode() == ISD::TRUNCATE) |
0 |
17429 |
if (N.getOpcode() == ISD::TRUNCATE) |
0 |
| 17430 |
N = N.getOperand(0); |
0 |
17430 |
N = N.getOperand(0); |
0 |
| 17431 |
|
--- |
17431 |
|
--- |
| 17432 |
// Match this pattern so that we can generate simpler code: |
--- |
17432 |
// Match this pattern so that we can generate simpler code: |
--- |
| 17433 |
// |
--- |
17433 |
// |
--- |
| 17434 |
// %a = ... |
--- |
17434 |
// %a = ... |
--- |
| 17435 |
// %b = and i32 %a, 2 |
--- |
17435 |
// %b = and i32 %a, 2 |
--- |
| 17436 |
// %c = srl i32 %b, 1 |
--- |
17436 |
// %c = srl i32 %b, 1 |
--- |
| 17437 |
// brcond i32 %c ... |
--- |
17437 |
// brcond i32 %c ... |
--- |
| 17438 |
// |
--- |
17438 |
// |
--- |
| 17439 |
// into |
--- |
17439 |
// into |
--- |
| 17440 |
// |
--- |
17440 |
// |
--- |
| 17441 |
// %a = ... |
--- |
17441 |
// %a = ... |
--- |
| 17442 |
// %b = and i32 %a, 2 |
--- |
17442 |
// %b = and i32 %a, 2 |
--- |
| 17443 |
// %c = setcc eq %b, 0 |
--- |
17443 |
// %c = setcc eq %b, 0 |
--- |
| 17444 |
// brcond %c ... |
--- |
17444 |
// brcond %c ... |
--- |
| 17445 |
// |
--- |
17445 |
// |
--- |
| 17446 |
// This applies only when the AND constant value has one bit set and the |
--- |
17446 |
// This applies only when the AND constant value has one bit set and the |
--- |
| 17447 |
// SRL constant is equal to the log2 of the AND constant. The back-end is |
--- |
17447 |
// SRL constant is equal to the log2 of the AND constant. The back-end is |
--- |
| 17448 |
// smart enough to convert the result into a TEST/JMP sequence. |
--- |
17448 |
// smart enough to convert the result into a TEST/JMP sequence. |
--- |
| 17449 |
SDValue Op0 = N.getOperand(0); |
0 |
17449 |
SDValue Op0 = N.getOperand(0); |
0 |
| 17450 |
SDValue Op1 = N.getOperand(1); |
0 |
17450 |
SDValue Op1 = N.getOperand(1); |
0 |
| 17451 |
|
--- |
17451 |
|
--- |
| 17452 |
if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::Constant) { |
0 |
17452 |
if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::Constant) { |
0 |
| 17453 |
SDValue AndOp1 = Op0.getOperand(1); |
0 |
17453 |
SDValue AndOp1 = Op0.getOperand(1); |
0 |
| 17454 |
|
--- |
17454 |
|
--- |
| 17455 |
if (AndOp1.getOpcode() == ISD::Constant) { |
0 |
17455 |
if (AndOp1.getOpcode() == ISD::Constant) { |
0 |
| 17456 |
const APInt &AndConst = cast(AndOp1)->getAPIntValue(); |
0 |
17456 |
const APInt &AndConst = cast(AndOp1)->getAPIntValue(); |
0 |
| 17457 |
|
--- |
17457 |
|
--- |
| 17458 |
if (AndConst.isPowerOf2() && |
0 |
17458 |
if (AndConst.isPowerOf2() && |
0 |
| 17459 |
cast(Op1)->getAPIntValue() == AndConst.logBase2()) { |
0 |
17459 |
cast(Op1)->getAPIntValue() == AndConst.logBase2()) { |
0 |
| 17460 |
SDLoc DL(N); |
0 |
17460 |
SDLoc DL(N); |
0 |
| 17461 |
return DAG.getSetCC(DL, getSetCCResultType(Op0.getValueType()), |
0 |
17461 |
return DAG.getSetCC(DL, getSetCCResultType(Op0.getValueType()), |
0 |
| 17462 |
Op0, DAG.getConstant(0, DL, Op0.getValueType()), |
0 |
17462 |
Op0, DAG.getConstant(0, DL, Op0.getValueType()), |
0 |
| 17463 |
ISD::SETNE); |
0 |
17463 |
ISD::SETNE); |
0 |
| 17464 |
} |
0 |
17464 |
} |
0 |
| 17465 |
} |
--- |
17465 |
} |
--- |
| 17466 |
} |
--- |
17466 |
} |
--- |
| 17467 |
} |
--- |
17467 |
} |
--- |
| 17468 |
|
--- |
17468 |
|
--- |
| 17469 |
// Transform (brcond (xor x, y)) -> (brcond (setcc, x, y, ne)) |
--- |
17469 |
// Transform (brcond (xor x, y)) -> (brcond (setcc, x, y, ne)) |
--- |
| 17470 |
// Transform (brcond (xor (xor x, y), -1)) -> (brcond (setcc, x, y, eq)) |
--- |
17470 |
// Transform (brcond (xor (xor x, y), -1)) -> (brcond (setcc, x, y, eq)) |
--- |
| 17471 |
if (N.getOpcode() == ISD::XOR) { |
4 |
17471 |
if (N.getOpcode() == ISD::XOR) { |
4 |
| 17472 |
// Because we may call this on a speculatively constructed |
--- |
17472 |
// Because we may call this on a speculatively constructed |
--- |
| 17473 |
// SimplifiedSetCC Node, we need to simplify this node first. |
--- |
17473 |
// SimplifiedSetCC Node, we need to simplify this node first. |
--- |
| 17474 |
// Ideally this should be folded into SimplifySetCC and not |
--- |
17474 |
// Ideally this should be folded into SimplifySetCC and not |
--- |
| 17475 |
// here. For now, grab a handle to N so we don't lose it from |
--- |
17475 |
// here. For now, grab a handle to N so we don't lose it from |
--- |
| 17476 |
// replacements interal to the visit. |
--- |
17476 |
// replacements interal to the visit. |
--- |
| 17477 |
HandleSDNode XORHandle(N); |
1 |
17477 |
HandleSDNode XORHandle(N); |
1 |
| 17478 |
while (N.getOpcode() == ISD::XOR) { |
2 |
17478 |
while (N.getOpcode() == ISD::XOR) { |
2 |
| 17479 |
SDValue Tmp = visitXOR(N.getNode()); |
1 |
17479 |
SDValue Tmp = visitXOR(N.getNode()); |
1 |
| 17480 |
// No simplification done. |
--- |
17480 |
// No simplification done. |
--- |
| 17481 |
if (!Tmp.getNode()) |
1 |
17481 |
if (!Tmp.getNode()) |
1 |
| 17482 |
break; |
0 |
17482 |
break; |
0 |
| 17483 |
// Returning N is form in-visit replacement that may invalidated |
--- |
17483 |
// Returning N is form in-visit replacement that may invalidated |
--- |
| 17484 |
// N. Grab value from Handle. |
--- |
17484 |
// N. Grab value from Handle. |
--- |
| 17485 |
if (Tmp.getNode() == N.getNode()) |
1 |
17485 |
if (Tmp.getNode() == N.getNode()) |
1 |
| 17486 |
N = XORHandle.getValue(); |
0 |
17486 |
N = XORHandle.getValue(); |
0 |
| 17487 |
else // Node simplified. Try simplifying again. |
--- |
17487 |
else // Node simplified. Try simplifying again. |
--- |
| 17488 |
N = Tmp; |
1 |
17488 |
N = Tmp; |
1 |
| 17489 |
} |
--- |
17489 |
} |
--- |
| 17490 |
|
--- |
17490 |
|
--- |
| 17491 |
if (N.getOpcode() != ISD::XOR) |
1 |
17491 |
if (N.getOpcode() != ISD::XOR) |
1 |
| 17492 |
return N; |
1 |
17492 |
return N; |
1 |
| 17493 |
|
--- |
17493 |
|
--- |
| 17494 |
SDValue Op0 = N->getOperand(0); |
0 |
17494 |
SDValue Op0 = N->getOperand(0); |
0 |
| 17495 |
SDValue Op1 = N->getOperand(1); |
0 |
17495 |
SDValue Op1 = N->getOperand(1); |
0 |
| 17496 |
|
--- |
17496 |
|
--- |
| 17497 |
if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { |
0 |
17497 |
if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { |
0 |
| 17498 |
bool Equal = false; |
0 |
17498 |
bool Equal = false; |
0 |
| 17499 |
// (brcond (xor (xor x, y), -1)) -> (brcond (setcc x, y, eq)) |
--- |
17499 |
// (brcond (xor (xor x, y), -1)) -> (brcond (setcc x, y, eq)) |
--- |
| 17500 |
if (isBitwiseNot(N) && Op0.hasOneUse() && Op0.getOpcode() == ISD::XOR && |
0 |
17500 |
if (isBitwiseNot(N) && Op0.hasOneUse() && Op0.getOpcode() == ISD::XOR && |
0 |
| 17501 |
Op0.getValueType() == MVT::i1) { |
0 |
17501 |
Op0.getValueType() == MVT::i1) { |
0 |
| 17502 |
N = Op0; |
0 |
17502 |
N = Op0; |
0 |
| 17503 |
Op0 = N->getOperand(0); |
0 |
17503 |
Op0 = N->getOperand(0); |
0 |
| 17504 |
Op1 = N->getOperand(1); |
0 |
17504 |
Op1 = N->getOperand(1); |
0 |
| 17505 |
Equal = true; |
0 |
17505 |
Equal = true; |
0 |
| 17506 |
} |
--- |
17506 |
} |
--- |
| 17507 |
|
--- |
17507 |
|
--- |
| 17508 |
EVT SetCCVT = N.getValueType(); |
0 |
17508 |
EVT SetCCVT = N.getValueType(); |
0 |
| 17509 |
if (LegalTypes) |
0 |
17509 |
if (LegalTypes) |
0 |
| 17510 |
SetCCVT = getSetCCResultType(SetCCVT); |
0 |
17510 |
SetCCVT = getSetCCResultType(SetCCVT); |
0 |
| 17511 |
// Replace the uses of XOR with SETCC |
--- |
17511 |
// Replace the uses of XOR with SETCC |
--- |
| 17512 |
return DAG.getSetCC(SDLoc(N), SetCCVT, Op0, Op1, |
0 |
17512 |
return DAG.getSetCC(SDLoc(N), SetCCVT, Op0, Op1, |
0 |
| 17513 |
Equal ? ISD::SETEQ : ISD::SETNE); |
0 |
17513 |
Equal ? ISD::SETEQ : ISD::SETNE); |
0 |
| 17514 |
} |
--- |
17514 |
} |
--- |
| 17515 |
} |
1 |
17515 |
} |
1 |
| 17516 |
|
--- |
17516 |
|
--- |
| 17517 |
return SDValue(); |
3 |
17517 |
return SDValue(); |
3 |
| 17518 |
} |
--- |
17518 |
} |
--- |
| 17519 |
|
--- |
17519 |
|
--- |
| 17520 |
// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. |
--- |
17520 |
// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. |
--- |
| 17521 |
// |
--- |
17521 |
// |
--- |
| 17522 |
SDValue DAGCombiner::visitBR_CC(SDNode *N) { |
0 |
17522 |
SDValue DAGCombiner::visitBR_CC(SDNode *N) { |
0 |
| 17523 |
CondCodeSDNode *CC = cast(N->getOperand(1)); |
0 |
17523 |
CondCodeSDNode *CC = cast(N->getOperand(1)); |
0 |
| 17524 |
SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); |
0 |
17524 |
SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); |
0 |
| 17525 |
|
--- |
17525 |
|
--- |
| 17526 |
// If N is a constant we could fold this into a fallthrough or unconditional |
--- |
17526 |
// If N is a constant we could fold this into a fallthrough or unconditional |
--- |
| 17527 |
// branch. However that doesn't happen very often in normal code, because |
--- |
17527 |
// branch. However that doesn't happen very often in normal code, because |
--- |
| 17528 |
// Instcombine/SimplifyCFG should have handled the available opportunities. |
--- |
17528 |
// Instcombine/SimplifyCFG should have handled the available opportunities. |
--- |
| 17529 |
// If we did this folding here, it would be necessary to update the |
--- |
17529 |
// If we did this folding here, it would be necessary to update the |
--- |
| 17530 |
// MachineBasicBlock CFG, which is awkward. |
--- |
17530 |
// MachineBasicBlock CFG, which is awkward. |
--- |
| 17531 |
|
--- |
17531 |
|
--- |
| 17532 |
// Use SimplifySetCC to simplify SETCC's. |
--- |
17532 |
// Use SimplifySetCC to simplify SETCC's. |
--- |
| 17533 |
SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()), |
0 |
17533 |
SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()), |
0 |
| 17534 |
CondLHS, CondRHS, CC->get(), SDLoc(N), |
0 |
17534 |
CondLHS, CondRHS, CC->get(), SDLoc(N), |
0 |
| 17535 |
false); |
--- |
17535 |
false); |
--- |
| 17536 |
if (Simp.getNode()) AddToWorklist(Simp.getNode()); |
0 |
17536 |
if (Simp.getNode()) AddToWorklist(Simp.getNode()); |
0 |
| 17537 |
|
--- |
17537 |
|
--- |
| 17538 |
// fold to a simpler setcc |
--- |
17538 |
// fold to a simpler setcc |
--- |
| 17539 |
if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) |
0 |
17539 |
if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) |
0 |
| 17540 |
return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, |
0 |
17540 |
return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, |
0 |
| 17541 |
N->getOperand(0), Simp.getOperand(2), |
0 |
17541 |
N->getOperand(0), Simp.getOperand(2), |
0 |
| 17542 |
Simp.getOperand(0), Simp.getOperand(1), |
0 |
17542 |
Simp.getOperand(0), Simp.getOperand(1), |
0 |
| 17543 |
N->getOperand(4)); |
0 |
17543 |
N->getOperand(4)); |
0 |
| 17544 |
|
--- |
17544 |
|
--- |
| 17545 |
return SDValue(); |
0 |
17545 |
return SDValue(); |
0 |
| 17546 |
} |
--- |
17546 |
} |
--- |
| 17547 |
|
--- |
17547 |
|
--- |
| 17548 |
static bool getCombineLoadStoreParts(SDNode *N, unsigned Inc, unsigned Dec, |
18 |
17548 |
static bool getCombineLoadStoreParts(SDNode *N, unsigned Inc, unsigned Dec, |
18 |
| 17549 |
bool &IsLoad, bool &IsMasked, SDValue &Ptr, |
--- |
17549 |
bool &IsLoad, bool &IsMasked, SDValue &Ptr, |
--- |
| 17550 |
const TargetLowering &TLI) { |
--- |
17550 |
const TargetLowering &TLI) { |
--- |
| 17551 |
if (LoadSDNode *LD = dyn_cast(N)) { |
18 |
17551 |
if (LoadSDNode *LD = dyn_cast(N)) { |
18 |
| 17552 |
if (LD->isIndexed()) |
10 |
17552 |
if (LD->isIndexed()) |
10 |
| 17553 |
return false; |
10 |
17553 |
return false; |
10 |
| 17554 |
EVT VT = LD->getMemoryVT(); |
10 |
17554 |
EVT VT = LD->getMemoryVT(); |
10 |
| 17555 |
if (!TLI.isIndexedLoadLegal(Inc, VT) && !TLI.isIndexedLoadLegal(Dec, VT)) |
10 |
17555 |
if (!TLI.isIndexedLoadLegal(Inc, VT) && !TLI.isIndexedLoadLegal(Dec, VT)) |
10 |
| 17556 |
return false; |
10 |
17556 |
return false; |
10 |
| 17557 |
Ptr = LD->getBasePtr(); |
0 |
17557 |
Ptr = LD->getBasePtr(); |
0 |
| 17558 |
} else if (StoreSDNode *ST = dyn_cast(N)) { |
8 |
17558 |
} else if (StoreSDNode *ST = dyn_cast(N)) { |
8 |
| 17559 |
if (ST->isIndexed()) |
8 |
17559 |
if (ST->isIndexed()) |
8 |
| 17560 |
return false; |
8 |
17560 |
return false; |
8 |
| 17561 |
EVT VT = ST->getMemoryVT(); |
8 |
17561 |
EVT VT = ST->getMemoryVT(); |
8 |
| 17562 |
if (!TLI.isIndexedStoreLegal(Inc, VT) && !TLI.isIndexedStoreLegal(Dec, VT)) |
8 |
17562 |
if (!TLI.isIndexedStoreLegal(Inc, VT) && !TLI.isIndexedStoreLegal(Dec, VT)) |
8 |
| 17563 |
return false; |
8 |
17563 |
return false; |
8 |
| 17564 |
Ptr = ST->getBasePtr(); |
0 |
17564 |
Ptr = ST->getBasePtr(); |
0 |
| 17565 |
IsLoad = false; |
0 |
17565 |
IsLoad = false; |
0 |
| 17566 |
} else if (MaskedLoadSDNode *LD = dyn_cast(N)) { |
0 |
17566 |
} else if (MaskedLoadSDNode *LD = dyn_cast(N)) { |
0 |
| 17567 |
if (LD->isIndexed()) |
0 |
17567 |
if (LD->isIndexed()) |
0 |
| 17568 |
return false; |
0 |
17568 |
return false; |
0 |
| 17569 |
EVT VT = LD->getMemoryVT(); |
0 |
17569 |
EVT VT = LD->getMemoryVT(); |
0 |
| 17570 |
if (!TLI.isIndexedMaskedLoadLegal(Inc, VT) && |
0 |
17570 |
if (!TLI.isIndexedMaskedLoadLegal(Inc, VT) && |
0 |
| 17571 |
!TLI.isIndexedMaskedLoadLegal(Dec, VT)) |
0 |
17571 |
!TLI.isIndexedMaskedLoadLegal(Dec, VT)) |
0 |
| 17572 |
return false; |
0 |
17572 |
return false; |
0 |
| 17573 |
Ptr = LD->getBasePtr(); |
0 |
17573 |
Ptr = LD->getBasePtr(); |
0 |
| 17574 |
IsMasked = true; |
0 |
17574 |
IsMasked = true; |
0 |
| 17575 |
} else if (MaskedStoreSDNode *ST = dyn_cast(N)) { |
0 |
17575 |
} else if (MaskedStoreSDNode *ST = dyn_cast(N)) { |
0 |
| 17576 |
if (ST->isIndexed()) |
0 |
17576 |
if (ST->isIndexed()) |
0 |
| 17577 |
return false; |
0 |
17577 |
return false; |
0 |
| 17578 |
EVT VT = ST->getMemoryVT(); |
0 |
17578 |
EVT VT = ST->getMemoryVT(); |
0 |
| 17579 |
if (!TLI.isIndexedMaskedStoreLegal(Inc, VT) && |
0 |
17579 |
if (!TLI.isIndexedMaskedStoreLegal(Inc, VT) && |
0 |
| 17580 |
!TLI.isIndexedMaskedStoreLegal(Dec, VT)) |
0 |
17580 |
!TLI.isIndexedMaskedStoreLegal(Dec, VT)) |
0 |
| 17581 |
return false; |
0 |
17581 |
return false; |
0 |
| 17582 |
Ptr = ST->getBasePtr(); |
0 |
17582 |
Ptr = ST->getBasePtr(); |
0 |
| 17583 |
IsLoad = false; |
0 |
17583 |
IsLoad = false; |
0 |
| 17584 |
IsMasked = true; |
0 |
17584 |
IsMasked = true; |
0 |
| 17585 |
} else { |
--- |
17585 |
} else { |
--- |
| 17586 |
return false; |
0 |
17586 |
return false; |
0 |
| 17587 |
} |
--- |
17587 |
} |
--- |
| 17588 |
return true; |
0 |
17588 |
return true; |
0 |
| 17589 |
} |
--- |
17589 |
} |
--- |
| 17590 |
|
--- |
17590 |
|
--- |
| 17591 |
/// Try turning a load/store into a pre-indexed load/store when the base |
--- |
17591 |
/// Try turning a load/store into a pre-indexed load/store when the base |
--- |
| 17592 |
/// pointer is an add or subtract and it has other uses besides the load/store. |
--- |
17592 |
/// pointer is an add or subtract and it has other uses besides the load/store. |
--- |
| 17593 |
/// After the transformation, the new indexed load/store has effectively folded |
--- |
17593 |
/// After the transformation, the new indexed load/store has effectively folded |
--- |
| 17594 |
/// the add/subtract in and all of its other uses are redirected to the |
--- |
17594 |
/// the add/subtract in and all of its other uses are redirected to the |
--- |
| 17595 |
/// new load/store. |
--- |
17595 |
/// new load/store. |
--- |
| 17596 |
bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { |
22 |
17596 |
bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { |
22 |
| 17597 |
if (Level < AfterLegalizeDAG) |
22 |
17597 |
if (Level < AfterLegalizeDAG) |
22 |
| 17598 |
return false; |
13 |
17598 |
return false; |
13 |
| 17599 |
|
--- |
17599 |
|
--- |
| 17600 |
bool IsLoad = true; |
9 |
17600 |
bool IsLoad = true; |
9 |
| 17601 |
bool IsMasked = false; |
9 |
17601 |
bool IsMasked = false; |
9 |
| 17602 |
SDValue Ptr; |
9 |
17602 |
SDValue Ptr; |
9 |
| 17603 |
if (!getCombineLoadStoreParts(N, ISD::PRE_INC, ISD::PRE_DEC, IsLoad, IsMasked, |
9 |
17603 |
if (!getCombineLoadStoreParts(N, ISD::PRE_INC, ISD::PRE_DEC, IsLoad, IsMasked, |
9 |
| 17604 |
Ptr, TLI)) |
--- |
17604 |
Ptr, TLI)) |
--- |
| 17605 |
return false; |
9 |
17605 |
return false; |
9 |
| 17606 |
|
--- |
17606 |
|
--- |
| 17607 |
// If the pointer is not an add/sub, or if it doesn't have multiple uses, bail |
--- |
17607 |
// If the pointer is not an add/sub, or if it doesn't have multiple uses, bail |
--- |
| 17608 |
// out. There is no reason to make this a preinc/predec. |
--- |
17608 |
// out. There is no reason to make this a preinc/predec. |
--- |
| 17609 |
if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || |
0 |
17609 |
if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || |
0 |
| 17610 |
Ptr->hasOneUse()) |
0 |
17610 |
Ptr->hasOneUse()) |
0 |
| 17611 |
return false; |
0 |
17611 |
return false; |
0 |
| 17612 |
|
--- |
17612 |
|
--- |
| 17613 |
// Ask the target to do addressing mode selection. |
--- |
17613 |
// Ask the target to do addressing mode selection. |
--- |
| 17614 |
SDValue BasePtr; |
0 |
17614 |
SDValue BasePtr; |
0 |
| 17615 |
SDValue Offset; |
0 |
17615 |
SDValue Offset; |
0 |
| 17616 |
ISD::MemIndexedMode AM = ISD::UNINDEXED; |
0 |
17616 |
ISD::MemIndexedMode AM = ISD::UNINDEXED; |
0 |
| 17617 |
if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) |
0 |
17617 |
if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) |
0 |
| 17618 |
return false; |
0 |
17618 |
return false; |
0 |
| 17619 |
|
--- |
17619 |
|
--- |
| 17620 |
// Backends without true r+i pre-indexed forms may need to pass a |
--- |
17620 |
// Backends without true r+i pre-indexed forms may need to pass a |
--- |
| 17621 |
// constant base with a variable offset so that constant coercion |
--- |
17621 |
// constant base with a variable offset so that constant coercion |
--- |
| 17622 |
// will work with the patterns in canonical form. |
--- |
17622 |
// will work with the patterns in canonical form. |
--- |
| 17623 |
bool Swapped = false; |
0 |
17623 |
bool Swapped = false; |
0 |
| 17624 |
if (isa(BasePtr)) { |
0 |
17624 |
if (isa(BasePtr)) { |
0 |
| 17625 |
std::swap(BasePtr, Offset); |
0 |
17625 |
std::swap(BasePtr, Offset); |
0 |
| 17626 |
Swapped = true; |
0 |
17626 |
Swapped = true; |
0 |
| 17627 |
} |
--- |
17627 |
} |
--- |
| 17628 |
|
--- |
17628 |
|
--- |
| 17629 |
// Don't create a indexed load / store with zero offset. |
--- |
17629 |
// Don't create a indexed load / store with zero offset. |
--- |
| 17630 |
if (isNullConstant(Offset)) |
0 |
17630 |
if (isNullConstant(Offset)) |
0 |
| 17631 |
return false; |
0 |
17631 |
return false; |
0 |
| 17632 |
|
--- |
17632 |
|
--- |
| 17633 |
// Try turning it into a pre-indexed load / store except when: |
--- |
17633 |
// Try turning it into a pre-indexed load / store except when: |
--- |
| 17634 |
// 1) The new base ptr is a frame index. |
--- |
17634 |
// 1) The new base ptr is a frame index. |
--- |
| 17635 |
// 2) If N is a store and the new base ptr is either the same as or is a |
--- |
17635 |
// 2) If N is a store and the new base ptr is either the same as or is a |
--- |
| 17636 |
// predecessor of the value being stored. |
--- |
17636 |
// predecessor of the value being stored. |
--- |
| 17637 |
// 3) Another use of old base ptr is a predecessor of N. If ptr is folded |
--- |
17637 |
// 3) Another use of old base ptr is a predecessor of N. If ptr is folded |
--- |
| 17638 |
// that would create a cycle. |
--- |
17638 |
// that would create a cycle. |
--- |
| 17639 |
// 4) All uses are load / store ops that use it as old base ptr. |
--- |
17639 |
// 4) All uses are load / store ops that use it as old base ptr. |
--- |
| 17640 |
|
--- |
17640 |
|
--- |
| 17641 |
// Check #1. Preinc'ing a frame index would require copying the stack pointer |
--- |
17641 |
// Check #1. Preinc'ing a frame index would require copying the stack pointer |
--- |
| 17642 |
// (plus the implicit offset) to a register to preinc anyway. |
--- |
17642 |
// (plus the implicit offset) to a register to preinc anyway. |
--- |
| 17643 |
if (isa(BasePtr) || isa(BasePtr)) |
0 |
17643 |
if (isa(BasePtr) || isa(BasePtr)) |
0 |
| 17644 |
return false; |
0 |
17644 |
return false; |
0 |
| 17645 |
|
--- |
17645 |
|
--- |
| 17646 |
// Check #2. |
--- |
17646 |
// Check #2. |
--- |
| 17647 |
if (!IsLoad) { |
0 |
17647 |
if (!IsLoad) { |
0 |
| 17648 |
SDValue Val = IsMasked ? cast(N)->getValue() |
0 |
17648 |
SDValue Val = IsMasked ? cast(N)->getValue() |
0 |
| 17649 |
: cast(N)->getValue(); |
0 |
17649 |
: cast(N)->getValue(); |
0 |
| 17650 |
|
--- |
17650 |
|
--- |
| 17651 |
// Would require a copy. |
--- |
17651 |
// Would require a copy. |
--- |
| 17652 |
if (Val == BasePtr) |
0 |
17652 |
if (Val == BasePtr) |
0 |
| 17653 |
return false; |
0 |
17653 |
return false; |
0 |
| 17654 |
|
--- |
17654 |
|
--- |
| 17655 |
// Would create a cycle. |
--- |
17655 |
// Would create a cycle. |
--- |
| 17656 |
if (Val == Ptr || Ptr->isPredecessorOf(Val.getNode())) |
0 |
17656 |
if (Val == Ptr || Ptr->isPredecessorOf(Val.getNode())) |
0 |
| 17657 |
return false; |
0 |
17657 |
return false; |
0 |
| 17658 |
} |
--- |
17658 |
} |
--- |
| 17659 |
|
--- |
17659 |
|
--- |
| 17660 |
// Caches for hasPredecessorHelper. |
--- |
17660 |
// Caches for hasPredecessorHelper. |
--- |
| 17661 |
SmallPtrSet Visited; |
0 |
17661 |
SmallPtrSet Visited; |
0 |
| 17662 |
SmallVector Worklist; |
0 |
17662 |
SmallVector Worklist; |
0 |
| 17663 |
Worklist.push_back(N); |
0 |
17663 |
Worklist.push_back(N); |
0 |
| 17664 |
|
--- |
17664 |
|
--- |
| 17665 |
// If the offset is a constant, there may be other adds of constants that |
--- |
17665 |
// If the offset is a constant, there may be other adds of constants that |
--- |
| 17666 |
// can be folded with this one. We should do this to avoid having to keep |
--- |
17666 |
// can be folded with this one. We should do this to avoid having to keep |
--- |
| 17667 |
// a copy of the original base pointer. |
--- |
17667 |
// a copy of the original base pointer. |
--- |
| 17668 |
SmallVector OtherUses; |
0 |
17668 |
SmallVector OtherUses; |
0 |
| 17669 |
constexpr unsigned int MaxSteps = 8192; |
0 |
17669 |
constexpr unsigned int MaxSteps = 8192; |
0 |
| 17670 |
if (isa(Offset)) |
0 |
17670 |
if (isa(Offset)) |
0 |
| 17671 |
for (SDNode::use_iterator UI = BasePtr->use_begin(), |
0 |
17671 |
for (SDNode::use_iterator UI = BasePtr->use_begin(), |
0 |
| 17672 |
UE = BasePtr->use_end(); |
0 |
17672 |
UE = BasePtr->use_end(); |
0 |
| 17673 |
UI != UE; ++UI) { |
0 |
17673 |
UI != UE; ++UI) { |
0 |
| 17674 |
SDUse &Use = UI.getUse(); |
0 |
17674 |
SDUse &Use = UI.getUse(); |
0 |
| 17675 |
// Skip the use that is Ptr and uses of other results from BasePtr's |
--- |
17675 |
// Skip the use that is Ptr and uses of other results from BasePtr's |
--- |
| 17676 |
// node (important for nodes that return multiple results). |
--- |
17676 |
// node (important for nodes that return multiple results). |
--- |
| 17677 |
if (Use.getUser() == Ptr.getNode() || Use != BasePtr) |
0 |
17677 |
if (Use.getUser() == Ptr.getNode() || Use != BasePtr) |
0 |
| 17678 |
continue; |
0 |
17678 |
continue; |
0 |
| 17679 |
|
--- |
17679 |
|
--- |
| 17680 |
if (SDNode::hasPredecessorHelper(Use.getUser(), Visited, Worklist, |
0 |
17680 |
if (SDNode::hasPredecessorHelper(Use.getUser(), Visited, Worklist, |
0 |
| 17681 |
MaxSteps)) |
--- |
17681 |
MaxSteps)) |
--- |
| 17682 |
continue; |
0 |
17682 |
continue; |
0 |
| 17683 |
|
--- |
17683 |
|
--- |
| 17684 |
if (Use.getUser()->getOpcode() != ISD::ADD && |
0 |
17684 |
if (Use.getUser()->getOpcode() != ISD::ADD && |
0 |
| 17685 |
Use.getUser()->getOpcode() != ISD::SUB) { |
0 |
17685 |
Use.getUser()->getOpcode() != ISD::SUB) { |
0 |
| 17686 |
OtherUses.clear(); |
0 |
17686 |
OtherUses.clear(); |
0 |
| 17687 |
break; |
0 |
17687 |
break; |
0 |
| 17688 |
} |
--- |
17688 |
} |
--- |
| 17689 |
|
--- |
17689 |
|
--- |
| 17690 |
SDValue Op1 = Use.getUser()->getOperand((UI.getOperandNo() + 1) & 1); |
0 |
17690 |
SDValue Op1 = Use.getUser()->getOperand((UI.getOperandNo() + 1) & 1); |
0 |
| 17691 |
if (!isa(Op1)) { |
0 |
17691 |
if (!isa(Op1)) { |
0 |
| 17692 |
OtherUses.clear(); |
0 |
17692 |
OtherUses.clear(); |
0 |
| 17693 |
break; |
0 |
17693 |
break; |
0 |
| 17694 |
} |
--- |
17694 |
} |
--- |
| 17695 |
|
--- |
17695 |
|
--- |
| 17696 |
// FIXME: In some cases, we can be smarter about this. |
--- |
17696 |
// FIXME: In some cases, we can be smarter about this. |
--- |
| 17697 |
if (Op1.getValueType() != Offset.getValueType()) { |
0 |
17697 |
if (Op1.getValueType() != Offset.getValueType()) { |
0 |
| 17698 |
OtherUses.clear(); |
0 |
17698 |
OtherUses.clear(); |
0 |
| 17699 |
break; |
0 |
17699 |
break; |
0 |
| 17700 |
} |
--- |
17700 |
} |
--- |
| 17701 |
|
--- |
17701 |
|
--- |
| 17702 |
OtherUses.push_back(Use.getUser()); |
0 |
17702 |
OtherUses.push_back(Use.getUser()); |
0 |
| 17703 |
} |
--- |
17703 |
} |
--- |
| 17704 |
|
--- |
17704 |
|
--- |
| 17705 |
if (Swapped) |
0 |
17705 |
if (Swapped) |
0 |
| 17706 |
std::swap(BasePtr, Offset); |
0 |
17706 |
std::swap(BasePtr, Offset); |
0 |
| 17707 |
|
--- |
17707 |
|
--- |
| 17708 |
// Now check for #3 and #4. |
--- |
17708 |
// Now check for #3 and #4. |
--- |
| 17709 |
bool RealUse = false; |
0 |
17709 |
bool RealUse = false; |
0 |
| 17710 |
|
--- |
17710 |
|
--- |
| 17711 |
for (SDNode *Use : Ptr->uses()) { |
0 |
17711 |
for (SDNode *Use : Ptr->uses()) { |
0 |
| 17712 |
if (Use == N) |
0 |
17712 |
if (Use == N) |
0 |
| 17713 |
continue; |
0 |
17713 |
continue; |
0 |
| 17714 |
if (SDNode::hasPredecessorHelper(Use, Visited, Worklist, MaxSteps)) |
0 |
17714 |
if (SDNode::hasPredecessorHelper(Use, Visited, Worklist, MaxSteps)) |
0 |
| 17715 |
return false; |
0 |
17715 |
return false; |
0 |
| 17716 |
|
--- |
17716 |
|
--- |
| 17717 |
// If Ptr may be folded in addressing mode of other use, then it's |
--- |
17717 |
// If Ptr may be folded in addressing mode of other use, then it's |
--- |
| 17718 |
// not profitable to do this transformation. |
--- |
17718 |
// not profitable to do this transformation. |
--- |
| 17719 |
if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) |
0 |
17719 |
if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) |
0 |
| 17720 |
RealUse = true; |
0 |
17720 |
RealUse = true; |
0 |
| 17721 |
} |
--- |
17721 |
} |
--- |
| 17722 |
|
--- |
17722 |
|
--- |
| 17723 |
if (!RealUse) |
0 |
17723 |
if (!RealUse) |
0 |
| 17724 |
return false; |
0 |
17724 |
return false; |
0 |
| 17725 |
|
--- |
17725 |
|
--- |
| 17726 |
SDValue Result; |
0 |
17726 |
SDValue Result; |
0 |
| 17727 |
if (!IsMasked) { |
0 |
17727 |
if (!IsMasked) { |
0 |
| 17728 |
if (IsLoad) |
0 |
17728 |
if (IsLoad) |
0 |
| 17729 |
Result = DAG.getIndexedLoad(SDValue(N, 0), SDLoc(N), BasePtr, Offset, AM); |
0 |
17729 |
Result = DAG.getIndexedLoad(SDValue(N, 0), SDLoc(N), BasePtr, Offset, AM); |
0 |
| 17730 |
else |
--- |
17730 |
else |
--- |
| 17731 |
Result = |
0 |
17731 |
Result = |
0 |
| 17732 |
DAG.getIndexedStore(SDValue(N, 0), SDLoc(N), BasePtr, Offset, AM); |
0 |
17732 |
DAG.getIndexedStore(SDValue(N, 0), SDLoc(N), BasePtr, Offset, AM); |
0 |
| 17733 |
} else { |
--- |
17733 |
} else { |
--- |
| 17734 |
if (IsLoad) |
0 |
17734 |
if (IsLoad) |
0 |
| 17735 |
Result = DAG.getIndexedMaskedLoad(SDValue(N, 0), SDLoc(N), BasePtr, |
0 |
17735 |
Result = DAG.getIndexedMaskedLoad(SDValue(N, 0), SDLoc(N), BasePtr, |
0 |
| 17736 |
Offset, AM); |
--- |
17736 |
Offset, AM); |
--- |
| 17737 |
else |
--- |
17737 |
else |
--- |
| 17738 |
Result = DAG.getIndexedMaskedStore(SDValue(N, 0), SDLoc(N), BasePtr, |
0 |
17738 |
Result = DAG.getIndexedMaskedStore(SDValue(N, 0), SDLoc(N), BasePtr, |
0 |
| 17739 |
Offset, AM); |
--- |
17739 |
Offset, AM); |
--- |
| 17740 |
} |
--- |
17740 |
} |
--- |
| 17741 |
++PreIndexedNodes; |
0 |
17741 |
++PreIndexedNodes; |
0 |
| 17742 |
++NodesCombined; |
0 |
17742 |
++NodesCombined; |
0 |
| 17743 |
LLVM_DEBUG(dbgs() << "\nReplacing.4 "; N->dump(&DAG); dbgs() << "\nWith: "; |
0 |
17743 |
LLVM_DEBUG(dbgs() << "\nReplacing.4 "; N->dump(&DAG); dbgs() << "\nWith: "; |
0 |
| 17744 |
Result.dump(&DAG); dbgs() << '\n'); |
--- |
17744 |
Result.dump(&DAG); dbgs() << '\n'); |
--- |
| 17745 |
WorklistRemover DeadNodes(*this); |
0 |
17745 |
WorklistRemover DeadNodes(*this); |
0 |
| 17746 |
if (IsLoad) { |
0 |
17746 |
if (IsLoad) { |
0 |
| 17747 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); |
0 |
17747 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); |
0 |
| 17748 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); |
0 |
17748 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); |
0 |
| 17749 |
} else { |
--- |
17749 |
} else { |
--- |
| 17750 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); |
0 |
17750 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); |
0 |
| 17751 |
} |
--- |
17751 |
} |
--- |
| 17752 |
|
--- |
17752 |
|
--- |
| 17753 |
// Finally, since the node is now dead, remove it from the graph. |
--- |
17753 |
// Finally, since the node is now dead, remove it from the graph. |
--- |
| 17754 |
deleteAndRecombine(N); |
0 |
17754 |
deleteAndRecombine(N); |
0 |
| 17755 |
|
--- |
17755 |
|
--- |
| 17756 |
if (Swapped) |
0 |
17756 |
if (Swapped) |
0 |
| 17757 |
std::swap(BasePtr, Offset); |
0 |
17757 |
std::swap(BasePtr, Offset); |
0 |
| 17758 |
|
--- |
17758 |
|
--- |
| 17759 |
// Replace other uses of BasePtr that can be updated to use Ptr |
--- |
17759 |
// Replace other uses of BasePtr that can be updated to use Ptr |
--- |
| 17760 |
for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) { |
0 |
17760 |
for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) { |
0 |
| 17761 |
unsigned OffsetIdx = 1; |
0 |
17761 |
unsigned OffsetIdx = 1; |
0 |
| 17762 |
if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode()) |
0 |
17762 |
if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode()) |
0 |
| 17763 |
OffsetIdx = 0; |
0 |
17763 |
OffsetIdx = 0; |
0 |
| 17764 |
assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() == |
0 |
17764 |
assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() == |
0 |
| 17765 |
BasePtr.getNode() && "Expected BasePtr operand"); |
--- |
17765 |
BasePtr.getNode() && "Expected BasePtr operand"); |
--- |
| 17766 |
|
--- |
17766 |
|
--- |
| 17767 |
// We need to replace ptr0 in the following expression: |
--- |
17767 |
// We need to replace ptr0 in the following expression: |
--- |
| 17768 |
// x0 * offset0 + y0 * ptr0 = t0 |
--- |
17768 |
// x0 * offset0 + y0 * ptr0 = t0 |
--- |
| 17769 |
// knowing that |
--- |
17769 |
// knowing that |
--- |
| 17770 |
// x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store) |
--- |
17770 |
// x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store) |
--- |
| 17771 |
// |
--- |
17771 |
// |
--- |
| 17772 |
// where x0, x1, y0 and y1 in {-1, 1} are given by the types of the |
--- |
17772 |
// where x0, x1, y0 and y1 in {-1, 1} are given by the types of the |
--- |
| 17773 |
// indexed load/store and the expression that needs to be re-written. |
--- |
17773 |
// indexed load/store and the expression that needs to be re-written. |
--- |
| 17774 |
// |
--- |
17774 |
// |
--- |
| 17775 |
// Therefore, we have: |
--- |
17775 |
// Therefore, we have: |
--- |
| 17776 |
// t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1 |
--- |
17776 |
// t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1 |
--- |
| 17777 |
|
--- |
17777 |
|
--- |
| 17778 |
auto *CN = cast(OtherUses[i]->getOperand(OffsetIdx)); |
0 |
17778 |
auto *CN = cast(OtherUses[i]->getOperand(OffsetIdx)); |
0 |
| 17779 |
const APInt &Offset0 = CN->getAPIntValue(); |
0 |
17779 |
const APInt &Offset0 = CN->getAPIntValue(); |
0 |
| 17780 |
const APInt &Offset1 = cast(Offset)->getAPIntValue(); |
0 |
17780 |
const APInt &Offset1 = cast(Offset)->getAPIntValue(); |
0 |
| 17781 |
int X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1; |
0 |
17781 |
int X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1; |
0 |
| 17782 |
int Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1; |
0 |
17782 |
int Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1; |
0 |
| 17783 |
int X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1; |
0 |
17783 |
int X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1; |
0 |
| 17784 |
int Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1; |
0 |
17784 |
int Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1; |
0 |
| 17785 |
|
--- |
17785 |
|
--- |
| 17786 |
unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD; |
0 |
17786 |
unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD; |
0 |
| 17787 |
|
--- |
17787 |
|
--- |
| 17788 |
APInt CNV = Offset0; |
0 |
17788 |
APInt CNV = Offset0; |
0 |
| 17789 |
if (X0 < 0) CNV = -CNV; |
0 |
17789 |
if (X0 < 0) CNV = -CNV; |
0 |
| 17790 |
if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1; |
0 |
17790 |
if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1; |
0 |
| 17791 |
else CNV = CNV - Offset1; |
0 |
17791 |
else CNV = CNV - Offset1; |
0 |
| 17792 |
|
--- |
17792 |
|
--- |
| 17793 |
SDLoc DL(OtherUses[i]); |
0 |
17793 |
SDLoc DL(OtherUses[i]); |
0 |
| 17794 |
|
--- |
17794 |
|
--- |
| 17795 |
// We can now generate the new expression. |
--- |
17795 |
// We can now generate the new expression. |
--- |
| 17796 |
SDValue NewOp1 = DAG.getConstant(CNV, DL, CN->getValueType(0)); |
0 |
17796 |
SDValue NewOp1 = DAG.getConstant(CNV, DL, CN->getValueType(0)); |
0 |
| 17797 |
SDValue NewOp2 = Result.getValue(IsLoad ? 1 : 0); |
0 |
17797 |
SDValue NewOp2 = Result.getValue(IsLoad ? 1 : 0); |
0 |
| 17798 |
|
--- |
17798 |
|
--- |
| 17799 |
SDValue NewUse = DAG.getNode(Opcode, |
0 |
17799 |
SDValue NewUse = DAG.getNode(Opcode, |
0 |
| 17800 |
DL, |
--- |
17800 |
DL, |
--- |
| 17801 |
OtherUses[i]->getValueType(0), NewOp1, NewOp2); |
0 |
17801 |
OtherUses[i]->getValueType(0), NewOp1, NewOp2); |
0 |
| 17802 |
DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse); |
0 |
17802 |
DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse); |
0 |
| 17803 |
deleteAndRecombine(OtherUses[i]); |
0 |
17803 |
deleteAndRecombine(OtherUses[i]); |
0 |
| 17804 |
} |
0 |
17804 |
} |
0 |
| 17805 |
|
--- |
17805 |
|
--- |
| 17806 |
// Replace the uses of Ptr with uses of the updated base value. |
--- |
17806 |
// Replace the uses of Ptr with uses of the updated base value. |
--- |
| 17807 |
DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(IsLoad ? 1 : 0)); |
0 |
17807 |
DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(IsLoad ? 1 : 0)); |
0 |
| 17808 |
deleteAndRecombine(Ptr.getNode()); |
0 |
17808 |
deleteAndRecombine(Ptr.getNode()); |
0 |
| 17809 |
AddToWorklist(Result.getNode()); |
0 |
17809 |
AddToWorklist(Result.getNode()); |
0 |
| 17810 |
|
--- |
17810 |
|
--- |
| 17811 |
return true; |
0 |
17811 |
return true; |
0 |
| 17812 |
} |
0 |
17812 |
} |
0 |
| 17813 |
|
--- |
17813 |
|
--- |
| 17814 |
static bool shouldCombineToPostInc(SDNode *N, SDValue Ptr, SDNode *PtrUse, |
0 |
17814 |
static bool shouldCombineToPostInc(SDNode *N, SDValue Ptr, SDNode *PtrUse, |
0 |
| 17815 |
SDValue &BasePtr, SDValue &Offset, |
--- |
17815 |
SDValue &BasePtr, SDValue &Offset, |
--- |
| 17816 |
ISD::MemIndexedMode &AM, |
--- |
17816 |
ISD::MemIndexedMode &AM, |
--- |
| 17817 |
SelectionDAG &DAG, |
--- |
17817 |
SelectionDAG &DAG, |
--- |
| 17818 |
const TargetLowering &TLI) { |
--- |
17818 |
const TargetLowering &TLI) { |
--- |
| 17819 |
if (PtrUse == N || |
0 |
17819 |
if (PtrUse == N || |
0 |
| 17820 |
(PtrUse->getOpcode() != ISD::ADD && PtrUse->getOpcode() != ISD::SUB)) |
0 |
17820 |
(PtrUse->getOpcode() != ISD::ADD && PtrUse->getOpcode() != ISD::SUB)) |
0 |
| 17821 |
return false; |
0 |
17821 |
return false; |
0 |
| 17822 |
|
--- |
17822 |
|
--- |
| 17823 |
if (!TLI.getPostIndexedAddressParts(N, PtrUse, BasePtr, Offset, AM, DAG)) |
0 |
17823 |
if (!TLI.getPostIndexedAddressParts(N, PtrUse, BasePtr, Offset, AM, DAG)) |
0 |
| 17824 |
return false; |
0 |
17824 |
return false; |
0 |
| 17825 |
|
--- |
17825 |
|
--- |
| 17826 |
// Don't create a indexed load / store with zero offset. |
--- |
17826 |
// Don't create a indexed load / store with zero offset. |
--- |
| 17827 |
if (isNullConstant(Offset)) |
0 |
17827 |
if (isNullConstant(Offset)) |
0 |
| 17828 |
return false; |
0 |
17828 |
return false; |
0 |
| 17829 |
|
--- |
17829 |
|
--- |
| 17830 |
if (isa(BasePtr) || isa(BasePtr)) |
0 |
17830 |
if (isa(BasePtr) || isa(BasePtr)) |
0 |
| 17831 |
return false; |
0 |
17831 |
return false; |
0 |
| 17832 |
|
--- |
17832 |
|
--- |
| 17833 |
SmallPtrSet Visited; |
0 |
17833 |
SmallPtrSet Visited; |
0 |
| 17834 |
for (SDNode *Use : BasePtr->uses()) { |
0 |
17834 |
for (SDNode *Use : BasePtr->uses()) { |
0 |
| 17835 |
if (Use == Ptr.getNode()) |
0 |
17835 |
if (Use == Ptr.getNode()) |
0 |
| 17836 |
continue; |
0 |
17836 |
continue; |
0 |
| 17837 |
|
--- |
17837 |
|
--- |
| 17838 |
// No if there's a later user which could perform the index instead. |
--- |
17838 |
// No if there's a later user which could perform the index instead. |
--- |
| 17839 |
if (isa(Use)) { |
0 |
17839 |
if (isa(Use)) { |
0 |
| 17840 |
bool IsLoad = true; |
0 |
17840 |
bool IsLoad = true; |
0 |
| 17841 |
bool IsMasked = false; |
0 |
17841 |
bool IsMasked = false; |
0 |
| 17842 |
SDValue OtherPtr; |
0 |
17842 |
SDValue OtherPtr; |
0 |
| 17843 |
if (getCombineLoadStoreParts(Use, ISD::POST_INC, ISD::POST_DEC, IsLoad, |
0 |
17843 |
if (getCombineLoadStoreParts(Use, ISD::POST_INC, ISD::POST_DEC, IsLoad, |
0 |
| 17844 |
IsMasked, OtherPtr, TLI)) { |
--- |
17844 |
IsMasked, OtherPtr, TLI)) { |
--- |
| 17845 |
SmallVector Worklist; |
0 |
17845 |
SmallVector Worklist; |
0 |
| 17846 |
Worklist.push_back(Use); |
0 |
17846 |
Worklist.push_back(Use); |
0 |
| 17847 |
if (SDNode::hasPredecessorHelper(N, Visited, Worklist)) |
0 |
17847 |
if (SDNode::hasPredecessorHelper(N, Visited, Worklist)) |
0 |
| 17848 |
return false; |
0 |
17848 |
return false; |
0 |
| 17849 |
} |
0 |
17849 |
} |
0 |
| 17850 |
} |
--- |
17850 |
} |
--- |
| 17851 |
|
--- |
17851 |
|
--- |
| 17852 |
// If all the uses are load / store addresses, then don't do the |
--- |
17852 |
// If all the uses are load / store addresses, then don't do the |
--- |
| 17853 |
// transformation. |
--- |
17853 |
// transformation. |
--- |
| 17854 |
if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB) { |
0 |
17854 |
if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB) { |
0 |
| 17855 |
for (SDNode *UseUse : Use->uses()) |
0 |
17855 |
for (SDNode *UseUse : Use->uses()) |
0 |
| 17856 |
if (canFoldInAddressingMode(Use, UseUse, DAG, TLI)) |
0 |
17856 |
if (canFoldInAddressingMode(Use, UseUse, DAG, TLI)) |
0 |
| 17857 |
return false; |
0 |
17857 |
return false; |
0 |
| 17858 |
} |
--- |
17858 |
} |
--- |
| 17859 |
} |
--- |
17859 |
} |
--- |
| 17860 |
return true; |
0 |
17860 |
return true; |
0 |
| 17861 |
} |
0 |
17861 |
} |
0 |
| 17862 |
|
--- |
17862 |
|
--- |
| 17863 |
static SDNode *getPostIndexedLoadStoreOp(SDNode *N, bool &IsLoad, |
9 |
17863 |
static SDNode *getPostIndexedLoadStoreOp(SDNode *N, bool &IsLoad, |
9 |
| 17864 |
bool &IsMasked, SDValue &Ptr, |
--- |
17864 |
bool &IsMasked, SDValue &Ptr, |
--- |
| 17865 |
SDValue &BasePtr, SDValue &Offset, |
--- |
17865 |
SDValue &BasePtr, SDValue &Offset, |
--- |
| 17866 |
ISD::MemIndexedMode &AM, |
--- |
17866 |
ISD::MemIndexedMode &AM, |
--- |
| 17867 |
SelectionDAG &DAG, |
--- |
17867 |
SelectionDAG &DAG, |
--- |
| 17868 |
const TargetLowering &TLI) { |
--- |
17868 |
const TargetLowering &TLI) { |
--- |
| 17869 |
if (!getCombineLoadStoreParts(N, ISD::POST_INC, ISD::POST_DEC, IsLoad, |
9 |
17869 |
if (!getCombineLoadStoreParts(N, ISD::POST_INC, ISD::POST_DEC, IsLoad, |
9 |
| 17870 |
IsMasked, Ptr, TLI) || |
9 |
17870 |
IsMasked, Ptr, TLI) || |
9 |
| 17871 |
Ptr->hasOneUse()) |
0 |
17871 |
Ptr->hasOneUse()) |
0 |
| 17872 |
return nullptr; |
9 |
17872 |
return nullptr; |
9 |
| 17873 |
|
--- |
17873 |
|
--- |
| 17874 |
// Try turning it into a post-indexed load / store except when |
--- |
17874 |
// Try turning it into a post-indexed load / store except when |
--- |
| 17875 |
// 1) All uses are load / store ops that use it as base ptr (and |
--- |
17875 |
// 1) All uses are load / store ops that use it as base ptr (and |
--- |
| 17876 |
// it may be folded as addressing mmode). |
--- |
17876 |
// it may be folded as addressing mmode). |
--- |
| 17877 |
// 2) Op must be independent of N, i.e. Op is neither a predecessor |
--- |
17877 |
// 2) Op must be independent of N, i.e. Op is neither a predecessor |
--- |
| 17878 |
// nor a successor of N. Otherwise, if Op is folded that would |
--- |
17878 |
// nor a successor of N. Otherwise, if Op is folded that would |
--- |
| 17879 |
// create a cycle. |
--- |
17879 |
// create a cycle. |
--- |
| 17880 |
for (SDNode *Op : Ptr->uses()) { |
0 |
17880 |
for (SDNode *Op : Ptr->uses()) { |
0 |
| 17881 |
// Check for #1. |
--- |
17881 |
// Check for #1. |
--- |
| 17882 |
if (!shouldCombineToPostInc(N, Ptr, Op, BasePtr, Offset, AM, DAG, TLI)) |
0 |
17882 |
if (!shouldCombineToPostInc(N, Ptr, Op, BasePtr, Offset, AM, DAG, TLI)) |
0 |
| 17883 |
continue; |
0 |
17883 |
continue; |
0 |
| 17884 |
|
--- |
17884 |
|
--- |
| 17885 |
// Check for #2. |
--- |
17885 |
// Check for #2. |
--- |
| 17886 |
SmallPtrSet Visited; |
0 |
17886 |
SmallPtrSet Visited; |
0 |
| 17887 |
SmallVector Worklist; |
0 |
17887 |
SmallVector Worklist; |
0 |
| 17888 |
constexpr unsigned int MaxSteps = 8192; |
0 |
17888 |
constexpr unsigned int MaxSteps = 8192; |
0 |
| 17889 |
// Ptr is predecessor to both N and Op. |
--- |
17889 |
// Ptr is predecessor to both N and Op. |
--- |
| 17890 |
Visited.insert(Ptr.getNode()); |
0 |
17890 |
Visited.insert(Ptr.getNode()); |
0 |
| 17891 |
Worklist.push_back(N); |
0 |
17891 |
Worklist.push_back(N); |
0 |
| 17892 |
Worklist.push_back(Op); |
0 |
17892 |
Worklist.push_back(Op); |
0 |
| 17893 |
if (!SDNode::hasPredecessorHelper(N, Visited, Worklist, MaxSteps) && |
0 |
17893 |
if (!SDNode::hasPredecessorHelper(N, Visited, Worklist, MaxSteps) && |
0 |
| 17894 |
!SDNode::hasPredecessorHelper(Op, Visited, Worklist, MaxSteps)) |
0 |
17894 |
!SDNode::hasPredecessorHelper(Op, Visited, Worklist, MaxSteps)) |
0 |
| 17895 |
return Op; |
0 |
17895 |
return Op; |
0 |
| 17896 |
} |
0 |
17896 |
} |
0 |
| 17897 |
return nullptr; |
0 |
17897 |
return nullptr; |
0 |
| 17898 |
} |
--- |
17898 |
} |
--- |
| 17899 |
|
--- |
17899 |
|
--- |
| 17900 |
/// Try to combine a load/store with a add/sub of the base pointer node into a |
--- |
17900 |
/// Try to combine a load/store with a add/sub of the base pointer node into a |
--- |
| 17901 |
/// post-indexed load/store. The transformation folded the add/subtract into the |
--- |
17901 |
/// post-indexed load/store. The transformation folded the add/subtract into the |
--- |
| 17902 |
/// new indexed load/store effectively and all of its uses are redirected to the |
--- |
17902 |
/// new indexed load/store effectively and all of its uses are redirected to the |
--- |
| 17903 |
/// new load/store. |
--- |
17903 |
/// new load/store. |
--- |
| 17904 |
bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { |
22 |
17904 |
bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { |
22 |
| 17905 |
if (Level < AfterLegalizeDAG) |
22 |
17905 |
if (Level < AfterLegalizeDAG) |
22 |
| 17906 |
return false; |
13 |
17906 |
return false; |
13 |
| 17907 |
|
--- |
17907 |
|
--- |
| 17908 |
bool IsLoad = true; |
9 |
17908 |
bool IsLoad = true; |
9 |
| 17909 |
bool IsMasked = false; |
9 |
17909 |
bool IsMasked = false; |
9 |
| 17910 |
SDValue Ptr; |
9 |
17910 |
SDValue Ptr; |
9 |
| 17911 |
SDValue BasePtr; |
9 |
17911 |
SDValue BasePtr; |
9 |
| 17912 |
SDValue Offset; |
9 |
17912 |
SDValue Offset; |
9 |
| 17913 |
ISD::MemIndexedMode AM = ISD::UNINDEXED; |
9 |
17913 |
ISD::MemIndexedMode AM = ISD::UNINDEXED; |
9 |
| 17914 |
SDNode *Op = getPostIndexedLoadStoreOp(N, IsLoad, IsMasked, Ptr, BasePtr, |
9 |
17914 |
SDNode *Op = getPostIndexedLoadStoreOp(N, IsLoad, IsMasked, Ptr, BasePtr, |
9 |
| 17915 |
Offset, AM, DAG, TLI); |
--- |
17915 |
Offset, AM, DAG, TLI); |
--- |
| 17916 |
if (!Op) |
9 |
17916 |
if (!Op) |
9 |
| 17917 |
return false; |
9 |
17917 |
return false; |
9 |
| 17918 |
|
--- |
17918 |
|
--- |
| 17919 |
SDValue Result; |
0 |
17919 |
SDValue Result; |
0 |
| 17920 |
if (!IsMasked) |
0 |
17920 |
if (!IsMasked) |
0 |
| 17921 |
Result = IsLoad ? DAG.getIndexedLoad(SDValue(N, 0), SDLoc(N), BasePtr, |
0 |
17921 |
Result = IsLoad ? DAG.getIndexedLoad(SDValue(N, 0), SDLoc(N), BasePtr, |
0 |
| 17922 |
Offset, AM) |
--- |
17922 |
Offset, AM) |
--- |
| 17923 |
: DAG.getIndexedStore(SDValue(N, 0), SDLoc(N), |
0 |
17923 |
: DAG.getIndexedStore(SDValue(N, 0), SDLoc(N), |
0 |
| 17924 |
BasePtr, Offset, AM); |
--- |
17924 |
BasePtr, Offset, AM); |
--- |
| 17925 |
else |
--- |
17925 |
else |
--- |
| 17926 |
Result = IsLoad ? DAG.getIndexedMaskedLoad(SDValue(N, 0), SDLoc(N), |
0 |
17926 |
Result = IsLoad ? DAG.getIndexedMaskedLoad(SDValue(N, 0), SDLoc(N), |
0 |
| 17927 |
BasePtr, Offset, AM) |
--- |
17927 |
BasePtr, Offset, AM) |
--- |
| 17928 |
: DAG.getIndexedMaskedStore(SDValue(N, 0), SDLoc(N), |
0 |
17928 |
: DAG.getIndexedMaskedStore(SDValue(N, 0), SDLoc(N), |
0 |
| 17929 |
BasePtr, Offset, AM); |
--- |
17929 |
BasePtr, Offset, AM); |
--- |
| 17930 |
++PostIndexedNodes; |
0 |
17930 |
++PostIndexedNodes; |
0 |
| 17931 |
++NodesCombined; |
0 |
17931 |
++NodesCombined; |
0 |
| 17932 |
LLVM_DEBUG(dbgs() << "\nReplacing.5 "; N->dump(&DAG); dbgs() << "\nWith: "; |
0 |
17932 |
LLVM_DEBUG(dbgs() << "\nReplacing.5 "; N->dump(&DAG); dbgs() << "\nWith: "; |
0 |
| 17933 |
Result.dump(&DAG); dbgs() << '\n'); |
--- |
17933 |
Result.dump(&DAG); dbgs() << '\n'); |
--- |
| 17934 |
WorklistRemover DeadNodes(*this); |
0 |
17934 |
WorklistRemover DeadNodes(*this); |
0 |
| 17935 |
if (IsLoad) { |
0 |
17935 |
if (IsLoad) { |
0 |
| 17936 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); |
0 |
17936 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); |
0 |
| 17937 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); |
0 |
17937 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); |
0 |
| 17938 |
} else { |
--- |
17938 |
} else { |
--- |
| 17939 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); |
0 |
17939 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); |
0 |
| 17940 |
} |
--- |
17940 |
} |
--- |
| 17941 |
|
--- |
17941 |
|
--- |
| 17942 |
// Finally, since the node is now dead, remove it from the graph. |
--- |
17942 |
// Finally, since the node is now dead, remove it from the graph. |
--- |
| 17943 |
deleteAndRecombine(N); |
0 |
17943 |
deleteAndRecombine(N); |
0 |
| 17944 |
|
--- |
17944 |
|
--- |
| 17945 |
// Replace the uses of Use with uses of the updated base value. |
--- |
17945 |
// Replace the uses of Use with uses of the updated base value. |
--- |
| 17946 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), |
0 |
17946 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), |
0 |
| 17947 |
Result.getValue(IsLoad ? 1 : 0)); |
--- |
17947 |
Result.getValue(IsLoad ? 1 : 0)); |
--- |
| 17948 |
deleteAndRecombine(Op); |
0 |
17948 |
deleteAndRecombine(Op); |
0 |
| 17949 |
return true; |
0 |
17949 |
return true; |
0 |
| 17950 |
} |
0 |
17950 |
} |
0 |
| 17951 |
|
--- |
17951 |
|
--- |
| 17952 |
/// Return the base-pointer arithmetic from an indexed \p LD. |
--- |
17952 |
/// Return the base-pointer arithmetic from an indexed \p LD. |
--- |
| 17953 |
SDValue DAGCombiner::SplitIndexingFromLoad(LoadSDNode *LD) { |
0 |
17953 |
SDValue DAGCombiner::SplitIndexingFromLoad(LoadSDNode *LD) { |
0 |
| 17954 |
ISD::MemIndexedMode AM = LD->getAddressingMode(); |
0 |
17954 |
ISD::MemIndexedMode AM = LD->getAddressingMode(); |
0 |
| 17955 |
assert(AM != ISD::UNINDEXED); |
0 |
17955 |
assert(AM != ISD::UNINDEXED); |
0 |
| 17956 |
SDValue BP = LD->getOperand(1); |
0 |
17956 |
SDValue BP = LD->getOperand(1); |
0 |
| 17957 |
SDValue Inc = LD->getOperand(2); |
0 |
17957 |
SDValue Inc = LD->getOperand(2); |
0 |
| 17958 |
|
--- |
17958 |
|
--- |
| 17959 |
// Some backends use TargetConstants for load offsets, but don't expect |
--- |
17959 |
// Some backends use TargetConstants for load offsets, but don't expect |
--- |
| 17960 |
// TargetConstants in general ADD nodes. We can convert these constants into |
--- |
17960 |
// TargetConstants in general ADD nodes. We can convert these constants into |
--- |
| 17961 |
// regular Constants (if the constant is not opaque). |
--- |
17961 |
// regular Constants (if the constant is not opaque). |
--- |
| 17962 |
assert((Inc.getOpcode() != ISD::TargetConstant || |
0 |
17962 |
assert((Inc.getOpcode() != ISD::TargetConstant || |
0 |
| 17963 |
!cast(Inc)->isOpaque()) && |
--- |
17963 |
!cast(Inc)->isOpaque()) && |
--- |
| 17964 |
"Cannot split out indexing using opaque target constants"); |
--- |
17964 |
"Cannot split out indexing using opaque target constants"); |
--- |
| 17965 |
if (Inc.getOpcode() == ISD::TargetConstant) { |
0 |
17965 |
if (Inc.getOpcode() == ISD::TargetConstant) { |
0 |
| 17966 |
ConstantSDNode *ConstInc = cast(Inc); |
0 |
17966 |
ConstantSDNode *ConstInc = cast(Inc); |
0 |
| 17967 |
Inc = DAG.getConstant(*ConstInc->getConstantIntValue(), SDLoc(Inc), |
0 |
17967 |
Inc = DAG.getConstant(*ConstInc->getConstantIntValue(), SDLoc(Inc), |
0 |
| 17968 |
ConstInc->getValueType(0)); |
--- |
17968 |
ConstInc->getValueType(0)); |
--- |
| 17969 |
} |
--- |
17969 |
} |
--- |
| 17970 |
|
--- |
17970 |
|
--- |
| 17971 |
unsigned Opc = |
0 |
17971 |
unsigned Opc = |
0 |
| 17972 |
(AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB); |
0 |
17972 |
(AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB); |
0 |
| 17973 |
return DAG.getNode(Opc, SDLoc(LD), BP.getSimpleValueType(), BP, Inc); |
0 |
17973 |
return DAG.getNode(Opc, SDLoc(LD), BP.getSimpleValueType(), BP, Inc); |
0 |
| 17974 |
} |
--- |
17974 |
} |
--- |
| 17975 |
|
--- |
17975 |
|
--- |
| 17976 |
static inline ElementCount numVectorEltsOrZero(EVT T) { |
0 |
17976 |
static inline ElementCount numVectorEltsOrZero(EVT T) { |
0 |
| 17977 |
return T.isVector() ? T.getVectorElementCount() : ElementCount::getFixed(0); |
0 |
17977 |
return T.isVector() ? T.getVectorElementCount() : ElementCount::getFixed(0); |
0 |
| 17978 |
} |
--- |
17978 |
} |
--- |
| 17979 |
|
--- |
17979 |
|
--- |
| 17980 |
bool DAGCombiner::getTruncatedStoreValue(StoreSDNode *ST, SDValue &Val) { |
0 |
17980 |
bool DAGCombiner::getTruncatedStoreValue(StoreSDNode *ST, SDValue &Val) { |
0 |
| 17981 |
EVT STType = Val.getValueType(); |
0 |
17981 |
EVT STType = Val.getValueType(); |
0 |
| 17982 |
EVT STMemType = ST->getMemoryVT(); |
0 |
17982 |
EVT STMemType = ST->getMemoryVT(); |
0 |
| 17983 |
if (STType == STMemType) |
0 |
17983 |
if (STType == STMemType) |
0 |
| 17984 |
return true; |
0 |
17984 |
return true; |
0 |
| 17985 |
if (isTypeLegal(STMemType)) |
0 |
17985 |
if (isTypeLegal(STMemType)) |
0 |
| 17986 |
return false; // fail. |
0 |
17986 |
return false; // fail. |
0 |
| 17987 |
if (STType.isFloatingPoint() && STMemType.isFloatingPoint() && |
0 |
17987 |
if (STType.isFloatingPoint() && STMemType.isFloatingPoint() && |
0 |
| 17988 |
TLI.isOperationLegal(ISD::FTRUNC, STMemType)) { |
0 |
17988 |
TLI.isOperationLegal(ISD::FTRUNC, STMemType)) { |
0 |
| 17989 |
Val = DAG.getNode(ISD::FTRUNC, SDLoc(ST), STMemType, Val); |
0 |
17989 |
Val = DAG.getNode(ISD::FTRUNC, SDLoc(ST), STMemType, Val); |
0 |
| 17990 |
return true; |
0 |
17990 |
return true; |
0 |
| 17991 |
} |
--- |
17991 |
} |
--- |
| 17992 |
if (numVectorEltsOrZero(STType) == numVectorEltsOrZero(STMemType) && |
0 |
17992 |
if (numVectorEltsOrZero(STType) == numVectorEltsOrZero(STMemType) && |
0 |
| 17993 |
STType.isInteger() && STMemType.isInteger()) { |
0 |
17993 |
STType.isInteger() && STMemType.isInteger()) { |
0 |
| 17994 |
Val = DAG.getNode(ISD::TRUNCATE, SDLoc(ST), STMemType, Val); |
0 |
17994 |
Val = DAG.getNode(ISD::TRUNCATE, SDLoc(ST), STMemType, Val); |
0 |
| 17995 |
return true; |
0 |
17995 |
return true; |
0 |
| 17996 |
} |
--- |
17996 |
} |
--- |
| 17997 |
if (STType.getSizeInBits() == STMemType.getSizeInBits()) { |
0 |
17997 |
if (STType.getSizeInBits() == STMemType.getSizeInBits()) { |
0 |
| 17998 |
Val = DAG.getBitcast(STMemType, Val); |
0 |
17998 |
Val = DAG.getBitcast(STMemType, Val); |
0 |
| 17999 |
return true; |
0 |
17999 |
return true; |
0 |
| 18000 |
} |
--- |
18000 |
} |
--- |
| 18001 |
return false; // fail. |
0 |
18001 |
return false; // fail. |
0 |
| 18002 |
} |
--- |
18002 |
} |
--- |
| 18003 |
|
--- |
18003 |
|
--- |
| 18004 |
bool DAGCombiner::extendLoadedValueToExtension(LoadSDNode *LD, SDValue &Val) { |
0 |
18004 |
bool DAGCombiner::extendLoadedValueToExtension(LoadSDNode *LD, SDValue &Val) { |
0 |
| 18005 |
EVT LDMemType = LD->getMemoryVT(); |
0 |
18005 |
EVT LDMemType = LD->getMemoryVT(); |
0 |
| 18006 |
EVT LDType = LD->getValueType(0); |
0 |
18006 |
EVT LDType = LD->getValueType(0); |
0 |
| 18007 |
assert(Val.getValueType() == LDMemType && |
0 |
18007 |
assert(Val.getValueType() == LDMemType && |
0 |
| 18008 |
"Attempting to extend value of non-matching type"); |
--- |
18008 |
"Attempting to extend value of non-matching type"); |
--- |
| 18009 |
if (LDType == LDMemType) |
0 |
18009 |
if (LDType == LDMemType) |
0 |
| 18010 |
return true; |
0 |
18010 |
return true; |
0 |
| 18011 |
if (LDMemType.isInteger() && LDType.isInteger()) { |
0 |
18011 |
if (LDMemType.isInteger() && LDType.isInteger()) { |
0 |
| 18012 |
switch (LD->getExtensionType()) { |
0 |
18012 |
switch (LD->getExtensionType()) { |
0 |
| 18013 |
case ISD::NON_EXTLOAD: |
0 |
18013 |
case ISD::NON_EXTLOAD: |
0 |
| 18014 |
Val = DAG.getBitcast(LDType, Val); |
0 |
18014 |
Val = DAG.getBitcast(LDType, Val); |
0 |
| 18015 |
return true; |
0 |
18015 |
return true; |
0 |
| 18016 |
case ISD::EXTLOAD: |
0 |
18016 |
case ISD::EXTLOAD: |
0 |
| 18017 |
Val = DAG.getNode(ISD::ANY_EXTEND, SDLoc(LD), LDType, Val); |
0 |
18017 |
Val = DAG.getNode(ISD::ANY_EXTEND, SDLoc(LD), LDType, Val); |
0 |
| 18018 |
return true; |
0 |
18018 |
return true; |
0 |
| 18019 |
case ISD::SEXTLOAD: |
0 |
18019 |
case ISD::SEXTLOAD: |
0 |
| 18020 |
Val = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(LD), LDType, Val); |
0 |
18020 |
Val = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(LD), LDType, Val); |
0 |
| 18021 |
return true; |
0 |
18021 |
return true; |
0 |
| 18022 |
case ISD::ZEXTLOAD: |
0 |
18022 |
case ISD::ZEXTLOAD: |
0 |
| 18023 |
Val = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(LD), LDType, Val); |
0 |
18023 |
Val = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(LD), LDType, Val); |
0 |
| 18024 |
return true; |
0 |
18024 |
return true; |
0 |
| 18025 |
} |
--- |
18025 |
} |
--- |
| 18026 |
} |
--- |
18026 |
} |
--- |
| 18027 |
return false; |
0 |
18027 |
return false; |
0 |
| 18028 |
} |
--- |
18028 |
} |
--- |
| 18029 |
|
--- |
18029 |
|
--- |
| 18030 |
StoreSDNode *DAGCombiner::getUniqueStoreFeeding(LoadSDNode *LD, |
0 |
18030 |
StoreSDNode *DAGCombiner::getUniqueStoreFeeding(LoadSDNode *LD, |
0 |
| 18031 |
int64_t &Offset) { |
--- |
18031 |
int64_t &Offset) { |
--- |
| 18032 |
SDValue Chain = LD->getOperand(0); |
0 |
18032 |
SDValue Chain = LD->getOperand(0); |
0 |
| 18033 |
|
--- |
18033 |
|
--- |
| 18034 |
// Look through CALLSEQ_START. |
--- |
18034 |
// Look through CALLSEQ_START. |
--- |
| 18035 |
if (Chain.getOpcode() == ISD::CALLSEQ_START) |
0 |
18035 |
if (Chain.getOpcode() == ISD::CALLSEQ_START) |
0 |
| 18036 |
Chain = Chain->getOperand(0); |
0 |
18036 |
Chain = Chain->getOperand(0); |
0 |
| 18037 |
|
--- |
18037 |
|
--- |
| 18038 |
StoreSDNode *ST = nullptr; |
0 |
18038 |
StoreSDNode *ST = nullptr; |
0 |
| 18039 |
SmallVector Aliases; |
0 |
18039 |
SmallVector Aliases; |
0 |
| 18040 |
if (Chain.getOpcode() == ISD::TokenFactor) { |
0 |
18040 |
if (Chain.getOpcode() == ISD::TokenFactor) { |
0 |
| 18041 |
// Look for unique store within the TokenFactor. |
--- |
18041 |
// Look for unique store within the TokenFactor. |
--- |
| 18042 |
for (SDValue Op : Chain->ops()) { |
0 |
18042 |
for (SDValue Op : Chain->ops()) { |
0 |
| 18043 |
StoreSDNode *Store = dyn_cast(Op.getNode()); |
0 |
18043 |
StoreSDNode *Store = dyn_cast(Op.getNode()); |
0 |
| 18044 |
if (!Store) |
0 |
18044 |
if (!Store) |
0 |
| 18045 |
continue; |
0 |
18045 |
continue; |
0 |
| 18046 |
BaseIndexOffset BasePtrLD = BaseIndexOffset::match(LD, DAG); |
0 |
18046 |
BaseIndexOffset BasePtrLD = BaseIndexOffset::match(LD, DAG); |
0 |
| 18047 |
BaseIndexOffset BasePtrST = BaseIndexOffset::match(Store, DAG); |
0 |
18047 |
BaseIndexOffset BasePtrST = BaseIndexOffset::match(Store, DAG); |
0 |
| 18048 |
if (!BasePtrST.equalBaseIndex(BasePtrLD, DAG, Offset)) |
0 |
18048 |
if (!BasePtrST.equalBaseIndex(BasePtrLD, DAG, Offset)) |
0 |
| 18049 |
continue; |
0 |
18049 |
continue; |
0 |
| 18050 |
// Make sure the store is not aliased with any nodes in TokenFactor. |
--- |
18050 |
// Make sure the store is not aliased with any nodes in TokenFactor. |
--- |
| 18051 |
GatherAllAliases(Store, Chain, Aliases); |
0 |
18051 |
GatherAllAliases(Store, Chain, Aliases); |
0 |
| 18052 |
if (Aliases.empty() || |
0 |
18052 |
if (Aliases.empty() || |
0 |
| 18053 |
(Aliases.size() == 1 && Aliases.front().getNode() == Store)) |
0 |
18053 |
(Aliases.size() == 1 && Aliases.front().getNode() == Store)) |
0 |
| 18054 |
ST = Store; |
0 |
18054 |
ST = Store; |
0 |
| 18055 |
break; |
0 |
18055 |
break; |
0 |
| 18056 |
} |
--- |
18056 |
} |
--- |
| 18057 |
} else { |
--- |
18057 |
} else { |
--- |
| 18058 |
StoreSDNode *Store = dyn_cast(Chain.getNode()); |
0 |
18058 |
StoreSDNode *Store = dyn_cast(Chain.getNode()); |
0 |
| 18059 |
if (Store) { |
0 |
18059 |
if (Store) { |
0 |
| 18060 |
BaseIndexOffset BasePtrLD = BaseIndexOffset::match(LD, DAG); |
0 |
18060 |
BaseIndexOffset BasePtrLD = BaseIndexOffset::match(LD, DAG); |
0 |
| 18061 |
BaseIndexOffset BasePtrST = BaseIndexOffset::match(Store, DAG); |
0 |
18061 |
BaseIndexOffset BasePtrST = BaseIndexOffset::match(Store, DAG); |
0 |
| 18062 |
if (BasePtrST.equalBaseIndex(BasePtrLD, DAG, Offset)) |
0 |
18062 |
if (BasePtrST.equalBaseIndex(BasePtrLD, DAG, Offset)) |
0 |
| 18063 |
ST = Store; |
0 |
18063 |
ST = Store; |
0 |
| 18064 |
} |
--- |
18064 |
} |
--- |
| 18065 |
} |
--- |
18065 |
} |
--- |
| 18066 |
|
--- |
18066 |
|
--- |
| 18067 |
return ST; |
0 |
18067 |
return ST; |
0 |
| 18068 |
} |
0 |
18068 |
} |
0 |
| 18069 |
|
--- |
18069 |
|
--- |
| 18070 |
SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) { |
12 |
18070 |
SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) { |
12 |
| 18071 |
if (OptLevel == CodeGenOpt::None || !LD->isSimple()) |
12 |
18071 |
if (OptLevel == CodeGenOpt::None || !LD->isSimple()) |
12 |
| 18072 |
return SDValue(); |
12 |
18072 |
return SDValue(); |
12 |
| 18073 |
SDValue Chain = LD->getOperand(0); |
0 |
18073 |
SDValue Chain = LD->getOperand(0); |
0 |
| 18074 |
int64_t Offset; |
--- |
18074 |
int64_t Offset; |
--- |
| 18075 |
|
--- |
18075 |
|
--- |
| 18076 |
StoreSDNode *ST = getUniqueStoreFeeding(LD, Offset); |
0 |
18076 |
StoreSDNode *ST = getUniqueStoreFeeding(LD, Offset); |
0 |
| 18077 |
// TODO: Relax this restriction for unordered atomics (see D66309) |
--- |
18077 |
// TODO: Relax this restriction for unordered atomics (see D66309) |
--- |
| 18078 |
if (!ST || !ST->isSimple() || ST->getAddressSpace() != LD->getAddressSpace()) |
0 |
18078 |
if (!ST || !ST->isSimple() || ST->getAddressSpace() != LD->getAddressSpace()) |
0 |
| 18079 |
return SDValue(); |
0 |
18079 |
return SDValue(); |
0 |
| 18080 |
|
--- |
18080 |
|
--- |
| 18081 |
EVT LDType = LD->getValueType(0); |
0 |
18081 |
EVT LDType = LD->getValueType(0); |
0 |
| 18082 |
EVT LDMemType = LD->getMemoryVT(); |
0 |
18082 |
EVT LDMemType = LD->getMemoryVT(); |
0 |
| 18083 |
EVT STMemType = ST->getMemoryVT(); |
0 |
18083 |
EVT STMemType = ST->getMemoryVT(); |
0 |
| 18084 |
EVT STType = ST->getValue().getValueType(); |
0 |
18084 |
EVT STType = ST->getValue().getValueType(); |
0 |
| 18085 |
|
--- |
18085 |
|
--- |
| 18086 |
// There are two cases to consider here: |
--- |
18086 |
// There are two cases to consider here: |
--- |
| 18087 |
// 1. The store is fixed width and the load is scalable. In this case we |
--- |
18087 |
// 1. The store is fixed width and the load is scalable. In this case we |
--- |
| 18088 |
// don't know at compile time if the store completely envelops the load |
--- |
18088 |
// don't know at compile time if the store completely envelops the load |
--- |
| 18089 |
// so we abandon the optimisation. |
--- |
18089 |
// so we abandon the optimisation. |
--- |
| 18090 |
// 2. The store is scalable and the load is fixed width. We could |
--- |
18090 |
// 2. The store is scalable and the load is fixed width. We could |
--- |
| 18091 |
// potentially support a limited number of cases here, but there has been |
--- |
18091 |
// potentially support a limited number of cases here, but there has been |
--- |
| 18092 |
// no cost-benefit analysis to prove it's worth it. |
--- |
18092 |
// no cost-benefit analysis to prove it's worth it. |
--- |
| 18093 |
bool LdStScalable = LDMemType.isScalableVT(); |
0 |
18093 |
bool LdStScalable = LDMemType.isScalableVT(); |
0 |
| 18094 |
if (LdStScalable != STMemType.isScalableVT()) |
0 |
18094 |
if (LdStScalable != STMemType.isScalableVT()) |
0 |
| 18095 |
return SDValue(); |
0 |
18095 |
return SDValue(); |
0 |
| 18096 |
|
--- |
18096 |
|
--- |
| 18097 |
// If we are dealing with scalable vectors on a big endian platform the |
--- |
18097 |
// If we are dealing with scalable vectors on a big endian platform the |
--- |
| 18098 |
// calculation of offsets below becomes trickier, since we do not know at |
--- |
18098 |
// calculation of offsets below becomes trickier, since we do not know at |
--- |
| 18099 |
// compile time the absolute size of the vector. Until we've done more |
--- |
18099 |
// compile time the absolute size of the vector. Until we've done more |
--- |
| 18100 |
// analysis on big-endian platforms it seems better to bail out for now. |
--- |
18100 |
// analysis on big-endian platforms it seems better to bail out for now. |
--- |
| 18101 |
if (LdStScalable && DAG.getDataLayout().isBigEndian()) |
0 |
18101 |
if (LdStScalable && DAG.getDataLayout().isBigEndian()) |
0 |
| 18102 |
return SDValue(); |
0 |
18102 |
return SDValue(); |
0 |
| 18103 |
|
--- |
18103 |
|
--- |
| 18104 |
// Normalize for Endianness. After this Offset=0 will denote that the least |
--- |
18104 |
// Normalize for Endianness. After this Offset=0 will denote that the least |
--- |
| 18105 |
// significant bit in the loaded value maps to the least significant bit in |
--- |
18105 |
// significant bit in the loaded value maps to the least significant bit in |
--- |
| 18106 |
// the stored value). With Offset=n (for n > 0) the loaded value starts at the |
--- |
18106 |
// the stored value). With Offset=n (for n > 0) the loaded value starts at the |
--- |
| 18107 |
// n:th least significant byte of the stored value. |
--- |
18107 |
// n:th least significant byte of the stored value. |
--- |
| 18108 |
int64_t OrigOffset = Offset; |
0 |
18108 |
int64_t OrigOffset = Offset; |
0 |
| 18109 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
18109 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
| 18110 |
Offset = ((int64_t)STMemType.getStoreSizeInBits().getFixedValue() - |
0 |
18110 |
Offset = ((int64_t)STMemType.getStoreSizeInBits().getFixedValue() - |
0 |
| 18111 |
(int64_t)LDMemType.getStoreSizeInBits().getFixedValue()) / |
0 |
18111 |
(int64_t)LDMemType.getStoreSizeInBits().getFixedValue()) / |
0 |
| 18112 |
8 - |
0 |
18112 |
8 - |
0 |
| 18113 |
Offset; |
--- |
18113 |
Offset; |
--- |
| 18114 |
|
--- |
18114 |
|
--- |
| 18115 |
// Check that the stored value cover all bits that are loaded. |
--- |
18115 |
// Check that the stored value cover all bits that are loaded. |
--- |
| 18116 |
bool STCoversLD; |
--- |
18116 |
bool STCoversLD; |
--- |
| 18117 |
|
--- |
18117 |
|
--- |
| 18118 |
TypeSize LdMemSize = LDMemType.getSizeInBits(); |
0 |
18118 |
TypeSize LdMemSize = LDMemType.getSizeInBits(); |
0 |
| 18119 |
TypeSize StMemSize = STMemType.getSizeInBits(); |
0 |
18119 |
TypeSize StMemSize = STMemType.getSizeInBits(); |
0 |
| 18120 |
if (LdStScalable) |
0 |
18120 |
if (LdStScalable) |
0 |
| 18121 |
STCoversLD = (Offset == 0) && LdMemSize == StMemSize; |
0 |
18121 |
STCoversLD = (Offset == 0) && LdMemSize == StMemSize; |
0 |
| 18122 |
else |
--- |
18122 |
else |
--- |
| 18123 |
STCoversLD = (Offset >= 0) && (Offset * 8 + LdMemSize.getFixedValue() <= |
0 |
18123 |
STCoversLD = (Offset >= 0) && (Offset * 8 + LdMemSize.getFixedValue() <= |
0 |
| 18124 |
StMemSize.getFixedValue()); |
0 |
18124 |
StMemSize.getFixedValue()); |
0 |
| 18125 |
|
--- |
18125 |
|
--- |
| 18126 |
auto ReplaceLd = [&](LoadSDNode *LD, SDValue Val, SDValue Chain) -> SDValue { |
0 |
18126 |
auto ReplaceLd = [&](LoadSDNode *LD, SDValue Val, SDValue Chain) -> SDValue { |
0 |
| 18127 |
if (LD->isIndexed()) { |
0 |
18127 |
if (LD->isIndexed()) { |
0 |
| 18128 |
// Cannot handle opaque target constants and we must respect the user's |
--- |
18128 |
// Cannot handle opaque target constants and we must respect the user's |
--- |
| 18129 |
// request not to split indexes from loads. |
--- |
18129 |
// request not to split indexes from loads. |
--- |
| 18130 |
if (!canSplitIdx(LD)) |
0 |
18130 |
if (!canSplitIdx(LD)) |
0 |
| 18131 |
return SDValue(); |
0 |
18131 |
return SDValue(); |
0 |
| 18132 |
SDValue Idx = SplitIndexingFromLoad(LD); |
0 |
18132 |
SDValue Idx = SplitIndexingFromLoad(LD); |
0 |
| 18133 |
SDValue Ops[] = {Val, Idx, Chain}; |
0 |
18133 |
SDValue Ops[] = {Val, Idx, Chain}; |
0 |
| 18134 |
return CombineTo(LD, Ops, 3); |
0 |
18134 |
return CombineTo(LD, Ops, 3); |
0 |
| 18135 |
} |
--- |
18135 |
} |
--- |
| 18136 |
return CombineTo(LD, Val, Chain); |
0 |
18136 |
return CombineTo(LD, Val, Chain); |
0 |
| 18137 |
}; |
0 |
18137 |
}; |
0 |
| 18138 |
|
--- |
18138 |
|
--- |
| 18139 |
if (!STCoversLD) |
0 |
18139 |
if (!STCoversLD) |
0 |
| 18140 |
return SDValue(); |
0 |
18140 |
return SDValue(); |
0 |
| 18141 |
|
--- |
18141 |
|
--- |
| 18142 |
// Memory as copy space (potentially masked). |
--- |
18142 |
// Memory as copy space (potentially masked). |
--- |
| 18143 |
if (Offset == 0 && LDType == STType && STMemType == LDMemType) { |
0 |
18143 |
if (Offset == 0 && LDType == STType && STMemType == LDMemType) { |
0 |
| 18144 |
// Simple case: Direct non-truncating forwarding |
--- |
18144 |
// Simple case: Direct non-truncating forwarding |
--- |
| 18145 |
if (LDType.getSizeInBits() == LdMemSize) |
0 |
18145 |
if (LDType.getSizeInBits() == LdMemSize) |
0 |
| 18146 |
return ReplaceLd(LD, ST->getValue(), Chain); |
0 |
18146 |
return ReplaceLd(LD, ST->getValue(), Chain); |
0 |
| 18147 |
// Can we model the truncate and extension with an and mask? |
--- |
18147 |
// Can we model the truncate and extension with an and mask? |
--- |
| 18148 |
if (STType.isInteger() && LDMemType.isInteger() && !STType.isVector() && |
0 |
18148 |
if (STType.isInteger() && LDMemType.isInteger() && !STType.isVector() && |
0 |
| 18149 |
!LDMemType.isVector() && LD->getExtensionType() != ISD::SEXTLOAD) { |
0 |
18149 |
!LDMemType.isVector() && LD->getExtensionType() != ISD::SEXTLOAD) { |
0 |
| 18150 |
// Mask to size of LDMemType |
--- |
18150 |
// Mask to size of LDMemType |
--- |
| 18151 |
auto Mask = |
--- |
18151 |
auto Mask = |
--- |
| 18152 |
DAG.getConstant(APInt::getLowBitsSet(STType.getFixedSizeInBits(), |
0 |
18152 |
DAG.getConstant(APInt::getLowBitsSet(STType.getFixedSizeInBits(), |
0 |
| 18153 |
StMemSize.getFixedValue()), |
0 |
18153 |
StMemSize.getFixedValue()), |
0 |
| 18154 |
SDLoc(ST), STType); |
0 |
18154 |
SDLoc(ST), STType); |
0 |
| 18155 |
auto Val = DAG.getNode(ISD::AND, SDLoc(LD), LDType, ST->getValue(), Mask); |
0 |
18155 |
auto Val = DAG.getNode(ISD::AND, SDLoc(LD), LDType, ST->getValue(), Mask); |
0 |
| 18156 |
return ReplaceLd(LD, Val, Chain); |
0 |
18156 |
return ReplaceLd(LD, Val, Chain); |
0 |
| 18157 |
} |
--- |
18157 |
} |
--- |
| 18158 |
} |
--- |
18158 |
} |
--- |
| 18159 |
|
--- |
18159 |
|
--- |
| 18160 |
// Handle some cases for big-endian that would be Offset 0 and handled for |
--- |
18160 |
// Handle some cases for big-endian that would be Offset 0 and handled for |
--- |
| 18161 |
// little-endian. |
--- |
18161 |
// little-endian. |
--- |
| 18162 |
SDValue Val = ST->getValue(); |
0 |
18162 |
SDValue Val = ST->getValue(); |
0 |
| 18163 |
if (DAG.getDataLayout().isBigEndian() && Offset > 0 && OrigOffset == 0) { |
0 |
18163 |
if (DAG.getDataLayout().isBigEndian() && Offset > 0 && OrigOffset == 0) { |
0 |
| 18164 |
if (STType.isInteger() && !STType.isVector() && LDType.isInteger() && |
0 |
18164 |
if (STType.isInteger() && !STType.isVector() && LDType.isInteger() && |
0 |
| 18165 |
!LDType.isVector() && isTypeLegal(STType) && |
0 |
18165 |
!LDType.isVector() && isTypeLegal(STType) && |
0 |
| 18166 |
TLI.isOperationLegal(ISD::SRL, STType)) { |
0 |
18166 |
TLI.isOperationLegal(ISD::SRL, STType)) { |
0 |
| 18167 |
Val = DAG.getNode(ISD::SRL, SDLoc(LD), STType, Val, |
0 |
18167 |
Val = DAG.getNode(ISD::SRL, SDLoc(LD), STType, Val, |
0 |
| 18168 |
DAG.getConstant(Offset * 8, SDLoc(LD), STType)); |
0 |
18168 |
DAG.getConstant(Offset * 8, SDLoc(LD), STType)); |
0 |
| 18169 |
Offset = 0; |
0 |
18169 |
Offset = 0; |
0 |
| 18170 |
} |
--- |
18170 |
} |
--- |
| 18171 |
} |
--- |
18171 |
} |
--- |
| 18172 |
|
--- |
18172 |
|
--- |
| 18173 |
// TODO: Deal with nonzero offset. |
--- |
18173 |
// TODO: Deal with nonzero offset. |
--- |
| 18174 |
if (LD->getBasePtr().isUndef() || Offset != 0) |
0 |
18174 |
if (LD->getBasePtr().isUndef() || Offset != 0) |
0 |
| 18175 |
return SDValue(); |
0 |
18175 |
return SDValue(); |
0 |
| 18176 |
// Model necessary truncations / extenstions. |
--- |
18176 |
// Model necessary truncations / extenstions. |
--- |
| 18177 |
// Truncate Value To Stored Memory Size. |
--- |
18177 |
// Truncate Value To Stored Memory Size. |
--- |
| 18178 |
do { |
--- |
18178 |
do { |
--- |
| 18179 |
if (!getTruncatedStoreValue(ST, Val)) |
0 |
18179 |
if (!getTruncatedStoreValue(ST, Val)) |
0 |
| 18180 |
continue; |
0 |
18180 |
continue; |
0 |
| 18181 |
if (!isTypeLegal(LDMemType)) |
0 |
18181 |
if (!isTypeLegal(LDMemType)) |
0 |
| 18182 |
continue; |
0 |
18182 |
continue; |
0 |
| 18183 |
if (STMemType != LDMemType) { |
0 |
18183 |
if (STMemType != LDMemType) { |
0 |
| 18184 |
// TODO: Support vectors? This requires extract_subvector/bitcast. |
--- |
18184 |
// TODO: Support vectors? This requires extract_subvector/bitcast. |
--- |
| 18185 |
if (!STMemType.isVector() && !LDMemType.isVector() && |
0 |
18185 |
if (!STMemType.isVector() && !LDMemType.isVector() && |
0 |
| 18186 |
STMemType.isInteger() && LDMemType.isInteger()) |
0 |
18186 |
STMemType.isInteger() && LDMemType.isInteger()) |
0 |
| 18187 |
Val = DAG.getNode(ISD::TRUNCATE, SDLoc(LD), LDMemType, Val); |
0 |
18187 |
Val = DAG.getNode(ISD::TRUNCATE, SDLoc(LD), LDMemType, Val); |
0 |
| 18188 |
else |
--- |
18188 |
else |
--- |
| 18189 |
continue; |
0 |
18189 |
continue; |
0 |
| 18190 |
} |
--- |
18190 |
} |
--- |
| 18191 |
if (!extendLoadedValueToExtension(LD, Val)) |
0 |
18191 |
if (!extendLoadedValueToExtension(LD, Val)) |
0 |
| 18192 |
continue; |
0 |
18192 |
continue; |
0 |
| 18193 |
return ReplaceLd(LD, Val, Chain); |
0 |
18193 |
return ReplaceLd(LD, Val, Chain); |
0 |
| 18194 |
} while (false); |
--- |
18194 |
} while (false); |
--- |
| 18195 |
|
--- |
18195 |
|
--- |
| 18196 |
// On failure, cleanup dead nodes we may have created. |
--- |
18196 |
// On failure, cleanup dead nodes we may have created. |
--- |
| 18197 |
if (Val->use_empty()) |
0 |
18197 |
if (Val->use_empty()) |
0 |
| 18198 |
deleteAndRecombine(Val.getNode()); |
0 |
18198 |
deleteAndRecombine(Val.getNode()); |
0 |
| 18199 |
return SDValue(); |
0 |
18199 |
return SDValue(); |
0 |
| 18200 |
} |
--- |
18200 |
} |
--- |
| 18201 |
|
--- |
18201 |
|
--- |
| 18202 |
SDValue DAGCombiner::visitLOAD(SDNode *N) { |
12 |
18202 |
SDValue DAGCombiner::visitLOAD(SDNode *N) { |
12 |
| 18203 |
LoadSDNode *LD = cast(N); |
12 |
18203 |
LoadSDNode *LD = cast(N); |
12 |
| 18204 |
SDValue Chain = LD->getChain(); |
12 |
18204 |
SDValue Chain = LD->getChain(); |
12 |
| 18205 |
SDValue Ptr = LD->getBasePtr(); |
12 |
18205 |
SDValue Ptr = LD->getBasePtr(); |
12 |
| 18206 |
|
--- |
18206 |
|
--- |
| 18207 |
// If load is not volatile and there are no uses of the loaded value (and |
--- |
18207 |
// If load is not volatile and there are no uses of the loaded value (and |
--- |
| 18208 |
// the updated indexed value in case of indexed loads), change uses of the |
--- |
18208 |
// the updated indexed value in case of indexed loads), change uses of the |
--- |
| 18209 |
// chain value into uses of the chain input (i.e. delete the dead load). |
--- |
18209 |
// chain value into uses of the chain input (i.e. delete the dead load). |
--- |
| 18210 |
// TODO: Allow this for unordered atomics (see D66309) |
--- |
18210 |
// TODO: Allow this for unordered atomics (see D66309) |
--- |
| 18211 |
if (LD->isSimple()) { |
12 |
18211 |
if (LD->isSimple()) { |
12 |
| 18212 |
if (N->getValueType(1) == MVT::Other) { |
12 |
18212 |
if (N->getValueType(1) == MVT::Other) { |
12 |
| 18213 |
// Unindexed loads. |
--- |
18213 |
// Unindexed loads. |
--- |
| 18214 |
if (!N->hasAnyUseOfValue(0)) { |
12 |
18214 |
if (!N->hasAnyUseOfValue(0)) { |
12 |
| 18215 |
// It's not safe to use the two value CombineTo variant here. e.g. |
--- |
18215 |
// It's not safe to use the two value CombineTo variant here. e.g. |
--- |
| 18216 |
// v1, chain2 = load chain1, loc |
--- |
18216 |
// v1, chain2 = load chain1, loc |
--- |
| 18217 |
// v2, chain3 = load chain2, loc |
--- |
18217 |
// v2, chain3 = load chain2, loc |
--- |
| 18218 |
// v3 = add v2, c |
--- |
18218 |
// v3 = add v2, c |
--- |
| 18219 |
// Now we replace use of chain2 with chain1. This makes the second load |
--- |
18219 |
// Now we replace use of chain2 with chain1. This makes the second load |
--- |
| 18220 |
// isomorphic to the one we are deleting, and thus makes this load live. |
--- |
18220 |
// isomorphic to the one we are deleting, and thus makes this load live. |
--- |
| 18221 |
LLVM_DEBUG(dbgs() << "\nReplacing.6 "; N->dump(&DAG); |
0 |
18221 |
LLVM_DEBUG(dbgs() << "\nReplacing.6 "; N->dump(&DAG); |
0 |
| 18222 |
dbgs() << "\nWith chain: "; Chain.dump(&DAG); |
--- |
18222 |
dbgs() << "\nWith chain: "; Chain.dump(&DAG); |
--- |
| 18223 |
dbgs() << "\n"); |
--- |
18223 |
dbgs() << "\n"); |
--- |
| 18224 |
WorklistRemover DeadNodes(*this); |
0 |
18224 |
WorklistRemover DeadNodes(*this); |
0 |
| 18225 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); |
0 |
18225 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); |
0 |
| 18226 |
AddUsersToWorklist(Chain.getNode()); |
0 |
18226 |
AddUsersToWorklist(Chain.getNode()); |
0 |
| 18227 |
if (N->use_empty()) |
0 |
18227 |
if (N->use_empty()) |
0 |
| 18228 |
deleteAndRecombine(N); |
0 |
18228 |
deleteAndRecombine(N); |
0 |
| 18229 |
|
--- |
18229 |
|
--- |
| 18230 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
18230 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 18231 |
} |
0 |
18231 |
} |
0 |
| 18232 |
} else { |
--- |
18232 |
} else { |
--- |
| 18233 |
// Indexed loads. |
--- |
18233 |
// Indexed loads. |
--- |
| 18234 |
assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); |
0 |
18234 |
assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); |
0 |
| 18235 |
|
--- |
18235 |
|
--- |
| 18236 |
// If this load has an opaque TargetConstant offset, then we cannot split |
--- |
18236 |
// If this load has an opaque TargetConstant offset, then we cannot split |
--- |
| 18237 |
// the indexing into an add/sub directly (that TargetConstant may not be |
--- |
18237 |
// the indexing into an add/sub directly (that TargetConstant may not be |
--- |
| 18238 |
// valid for a different type of node, and we cannot convert an opaque |
--- |
18238 |
// valid for a different type of node, and we cannot convert an opaque |
--- |
| 18239 |
// target constant into a regular constant). |
--- |
18239 |
// target constant into a regular constant). |
--- |
| 18240 |
bool CanSplitIdx = canSplitIdx(LD); |
0 |
18240 |
bool CanSplitIdx = canSplitIdx(LD); |
0 |
| 18241 |
|
--- |
18241 |
|
--- |
| 18242 |
if (!N->hasAnyUseOfValue(0) && (CanSplitIdx || !N->hasAnyUseOfValue(1))) { |
0 |
18242 |
if (!N->hasAnyUseOfValue(0) && (CanSplitIdx || !N->hasAnyUseOfValue(1))) { |
0 |
| 18243 |
SDValue Undef = DAG.getUNDEF(N->getValueType(0)); |
0 |
18243 |
SDValue Undef = DAG.getUNDEF(N->getValueType(0)); |
0 |
| 18244 |
SDValue Index; |
0 |
18244 |
SDValue Index; |
0 |
| 18245 |
if (N->hasAnyUseOfValue(1) && CanSplitIdx) { |
0 |
18245 |
if (N->hasAnyUseOfValue(1) && CanSplitIdx) { |
0 |
| 18246 |
Index = SplitIndexingFromLoad(LD); |
0 |
18246 |
Index = SplitIndexingFromLoad(LD); |
0 |
| 18247 |
// Try to fold the base pointer arithmetic into subsequent loads and |
--- |
18247 |
// Try to fold the base pointer arithmetic into subsequent loads and |
--- |
| 18248 |
// stores. |
--- |
18248 |
// stores. |
--- |
| 18249 |
AddUsersToWorklist(N); |
0 |
18249 |
AddUsersToWorklist(N); |
0 |
| 18250 |
} else |
--- |
18250 |
} else |
--- |
| 18251 |
Index = DAG.getUNDEF(N->getValueType(1)); |
0 |
18251 |
Index = DAG.getUNDEF(N->getValueType(1)); |
0 |
| 18252 |
LLVM_DEBUG(dbgs() << "\nReplacing.7 "; N->dump(&DAG); |
0 |
18252 |
LLVM_DEBUG(dbgs() << "\nReplacing.7 "; N->dump(&DAG); |
0 |
| 18253 |
dbgs() << "\nWith: "; Undef.dump(&DAG); |
--- |
18253 |
dbgs() << "\nWith: "; Undef.dump(&DAG); |
--- |
| 18254 |
dbgs() << " and 2 other values\n"); |
--- |
18254 |
dbgs() << " and 2 other values\n"); |
--- |
| 18255 |
WorklistRemover DeadNodes(*this); |
0 |
18255 |
WorklistRemover DeadNodes(*this); |
0 |
| 18256 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); |
0 |
18256 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); |
0 |
| 18257 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Index); |
0 |
18257 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Index); |
0 |
| 18258 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); |
0 |
18258 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); |
0 |
| 18259 |
deleteAndRecombine(N); |
0 |
18259 |
deleteAndRecombine(N); |
0 |
| 18260 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
18260 |
return SDValue(N, 0); // Return N so it doesn't get rechecked! |
0 |
| 18261 |
} |
0 |
18261 |
} |
0 |
| 18262 |
} |
--- |
18262 |
} |
--- |
| 18263 |
} |
--- |
18263 |
} |
--- |
| 18264 |
|
--- |
18264 |
|
--- |
| 18265 |
// If this load is directly stored, replace the load value with the stored |
--- |
18265 |
// If this load is directly stored, replace the load value with the stored |
--- |
| 18266 |
// value. |
--- |
18266 |
// value. |
--- |
| 18267 |
if (auto V = ForwardStoreValueToDirectLoad(LD)) |
12 |
18267 |
if (auto V = ForwardStoreValueToDirectLoad(LD)) |
12 |
| 18268 |
return V; |
0 |
18268 |
return V; |
0 |
| 18269 |
|
--- |
18269 |
|
--- |
| 18270 |
// Try to infer better alignment information than the load already has. |
--- |
18270 |
// Try to infer better alignment information than the load already has. |
--- |
| 18271 |
if (OptLevel != CodeGenOpt::None && LD->isUnindexed() && !LD->isAtomic()) { |
12 |
18271 |
if (OptLevel != CodeGenOpt::None && LD->isUnindexed() && !LD->isAtomic()) { |
12 |
| 18272 |
if (MaybeAlign Alignment = DAG.InferPtrAlign(Ptr)) { |
0 |
18272 |
if (MaybeAlign Alignment = DAG.InferPtrAlign(Ptr)) { |
0 |
| 18273 |
if (*Alignment > LD->getAlign() && |
0 |
18273 |
if (*Alignment > LD->getAlign() && |
0 |
| 18274 |
isAligned(*Alignment, LD->getSrcValueOffset())) { |
0 |
18274 |
isAligned(*Alignment, LD->getSrcValueOffset())) { |
0 |
| 18275 |
SDValue NewLoad = DAG.getExtLoad( |
0 |
18275 |
SDValue NewLoad = DAG.getExtLoad( |
0 |
| 18276 |
LD->getExtensionType(), SDLoc(N), LD->getValueType(0), Chain, Ptr, |
0 |
18276 |
LD->getExtensionType(), SDLoc(N), LD->getValueType(0), Chain, Ptr, |
0 |
| 18277 |
LD->getPointerInfo(), LD->getMemoryVT(), *Alignment, |
0 |
18277 |
LD->getPointerInfo(), LD->getMemoryVT(), *Alignment, |
0 |
| 18278 |
LD->getMemOperand()->getFlags(), LD->getAAInfo()); |
0 |
18278 |
LD->getMemOperand()->getFlags(), LD->getAAInfo()); |
0 |
| 18279 |
// NewLoad will always be N as we are only refining the alignment |
--- |
18279 |
// NewLoad will always be N as we are only refining the alignment |
--- |
| 18280 |
assert(NewLoad.getNode() == N); |
0 |
18280 |
assert(NewLoad.getNode() == N); |
0 |
| 18281 |
(void)NewLoad; |
--- |
18281 |
(void)NewLoad; |
--- |
| 18282 |
} |
--- |
18282 |
} |
--- |
| 18283 |
} |
--- |
18283 |
} |
--- |
| 18284 |
} |
--- |
18284 |
} |
--- |
| 18285 |
|
--- |
18285 |
|
--- |
| 18286 |
if (LD->isUnindexed()) { |
12 |
18286 |
if (LD->isUnindexed()) { |
12 |
| 18287 |
// Walk up chain skipping non-aliasing memory nodes. |
--- |
18287 |
// Walk up chain skipping non-aliasing memory nodes. |
--- |
| 18288 |
SDValue BetterChain = FindBetterChain(LD, Chain); |
12 |
18288 |
SDValue BetterChain = FindBetterChain(LD, Chain); |
12 |
| 18289 |
|
--- |
18289 |
|
--- |
| 18290 |
// If there is a better chain. |
--- |
18290 |
// If there is a better chain. |
--- |
| 18291 |
if (Chain != BetterChain) { |
12 |
18291 |
if (Chain != BetterChain) { |
12 |
| 18292 |
SDValue ReplLoad; |
0 |
18292 |
SDValue ReplLoad; |
0 |
| 18293 |
|
--- |
18293 |
|
--- |
| 18294 |
// Replace the chain to void dependency. |
--- |
18294 |
// Replace the chain to void dependency. |
--- |
| 18295 |
if (LD->getExtensionType() == ISD::NON_EXTLOAD) { |
0 |
18295 |
if (LD->getExtensionType() == ISD::NON_EXTLOAD) { |
0 |
| 18296 |
ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD), |
0 |
18296 |
ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD), |
0 |
| 18297 |
BetterChain, Ptr, LD->getMemOperand()); |
--- |
18297 |
BetterChain, Ptr, LD->getMemOperand()); |
--- |
| 18298 |
} else { |
--- |
18298 |
} else { |
--- |
| 18299 |
ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), |
0 |
18299 |
ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), |
0 |
| 18300 |
LD->getValueType(0), |
--- |
18300 |
LD->getValueType(0), |
--- |
| 18301 |
BetterChain, Ptr, LD->getMemoryVT(), |
--- |
18301 |
BetterChain, Ptr, LD->getMemoryVT(), |
--- |
| 18302 |
LD->getMemOperand()); |
--- |
18302 |
LD->getMemOperand()); |
--- |
| 18303 |
} |
--- |
18303 |
} |
--- |
| 18304 |
|
--- |
18304 |
|
--- |
| 18305 |
// Create token factor to keep old chain connected. |
--- |
18305 |
// Create token factor to keep old chain connected. |
--- |
| 18306 |
SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N), |
0 |
18306 |
SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N), |
0 |
| 18307 |
MVT::Other, Chain, ReplLoad.getValue(1)); |
--- |
18307 |
MVT::Other, Chain, ReplLoad.getValue(1)); |
--- |
| 18308 |
|
--- |
18308 |
|
--- |
| 18309 |
// Replace uses with load result and token factor |
--- |
18309 |
// Replace uses with load result and token factor |
--- |
| 18310 |
return CombineTo(N, ReplLoad.getValue(0), Token); |
0 |
18310 |
return CombineTo(N, ReplLoad.getValue(0), Token); |
0 |
| 18311 |
} |
--- |
18311 |
} |
--- |
| 18312 |
} |
--- |
18312 |
} |
--- |
| 18313 |
|
--- |
18313 |
|
--- |
| 18314 |
// Try transforming N to an indexed load. |
--- |
18314 |
// Try transforming N to an indexed load. |
--- |
| 18315 |
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) |
12 |
18315 |
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) |
12 |
| 18316 |
return SDValue(N, 0); |
0 |
18316 |
return SDValue(N, 0); |
0 |
| 18317 |
|
--- |
18317 |
|
--- |
| 18318 |
// Try to slice up N to more direct loads if the slices are mapped to |
--- |
18318 |
// Try to slice up N to more direct loads if the slices are mapped to |
--- |
| 18319 |
// different register banks or pairing can take place. |
--- |
18319 |
// different register banks or pairing can take place. |
--- |
| 18320 |
if (SliceUpLoad(N)) |
12 |
18320 |
if (SliceUpLoad(N)) |
12 |
| 18321 |
return SDValue(N, 0); |
0 |
18321 |
return SDValue(N, 0); |
0 |
| 18322 |
|
--- |
18322 |
|
--- |
| 18323 |
return SDValue(); |
12 |
18323 |
return SDValue(); |
12 |
| 18324 |
} |
--- |
18324 |
} |
--- |
| 18325 |
|
--- |
18325 |
|
--- |
| 18326 |
namespace { |
--- |
18326 |
namespace { |
--- |
| 18327 |
|
--- |
18327 |
|
--- |
| 18328 |
/// Helper structure used to slice a load in smaller loads. |
--- |
18328 |
/// Helper structure used to slice a load in smaller loads. |
--- |
| 18329 |
/// Basically a slice is obtained from the following sequence: |
--- |
18329 |
/// Basically a slice is obtained from the following sequence: |
--- |
| 18330 |
/// Origin = load Ty1, Base |
--- |
18330 |
/// Origin = load Ty1, Base |
--- |
| 18331 |
/// Shift = srl Ty1 Origin, CstTy Amount |
--- |
18331 |
/// Shift = srl Ty1 Origin, CstTy Amount |
--- |
| 18332 |
/// Inst = trunc Shift to Ty2 |
--- |
18332 |
/// Inst = trunc Shift to Ty2 |
--- |
| 18333 |
/// |
--- |
18333 |
/// |
--- |
| 18334 |
/// Then, it will be rewritten into: |
--- |
18334 |
/// Then, it will be rewritten into: |
--- |
| 18335 |
/// Slice = load SliceTy, Base + SliceOffset |
--- |
18335 |
/// Slice = load SliceTy, Base + SliceOffset |
--- |
| 18336 |
/// [Inst = zext Slice to Ty2], only if SliceTy <> Ty2 |
--- |
18336 |
/// [Inst = zext Slice to Ty2], only if SliceTy <> Ty2 |
--- |
| 18337 |
/// |
--- |
18337 |
/// |
--- |
| 18338 |
/// SliceTy is deduced from the number of bits that are actually used to |
--- |
18338 |
/// SliceTy is deduced from the number of bits that are actually used to |
--- |
| 18339 |
/// build Inst. |
--- |
18339 |
/// build Inst. |
--- |
| 18340 |
struct LoadedSlice { |
--- |
18340 |
struct LoadedSlice { |
--- |
| 18341 |
/// Helper structure used to compute the cost of a slice. |
--- |
18341 |
/// Helper structure used to compute the cost of a slice. |
--- |
| 18342 |
struct Cost { |
--- |
18342 |
struct Cost { |
--- |
| 18343 |
/// Are we optimizing for code size. |
--- |
18343 |
/// Are we optimizing for code size. |
--- |
| 18344 |
bool ForCodeSize = false; |
--- |
18344 |
bool ForCodeSize = false; |
--- |
| 18345 |
|
--- |
18345 |
|
--- |
| 18346 |
/// Various cost. |
--- |
18346 |
/// Various cost. |
--- |
| 18347 |
unsigned Loads = 0; |
--- |
18347 |
unsigned Loads = 0; |
--- |
| 18348 |
unsigned Truncates = 0; |
--- |
18348 |
unsigned Truncates = 0; |
--- |
| 18349 |
unsigned CrossRegisterBanksCopies = 0; |
--- |
18349 |
unsigned CrossRegisterBanksCopies = 0; |
--- |
| 18350 |
unsigned ZExts = 0; |
--- |
18350 |
unsigned ZExts = 0; |
--- |
| 18351 |
unsigned Shift = 0; |
--- |
18351 |
unsigned Shift = 0; |
--- |
| 18352 |
|
--- |
18352 |
|
--- |
| 18353 |
explicit Cost(bool ForCodeSize) : ForCodeSize(ForCodeSize) {} |
0 |
18353 |
explicit Cost(bool ForCodeSize) : ForCodeSize(ForCodeSize) {} |
0 |
| 18354 |
|
--- |
18354 |
|
--- |
| 18355 |
/// Get the cost of one isolated slice. |
--- |
18355 |
/// Get the cost of one isolated slice. |
--- |
| 18356 |
Cost(const LoadedSlice &LS, bool ForCodeSize) |
0 |
18356 |
Cost(const LoadedSlice &LS, bool ForCodeSize) |
0 |
| 18357 |
: ForCodeSize(ForCodeSize), Loads(1) { |
0 |
18357 |
: ForCodeSize(ForCodeSize), Loads(1) { |
0 |
| 18358 |
EVT TruncType = LS.Inst->getValueType(0); |
0 |
18358 |
EVT TruncType = LS.Inst->getValueType(0); |
0 |
| 18359 |
EVT LoadedType = LS.getLoadedType(); |
0 |
18359 |
EVT LoadedType = LS.getLoadedType(); |
0 |
| 18360 |
if (TruncType != LoadedType && |
0 |
18360 |
if (TruncType != LoadedType && |
0 |
| 18361 |
!LS.DAG->getTargetLoweringInfo().isZExtFree(LoadedType, TruncType)) |
0 |
18361 |
!LS.DAG->getTargetLoweringInfo().isZExtFree(LoadedType, TruncType)) |
0 |
| 18362 |
ZExts = 1; |
0 |
18362 |
ZExts = 1; |
0 |
| 18363 |
} |
0 |
18363 |
} |
0 |
| 18364 |
|
--- |
18364 |
|
--- |
| 18365 |
/// Account for slicing gain in the current cost. |
--- |
18365 |
/// Account for slicing gain in the current cost. |
--- |
| 18366 |
/// Slicing provide a few gains like removing a shift or a |
--- |
18366 |
/// Slicing provide a few gains like removing a shift or a |
--- |
| 18367 |
/// truncate. This method allows to grow the cost of the original |
--- |
18367 |
/// truncate. This method allows to grow the cost of the original |
--- |
| 18368 |
/// load with the gain from this slice. |
--- |
18368 |
/// load with the gain from this slice. |
--- |
| 18369 |
void addSliceGain(const LoadedSlice &LS) { |
0 |
18369 |
void addSliceGain(const LoadedSlice &LS) { |
0 |
| 18370 |
// Each slice saves a truncate. |
--- |
18370 |
// Each slice saves a truncate. |
--- |
| 18371 |
const TargetLowering &TLI = LS.DAG->getTargetLoweringInfo(); |
0 |
18371 |
const TargetLowering &TLI = LS.DAG->getTargetLoweringInfo(); |
0 |
| 18372 |
if (!TLI.isTruncateFree(LS.Inst->getOperand(0).getValueType(), |
0 |
18372 |
if (!TLI.isTruncateFree(LS.Inst->getOperand(0).getValueType(), |
0 |
| 18373 |
LS.Inst->getValueType(0))) |
0 |
18373 |
LS.Inst->getValueType(0))) |
0 |
| 18374 |
++Truncates; |
0 |
18374 |
++Truncates; |
0 |
| 18375 |
// If there is a shift amount, this slice gets rid of it. |
--- |
18375 |
// If there is a shift amount, this slice gets rid of it. |
--- |
| 18376 |
if (LS.Shift) |
0 |
18376 |
if (LS.Shift) |
0 |
| 18377 |
++Shift; |
0 |
18377 |
++Shift; |
0 |
| 18378 |
// If this slice can merge a cross register bank copy, account for it. |
--- |
18378 |
// If this slice can merge a cross register bank copy, account for it. |
--- |
| 18379 |
if (LS.canMergeExpensiveCrossRegisterBankCopy()) |
0 |
18379 |
if (LS.canMergeExpensiveCrossRegisterBankCopy()) |
0 |
| 18380 |
++CrossRegisterBanksCopies; |
0 |
18380 |
++CrossRegisterBanksCopies; |
0 |
| 18381 |
} |
0 |
18381 |
} |
0 |
| 18382 |
|
--- |
18382 |
|
--- |
| 18383 |
Cost &operator+=(const Cost &RHS) { |
0 |
18383 |
Cost &operator+=(const Cost &RHS) { |
0 |
| 18384 |
Loads += RHS.Loads; |
0 |
18384 |
Loads += RHS.Loads; |
0 |
| 18385 |
Truncates += RHS.Truncates; |
0 |
18385 |
Truncates += RHS.Truncates; |
0 |
| 18386 |
CrossRegisterBanksCopies += RHS.CrossRegisterBanksCopies; |
0 |
18386 |
CrossRegisterBanksCopies += RHS.CrossRegisterBanksCopies; |
0 |
| 18387 |
ZExts += RHS.ZExts; |
0 |
18387 |
ZExts += RHS.ZExts; |
0 |
| 18388 |
Shift += RHS.Shift; |
0 |
18388 |
Shift += RHS.Shift; |
0 |
| 18389 |
return *this; |
0 |
18389 |
return *this; |
0 |
| 18390 |
} |
--- |
18390 |
} |
--- |
| 18391 |
|
--- |
18391 |
|
--- |
| 18392 |
bool operator==(const Cost &RHS) const { |
--- |
18392 |
bool operator==(const Cost &RHS) const { |
--- |
| 18393 |
return Loads == RHS.Loads && Truncates == RHS.Truncates && |
--- |
18393 |
return Loads == RHS.Loads && Truncates == RHS.Truncates && |
--- |
| 18394 |
CrossRegisterBanksCopies == RHS.CrossRegisterBanksCopies && |
--- |
18394 |
CrossRegisterBanksCopies == RHS.CrossRegisterBanksCopies && |
--- |
| 18395 |
ZExts == RHS.ZExts && Shift == RHS.Shift; |
--- |
18395 |
ZExts == RHS.ZExts && Shift == RHS.Shift; |
--- |
| 18396 |
} |
--- |
18396 |
} |
--- |
| 18397 |
|
--- |
18397 |
|
--- |
| 18398 |
bool operator!=(const Cost &RHS) const { return !(*this == RHS); } |
--- |
18398 |
bool operator!=(const Cost &RHS) const { return !(*this == RHS); } |
--- |
| 18399 |
|
--- |
18399 |
|
--- |
| 18400 |
bool operator<(const Cost &RHS) const { |
0 |
18400 |
bool operator<(const Cost &RHS) const { |
0 |
| 18401 |
// Assume cross register banks copies are as expensive as loads. |
--- |
18401 |
// Assume cross register banks copies are as expensive as loads. |
--- |
| 18402 |
// FIXME: Do we want some more target hooks? |
--- |
18402 |
// FIXME: Do we want some more target hooks? |
--- |
| 18403 |
unsigned ExpensiveOpsLHS = Loads + CrossRegisterBanksCopies; |
0 |
18403 |
unsigned ExpensiveOpsLHS = Loads + CrossRegisterBanksCopies; |
0 |
| 18404 |
unsigned ExpensiveOpsRHS = RHS.Loads + RHS.CrossRegisterBanksCopies; |
0 |
18404 |
unsigned ExpensiveOpsRHS = RHS.Loads + RHS.CrossRegisterBanksCopies; |
0 |
| 18405 |
// Unless we are optimizing for code size, consider the |
--- |
18405 |
// Unless we are optimizing for code size, consider the |
--- |
| 18406 |
// expensive operation first. |
--- |
18406 |
// expensive operation first. |
--- |
| 18407 |
if (!ForCodeSize && ExpensiveOpsLHS != ExpensiveOpsRHS) |
0 |
18407 |
if (!ForCodeSize && ExpensiveOpsLHS != ExpensiveOpsRHS) |
0 |
| 18408 |
return ExpensiveOpsLHS < ExpensiveOpsRHS; |
0 |
18408 |
return ExpensiveOpsLHS < ExpensiveOpsRHS; |
0 |
| 18409 |
return (Truncates + ZExts + Shift + ExpensiveOpsLHS) < |
0 |
18409 |
return (Truncates + ZExts + Shift + ExpensiveOpsLHS) < |
0 |
| 18410 |
(RHS.Truncates + RHS.ZExts + RHS.Shift + ExpensiveOpsRHS); |
0 |
18410 |
(RHS.Truncates + RHS.ZExts + RHS.Shift + ExpensiveOpsRHS); |
0 |
| 18411 |
} |
--- |
18411 |
} |
--- |
| 18412 |
|
--- |
18412 |
|
--- |
| 18413 |
bool operator>(const Cost &RHS) const { return RHS < *this; } |
0 |
18413 |
bool operator>(const Cost &RHS) const { return RHS < *this; } |
0 |
| 18414 |
|
--- |
18414 |
|
--- |
| 18415 |
bool operator<=(const Cost &RHS) const { return !(RHS < *this); } |
--- |
18415 |
bool operator<=(const Cost &RHS) const { return !(RHS < *this); } |
--- |
| 18416 |
|
--- |
18416 |
|
--- |
| 18417 |
bool operator>=(const Cost &RHS) const { return !(*this < RHS); } |
--- |
18417 |
bool operator>=(const Cost &RHS) const { return !(*this < RHS); } |
--- |
| 18418 |
}; |
--- |
18418 |
}; |
--- |
| 18419 |
|
--- |
18419 |
|
--- |
| 18420 |
// The last instruction that represent the slice. This should be a |
--- |
18420 |
// The last instruction that represent the slice. This should be a |
--- |
| 18421 |
// truncate instruction. |
--- |
18421 |
// truncate instruction. |
--- |
| 18422 |
SDNode *Inst; |
--- |
18422 |
SDNode *Inst; |
--- |
| 18423 |
|
--- |
18423 |
|
--- |
| 18424 |
// The original load instruction. |
--- |
18424 |
// The original load instruction. |
--- |
| 18425 |
LoadSDNode *Origin; |
--- |
18425 |
LoadSDNode *Origin; |
--- |
| 18426 |
|
--- |
18426 |
|
--- |
| 18427 |
// The right shift amount in bits from the original load. |
--- |
18427 |
// The right shift amount in bits from the original load. |
--- |
| 18428 |
unsigned Shift; |
--- |
18428 |
unsigned Shift; |
--- |
| 18429 |
|
--- |
18429 |
|
--- |
| 18430 |
// The DAG from which Origin came from. |
--- |
18430 |
// The DAG from which Origin came from. |
--- |
| 18431 |
// This is used to get some contextual information about legal types, etc. |
--- |
18431 |
// This is used to get some contextual information about legal types, etc. |
--- |
| 18432 |
SelectionDAG *DAG; |
--- |
18432 |
SelectionDAG *DAG; |
--- |
| 18433 |
|
--- |
18433 |
|
--- |
| 18434 |
LoadedSlice(SDNode *Inst = nullptr, LoadSDNode *Origin = nullptr, |
0 |
18434 |
LoadedSlice(SDNode *Inst = nullptr, LoadSDNode *Origin = nullptr, |
0 |
| 18435 |
unsigned Shift = 0, SelectionDAG *DAG = nullptr) |
--- |
18435 |
unsigned Shift = 0, SelectionDAG *DAG = nullptr) |
--- |
| 18436 |
: Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {} |
0 |
18436 |
: Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {} |
0 |
| 18437 |
|
--- |
18437 |
|
--- |
| 18438 |
/// Get the bits used in a chunk of bits \p BitWidth large. |
--- |
18438 |
/// Get the bits used in a chunk of bits \p BitWidth large. |
--- |
| 18439 |
/// \return Result is \p BitWidth and has used bits set to 1 and |
--- |
18439 |
/// \return Result is \p BitWidth and has used bits set to 1 and |
--- |
| 18440 |
/// not used bits set to 0. |
--- |
18440 |
/// not used bits set to 0. |
--- |
| 18441 |
APInt getUsedBits() const { |
0 |
18441 |
APInt getUsedBits() const { |
0 |
| 18442 |
// Reproduce the trunc(lshr) sequence: |
--- |
18442 |
// Reproduce the trunc(lshr) sequence: |
--- |
| 18443 |
// - Start from the truncated value. |
--- |
18443 |
// - Start from the truncated value. |
--- |
| 18444 |
// - Zero extend to the desired bit width. |
--- |
18444 |
// - Zero extend to the desired bit width. |
--- |
| 18445 |
// - Shift left. |
--- |
18445 |
// - Shift left. |
--- |
| 18446 |
assert(Origin && "No original load to compare against."); |
0 |
18446 |
assert(Origin && "No original load to compare against."); |
0 |
| 18447 |
unsigned BitWidth = Origin->getValueSizeInBits(0); |
0 |
18447 |
unsigned BitWidth = Origin->getValueSizeInBits(0); |
0 |
| 18448 |
assert(Inst && "This slice is not bound to an instruction"); |
0 |
18448 |
assert(Inst && "This slice is not bound to an instruction"); |
0 |
| 18449 |
assert(Inst->getValueSizeInBits(0) <= BitWidth && |
0 |
18449 |
assert(Inst->getValueSizeInBits(0) <= BitWidth && |
0 |
| 18450 |
"Extracted slice is bigger than the whole type!"); |
--- |
18450 |
"Extracted slice is bigger than the whole type!"); |
--- |
| 18451 |
APInt UsedBits(Inst->getValueSizeInBits(0), 0); |
0 |
18451 |
APInt UsedBits(Inst->getValueSizeInBits(0), 0); |
0 |
| 18452 |
UsedBits.setAllBits(); |
0 |
18452 |
UsedBits.setAllBits(); |
0 |
| 18453 |
UsedBits = UsedBits.zext(BitWidth); |
0 |
18453 |
UsedBits = UsedBits.zext(BitWidth); |
0 |
| 18454 |
UsedBits <<= Shift; |
0 |
18454 |
UsedBits <<= Shift; |
0 |
| 18455 |
return UsedBits; |
0 |
18455 |
return UsedBits; |
0 |
| 18456 |
} |
--- |
18456 |
} |
--- |
| 18457 |
|
--- |
18457 |
|
--- |
| 18458 |
/// Get the size of the slice to be loaded in bytes. |
--- |
18458 |
/// Get the size of the slice to be loaded in bytes. |
--- |
| 18459 |
unsigned getLoadedSize() const { |
0 |
18459 |
unsigned getLoadedSize() const { |
0 |
| 18460 |
unsigned SliceSize = getUsedBits().popcount(); |
0 |
18460 |
unsigned SliceSize = getUsedBits().popcount(); |
0 |
| 18461 |
assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte."); |
0 |
18461 |
assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte."); |
0 |
| 18462 |
return SliceSize / 8; |
0 |
18462 |
return SliceSize / 8; |
0 |
| 18463 |
} |
--- |
18463 |
} |
--- |
| 18464 |
|
--- |
18464 |
|
--- |
| 18465 |
/// Get the type that will be loaded for this slice. |
--- |
18465 |
/// Get the type that will be loaded for this slice. |
--- |
| 18466 |
/// Note: This may not be the final type for the slice. |
--- |
18466 |
/// Note: This may not be the final type for the slice. |
--- |
| 18467 |
EVT getLoadedType() const { |
0 |
18467 |
EVT getLoadedType() const { |
0 |
| 18468 |
assert(DAG && "Missing context"); |
0 |
18468 |
assert(DAG && "Missing context"); |
0 |
| 18469 |
LLVMContext &Ctxt = *DAG->getContext(); |
0 |
18469 |
LLVMContext &Ctxt = *DAG->getContext(); |
0 |
| 18470 |
return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8); |
0 |
18470 |
return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8); |
0 |
| 18471 |
} |
--- |
18471 |
} |
--- |
| 18472 |
|
--- |
18472 |
|
--- |
| 18473 |
/// Get the alignment of the load used for this slice. |
--- |
18473 |
/// Get the alignment of the load used for this slice. |
--- |
| 18474 |
Align getAlign() const { |
0 |
18474 |
Align getAlign() const { |
0 |
| 18475 |
Align Alignment = Origin->getAlign(); |
0 |
18475 |
Align Alignment = Origin->getAlign(); |
0 |
| 18476 |
uint64_t Offset = getOffsetFromBase(); |
0 |
18476 |
uint64_t Offset = getOffsetFromBase(); |
0 |
| 18477 |
if (Offset != 0) |
0 |
18477 |
if (Offset != 0) |
0 |
| 18478 |
Alignment = commonAlignment(Alignment, Alignment.value() + Offset); |
0 |
18478 |
Alignment = commonAlignment(Alignment, Alignment.value() + Offset); |
0 |
| 18479 |
return Alignment; |
0 |
18479 |
return Alignment; |
0 |
| 18480 |
} |
--- |
18480 |
} |
--- |
| 18481 |
|
--- |
18481 |
|
--- |
| 18482 |
/// Check if this slice can be rewritten with legal operations. |
--- |
18482 |
/// Check if this slice can be rewritten with legal operations. |
--- |
| 18483 |
bool isLegal() const { |
0 |
18483 |
bool isLegal() const { |
0 |
| 18484 |
// An invalid slice is not legal. |
--- |
18484 |
// An invalid slice is not legal. |
--- |
| 18485 |
if (!Origin || !Inst || !DAG) |
0 |
18485 |
if (!Origin || !Inst || !DAG) |
0 |
| 18486 |
return false; |
0 |
18486 |
return false; |
0 |
| 18487 |
|
--- |
18487 |
|
--- |
| 18488 |
// Offsets are for indexed load only, we do not handle that. |
--- |
18488 |
// Offsets are for indexed load only, we do not handle that. |
--- |
| 18489 |
if (!Origin->getOffset().isUndef()) |
0 |
18489 |
if (!Origin->getOffset().isUndef()) |
0 |
| 18490 |
return false; |
0 |
18490 |
return false; |
0 |
| 18491 |
|
--- |
18491 |
|
--- |
| 18492 |
const TargetLowering &TLI = DAG->getTargetLoweringInfo(); |
0 |
18492 |
const TargetLowering &TLI = DAG->getTargetLoweringInfo(); |
0 |
| 18493 |
|
--- |
18493 |
|
--- |
| 18494 |
// Check that the type is legal. |
--- |
18494 |
// Check that the type is legal. |
--- |
| 18495 |
EVT SliceType = getLoadedType(); |
0 |
18495 |
EVT SliceType = getLoadedType(); |
0 |
| 18496 |
if (!TLI.isTypeLegal(SliceType)) |
0 |
18496 |
if (!TLI.isTypeLegal(SliceType)) |
0 |
| 18497 |
return false; |
0 |
18497 |
return false; |
0 |
| 18498 |
|
--- |
18498 |
|
--- |
| 18499 |
// Check that the load is legal for this type. |
--- |
18499 |
// Check that the load is legal for this type. |
--- |
| 18500 |
if (!TLI.isOperationLegal(ISD::LOAD, SliceType)) |
0 |
18500 |
if (!TLI.isOperationLegal(ISD::LOAD, SliceType)) |
0 |
| 18501 |
return false; |
0 |
18501 |
return false; |
0 |
| 18502 |
|
--- |
18502 |
|
--- |
| 18503 |
// Check that the offset can be computed. |
--- |
18503 |
// Check that the offset can be computed. |
--- |
| 18504 |
// 1. Check its type. |
--- |
18504 |
// 1. Check its type. |
--- |
| 18505 |
EVT PtrType = Origin->getBasePtr().getValueType(); |
0 |
18505 |
EVT PtrType = Origin->getBasePtr().getValueType(); |
0 |
| 18506 |
if (PtrType == MVT::Untyped || PtrType.isExtended()) |
0 |
18506 |
if (PtrType == MVT::Untyped || PtrType.isExtended()) |
0 |
| 18507 |
return false; |
0 |
18507 |
return false; |
0 |
| 18508 |
|
--- |
18508 |
|
--- |
| 18509 |
// 2. Check that it fits in the immediate. |
--- |
18509 |
// 2. Check that it fits in the immediate. |
--- |
| 18510 |
if (!TLI.isLegalAddImmediate(getOffsetFromBase())) |
0 |
18510 |
if (!TLI.isLegalAddImmediate(getOffsetFromBase())) |
0 |
| 18511 |
return false; |
0 |
18511 |
return false; |
0 |
| 18512 |
|
--- |
18512 |
|
--- |
| 18513 |
// 3. Check that the computation is legal. |
--- |
18513 |
// 3. Check that the computation is legal. |
--- |
| 18514 |
if (!TLI.isOperationLegal(ISD::ADD, PtrType)) |
0 |
18514 |
if (!TLI.isOperationLegal(ISD::ADD, PtrType)) |
0 |
| 18515 |
return false; |
0 |
18515 |
return false; |
0 |
| 18516 |
|
--- |
18516 |
|
--- |
| 18517 |
// Check that the zext is legal if it needs one. |
--- |
18517 |
// Check that the zext is legal if it needs one. |
--- |
| 18518 |
EVT TruncateType = Inst->getValueType(0); |
0 |
18518 |
EVT TruncateType = Inst->getValueType(0); |
0 |
| 18519 |
if (TruncateType != SliceType && |
0 |
18519 |
if (TruncateType != SliceType && |
0 |
| 18520 |
!TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType)) |
0 |
18520 |
!TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType)) |
0 |
| 18521 |
return false; |
0 |
18521 |
return false; |
0 |
| 18522 |
|
--- |
18522 |
|
--- |
| 18523 |
return true; |
0 |
18523 |
return true; |
0 |
| 18524 |
} |
--- |
18524 |
} |
--- |
| 18525 |
|
--- |
18525 |
|
--- |
| 18526 |
/// Get the offset in bytes of this slice in the original chunk of |
--- |
18526 |
/// Get the offset in bytes of this slice in the original chunk of |
--- |
| 18527 |
/// bits. |
--- |
18527 |
/// bits. |
--- |
| 18528 |
/// \pre DAG != nullptr. |
--- |
18528 |
/// \pre DAG != nullptr. |
--- |
| 18529 |
uint64_t getOffsetFromBase() const { |
0 |
18529 |
uint64_t getOffsetFromBase() const { |
0 |
| 18530 |
assert(DAG && "Missing context."); |
0 |
18530 |
assert(DAG && "Missing context."); |
0 |
| 18531 |
bool IsBigEndian = DAG->getDataLayout().isBigEndian(); |
0 |
18531 |
bool IsBigEndian = DAG->getDataLayout().isBigEndian(); |
0 |
| 18532 |
assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported."); |
0 |
18532 |
assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported."); |
0 |
| 18533 |
uint64_t Offset = Shift / 8; |
0 |
18533 |
uint64_t Offset = Shift / 8; |
0 |
| 18534 |
unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8; |
0 |
18534 |
unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8; |
0 |
| 18535 |
assert(!(Origin->getValueSizeInBits(0) & 0x7) && |
0 |
18535 |
assert(!(Origin->getValueSizeInBits(0) & 0x7) && |
0 |
| 18536 |
"The size of the original loaded type is not a multiple of a" |
--- |
18536 |
"The size of the original loaded type is not a multiple of a" |
--- |
| 18537 |
" byte."); |
--- |
18537 |
" byte."); |
--- |
| 18538 |
// If Offset is bigger than TySizeInBytes, it means we are loading all |
--- |
18538 |
// If Offset is bigger than TySizeInBytes, it means we are loading all |
--- |
| 18539 |
// zeros. This should have been optimized before in the process. |
--- |
18539 |
// zeros. This should have been optimized before in the process. |
--- |
| 18540 |
assert(TySizeInBytes > Offset && |
0 |
18540 |
assert(TySizeInBytes > Offset && |
0 |
| 18541 |
"Invalid shift amount for given loaded size"); |
--- |
18541 |
"Invalid shift amount for given loaded size"); |
--- |
| 18542 |
if (IsBigEndian) |
0 |
18542 |
if (IsBigEndian) |
0 |
| 18543 |
Offset = TySizeInBytes - Offset - getLoadedSize(); |
0 |
18543 |
Offset = TySizeInBytes - Offset - getLoadedSize(); |
0 |
| 18544 |
return Offset; |
0 |
18544 |
return Offset; |
0 |
| 18545 |
} |
--- |
18545 |
} |
--- |
| 18546 |
|
--- |
18546 |
|
--- |
| 18547 |
/// Generate the sequence of instructions to load the slice |
--- |
18547 |
/// Generate the sequence of instructions to load the slice |
--- |
| 18548 |
/// represented by this object and redirect the uses of this slice to |
--- |
18548 |
/// represented by this object and redirect the uses of this slice to |
--- |
| 18549 |
/// this new sequence of instructions. |
--- |
18549 |
/// this new sequence of instructions. |
--- |
| 18550 |
/// \pre this->Inst && this->Origin are valid Instructions and this |
--- |
18550 |
/// \pre this->Inst && this->Origin are valid Instructions and this |
--- |
| 18551 |
/// object passed the legal check: LoadedSlice::isLegal returned true. |
--- |
18551 |
/// object passed the legal check: LoadedSlice::isLegal returned true. |
--- |
| 18552 |
/// \return The last instruction of the sequence used to load the slice. |
--- |
18552 |
/// \return The last instruction of the sequence used to load the slice. |
--- |
| 18553 |
SDValue loadSlice() const { |
0 |
18553 |
SDValue loadSlice() const { |
0 |
| 18554 |
assert(Inst && Origin && "Unable to replace a non-existing slice."); |
0 |
18554 |
assert(Inst && Origin && "Unable to replace a non-existing slice."); |
0 |
| 18555 |
const SDValue &OldBaseAddr = Origin->getBasePtr(); |
0 |
18555 |
const SDValue &OldBaseAddr = Origin->getBasePtr(); |
0 |
| 18556 |
SDValue BaseAddr = OldBaseAddr; |
0 |
18556 |
SDValue BaseAddr = OldBaseAddr; |
0 |
| 18557 |
// Get the offset in that chunk of bytes w.r.t. the endianness. |
--- |
18557 |
// Get the offset in that chunk of bytes w.r.t. the endianness. |
--- |
| 18558 |
int64_t Offset = static_cast(getOffsetFromBase()); |
0 |
18558 |
int64_t Offset = static_cast(getOffsetFromBase()); |
0 |
| 18559 |
assert(Offset >= 0 && "Offset too big to fit in int64_t!"); |
0 |
18559 |
assert(Offset >= 0 && "Offset too big to fit in int64_t!"); |
0 |
| 18560 |
if (Offset) { |
0 |
18560 |
if (Offset) { |
0 |
| 18561 |
// BaseAddr = BaseAddr + Offset. |
--- |
18561 |
// BaseAddr = BaseAddr + Offset. |
--- |
| 18562 |
EVT ArithType = BaseAddr.getValueType(); |
0 |
18562 |
EVT ArithType = BaseAddr.getValueType(); |
0 |
| 18563 |
SDLoc DL(Origin); |
0 |
18563 |
SDLoc DL(Origin); |
0 |
| 18564 |
BaseAddr = DAG->getNode(ISD::ADD, DL, ArithType, BaseAddr, |
0 |
18564 |
BaseAddr = DAG->getNode(ISD::ADD, DL, ArithType, BaseAddr, |
0 |
| 18565 |
DAG->getConstant(Offset, DL, ArithType)); |
0 |
18565 |
DAG->getConstant(Offset, DL, ArithType)); |
0 |
| 18566 |
} |
0 |
18566 |
} |
0 |
| 18567 |
|
--- |
18567 |
|
--- |
| 18568 |
// Create the type of the loaded slice according to its size. |
--- |
18568 |
// Create the type of the loaded slice according to its size. |
--- |
| 18569 |
EVT SliceType = getLoadedType(); |
0 |
18569 |
EVT SliceType = getLoadedType(); |
0 |
| 18570 |
|
--- |
18570 |
|
--- |
| 18571 |
// Create the load for the slice. |
--- |
18571 |
// Create the load for the slice. |
--- |
| 18572 |
SDValue LastInst = |
--- |
18572 |
SDValue LastInst = |
--- |
| 18573 |
DAG->getLoad(SliceType, SDLoc(Origin), Origin->getChain(), BaseAddr, |
0 |
18573 |
DAG->getLoad(SliceType, SDLoc(Origin), Origin->getChain(), BaseAddr, |
0 |
| 18574 |
Origin->getPointerInfo().getWithOffset(Offset), getAlign(), |
0 |
18574 |
Origin->getPointerInfo().getWithOffset(Offset), getAlign(), |
0 |
| 18575 |
Origin->getMemOperand()->getFlags()); |
0 |
18575 |
Origin->getMemOperand()->getFlags()); |
0 |
| 18576 |
// If the final type is not the same as the loaded type, this means that |
--- |
18576 |
// If the final type is not the same as the loaded type, this means that |
--- |
| 18577 |
// we have to pad with zero. Create a zero extend for that. |
--- |
18577 |
// we have to pad with zero. Create a zero extend for that. |
--- |
| 18578 |
EVT FinalType = Inst->getValueType(0); |
0 |
18578 |
EVT FinalType = Inst->getValueType(0); |
0 |
| 18579 |
if (SliceType != FinalType) |
0 |
18579 |
if (SliceType != FinalType) |
0 |
| 18580 |
LastInst = |
0 |
18580 |
LastInst = |
0 |
| 18581 |
DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst); |
0 |
18581 |
DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst); |
0 |
| 18582 |
return LastInst; |
0 |
18582 |
return LastInst; |
0 |
| 18583 |
} |
--- |
18583 |
} |
--- |
| 18584 |
|
--- |
18584 |
|
--- |
| 18585 |
/// Check if this slice can be merged with an expensive cross register |
--- |
18585 |
/// Check if this slice can be merged with an expensive cross register |
--- |
| 18586 |
/// bank copy. E.g., |
--- |
18586 |
/// bank copy. E.g., |
--- |
| 18587 |
/// i = load i32 |
--- |
18587 |
/// i = load i32 |
--- |
| 18588 |
/// f = bitcast i32 i to float |
--- |
18588 |
/// f = bitcast i32 i to float |
--- |
| 18589 |
bool canMergeExpensiveCrossRegisterBankCopy() const { |
0 |
18589 |
bool canMergeExpensiveCrossRegisterBankCopy() const { |
0 |
| 18590 |
if (!Inst || !Inst->hasOneUse()) |
0 |
18590 |
if (!Inst || !Inst->hasOneUse()) |
0 |
| 18591 |
return false; |
0 |
18591 |
return false; |
0 |
| 18592 |
SDNode *Use = *Inst->use_begin(); |
0 |
18592 |
SDNode *Use = *Inst->use_begin(); |
0 |
| 18593 |
if (Use->getOpcode() != ISD::BITCAST) |
0 |
18593 |
if (Use->getOpcode() != ISD::BITCAST) |
0 |
| 18594 |
return false; |
0 |
18594 |
return false; |
0 |
| 18595 |
assert(DAG && "Missing context"); |
0 |
18595 |
assert(DAG && "Missing context"); |
0 |
| 18596 |
const TargetLowering &TLI = DAG->getTargetLoweringInfo(); |
0 |
18596 |
const TargetLowering &TLI = DAG->getTargetLoweringInfo(); |
0 |
| 18597 |
EVT ResVT = Use->getValueType(0); |
0 |
18597 |
EVT ResVT = Use->getValueType(0); |
0 |
| 18598 |
const TargetRegisterClass *ResRC = |
--- |
18598 |
const TargetRegisterClass *ResRC = |
--- |
| 18599 |
TLI.getRegClassFor(ResVT.getSimpleVT(), Use->isDivergent()); |
0 |
18599 |
TLI.getRegClassFor(ResVT.getSimpleVT(), Use->isDivergent()); |
0 |
| 18600 |
const TargetRegisterClass *ArgRC = |
--- |
18600 |
const TargetRegisterClass *ArgRC = |
--- |
| 18601 |
TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT(), |
0 |
18601 |
TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT(), |
0 |
| 18602 |
Use->getOperand(0)->isDivergent()); |
0 |
18602 |
Use->getOperand(0)->isDivergent()); |
0 |
| 18603 |
if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) |
0 |
18603 |
if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) |
0 |
| 18604 |
return false; |
0 |
18604 |
return false; |
0 |
| 18605 |
|
--- |
18605 |
|
--- |
| 18606 |
// At this point, we know that we perform a cross-register-bank copy. |
--- |
18606 |
// At this point, we know that we perform a cross-register-bank copy. |
--- |
| 18607 |
// Check if it is expensive. |
--- |
18607 |
// Check if it is expensive. |
--- |
| 18608 |
const TargetRegisterInfo *TRI = DAG->getSubtarget().getRegisterInfo(); |
0 |
18608 |
const TargetRegisterInfo *TRI = DAG->getSubtarget().getRegisterInfo(); |
0 |
| 18609 |
// Assume bitcasts are cheap, unless both register classes do not |
--- |
18609 |
// Assume bitcasts are cheap, unless both register classes do not |
--- |
| 18610 |
// explicitly share a common sub class. |
--- |
18610 |
// explicitly share a common sub class. |
--- |
| 18611 |
if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC)) |
0 |
18611 |
if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC)) |
0 |
| 18612 |
return false; |
0 |
18612 |
return false; |
0 |
| 18613 |
|
--- |
18613 |
|
--- |
| 18614 |
// Check if it will be merged with the load. |
--- |
18614 |
// Check if it will be merged with the load. |
--- |
| 18615 |
// 1. Check the alignment / fast memory access constraint. |
--- |
18615 |
// 1. Check the alignment / fast memory access constraint. |
--- |
| 18616 |
unsigned IsFast = 0; |
0 |
18616 |
unsigned IsFast = 0; |
0 |
| 18617 |
if (!TLI.allowsMemoryAccess(*DAG->getContext(), DAG->getDataLayout(), ResVT, |
0 |
18617 |
if (!TLI.allowsMemoryAccess(*DAG->getContext(), DAG->getDataLayout(), ResVT, |
0 |
| 18618 |
Origin->getAddressSpace(), getAlign(), |
0 |
18618 |
Origin->getAddressSpace(), getAlign(), |
0 |
| 18619 |
Origin->getMemOperand()->getFlags(), &IsFast) || |
0 |
18619 |
Origin->getMemOperand()->getFlags(), &IsFast) || |
0 |
| 18620 |
!IsFast) |
0 |
18620 |
!IsFast) |
0 |
| 18621 |
return false; |
0 |
18621 |
return false; |
0 |
| 18622 |
|
--- |
18622 |
|
--- |
| 18623 |
// 2. Check that the load is a legal operation for that type. |
--- |
18623 |
// 2. Check that the load is a legal operation for that type. |
--- |
| 18624 |
if (!TLI.isOperationLegal(ISD::LOAD, ResVT)) |
0 |
18624 |
if (!TLI.isOperationLegal(ISD::LOAD, ResVT)) |
0 |
| 18625 |
return false; |
0 |
18625 |
return false; |
0 |
| 18626 |
|
--- |
18626 |
|
--- |
| 18627 |
// 3. Check that we do not have a zext in the way. |
--- |
18627 |
// 3. Check that we do not have a zext in the way. |
--- |
| 18628 |
if (Inst->getValueType(0) != getLoadedType()) |
0 |
18628 |
if (Inst->getValueType(0) != getLoadedType()) |
0 |
| 18629 |
return false; |
0 |
18629 |
return false; |
0 |
| 18630 |
|
--- |
18630 |
|
--- |
| 18631 |
return true; |
0 |
18631 |
return true; |
0 |
| 18632 |
} |
--- |
18632 |
} |
--- |
| 18633 |
}; |
--- |
18633 |
}; |
--- |
| 18634 |
|
--- |
18634 |
|
--- |
| 18635 |
} // end anonymous namespace |
--- |
18635 |
} // end anonymous namespace |
--- |
| 18636 |
|
--- |
18636 |
|
--- |
| 18637 |
/// Check that all bits set in \p UsedBits form a dense region, i.e., |
--- |
18637 |
/// Check that all bits set in \p UsedBits form a dense region, i.e., |
--- |
| 18638 |
/// \p UsedBits looks like 0..0 1..1 0..0. |
--- |
18638 |
/// \p UsedBits looks like 0..0 1..1 0..0. |
--- |
| 18639 |
static bool areUsedBitsDense(const APInt &UsedBits) { |
0 |
18639 |
static bool areUsedBitsDense(const APInt &UsedBits) { |
0 |
| 18640 |
// If all the bits are one, this is dense! |
--- |
18640 |
// If all the bits are one, this is dense! |
--- |
| 18641 |
if (UsedBits.isAllOnes()) |
0 |
18641 |
if (UsedBits.isAllOnes()) |
0 |
| 18642 |
return true; |
0 |
18642 |
return true; |
0 |
| 18643 |
|
--- |
18643 |
|
--- |
| 18644 |
// Get rid of the unused bits on the right. |
--- |
18644 |
// Get rid of the unused bits on the right. |
--- |
| 18645 |
APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countr_zero()); |
0 |
18645 |
APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countr_zero()); |
0 |
| 18646 |
// Get rid of the unused bits on the left. |
--- |
18646 |
// Get rid of the unused bits on the left. |
--- |
| 18647 |
if (NarrowedUsedBits.countl_zero()) |
0 |
18647 |
if (NarrowedUsedBits.countl_zero()) |
0 |
| 18648 |
NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits()); |
0 |
18648 |
NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits()); |
0 |
| 18649 |
// Check that the chunk of bits is completely used. |
--- |
18649 |
// Check that the chunk of bits is completely used. |
--- |
| 18650 |
return NarrowedUsedBits.isAllOnes(); |
0 |
18650 |
return NarrowedUsedBits.isAllOnes(); |
0 |
| 18651 |
} |
0 |
18651 |
} |
0 |
| 18652 |
|
--- |
18652 |
|
--- |
| 18653 |
/// Check whether or not \p First and \p Second are next to each other |
--- |
18653 |
/// Check whether or not \p First and \p Second are next to each other |
--- |
| 18654 |
/// in memory. This means that there is no hole between the bits loaded |
--- |
18654 |
/// in memory. This means that there is no hole between the bits loaded |
--- |
| 18655 |
/// by \p First and the bits loaded by \p Second. |
--- |
18655 |
/// by \p First and the bits loaded by \p Second. |
--- |
| 18656 |
static bool areSlicesNextToEachOther(const LoadedSlice &First, |
0 |
18656 |
static bool areSlicesNextToEachOther(const LoadedSlice &First, |
0 |
| 18657 |
const LoadedSlice &Second) { |
--- |
18657 |
const LoadedSlice &Second) { |
--- |
| 18658 |
assert(First.Origin == Second.Origin && First.Origin && |
0 |
18658 |
assert(First.Origin == Second.Origin && First.Origin && |
0 |
| 18659 |
"Unable to match different memory origins."); |
--- |
18659 |
"Unable to match different memory origins."); |
--- |
| 18660 |
APInt UsedBits = First.getUsedBits(); |
0 |
18660 |
APInt UsedBits = First.getUsedBits(); |
0 |
| 18661 |
assert((UsedBits & Second.getUsedBits()) == 0 && |
0 |
18661 |
assert((UsedBits & Second.getUsedBits()) == 0 && |
0 |
| 18662 |
"Slices are not supposed to overlap."); |
--- |
18662 |
"Slices are not supposed to overlap."); |
--- |
| 18663 |
UsedBits |= Second.getUsedBits(); |
0 |
18663 |
UsedBits |= Second.getUsedBits(); |
0 |
| 18664 |
return areUsedBitsDense(UsedBits); |
0 |
18664 |
return areUsedBitsDense(UsedBits); |
0 |
| 18665 |
} |
0 |
18665 |
} |
0 |
| 18666 |
|
--- |
18666 |
|
--- |
| 18667 |
/// Adjust the \p GlobalLSCost according to the target |
--- |
18667 |
/// Adjust the \p GlobalLSCost according to the target |
--- |
| 18668 |
/// paring capabilities and the layout of the slices. |
--- |
18668 |
/// paring capabilities and the layout of the slices. |
--- |
| 18669 |
/// \pre \p GlobalLSCost should account for at least as many loads as |
--- |
18669 |
/// \pre \p GlobalLSCost should account for at least as many loads as |
--- |
| 18670 |
/// there is in the slices in \p LoadedSlices. |
--- |
18670 |
/// there is in the slices in \p LoadedSlices. |
--- |
| 18671 |
static void adjustCostForPairing(SmallVectorImpl &LoadedSlices, |
0 |
18671 |
static void adjustCostForPairing(SmallVectorImpl &LoadedSlices, |
0 |
| 18672 |
LoadedSlice::Cost &GlobalLSCost) { |
--- |
18672 |
LoadedSlice::Cost &GlobalLSCost) { |
--- |
| 18673 |
unsigned NumberOfSlices = LoadedSlices.size(); |
0 |
18673 |
unsigned NumberOfSlices = LoadedSlices.size(); |
0 |
| 18674 |
// If there is less than 2 elements, no pairing is possible. |
--- |
18674 |
// If there is less than 2 elements, no pairing is possible. |
--- |
| 18675 |
if (NumberOfSlices < 2) |
0 |
18675 |
if (NumberOfSlices < 2) |
0 |
| 18676 |
return; |
0 |
18676 |
return; |
0 |
| 18677 |
|
--- |
18677 |
|
--- |
| 18678 |
// Sort the slices so that elements that are likely to be next to each |
--- |
18678 |
// Sort the slices so that elements that are likely to be next to each |
--- |
| 18679 |
// other in memory are next to each other in the list. |
--- |
18679 |
// other in memory are next to each other in the list. |
--- |
| 18680 |
llvm::sort(LoadedSlices, [](const LoadedSlice &LHS, const LoadedSlice &RHS) { |
0 |
18680 |
llvm::sort(LoadedSlices, [](const LoadedSlice &LHS, const LoadedSlice &RHS) { |
0 |
| 18681 |
assert(LHS.Origin == RHS.Origin && "Different bases not implemented."); |
0 |
18681 |
assert(LHS.Origin == RHS.Origin && "Different bases not implemented."); |
0 |
| 18682 |
return LHS.getOffsetFromBase() < RHS.getOffsetFromBase(); |
0 |
18682 |
return LHS.getOffsetFromBase() < RHS.getOffsetFromBase(); |
0 |
| 18683 |
}); |
--- |
18683 |
}); |
--- |
| 18684 |
const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo(); |
0 |
18684 |
const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo(); |
0 |
| 18685 |
// First (resp. Second) is the first (resp. Second) potentially candidate |
--- |
18685 |
// First (resp. Second) is the first (resp. Second) potentially candidate |
--- |
| 18686 |
// to be placed in a paired load. |
--- |
18686 |
// to be placed in a paired load. |
--- |
| 18687 |
const LoadedSlice *First = nullptr; |
0 |
18687 |
const LoadedSlice *First = nullptr; |
0 |
| 18688 |
const LoadedSlice *Second = nullptr; |
0 |
18688 |
const LoadedSlice *Second = nullptr; |
0 |
| 18689 |
for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice, |
0 |
18689 |
for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice, |
0 |
| 18690 |
// Set the beginning of the pair. |
--- |
18690 |
// Set the beginning of the pair. |
--- |
| 18691 |
First = Second) { |
0 |
18691 |
First = Second) { |
0 |
| 18692 |
Second = &LoadedSlices[CurrSlice]; |
0 |
18692 |
Second = &LoadedSlices[CurrSlice]; |
0 |
| 18693 |
|
--- |
18693 |
|
--- |
| 18694 |
// If First is NULL, it means we start a new pair. |
--- |
18694 |
// If First is NULL, it means we start a new pair. |
--- |
| 18695 |
// Get to the next slice. |
--- |
18695 |
// Get to the next slice. |
--- |
| 18696 |
if (!First) |
0 |
18696 |
if (!First) |
0 |
| 18697 |
continue; |
0 |
18697 |
continue; |
0 |
| 18698 |
|
--- |
18698 |
|
--- |
| 18699 |
EVT LoadedType = First->getLoadedType(); |
0 |
18699 |
EVT LoadedType = First->getLoadedType(); |
0 |
| 18700 |
|
--- |
18700 |
|
--- |
| 18701 |
// If the types of the slices are different, we cannot pair them. |
--- |
18701 |
// If the types of the slices are different, we cannot pair them. |
--- |
| 18702 |
if (LoadedType != Second->getLoadedType()) |
0 |
18702 |
if (LoadedType != Second->getLoadedType()) |
0 |
| 18703 |
continue; |
0 |
18703 |
continue; |
0 |
| 18704 |
|
--- |
18704 |
|
--- |
| 18705 |
// Check if the target supplies paired loads for this type. |
--- |
18705 |
// Check if the target supplies paired loads for this type. |
--- |
| 18706 |
Align RequiredAlignment; |
0 |
18706 |
Align RequiredAlignment; |
0 |
| 18707 |
if (!TLI.hasPairedLoad(LoadedType, RequiredAlignment)) { |
0 |
18707 |
if (!TLI.hasPairedLoad(LoadedType, RequiredAlignment)) { |
0 |
| 18708 |
// move to the next pair, this type is hopeless. |
--- |
18708 |
// move to the next pair, this type is hopeless. |
--- |
| 18709 |
Second = nullptr; |
0 |
18709 |
Second = nullptr; |
0 |
| 18710 |
continue; |
0 |
18710 |
continue; |
0 |
| 18711 |
} |
--- |
18711 |
} |
--- |
| 18712 |
// Check if we meet the alignment requirement. |
--- |
18712 |
// Check if we meet the alignment requirement. |
--- |
| 18713 |
if (First->getAlign() < RequiredAlignment) |
0 |
18713 |
if (First->getAlign() < RequiredAlignment) |
0 |
| 18714 |
continue; |
0 |
18714 |
continue; |
0 |
| 18715 |
|
--- |
18715 |
|
--- |
| 18716 |
// Check that both loads are next to each other in memory. |
--- |
18716 |
// Check that both loads are next to each other in memory. |
--- |
| 18717 |
if (!areSlicesNextToEachOther(*First, *Second)) |
0 |
18717 |
if (!areSlicesNextToEachOther(*First, *Second)) |
0 |
| 18718 |
continue; |
0 |
18718 |
continue; |
0 |
| 18719 |
|
--- |
18719 |
|
--- |
| 18720 |
assert(GlobalLSCost.Loads > 0 && "We save more loads than we created!"); |
0 |
18720 |
assert(GlobalLSCost.Loads > 0 && "We save more loads than we created!"); |
0 |
| 18721 |
--GlobalLSCost.Loads; |
0 |
18721 |
--GlobalLSCost.Loads; |
0 |
| 18722 |
// Move to the next pair. |
--- |
18722 |
// Move to the next pair. |
--- |
| 18723 |
Second = nullptr; |
0 |
18723 |
Second = nullptr; |
0 |
| 18724 |
} |
--- |
18724 |
} |
--- |
| 18725 |
} |
--- |
18725 |
} |
--- |
| 18726 |
|
--- |
18726 |
|
--- |
| 18727 |
/// Check the profitability of all involved LoadedSlice. |
--- |
18727 |
/// Check the profitability of all involved LoadedSlice. |
--- |
| 18728 |
/// Currently, it is considered profitable if there is exactly two |
--- |
18728 |
/// Currently, it is considered profitable if there is exactly two |
--- |
| 18729 |
/// involved slices (1) which are (2) next to each other in memory, and |
--- |
18729 |
/// involved slices (1) which are (2) next to each other in memory, and |
--- |
| 18730 |
/// whose cost (\see LoadedSlice::Cost) is smaller than the original load (3). |
--- |
18730 |
/// whose cost (\see LoadedSlice::Cost) is smaller than the original load (3). |
--- |
| 18731 |
/// |
--- |
18731 |
/// |
--- |
| 18732 |
/// Note: The order of the elements in \p LoadedSlices may be modified, but not |
--- |
18732 |
/// Note: The order of the elements in \p LoadedSlices may be modified, but not |
--- |
| 18733 |
/// the elements themselves. |
--- |
18733 |
/// the elements themselves. |
--- |
| 18734 |
/// |
--- |
18734 |
/// |
--- |
| 18735 |
/// FIXME: When the cost model will be mature enough, we can relax |
--- |
18735 |
/// FIXME: When the cost model will be mature enough, we can relax |
--- |
| 18736 |
/// constraints (1) and (2). |
--- |
18736 |
/// constraints (1) and (2). |
--- |
| 18737 |
static bool isSlicingProfitable(SmallVectorImpl &LoadedSlices, |
0 |
18737 |
static bool isSlicingProfitable(SmallVectorImpl &LoadedSlices, |
0 |
| 18738 |
const APInt &UsedBits, bool ForCodeSize) { |
--- |
18738 |
const APInt &UsedBits, bool ForCodeSize) { |
--- |
| 18739 |
unsigned NumberOfSlices = LoadedSlices.size(); |
0 |
18739 |
unsigned NumberOfSlices = LoadedSlices.size(); |
0 |
| 18740 |
if (StressLoadSlicing) |
0 |
18740 |
if (StressLoadSlicing) |
0 |
| 18741 |
return NumberOfSlices > 1; |
0 |
18741 |
return NumberOfSlices > 1; |
0 |
| 18742 |
|
--- |
18742 |
|
--- |
| 18743 |
// Check (1). |
--- |
18743 |
// Check (1). |
--- |
| 18744 |
if (NumberOfSlices != 2) |
0 |
18744 |
if (NumberOfSlices != 2) |
0 |
| 18745 |
return false; |
0 |
18745 |
return false; |
0 |
| 18746 |
|
--- |
18746 |
|
--- |
| 18747 |
// Check (2). |
--- |
18747 |
// Check (2). |
--- |
| 18748 |
if (!areUsedBitsDense(UsedBits)) |
0 |
18748 |
if (!areUsedBitsDense(UsedBits)) |
0 |
| 18749 |
return false; |
0 |
18749 |
return false; |
0 |
| 18750 |
|
--- |
18750 |
|
--- |
| 18751 |
// Check (3). |
--- |
18751 |
// Check (3). |
--- |
| 18752 |
LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize); |
0 |
18752 |
LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize); |
0 |
| 18753 |
// The original code has one big load. |
--- |
18753 |
// The original code has one big load. |
--- |
| 18754 |
OrigCost.Loads = 1; |
0 |
18754 |
OrigCost.Loads = 1; |
0 |
| 18755 |
for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice) { |
0 |
18755 |
for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice) { |
0 |
| 18756 |
const LoadedSlice &LS = LoadedSlices[CurrSlice]; |
0 |
18756 |
const LoadedSlice &LS = LoadedSlices[CurrSlice]; |
0 |
| 18757 |
// Accumulate the cost of all the slices. |
--- |
18757 |
// Accumulate the cost of all the slices. |
--- |
| 18758 |
LoadedSlice::Cost SliceCost(LS, ForCodeSize); |
0 |
18758 |
LoadedSlice::Cost SliceCost(LS, ForCodeSize); |
0 |
| 18759 |
GlobalSlicingCost += SliceCost; |
0 |
18759 |
GlobalSlicingCost += SliceCost; |
0 |
| 18760 |
|
--- |
18760 |
|
--- |
| 18761 |
// Account as cost in the original configuration the gain obtained |
--- |
18761 |
// Account as cost in the original configuration the gain obtained |
--- |
| 18762 |
// with the current slices. |
--- |
18762 |
// with the current slices. |
--- |
| 18763 |
OrigCost.addSliceGain(LS); |
0 |
18763 |
OrigCost.addSliceGain(LS); |
0 |
| 18764 |
} |
--- |
18764 |
} |
--- |
| 18765 |
|
--- |
18765 |
|
--- |
| 18766 |
// If the target supports paired load, adjust the cost accordingly. |
--- |
18766 |
// If the target supports paired load, adjust the cost accordingly. |
--- |
| 18767 |
adjustCostForPairing(LoadedSlices, GlobalSlicingCost); |
0 |
18767 |
adjustCostForPairing(LoadedSlices, GlobalSlicingCost); |
0 |
| 18768 |
return OrigCost > GlobalSlicingCost; |
0 |
18768 |
return OrigCost > GlobalSlicingCost; |
0 |
| 18769 |
} |
--- |
18769 |
} |
--- |
| 18770 |
|
--- |
18770 |
|
--- |
| 18771 |
/// If the given load, \p LI, is used only by trunc or trunc(lshr) |
--- |
18771 |
/// If the given load, \p LI, is used only by trunc or trunc(lshr) |
--- |
| 18772 |
/// operations, split it in the various pieces being extracted. |
--- |
18772 |
/// operations, split it in the various pieces being extracted. |
--- |
| 18773 |
/// |
--- |
18773 |
/// |
--- |
| 18774 |
/// This sort of thing is introduced by SROA. |
--- |
18774 |
/// This sort of thing is introduced by SROA. |
--- |
| 18775 |
/// This slicing takes care not to insert overlapping loads. |
--- |
18775 |
/// This slicing takes care not to insert overlapping loads. |
--- |
| 18776 |
/// \pre LI is a simple load (i.e., not an atomic or volatile load). |
--- |
18776 |
/// \pre LI is a simple load (i.e., not an atomic or volatile load). |
--- |
| 18777 |
bool DAGCombiner::SliceUpLoad(SDNode *N) { |
12 |
18777 |
bool DAGCombiner::SliceUpLoad(SDNode *N) { |
12 |
| 18778 |
if (Level < AfterLegalizeDAG) |
12 |
18778 |
if (Level < AfterLegalizeDAG) |
12 |
| 18779 |
return false; |
7 |
18779 |
return false; |
7 |
| 18780 |
|
--- |
18780 |
|
--- |
| 18781 |
LoadSDNode *LD = cast(N); |
5 |
18781 |
LoadSDNode *LD = cast(N); |
5 |
| 18782 |
if (!LD->isSimple() || !ISD::isNormalLoad(LD) || |
10 |
18782 |
if (!LD->isSimple() || !ISD::isNormalLoad(LD) || |
10 |
| 18783 |
!LD->getValueType(0).isInteger()) |
10 |
18783 |
!LD->getValueType(0).isInteger()) |
10 |
| 18784 |
return false; |
0 |
18784 |
return false; |
0 |
| 18785 |
|
--- |
18785 |
|
--- |
| 18786 |
// The algorithm to split up a load of a scalable vector into individual |
--- |
18786 |
// The algorithm to split up a load of a scalable vector into individual |
--- |
| 18787 |
// elements currently requires knowing the length of the loaded type, |
--- |
18787 |
// elements currently requires knowing the length of the loaded type, |
--- |
| 18788 |
// so will need adjusting to work on scalable vectors. |
--- |
18788 |
// so will need adjusting to work on scalable vectors. |
--- |
| 18789 |
if (LD->getValueType(0).isScalableVector()) |
5 |
18789 |
if (LD->getValueType(0).isScalableVector()) |
5 |
| 18790 |
return false; |
0 |
18790 |
return false; |
0 |
| 18791 |
|
--- |
18791 |
|
--- |
| 18792 |
// Keep track of already used bits to detect overlapping values. |
--- |
18792 |
// Keep track of already used bits to detect overlapping values. |
--- |
| 18793 |
// In that case, we will just abort the transformation. |
--- |
18793 |
// In that case, we will just abort the transformation. |
--- |
| 18794 |
APInt UsedBits(LD->getValueSizeInBits(0), 0); |
5 |
18794 |
APInt UsedBits(LD->getValueSizeInBits(0), 0); |
5 |
| 18795 |
|
--- |
18795 |
|
--- |
| 18796 |
SmallVector LoadedSlices; |
5 |
18796 |
SmallVector LoadedSlices; |
5 |
| 18797 |
|
--- |
18797 |
|
--- |
| 18798 |
// Check if this load is used as several smaller chunks of bits. |
--- |
18798 |
// Check if this load is used as several smaller chunks of bits. |
--- |
| 18799 |
// Basically, look for uses in trunc or trunc(lshr) and record a new chain |
--- |
18799 |
// Basically, look for uses in trunc or trunc(lshr) and record a new chain |
--- |
| 18800 |
// of computation for each trunc. |
--- |
18800 |
// of computation for each trunc. |
--- |
| 18801 |
for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end(); |
5 |
18801 |
for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end(); |
5 |
| 18802 |
UI != UIEnd; ++UI) { |
5 |
18802 |
UI != UIEnd; ++UI) { |
5 |
| 18803 |
// Skip the uses of the chain. |
--- |
18803 |
// Skip the uses of the chain. |
--- |
| 18804 |
if (UI.getUse().getResNo() != 0) |
5 |
18804 |
if (UI.getUse().getResNo() != 0) |
5 |
| 18805 |
continue; |
0 |
18805 |
continue; |
0 |
| 18806 |
|
--- |
18806 |
|
--- |
| 18807 |
SDNode *User = *UI; |
5 |
18807 |
SDNode *User = *UI; |
5 |
| 18808 |
unsigned Shift = 0; |
5 |
18808 |
unsigned Shift = 0; |
5 |
| 18809 |
|
--- |
18809 |
|
--- |
| 18810 |
// Check if this is a trunc(lshr). |
--- |
18810 |
// Check if this is a trunc(lshr). |
--- |
| 18811 |
if (User->getOpcode() == ISD::SRL && User->hasOneUse() && |
5 |
18811 |
if (User->getOpcode() == ISD::SRL && User->hasOneUse() && |
5 |
| 18812 |
isa(User->getOperand(1))) { |
0 |
18812 |
isa(User->getOperand(1))) { |
0 |
| 18813 |
Shift = User->getConstantOperandVal(1); |
0 |
18813 |
Shift = User->getConstantOperandVal(1); |
0 |
| 18814 |
User = *User->use_begin(); |
0 |
18814 |
User = *User->use_begin(); |
0 |
| 18815 |
} |
--- |
18815 |
} |
--- |
| 18816 |
|
--- |
18816 |
|
--- |
| 18817 |
// At this point, User is a Truncate, iff we encountered, trunc or |
--- |
18817 |
// At this point, User is a Truncate, iff we encountered, trunc or |
--- |
| 18818 |
// trunc(lshr). |
--- |
18818 |
// trunc(lshr). |
--- |
| 18819 |
if (User->getOpcode() != ISD::TRUNCATE) |
5 |
18819 |
if (User->getOpcode() != ISD::TRUNCATE) |
5 |
| 18820 |
return false; |
5 |
18820 |
return false; |
5 |
| 18821 |
|
--- |
18821 |
|
--- |
| 18822 |
// The width of the type must be a power of 2 and greater than 8-bits. |
--- |
18822 |
// The width of the type must be a power of 2 and greater than 8-bits. |
--- |
| 18823 |
// Otherwise the load cannot be represented in LLVM IR. |
--- |
18823 |
// Otherwise the load cannot be represented in LLVM IR. |
--- |
| 18824 |
// Moreover, if we shifted with a non-8-bits multiple, the slice |
--- |
18824 |
// Moreover, if we shifted with a non-8-bits multiple, the slice |
--- |
| 18825 |
// will be across several bytes. We do not support that. |
--- |
18825 |
// will be across several bytes. We do not support that. |
--- |
| 18826 |
unsigned Width = User->getValueSizeInBits(0); |
0 |
18826 |
unsigned Width = User->getValueSizeInBits(0); |
0 |
| 18827 |
if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7)) |
0 |
18827 |
if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7)) |
0 |
| 18828 |
return false; |
0 |
18828 |
return false; |
0 |
| 18829 |
|
--- |
18829 |
|
--- |
| 18830 |
// Build the slice for this chain of computations. |
--- |
18830 |
// Build the slice for this chain of computations. |
--- |
| 18831 |
LoadedSlice LS(User, LD, Shift, &DAG); |
0 |
18831 |
LoadedSlice LS(User, LD, Shift, &DAG); |
0 |
| 18832 |
APInt CurrentUsedBits = LS.getUsedBits(); |
0 |
18832 |
APInt CurrentUsedBits = LS.getUsedBits(); |
0 |
| 18833 |
|
--- |
18833 |
|
--- |
| 18834 |
// Check if this slice overlaps with another. |
--- |
18834 |
// Check if this slice overlaps with another. |
--- |
| 18835 |
if ((CurrentUsedBits & UsedBits) != 0) |
0 |
18835 |
if ((CurrentUsedBits & UsedBits) != 0) |
0 |
| 18836 |
return false; |
0 |
18836 |
return false; |
0 |
| 18837 |
// Update the bits used globally. |
--- |
18837 |
// Update the bits used globally. |
--- |
| 18838 |
UsedBits |= CurrentUsedBits; |
0 |
18838 |
UsedBits |= CurrentUsedBits; |
0 |
| 18839 |
|
--- |
18839 |
|
--- |
| 18840 |
// Check if the new slice would be legal. |
--- |
18840 |
// Check if the new slice would be legal. |
--- |
| 18841 |
if (!LS.isLegal()) |
0 |
18841 |
if (!LS.isLegal()) |
0 |
| 18842 |
return false; |
0 |
18842 |
return false; |
0 |
| 18843 |
|
--- |
18843 |
|
--- |
| 18844 |
// Record the slice. |
--- |
18844 |
// Record the slice. |
--- |
| 18845 |
LoadedSlices.push_back(LS); |
0 |
18845 |
LoadedSlices.push_back(LS); |
0 |
| 18846 |
} |
0 |
18846 |
} |
0 |
| 18847 |
|
--- |
18847 |
|
--- |
| 18848 |
// Abort slicing if it does not seem to be profitable. |
--- |
18848 |
// Abort slicing if it does not seem to be profitable. |
--- |
| 18849 |
if (!isSlicingProfitable(LoadedSlices, UsedBits, ForCodeSize)) |
0 |
18849 |
if (!isSlicingProfitable(LoadedSlices, UsedBits, ForCodeSize)) |
0 |
| 18850 |
return false; |
0 |
18850 |
return false; |
0 |
| 18851 |
|
--- |
18851 |
|
--- |
| 18852 |
++SlicedLoads; |
0 |
18852 |
++SlicedLoads; |
0 |
| 18853 |
|
--- |
18853 |
|
--- |
| 18854 |
// Rewrite each chain to use an independent load. |
--- |
18854 |
// Rewrite each chain to use an independent load. |
--- |
| 18855 |
// By construction, each chain can be represented by a unique load. |
--- |
18855 |
// By construction, each chain can be represented by a unique load. |
--- |
| 18856 |
|
--- |
18856 |
|
--- |
| 18857 |
// Prepare the argument for the new token factor for all the slices. |
--- |
18857 |
// Prepare the argument for the new token factor for all the slices. |
--- |
| 18858 |
SmallVector ArgChains; |
0 |
18858 |
SmallVector ArgChains; |
0 |
| 18859 |
for (const LoadedSlice &LS : LoadedSlices) { |
0 |
18859 |
for (const LoadedSlice &LS : LoadedSlices) { |
0 |
| 18860 |
SDValue SliceInst = LS.loadSlice(); |
0 |
18860 |
SDValue SliceInst = LS.loadSlice(); |
0 |
| 18861 |
CombineTo(LS.Inst, SliceInst, true); |
0 |
18861 |
CombineTo(LS.Inst, SliceInst, true); |
0 |
| 18862 |
if (SliceInst.getOpcode() != ISD::LOAD) |
0 |
18862 |
if (SliceInst.getOpcode() != ISD::LOAD) |
0 |
| 18863 |
SliceInst = SliceInst.getOperand(0); |
0 |
18863 |
SliceInst = SliceInst.getOperand(0); |
0 |
| 18864 |
assert(SliceInst->getOpcode() == ISD::LOAD && |
0 |
18864 |
assert(SliceInst->getOpcode() == ISD::LOAD && |
0 |
| 18865 |
"It takes more than a zext to get to the loaded slice!!"); |
--- |
18865 |
"It takes more than a zext to get to the loaded slice!!"); |
--- |
| 18866 |
ArgChains.push_back(SliceInst.getValue(1)); |
0 |
18866 |
ArgChains.push_back(SliceInst.getValue(1)); |
0 |
| 18867 |
} |
--- |
18867 |
} |
--- |
| 18868 |
|
--- |
18868 |
|
--- |
| 18869 |
SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, |
0 |
18869 |
SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, |
0 |
| 18870 |
ArgChains); |
--- |
18870 |
ArgChains); |
--- |
| 18871 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); |
0 |
18871 |
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); |
0 |
| 18872 |
AddToWorklist(Chain.getNode()); |
0 |
18872 |
AddToWorklist(Chain.getNode()); |
0 |
| 18873 |
return true; |
0 |
18873 |
return true; |
0 |
| 18874 |
} |
5 |
18874 |
} |
5 |
| 18875 |
|
--- |
18875 |
|
--- |
| 18876 |
/// Check to see if V is (and load (ptr), imm), where the load is having |
--- |
18876 |
/// Check to see if V is (and load (ptr), imm), where the load is having |
--- |
| 18877 |
/// specific bytes cleared out. If so, return the byte size being masked out |
--- |
18877 |
/// specific bytes cleared out. If so, return the byte size being masked out |
--- |
| 18878 |
/// and the shift amount. |
--- |
18878 |
/// and the shift amount. |
--- |
| 18879 |
static std::pair |
--- |
18879 |
static std::pair |
--- |
| 18880 |
CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { |
0 |
18880 |
CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { |
0 |
| 18881 |
std::pair Result(0, 0); |
0 |
18881 |
std::pair Result(0, 0); |
0 |
| 18882 |
|
--- |
18882 |
|
--- |
| 18883 |
// Check for the structure we're looking for. |
--- |
18883 |
// Check for the structure we're looking for. |
--- |
| 18884 |
if (V->getOpcode() != ISD::AND || |
0 |
18884 |
if (V->getOpcode() != ISD::AND || |
0 |
| 18885 |
!isa(V->getOperand(1)) || |
0 |
18885 |
!isa(V->getOperand(1)) || |
0 |
| 18886 |
!ISD::isNormalLoad(V->getOperand(0).getNode())) |
0 |
18886 |
!ISD::isNormalLoad(V->getOperand(0).getNode())) |
0 |
| 18887 |
return Result; |
0 |
18887 |
return Result; |
0 |
| 18888 |
|
--- |
18888 |
|
--- |
| 18889 |
// Check the chain and pointer. |
--- |
18889 |
// Check the chain and pointer. |
--- |
| 18890 |
LoadSDNode *LD = cast(V->getOperand(0)); |
0 |
18890 |
LoadSDNode *LD = cast(V->getOperand(0)); |
0 |
| 18891 |
if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. |
0 |
18891 |
if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. |
0 |
| 18892 |
|
--- |
18892 |
|
--- |
| 18893 |
// This only handles simple types. |
--- |
18893 |
// This only handles simple types. |
--- |
| 18894 |
if (V.getValueType() != MVT::i16 && |
0 |
18894 |
if (V.getValueType() != MVT::i16 && |
0 |
| 18895 |
V.getValueType() != MVT::i32 && |
0 |
18895 |
V.getValueType() != MVT::i32 && |
0 |
| 18896 |
V.getValueType() != MVT::i64) |
0 |
18896 |
V.getValueType() != MVT::i64) |
0 |
| 18897 |
return Result; |
0 |
18897 |
return Result; |
0 |
| 18898 |
|
--- |
18898 |
|
--- |
| 18899 |
// Check the constant mask. Invert it so that the bits being masked out are |
--- |
18899 |
// Check the constant mask. Invert it so that the bits being masked out are |
--- |
| 18900 |
// 0 and the bits being kept are 1. Use getSExtValue so that leading bits |
--- |
18900 |
// 0 and the bits being kept are 1. Use getSExtValue so that leading bits |
--- |
| 18901 |
// follow the sign bit for uniformity. |
--- |
18901 |
// follow the sign bit for uniformity. |
--- |
| 18902 |
uint64_t NotMask = ~cast(V->getOperand(1))->getSExtValue(); |
0 |
18902 |
uint64_t NotMask = ~cast(V->getOperand(1))->getSExtValue(); |
0 |
| 18903 |
unsigned NotMaskLZ = llvm::countl_zero(NotMask); |
0 |
18903 |
unsigned NotMaskLZ = llvm::countl_zero(NotMask); |
0 |
| 18904 |
if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. |
0 |
18904 |
if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. |
0 |
| 18905 |
unsigned NotMaskTZ = llvm::countr_zero(NotMask); |
0 |
18905 |
unsigned NotMaskTZ = llvm::countr_zero(NotMask); |
0 |
| 18906 |
if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. |
0 |
18906 |
if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. |
0 |
| 18907 |
if (NotMaskLZ == 64) return Result; // All zero mask. |
0 |
18907 |
if (NotMaskLZ == 64) return Result; // All zero mask. |
0 |
| 18908 |
|
--- |
18908 |
|
--- |
| 18909 |
// See if we have a continuous run of bits. If so, we have 0*1+0* |
--- |
18909 |
// See if we have a continuous run of bits. If so, we have 0*1+0* |
--- |
| 18910 |
if (llvm::countr_one(NotMask >> NotMaskTZ) + NotMaskTZ + NotMaskLZ != 64) |
0 |
18910 |
if (llvm::countr_one(NotMask >> NotMaskTZ) + NotMaskTZ + NotMaskLZ != 64) |
0 |
| 18911 |
return Result; |
0 |
18911 |
return Result; |
0 |
| 18912 |
|
--- |
18912 |
|
--- |
| 18913 |
// Adjust NotMaskLZ down to be from the actual size of the int instead of i64. |
--- |
18913 |
// Adjust NotMaskLZ down to be from the actual size of the int instead of i64. |
--- |
| 18914 |
if (V.getValueType() != MVT::i64 && NotMaskLZ) |
0 |
18914 |
if (V.getValueType() != MVT::i64 && NotMaskLZ) |
0 |
| 18915 |
NotMaskLZ -= 64-V.getValueSizeInBits(); |
0 |
18915 |
NotMaskLZ -= 64-V.getValueSizeInBits(); |
0 |
| 18916 |
|
--- |
18916 |
|
--- |
| 18917 |
unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; |
0 |
18917 |
unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; |
0 |
| 18918 |
switch (MaskedBytes) { |
0 |
18918 |
switch (MaskedBytes) { |
0 |
| 18919 |
case 1: |
0 |
18919 |
case 1: |
0 |
| 18920 |
case 2: |
--- |
18920 |
case 2: |
--- |
| 18921 |
case 4: break; |
0 |
18921 |
case 4: break; |
0 |
| 18922 |
default: return Result; // All one mask, or 5-byte mask. |
0 |
18922 |
default: return Result; // All one mask, or 5-byte mask. |
0 |
| 18923 |
} |
--- |
18923 |
} |
--- |
| 18924 |
|
--- |
18924 |
|
--- |
| 18925 |
// Verify that the first bit starts at a multiple of mask so that the access |
--- |
18925 |
// Verify that the first bit starts at a multiple of mask so that the access |
--- |
| 18926 |
// is aligned the same as the access width. |
--- |
18926 |
// is aligned the same as the access width. |
--- |
| 18927 |
if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; |
0 |
18927 |
if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; |
0 |
| 18928 |
|
--- |
18928 |
|
--- |
| 18929 |
// For narrowing to be valid, it must be the case that the load the |
--- |
18929 |
// For narrowing to be valid, it must be the case that the load the |
--- |
| 18930 |
// immediately preceding memory operation before the store. |
--- |
18930 |
// immediately preceding memory operation before the store. |
--- |
| 18931 |
if (LD == Chain.getNode()) |
0 |
18931 |
if (LD == Chain.getNode()) |
0 |
| 18932 |
; // ok. |
--- |
18932 |
; // ok. |
--- |
| 18933 |
else if (Chain->getOpcode() == ISD::TokenFactor && |
0 |
18933 |
else if (Chain->getOpcode() == ISD::TokenFactor && |
0 |
| 18934 |
SDValue(LD, 1).hasOneUse()) { |
0 |
18934 |
SDValue(LD, 1).hasOneUse()) { |
0 |
| 18935 |
// LD has only 1 chain use so they are no indirect dependencies. |
--- |
18935 |
// LD has only 1 chain use so they are no indirect dependencies. |
--- |
| 18936 |
if (!LD->isOperandOf(Chain.getNode())) |
0 |
18936 |
if (!LD->isOperandOf(Chain.getNode())) |
0 |
| 18937 |
return Result; |
0 |
18937 |
return Result; |
0 |
| 18938 |
} else |
--- |
18938 |
} else |
--- |
| 18939 |
return Result; // Fail. |
0 |
18939 |
return Result; // Fail. |
0 |
| 18940 |
|
--- |
18940 |
|
--- |
| 18941 |
Result.first = MaskedBytes; |
0 |
18941 |
Result.first = MaskedBytes; |
0 |
| 18942 |
Result.second = NotMaskTZ/8; |
0 |
18942 |
Result.second = NotMaskTZ/8; |
0 |
| 18943 |
return Result; |
0 |
18943 |
return Result; |
0 |
| 18944 |
} |
--- |
18944 |
} |
--- |
| 18945 |
|
--- |
18945 |
|
--- |
| 18946 |
/// Check to see if IVal is something that provides a value as specified by |
--- |
18946 |
/// Check to see if IVal is something that provides a value as specified by |
--- |
| 18947 |
/// MaskInfo. If so, replace the specified store with a narrower store of |
--- |
18947 |
/// MaskInfo. If so, replace the specified store with a narrower store of |
--- |
| 18948 |
/// truncated IVal. |
--- |
18948 |
/// truncated IVal. |
--- |
| 18949 |
static SDValue |
--- |
18949 |
static SDValue |
--- |
| 18950 |
ShrinkLoadReplaceStoreWithStore(const std::pair &MaskInfo, |
0 |
18950 |
ShrinkLoadReplaceStoreWithStore(const std::pair &MaskInfo, |
0 |
| 18951 |
SDValue IVal, StoreSDNode *St, |
--- |
18951 |
SDValue IVal, StoreSDNode *St, |
--- |
| 18952 |
DAGCombiner *DC) { |
--- |
18952 |
DAGCombiner *DC) { |
--- |
| 18953 |
unsigned NumBytes = MaskInfo.first; |
0 |
18953 |
unsigned NumBytes = MaskInfo.first; |
0 |
| 18954 |
unsigned ByteShift = MaskInfo.second; |
0 |
18954 |
unsigned ByteShift = MaskInfo.second; |
0 |
| 18955 |
SelectionDAG &DAG = DC->getDAG(); |
0 |
18955 |
SelectionDAG &DAG = DC->getDAG(); |
0 |
| 18956 |
|
--- |
18956 |
|
--- |
| 18957 |
// Check to see if IVal is all zeros in the part being masked in by the 'or' |
--- |
18957 |
// Check to see if IVal is all zeros in the part being masked in by the 'or' |
--- |
| 18958 |
// that uses this. If not, this is not a replacement. |
--- |
18958 |
// that uses this. If not, this is not a replacement. |
--- |
| 18959 |
APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), |
0 |
18959 |
APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), |
0 |
| 18960 |
ByteShift*8, (ByteShift+NumBytes)*8); |
0 |
18960 |
ByteShift*8, (ByteShift+NumBytes)*8); |
0 |
| 18961 |
if (!DAG.MaskedValueIsZero(IVal, Mask)) return SDValue(); |
0 |
18961 |
if (!DAG.MaskedValueIsZero(IVal, Mask)) return SDValue(); |
0 |
| 18962 |
|
--- |
18962 |
|
--- |
| 18963 |
// Check that it is legal on the target to do this. It is legal if the new |
--- |
18963 |
// Check that it is legal on the target to do this. It is legal if the new |
--- |
| 18964 |
// VT we're shrinking to (i8/i16/i32) is legal or we're still before type |
--- |
18964 |
// VT we're shrinking to (i8/i16/i32) is legal or we're still before type |
--- |
| 18965 |
// legalization. If the source type is legal, but the store type isn't, see |
--- |
18965 |
// legalization. If the source type is legal, but the store type isn't, see |
--- |
| 18966 |
// if we can use a truncating store. |
--- |
18966 |
// if we can use a truncating store. |
--- |
| 18967 |
MVT VT = MVT::getIntegerVT(NumBytes * 8); |
0 |
18967 |
MVT VT = MVT::getIntegerVT(NumBytes * 8); |
0 |
| 18968 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
18968 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 18969 |
bool UseTruncStore; |
--- |
18969 |
bool UseTruncStore; |
--- |
| 18970 |
if (DC->isTypeLegal(VT)) |
0 |
18970 |
if (DC->isTypeLegal(VT)) |
0 |
| 18971 |
UseTruncStore = false; |
0 |
18971 |
UseTruncStore = false; |
0 |
| 18972 |
else if (TLI.isTypeLegal(IVal.getValueType()) && |
0 |
18972 |
else if (TLI.isTypeLegal(IVal.getValueType()) && |
0 |
| 18973 |
TLI.isTruncStoreLegal(IVal.getValueType(), VT)) |
0 |
18973 |
TLI.isTruncStoreLegal(IVal.getValueType(), VT)) |
0 |
| 18974 |
UseTruncStore = true; |
0 |
18974 |
UseTruncStore = true; |
0 |
| 18975 |
else |
--- |
18975 |
else |
--- |
| 18976 |
return SDValue(); |
0 |
18976 |
return SDValue(); |
0 |
| 18977 |
|
--- |
18977 |
|
--- |
| 18978 |
// Can't do this for indexed stores. |
--- |
18978 |
// Can't do this for indexed stores. |
--- |
| 18979 |
if (St->isIndexed()) |
0 |
18979 |
if (St->isIndexed()) |
0 |
| 18980 |
return SDValue(); |
0 |
18980 |
return SDValue(); |
0 |
| 18981 |
|
--- |
18981 |
|
--- |
| 18982 |
// Check that the target doesn't think this is a bad idea. |
--- |
18982 |
// Check that the target doesn't think this is a bad idea. |
--- |
| 18983 |
if (St->getMemOperand() && |
0 |
18983 |
if (St->getMemOperand() && |
0 |
| 18984 |
!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, |
0 |
18984 |
!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, |
0 |
| 18985 |
*St->getMemOperand())) |
0 |
18985 |
*St->getMemOperand())) |
0 |
| 18986 |
return SDValue(); |
0 |
18986 |
return SDValue(); |
0 |
| 18987 |
|
--- |
18987 |
|
--- |
| 18988 |
// Okay, we can do this! Replace the 'St' store with a store of IVal that is |
--- |
18988 |
// Okay, we can do this! Replace the 'St' store with a store of IVal that is |
--- |
| 18989 |
// shifted by ByteShift and truncated down to NumBytes. |
--- |
18989 |
// shifted by ByteShift and truncated down to NumBytes. |
--- |
| 18990 |
if (ByteShift) { |
0 |
18990 |
if (ByteShift) { |
0 |
| 18991 |
SDLoc DL(IVal); |
0 |
18991 |
SDLoc DL(IVal); |
0 |
| 18992 |
IVal = DAG.getNode(ISD::SRL, DL, IVal.getValueType(), IVal, |
0 |
18992 |
IVal = DAG.getNode(ISD::SRL, DL, IVal.getValueType(), IVal, |
0 |
| 18993 |
DAG.getConstant(ByteShift*8, DL, |
0 |
18993 |
DAG.getConstant(ByteShift*8, DL, |
0 |
| 18994 |
DC->getShiftAmountTy(IVal.getValueType()))); |
--- |
18994 |
DC->getShiftAmountTy(IVal.getValueType()))); |
--- |
| 18995 |
} |
0 |
18995 |
} |
0 |
| 18996 |
|
--- |
18996 |
|
--- |
| 18997 |
// Figure out the offset for the store and the alignment of the access. |
--- |
18997 |
// Figure out the offset for the store and the alignment of the access. |
--- |
| 18998 |
unsigned StOffset; |
--- |
18998 |
unsigned StOffset; |
--- |
| 18999 |
if (DAG.getDataLayout().isLittleEndian()) |
0 |
18999 |
if (DAG.getDataLayout().isLittleEndian()) |
0 |
| 19000 |
StOffset = ByteShift; |
0 |
19000 |
StOffset = ByteShift; |
0 |
| 19001 |
else |
--- |
19001 |
else |
--- |
| 19002 |
StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; |
0 |
19002 |
StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; |
0 |
| 19003 |
|
--- |
19003 |
|
--- |
| 19004 |
SDValue Ptr = St->getBasePtr(); |
0 |
19004 |
SDValue Ptr = St->getBasePtr(); |
0 |
| 19005 |
if (StOffset) { |
0 |
19005 |
if (StOffset) { |
0 |
| 19006 |
SDLoc DL(IVal); |
0 |
19006 |
SDLoc DL(IVal); |
0 |
| 19007 |
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(StOffset), DL); |
0 |
19007 |
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(StOffset), DL); |
0 |
| 19008 |
} |
0 |
19008 |
} |
0 |
| 19009 |
|
--- |
19009 |
|
--- |
| 19010 |
++OpsNarrowed; |
0 |
19010 |
++OpsNarrowed; |
0 |
| 19011 |
if (UseTruncStore) |
0 |
19011 |
if (UseTruncStore) |
0 |
| 19012 |
return DAG.getTruncStore(St->getChain(), SDLoc(St), IVal, Ptr, |
0 |
19012 |
return DAG.getTruncStore(St->getChain(), SDLoc(St), IVal, Ptr, |
0 |
| 19013 |
St->getPointerInfo().getWithOffset(StOffset), |
0 |
19013 |
St->getPointerInfo().getWithOffset(StOffset), |
0 |
| 19014 |
VT, St->getOriginalAlign()); |
0 |
19014 |
VT, St->getOriginalAlign()); |
0 |
| 19015 |
|
--- |
19015 |
|
--- |
| 19016 |
// Truncate down to the new size. |
--- |
19016 |
// Truncate down to the new size. |
--- |
| 19017 |
IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal); |
0 |
19017 |
IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal); |
0 |
| 19018 |
|
--- |
19018 |
|
--- |
| 19019 |
return DAG |
--- |
19019 |
return DAG |
--- |
| 19020 |
.getStore(St->getChain(), SDLoc(St), IVal, Ptr, |
0 |
19020 |
.getStore(St->getChain(), SDLoc(St), IVal, Ptr, |
0 |
| 19021 |
St->getPointerInfo().getWithOffset(StOffset), |
0 |
19021 |
St->getPointerInfo().getWithOffset(StOffset), |
0 |
| 19022 |
St->getOriginalAlign()); |
0 |
19022 |
St->getOriginalAlign()); |
0 |
| 19023 |
} |
0 |
19023 |
} |
0 |
| 19024 |
|
--- |
19024 |
|
--- |
| 19025 |
/// Look for sequence of load / op / store where op is one of 'or', 'xor', and |
--- |
19025 |
/// Look for sequence of load / op / store where op is one of 'or', 'xor', and |
--- |
| 19026 |
/// 'and' of immediates. If 'op' is only touching some of the loaded bits, try |
--- |
19026 |
/// 'and' of immediates. If 'op' is only touching some of the loaded bits, try |
--- |
| 19027 |
/// narrowing the load and store if it would end up being a win for performance |
--- |
19027 |
/// narrowing the load and store if it would end up being a win for performance |
--- |
| 19028 |
/// or code size. |
--- |
19028 |
/// or code size. |
--- |
| 19029 |
SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { |
10 |
19029 |
SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { |
10 |
| 19030 |
StoreSDNode *ST = cast(N); |
10 |
19030 |
StoreSDNode *ST = cast(N); |
10 |
| 19031 |
if (!ST->isSimple()) |
10 |
19031 |
if (!ST->isSimple()) |
10 |
| 19032 |
return SDValue(); |
0 |
19032 |
return SDValue(); |
0 |
| 19033 |
|
--- |
19033 |
|
--- |
| 19034 |
SDValue Chain = ST->getChain(); |
10 |
19034 |
SDValue Chain = ST->getChain(); |
10 |
| 19035 |
SDValue Value = ST->getValue(); |
10 |
19035 |
SDValue Value = ST->getValue(); |
10 |
| 19036 |
SDValue Ptr = ST->getBasePtr(); |
10 |
19036 |
SDValue Ptr = ST->getBasePtr(); |
10 |
| 19037 |
EVT VT = Value.getValueType(); |
10 |
19037 |
EVT VT = Value.getValueType(); |
10 |
| 19038 |
|
--- |
19038 |
|
--- |
| 19039 |
if (ST->isTruncatingStore() || VT.isVector()) |
10 |
19039 |
if (ST->isTruncatingStore() || VT.isVector()) |
10 |
| 19040 |
return SDValue(); |
0 |
19040 |
return SDValue(); |
0 |
| 19041 |
|
--- |
19041 |
|
--- |
| 19042 |
unsigned Opc = Value.getOpcode(); |
10 |
19042 |
unsigned Opc = Value.getOpcode(); |
10 |
| 19043 |
|
--- |
19043 |
|
--- |
| 19044 |
if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || |
10 |
19044 |
if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || |
10 |
| 19045 |
!Value.hasOneUse()) |
0 |
19045 |
!Value.hasOneUse()) |
0 |
| 19046 |
return SDValue(); |
10 |
19046 |
return SDValue(); |
10 |
| 19047 |
|
--- |
19047 |
|
--- |
| 19048 |
// If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst |
--- |
19048 |
// If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst |
--- |
| 19049 |
// is a byte mask indicating a consecutive number of bytes, check to see if |
--- |
19049 |
// is a byte mask indicating a consecutive number of bytes, check to see if |
--- |
| 19050 |
// Y is known to provide just those bytes. If so, we try to replace the |
--- |
19050 |
// Y is known to provide just those bytes. If so, we try to replace the |
--- |
| 19051 |
// load + replace + store sequence with a single (narrower) store, which makes |
--- |
19051 |
// load + replace + store sequence with a single (narrower) store, which makes |
--- |
| 19052 |
// the load dead. |
--- |
19052 |
// the load dead. |
--- |
| 19053 |
if (Opc == ISD::OR && EnableShrinkLoadReplaceStoreWithStore) { |
0 |
19053 |
if (Opc == ISD::OR && EnableShrinkLoadReplaceStoreWithStore) { |
0 |
| 19054 |
std::pair MaskedLoad; |
0 |
19054 |
std::pair MaskedLoad; |
0 |
| 19055 |
MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); |
0 |
19055 |
MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); |
0 |
| 19056 |
if (MaskedLoad.first) |
0 |
19056 |
if (MaskedLoad.first) |
0 |
| 19057 |
if (SDValue NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, |
0 |
19057 |
if (SDValue NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, |
0 |
| 19058 |
Value.getOperand(1), ST,this)) |
0 |
19058 |
Value.getOperand(1), ST,this)) |
0 |
| 19059 |
return NewST; |
0 |
19059 |
return NewST; |
0 |
| 19060 |
|
--- |
19060 |
|
--- |
| 19061 |
// Or is commutative, so try swapping X and Y. |
--- |
19061 |
// Or is commutative, so try swapping X and Y. |
--- |
| 19062 |
MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); |
0 |
19062 |
MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); |
0 |
| 19063 |
if (MaskedLoad.first) |
0 |
19063 |
if (MaskedLoad.first) |
0 |
| 19064 |
if (SDValue NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, |
0 |
19064 |
if (SDValue NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, |
0 |
| 19065 |
Value.getOperand(0), ST,this)) |
0 |
19065 |
Value.getOperand(0), ST,this)) |
0 |
| 19066 |
return NewST; |
0 |
19066 |
return NewST; |
0 |
| 19067 |
} |
--- |
19067 |
} |
--- |
| 19068 |
|
--- |
19068 |
|
--- |
| 19069 |
if (!EnableReduceLoadOpStoreWidth) |
0 |
19069 |
if (!EnableReduceLoadOpStoreWidth) |
0 |
| 19070 |
return SDValue(); |
0 |
19070 |
return SDValue(); |
0 |
| 19071 |
|
--- |
19071 |
|
--- |
| 19072 |
if (Value.getOperand(1).getOpcode() != ISD::Constant) |
0 |
19072 |
if (Value.getOperand(1).getOpcode() != ISD::Constant) |
0 |
| 19073 |
return SDValue(); |
0 |
19073 |
return SDValue(); |
0 |
| 19074 |
|
--- |
19074 |
|
--- |
| 19075 |
SDValue N0 = Value.getOperand(0); |
0 |
19075 |
SDValue N0 = Value.getOperand(0); |
0 |
| 19076 |
if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && |
0 |
19076 |
if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && |
0 |
| 19077 |
Chain == SDValue(N0.getNode(), 1)) { |
0 |
19077 |
Chain == SDValue(N0.getNode(), 1)) { |
0 |
| 19078 |
LoadSDNode *LD = cast(N0); |
0 |
19078 |
LoadSDNode *LD = cast(N0); |
0 |
| 19079 |
if (LD->getBasePtr() != Ptr || |
0 |
19079 |
if (LD->getBasePtr() != Ptr || |
0 |
| 19080 |
LD->getPointerInfo().getAddrSpace() != |
0 |
19080 |
LD->getPointerInfo().getAddrSpace() != |
0 |
| 19081 |
ST->getPointerInfo().getAddrSpace()) |
0 |
19081 |
ST->getPointerInfo().getAddrSpace()) |
0 |
| 19082 |
return SDValue(); |
0 |
19082 |
return SDValue(); |
0 |
| 19083 |
|
--- |
19083 |
|
--- |
| 19084 |
// Find the type to narrow it the load / op / store to. |
--- |
19084 |
// Find the type to narrow it the load / op / store to. |
--- |
| 19085 |
SDValue N1 = Value.getOperand(1); |
0 |
19085 |
SDValue N1 = Value.getOperand(1); |
0 |
| 19086 |
unsigned BitWidth = N1.getValueSizeInBits(); |
0 |
19086 |
unsigned BitWidth = N1.getValueSizeInBits(); |
0 |
| 19087 |
APInt Imm = cast(N1)->getAPIntValue(); |
0 |
19087 |
APInt Imm = cast(N1)->getAPIntValue(); |
0 |
| 19088 |
if (Opc == ISD::AND) |
0 |
19088 |
if (Opc == ISD::AND) |
0 |
| 19089 |
Imm ^= APInt::getAllOnes(BitWidth); |
0 |
19089 |
Imm ^= APInt::getAllOnes(BitWidth); |
0 |
| 19090 |
if (Imm == 0 || Imm.isAllOnes()) |
0 |
19090 |
if (Imm == 0 || Imm.isAllOnes()) |
0 |
| 19091 |
return SDValue(); |
0 |
19091 |
return SDValue(); |
0 |
| 19092 |
unsigned ShAmt = Imm.countr_zero(); |
0 |
19092 |
unsigned ShAmt = Imm.countr_zero(); |
0 |
| 19093 |
unsigned MSB = BitWidth - Imm.countl_zero() - 1; |
0 |
19093 |
unsigned MSB = BitWidth - Imm.countl_zero() - 1; |
0 |
| 19094 |
unsigned NewBW = NextPowerOf2(MSB - ShAmt); |
0 |
19094 |
unsigned NewBW = NextPowerOf2(MSB - ShAmt); |
0 |
| 19095 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); |
0 |
19095 |
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); |
0 |
| 19096 |
// The narrowing should be profitable, the load/store operation should be |
--- |
19096 |
// The narrowing should be profitable, the load/store operation should be |
--- |
| 19097 |
// legal (or custom) and the store size should be equal to the NewVT width. |
--- |
19097 |
// legal (or custom) and the store size should be equal to the NewVT width. |
--- |
| 19098 |
while (NewBW < BitWidth && |
0 |
19098 |
while (NewBW < BitWidth && |
0 |
| 19099 |
(NewVT.getStoreSizeInBits() != NewBW || |
0 |
19099 |
(NewVT.getStoreSizeInBits() != NewBW || |
0 |
| 19100 |
!TLI.isOperationLegalOrCustom(Opc, NewVT) || |
0 |
19100 |
!TLI.isOperationLegalOrCustom(Opc, NewVT) || |
0 |
| 19101 |
!TLI.isNarrowingProfitable(VT, NewVT))) { |
0 |
19101 |
!TLI.isNarrowingProfitable(VT, NewVT))) { |
0 |
| 19102 |
NewBW = NextPowerOf2(NewBW); |
0 |
19102 |
NewBW = NextPowerOf2(NewBW); |
0 |
| 19103 |
NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); |
0 |
19103 |
NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); |
0 |
| 19104 |
} |
--- |
19104 |
} |
--- |
| 19105 |
if (NewBW >= BitWidth) |
0 |
19105 |
if (NewBW >= BitWidth) |
0 |
| 19106 |
return SDValue(); |
0 |
19106 |
return SDValue(); |
0 |
| 19107 |
|
--- |
19107 |
|
--- |
| 19108 |
// If the lsb changed does not start at the type bitwidth boundary, |
--- |
19108 |
// If the lsb changed does not start at the type bitwidth boundary, |
--- |
| 19109 |
// start at the previous one. |
--- |
19109 |
// start at the previous one. |
--- |
| 19110 |
if (ShAmt % NewBW) |
0 |
19110 |
if (ShAmt % NewBW) |
0 |
| 19111 |
ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; |
0 |
19111 |
ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; |
0 |
| 19112 |
APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, |
--- |
19112 |
APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, |
--- |
| 19113 |
std::min(BitWidth, ShAmt + NewBW)); |
0 |
19113 |
std::min(BitWidth, ShAmt + NewBW)); |
0 |
| 19114 |
if ((Imm & Mask) == Imm) { |
0 |
19114 |
if ((Imm & Mask) == Imm) { |
0 |
| 19115 |
APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); |
0 |
19115 |
APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); |
0 |
| 19116 |
if (Opc == ISD::AND) |
0 |
19116 |
if (Opc == ISD::AND) |
0 |
| 19117 |
NewImm ^= APInt::getAllOnes(NewBW); |
0 |
19117 |
NewImm ^= APInt::getAllOnes(NewBW); |
0 |
| 19118 |
uint64_t PtrOff = ShAmt / 8; |
0 |
19118 |
uint64_t PtrOff = ShAmt / 8; |
0 |
| 19119 |
// For big endian targets, we need to adjust the offset to the pointer to |
--- |
19119 |
// For big endian targets, we need to adjust the offset to the pointer to |
--- |
| 19120 |
// load the correct bytes. |
--- |
19120 |
// load the correct bytes. |
--- |
| 19121 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
19121 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
| 19122 |
PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; |
0 |
19122 |
PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; |
0 |
| 19123 |
|
--- |
19123 |
|
--- |
| 19124 |
unsigned IsFast = 0; |
0 |
19124 |
unsigned IsFast = 0; |
0 |
| 19125 |
Align NewAlign = commonAlignment(LD->getAlign(), PtrOff); |
0 |
19125 |
Align NewAlign = commonAlignment(LD->getAlign(), PtrOff); |
0 |
| 19126 |
if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), NewVT, |
0 |
19126 |
if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), NewVT, |
0 |
| 19127 |
LD->getAddressSpace(), NewAlign, |
--- |
19127 |
LD->getAddressSpace(), NewAlign, |
--- |
| 19128 |
LD->getMemOperand()->getFlags(), &IsFast) || |
0 |
19128 |
LD->getMemOperand()->getFlags(), &IsFast) || |
0 |
| 19129 |
!IsFast) |
0 |
19129 |
!IsFast) |
0 |
| 19130 |
return SDValue(); |
0 |
19130 |
return SDValue(); |
0 |
| 19131 |
|
--- |
19131 |
|
--- |
| 19132 |
SDValue NewPtr = |
--- |
19132 |
SDValue NewPtr = |
--- |
| 19133 |
DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(PtrOff), SDLoc(LD)); |
0 |
19133 |
DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(PtrOff), SDLoc(LD)); |
0 |
| 19134 |
SDValue NewLD = |
--- |
19134 |
SDValue NewLD = |
--- |
| 19135 |
DAG.getLoad(NewVT, SDLoc(N0), LD->getChain(), NewPtr, |
0 |
19135 |
DAG.getLoad(NewVT, SDLoc(N0), LD->getChain(), NewPtr, |
0 |
| 19136 |
LD->getPointerInfo().getWithOffset(PtrOff), NewAlign, |
0 |
19136 |
LD->getPointerInfo().getWithOffset(PtrOff), NewAlign, |
0 |
| 19137 |
LD->getMemOperand()->getFlags(), LD->getAAInfo()); |
0 |
19137 |
LD->getMemOperand()->getFlags(), LD->getAAInfo()); |
0 |
| 19138 |
SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD, |
0 |
19138 |
SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD, |
0 |
| 19139 |
DAG.getConstant(NewImm, SDLoc(Value), |
0 |
19139 |
DAG.getConstant(NewImm, SDLoc(Value), |
0 |
| 19140 |
NewVT)); |
--- |
19140 |
NewVT)); |
--- |
| 19141 |
SDValue NewST = |
--- |
19141 |
SDValue NewST = |
--- |
| 19142 |
DAG.getStore(Chain, SDLoc(N), NewVal, NewPtr, |
0 |
19142 |
DAG.getStore(Chain, SDLoc(N), NewVal, NewPtr, |
0 |
| 19143 |
ST->getPointerInfo().getWithOffset(PtrOff), NewAlign); |
0 |
19143 |
ST->getPointerInfo().getWithOffset(PtrOff), NewAlign); |
0 |
| 19144 |
|
--- |
19144 |
|
--- |
| 19145 |
AddToWorklist(NewPtr.getNode()); |
0 |
19145 |
AddToWorklist(NewPtr.getNode()); |
0 |
| 19146 |
AddToWorklist(NewLD.getNode()); |
0 |
19146 |
AddToWorklist(NewLD.getNode()); |
0 |
| 19147 |
AddToWorklist(NewVal.getNode()); |
0 |
19147 |
AddToWorklist(NewVal.getNode()); |
0 |
| 19148 |
WorklistRemover DeadNodes(*this); |
0 |
19148 |
WorklistRemover DeadNodes(*this); |
0 |
| 19149 |
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); |
0 |
19149 |
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); |
0 |
| 19150 |
++OpsNarrowed; |
0 |
19150 |
++OpsNarrowed; |
0 |
| 19151 |
return NewST; |
0 |
19151 |
return NewST; |
0 |
| 19152 |
} |
0 |
19152 |
} |
0 |
| 19153 |
} |
0 |
19153 |
} |
0 |
| 19154 |
|
--- |
19154 |
|
--- |
| 19155 |
return SDValue(); |
0 |
19155 |
return SDValue(); |
0 |
| 19156 |
} |
--- |
19156 |
} |
--- |
| 19157 |
|
--- |
19157 |
|
--- |
| 19158 |
/// For a given floating point load / store pair, if the load value isn't used |
--- |
19158 |
/// For a given floating point load / store pair, if the load value isn't used |
--- |
| 19159 |
/// by any other operations, then consider transforming the pair to integer |
--- |
19159 |
/// by any other operations, then consider transforming the pair to integer |
--- |
| 19160 |
/// load / store operations if the target deems the transformation profitable. |
--- |
19160 |
/// load / store operations if the target deems the transformation profitable. |
--- |
| 19161 |
SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { |
10 |
19161 |
SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { |
10 |
| 19162 |
StoreSDNode *ST = cast(N); |
10 |
19162 |
StoreSDNode *ST = cast(N); |
10 |
| 19163 |
SDValue Value = ST->getValue(); |
10 |
19163 |
SDValue Value = ST->getValue(); |
10 |
| 19164 |
if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && |
14 |
19164 |
if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && |
14 |
| 19165 |
Value.hasOneUse()) { |
4 |
19165 |
Value.hasOneUse()) { |
4 |
| 19166 |
LoadSDNode *LD = cast(Value); |
4 |
19166 |
LoadSDNode *LD = cast(Value); |
4 |
| 19167 |
EVT VT = LD->getMemoryVT(); |
4 |
19167 |
EVT VT = LD->getMemoryVT(); |
4 |
| 19168 |
if (!VT.isFloatingPoint() || |
4 |
19168 |
if (!VT.isFloatingPoint() || |
4 |
| 19169 |
VT != ST->getMemoryVT() || |
0 |
19169 |
VT != ST->getMemoryVT() || |
0 |
| 19170 |
LD->isNonTemporal() || |
0 |
19170 |
LD->isNonTemporal() || |
0 |
| 19171 |
ST->isNonTemporal() || |
0 |
19171 |
ST->isNonTemporal() || |
0 |
| 19172 |
LD->getPointerInfo().getAddrSpace() != 0 || |
4 |
19172 |
LD->getPointerInfo().getAddrSpace() != 0 || |
4 |
| 19173 |
ST->getPointerInfo().getAddrSpace() != 0) |
0 |
19173 |
ST->getPointerInfo().getAddrSpace() != 0) |
0 |
| 19174 |
return SDValue(); |
4 |
19174 |
return SDValue(); |
4 |
| 19175 |
|
--- |
19175 |
|
--- |
| 19176 |
TypeSize VTSize = VT.getSizeInBits(); |
0 |
19176 |
TypeSize VTSize = VT.getSizeInBits(); |
0 |
| 19177 |
|
--- |
19177 |
|
--- |
| 19178 |
// We don't know the size of scalable types at compile time so we cannot |
--- |
19178 |
// We don't know the size of scalable types at compile time so we cannot |
--- |
| 19179 |
// create an integer of the equivalent size. |
--- |
19179 |
// create an integer of the equivalent size. |
--- |
| 19180 |
if (VTSize.isScalable()) |
0 |
19180 |
if (VTSize.isScalable()) |
0 |
| 19181 |
return SDValue(); |
0 |
19181 |
return SDValue(); |
0 |
| 19182 |
|
--- |
19182 |
|
--- |
| 19183 |
unsigned FastLD = 0, FastST = 0; |
0 |
19183 |
unsigned FastLD = 0, FastST = 0; |
0 |
| 19184 |
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VTSize.getFixedValue()); |
0 |
19184 |
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VTSize.getFixedValue()); |
0 |
| 19185 |
if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || |
0 |
19185 |
if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || |
0 |
| 19186 |
!TLI.isOperationLegal(ISD::STORE, IntVT) || |
0 |
19186 |
!TLI.isOperationLegal(ISD::STORE, IntVT) || |
0 |
| 19187 |
!TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || |
0 |
19187 |
!TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || |
0 |
| 19188 |
!TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT) || |
0 |
19188 |
!TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT) || |
0 |
| 19189 |
!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), IntVT, |
0 |
19189 |
!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), IntVT, |
0 |
| 19190 |
*LD->getMemOperand(), &FastLD) || |
0 |
19190 |
*LD->getMemOperand(), &FastLD) || |
0 |
| 19191 |
!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), IntVT, |
0 |
19191 |
!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), IntVT, |
0 |
| 19192 |
*ST->getMemOperand(), &FastST) || |
0 |
19192 |
*ST->getMemOperand(), &FastST) || |
0 |
| 19193 |
!FastLD || !FastST) |
0 |
19193 |
!FastLD || !FastST) |
0 |
| 19194 |
return SDValue(); |
0 |
19194 |
return SDValue(); |
0 |
| 19195 |
|
--- |
19195 |
|
--- |
| 19196 |
SDValue NewLD = |
--- |
19196 |
SDValue NewLD = |
--- |
| 19197 |
DAG.getLoad(IntVT, SDLoc(Value), LD->getChain(), LD->getBasePtr(), |
0 |
19197 |
DAG.getLoad(IntVT, SDLoc(Value), LD->getChain(), LD->getBasePtr(), |
0 |
| 19198 |
LD->getPointerInfo(), LD->getAlign()); |
0 |
19198 |
LD->getPointerInfo(), LD->getAlign()); |
0 |
| 19199 |
|
--- |
19199 |
|
--- |
| 19200 |
SDValue NewST = |
--- |
19200 |
SDValue NewST = |
--- |
| 19201 |
DAG.getStore(ST->getChain(), SDLoc(N), NewLD, ST->getBasePtr(), |
0 |
19201 |
DAG.getStore(ST->getChain(), SDLoc(N), NewLD, ST->getBasePtr(), |
0 |
| 19202 |
ST->getPointerInfo(), ST->getAlign()); |
0 |
19202 |
ST->getPointerInfo(), ST->getAlign()); |
0 |
| 19203 |
|
--- |
19203 |
|
--- |
| 19204 |
AddToWorklist(NewLD.getNode()); |
0 |
19204 |
AddToWorklist(NewLD.getNode()); |
0 |
| 19205 |
AddToWorklist(NewST.getNode()); |
0 |
19205 |
AddToWorklist(NewST.getNode()); |
0 |
| 19206 |
WorklistRemover DeadNodes(*this); |
0 |
19206 |
WorklistRemover DeadNodes(*this); |
0 |
| 19207 |
DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); |
0 |
19207 |
DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); |
0 |
| 19208 |
++LdStFP2Int; |
0 |
19208 |
++LdStFP2Int; |
0 |
| 19209 |
return NewST; |
0 |
19209 |
return NewST; |
0 |
| 19210 |
} |
0 |
19210 |
} |
0 |
| 19211 |
|
--- |
19211 |
|
--- |
| 19212 |
return SDValue(); |
6 |
19212 |
return SDValue(); |
6 |
| 19213 |
} |
--- |
19213 |
} |
--- |
| 19214 |
|
--- |
19214 |
|
--- |
| 19215 |
// This is a helper function for visitMUL to check the profitability |
--- |
19215 |
// This is a helper function for visitMUL to check the profitability |
--- |
| 19216 |
// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2). |
--- |
19216 |
// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2). |
--- |
| 19217 |
// MulNode is the original multiply, AddNode is (add x, c1), |
--- |
19217 |
// MulNode is the original multiply, AddNode is (add x, c1), |
--- |
| 19218 |
// and ConstNode is c2. |
--- |
19218 |
// and ConstNode is c2. |
--- |
| 19219 |
// |
--- |
19219 |
// |
--- |
| 19220 |
// If the (add x, c1) has multiple uses, we could increase |
--- |
19220 |
// If the (add x, c1) has multiple uses, we could increase |
--- |
| 19221 |
// the number of adds if we make this transformation. |
--- |
19221 |
// the number of adds if we make this transformation. |
--- |
| 19222 |
// It would only be worth doing this if we can remove a |
--- |
19222 |
// It would only be worth doing this if we can remove a |
--- |
| 19223 |
// multiply in the process. Check for that here. |
--- |
19223 |
// multiply in the process. Check for that here. |
--- |
| 19224 |
// To illustrate: |
--- |
19224 |
// To illustrate: |
--- |
| 19225 |
// (A + c1) * c3 |
--- |
19225 |
// (A + c1) * c3 |
--- |
| 19226 |
// (A + c2) * c3 |
--- |
19226 |
// (A + c2) * c3 |
--- |
| 19227 |
// We're checking for cases where we have common "c3 * A" expressions. |
--- |
19227 |
// We're checking for cases where we have common "c3 * A" expressions. |
--- |
| 19228 |
bool DAGCombiner::isMulAddWithConstProfitable(SDNode *MulNode, SDValue AddNode, |
0 |
19228 |
bool DAGCombiner::isMulAddWithConstProfitable(SDNode *MulNode, SDValue AddNode, |
0 |
| 19229 |
SDValue ConstNode) { |
--- |
19229 |
SDValue ConstNode) { |
--- |
| 19230 |
APInt Val; |
0 |
19230 |
APInt Val; |
0 |
| 19231 |
|
--- |
19231 |
|
--- |
| 19232 |
// If the add only has one use, and the target thinks the folding is |
--- |
19232 |
// If the add only has one use, and the target thinks the folding is |
--- |
| 19233 |
// profitable or does not lead to worse code, this would be OK to do. |
--- |
19233 |
// profitable or does not lead to worse code, this would be OK to do. |
--- |
| 19234 |
if (AddNode->hasOneUse() && |
0 |
19234 |
if (AddNode->hasOneUse() && |
0 |
| 19235 |
TLI.isMulAddWithConstProfitable(AddNode, ConstNode)) |
0 |
19235 |
TLI.isMulAddWithConstProfitable(AddNode, ConstNode)) |
0 |
| 19236 |
return true; |
0 |
19236 |
return true; |
0 |
| 19237 |
|
--- |
19237 |
|
--- |
| 19238 |
// Walk all the users of the constant with which we're multiplying. |
--- |
19238 |
// Walk all the users of the constant with which we're multiplying. |
--- |
| 19239 |
for (SDNode *Use : ConstNode->uses()) { |
0 |
19239 |
for (SDNode *Use : ConstNode->uses()) { |
0 |
| 19240 |
if (Use == MulNode) // This use is the one we're on right now. Skip it. |
0 |
19240 |
if (Use == MulNode) // This use is the one we're on right now. Skip it. |
0 |
| 19241 |
continue; |
0 |
19241 |
continue; |
0 |
| 19242 |
|
--- |
19242 |
|
--- |
| 19243 |
if (Use->getOpcode() == ISD::MUL) { // We have another multiply use. |
0 |
19243 |
if (Use->getOpcode() == ISD::MUL) { // We have another multiply use. |
0 |
| 19244 |
SDNode *OtherOp; |
--- |
19244 |
SDNode *OtherOp; |
--- |
| 19245 |
SDNode *MulVar = AddNode.getOperand(0).getNode(); |
0 |
19245 |
SDNode *MulVar = AddNode.getOperand(0).getNode(); |
0 |
| 19246 |
|
--- |
19246 |
|
--- |
| 19247 |
// OtherOp is what we're multiplying against the constant. |
--- |
19247 |
// OtherOp is what we're multiplying against the constant. |
--- |
| 19248 |
if (Use->getOperand(0) == ConstNode) |
0 |
19248 |
if (Use->getOperand(0) == ConstNode) |
0 |
| 19249 |
OtherOp = Use->getOperand(1).getNode(); |
0 |
19249 |
OtherOp = Use->getOperand(1).getNode(); |
0 |
| 19250 |
else |
--- |
19250 |
else |
--- |
| 19251 |
OtherOp = Use->getOperand(0).getNode(); |
0 |
19251 |
OtherOp = Use->getOperand(0).getNode(); |
0 |
| 19252 |
|
--- |
19252 |
|
--- |
| 19253 |
// Check to see if multiply is with the same operand of our "add". |
--- |
19253 |
// Check to see if multiply is with the same operand of our "add". |
--- |
| 19254 |
// |
--- |
19254 |
// |
--- |
| 19255 |
// ConstNode = CONST |
--- |
19255 |
// ConstNode = CONST |
--- |
| 19256 |
// Use = ConstNode * A <-- visiting Use. OtherOp is A. |
--- |
19256 |
// Use = ConstNode * A <-- visiting Use. OtherOp is A. |
--- |
| 19257 |
// ... |
--- |
19257 |
// ... |
--- |
| 19258 |
// AddNode = (A + c1) <-- MulVar is A. |
--- |
19258 |
// AddNode = (A + c1) <-- MulVar is A. |
--- |
| 19259 |
// = AddNode * ConstNode <-- current visiting instruction. |
--- |
19259 |
// = AddNode * ConstNode <-- current visiting instruction. |
--- |
| 19260 |
// |
--- |
19260 |
// |
--- |
| 19261 |
// If we make this transformation, we will have a common |
--- |
19261 |
// If we make this transformation, we will have a common |
--- |
| 19262 |
// multiply (ConstNode * A) that we can save. |
--- |
19262 |
// multiply (ConstNode * A) that we can save. |
--- |
| 19263 |
if (OtherOp == MulVar) |
0 |
19263 |
if (OtherOp == MulVar) |
0 |
| 19264 |
return true; |
0 |
19264 |
return true; |
0 |
| 19265 |
|
--- |
19265 |
|
--- |
| 19266 |
// Now check to see if a future expansion will give us a common |
--- |
19266 |
// Now check to see if a future expansion will give us a common |
--- |
| 19267 |
// multiply. |
--- |
19267 |
// multiply. |
--- |
| 19268 |
// |
--- |
19268 |
// |
--- |
| 19269 |
// ConstNode = CONST |
--- |
19269 |
// ConstNode = CONST |
--- |
| 19270 |
// AddNode = (A + c1) |
--- |
19270 |
// AddNode = (A + c1) |
--- |
| 19271 |
// ... = AddNode * ConstNode <-- current visiting instruction. |
--- |
19271 |
// ... = AddNode * ConstNode <-- current visiting instruction. |
--- |
| 19272 |
// ... |
--- |
19272 |
// ... |
--- |
| 19273 |
// OtherOp = (A + c2) |
--- |
19273 |
// OtherOp = (A + c2) |
--- |
| 19274 |
// Use = OtherOp * ConstNode <-- visiting Use. |
--- |
19274 |
// Use = OtherOp * ConstNode <-- visiting Use. |
--- |
| 19275 |
// |
--- |
19275 |
// |
--- |
| 19276 |
// If we make this transformation, we will have a common |
--- |
19276 |
// If we make this transformation, we will have a common |
--- |
| 19277 |
// multiply (CONST * A) after we also do the same transformation |
--- |
19277 |
// multiply (CONST * A) after we also do the same transformation |
--- |
| 19278 |
// to the "t2" instruction. |
--- |
19278 |
// to the "t2" instruction. |
--- |
| 19279 |
if (OtherOp->getOpcode() == ISD::ADD && |
0 |
19279 |
if (OtherOp->getOpcode() == ISD::ADD && |
0 |
| 19280 |
DAG.isConstantIntBuildVectorOrConstantInt(OtherOp->getOperand(1)) && |
0 |
19280 |
DAG.isConstantIntBuildVectorOrConstantInt(OtherOp->getOperand(1)) && |
0 |
| 19281 |
OtherOp->getOperand(0).getNode() == MulVar) |
0 |
19281 |
OtherOp->getOperand(0).getNode() == MulVar) |
0 |
| 19282 |
return true; |
0 |
19282 |
return true; |
0 |
| 19283 |
} |
--- |
19283 |
} |
--- |
| 19284 |
} |
--- |
19284 |
} |
--- |
| 19285 |
|
--- |
19285 |
|
--- |
| 19286 |
// Didn't find a case where this would be profitable. |
--- |
19286 |
// Didn't find a case where this would be profitable. |
--- |
| 19287 |
return false; |
0 |
19287 |
return false; |
0 |
| 19288 |
} |
0 |
19288 |
} |
0 |
| 19289 |
|
--- |
19289 |
|
--- |
| 19290 |
SDValue DAGCombiner::getMergeStoreChains(SmallVectorImpl &StoreNodes, |
0 |
19290 |
SDValue DAGCombiner::getMergeStoreChains(SmallVectorImpl &StoreNodes, |
0 |
| 19291 |
unsigned NumStores) { |
--- |
19291 |
unsigned NumStores) { |
--- |
| 19292 |
SmallVector Chains; |
0 |
19292 |
SmallVector Chains; |
0 |
| 19293 |
SmallPtrSet Visited; |
0 |
19293 |
SmallPtrSet Visited; |
0 |
| 19294 |
SDLoc StoreDL(StoreNodes[0].MemNode); |
0 |
19294 |
SDLoc StoreDL(StoreNodes[0].MemNode); |
0 |
| 19295 |
|
--- |
19295 |
|
--- |
| 19296 |
for (unsigned i = 0; i < NumStores; ++i) { |
0 |
19296 |
for (unsigned i = 0; i < NumStores; ++i) { |
0 |
| 19297 |
Visited.insert(StoreNodes[i].MemNode); |
0 |
19297 |
Visited.insert(StoreNodes[i].MemNode); |
0 |
| 19298 |
} |
--- |
19298 |
} |
--- |
| 19299 |
|
--- |
19299 |
|
--- |
| 19300 |
// don't include nodes that are children or repeated nodes. |
--- |
19300 |
// don't include nodes that are children or repeated nodes. |
--- |
| 19301 |
for (unsigned i = 0; i < NumStores; ++i) { |
0 |
19301 |
for (unsigned i = 0; i < NumStores; ++i) { |
0 |
| 19302 |
if (Visited.insert(StoreNodes[i].MemNode->getChain().getNode()).second) |
0 |
19302 |
if (Visited.insert(StoreNodes[i].MemNode->getChain().getNode()).second) |
0 |
| 19303 |
Chains.push_back(StoreNodes[i].MemNode->getChain()); |
0 |
19303 |
Chains.push_back(StoreNodes[i].MemNode->getChain()); |
0 |
| 19304 |
} |
--- |
19304 |
} |
--- |
| 19305 |
|
--- |
19305 |
|
--- |
| 19306 |
assert(Chains.size() > 0 && "Chain should have generated a chain"); |
0 |
19306 |
assert(Chains.size() > 0 && "Chain should have generated a chain"); |
0 |
| 19307 |
return DAG.getTokenFactor(StoreDL, Chains); |
0 |
19307 |
return DAG.getTokenFactor(StoreDL, Chains); |
0 |
| 19308 |
} |
0 |
19308 |
} |
0 |
| 19309 |
|
--- |
19309 |
|
--- |
| 19310 |
bool DAGCombiner::hasSameUnderlyingObj(ArrayRef StoreNodes) { |
0 |
19310 |
bool DAGCombiner::hasSameUnderlyingObj(ArrayRef StoreNodes) { |
0 |
| 19311 |
const Value *UnderlyingObj = nullptr; |
0 |
19311 |
const Value *UnderlyingObj = nullptr; |
0 |
| 19312 |
for (const auto &MemOp : StoreNodes) { |
0 |
19312 |
for (const auto &MemOp : StoreNodes) { |
0 |
| 19313 |
const MachineMemOperand *MMO = MemOp.MemNode->getMemOperand(); |
0 |
19313 |
const MachineMemOperand *MMO = MemOp.MemNode->getMemOperand(); |
0 |
| 19314 |
// Pseudo value like stack frame has its own frame index and size, should |
--- |
19314 |
// Pseudo value like stack frame has its own frame index and size, should |
--- |
| 19315 |
// not use the first store's frame index for other frames. |
--- |
19315 |
// not use the first store's frame index for other frames. |
--- |
| 19316 |
if (MMO->getPseudoValue()) |
0 |
19316 |
if (MMO->getPseudoValue()) |
0 |
| 19317 |
return false; |
0 |
19317 |
return false; |
0 |
| 19318 |
|
--- |
19318 |
|
--- |
| 19319 |
if (!MMO->getValue()) |
0 |
19319 |
if (!MMO->getValue()) |
0 |
| 19320 |
return false; |
0 |
19320 |
return false; |
0 |
| 19321 |
|
--- |
19321 |
|
--- |
| 19322 |
const Value *Obj = getUnderlyingObject(MMO->getValue()); |
0 |
19322 |
const Value *Obj = getUnderlyingObject(MMO->getValue()); |
0 |
| 19323 |
|
--- |
19323 |
|
--- |
| 19324 |
if (UnderlyingObj && UnderlyingObj != Obj) |
0 |
19324 |
if (UnderlyingObj && UnderlyingObj != Obj) |
0 |
| 19325 |
return false; |
0 |
19325 |
return false; |
0 |
| 19326 |
|
--- |
19326 |
|
--- |
| 19327 |
if (!UnderlyingObj) |
0 |
19327 |
if (!UnderlyingObj) |
0 |
| 19328 |
UnderlyingObj = Obj; |
0 |
19328 |
UnderlyingObj = Obj; |
0 |
| 19329 |
} |
--- |
19329 |
} |
--- |
| 19330 |
|
--- |
19330 |
|
--- |
| 19331 |
return true; |
0 |
19331 |
return true; |
0 |
| 19332 |
} |
--- |
19332 |
} |
--- |
| 19333 |
|
--- |
19333 |
|
--- |
| 19334 |
bool DAGCombiner::mergeStoresOfConstantsOrVecElts( |
0 |
19334 |
bool DAGCombiner::mergeStoresOfConstantsOrVecElts( |
0 |
| 19335 |
SmallVectorImpl &StoreNodes, EVT MemVT, unsigned NumStores, |
--- |
19335 |
SmallVectorImpl &StoreNodes, EVT MemVT, unsigned NumStores, |
--- |
| 19336 |
bool IsConstantSrc, bool UseVector, bool UseTrunc) { |
--- |
19336 |
bool IsConstantSrc, bool UseVector, bool UseTrunc) { |
--- |
| 19337 |
// Make sure we have something to merge. |
--- |
19337 |
// Make sure we have something to merge. |
--- |
| 19338 |
if (NumStores < 2) |
0 |
19338 |
if (NumStores < 2) |
0 |
| 19339 |
return false; |
0 |
19339 |
return false; |
0 |
| 19340 |
|
--- |
19340 |
|
--- |
| 19341 |
assert((!UseTrunc || !UseVector) && |
0 |
19341 |
assert((!UseTrunc || !UseVector) && |
0 |
| 19342 |
"This optimization cannot emit a vector truncating store"); |
--- |
19342 |
"This optimization cannot emit a vector truncating store"); |
--- |
| 19343 |
|
--- |
19343 |
|
--- |
| 19344 |
// The latest Node in the DAG. |
--- |
19344 |
// The latest Node in the DAG. |
--- |
| 19345 |
SDLoc DL(StoreNodes[0].MemNode); |
0 |
19345 |
SDLoc DL(StoreNodes[0].MemNode); |
0 |
| 19346 |
|
--- |
19346 |
|
--- |
| 19347 |
TypeSize ElementSizeBits = MemVT.getStoreSizeInBits(); |
0 |
19347 |
TypeSize ElementSizeBits = MemVT.getStoreSizeInBits(); |
0 |
| 19348 |
unsigned SizeInBits = NumStores * ElementSizeBits; |
0 |
19348 |
unsigned SizeInBits = NumStores * ElementSizeBits; |
0 |
| 19349 |
unsigned NumMemElts = MemVT.isVector() ? MemVT.getVectorNumElements() : 1; |
0 |
19349 |
unsigned NumMemElts = MemVT.isVector() ? MemVT.getVectorNumElements() : 1; |
0 |
| 19350 |
|
--- |
19350 |
|
--- |
| 19351 |
std::optional Flags; |
0 |
19351 |
std::optional Flags; |
0 |
| 19352 |
AAMDNodes AAInfo; |
0 |
19352 |
AAMDNodes AAInfo; |
0 |
| 19353 |
for (unsigned I = 0; I != NumStores; ++I) { |
0 |
19353 |
for (unsigned I = 0; I != NumStores; ++I) { |
0 |
| 19354 |
StoreSDNode *St = cast(StoreNodes[I].MemNode); |
0 |
19354 |
StoreSDNode *St = cast(StoreNodes[I].MemNode); |
0 |
| 19355 |
if (!Flags) { |
0 |
19355 |
if (!Flags) { |
0 |
| 19356 |
Flags = St->getMemOperand()->getFlags(); |
0 |
19356 |
Flags = St->getMemOperand()->getFlags(); |
0 |
| 19357 |
AAInfo = St->getAAInfo(); |
0 |
19357 |
AAInfo = St->getAAInfo(); |
0 |
| 19358 |
continue; |
0 |
19358 |
continue; |
0 |
| 19359 |
} |
--- |
19359 |
} |
--- |
| 19360 |
// Skip merging if there's an inconsistent flag. |
--- |
19360 |
// Skip merging if there's an inconsistent flag. |
--- |
| 19361 |
if (Flags != St->getMemOperand()->getFlags()) |
0 |
19361 |
if (Flags != St->getMemOperand()->getFlags()) |
0 |
| 19362 |
return false; |
0 |
19362 |
return false; |
0 |
| 19363 |
// Concatenate AA metadata. |
--- |
19363 |
// Concatenate AA metadata. |
--- |
| 19364 |
AAInfo = AAInfo.concat(St->getAAInfo()); |
0 |
19364 |
AAInfo = AAInfo.concat(St->getAAInfo()); |
0 |
| 19365 |
} |
--- |
19365 |
} |
--- |
| 19366 |
|
--- |
19366 |
|
--- |
| 19367 |
EVT StoreTy; |
0 |
19367 |
EVT StoreTy; |
0 |
| 19368 |
if (UseVector) { |
0 |
19368 |
if (UseVector) { |
0 |
| 19369 |
unsigned Elts = NumStores * NumMemElts; |
0 |
19369 |
unsigned Elts = NumStores * NumMemElts; |
0 |
| 19370 |
// Get the type for the merged vector store. |
--- |
19370 |
// Get the type for the merged vector store. |
--- |
| 19371 |
StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), Elts); |
0 |
19371 |
StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), Elts); |
0 |
| 19372 |
} else |
--- |
19372 |
} else |
--- |
| 19373 |
StoreTy = EVT::getIntegerVT(*DAG.getContext(), SizeInBits); |
0 |
19373 |
StoreTy = EVT::getIntegerVT(*DAG.getContext(), SizeInBits); |
0 |
| 19374 |
|
--- |
19374 |
|
--- |
| 19375 |
SDValue StoredVal; |
0 |
19375 |
SDValue StoredVal; |
0 |
| 19376 |
if (UseVector) { |
0 |
19376 |
if (UseVector) { |
0 |
| 19377 |
if (IsConstantSrc) { |
0 |
19377 |
if (IsConstantSrc) { |
0 |
| 19378 |
SmallVector BuildVector; |
0 |
19378 |
SmallVector BuildVector; |
0 |
| 19379 |
for (unsigned I = 0; I != NumStores; ++I) { |
0 |
19379 |
for (unsigned I = 0; I != NumStores; ++I) { |
0 |
| 19380 |
StoreSDNode *St = cast(StoreNodes[I].MemNode); |
0 |
19380 |
StoreSDNode *St = cast(StoreNodes[I].MemNode); |
0 |
| 19381 |
SDValue Val = St->getValue(); |
0 |
19381 |
SDValue Val = St->getValue(); |
0 |
| 19382 |
// If constant is of the wrong type, convert it now. |
--- |
19382 |
// If constant is of the wrong type, convert it now. |
--- |
| 19383 |
if (MemVT != Val.getValueType()) { |
0 |
19383 |
if (MemVT != Val.getValueType()) { |
0 |
| 19384 |
Val = peekThroughBitcasts(Val); |
0 |
19384 |
Val = peekThroughBitcasts(Val); |
0 |
| 19385 |
// Deal with constants of wrong size. |
--- |
19385 |
// Deal with constants of wrong size. |
--- |
| 19386 |
if (ElementSizeBits != Val.getValueSizeInBits()) { |
0 |
19386 |
if (ElementSizeBits != Val.getValueSizeInBits()) { |
0 |
| 19387 |
EVT IntMemVT = |
--- |
19387 |
EVT IntMemVT = |
--- |
| 19388 |
EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits()); |
0 |
19388 |
EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits()); |
0 |
| 19389 |
if (isa(Val)) { |
0 |
19389 |
if (isa(Val)) { |
0 |
| 19390 |
// Not clear how to truncate FP values. |
--- |
19390 |
// Not clear how to truncate FP values. |
--- |
| 19391 |
return false; |
0 |
19391 |
return false; |
0 |
| 19392 |
} |
--- |
19392 |
} |
--- |
| 19393 |
|
--- |
19393 |
|
--- |
| 19394 |
if (auto *C = dyn_cast(Val)) |
0 |
19394 |
if (auto *C = dyn_cast(Val)) |
0 |
| 19395 |
Val = DAG.getConstant(C->getAPIntValue() |
0 |
19395 |
Val = DAG.getConstant(C->getAPIntValue() |
0 |
| 19396 |
.zextOrTrunc(Val.getValueSizeInBits()) |
0 |
19396 |
.zextOrTrunc(Val.getValueSizeInBits()) |
0 |
| 19397 |
.zextOrTrunc(ElementSizeBits), |
0 |
19397 |
.zextOrTrunc(ElementSizeBits), |
0 |
| 19398 |
SDLoc(C), IntMemVT); |
0 |
19398 |
SDLoc(C), IntMemVT); |
0 |
| 19399 |
} |
--- |
19399 |
} |
--- |
| 19400 |
// Make sure correctly size type is the correct type. |
--- |
19400 |
// Make sure correctly size type is the correct type. |
--- |
| 19401 |
Val = DAG.getBitcast(MemVT, Val); |
0 |
19401 |
Val = DAG.getBitcast(MemVT, Val); |
0 |
| 19402 |
} |
--- |
19402 |
} |
--- |
| 19403 |
BuildVector.push_back(Val); |
0 |
19403 |
BuildVector.push_back(Val); |
0 |
| 19404 |
} |
--- |
19404 |
} |
--- |
| 19405 |
StoredVal = DAG.getNode(MemVT.isVector() ? ISD::CONCAT_VECTORS |
0 |
19405 |
StoredVal = DAG.getNode(MemVT.isVector() ? ISD::CONCAT_VECTORS |
0 |
| 19406 |
: ISD::BUILD_VECTOR, |
--- |
19406 |
: ISD::BUILD_VECTOR, |
--- |
| 19407 |
DL, StoreTy, BuildVector); |
--- |
19407 |
DL, StoreTy, BuildVector); |
--- |
| 19408 |
} else { |
0 |
19408 |
} else { |
0 |
| 19409 |
SmallVector Ops; |
0 |
19409 |
SmallVector Ops; |
0 |
| 19410 |
for (unsigned i = 0; i < NumStores; ++i) { |
0 |
19410 |
for (unsigned i = 0; i < NumStores; ++i) { |
0 |
| 19411 |
StoreSDNode *St = cast(StoreNodes[i].MemNode); |
0 |
19411 |
StoreSDNode *St = cast(StoreNodes[i].MemNode); |
0 |
| 19412 |
SDValue Val = peekThroughBitcasts(St->getValue()); |
0 |
19412 |
SDValue Val = peekThroughBitcasts(St->getValue()); |
0 |
| 19413 |
// All operands of BUILD_VECTOR / CONCAT_VECTOR must be of |
--- |
19413 |
// All operands of BUILD_VECTOR / CONCAT_VECTOR must be of |
--- |
| 19414 |
// type MemVT. If the underlying value is not the correct |
--- |
19414 |
// type MemVT. If the underlying value is not the correct |
--- |
| 19415 |
// type, but it is an extraction of an appropriate vector we |
--- |
19415 |
// type, but it is an extraction of an appropriate vector we |
--- |
| 19416 |
// can recast Val to be of the correct type. This may require |
--- |
19416 |
// can recast Val to be of the correct type. This may require |
--- |
| 19417 |
// converting between EXTRACT_VECTOR_ELT and |
--- |
19417 |
// converting between EXTRACT_VECTOR_ELT and |
--- |
| 19418 |
// EXTRACT_SUBVECTOR. |
--- |
19418 |
// EXTRACT_SUBVECTOR. |
--- |
| 19419 |
if ((MemVT != Val.getValueType()) && |
0 |
19419 |
if ((MemVT != Val.getValueType()) && |
0 |
| 19420 |
(Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || |
0 |
19420 |
(Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || |
0 |
| 19421 |
Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { |
0 |
19421 |
Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { |
0 |
| 19422 |
EVT MemVTScalarTy = MemVT.getScalarType(); |
0 |
19422 |
EVT MemVTScalarTy = MemVT.getScalarType(); |
0 |
| 19423 |
// We may need to add a bitcast here to get types to line up. |
--- |
19423 |
// We may need to add a bitcast here to get types to line up. |
--- |
| 19424 |
if (MemVTScalarTy != Val.getValueType().getScalarType()) { |
0 |
19424 |
if (MemVTScalarTy != Val.getValueType().getScalarType()) { |
0 |
| 19425 |
Val = DAG.getBitcast(MemVT, Val); |
0 |
19425 |
Val = DAG.getBitcast(MemVT, Val); |
0 |
| 19426 |
} else if (MemVT.isVector() && |
0 |
19426 |
} else if (MemVT.isVector() && |
0 |
| 19427 |
Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { |
0 |
19427 |
Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { |
0 |
| 19428 |
Val = DAG.getNode(ISD::BUILD_VECTOR, DL, MemVT, Val); |
0 |
19428 |
Val = DAG.getNode(ISD::BUILD_VECTOR, DL, MemVT, Val); |
0 |
| 19429 |
} else { |
--- |
19429 |
} else { |
--- |
| 19430 |
unsigned OpC = MemVT.isVector() ? ISD::EXTRACT_SUBVECTOR |
0 |
19430 |
unsigned OpC = MemVT.isVector() ? ISD::EXTRACT_SUBVECTOR |
0 |
| 19431 |
: ISD::EXTRACT_VECTOR_ELT; |
0 |
19431 |
: ISD::EXTRACT_VECTOR_ELT; |
0 |
| 19432 |
SDValue Vec = Val.getOperand(0); |
0 |
19432 |
SDValue Vec = Val.getOperand(0); |
0 |
| 19433 |
SDValue Idx = Val.getOperand(1); |
0 |
19433 |
SDValue Idx = Val.getOperand(1); |
0 |
| 19434 |
Val = DAG.getNode(OpC, SDLoc(Val), MemVT, Vec, Idx); |
0 |
19434 |
Val = DAG.getNode(OpC, SDLoc(Val), MemVT, Vec, Idx); |
0 |
| 19435 |
} |
--- |
19435 |
} |
--- |
| 19436 |
} |
--- |
19436 |
} |
--- |
| 19437 |
Ops.push_back(Val); |
0 |
19437 |
Ops.push_back(Val); |
0 |
| 19438 |
} |
--- |
19438 |
} |
--- |
| 19439 |
|
--- |
19439 |
|
--- |
| 19440 |
// Build the extracted vector elements back into a vector. |
--- |
19440 |
// Build the extracted vector elements back into a vector. |
--- |
| 19441 |
StoredVal = DAG.getNode(MemVT.isVector() ? ISD::CONCAT_VECTORS |
0 |
19441 |
StoredVal = DAG.getNode(MemVT.isVector() ? ISD::CONCAT_VECTORS |
0 |
| 19442 |
: ISD::BUILD_VECTOR, |
--- |
19442 |
: ISD::BUILD_VECTOR, |
--- |
| 19443 |
DL, StoreTy, Ops); |
--- |
19443 |
DL, StoreTy, Ops); |
--- |
| 19444 |
} |
0 |
19444 |
} |
0 |
| 19445 |
} else { |
--- |
19445 |
} else { |
--- |
| 19446 |
// We should always use a vector store when merging extracted vector |
--- |
19446 |
// We should always use a vector store when merging extracted vector |
--- |
| 19447 |
// elements, so this path implies a store of constants. |
--- |
19447 |
// elements, so this path implies a store of constants. |
--- |
| 19448 |
assert(IsConstantSrc && "Merged vector elements should use vector store"); |
0 |
19448 |
assert(IsConstantSrc && "Merged vector elements should use vector store"); |
0 |
| 19449 |
|
--- |
19449 |
|
--- |
| 19450 |
APInt StoreInt(SizeInBits, 0); |
0 |
19450 |
APInt StoreInt(SizeInBits, 0); |
0 |
| 19451 |
|
--- |
19451 |
|
--- |
| 19452 |
// Construct a single integer constant which is made of the smaller |
--- |
19452 |
// Construct a single integer constant which is made of the smaller |
--- |
| 19453 |
// constant inputs. |
--- |
19453 |
// constant inputs. |
--- |
| 19454 |
bool IsLE = DAG.getDataLayout().isLittleEndian(); |
0 |
19454 |
bool IsLE = DAG.getDataLayout().isLittleEndian(); |
0 |
| 19455 |
for (unsigned i = 0; i < NumStores; ++i) { |
0 |
19455 |
for (unsigned i = 0; i < NumStores; ++i) { |
0 |
| 19456 |
unsigned Idx = IsLE ? (NumStores - 1 - i) : i; |
0 |
19456 |
unsigned Idx = IsLE ? (NumStores - 1 - i) : i; |
0 |
| 19457 |
StoreSDNode *St = cast(StoreNodes[Idx].MemNode); |
0 |
19457 |
StoreSDNode *St = cast(StoreNodes[Idx].MemNode); |
0 |
| 19458 |
|
--- |
19458 |
|
--- |
| 19459 |
SDValue Val = St->getValue(); |
0 |
19459 |
SDValue Val = St->getValue(); |
0 |
| 19460 |
Val = peekThroughBitcasts(Val); |
0 |
19460 |
Val = peekThroughBitcasts(Val); |
0 |
| 19461 |
StoreInt <<= ElementSizeBits; |
0 |
19461 |
StoreInt <<= ElementSizeBits; |
0 |
| 19462 |
if (ConstantSDNode *C = dyn_cast(Val)) { |
0 |
19462 |
if (ConstantSDNode *C = dyn_cast(Val)) { |
0 |
| 19463 |
StoreInt |= C->getAPIntValue() |
0 |
19463 |
StoreInt |= C->getAPIntValue() |
0 |
| 19464 |
.zextOrTrunc(ElementSizeBits) |
0 |
19464 |
.zextOrTrunc(ElementSizeBits) |
0 |
| 19465 |
.zextOrTrunc(SizeInBits); |
0 |
19465 |
.zextOrTrunc(SizeInBits); |
0 |
| 19466 |
} else if (ConstantFPSDNode *C = dyn_cast(Val)) { |
0 |
19466 |
} else if (ConstantFPSDNode *C = dyn_cast(Val)) { |
0 |
| 19467 |
StoreInt |= C->getValueAPF() |
0 |
19467 |
StoreInt |= C->getValueAPF() |
0 |
| 19468 |
.bitcastToAPInt() |
0 |
19468 |
.bitcastToAPInt() |
0 |
| 19469 |
.zextOrTrunc(ElementSizeBits) |
0 |
19469 |
.zextOrTrunc(ElementSizeBits) |
0 |
| 19470 |
.zextOrTrunc(SizeInBits); |
0 |
19470 |
.zextOrTrunc(SizeInBits); |
0 |
| 19471 |
// If fp truncation is necessary give up for now. |
--- |
19471 |
// If fp truncation is necessary give up for now. |
--- |
| 19472 |
if (MemVT.getSizeInBits() != ElementSizeBits) |
0 |
19472 |
if (MemVT.getSizeInBits() != ElementSizeBits) |
0 |
| 19473 |
return false; |
0 |
19473 |
return false; |
0 |
| 19474 |
} else { |
--- |
19474 |
} else { |
--- |
| 19475 |
llvm_unreachable("Invalid constant element type"); |
0 |
19475 |
llvm_unreachable("Invalid constant element type"); |
0 |
| 19476 |
} |
--- |
19476 |
} |
--- |
| 19477 |
} |
--- |
19477 |
} |
--- |
| 19478 |
|
--- |
19478 |
|
--- |
| 19479 |
// Create the new Load and Store operations. |
--- |
19479 |
// Create the new Load and Store operations. |
--- |
| 19480 |
StoredVal = DAG.getConstant(StoreInt, DL, StoreTy); |
0 |
19480 |
StoredVal = DAG.getConstant(StoreInt, DL, StoreTy); |
0 |
| 19481 |
} |
0 |
19481 |
} |
0 |
| 19482 |
|
--- |
19482 |
|
--- |
| 19483 |
LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; |
0 |
19483 |
LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; |
0 |
| 19484 |
SDValue NewChain = getMergeStoreChains(StoreNodes, NumStores); |
0 |
19484 |
SDValue NewChain = getMergeStoreChains(StoreNodes, NumStores); |
0 |
| 19485 |
bool CanReusePtrInfo = hasSameUnderlyingObj(StoreNodes); |
0 |
19485 |
bool CanReusePtrInfo = hasSameUnderlyingObj(StoreNodes); |
0 |
| 19486 |
|
--- |
19486 |
|
--- |
| 19487 |
// make sure we use trunc store if it's necessary to be legal. |
--- |
19487 |
// make sure we use trunc store if it's necessary to be legal. |
--- |
| 19488 |
// When generate the new widen store, if the first store's pointer info can |
--- |
19488 |
// When generate the new widen store, if the first store's pointer info can |
--- |
| 19489 |
// not be reused, discard the pointer info except the address space because |
--- |
19489 |
// not be reused, discard the pointer info except the address space because |
--- |
| 19490 |
// now the widen store can not be represented by the original pointer info |
--- |
19490 |
// now the widen store can not be represented by the original pointer info |
--- |
| 19491 |
// which is for the narrow memory object. |
--- |
19491 |
// which is for the narrow memory object. |
--- |
| 19492 |
SDValue NewStore; |
0 |
19492 |
SDValue NewStore; |
0 |
| 19493 |
if (!UseTrunc) { |
0 |
19493 |
if (!UseTrunc) { |
0 |
| 19494 |
NewStore = DAG.getStore( |
0 |
19494 |
NewStore = DAG.getStore( |
0 |
| 19495 |
NewChain, DL, StoredVal, FirstInChain->getBasePtr(), |
0 |
19495 |
NewChain, DL, StoredVal, FirstInChain->getBasePtr(), |
0 |
| 19496 |
CanReusePtrInfo |
--- |
19496 |
CanReusePtrInfo |
--- |
| 19497 |
? FirstInChain->getPointerInfo() |
0 |
19497 |
? FirstInChain->getPointerInfo() |
0 |
| 19498 |
: MachinePointerInfo(FirstInChain->getPointerInfo().getAddrSpace()), |
0 |
19498 |
: MachinePointerInfo(FirstInChain->getPointerInfo().getAddrSpace()), |
0 |
| 19499 |
FirstInChain->getAlign(), *Flags, AAInfo); |
0 |
19499 |
FirstInChain->getAlign(), *Flags, AAInfo); |
0 |
| 19500 |
} else { // Must be realized as a trunc store |
--- |
19500 |
} else { // Must be realized as a trunc store |
--- |
| 19501 |
EVT LegalizedStoredValTy = |
--- |
19501 |
EVT LegalizedStoredValTy = |
--- |
| 19502 |
TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType()); |
0 |
19502 |
TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType()); |
0 |
| 19503 |
unsigned LegalizedStoreSize = LegalizedStoredValTy.getSizeInBits(); |
0 |
19503 |
unsigned LegalizedStoreSize = LegalizedStoredValTy.getSizeInBits(); |
0 |
| 19504 |
ConstantSDNode *C = cast(StoredVal); |
0 |
19504 |
ConstantSDNode *C = cast(StoredVal); |
0 |
| 19505 |
SDValue ExtendedStoreVal = |
--- |
19505 |
SDValue ExtendedStoreVal = |
--- |
| 19506 |
DAG.getConstant(C->getAPIntValue().zextOrTrunc(LegalizedStoreSize), DL, |
0 |
19506 |
DAG.getConstant(C->getAPIntValue().zextOrTrunc(LegalizedStoreSize), DL, |
0 |
| 19507 |
LegalizedStoredValTy); |
--- |
19507 |
LegalizedStoredValTy); |
--- |
| 19508 |
NewStore = DAG.getTruncStore( |
0 |
19508 |
NewStore = DAG.getTruncStore( |
0 |
| 19509 |
NewChain, DL, ExtendedStoreVal, FirstInChain->getBasePtr(), |
0 |
19509 |
NewChain, DL, ExtendedStoreVal, FirstInChain->getBasePtr(), |
0 |
| 19510 |
CanReusePtrInfo |
--- |
19510 |
CanReusePtrInfo |
--- |
| 19511 |
? FirstInChain->getPointerInfo() |
0 |
19511 |
? FirstInChain->getPointerInfo() |
0 |
| 19512 |
: MachinePointerInfo(FirstInChain->getPointerInfo().getAddrSpace()), |
0 |
19512 |
: MachinePointerInfo(FirstInChain->getPointerInfo().getAddrSpace()), |
0 |
| 19513 |
StoredVal.getValueType() /*TVT*/, FirstInChain->getAlign(), *Flags, |
0 |
19513 |
StoredVal.getValueType() /*TVT*/, FirstInChain->getAlign(), *Flags, |
0 |
| 19514 |
AAInfo); |
--- |
19514 |
AAInfo); |
--- |
| 19515 |
} |
--- |
19515 |
} |
--- |
| 19516 |
|
--- |
19516 |
|
--- |
| 19517 |
// Replace all merged stores with the new store. |
--- |
19517 |
// Replace all merged stores with the new store. |
--- |
| 19518 |
for (unsigned i = 0; i < NumStores; ++i) |
0 |
19518 |
for (unsigned i = 0; i < NumStores; ++i) |
0 |
| 19519 |
CombineTo(StoreNodes[i].MemNode, NewStore); |
0 |
19519 |
CombineTo(StoreNodes[i].MemNode, NewStore); |
0 |
| 19520 |
|
--- |
19520 |
|
--- |
| 19521 |
AddToWorklist(NewChain.getNode()); |
0 |
19521 |
AddToWorklist(NewChain.getNode()); |
0 |
| 19522 |
return true; |
0 |
19522 |
return true; |
0 |
| 19523 |
} |
0 |
19523 |
} |
0 |
| 19524 |
|
--- |
19524 |
|
--- |
| 19525 |
void DAGCombiner::getStoreMergeCandidates( |
0 |
19525 |
void DAGCombiner::getStoreMergeCandidates( |
0 |
| 19526 |
StoreSDNode *St, SmallVectorImpl &StoreNodes, |
--- |
19526 |
StoreSDNode *St, SmallVectorImpl &StoreNodes, |
--- |
| 19527 |
SDNode *&RootNode) { |
--- |
19527 |
SDNode *&RootNode) { |
--- |
| 19528 |
// This holds the base pointer, index, and the offset in bytes from the base |
--- |
19528 |
// This holds the base pointer, index, and the offset in bytes from the base |
--- |
| 19529 |
// pointer. We must have a base and an offset. Do not handle stores to undef |
--- |
19529 |
// pointer. We must have a base and an offset. Do not handle stores to undef |
--- |
| 19530 |
// base pointers. |
--- |
19530 |
// base pointers. |
--- |
| 19531 |
BaseIndexOffset BasePtr = BaseIndexOffset::match(St, DAG); |
0 |
19531 |
BaseIndexOffset BasePtr = BaseIndexOffset::match(St, DAG); |
0 |
| 19532 |
if (!BasePtr.getBase().getNode() || BasePtr.getBase().isUndef()) |
0 |
19532 |
if (!BasePtr.getBase().getNode() || BasePtr.getBase().isUndef()) |
0 |
| 19533 |
return; |
0 |
19533 |
return; |
0 |
| 19534 |
|
--- |
19534 |
|
--- |
| 19535 |
SDValue Val = peekThroughBitcasts(St->getValue()); |
0 |
19535 |
SDValue Val = peekThroughBitcasts(St->getValue()); |
0 |
| 19536 |
StoreSource StoreSrc = getStoreSource(Val); |
0 |
19536 |
StoreSource StoreSrc = getStoreSource(Val); |
0 |
| 19537 |
assert(StoreSrc != StoreSource::Unknown && "Expected known source for store"); |
0 |
19537 |
assert(StoreSrc != StoreSource::Unknown && "Expected known source for store"); |
0 |
| 19538 |
|
--- |
19538 |
|
--- |
| 19539 |
// Match on loadbaseptr if relevant. |
--- |
19539 |
// Match on loadbaseptr if relevant. |
--- |
| 19540 |
EVT MemVT = St->getMemoryVT(); |
0 |
19540 |
EVT MemVT = St->getMemoryVT(); |
0 |
| 19541 |
BaseIndexOffset LBasePtr; |
0 |
19541 |
BaseIndexOffset LBasePtr; |
0 |
| 19542 |
EVT LoadVT; |
0 |
19542 |
EVT LoadVT; |
0 |
| 19543 |
if (StoreSrc == StoreSource::Load) { |
0 |
19543 |
if (StoreSrc == StoreSource::Load) { |
0 |
| 19544 |
auto *Ld = cast(Val); |
0 |
19544 |
auto *Ld = cast(Val); |
0 |
| 19545 |
LBasePtr = BaseIndexOffset::match(Ld, DAG); |
0 |
19545 |
LBasePtr = BaseIndexOffset::match(Ld, DAG); |
0 |
| 19546 |
LoadVT = Ld->getMemoryVT(); |
0 |
19546 |
LoadVT = Ld->getMemoryVT(); |
0 |
| 19547 |
// Load and store should be the same type. |
--- |
19547 |
// Load and store should be the same type. |
--- |
| 19548 |
if (MemVT != LoadVT) |
0 |
19548 |
if (MemVT != LoadVT) |
0 |
| 19549 |
return; |
0 |
19549 |
return; |
0 |
| 19550 |
// Loads must only have one use. |
--- |
19550 |
// Loads must only have one use. |
--- |
| 19551 |
if (!Ld->hasNUsesOfValue(1, 0)) |
0 |
19551 |
if (!Ld->hasNUsesOfValue(1, 0)) |
0 |
| 19552 |
return; |
0 |
19552 |
return; |
0 |
| 19553 |
// The memory operands must not be volatile/indexed/atomic. |
--- |
19553 |
// The memory operands must not be volatile/indexed/atomic. |
--- |
| 19554 |
// TODO: May be able to relax for unordered atomics (see D66309) |
--- |
19554 |
// TODO: May be able to relax for unordered atomics (see D66309) |
--- |
| 19555 |
if (!Ld->isSimple() || Ld->isIndexed()) |
0 |
19555 |
if (!Ld->isSimple() || Ld->isIndexed()) |
0 |
| 19556 |
return; |
0 |
19556 |
return; |
0 |
| 19557 |
} |
--- |
19557 |
} |
--- |
| 19558 |
auto CandidateMatch = [&](StoreSDNode *Other, BaseIndexOffset &Ptr, |
0 |
19558 |
auto CandidateMatch = [&](StoreSDNode *Other, BaseIndexOffset &Ptr, |
0 |
| 19559 |
int64_t &Offset) -> bool { |
--- |
19559 |
int64_t &Offset) -> bool { |
--- |
| 19560 |
// The memory operands must not be volatile/indexed/atomic. |
--- |
19560 |
// The memory operands must not be volatile/indexed/atomic. |
--- |
| 19561 |
// TODO: May be able to relax for unordered atomics (see D66309) |
--- |
19561 |
// TODO: May be able to relax for unordered atomics (see D66309) |
--- |
| 19562 |
if (!Other->isSimple() || Other->isIndexed()) |
0 |
19562 |
if (!Other->isSimple() || Other->isIndexed()) |
0 |
| 19563 |
return false; |
0 |
19563 |
return false; |
0 |
| 19564 |
// Don't mix temporal stores with non-temporal stores. |
--- |
19564 |
// Don't mix temporal stores with non-temporal stores. |
--- |
| 19565 |
if (St->isNonTemporal() != Other->isNonTemporal()) |
0 |
19565 |
if (St->isNonTemporal() != Other->isNonTemporal()) |
0 |
| 19566 |
return false; |
0 |
19566 |
return false; |
0 |
| 19567 |
if (!TLI.areTwoSDNodeTargetMMOFlagsMergeable(*St, *Other)) |
0 |
19567 |
if (!TLI.areTwoSDNodeTargetMMOFlagsMergeable(*St, *Other)) |
0 |
| 19568 |
return false; |
0 |
19568 |
return false; |
0 |
| 19569 |
SDValue OtherBC = peekThroughBitcasts(Other->getValue()); |
0 |
19569 |
SDValue OtherBC = peekThroughBitcasts(Other->getValue()); |
0 |
| 19570 |
// Allow merging constants of different types as integers. |
--- |
19570 |
// Allow merging constants of different types as integers. |
--- |
| 19571 |
bool NoTypeMatch = (MemVT.isInteger()) ? !MemVT.bitsEq(Other->getMemoryVT()) |
0 |
19571 |
bool NoTypeMatch = (MemVT.isInteger()) ? !MemVT.bitsEq(Other->getMemoryVT()) |
0 |
| 19572 |
: Other->getMemoryVT() != MemVT; |
0 |
19572 |
: Other->getMemoryVT() != MemVT; |
0 |
| 19573 |
switch (StoreSrc) { |
0 |
19573 |
switch (StoreSrc) { |
0 |
| 19574 |
case StoreSource::Load: { |
0 |
19574 |
case StoreSource::Load: { |
0 |
| 19575 |
if (NoTypeMatch) |
0 |
19575 |
if (NoTypeMatch) |
0 |
| 19576 |
return false; |
0 |
19576 |
return false; |
0 |
| 19577 |
// The Load's Base Ptr must also match. |
--- |
19577 |
// The Load's Base Ptr must also match. |
--- |
| 19578 |
auto *OtherLd = dyn_cast(OtherBC); |
0 |
19578 |
auto *OtherLd = dyn_cast(OtherBC); |
0 |
| 19579 |
if (!OtherLd) |
0 |
19579 |
if (!OtherLd) |
0 |
| 19580 |
return false; |
0 |
19580 |
return false; |
0 |
| 19581 |
BaseIndexOffset LPtr = BaseIndexOffset::match(OtherLd, DAG); |
0 |
19581 |
BaseIndexOffset LPtr = BaseIndexOffset::match(OtherLd, DAG); |
0 |
| 19582 |
if (LoadVT != OtherLd->getMemoryVT()) |
0 |
19582 |
if (LoadVT != OtherLd->getMemoryVT()) |
0 |
| 19583 |
return false; |
0 |
19583 |
return false; |
0 |
| 19584 |
// Loads must only have one use. |
--- |
19584 |
// Loads must only have one use. |
--- |
| 19585 |
if (!OtherLd->hasNUsesOfValue(1, 0)) |
0 |
19585 |
if (!OtherLd->hasNUsesOfValue(1, 0)) |
0 |
| 19586 |
return false; |
0 |
19586 |
return false; |
0 |
| 19587 |
// The memory operands must not be volatile/indexed/atomic. |
--- |
19587 |
// The memory operands must not be volatile/indexed/atomic. |
--- |
| 19588 |
// TODO: May be able to relax for unordered atomics (see D66309) |
--- |
19588 |
// TODO: May be able to relax for unordered atomics (see D66309) |
--- |
| 19589 |
if (!OtherLd->isSimple() || OtherLd->isIndexed()) |
0 |
19589 |
if (!OtherLd->isSimple() || OtherLd->isIndexed()) |
0 |
| 19590 |
return false; |
0 |
19590 |
return false; |
0 |
| 19591 |
// Don't mix temporal loads with non-temporal loads. |
--- |
19591 |
// Don't mix temporal loads with non-temporal loads. |
--- |
| 19592 |
if (cast(Val)->isNonTemporal() != OtherLd->isNonTemporal()) |
0 |
19592 |
if (cast(Val)->isNonTemporal() != OtherLd->isNonTemporal()) |
0 |
| 19593 |
return false; |
0 |
19593 |
return false; |
0 |
| 19594 |
if (!TLI.areTwoSDNodeTargetMMOFlagsMergeable(*cast(Val), |
0 |
19594 |
if (!TLI.areTwoSDNodeTargetMMOFlagsMergeable(*cast(Val), |
0 |
| 19595 |
*OtherLd)) |
--- |
19595 |
*OtherLd)) |
--- |
| 19596 |
return false; |
0 |
19596 |
return false; |
0 |
| 19597 |
if (!(LBasePtr.equalBaseIndex(LPtr, DAG))) |
0 |
19597 |
if (!(LBasePtr.equalBaseIndex(LPtr, DAG))) |
0 |
| 19598 |
return false; |
0 |
19598 |
return false; |
0 |
| 19599 |
break; |
0 |
19599 |
break; |
0 |
| 19600 |
} |
--- |
19600 |
} |
--- |
| 19601 |
case StoreSource::Constant: |
0 |
19601 |
case StoreSource::Constant: |
0 |
| 19602 |
if (NoTypeMatch) |
0 |
19602 |
if (NoTypeMatch) |
0 |
| 19603 |
return false; |
0 |
19603 |
return false; |
0 |
| 19604 |
if (!isIntOrFPConstant(OtherBC)) |
0 |
19604 |
if (!isIntOrFPConstant(OtherBC)) |
0 |
| 19605 |
return false; |
0 |
19605 |
return false; |
0 |
| 19606 |
break; |
0 |
19606 |
break; |
0 |
| 19607 |
case StoreSource::Extract: |
0 |
19607 |
case StoreSource::Extract: |
0 |
| 19608 |
// Do not merge truncated stores here. |
--- |
19608 |
// Do not merge truncated stores here. |
--- |
| 19609 |
if (Other->isTruncatingStore()) |
0 |
19609 |
if (Other->isTruncatingStore()) |
0 |
| 19610 |
return false; |
0 |
19610 |
return false; |
0 |
| 19611 |
if (!MemVT.bitsEq(OtherBC.getValueType())) |
0 |
19611 |
if (!MemVT.bitsEq(OtherBC.getValueType())) |
0 |
| 19612 |
return false; |
0 |
19612 |
return false; |
0 |
| 19613 |
if (OtherBC.getOpcode() != ISD::EXTRACT_VECTOR_ELT && |
0 |
19613 |
if (OtherBC.getOpcode() != ISD::EXTRACT_VECTOR_ELT && |
0 |
| 19614 |
OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) |
0 |
19614 |
OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) |
0 |
| 19615 |
return false; |
0 |
19615 |
return false; |
0 |
| 19616 |
break; |
0 |
19616 |
break; |
0 |
| 19617 |
default: |
0 |
19617 |
default: |
0 |
| 19618 |
llvm_unreachable("Unhandled store source for merging"); |
0 |
19618 |
llvm_unreachable("Unhandled store source for merging"); |
0 |
| 19619 |
} |
--- |
19619 |
} |
--- |
| 19620 |
Ptr = BaseIndexOffset::match(Other, DAG); |
0 |
19620 |
Ptr = BaseIndexOffset::match(Other, DAG); |
0 |
| 19621 |
return (BasePtr.equalBaseIndex(Ptr, DAG, Offset)); |
0 |
19621 |
return (BasePtr.equalBaseIndex(Ptr, DAG, Offset)); |
0 |
| 19622 |
}; |
0 |
19622 |
}; |
0 |
| 19623 |
|
--- |
19623 |
|
--- |
| 19624 |
// Check if the pair of StoreNode and the RootNode already bail out many |
--- |
19624 |
// Check if the pair of StoreNode and the RootNode already bail out many |
--- |
| 19625 |
// times which is over the limit in dependence check. |
--- |
19625 |
// times which is over the limit in dependence check. |
--- |
| 19626 |
auto OverLimitInDependenceCheck = [&](SDNode *StoreNode, |
0 |
19626 |
auto OverLimitInDependenceCheck = [&](SDNode *StoreNode, |
0 |
| 19627 |
SDNode *RootNode) -> bool { |
--- |
19627 |
SDNode *RootNode) -> bool { |
--- |
| 19628 |
auto RootCount = StoreRootCountMap.find(StoreNode); |
0 |
19628 |
auto RootCount = StoreRootCountMap.find(StoreNode); |
0 |
| 19629 |
return RootCount != StoreRootCountMap.end() && |
0 |
19629 |
return RootCount != StoreRootCountMap.end() && |
0 |
| 19630 |
RootCount->second.first == RootNode && |
0 |
19630 |
RootCount->second.first == RootNode && |
0 |
| 19631 |
RootCount->second.second > StoreMergeDependenceLimit; |
0 |
19631 |
RootCount->second.second > StoreMergeDependenceLimit; |
0 |
| 19632 |
}; |
0 |
19632 |
}; |
0 |
| 19633 |
|
--- |
19633 |
|
--- |
| 19634 |
auto TryToAddCandidate = [&](SDNode::use_iterator UseIter) { |
0 |
19634 |
auto TryToAddCandidate = [&](SDNode::use_iterator UseIter) { |
0 |
| 19635 |
// This must be a chain use. |
--- |
19635 |
// This must be a chain use. |
--- |
| 19636 |
if (UseIter.getOperandNo() != 0) |
0 |
19636 |
if (UseIter.getOperandNo() != 0) |
0 |
| 19637 |
return; |
0 |
19637 |
return; |
0 |
| 19638 |
if (auto *OtherStore = dyn_cast(*UseIter)) { |
0 |
19638 |
if (auto *OtherStore = dyn_cast(*UseIter)) { |
0 |
| 19639 |
BaseIndexOffset Ptr; |
0 |
19639 |
BaseIndexOffset Ptr; |
0 |
| 19640 |
int64_t PtrDiff; |
--- |
19640 |
int64_t PtrDiff; |
--- |
| 19641 |
if (CandidateMatch(OtherStore, Ptr, PtrDiff) && |
0 |
19641 |
if (CandidateMatch(OtherStore, Ptr, PtrDiff) && |
0 |
| 19642 |
!OverLimitInDependenceCheck(OtherStore, RootNode)) |
0 |
19642 |
!OverLimitInDependenceCheck(OtherStore, RootNode)) |
0 |
| 19643 |
StoreNodes.push_back(MemOpLink(OtherStore, PtrDiff)); |
0 |
19643 |
StoreNodes.push_back(MemOpLink(OtherStore, PtrDiff)); |
0 |
| 19644 |
} |
--- |
19644 |
} |
--- |
| 19645 |
}; |
0 |
19645 |
}; |
0 |
| 19646 |
|
--- |
19646 |
|
--- |
| 19647 |
// We looking for a root node which is an ancestor to all mergable |
--- |
19647 |
// We looking for a root node which is an ancestor to all mergable |
--- |
| 19648 |
// stores. We search up through a load, to our root and then down |
--- |
19648 |
// stores. We search up through a load, to our root and then down |
--- |
| 19649 |
// through all children. For instance we will find Store{1,2,3} if |
--- |
19649 |
// through all children. For instance we will find Store{1,2,3} if |
--- |
| 19650 |
// St is Store1, Store2. or Store3 where the root is not a load |
--- |
19650 |
// St is Store1, Store2. or Store3 where the root is not a load |
--- |
| 19651 |
// which always true for nonvolatile ops. TODO: Expand |
--- |
19651 |
// which always true for nonvolatile ops. TODO: Expand |
--- |
| 19652 |
// the search to find all valid candidates through multiple layers of loads. |
--- |
19652 |
// the search to find all valid candidates through multiple layers of loads. |
--- |
| 19653 |
// |
--- |
19653 |
// |
--- |
| 19654 |
// Root |
--- |
19654 |
// Root |
--- |
| 19655 |
// |-------|-------| |
--- |
19655 |
// |-------|-------| |
--- |
| 19656 |
// Load Load Store3 |
--- |
19656 |
// Load Load Store3 |
--- |
| 19657 |
// | | |
--- |
19657 |
// | | |
--- |
| 19658 |
// Store1 Store2 |
--- |
19658 |
// Store1 Store2 |
--- |
| 19659 |
// |
--- |
19659 |
// |
--- |
| 19660 |
// FIXME: We should be able to climb and |
--- |
19660 |
// FIXME: We should be able to climb and |
--- |
| 19661 |
// descend TokenFactors to find candidates as well. |
--- |
19661 |
// descend TokenFactors to find candidates as well. |
--- |
| 19662 |
|
--- |
19662 |
|
--- |
| 19663 |
RootNode = St->getChain().getNode(); |
0 |
19663 |
RootNode = St->getChain().getNode(); |
0 |
| 19664 |
|
--- |
19664 |
|
--- |
| 19665 |
unsigned NumNodesExplored = 0; |
0 |
19665 |
unsigned NumNodesExplored = 0; |
0 |
| 19666 |
const unsigned MaxSearchNodes = 1024; |
0 |
19666 |
const unsigned MaxSearchNodes = 1024; |
0 |
| 19667 |
if (auto *Ldn = dyn_cast(RootNode)) { |
0 |
19667 |
if (auto *Ldn = dyn_cast(RootNode)) { |
0 |
| 19668 |
RootNode = Ldn->getChain().getNode(); |
0 |
19668 |
RootNode = Ldn->getChain().getNode(); |
0 |
| 19669 |
for (auto I = RootNode->use_begin(), E = RootNode->use_end(); |
0 |
19669 |
for (auto I = RootNode->use_begin(), E = RootNode->use_end(); |
0 |
| 19670 |
I != E && NumNodesExplored < MaxSearchNodes; ++I, ++NumNodesExplored) { |
0 |
19670 |
I != E && NumNodesExplored < MaxSearchNodes; ++I, ++NumNodesExplored) { |
0 |
| 19671 |
if (I.getOperandNo() == 0 && isa(*I)) { // walk down chain |
0 |
19671 |
if (I.getOperandNo() == 0 && isa(*I)) { // walk down chain |
0 |
| 19672 |
for (auto I2 = (*I)->use_begin(), E2 = (*I)->use_end(); I2 != E2; ++I2) |
0 |
19672 |
for (auto I2 = (*I)->use_begin(), E2 = (*I)->use_end(); I2 != E2; ++I2) |
0 |
| 19673 |
TryToAddCandidate(I2); |
0 |
19673 |
TryToAddCandidate(I2); |
0 |
| 19674 |
} |
--- |
19674 |
} |
--- |
| 19675 |
// Check stores that depend on the root (e.g. Store 3 in the chart above). |
--- |
19675 |
// Check stores that depend on the root (e.g. Store 3 in the chart above). |
--- |
| 19676 |
if (I.getOperandNo() == 0 && isa(*I)) { |
0 |
19676 |
if (I.getOperandNo() == 0 && isa(*I)) { |
0 |
| 19677 |
TryToAddCandidate(I); |
0 |
19677 |
TryToAddCandidate(I); |
0 |
| 19678 |
} |
--- |
19678 |
} |
--- |
| 19679 |
} |
--- |
19679 |
} |
--- |
| 19680 |
} else { |
--- |
19680 |
} else { |
--- |
| 19681 |
for (auto I = RootNode->use_begin(), E = RootNode->use_end(); |
0 |
19681 |
for (auto I = RootNode->use_begin(), E = RootNode->use_end(); |
0 |
| 19682 |
I != E && NumNodesExplored < MaxSearchNodes; ++I, ++NumNodesExplored) |
0 |
19682 |
I != E && NumNodesExplored < MaxSearchNodes; ++I, ++NumNodesExplored) |
0 |
| 19683 |
TryToAddCandidate(I); |
0 |
19683 |
TryToAddCandidate(I); |
0 |
| 19684 |
} |
--- |
19684 |
} |
--- |
| 19685 |
} |
--- |
19685 |
} |
--- |
| 19686 |
|
--- |
19686 |
|
--- |
| 19687 |
// We need to check that merging these stores does not cause a loop in the |
--- |
19687 |
// We need to check that merging these stores does not cause a loop in the |
--- |
| 19688 |
// DAG. Any store candidate may depend on another candidate indirectly through |
--- |
19688 |
// DAG. Any store candidate may depend on another candidate indirectly through |
--- |
| 19689 |
// its operands. Check in parallel by searching up from operands of candidates. |
--- |
19689 |
// its operands. Check in parallel by searching up from operands of candidates. |
--- |
| 19690 |
bool DAGCombiner::checkMergeStoreCandidatesForDependencies( |
0 |
19690 |
bool DAGCombiner::checkMergeStoreCandidatesForDependencies( |
0 |
| 19691 |
SmallVectorImpl &StoreNodes, unsigned NumStores, |
--- |
19691 |
SmallVectorImpl &StoreNodes, unsigned NumStores, |
--- |
| 19692 |
SDNode *RootNode) { |
--- |
19692 |
SDNode *RootNode) { |
--- |
| 19693 |
// FIXME: We should be able to truncate a full search of |
--- |
19693 |
// FIXME: We should be able to truncate a full search of |
--- |
| 19694 |
// predecessors by doing a BFS and keeping tabs the originating |
--- |
19694 |
// predecessors by doing a BFS and keeping tabs the originating |
--- |
| 19695 |
// stores from which worklist nodes come from in a similar way to |
--- |
19695 |
// stores from which worklist nodes come from in a similar way to |
--- |
| 19696 |
// TokenFactor simplfication. |
--- |
19696 |
// TokenFactor simplfication. |
--- |
| 19697 |
|
--- |
19697 |
|
--- |
| 19698 |
SmallPtrSet Visited; |
0 |
19698 |
SmallPtrSet Visited; |
0 |
| 19699 |
SmallVector Worklist; |
0 |
19699 |
SmallVector Worklist; |
0 |
| 19700 |
|
--- |
19700 |
|
--- |
| 19701 |
// RootNode is a predecessor to all candidates so we need not search |
--- |
19701 |
// RootNode is a predecessor to all candidates so we need not search |
--- |
| 19702 |
// past it. Add RootNode (peeking through TokenFactors). Do not count |
--- |
19702 |
// past it. Add RootNode (peeking through TokenFactors). Do not count |
--- |
| 19703 |
// these towards size check. |
--- |
19703 |
// these towards size check. |
--- |
| 19704 |
|
--- |
19704 |
|
--- |
| 19705 |
Worklist.push_back(RootNode); |
0 |
19705 |
Worklist.push_back(RootNode); |
0 |
| 19706 |
while (!Worklist.empty()) { |
0 |
19706 |
while (!Worklist.empty()) { |
0 |
| 19707 |
auto N = Worklist.pop_back_val(); |
0 |
19707 |
auto N = Worklist.pop_back_val(); |
0 |
| 19708 |
if (!Visited.insert(N).second) |
0 |
19708 |
if (!Visited.insert(N).second) |
0 |
| 19709 |
continue; // Already present in Visited. |
0 |
19709 |
continue; // Already present in Visited. |
0 |
| 19710 |
if (N->getOpcode() == ISD::TokenFactor) { |
0 |
19710 |
if (N->getOpcode() == ISD::TokenFactor) { |
0 |
| 19711 |
for (SDValue Op : N->ops()) |
0 |
19711 |
for (SDValue Op : N->ops()) |
0 |
| 19712 |
Worklist.push_back(Op.getNode()); |
0 |
19712 |
Worklist.push_back(Op.getNode()); |
0 |
| 19713 |
} |
--- |
19713 |
} |
--- |
| 19714 |
} |
--- |
19714 |
} |
--- |
| 19715 |
|
--- |
19715 |
|
--- |
| 19716 |
// Don't count pruning nodes towards max. |
--- |
19716 |
// Don't count pruning nodes towards max. |
--- |
| 19717 |
unsigned int Max = 1024 + Visited.size(); |
0 |
19717 |
unsigned int Max = 1024 + Visited.size(); |
0 |
| 19718 |
// Search Ops of store candidates. |
--- |
19718 |
// Search Ops of store candidates. |
--- |
| 19719 |
for (unsigned i = 0; i < NumStores; ++i) { |
0 |
19719 |
for (unsigned i = 0; i < NumStores; ++i) { |
0 |
| 19720 |
SDNode *N = StoreNodes[i].MemNode; |
0 |
19720 |
SDNode *N = StoreNodes[i].MemNode; |
0 |
| 19721 |
// Of the 4 Store Operands: |
--- |
19721 |
// Of the 4 Store Operands: |
--- |
| 19722 |
// * Chain (Op 0) -> We have already considered these |
--- |
19722 |
// * Chain (Op 0) -> We have already considered these |
--- |
| 19723 |
// in candidate selection, but only by following the |
--- |
19723 |
// in candidate selection, but only by following the |
--- |
| 19724 |
// chain dependencies. We could still have a chain |
--- |
19724 |
// chain dependencies. We could still have a chain |
--- |
| 19725 |
// dependency to a load, that has a non-chain dep to |
--- |
19725 |
// dependency to a load, that has a non-chain dep to |
--- |
| 19726 |
// another load, that depends on a store, etc. So it is |
--- |
19726 |
// another load, that depends on a store, etc. So it is |
--- |
| 19727 |
// possible to have dependencies that consist of a mix |
--- |
19727 |
// possible to have dependencies that consist of a mix |
--- |
| 19728 |
// of chain and non-chain deps, and we need to include |
--- |
19728 |
// of chain and non-chain deps, and we need to include |
--- |
| 19729 |
// chain operands in the analysis here.. |
--- |
19729 |
// chain operands in the analysis here.. |
--- |
| 19730 |
// * Value (Op 1) -> Cycles may happen (e.g. through load chains) |
--- |
19730 |
// * Value (Op 1) -> Cycles may happen (e.g. through load chains) |
--- |
| 19731 |
// * Address (Op 2) -> Merged addresses may only vary by a fixed constant, |
--- |
19731 |
// * Address (Op 2) -> Merged addresses may only vary by a fixed constant, |
--- |
| 19732 |
// but aren't necessarily fromt the same base node, so |
--- |
19732 |
// but aren't necessarily fromt the same base node, so |
--- |
| 19733 |
// cycles possible (e.g. via indexed store). |
--- |
19733 |
// cycles possible (e.g. via indexed store). |
--- |
| 19734 |
// * (Op 3) -> Represents the pre or post-indexing offset (or undef for |
--- |
19734 |
// * (Op 3) -> Represents the pre or post-indexing offset (or undef for |
--- |
| 19735 |
// non-indexed stores). Not constant on all targets (e.g. ARM) |
--- |
19735 |
// non-indexed stores). Not constant on all targets (e.g. ARM) |
--- |
| 19736 |
// and so can participate in a cycle. |
--- |
19736 |
// and so can participate in a cycle. |
--- |
| 19737 |
for (unsigned j = 0; j < N->getNumOperands(); ++j) |
0 |
19737 |
for (unsigned j = 0; j < N->getNumOperands(); ++j) |
0 |
| 19738 |
Worklist.push_back(N->getOperand(j).getNode()); |
0 |
19738 |
Worklist.push_back(N->getOperand(j).getNode()); |
0 |
| 19739 |
} |
--- |
19739 |
} |
--- |
| 19740 |
// Search through DAG. We can stop early if we find a store node. |
--- |
19740 |
// Search through DAG. We can stop early if we find a store node. |
--- |
| 19741 |
for (unsigned i = 0; i < NumStores; ++i) |
0 |
19741 |
for (unsigned i = 0; i < NumStores; ++i) |
0 |
| 19742 |
if (SDNode::hasPredecessorHelper(StoreNodes[i].MemNode, Visited, Worklist, |
0 |
19742 |
if (SDNode::hasPredecessorHelper(StoreNodes[i].MemNode, Visited, Worklist, |
0 |
| 19743 |
Max)) { |
--- |
19743 |
Max)) { |
--- |
| 19744 |
// If the searching bail out, record the StoreNode and RootNode in the |
--- |
19744 |
// If the searching bail out, record the StoreNode and RootNode in the |
--- |
| 19745 |
// StoreRootCountMap. If we have seen the pair many times over a limit, |
--- |
19745 |
// StoreRootCountMap. If we have seen the pair many times over a limit, |
--- |
| 19746 |
// we won't add the StoreNode into StoreNodes set again. |
--- |
19746 |
// we won't add the StoreNode into StoreNodes set again. |
--- |
| 19747 |
if (Visited.size() >= Max) { |
0 |
19747 |
if (Visited.size() >= Max) { |
0 |
| 19748 |
auto &RootCount = StoreRootCountMap[StoreNodes[i].MemNode]; |
0 |
19748 |
auto &RootCount = StoreRootCountMap[StoreNodes[i].MemNode]; |
0 |
| 19749 |
if (RootCount.first == RootNode) |
0 |
19749 |
if (RootCount.first == RootNode) |
0 |
| 19750 |
RootCount.second++; |
0 |
19750 |
RootCount.second++; |
0 |
| 19751 |
else |
--- |
19751 |
else |
--- |
| 19752 |
RootCount = {RootNode, 1}; |
0 |
19752 |
RootCount = {RootNode, 1}; |
0 |
| 19753 |
} |
--- |
19753 |
} |
--- |
| 19754 |
return false; |
0 |
19754 |
return false; |
0 |
| 19755 |
} |
--- |
19755 |
} |
--- |
| 19756 |
return true; |
0 |
19756 |
return true; |
0 |
| 19757 |
} |
0 |
19757 |
} |
0 |
| 19758 |
|
--- |
19758 |
|
--- |
| 19759 |
unsigned |
--- |
19759 |
unsigned |
--- |
| 19760 |
DAGCombiner::getConsecutiveStores(SmallVectorImpl &StoreNodes, |
0 |
19760 |
DAGCombiner::getConsecutiveStores(SmallVectorImpl &StoreNodes, |
0 |
| 19761 |
int64_t ElementSizeBytes) const { |
--- |
19761 |
int64_t ElementSizeBytes) const { |
--- |
| 19762 |
while (true) { |
--- |
19762 |
while (true) { |
--- |
| 19763 |
// Find a store past the width of the first store. |
--- |
19763 |
// Find a store past the width of the first store. |
--- |
| 19764 |
size_t StartIdx = 0; |
0 |
19764 |
size_t StartIdx = 0; |
0 |
| 19765 |
while ((StartIdx + 1 < StoreNodes.size()) && |
0 |
19765 |
while ((StartIdx + 1 < StoreNodes.size()) && |
0 |
| 19766 |
StoreNodes[StartIdx].OffsetFromBase + ElementSizeBytes != |
0 |
19766 |
StoreNodes[StartIdx].OffsetFromBase + ElementSizeBytes != |
0 |
| 19767 |
StoreNodes[StartIdx + 1].OffsetFromBase) |
0 |
19767 |
StoreNodes[StartIdx + 1].OffsetFromBase) |
0 |
| 19768 |
++StartIdx; |
0 |
19768 |
++StartIdx; |
0 |
| 19769 |
|
--- |
19769 |
|
--- |
| 19770 |
// Bail if we don't have enough candidates to merge. |
--- |
19770 |
// Bail if we don't have enough candidates to merge. |
--- |
| 19771 |
if (StartIdx + 1 >= StoreNodes.size()) |
0 |
19771 |
if (StartIdx + 1 >= StoreNodes.size()) |
0 |
| 19772 |
return 0; |
0 |
19772 |
return 0; |
0 |
| 19773 |
|
--- |
19773 |
|
--- |
| 19774 |
// Trim stores that overlapped with the first store. |
--- |
19774 |
// Trim stores that overlapped with the first store. |
--- |
| 19775 |
if (StartIdx) |
0 |
19775 |
if (StartIdx) |
0 |
| 19776 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + StartIdx); |
0 |
19776 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + StartIdx); |
0 |
| 19777 |
|
--- |
19777 |
|
--- |
| 19778 |
// Scan the memory operations on the chain and find the first |
--- |
19778 |
// Scan the memory operations on the chain and find the first |
--- |
| 19779 |
// non-consecutive store memory address. |
--- |
19779 |
// non-consecutive store memory address. |
--- |
| 19780 |
unsigned NumConsecutiveStores = 1; |
0 |
19780 |
unsigned NumConsecutiveStores = 1; |
0 |
| 19781 |
int64_t StartAddress = StoreNodes[0].OffsetFromBase; |
0 |
19781 |
int64_t StartAddress = StoreNodes[0].OffsetFromBase; |
0 |
| 19782 |
// Check that the addresses are consecutive starting from the second |
--- |
19782 |
// Check that the addresses are consecutive starting from the second |
--- |
| 19783 |
// element in the list of stores. |
--- |
19783 |
// element in the list of stores. |
--- |
| 19784 |
for (unsigned i = 1, e = StoreNodes.size(); i < e; ++i) { |
0 |
19784 |
for (unsigned i = 1, e = StoreNodes.size(); i < e; ++i) { |
0 |
| 19785 |
int64_t CurrAddress = StoreNodes[i].OffsetFromBase; |
0 |
19785 |
int64_t CurrAddress = StoreNodes[i].OffsetFromBase; |
0 |
| 19786 |
if (CurrAddress - StartAddress != (ElementSizeBytes * i)) |
0 |
19786 |
if (CurrAddress - StartAddress != (ElementSizeBytes * i)) |
0 |
| 19787 |
break; |
0 |
19787 |
break; |
0 |
| 19788 |
NumConsecutiveStores = i + 1; |
0 |
19788 |
NumConsecutiveStores = i + 1; |
0 |
| 19789 |
} |
--- |
19789 |
} |
--- |
| 19790 |
if (NumConsecutiveStores > 1) |
0 |
19790 |
if (NumConsecutiveStores > 1) |
0 |
| 19791 |
return NumConsecutiveStores; |
0 |
19791 |
return NumConsecutiveStores; |
0 |
| 19792 |
|
--- |
19792 |
|
--- |
| 19793 |
// There are no consecutive stores at the start of the list. |
--- |
19793 |
// There are no consecutive stores at the start of the list. |
--- |
| 19794 |
// Remove the first store and try again. |
--- |
19794 |
// Remove the first store and try again. |
--- |
| 19795 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + 1); |
0 |
19795 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + 1); |
0 |
| 19796 |
} |
0 |
19796 |
} |
0 |
| 19797 |
} |
--- |
19797 |
} |
--- |
| 19798 |
|
--- |
19798 |
|
--- |
| 19799 |
bool DAGCombiner::tryStoreMergeOfConstants( |
0 |
19799 |
bool DAGCombiner::tryStoreMergeOfConstants( |
0 |
| 19800 |
SmallVectorImpl &StoreNodes, unsigned NumConsecutiveStores, |
--- |
19800 |
SmallVectorImpl &StoreNodes, unsigned NumConsecutiveStores, |
--- |
| 19801 |
EVT MemVT, SDNode *RootNode, bool AllowVectors) { |
--- |
19801 |
EVT MemVT, SDNode *RootNode, bool AllowVectors) { |
--- |
| 19802 |
LLVMContext &Context = *DAG.getContext(); |
0 |
19802 |
LLVMContext &Context = *DAG.getContext(); |
0 |
| 19803 |
const DataLayout &DL = DAG.getDataLayout(); |
0 |
19803 |
const DataLayout &DL = DAG.getDataLayout(); |
0 |
| 19804 |
int64_t ElementSizeBytes = MemVT.getStoreSize(); |
0 |
19804 |
int64_t ElementSizeBytes = MemVT.getStoreSize(); |
0 |
| 19805 |
unsigned NumMemElts = MemVT.isVector() ? MemVT.getVectorNumElements() : 1; |
0 |
19805 |
unsigned NumMemElts = MemVT.isVector() ? MemVT.getVectorNumElements() : 1; |
0 |
| 19806 |
bool MadeChange = false; |
0 |
19806 |
bool MadeChange = false; |
0 |
| 19807 |
|
--- |
19807 |
|
--- |
| 19808 |
// Store the constants into memory as one consecutive store. |
--- |
19808 |
// Store the constants into memory as one consecutive store. |
--- |
| 19809 |
while (NumConsecutiveStores >= 2) { |
0 |
19809 |
while (NumConsecutiveStores >= 2) { |
0 |
| 19810 |
LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; |
0 |
19810 |
LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; |
0 |
| 19811 |
unsigned FirstStoreAS = FirstInChain->getAddressSpace(); |
0 |
19811 |
unsigned FirstStoreAS = FirstInChain->getAddressSpace(); |
0 |
| 19812 |
Align FirstStoreAlign = FirstInChain->getAlign(); |
0 |
19812 |
Align FirstStoreAlign = FirstInChain->getAlign(); |
0 |
| 19813 |
unsigned LastLegalType = 1; |
0 |
19813 |
unsigned LastLegalType = 1; |
0 |
| 19814 |
unsigned LastLegalVectorType = 1; |
0 |
19814 |
unsigned LastLegalVectorType = 1; |
0 |
| 19815 |
bool LastIntegerTrunc = false; |
0 |
19815 |
bool LastIntegerTrunc = false; |
0 |
| 19816 |
bool NonZero = false; |
0 |
19816 |
bool NonZero = false; |
0 |
| 19817 |
unsigned FirstZeroAfterNonZero = NumConsecutiveStores; |
0 |
19817 |
unsigned FirstZeroAfterNonZero = NumConsecutiveStores; |
0 |
| 19818 |
for (unsigned i = 0; i < NumConsecutiveStores; ++i) { |
0 |
19818 |
for (unsigned i = 0; i < NumConsecutiveStores; ++i) { |
0 |
| 19819 |
StoreSDNode *ST = cast(StoreNodes[i].MemNode); |
0 |
19819 |
StoreSDNode *ST = cast(StoreNodes[i].MemNode); |
0 |
| 19820 |
SDValue StoredVal = ST->getValue(); |
0 |
19820 |
SDValue StoredVal = ST->getValue(); |
0 |
| 19821 |
bool IsElementZero = false; |
0 |
19821 |
bool IsElementZero = false; |
0 |
| 19822 |
if (ConstantSDNode *C = dyn_cast(StoredVal)) |
0 |
19822 |
if (ConstantSDNode *C = dyn_cast(StoredVal)) |
0 |
| 19823 |
IsElementZero = C->isZero(); |
0 |
19823 |
IsElementZero = C->isZero(); |
0 |
| 19824 |
else if (ConstantFPSDNode *C = dyn_cast(StoredVal)) |
0 |
19824 |
else if (ConstantFPSDNode *C = dyn_cast(StoredVal)) |
0 |
| 19825 |
IsElementZero = C->getConstantFPValue()->isNullValue(); |
0 |
19825 |
IsElementZero = C->getConstantFPValue()->isNullValue(); |
0 |
| 19826 |
if (IsElementZero) { |
0 |
19826 |
if (IsElementZero) { |
0 |
| 19827 |
if (NonZero && FirstZeroAfterNonZero == NumConsecutiveStores) |
0 |
19827 |
if (NonZero && FirstZeroAfterNonZero == NumConsecutiveStores) |
0 |
| 19828 |
FirstZeroAfterNonZero = i; |
0 |
19828 |
FirstZeroAfterNonZero = i; |
0 |
| 19829 |
} |
--- |
19829 |
} |
--- |
| 19830 |
NonZero |= !IsElementZero; |
0 |
19830 |
NonZero |= !IsElementZero; |
0 |
| 19831 |
|
--- |
19831 |
|
--- |
| 19832 |
// Find a legal type for the constant store. |
--- |
19832 |
// Find a legal type for the constant store. |
--- |
| 19833 |
unsigned SizeInBits = (i + 1) * ElementSizeBytes * 8; |
0 |
19833 |
unsigned SizeInBits = (i + 1) * ElementSizeBytes * 8; |
0 |
| 19834 |
EVT StoreTy = EVT::getIntegerVT(Context, SizeInBits); |
0 |
19834 |
EVT StoreTy = EVT::getIntegerVT(Context, SizeInBits); |
0 |
| 19835 |
unsigned IsFast = 0; |
0 |
19835 |
unsigned IsFast = 0; |
0 |
| 19836 |
|
--- |
19836 |
|
--- |
| 19837 |
// Break early when size is too large to be legal. |
--- |
19837 |
// Break early when size is too large to be legal. |
--- |
| 19838 |
if (StoreTy.getSizeInBits() > MaximumLegalStoreInBits) |
0 |
19838 |
if (StoreTy.getSizeInBits() > MaximumLegalStoreInBits) |
0 |
| 19839 |
break; |
0 |
19839 |
break; |
0 |
| 19840 |
|
--- |
19840 |
|
--- |
| 19841 |
if (TLI.isTypeLegal(StoreTy) && |
0 |
19841 |
if (TLI.isTypeLegal(StoreTy) && |
0 |
| 19842 |
TLI.canMergeStoresTo(FirstStoreAS, StoreTy, |
0 |
19842 |
TLI.canMergeStoresTo(FirstStoreAS, StoreTy, |
0 |
| 19843 |
DAG.getMachineFunction()) && |
0 |
19843 |
DAG.getMachineFunction()) && |
0 |
| 19844 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
19844 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
| 19845 |
*FirstInChain->getMemOperand(), &IsFast) && |
0 |
19845 |
*FirstInChain->getMemOperand(), &IsFast) && |
0 |
| 19846 |
IsFast) { |
0 |
19846 |
IsFast) { |
0 |
| 19847 |
LastIntegerTrunc = false; |
0 |
19847 |
LastIntegerTrunc = false; |
0 |
| 19848 |
LastLegalType = i + 1; |
0 |
19848 |
LastLegalType = i + 1; |
0 |
| 19849 |
// Or check whether a truncstore is legal. |
--- |
19849 |
// Or check whether a truncstore is legal. |
--- |
| 19850 |
} else if (TLI.getTypeAction(Context, StoreTy) == |
0 |
19850 |
} else if (TLI.getTypeAction(Context, StoreTy) == |
0 |
| 19851 |
TargetLowering::TypePromoteInteger) { |
--- |
19851 |
TargetLowering::TypePromoteInteger) { |
--- |
| 19852 |
EVT LegalizedStoredValTy = |
--- |
19852 |
EVT LegalizedStoredValTy = |
--- |
| 19853 |
TLI.getTypeToTransformTo(Context, StoredVal.getValueType()); |
0 |
19853 |
TLI.getTypeToTransformTo(Context, StoredVal.getValueType()); |
0 |
| 19854 |
if (TLI.isTruncStoreLegal(LegalizedStoredValTy, StoreTy) && |
0 |
19854 |
if (TLI.isTruncStoreLegal(LegalizedStoredValTy, StoreTy) && |
0 |
| 19855 |
TLI.canMergeStoresTo(FirstStoreAS, LegalizedStoredValTy, |
0 |
19855 |
TLI.canMergeStoresTo(FirstStoreAS, LegalizedStoredValTy, |
0 |
| 19856 |
DAG.getMachineFunction()) && |
0 |
19856 |
DAG.getMachineFunction()) && |
0 |
| 19857 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
19857 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
| 19858 |
*FirstInChain->getMemOperand(), &IsFast) && |
0 |
19858 |
*FirstInChain->getMemOperand(), &IsFast) && |
0 |
| 19859 |
IsFast) { |
0 |
19859 |
IsFast) { |
0 |
| 19860 |
LastIntegerTrunc = true; |
0 |
19860 |
LastIntegerTrunc = true; |
0 |
| 19861 |
LastLegalType = i + 1; |
0 |
19861 |
LastLegalType = i + 1; |
0 |
| 19862 |
} |
--- |
19862 |
} |
--- |
| 19863 |
} |
--- |
19863 |
} |
--- |
| 19864 |
|
--- |
19864 |
|
--- |
| 19865 |
// We only use vectors if the target allows it and the function is not |
--- |
19865 |
// We only use vectors if the target allows it and the function is not |
--- |
| 19866 |
// marked with the noimplicitfloat attribute. |
--- |
19866 |
// marked with the noimplicitfloat attribute. |
--- |
| 19867 |
if (TLI.storeOfVectorConstantIsCheap(!NonZero, MemVT, i + 1, FirstStoreAS) && |
0 |
19867 |
if (TLI.storeOfVectorConstantIsCheap(!NonZero, MemVT, i + 1, FirstStoreAS) && |
0 |
| 19868 |
AllowVectors) { |
--- |
19868 |
AllowVectors) { |
--- |
| 19869 |
// Find a legal type for the vector store. |
--- |
19869 |
// Find a legal type for the vector store. |
--- |
| 19870 |
unsigned Elts = (i + 1) * NumMemElts; |
0 |
19870 |
unsigned Elts = (i + 1) * NumMemElts; |
0 |
| 19871 |
EVT Ty = EVT::getVectorVT(Context, MemVT.getScalarType(), Elts); |
0 |
19871 |
EVT Ty = EVT::getVectorVT(Context, MemVT.getScalarType(), Elts); |
0 |
| 19872 |
if (TLI.isTypeLegal(Ty) && TLI.isTypeLegal(MemVT) && |
0 |
19872 |
if (TLI.isTypeLegal(Ty) && TLI.isTypeLegal(MemVT) && |
0 |
| 19873 |
TLI.canMergeStoresTo(FirstStoreAS, Ty, DAG.getMachineFunction()) && |
0 |
19873 |
TLI.canMergeStoresTo(FirstStoreAS, Ty, DAG.getMachineFunction()) && |
0 |
| 19874 |
TLI.allowsMemoryAccess(Context, DL, Ty, |
0 |
19874 |
TLI.allowsMemoryAccess(Context, DL, Ty, |
0 |
| 19875 |
*FirstInChain->getMemOperand(), &IsFast) && |
0 |
19875 |
*FirstInChain->getMemOperand(), &IsFast) && |
0 |
| 19876 |
IsFast) |
0 |
19876 |
IsFast) |
0 |
| 19877 |
LastLegalVectorType = i + 1; |
0 |
19877 |
LastLegalVectorType = i + 1; |
0 |
| 19878 |
} |
--- |
19878 |
} |
--- |
| 19879 |
} |
--- |
19879 |
} |
--- |
| 19880 |
|
--- |
19880 |
|
--- |
| 19881 |
bool UseVector = (LastLegalVectorType > LastLegalType) && AllowVectors; |
0 |
19881 |
bool UseVector = (LastLegalVectorType > LastLegalType) && AllowVectors; |
0 |
| 19882 |
unsigned NumElem = (UseVector) ? LastLegalVectorType : LastLegalType; |
0 |
19882 |
unsigned NumElem = (UseVector) ? LastLegalVectorType : LastLegalType; |
0 |
| 19883 |
bool UseTrunc = LastIntegerTrunc && !UseVector; |
0 |
19883 |
bool UseTrunc = LastIntegerTrunc && !UseVector; |
0 |
| 19884 |
|
--- |
19884 |
|
--- |
| 19885 |
// Check if we found a legal integer type that creates a meaningful |
--- |
19885 |
// Check if we found a legal integer type that creates a meaningful |
--- |
| 19886 |
// merge. |
--- |
19886 |
// merge. |
--- |
| 19887 |
if (NumElem < 2) { |
0 |
19887 |
if (NumElem < 2) { |
0 |
| 19888 |
// We know that candidate stores are in order and of correct |
--- |
19888 |
// We know that candidate stores are in order and of correct |
--- |
| 19889 |
// shape. While there is no mergeable sequence from the |
--- |
19889 |
// shape. While there is no mergeable sequence from the |
--- |
| 19890 |
// beginning one may start later in the sequence. The only |
--- |
19890 |
// beginning one may start later in the sequence. The only |
--- |
| 19891 |
// reason a merge of size N could have failed where another of |
--- |
19891 |
// reason a merge of size N could have failed where another of |
--- |
| 19892 |
// the same size would not have, is if the alignment has |
--- |
19892 |
// the same size would not have, is if the alignment has |
--- |
| 19893 |
// improved or we've dropped a non-zero value. Drop as many |
--- |
19893 |
// improved or we've dropped a non-zero value. Drop as many |
--- |
| 19894 |
// candidates as we can here. |
--- |
19894 |
// candidates as we can here. |
--- |
| 19895 |
unsigned NumSkip = 1; |
0 |
19895 |
unsigned NumSkip = 1; |
0 |
| 19896 |
while ((NumSkip < NumConsecutiveStores) && |
0 |
19896 |
while ((NumSkip < NumConsecutiveStores) && |
0 |
| 19897 |
(NumSkip < FirstZeroAfterNonZero) && |
0 |
19897 |
(NumSkip < FirstZeroAfterNonZero) && |
0 |
| 19898 |
(StoreNodes[NumSkip].MemNode->getAlign() <= FirstStoreAlign)) |
0 |
19898 |
(StoreNodes[NumSkip].MemNode->getAlign() <= FirstStoreAlign)) |
0 |
| 19899 |
NumSkip++; |
0 |
19899 |
NumSkip++; |
0 |
| 19900 |
|
--- |
19900 |
|
--- |
| 19901 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumSkip); |
0 |
19901 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumSkip); |
0 |
| 19902 |
NumConsecutiveStores -= NumSkip; |
0 |
19902 |
NumConsecutiveStores -= NumSkip; |
0 |
| 19903 |
continue; |
0 |
19903 |
continue; |
0 |
| 19904 |
} |
0 |
19904 |
} |
0 |
| 19905 |
|
--- |
19905 |
|
--- |
| 19906 |
// Check that we can merge these candidates without causing a cycle. |
--- |
19906 |
// Check that we can merge these candidates without causing a cycle. |
--- |
| 19907 |
if (!checkMergeStoreCandidatesForDependencies(StoreNodes, NumElem, |
0 |
19907 |
if (!checkMergeStoreCandidatesForDependencies(StoreNodes, NumElem, |
0 |
| 19908 |
RootNode)) { |
--- |
19908 |
RootNode)) { |
--- |
| 19909 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumElem); |
0 |
19909 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumElem); |
0 |
| 19910 |
NumConsecutiveStores -= NumElem; |
0 |
19910 |
NumConsecutiveStores -= NumElem; |
0 |
| 19911 |
continue; |
0 |
19911 |
continue; |
0 |
| 19912 |
} |
--- |
19912 |
} |
--- |
| 19913 |
|
--- |
19913 |
|
--- |
| 19914 |
MadeChange |= mergeStoresOfConstantsOrVecElts(StoreNodes, MemVT, NumElem, |
0 |
19914 |
MadeChange |= mergeStoresOfConstantsOrVecElts(StoreNodes, MemVT, NumElem, |
0 |
| 19915 |
/*IsConstantSrc*/ true, |
--- |
19915 |
/*IsConstantSrc*/ true, |
--- |
| 19916 |
UseVector, UseTrunc); |
--- |
19916 |
UseVector, UseTrunc); |
--- |
| 19917 |
|
--- |
19917 |
|
--- |
| 19918 |
// Remove merged stores for next iteration. |
--- |
19918 |
// Remove merged stores for next iteration. |
--- |
| 19919 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumElem); |
0 |
19919 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumElem); |
0 |
| 19920 |
NumConsecutiveStores -= NumElem; |
0 |
19920 |
NumConsecutiveStores -= NumElem; |
0 |
| 19921 |
} |
--- |
19921 |
} |
--- |
| 19922 |
return MadeChange; |
0 |
19922 |
return MadeChange; |
0 |
| 19923 |
} |
--- |
19923 |
} |
--- |
| 19924 |
|
--- |
19924 |
|
--- |
| 19925 |
bool DAGCombiner::tryStoreMergeOfExtracts( |
0 |
19925 |
bool DAGCombiner::tryStoreMergeOfExtracts( |
0 |
| 19926 |
SmallVectorImpl &StoreNodes, unsigned NumConsecutiveStores, |
--- |
19926 |
SmallVectorImpl &StoreNodes, unsigned NumConsecutiveStores, |
--- |
| 19927 |
EVT MemVT, SDNode *RootNode) { |
--- |
19927 |
EVT MemVT, SDNode *RootNode) { |
--- |
| 19928 |
LLVMContext &Context = *DAG.getContext(); |
0 |
19928 |
LLVMContext &Context = *DAG.getContext(); |
0 |
| 19929 |
const DataLayout &DL = DAG.getDataLayout(); |
0 |
19929 |
const DataLayout &DL = DAG.getDataLayout(); |
0 |
| 19930 |
unsigned NumMemElts = MemVT.isVector() ? MemVT.getVectorNumElements() : 1; |
0 |
19930 |
unsigned NumMemElts = MemVT.isVector() ? MemVT.getVectorNumElements() : 1; |
0 |
| 19931 |
bool MadeChange = false; |
0 |
19931 |
bool MadeChange = false; |
0 |
| 19932 |
|
--- |
19932 |
|
--- |
| 19933 |
// Loop on Consecutive Stores on success. |
--- |
19933 |
// Loop on Consecutive Stores on success. |
--- |
| 19934 |
while (NumConsecutiveStores >= 2) { |
0 |
19934 |
while (NumConsecutiveStores >= 2) { |
0 |
| 19935 |
LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; |
0 |
19935 |
LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; |
0 |
| 19936 |
unsigned FirstStoreAS = FirstInChain->getAddressSpace(); |
0 |
19936 |
unsigned FirstStoreAS = FirstInChain->getAddressSpace(); |
0 |
| 19937 |
Align FirstStoreAlign = FirstInChain->getAlign(); |
0 |
19937 |
Align FirstStoreAlign = FirstInChain->getAlign(); |
0 |
| 19938 |
unsigned NumStoresToMerge = 1; |
0 |
19938 |
unsigned NumStoresToMerge = 1; |
0 |
| 19939 |
for (unsigned i = 0; i < NumConsecutiveStores; ++i) { |
0 |
19939 |
for (unsigned i = 0; i < NumConsecutiveStores; ++i) { |
0 |
| 19940 |
// Find a legal type for the vector store. |
--- |
19940 |
// Find a legal type for the vector store. |
--- |
| 19941 |
unsigned Elts = (i + 1) * NumMemElts; |
0 |
19941 |
unsigned Elts = (i + 1) * NumMemElts; |
0 |
| 19942 |
EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), Elts); |
0 |
19942 |
EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), Elts); |
0 |
| 19943 |
unsigned IsFast = 0; |
0 |
19943 |
unsigned IsFast = 0; |
0 |
| 19944 |
|
--- |
19944 |
|
--- |
| 19945 |
// Break early when size is too large to be legal. |
--- |
19945 |
// Break early when size is too large to be legal. |
--- |
| 19946 |
if (Ty.getSizeInBits() > MaximumLegalStoreInBits) |
0 |
19946 |
if (Ty.getSizeInBits() > MaximumLegalStoreInBits) |
0 |
| 19947 |
break; |
0 |
19947 |
break; |
0 |
| 19948 |
|
--- |
19948 |
|
--- |
| 19949 |
if (TLI.isTypeLegal(Ty) && |
0 |
19949 |
if (TLI.isTypeLegal(Ty) && |
0 |
| 19950 |
TLI.canMergeStoresTo(FirstStoreAS, Ty, DAG.getMachineFunction()) && |
0 |
19950 |
TLI.canMergeStoresTo(FirstStoreAS, Ty, DAG.getMachineFunction()) && |
0 |
| 19951 |
TLI.allowsMemoryAccess(Context, DL, Ty, |
0 |
19951 |
TLI.allowsMemoryAccess(Context, DL, Ty, |
0 |
| 19952 |
*FirstInChain->getMemOperand(), &IsFast) && |
0 |
19952 |
*FirstInChain->getMemOperand(), &IsFast) && |
0 |
| 19953 |
IsFast) |
0 |
19953 |
IsFast) |
0 |
| 19954 |
NumStoresToMerge = i + 1; |
0 |
19954 |
NumStoresToMerge = i + 1; |
0 |
| 19955 |
} |
--- |
19955 |
} |
--- |
| 19956 |
|
--- |
19956 |
|
--- |
| 19957 |
// Check if we found a legal integer type creating a meaningful |
--- |
19957 |
// Check if we found a legal integer type creating a meaningful |
--- |
| 19958 |
// merge. |
--- |
19958 |
// merge. |
--- |
| 19959 |
if (NumStoresToMerge < 2) { |
0 |
19959 |
if (NumStoresToMerge < 2) { |
0 |
| 19960 |
// We know that candidate stores are in order and of correct |
--- |
19960 |
// We know that candidate stores are in order and of correct |
--- |
| 19961 |
// shape. While there is no mergeable sequence from the |
--- |
19961 |
// shape. While there is no mergeable sequence from the |
--- |
| 19962 |
// beginning one may start later in the sequence. The only |
--- |
19962 |
// beginning one may start later in the sequence. The only |
--- |
| 19963 |
// reason a merge of size N could have failed where another of |
--- |
19963 |
// reason a merge of size N could have failed where another of |
--- |
| 19964 |
// the same size would not have, is if the alignment has |
--- |
19964 |
// the same size would not have, is if the alignment has |
--- |
| 19965 |
// improved. Drop as many candidates as we can here. |
--- |
19965 |
// improved. Drop as many candidates as we can here. |
--- |
| 19966 |
unsigned NumSkip = 1; |
0 |
19966 |
unsigned NumSkip = 1; |
0 |
| 19967 |
while ((NumSkip < NumConsecutiveStores) && |
0 |
19967 |
while ((NumSkip < NumConsecutiveStores) && |
0 |
| 19968 |
(StoreNodes[NumSkip].MemNode->getAlign() <= FirstStoreAlign)) |
0 |
19968 |
(StoreNodes[NumSkip].MemNode->getAlign() <= FirstStoreAlign)) |
0 |
| 19969 |
NumSkip++; |
0 |
19969 |
NumSkip++; |
0 |
| 19970 |
|
--- |
19970 |
|
--- |
| 19971 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumSkip); |
0 |
19971 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumSkip); |
0 |
| 19972 |
NumConsecutiveStores -= NumSkip; |
0 |
19972 |
NumConsecutiveStores -= NumSkip; |
0 |
| 19973 |
continue; |
0 |
19973 |
continue; |
0 |
| 19974 |
} |
0 |
19974 |
} |
0 |
| 19975 |
|
--- |
19975 |
|
--- |
| 19976 |
// Check that we can merge these candidates without causing a cycle. |
--- |
19976 |
// Check that we can merge these candidates without causing a cycle. |
--- |
| 19977 |
if (!checkMergeStoreCandidatesForDependencies(StoreNodes, NumStoresToMerge, |
0 |
19977 |
if (!checkMergeStoreCandidatesForDependencies(StoreNodes, NumStoresToMerge, |
0 |
| 19978 |
RootNode)) { |
--- |
19978 |
RootNode)) { |
--- |
| 19979 |
StoreNodes.erase(StoreNodes.begin(), |
0 |
19979 |
StoreNodes.erase(StoreNodes.begin(), |
0 |
| 19980 |
StoreNodes.begin() + NumStoresToMerge); |
0 |
19980 |
StoreNodes.begin() + NumStoresToMerge); |
0 |
| 19981 |
NumConsecutiveStores -= NumStoresToMerge; |
0 |
19981 |
NumConsecutiveStores -= NumStoresToMerge; |
0 |
| 19982 |
continue; |
0 |
19982 |
continue; |
0 |
| 19983 |
} |
--- |
19983 |
} |
--- |
| 19984 |
|
--- |
19984 |
|
--- |
| 19985 |
MadeChange |= mergeStoresOfConstantsOrVecElts( |
0 |
19985 |
MadeChange |= mergeStoresOfConstantsOrVecElts( |
0 |
| 19986 |
StoreNodes, MemVT, NumStoresToMerge, /*IsConstantSrc*/ false, |
--- |
19986 |
StoreNodes, MemVT, NumStoresToMerge, /*IsConstantSrc*/ false, |
--- |
| 19987 |
/*UseVector*/ true, /*UseTrunc*/ false); |
--- |
19987 |
/*UseVector*/ true, /*UseTrunc*/ false); |
--- |
| 19988 |
|
--- |
19988 |
|
--- |
| 19989 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumStoresToMerge); |
0 |
19989 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumStoresToMerge); |
0 |
| 19990 |
NumConsecutiveStores -= NumStoresToMerge; |
0 |
19990 |
NumConsecutiveStores -= NumStoresToMerge; |
0 |
| 19991 |
} |
--- |
19991 |
} |
--- |
| 19992 |
return MadeChange; |
0 |
19992 |
return MadeChange; |
0 |
| 19993 |
} |
--- |
19993 |
} |
--- |
| 19994 |
|
--- |
19994 |
|
--- |
| 19995 |
bool DAGCombiner::tryStoreMergeOfLoads(SmallVectorImpl &StoreNodes, |
0 |
19995 |
bool DAGCombiner::tryStoreMergeOfLoads(SmallVectorImpl &StoreNodes, |
0 |
| 19996 |
unsigned NumConsecutiveStores, EVT MemVT, |
--- |
19996 |
unsigned NumConsecutiveStores, EVT MemVT, |
--- |
| 19997 |
SDNode *RootNode, bool AllowVectors, |
--- |
19997 |
SDNode *RootNode, bool AllowVectors, |
--- |
| 19998 |
bool IsNonTemporalStore, |
--- |
19998 |
bool IsNonTemporalStore, |
--- |
| 19999 |
bool IsNonTemporalLoad) { |
--- |
19999 |
bool IsNonTemporalLoad) { |
--- |
| 20000 |
LLVMContext &Context = *DAG.getContext(); |
0 |
20000 |
LLVMContext &Context = *DAG.getContext(); |
0 |
| 20001 |
const DataLayout &DL = DAG.getDataLayout(); |
0 |
20001 |
const DataLayout &DL = DAG.getDataLayout(); |
0 |
| 20002 |
int64_t ElementSizeBytes = MemVT.getStoreSize(); |
0 |
20002 |
int64_t ElementSizeBytes = MemVT.getStoreSize(); |
0 |
| 20003 |
unsigned NumMemElts = MemVT.isVector() ? MemVT.getVectorNumElements() : 1; |
0 |
20003 |
unsigned NumMemElts = MemVT.isVector() ? MemVT.getVectorNumElements() : 1; |
0 |
| 20004 |
bool MadeChange = false; |
0 |
20004 |
bool MadeChange = false; |
0 |
| 20005 |
|
--- |
20005 |
|
--- |
| 20006 |
// Look for load nodes which are used by the stored values. |
--- |
20006 |
// Look for load nodes which are used by the stored values. |
--- |
| 20007 |
SmallVector LoadNodes; |
0 |
20007 |
SmallVector LoadNodes; |
0 |
| 20008 |
|
--- |
20008 |
|
--- |
| 20009 |
// Find acceptable loads. Loads need to have the same chain (token factor), |
--- |
20009 |
// Find acceptable loads. Loads need to have the same chain (token factor), |
--- |
| 20010 |
// must not be zext, volatile, indexed, and they must be consecutive. |
--- |
20010 |
// must not be zext, volatile, indexed, and they must be consecutive. |
--- |
| 20011 |
BaseIndexOffset LdBasePtr; |
0 |
20011 |
BaseIndexOffset LdBasePtr; |
0 |
| 20012 |
|
--- |
20012 |
|
--- |
| 20013 |
for (unsigned i = 0; i < NumConsecutiveStores; ++i) { |
0 |
20013 |
for (unsigned i = 0; i < NumConsecutiveStores; ++i) { |
0 |
| 20014 |
StoreSDNode *St = cast(StoreNodes[i].MemNode); |
0 |
20014 |
StoreSDNode *St = cast(StoreNodes[i].MemNode); |
0 |
| 20015 |
SDValue Val = peekThroughBitcasts(St->getValue()); |
0 |
20015 |
SDValue Val = peekThroughBitcasts(St->getValue()); |
0 |
| 20016 |
LoadSDNode *Ld = cast(Val); |
0 |
20016 |
LoadSDNode *Ld = cast(Val); |
0 |
| 20017 |
|
--- |
20017 |
|
--- |
| 20018 |
BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld, DAG); |
0 |
20018 |
BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld, DAG); |
0 |
| 20019 |
// If this is not the first ptr that we check. |
--- |
20019 |
// If this is not the first ptr that we check. |
--- |
| 20020 |
int64_t LdOffset = 0; |
0 |
20020 |
int64_t LdOffset = 0; |
0 |
| 20021 |
if (LdBasePtr.getBase().getNode()) { |
0 |
20021 |
if (LdBasePtr.getBase().getNode()) { |
0 |
| 20022 |
// The base ptr must be the same. |
--- |
20022 |
// The base ptr must be the same. |
--- |
| 20023 |
if (!LdBasePtr.equalBaseIndex(LdPtr, DAG, LdOffset)) |
0 |
20023 |
if (!LdBasePtr.equalBaseIndex(LdPtr, DAG, LdOffset)) |
0 |
| 20024 |
break; |
0 |
20024 |
break; |
0 |
| 20025 |
} else { |
--- |
20025 |
} else { |
--- |
| 20026 |
// Check that all other base pointers are the same as this one. |
--- |
20026 |
// Check that all other base pointers are the same as this one. |
--- |
| 20027 |
LdBasePtr = LdPtr; |
0 |
20027 |
LdBasePtr = LdPtr; |
0 |
| 20028 |
} |
--- |
20028 |
} |
--- |
| 20029 |
|
--- |
20029 |
|
--- |
| 20030 |
// We found a potential memory operand to merge. |
--- |
20030 |
// We found a potential memory operand to merge. |
--- |
| 20031 |
LoadNodes.push_back(MemOpLink(Ld, LdOffset)); |
0 |
20031 |
LoadNodes.push_back(MemOpLink(Ld, LdOffset)); |
0 |
| 20032 |
} |
--- |
20032 |
} |
--- |
| 20033 |
|
--- |
20033 |
|
--- |
| 20034 |
while (NumConsecutiveStores >= 2 && LoadNodes.size() >= 2) { |
0 |
20034 |
while (NumConsecutiveStores >= 2 && LoadNodes.size() >= 2) { |
0 |
| 20035 |
Align RequiredAlignment; |
0 |
20035 |
Align RequiredAlignment; |
0 |
| 20036 |
bool NeedRotate = false; |
0 |
20036 |
bool NeedRotate = false; |
0 |
| 20037 |
if (LoadNodes.size() == 2) { |
0 |
20037 |
if (LoadNodes.size() == 2) { |
0 |
| 20038 |
// If we have load/store pair instructions and we only have two values, |
--- |
20038 |
// If we have load/store pair instructions and we only have two values, |
--- |
| 20039 |
// don't bother merging. |
--- |
20039 |
// don't bother merging. |
--- |
| 20040 |
if (TLI.hasPairedLoad(MemVT, RequiredAlignment) && |
0 |
20040 |
if (TLI.hasPairedLoad(MemVT, RequiredAlignment) && |
0 |
| 20041 |
StoreNodes[0].MemNode->getAlign() >= RequiredAlignment) { |
0 |
20041 |
StoreNodes[0].MemNode->getAlign() >= RequiredAlignment) { |
0 |
| 20042 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + 2); |
0 |
20042 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + 2); |
0 |
| 20043 |
LoadNodes.erase(LoadNodes.begin(), LoadNodes.begin() + 2); |
0 |
20043 |
LoadNodes.erase(LoadNodes.begin(), LoadNodes.begin() + 2); |
0 |
| 20044 |
break; |
0 |
20044 |
break; |
0 |
| 20045 |
} |
--- |
20045 |
} |
--- |
| 20046 |
// If the loads are reversed, see if we can rotate the halves into place. |
--- |
20046 |
// If the loads are reversed, see if we can rotate the halves into place. |
--- |
| 20047 |
int64_t Offset0 = LoadNodes[0].OffsetFromBase; |
0 |
20047 |
int64_t Offset0 = LoadNodes[0].OffsetFromBase; |
0 |
| 20048 |
int64_t Offset1 = LoadNodes[1].OffsetFromBase; |
0 |
20048 |
int64_t Offset1 = LoadNodes[1].OffsetFromBase; |
0 |
| 20049 |
EVT PairVT = EVT::getIntegerVT(Context, ElementSizeBytes * 8 * 2); |
0 |
20049 |
EVT PairVT = EVT::getIntegerVT(Context, ElementSizeBytes * 8 * 2); |
0 |
| 20050 |
if (Offset0 - Offset1 == ElementSizeBytes && |
0 |
20050 |
if (Offset0 - Offset1 == ElementSizeBytes && |
0 |
| 20051 |
(hasOperation(ISD::ROTL, PairVT) || |
0 |
20051 |
(hasOperation(ISD::ROTL, PairVT) || |
0 |
| 20052 |
hasOperation(ISD::ROTR, PairVT))) { |
0 |
20052 |
hasOperation(ISD::ROTR, PairVT))) { |
0 |
| 20053 |
std::swap(LoadNodes[0], LoadNodes[1]); |
0 |
20053 |
std::swap(LoadNodes[0], LoadNodes[1]); |
0 |
| 20054 |
NeedRotate = true; |
0 |
20054 |
NeedRotate = true; |
0 |
| 20055 |
} |
--- |
20055 |
} |
--- |
| 20056 |
} |
--- |
20056 |
} |
--- |
| 20057 |
LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; |
0 |
20057 |
LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; |
0 |
| 20058 |
unsigned FirstStoreAS = FirstInChain->getAddressSpace(); |
0 |
20058 |
unsigned FirstStoreAS = FirstInChain->getAddressSpace(); |
0 |
| 20059 |
Align FirstStoreAlign = FirstInChain->getAlign(); |
0 |
20059 |
Align FirstStoreAlign = FirstInChain->getAlign(); |
0 |
| 20060 |
LoadSDNode *FirstLoad = cast(LoadNodes[0].MemNode); |
0 |
20060 |
LoadSDNode *FirstLoad = cast(LoadNodes[0].MemNode); |
0 |
| 20061 |
|
--- |
20061 |
|
--- |
| 20062 |
// Scan the memory operations on the chain and find the first |
--- |
20062 |
// Scan the memory operations on the chain and find the first |
--- |
| 20063 |
// non-consecutive load memory address. These variables hold the index in |
--- |
20063 |
// non-consecutive load memory address. These variables hold the index in |
--- |
| 20064 |
// the store node array. |
--- |
20064 |
// the store node array. |
--- |
| 20065 |
|
--- |
20065 |
|
--- |
| 20066 |
unsigned LastConsecutiveLoad = 1; |
0 |
20066 |
unsigned LastConsecutiveLoad = 1; |
0 |
| 20067 |
|
--- |
20067 |
|
--- |
| 20068 |
// This variable refers to the size and not index in the array. |
--- |
20068 |
// This variable refers to the size and not index in the array. |
--- |
| 20069 |
unsigned LastLegalVectorType = 1; |
0 |
20069 |
unsigned LastLegalVectorType = 1; |
0 |
| 20070 |
unsigned LastLegalIntegerType = 1; |
0 |
20070 |
unsigned LastLegalIntegerType = 1; |
0 |
| 20071 |
bool isDereferenceable = true; |
0 |
20071 |
bool isDereferenceable = true; |
0 |
| 20072 |
bool DoIntegerTruncate = false; |
0 |
20072 |
bool DoIntegerTruncate = false; |
0 |
| 20073 |
int64_t StartAddress = LoadNodes[0].OffsetFromBase; |
0 |
20073 |
int64_t StartAddress = LoadNodes[0].OffsetFromBase; |
0 |
| 20074 |
SDValue LoadChain = FirstLoad->getChain(); |
0 |
20074 |
SDValue LoadChain = FirstLoad->getChain(); |
0 |
| 20075 |
for (unsigned i = 1; i < LoadNodes.size(); ++i) { |
0 |
20075 |
for (unsigned i = 1; i < LoadNodes.size(); ++i) { |
0 |
| 20076 |
// All loads must share the same chain. |
--- |
20076 |
// All loads must share the same chain. |
--- |
| 20077 |
if (LoadNodes[i].MemNode->getChain() != LoadChain) |
0 |
20077 |
if (LoadNodes[i].MemNode->getChain() != LoadChain) |
0 |
| 20078 |
break; |
0 |
20078 |
break; |
0 |
| 20079 |
|
--- |
20079 |
|
--- |
| 20080 |
int64_t CurrAddress = LoadNodes[i].OffsetFromBase; |
0 |
20080 |
int64_t CurrAddress = LoadNodes[i].OffsetFromBase; |
0 |
| 20081 |
if (CurrAddress - StartAddress != (ElementSizeBytes * i)) |
0 |
20081 |
if (CurrAddress - StartAddress != (ElementSizeBytes * i)) |
0 |
| 20082 |
break; |
0 |
20082 |
break; |
0 |
| 20083 |
LastConsecutiveLoad = i; |
0 |
20083 |
LastConsecutiveLoad = i; |
0 |
| 20084 |
|
--- |
20084 |
|
--- |
| 20085 |
if (isDereferenceable && !LoadNodes[i].MemNode->isDereferenceable()) |
0 |
20085 |
if (isDereferenceable && !LoadNodes[i].MemNode->isDereferenceable()) |
0 |
| 20086 |
isDereferenceable = false; |
0 |
20086 |
isDereferenceable = false; |
0 |
| 20087 |
|
--- |
20087 |
|
--- |
| 20088 |
// Find a legal type for the vector store. |
--- |
20088 |
// Find a legal type for the vector store. |
--- |
| 20089 |
unsigned Elts = (i + 1) * NumMemElts; |
0 |
20089 |
unsigned Elts = (i + 1) * NumMemElts; |
0 |
| 20090 |
EVT StoreTy = EVT::getVectorVT(Context, MemVT.getScalarType(), Elts); |
0 |
20090 |
EVT StoreTy = EVT::getVectorVT(Context, MemVT.getScalarType(), Elts); |
0 |
| 20091 |
|
--- |
20091 |
|
--- |
| 20092 |
// Break early when size is too large to be legal. |
--- |
20092 |
// Break early when size is too large to be legal. |
--- |
| 20093 |
if (StoreTy.getSizeInBits() > MaximumLegalStoreInBits) |
0 |
20093 |
if (StoreTy.getSizeInBits() > MaximumLegalStoreInBits) |
0 |
| 20094 |
break; |
0 |
20094 |
break; |
0 |
| 20095 |
|
--- |
20095 |
|
--- |
| 20096 |
unsigned IsFastSt = 0; |
0 |
20096 |
unsigned IsFastSt = 0; |
0 |
| 20097 |
unsigned IsFastLd = 0; |
0 |
20097 |
unsigned IsFastLd = 0; |
0 |
| 20098 |
// Don't try vector types if we need a rotate. We may still fail the |
--- |
20098 |
// Don't try vector types if we need a rotate. We may still fail the |
--- |
| 20099 |
// legality checks for the integer type, but we can't handle the rotate |
--- |
20099 |
// legality checks for the integer type, but we can't handle the rotate |
--- |
| 20100 |
// case with vectors. |
--- |
20100 |
// case with vectors. |
--- |
| 20101 |
// FIXME: We could use a shuffle in place of the rotate. |
--- |
20101 |
// FIXME: We could use a shuffle in place of the rotate. |
--- |
| 20102 |
if (!NeedRotate && TLI.isTypeLegal(StoreTy) && |
0 |
20102 |
if (!NeedRotate && TLI.isTypeLegal(StoreTy) && |
0 |
| 20103 |
TLI.canMergeStoresTo(FirstStoreAS, StoreTy, |
0 |
20103 |
TLI.canMergeStoresTo(FirstStoreAS, StoreTy, |
0 |
| 20104 |
DAG.getMachineFunction()) && |
0 |
20104 |
DAG.getMachineFunction()) && |
0 |
| 20105 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
20105 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
| 20106 |
*FirstInChain->getMemOperand(), &IsFastSt) && |
0 |
20106 |
*FirstInChain->getMemOperand(), &IsFastSt) && |
0 |
| 20107 |
IsFastSt && |
0 |
20107 |
IsFastSt && |
0 |
| 20108 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
20108 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
| 20109 |
*FirstLoad->getMemOperand(), &IsFastLd) && |
0 |
20109 |
*FirstLoad->getMemOperand(), &IsFastLd) && |
0 |
| 20110 |
IsFastLd) { |
0 |
20110 |
IsFastLd) { |
0 |
| 20111 |
LastLegalVectorType = i + 1; |
0 |
20111 |
LastLegalVectorType = i + 1; |
0 |
| 20112 |
} |
--- |
20112 |
} |
--- |
| 20113 |
|
--- |
20113 |
|
--- |
| 20114 |
// Find a legal type for the integer store. |
--- |
20114 |
// Find a legal type for the integer store. |
--- |
| 20115 |
unsigned SizeInBits = (i + 1) * ElementSizeBytes * 8; |
0 |
20115 |
unsigned SizeInBits = (i + 1) * ElementSizeBytes * 8; |
0 |
| 20116 |
StoreTy = EVT::getIntegerVT(Context, SizeInBits); |
0 |
20116 |
StoreTy = EVT::getIntegerVT(Context, SizeInBits); |
0 |
| 20117 |
if (TLI.isTypeLegal(StoreTy) && |
0 |
20117 |
if (TLI.isTypeLegal(StoreTy) && |
0 |
| 20118 |
TLI.canMergeStoresTo(FirstStoreAS, StoreTy, |
0 |
20118 |
TLI.canMergeStoresTo(FirstStoreAS, StoreTy, |
0 |
| 20119 |
DAG.getMachineFunction()) && |
0 |
20119 |
DAG.getMachineFunction()) && |
0 |
| 20120 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
20120 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
| 20121 |
*FirstInChain->getMemOperand(), &IsFastSt) && |
0 |
20121 |
*FirstInChain->getMemOperand(), &IsFastSt) && |
0 |
| 20122 |
IsFastSt && |
0 |
20122 |
IsFastSt && |
0 |
| 20123 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
20123 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
| 20124 |
*FirstLoad->getMemOperand(), &IsFastLd) && |
0 |
20124 |
*FirstLoad->getMemOperand(), &IsFastLd) && |
0 |
| 20125 |
IsFastLd) { |
0 |
20125 |
IsFastLd) { |
0 |
| 20126 |
LastLegalIntegerType = i + 1; |
0 |
20126 |
LastLegalIntegerType = i + 1; |
0 |
| 20127 |
DoIntegerTruncate = false; |
0 |
20127 |
DoIntegerTruncate = false; |
0 |
| 20128 |
// Or check whether a truncstore and extload is legal. |
--- |
20128 |
// Or check whether a truncstore and extload is legal. |
--- |
| 20129 |
} else if (TLI.getTypeAction(Context, StoreTy) == |
0 |
20129 |
} else if (TLI.getTypeAction(Context, StoreTy) == |
0 |
| 20130 |
TargetLowering::TypePromoteInteger) { |
--- |
20130 |
TargetLowering::TypePromoteInteger) { |
--- |
| 20131 |
EVT LegalizedStoredValTy = TLI.getTypeToTransformTo(Context, StoreTy); |
0 |
20131 |
EVT LegalizedStoredValTy = TLI.getTypeToTransformTo(Context, StoreTy); |
0 |
| 20132 |
if (TLI.isTruncStoreLegal(LegalizedStoredValTy, StoreTy) && |
0 |
20132 |
if (TLI.isTruncStoreLegal(LegalizedStoredValTy, StoreTy) && |
0 |
| 20133 |
TLI.canMergeStoresTo(FirstStoreAS, LegalizedStoredValTy, |
0 |
20133 |
TLI.canMergeStoresTo(FirstStoreAS, LegalizedStoredValTy, |
0 |
| 20134 |
DAG.getMachineFunction()) && |
0 |
20134 |
DAG.getMachineFunction()) && |
0 |
| 20135 |
TLI.isLoadExtLegal(ISD::ZEXTLOAD, LegalizedStoredValTy, StoreTy) && |
0 |
20135 |
TLI.isLoadExtLegal(ISD::ZEXTLOAD, LegalizedStoredValTy, StoreTy) && |
0 |
| 20136 |
TLI.isLoadExtLegal(ISD::SEXTLOAD, LegalizedStoredValTy, StoreTy) && |
0 |
20136 |
TLI.isLoadExtLegal(ISD::SEXTLOAD, LegalizedStoredValTy, StoreTy) && |
0 |
| 20137 |
TLI.isLoadExtLegal(ISD::EXTLOAD, LegalizedStoredValTy, StoreTy) && |
0 |
20137 |
TLI.isLoadExtLegal(ISD::EXTLOAD, LegalizedStoredValTy, StoreTy) && |
0 |
| 20138 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
20138 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
| 20139 |
*FirstInChain->getMemOperand(), &IsFastSt) && |
0 |
20139 |
*FirstInChain->getMemOperand(), &IsFastSt) && |
0 |
| 20140 |
IsFastSt && |
0 |
20140 |
IsFastSt && |
0 |
| 20141 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
20141 |
TLI.allowsMemoryAccess(Context, DL, StoreTy, |
0 |
| 20142 |
*FirstLoad->getMemOperand(), &IsFastLd) && |
0 |
20142 |
*FirstLoad->getMemOperand(), &IsFastLd) && |
0 |
| 20143 |
IsFastLd) { |
0 |
20143 |
IsFastLd) { |
0 |
| 20144 |
LastLegalIntegerType = i + 1; |
0 |
20144 |
LastLegalIntegerType = i + 1; |
0 |
| 20145 |
DoIntegerTruncate = true; |
0 |
20145 |
DoIntegerTruncate = true; |
0 |
| 20146 |
} |
--- |
20146 |
} |
--- |
| 20147 |
} |
--- |
20147 |
} |
--- |
| 20148 |
} |
--- |
20148 |
} |
--- |
| 20149 |
|
--- |
20149 |
|
--- |
| 20150 |
// Only use vector types if the vector type is larger than the integer |
--- |
20150 |
// Only use vector types if the vector type is larger than the integer |
--- |
| 20151 |
// type. If they are the same, use integers. |
--- |
20151 |
// type. If they are the same, use integers. |
--- |
| 20152 |
bool UseVectorTy = |
0 |
20152 |
bool UseVectorTy = |
0 |
| 20153 |
LastLegalVectorType > LastLegalIntegerType && AllowVectors; |
0 |
20153 |
LastLegalVectorType > LastLegalIntegerType && AllowVectors; |
0 |
| 20154 |
unsigned LastLegalType = |
--- |
20154 |
unsigned LastLegalType = |
--- |
| 20155 |
std::max(LastLegalVectorType, LastLegalIntegerType); |
0 |
20155 |
std::max(LastLegalVectorType, LastLegalIntegerType); |
0 |
| 20156 |
|
--- |
20156 |
|
--- |
| 20157 |
// We add +1 here because the LastXXX variables refer to location while |
--- |
20157 |
// We add +1 here because the LastXXX variables refer to location while |
--- |
| 20158 |
// the NumElem refers to array/index size. |
--- |
20158 |
// the NumElem refers to array/index size. |
--- |
| 20159 |
unsigned NumElem = std::min(NumConsecutiveStores, LastConsecutiveLoad + 1); |
0 |
20159 |
unsigned NumElem = std::min(NumConsecutiveStores, LastConsecutiveLoad + 1); |
0 |
| 20160 |
NumElem = std::min(LastLegalType, NumElem); |
0 |
20160 |
NumElem = std::min(LastLegalType, NumElem); |
0 |
| 20161 |
Align FirstLoadAlign = FirstLoad->getAlign(); |
0 |
20161 |
Align FirstLoadAlign = FirstLoad->getAlign(); |
0 |
| 20162 |
|
--- |
20162 |
|
--- |
| 20163 |
if (NumElem < 2) { |
0 |
20163 |
if (NumElem < 2) { |
0 |
| 20164 |
// We know that candidate stores are in order and of correct |
--- |
20164 |
// We know that candidate stores are in order and of correct |
--- |
| 20165 |
// shape. While there is no mergeable sequence from the |
--- |
20165 |
// shape. While there is no mergeable sequence from the |
--- |
| 20166 |
// beginning one may start later in the sequence. The only |
--- |
20166 |
// beginning one may start later in the sequence. The only |
--- |
| 20167 |
// reason a merge of size N could have failed where another of |
--- |
20167 |
// reason a merge of size N could have failed where another of |
--- |
| 20168 |
// the same size would not have is if the alignment or either |
--- |
20168 |
// the same size would not have is if the alignment or either |
--- |
| 20169 |
// the load or store has improved. Drop as many candidates as we |
--- |
20169 |
// the load or store has improved. Drop as many candidates as we |
--- |
| 20170 |
// can here. |
--- |
20170 |
// can here. |
--- |
| 20171 |
unsigned NumSkip = 1; |
0 |
20171 |
unsigned NumSkip = 1; |
0 |
| 20172 |
while ((NumSkip < LoadNodes.size()) && |
0 |
20172 |
while ((NumSkip < LoadNodes.size()) && |
0 |
| 20173 |
(LoadNodes[NumSkip].MemNode->getAlign() <= FirstLoadAlign) && |
0 |
20173 |
(LoadNodes[NumSkip].MemNode->getAlign() <= FirstLoadAlign) && |
0 |
| 20174 |
(StoreNodes[NumSkip].MemNode->getAlign() <= FirstStoreAlign)) |
0 |
20174 |
(StoreNodes[NumSkip].MemNode->getAlign() <= FirstStoreAlign)) |
0 |
| 20175 |
NumSkip++; |
0 |
20175 |
NumSkip++; |
0 |
| 20176 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumSkip); |
0 |
20176 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumSkip); |
0 |
| 20177 |
LoadNodes.erase(LoadNodes.begin(), LoadNodes.begin() + NumSkip); |
0 |
20177 |
LoadNodes.erase(LoadNodes.begin(), LoadNodes.begin() + NumSkip); |
0 |
| 20178 |
NumConsecutiveStores -= NumSkip; |
0 |
20178 |
NumConsecutiveStores -= NumSkip; |
0 |
| 20179 |
continue; |
0 |
20179 |
continue; |
0 |
| 20180 |
} |
0 |
20180 |
} |
0 |
| 20181 |
|
--- |
20181 |
|
--- |
| 20182 |
// Check that we can merge these candidates without causing a cycle. |
--- |
20182 |
// Check that we can merge these candidates without causing a cycle. |
--- |
| 20183 |
if (!checkMergeStoreCandidatesForDependencies(StoreNodes, NumElem, |
0 |
20183 |
if (!checkMergeStoreCandidatesForDependencies(StoreNodes, NumElem, |
0 |
| 20184 |
RootNode)) { |
--- |
20184 |
RootNode)) { |
--- |
| 20185 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumElem); |
0 |
20185 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumElem); |
0 |
| 20186 |
LoadNodes.erase(LoadNodes.begin(), LoadNodes.begin() + NumElem); |
0 |
20186 |
LoadNodes.erase(LoadNodes.begin(), LoadNodes.begin() + NumElem); |
0 |
| 20187 |
NumConsecutiveStores -= NumElem; |
0 |
20187 |
NumConsecutiveStores -= NumElem; |
0 |
| 20188 |
continue; |
0 |
20188 |
continue; |
0 |
| 20189 |
} |
--- |
20189 |
} |
--- |
| 20190 |
|
--- |
20190 |
|
--- |
| 20191 |
// Find if it is better to use vectors or integers to load and store |
--- |
20191 |
// Find if it is better to use vectors or integers to load and store |
--- |
| 20192 |
// to memory. |
--- |
20192 |
// to memory. |
--- |
| 20193 |
EVT JointMemOpVT; |
0 |
20193 |
EVT JointMemOpVT; |
0 |
| 20194 |
if (UseVectorTy) { |
0 |
20194 |
if (UseVectorTy) { |
0 |
| 20195 |
// Find a legal type for the vector store. |
--- |
20195 |
// Find a legal type for the vector store. |
--- |
| 20196 |
unsigned Elts = NumElem * NumMemElts; |
0 |
20196 |
unsigned Elts = NumElem * NumMemElts; |
0 |
| 20197 |
JointMemOpVT = EVT::getVectorVT(Context, MemVT.getScalarType(), Elts); |
0 |
20197 |
JointMemOpVT = EVT::getVectorVT(Context, MemVT.getScalarType(), Elts); |
0 |
| 20198 |
} else { |
--- |
20198 |
} else { |
--- |
| 20199 |
unsigned SizeInBits = NumElem * ElementSizeBytes * 8; |
0 |
20199 |
unsigned SizeInBits = NumElem * ElementSizeBytes * 8; |
0 |
| 20200 |
JointMemOpVT = EVT::getIntegerVT(Context, SizeInBits); |
0 |
20200 |
JointMemOpVT = EVT::getIntegerVT(Context, SizeInBits); |
0 |
| 20201 |
} |
--- |
20201 |
} |
--- |
| 20202 |
|
--- |
20202 |
|
--- |
| 20203 |
SDLoc LoadDL(LoadNodes[0].MemNode); |
0 |
20203 |
SDLoc LoadDL(LoadNodes[0].MemNode); |
0 |
| 20204 |
SDLoc StoreDL(StoreNodes[0].MemNode); |
0 |
20204 |
SDLoc StoreDL(StoreNodes[0].MemNode); |
0 |
| 20205 |
|
--- |
20205 |
|
--- |
| 20206 |
// The merged loads are required to have the same incoming chain, so |
--- |
20206 |
// The merged loads are required to have the same incoming chain, so |
--- |
| 20207 |
// using the first's chain is acceptable. |
--- |
20207 |
// using the first's chain is acceptable. |
--- |
| 20208 |
|
--- |
20208 |
|
--- |
| 20209 |
SDValue NewStoreChain = getMergeStoreChains(StoreNodes, NumElem); |
0 |
20209 |
SDValue NewStoreChain = getMergeStoreChains(StoreNodes, NumElem); |
0 |
| 20210 |
bool CanReusePtrInfo = hasSameUnderlyingObj(StoreNodes); |
0 |
20210 |
bool CanReusePtrInfo = hasSameUnderlyingObj(StoreNodes); |
0 |
| 20211 |
AddToWorklist(NewStoreChain.getNode()); |
0 |
20211 |
AddToWorklist(NewStoreChain.getNode()); |
0 |
| 20212 |
|
--- |
20212 |
|
--- |
| 20213 |
MachineMemOperand::Flags LdMMOFlags = |
0 |
20213 |
MachineMemOperand::Flags LdMMOFlags = |
0 |
| 20214 |
isDereferenceable ? MachineMemOperand::MODereferenceable |
0 |
20214 |
isDereferenceable ? MachineMemOperand::MODereferenceable |
0 |
| 20215 |
: MachineMemOperand::MONone; |
--- |
20215 |
: MachineMemOperand::MONone; |
--- |
| 20216 |
if (IsNonTemporalLoad) |
0 |
20216 |
if (IsNonTemporalLoad) |
0 |
| 20217 |
LdMMOFlags |= MachineMemOperand::MONonTemporal; |
0 |
20217 |
LdMMOFlags |= MachineMemOperand::MONonTemporal; |
0 |
| 20218 |
|
--- |
20218 |
|
--- |
| 20219 |
LdMMOFlags |= TLI.getTargetMMOFlags(*FirstLoad); |
0 |
20219 |
LdMMOFlags |= TLI.getTargetMMOFlags(*FirstLoad); |
0 |
| 20220 |
|
--- |
20220 |
|
--- |
| 20221 |
MachineMemOperand::Flags StMMOFlags = IsNonTemporalStore |
0 |
20221 |
MachineMemOperand::Flags StMMOFlags = IsNonTemporalStore |
0 |
| 20222 |
? MachineMemOperand::MONonTemporal |
0 |
20222 |
? MachineMemOperand::MONonTemporal |
0 |
| 20223 |
: MachineMemOperand::MONone; |
--- |
20223 |
: MachineMemOperand::MONone; |
--- |
| 20224 |
|
--- |
20224 |
|
--- |
| 20225 |
StMMOFlags |= TLI.getTargetMMOFlags(*StoreNodes[0].MemNode); |
0 |
20225 |
StMMOFlags |= TLI.getTargetMMOFlags(*StoreNodes[0].MemNode); |
0 |
| 20226 |
|
--- |
20226 |
|
--- |
| 20227 |
SDValue NewLoad, NewStore; |
0 |
20227 |
SDValue NewLoad, NewStore; |
0 |
| 20228 |
if (UseVectorTy || !DoIntegerTruncate) { |
0 |
20228 |
if (UseVectorTy || !DoIntegerTruncate) { |
0 |
| 20229 |
NewLoad = DAG.getLoad( |
0 |
20229 |
NewLoad = DAG.getLoad( |
0 |
| 20230 |
JointMemOpVT, LoadDL, FirstLoad->getChain(), FirstLoad->getBasePtr(), |
0 |
20230 |
JointMemOpVT, LoadDL, FirstLoad->getChain(), FirstLoad->getBasePtr(), |
0 |
| 20231 |
FirstLoad->getPointerInfo(), FirstLoadAlign, LdMMOFlags); |
0 |
20231 |
FirstLoad->getPointerInfo(), FirstLoadAlign, LdMMOFlags); |
0 |
| 20232 |
SDValue StoreOp = NewLoad; |
0 |
20232 |
SDValue StoreOp = NewLoad; |
0 |
| 20233 |
if (NeedRotate) { |
0 |
20233 |
if (NeedRotate) { |
0 |
| 20234 |
unsigned LoadWidth = ElementSizeBytes * 8 * 2; |
0 |
20234 |
unsigned LoadWidth = ElementSizeBytes * 8 * 2; |
0 |
| 20235 |
assert(JointMemOpVT == EVT::getIntegerVT(Context, LoadWidth) && |
0 |
20235 |
assert(JointMemOpVT == EVT::getIntegerVT(Context, LoadWidth) && |
0 |
| 20236 |
"Unexpected type for rotate-able load pair"); |
--- |
20236 |
"Unexpected type for rotate-able load pair"); |
--- |
| 20237 |
SDValue RotAmt = |
--- |
20237 |
SDValue RotAmt = |
--- |
| 20238 |
DAG.getShiftAmountConstant(LoadWidth / 2, JointMemOpVT, LoadDL); |
0 |
20238 |
DAG.getShiftAmountConstant(LoadWidth / 2, JointMemOpVT, LoadDL); |
0 |
| 20239 |
// Target can convert to the identical ROTR if it does not have ROTL. |
--- |
20239 |
// Target can convert to the identical ROTR if it does not have ROTL. |
--- |
| 20240 |
StoreOp = DAG.getNode(ISD::ROTL, LoadDL, JointMemOpVT, NewLoad, RotAmt); |
0 |
20240 |
StoreOp = DAG.getNode(ISD::ROTL, LoadDL, JointMemOpVT, NewLoad, RotAmt); |
0 |
| 20241 |
} |
--- |
20241 |
} |
--- |
| 20242 |
NewStore = DAG.getStore( |
0 |
20242 |
NewStore = DAG.getStore( |
0 |
| 20243 |
NewStoreChain, StoreDL, StoreOp, FirstInChain->getBasePtr(), |
0 |
20243 |
NewStoreChain, StoreDL, StoreOp, FirstInChain->getBasePtr(), |
0 |
| 20244 |
CanReusePtrInfo ? FirstInChain->getPointerInfo() |
0 |
20244 |
CanReusePtrInfo ? FirstInChain->getPointerInfo() |
0 |
| 20245 |
: MachinePointerInfo(FirstStoreAS), |
--- |
20245 |
: MachinePointerInfo(FirstStoreAS), |
--- |
| 20246 |
FirstStoreAlign, StMMOFlags); |
--- |
20246 |
FirstStoreAlign, StMMOFlags); |
--- |
| 20247 |
} else { // This must be the truncstore/extload case |
0 |
20247 |
} else { // This must be the truncstore/extload case |
0 |
| 20248 |
EVT ExtendedTy = |
--- |
20248 |
EVT ExtendedTy = |
--- |
| 20249 |
TLI.getTypeToTransformTo(*DAG.getContext(), JointMemOpVT); |
0 |
20249 |
TLI.getTypeToTransformTo(*DAG.getContext(), JointMemOpVT); |
0 |
| 20250 |
NewLoad = DAG.getExtLoad(ISD::EXTLOAD, LoadDL, ExtendedTy, |
0 |
20250 |
NewLoad = DAG.getExtLoad(ISD::EXTLOAD, LoadDL, ExtendedTy, |
0 |
| 20251 |
FirstLoad->getChain(), FirstLoad->getBasePtr(), |
0 |
20251 |
FirstLoad->getChain(), FirstLoad->getBasePtr(), |
0 |
| 20252 |
FirstLoad->getPointerInfo(), JointMemOpVT, |
0 |
20252 |
FirstLoad->getPointerInfo(), JointMemOpVT, |
0 |
| 20253 |
FirstLoadAlign, LdMMOFlags); |
--- |
20253 |
FirstLoadAlign, LdMMOFlags); |
--- |
| 20254 |
NewStore = DAG.getTruncStore( |
0 |
20254 |
NewStore = DAG.getTruncStore( |
0 |
| 20255 |
NewStoreChain, StoreDL, NewLoad, FirstInChain->getBasePtr(), |
0 |
20255 |
NewStoreChain, StoreDL, NewLoad, FirstInChain->getBasePtr(), |
0 |
| 20256 |
CanReusePtrInfo ? FirstInChain->getPointerInfo() |
0 |
20256 |
CanReusePtrInfo ? FirstInChain->getPointerInfo() |
0 |
| 20257 |
: MachinePointerInfo(FirstStoreAS), |
--- |
20257 |
: MachinePointerInfo(FirstStoreAS), |
--- |
| 20258 |
JointMemOpVT, FirstInChain->getAlign(), |
--- |
20258 |
JointMemOpVT, FirstInChain->getAlign(), |
--- |
| 20259 |
FirstInChain->getMemOperand()->getFlags()); |
0 |
20259 |
FirstInChain->getMemOperand()->getFlags()); |
0 |
| 20260 |
} |
--- |
20260 |
} |
--- |
| 20261 |
|
--- |
20261 |
|
--- |
| 20262 |
// Transfer chain users from old loads to the new load. |
--- |
20262 |
// Transfer chain users from old loads to the new load. |
--- |
| 20263 |
for (unsigned i = 0; i < NumElem; ++i) { |
0 |
20263 |
for (unsigned i = 0; i < NumElem; ++i) { |
0 |
| 20264 |
LoadSDNode *Ld = cast(LoadNodes[i].MemNode); |
0 |
20264 |
LoadSDNode *Ld = cast(LoadNodes[i].MemNode); |
0 |
| 20265 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), |
0 |
20265 |
DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), |
0 |
| 20266 |
SDValue(NewLoad.getNode(), 1)); |
--- |
20266 |
SDValue(NewLoad.getNode(), 1)); |
--- |
| 20267 |
} |
--- |
20267 |
} |
--- |
| 20268 |
|
--- |
20268 |
|
--- |
| 20269 |
// Replace all stores with the new store. Recursively remove corresponding |
--- |
20269 |
// Replace all stores with the new store. Recursively remove corresponding |
--- |
| 20270 |
// values if they are no longer used. |
--- |
20270 |
// values if they are no longer used. |
--- |
| 20271 |
for (unsigned i = 0; i < NumElem; ++i) { |
0 |
20271 |
for (unsigned i = 0; i < NumElem; ++i) { |
0 |
| 20272 |
SDValue Val = StoreNodes[i].MemNode->getOperand(1); |
0 |
20272 |
SDValue Val = StoreNodes[i].MemNode->getOperand(1); |
0 |
| 20273 |
CombineTo(StoreNodes[i].MemNode, NewStore); |
0 |
20273 |
CombineTo(StoreNodes[i].MemNode, NewStore); |
0 |
| 20274 |
if (Val->use_empty()) |
0 |
20274 |
if (Val->use_empty()) |
0 |
| 20275 |
recursivelyDeleteUnusedNodes(Val.getNode()); |
0 |
20275 |
recursivelyDeleteUnusedNodes(Val.getNode()); |
0 |
| 20276 |
} |
--- |
20276 |
} |
--- |
| 20277 |
|
--- |
20277 |
|
--- |
| 20278 |
MadeChange = true; |
0 |
20278 |
MadeChange = true; |
0 |
| 20279 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumElem); |
0 |
20279 |
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumElem); |
0 |
| 20280 |
LoadNodes.erase(LoadNodes.begin(), LoadNodes.begin() + NumElem); |
0 |
20280 |
LoadNodes.erase(LoadNodes.begin(), LoadNodes.begin() + NumElem); |
0 |
| 20281 |
NumConsecutiveStores -= NumElem; |
0 |
20281 |
NumConsecutiveStores -= NumElem; |
0 |
| 20282 |
} |
0 |
20282 |
} |
0 |
| 20283 |
return MadeChange; |
0 |
20283 |
return MadeChange; |
0 |
| 20284 |
} |
0 |
20284 |
} |
0 |
| 20285 |
|
--- |
20285 |
|
--- |
| 20286 |
bool DAGCombiner::mergeConsecutiveStores(StoreSDNode *St) { |
10 |
20286 |
bool DAGCombiner::mergeConsecutiveStores(StoreSDNode *St) { |
10 |
| 20287 |
if (OptLevel == CodeGenOpt::None || !EnableStoreMerging) |
10 |
20287 |
if (OptLevel == CodeGenOpt::None || !EnableStoreMerging) |
10 |
| 20288 |
return false; |
10 |
20288 |
return false; |
10 |
| 20289 |
|
--- |
20289 |
|
--- |
| 20290 |
// TODO: Extend this function to merge stores of scalable vectors. |
--- |
20290 |
// TODO: Extend this function to merge stores of scalable vectors. |
--- |
| 20291 |
// (i.e. two stores can be merged to one |
--- |
20291 |
// (i.e. two stores can be merged to one |
--- |
| 20292 |
// store since we know is exactly twice as large as |
--- |
20292 |
// store since we know is exactly twice as large as |
--- |
| 20293 |
// ). Until then, bail out for scalable vectors. |
--- |
20293 |
// ). Until then, bail out for scalable vectors. |
--- |
| 20294 |
EVT MemVT = St->getMemoryVT(); |
0 |
20294 |
EVT MemVT = St->getMemoryVT(); |
0 |
| 20295 |
if (MemVT.isScalableVT()) |
0 |
20295 |
if (MemVT.isScalableVT()) |
0 |
| 20296 |
return false; |
0 |
20296 |
return false; |
0 |
| 20297 |
if (!MemVT.isSimple() || MemVT.getSizeInBits() * 2 > MaximumLegalStoreInBits) |
0 |
20297 |
if (!MemVT.isSimple() || MemVT.getSizeInBits() * 2 > MaximumLegalStoreInBits) |
0 |
| 20298 |
return false; |
0 |
20298 |
return false; |
0 |
| 20299 |
|
--- |
20299 |
|
--- |
| 20300 |
// This function cannot currently deal with non-byte-sized memory sizes. |
--- |
20300 |
// This function cannot currently deal with non-byte-sized memory sizes. |
--- |
| 20301 |
int64_t ElementSizeBytes = MemVT.getStoreSize(); |
0 |
20301 |
int64_t ElementSizeBytes = MemVT.getStoreSize(); |
0 |
| 20302 |
if (ElementSizeBytes * 8 != (int64_t)MemVT.getSizeInBits()) |
0 |
20302 |
if (ElementSizeBytes * 8 != (int64_t)MemVT.getSizeInBits()) |
0 |
| 20303 |
return false; |
0 |
20303 |
return false; |
0 |
| 20304 |
|
--- |
20304 |
|
--- |
| 20305 |
// Do not bother looking at stored values that are not constants, loads, or |
--- |
20305 |
// Do not bother looking at stored values that are not constants, loads, or |
--- |
| 20306 |
// extracted vector elements. |
--- |
20306 |
// extracted vector elements. |
--- |
| 20307 |
SDValue StoredVal = peekThroughBitcasts(St->getValue()); |
0 |
20307 |
SDValue StoredVal = peekThroughBitcasts(St->getValue()); |
0 |
| 20308 |
const StoreSource StoreSrc = getStoreSource(StoredVal); |
0 |
20308 |
const StoreSource StoreSrc = getStoreSource(StoredVal); |
0 |
| 20309 |
if (StoreSrc == StoreSource::Unknown) |
0 |
20309 |
if (StoreSrc == StoreSource::Unknown) |
0 |
| 20310 |
return false; |
0 |
20310 |
return false; |
0 |
| 20311 |
|
--- |
20311 |
|
--- |
| 20312 |
SmallVector StoreNodes; |
0 |
20312 |
SmallVector StoreNodes; |
0 |
| 20313 |
SDNode *RootNode; |
--- |
20313 |
SDNode *RootNode; |
--- |
| 20314 |
// Find potential store merge candidates by searching through chain sub-DAG |
--- |
20314 |
// Find potential store merge candidates by searching through chain sub-DAG |
--- |
| 20315 |
getStoreMergeCandidates(St, StoreNodes, RootNode); |
0 |
20315 |
getStoreMergeCandidates(St, StoreNodes, RootNode); |
0 |
| 20316 |
|
--- |
20316 |
|
--- |
| 20317 |
// Check if there is anything to merge. |
--- |
20317 |
// Check if there is anything to merge. |
--- |
| 20318 |
if (StoreNodes.size() < 2) |
0 |
20318 |
if (StoreNodes.size() < 2) |
0 |
| 20319 |
return false; |
0 |
20319 |
return false; |
0 |
| 20320 |
|
--- |
20320 |
|
--- |
| 20321 |
// Sort the memory operands according to their distance from the |
--- |
20321 |
// Sort the memory operands according to their distance from the |
--- |
| 20322 |
// base pointer. |
--- |
20322 |
// base pointer. |
--- |
| 20323 |
llvm::sort(StoreNodes, [](MemOpLink LHS, MemOpLink RHS) { |
0 |
20323 |
llvm::sort(StoreNodes, [](MemOpLink LHS, MemOpLink RHS) { |
0 |
| 20324 |
return LHS.OffsetFromBase < RHS.OffsetFromBase; |
0 |
20324 |
return LHS.OffsetFromBase < RHS.OffsetFromBase; |
0 |
| 20325 |
}); |
--- |
20325 |
}); |
--- |
| 20326 |
|
--- |
20326 |
|
--- |
| 20327 |
bool AllowVectors = !DAG.getMachineFunction().getFunction().hasFnAttribute( |
0 |
20327 |
bool AllowVectors = !DAG.getMachineFunction().getFunction().hasFnAttribute( |
0 |
| 20328 |
Attribute::NoImplicitFloat); |
0 |
20328 |
Attribute::NoImplicitFloat); |
0 |
| 20329 |
bool IsNonTemporalStore = St->isNonTemporal(); |
0 |
20329 |
bool IsNonTemporalStore = St->isNonTemporal(); |
0 |
| 20330 |
bool IsNonTemporalLoad = StoreSrc == StoreSource::Load && |
0 |
20330 |
bool IsNonTemporalLoad = StoreSrc == StoreSource::Load && |
0 |
| 20331 |
cast(StoredVal)->isNonTemporal(); |
0 |
20331 |
cast(StoredVal)->isNonTemporal(); |
0 |
| 20332 |
|
--- |
20332 |
|
--- |
| 20333 |
// Store Merge attempts to merge the lowest stores. This generally |
--- |
20333 |
// Store Merge attempts to merge the lowest stores. This generally |
--- |
| 20334 |
// works out as if successful, as the remaining stores are checked |
--- |
20334 |
// works out as if successful, as the remaining stores are checked |
--- |
| 20335 |
// after the first collection of stores is merged. However, in the |
--- |
20335 |
// after the first collection of stores is merged. However, in the |
--- |
| 20336 |
// case that a non-mergeable store is found first, e.g., {p[-2], |
--- |
20336 |
// case that a non-mergeable store is found first, e.g., {p[-2], |
--- |
| 20337 |
// p[0], p[1], p[2], p[3]}, we would fail and miss the subsequent |
--- |
20337 |
// p[0], p[1], p[2], p[3]}, we would fail and miss the subsequent |
--- |
| 20338 |
// mergeable cases. To prevent this, we prune such stores from the |
--- |
20338 |
// mergeable cases. To prevent this, we prune such stores from the |
--- |
| 20339 |
// front of StoreNodes here. |
--- |
20339 |
// front of StoreNodes here. |
--- |
| 20340 |
bool MadeChange = false; |
0 |
20340 |
bool MadeChange = false; |
0 |
| 20341 |
while (StoreNodes.size() > 1) { |
0 |
20341 |
while (StoreNodes.size() > 1) { |
0 |
| 20342 |
unsigned NumConsecutiveStores = |
--- |
20342 |
unsigned NumConsecutiveStores = |
--- |
| 20343 |
getConsecutiveStores(StoreNodes, ElementSizeBytes); |
0 |
20343 |
getConsecutiveStores(StoreNodes, ElementSizeBytes); |
0 |
| 20344 |
// There are no more stores in the list to examine. |
--- |
20344 |
// There are no more stores in the list to examine. |
--- |
| 20345 |
if (NumConsecutiveStores == 0) |
0 |
20345 |
if (NumConsecutiveStores == 0) |
0 |
| 20346 |
return MadeChange; |
0 |
20346 |
return MadeChange; |
0 |
| 20347 |
|
--- |
20347 |
|
--- |
| 20348 |
// We have at least 2 consecutive stores. Try to merge them. |
--- |
20348 |
// We have at least 2 consecutive stores. Try to merge them. |
--- |
| 20349 |
assert(NumConsecutiveStores >= 2 && "Expected at least 2 stores"); |
0 |
20349 |
assert(NumConsecutiveStores >= 2 && "Expected at least 2 stores"); |
0 |
| 20350 |
switch (StoreSrc) { |
0 |
20350 |
switch (StoreSrc) { |
0 |
| 20351 |
case StoreSource::Constant: |
0 |
20351 |
case StoreSource::Constant: |
0 |
| 20352 |
MadeChange |= tryStoreMergeOfConstants(StoreNodes, NumConsecutiveStores, |
0 |
20352 |
MadeChange |= tryStoreMergeOfConstants(StoreNodes, NumConsecutiveStores, |
0 |
| 20353 |
MemVT, RootNode, AllowVectors); |
--- |
20353 |
MemVT, RootNode, AllowVectors); |
--- |
| 20354 |
break; |
0 |
20354 |
break; |
0 |
| 20355 |
|
--- |
20355 |
|
--- |
| 20356 |
case StoreSource::Extract: |
0 |
20356 |
case StoreSource::Extract: |
0 |
| 20357 |
MadeChange |= tryStoreMergeOfExtracts(StoreNodes, NumConsecutiveStores, |
0 |
20357 |
MadeChange |= tryStoreMergeOfExtracts(StoreNodes, NumConsecutiveStores, |
0 |
| 20358 |
MemVT, RootNode); |
--- |
20358 |
MemVT, RootNode); |
--- |
| 20359 |
break; |
0 |
20359 |
break; |
0 |
| 20360 |
|
--- |
20360 |
|
--- |
| 20361 |
case StoreSource::Load: |
0 |
20361 |
case StoreSource::Load: |
0 |
| 20362 |
MadeChange |= tryStoreMergeOfLoads(StoreNodes, NumConsecutiveStores, |
0 |
20362 |
MadeChange |= tryStoreMergeOfLoads(StoreNodes, NumConsecutiveStores, |
0 |
| 20363 |
MemVT, RootNode, AllowVectors, |
--- |
20363 |
MemVT, RootNode, AllowVectors, |
--- |
| 20364 |
IsNonTemporalStore, IsNonTemporalLoad); |
--- |
20364 |
IsNonTemporalStore, IsNonTemporalLoad); |
--- |
| 20365 |
break; |
0 |
20365 |
break; |
0 |
| 20366 |
|
--- |
20366 |
|
--- |
| 20367 |
default: |
0 |
20367 |
default: |
0 |
| 20368 |
llvm_unreachable("Unhandled store source type"); |
0 |
20368 |
llvm_unreachable("Unhandled store source type"); |
0 |
| 20369 |
} |
--- |
20369 |
} |
--- |
| 20370 |
} |
--- |
20370 |
} |
--- |
| 20371 |
return MadeChange; |
0 |
20371 |
return MadeChange; |
0 |
| 20372 |
} |
0 |
20372 |
} |
0 |
| 20373 |
|
--- |
20373 |
|
--- |
| 20374 |
SDValue DAGCombiner::replaceStoreChain(StoreSDNode *ST, SDValue BetterChain) { |
0 |
20374 |
SDValue DAGCombiner::replaceStoreChain(StoreSDNode *ST, SDValue BetterChain) { |
0 |
| 20375 |
SDLoc SL(ST); |
0 |
20375 |
SDLoc SL(ST); |
0 |
| 20376 |
SDValue ReplStore; |
0 |
20376 |
SDValue ReplStore; |
0 |
| 20377 |
|
--- |
20377 |
|
--- |
| 20378 |
// Replace the chain to avoid dependency. |
--- |
20378 |
// Replace the chain to avoid dependency. |
--- |
| 20379 |
if (ST->isTruncatingStore()) { |
0 |
20379 |
if (ST->isTruncatingStore()) { |
0 |
| 20380 |
ReplStore = DAG.getTruncStore(BetterChain, SL, ST->getValue(), |
0 |
20380 |
ReplStore = DAG.getTruncStore(BetterChain, SL, ST->getValue(), |
0 |
| 20381 |
ST->getBasePtr(), ST->getMemoryVT(), |
0 |
20381 |
ST->getBasePtr(), ST->getMemoryVT(), |
0 |
| 20382 |
ST->getMemOperand()); |
--- |
20382 |
ST->getMemOperand()); |
--- |
| 20383 |
} else { |
--- |
20383 |
} else { |
--- |
| 20384 |
ReplStore = DAG.getStore(BetterChain, SL, ST->getValue(), ST->getBasePtr(), |
0 |
20384 |
ReplStore = DAG.getStore(BetterChain, SL, ST->getValue(), ST->getBasePtr(), |
0 |
| 20385 |
ST->getMemOperand()); |
--- |
20385 |
ST->getMemOperand()); |
--- |
| 20386 |
} |
--- |
20386 |
} |
--- |
| 20387 |
|
--- |
20387 |
|
--- |
| 20388 |
// Create token to keep both nodes around. |
--- |
20388 |
// Create token to keep both nodes around. |
--- |
| 20389 |
SDValue Token = DAG.getNode(ISD::TokenFactor, SL, |
0 |
20389 |
SDValue Token = DAG.getNode(ISD::TokenFactor, SL, |
0 |
| 20390 |
MVT::Other, ST->getChain(), ReplStore); |
0 |
20390 |
MVT::Other, ST->getChain(), ReplStore); |
0 |
| 20391 |
|
--- |
20391 |
|
--- |
| 20392 |
// Make sure the new and old chains are cleaned up. |
--- |
20392 |
// Make sure the new and old chains are cleaned up. |
--- |
| 20393 |
AddToWorklist(Token.getNode()); |
0 |
20393 |
AddToWorklist(Token.getNode()); |
0 |
| 20394 |
|
--- |
20394 |
|
--- |
| 20395 |
// Don't add users to work list. |
--- |
20395 |
// Don't add users to work list. |
--- |
| 20396 |
return CombineTo(ST, Token, false); |
0 |
20396 |
return CombineTo(ST, Token, false); |
0 |
| 20397 |
} |
0 |
20397 |
} |
0 |
| 20398 |
|
--- |
20398 |
|
--- |
| 20399 |
SDValue DAGCombiner::replaceStoreOfFPConstant(StoreSDNode *ST) { |
0 |
20399 |
SDValue DAGCombiner::replaceStoreOfFPConstant(StoreSDNode *ST) { |
0 |
| 20400 |
SDValue Value = ST->getValue(); |
0 |
20400 |
SDValue Value = ST->getValue(); |
0 |
| 20401 |
if (Value.getOpcode() == ISD::TargetConstantFP) |
0 |
20401 |
if (Value.getOpcode() == ISD::TargetConstantFP) |
0 |
| 20402 |
return SDValue(); |
0 |
20402 |
return SDValue(); |
0 |
| 20403 |
|
--- |
20403 |
|
--- |
| 20404 |
if (!ISD::isNormalStore(ST)) |
0 |
20404 |
if (!ISD::isNormalStore(ST)) |
0 |
| 20405 |
return SDValue(); |
0 |
20405 |
return SDValue(); |
0 |
| 20406 |
|
--- |
20406 |
|
--- |
| 20407 |
SDLoc DL(ST); |
0 |
20407 |
SDLoc DL(ST); |
0 |
| 20408 |
|
--- |
20408 |
|
--- |
| 20409 |
SDValue Chain = ST->getChain(); |
0 |
20409 |
SDValue Chain = ST->getChain(); |
0 |
| 20410 |
SDValue Ptr = ST->getBasePtr(); |
0 |
20410 |
SDValue Ptr = ST->getBasePtr(); |
0 |
| 20411 |
|
--- |
20411 |
|
--- |
| 20412 |
const ConstantFPSDNode *CFP = cast(Value); |
0 |
20412 |
const ConstantFPSDNode *CFP = cast(Value); |
0 |
| 20413 |
|
--- |
20413 |
|
--- |
| 20414 |
// NOTE: If the original store is volatile, this transform must not increase |
--- |
20414 |
// NOTE: If the original store is volatile, this transform must not increase |
--- |
| 20415 |
// the number of stores. For example, on x86-32 an f64 can be stored in one |
--- |
20415 |
// the number of stores. For example, on x86-32 an f64 can be stored in one |
--- |
| 20416 |
// processor operation but an i64 (which is not legal) requires two. So the |
--- |
20416 |
// processor operation but an i64 (which is not legal) requires two. So the |
--- |
| 20417 |
// transform should not be done in this case. |
--- |
20417 |
// transform should not be done in this case. |
--- |
| 20418 |
|
--- |
20418 |
|
--- |
| 20419 |
SDValue Tmp; |
0 |
20419 |
SDValue Tmp; |
0 |
| 20420 |
switch (CFP->getSimpleValueType(0).SimpleTy) { |
0 |
20420 |
switch (CFP->getSimpleValueType(0).SimpleTy) { |
0 |
| 20421 |
default: |
0 |
20421 |
default: |
0 |
| 20422 |
llvm_unreachable("Unknown FP type"); |
0 |
20422 |
llvm_unreachable("Unknown FP type"); |
0 |
| 20423 |
case MVT::f16: // We don't do this for these yet. |
0 |
20423 |
case MVT::f16: // We don't do this for these yet. |
0 |
| 20424 |
case MVT::bf16: |
--- |
20424 |
case MVT::bf16: |
--- |
| 20425 |
case MVT::f80: |
--- |
20425 |
case MVT::f80: |
--- |
| 20426 |
case MVT::f128: |
--- |
20426 |
case MVT::f128: |
--- |
| 20427 |
case MVT::ppcf128: |
--- |
20427 |
case MVT::ppcf128: |
--- |
| 20428 |
return SDValue(); |
0 |
20428 |
return SDValue(); |
0 |
| 20429 |
case MVT::f32: |
0 |
20429 |
case MVT::f32: |
0 |
| 20430 |
if ((isTypeLegal(MVT::i32) && !LegalOperations && ST->isSimple()) || |
0 |
20430 |
if ((isTypeLegal(MVT::i32) && !LegalOperations && ST->isSimple()) || |
0 |
| 20431 |
TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { |
0 |
20431 |
TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { |
0 |
| 20432 |
Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). |
0 |
20432 |
Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). |
0 |
| 20433 |
bitcastToAPInt().getZExtValue(), SDLoc(CFP), |
0 |
20433 |
bitcastToAPInt().getZExtValue(), SDLoc(CFP), |
0 |
| 20434 |
MVT::i32); |
--- |
20434 |
MVT::i32); |
--- |
| 20435 |
return DAG.getStore(Chain, DL, Tmp, Ptr, ST->getMemOperand()); |
0 |
20435 |
return DAG.getStore(Chain, DL, Tmp, Ptr, ST->getMemOperand()); |
0 |
| 20436 |
} |
--- |
20436 |
} |
--- |
| 20437 |
|
--- |
20437 |
|
--- |
| 20438 |
return SDValue(); |
0 |
20438 |
return SDValue(); |
0 |
| 20439 |
case MVT::f64: |
0 |
20439 |
case MVT::f64: |
0 |
| 20440 |
if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && |
0 |
20440 |
if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && |
0 |
| 20441 |
ST->isSimple()) || |
0 |
20441 |
ST->isSimple()) || |
0 |
| 20442 |
TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { |
0 |
20442 |
TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { |
0 |
| 20443 |
Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). |
0 |
20443 |
Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). |
0 |
| 20444 |
getZExtValue(), SDLoc(CFP), MVT::i64); |
0 |
20444 |
getZExtValue(), SDLoc(CFP), MVT::i64); |
0 |
| 20445 |
return DAG.getStore(Chain, DL, Tmp, |
0 |
20445 |
return DAG.getStore(Chain, DL, Tmp, |
0 |
| 20446 |
Ptr, ST->getMemOperand()); |
0 |
20446 |
Ptr, ST->getMemOperand()); |
0 |
| 20447 |
} |
--- |
20447 |
} |
--- |
| 20448 |
|
--- |
20448 |
|
--- |
| 20449 |
if (ST->isSimple() && |
0 |
20449 |
if (ST->isSimple() && |
0 |
| 20450 |
TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { |
0 |
20450 |
TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { |
0 |
| 20451 |
// Many FP stores are not made apparent until after legalize, e.g. for |
--- |
20451 |
// Many FP stores are not made apparent until after legalize, e.g. for |
--- |
| 20452 |
// argument passing. Since this is so common, custom legalize the |
--- |
20452 |
// argument passing. Since this is so common, custom legalize the |
--- |
| 20453 |
// 64-bit integer store into two 32-bit stores. |
--- |
20453 |
// 64-bit integer store into two 32-bit stores. |
--- |
| 20454 |
uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); |
0 |
20454 |
uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); |
0 |
| 20455 |
SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, SDLoc(CFP), MVT::i32); |
0 |
20455 |
SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, SDLoc(CFP), MVT::i32); |
0 |
| 20456 |
SDValue Hi = DAG.getConstant(Val >> 32, SDLoc(CFP), MVT::i32); |
0 |
20456 |
SDValue Hi = DAG.getConstant(Val >> 32, SDLoc(CFP), MVT::i32); |
0 |
| 20457 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
20457 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
| 20458 |
std::swap(Lo, Hi); |
0 |
20458 |
std::swap(Lo, Hi); |
0 |
| 20459 |
|
--- |
20459 |
|
--- |
| 20460 |
MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags(); |
0 |
20460 |
MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags(); |
0 |
| 20461 |
AAMDNodes AAInfo = ST->getAAInfo(); |
0 |
20461 |
AAMDNodes AAInfo = ST->getAAInfo(); |
0 |
| 20462 |
|
--- |
20462 |
|
--- |
| 20463 |
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(), |
0 |
20463 |
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(), |
0 |
| 20464 |
ST->getOriginalAlign(), MMOFlags, AAInfo); |
--- |
20464 |
ST->getOriginalAlign(), MMOFlags, AAInfo); |
--- |
| 20465 |
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(4), DL); |
0 |
20465 |
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(4), DL); |
0 |
| 20466 |
SDValue St1 = DAG.getStore(Chain, DL, Hi, Ptr, |
0 |
20466 |
SDValue St1 = DAG.getStore(Chain, DL, Hi, Ptr, |
0 |
| 20467 |
ST->getPointerInfo().getWithOffset(4), |
0 |
20467 |
ST->getPointerInfo().getWithOffset(4), |
0 |
| 20468 |
ST->getOriginalAlign(), MMOFlags, AAInfo); |
--- |
20468 |
ST->getOriginalAlign(), MMOFlags, AAInfo); |
--- |
| 20469 |
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, |
0 |
20469 |
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, |
0 |
| 20470 |
St0, St1); |
0 |
20470 |
St0, St1); |
0 |
| 20471 |
} |
--- |
20471 |
} |
--- |
| 20472 |
|
--- |
20472 |
|
--- |
| 20473 |
return SDValue(); |
0 |
20473 |
return SDValue(); |
0 |
| 20474 |
} |
--- |
20474 |
} |
--- |
| 20475 |
} |
0 |
20475 |
} |
0 |
| 20476 |
|
--- |
20476 |
|
--- |
| 20477 |
// (store (insert_vector_elt (load p), x, i), p) -> (store x, p+offset) |
--- |
20477 |
// (store (insert_vector_elt (load p), x, i), p) -> (store x, p+offset) |
--- |
| 20478 |
// |
--- |
20478 |
// |
--- |
| 20479 |
// If a store of a load with an element inserted into it has no other |
--- |
20479 |
// If a store of a load with an element inserted into it has no other |
--- |
| 20480 |
// uses in between the chain, then we can consider the vector store |
--- |
20480 |
// uses in between the chain, then we can consider the vector store |
--- |
| 20481 |
// dead and replace it with just the single scalar element store. |
--- |
20481 |
// dead and replace it with just the single scalar element store. |
--- |
| 20482 |
SDValue DAGCombiner::replaceStoreOfInsertLoad(StoreSDNode *ST) { |
10 |
20482 |
SDValue DAGCombiner::replaceStoreOfInsertLoad(StoreSDNode *ST) { |
10 |
| 20483 |
SDLoc DL(ST); |
10 |
20483 |
SDLoc DL(ST); |
10 |
| 20484 |
SDValue Value = ST->getValue(); |
10 |
20484 |
SDValue Value = ST->getValue(); |
10 |
| 20485 |
SDValue Ptr = ST->getBasePtr(); |
10 |
20485 |
SDValue Ptr = ST->getBasePtr(); |
10 |
| 20486 |
SDValue Chain = ST->getChain(); |
10 |
20486 |
SDValue Chain = ST->getChain(); |
10 |
| 20487 |
if (Value.getOpcode() != ISD::INSERT_VECTOR_ELT || !Value.hasOneUse()) |
10 |
20487 |
if (Value.getOpcode() != ISD::INSERT_VECTOR_ELT || !Value.hasOneUse()) |
10 |
| 20488 |
return SDValue(); |
10 |
20488 |
return SDValue(); |
10 |
| 20489 |
|
--- |
20489 |
|
--- |
| 20490 |
SDValue Elt = Value.getOperand(1); |
0 |
20490 |
SDValue Elt = Value.getOperand(1); |
0 |
| 20491 |
SDValue Idx = Value.getOperand(2); |
0 |
20491 |
SDValue Idx = Value.getOperand(2); |
0 |
| 20492 |
|
--- |
20492 |
|
--- |
| 20493 |
// If the element isn't byte sized then we can't compute an offset |
--- |
20493 |
// If the element isn't byte sized then we can't compute an offset |
--- |
| 20494 |
EVT EltVT = Elt.getValueType(); |
0 |
20494 |
EVT EltVT = Elt.getValueType(); |
0 |
| 20495 |
if (!EltVT.isByteSized()) |
0 |
20495 |
if (!EltVT.isByteSized()) |
0 |
| 20496 |
return SDValue(); |
0 |
20496 |
return SDValue(); |
0 |
| 20497 |
|
--- |
20497 |
|
--- |
| 20498 |
auto *Ld = dyn_cast(Value.getOperand(0)); |
0 |
20498 |
auto *Ld = dyn_cast(Value.getOperand(0)); |
0 |
| 20499 |
if (!Ld || Ld->getBasePtr() != Ptr || |
0 |
20499 |
if (!Ld || Ld->getBasePtr() != Ptr || |
0 |
| 20500 |
ST->getMemoryVT() != Ld->getMemoryVT() || !ST->isSimple() || |
0 |
20500 |
ST->getMemoryVT() != Ld->getMemoryVT() || !ST->isSimple() || |
0 |
| 20501 |
!ISD::isNormalStore(ST) || |
0 |
20501 |
!ISD::isNormalStore(ST) || |
0 |
| 20502 |
Ld->getAddressSpace() != ST->getAddressSpace() || |
0 |
20502 |
Ld->getAddressSpace() != ST->getAddressSpace() || |
0 |
| 20503 |
!Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) |
0 |
20503 |
!Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) |
0 |
| 20504 |
return SDValue(); |
0 |
20504 |
return SDValue(); |
0 |
| 20505 |
|
--- |
20505 |
|
--- |
| 20506 |
unsigned IsFast; |
--- |
20506 |
unsigned IsFast; |
--- |
| 20507 |
if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), |
0 |
20507 |
if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), |
0 |
| 20508 |
Elt.getValueType(), ST->getAddressSpace(), |
--- |
20508 |
Elt.getValueType(), ST->getAddressSpace(), |
--- |
| 20509 |
ST->getAlign(), ST->getMemOperand()->getFlags(), |
0 |
20509 |
ST->getAlign(), ST->getMemOperand()->getFlags(), |
0 |
| 20510 |
&IsFast) || |
0 |
20510 |
&IsFast) || |
0 |
| 20511 |
!IsFast) |
0 |
20511 |
!IsFast) |
0 |
| 20512 |
return SDValue(); |
0 |
20512 |
return SDValue(); |
0 |
| 20513 |
EVT PtrVT = Ptr.getValueType(); |
0 |
20513 |
EVT PtrVT = Ptr.getValueType(); |
0 |
| 20514 |
|
--- |
20514 |
|
--- |
| 20515 |
SDValue Offset = |
--- |
20515 |
SDValue Offset = |
--- |
| 20516 |
DAG.getNode(ISD::MUL, DL, PtrVT, Idx, |
0 |
20516 |
DAG.getNode(ISD::MUL, DL, PtrVT, Idx, |
0 |
| 20517 |
DAG.getConstant(EltVT.getSizeInBits() / 8, DL, PtrVT)); |
0 |
20517 |
DAG.getConstant(EltVT.getSizeInBits() / 8, DL, PtrVT)); |
0 |
| 20518 |
SDValue NewPtr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, Offset); |
0 |
20518 |
SDValue NewPtr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, Offset); |
0 |
| 20519 |
MachinePointerInfo PointerInfo(ST->getAddressSpace()); |
0 |
20519 |
MachinePointerInfo PointerInfo(ST->getAddressSpace()); |
0 |
| 20520 |
|
--- |
20520 |
|
--- |
| 20521 |
// If the offset is a known constant then try to recover the pointer |
--- |
20521 |
// If the offset is a known constant then try to recover the pointer |
--- |
| 20522 |
// info |
--- |
20522 |
// info |
--- |
| 20523 |
if (auto *CIdx = dyn_cast(Idx)) { |
0 |
20523 |
if (auto *CIdx = dyn_cast(Idx)) { |
0 |
| 20524 |
unsigned COffset = CIdx->getSExtValue() * EltVT.getSizeInBits() / 8; |
0 |
20524 |
unsigned COffset = CIdx->getSExtValue() * EltVT.getSizeInBits() / 8; |
0 |
| 20525 |
NewPtr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(COffset), DL); |
0 |
20525 |
NewPtr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(COffset), DL); |
0 |
| 20526 |
PointerInfo = ST->getPointerInfo().getWithOffset(COffset); |
0 |
20526 |
PointerInfo = ST->getPointerInfo().getWithOffset(COffset); |
0 |
| 20527 |
} |
--- |
20527 |
} |
--- |
| 20528 |
|
--- |
20528 |
|
--- |
| 20529 |
return DAG.getStore(Chain, DL, Elt, NewPtr, PointerInfo, ST->getAlign(), |
0 |
20529 |
return DAG.getStore(Chain, DL, Elt, NewPtr, PointerInfo, ST->getAlign(), |
0 |
| 20530 |
ST->getMemOperand()->getFlags()); |
0 |
20530 |
ST->getMemOperand()->getFlags()); |
0 |
| 20531 |
} |
10 |
20531 |
} |
10 |
| 20532 |
|
--- |
20532 |
|
--- |
| 20533 |
SDValue DAGCombiner::visitSTORE(SDNode *N) { |
10 |
20533 |
SDValue DAGCombiner::visitSTORE(SDNode *N) { |
10 |
| 20534 |
StoreSDNode *ST = cast(N); |
10 |
20534 |
StoreSDNode *ST = cast(N); |
10 |
| 20535 |
SDValue Chain = ST->getChain(); |
10 |
20535 |
SDValue Chain = ST->getChain(); |
10 |
| 20536 |
SDValue Value = ST->getValue(); |
10 |
20536 |
SDValue Value = ST->getValue(); |
10 |
| 20537 |
SDValue Ptr = ST->getBasePtr(); |
10 |
20537 |
SDValue Ptr = ST->getBasePtr(); |
10 |
| 20538 |
|
--- |
20538 |
|
--- |
| 20539 |
// If this is a store of a bit convert, store the input value if the |
--- |
20539 |
// If this is a store of a bit convert, store the input value if the |
--- |
| 20540 |
// resultant store does not need a higher alignment than the original. |
--- |
20540 |
// resultant store does not need a higher alignment than the original. |
--- |
| 20541 |
if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && |
10 |
20541 |
if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && |
10 |
| 20542 |
ST->isUnindexed()) { |
0 |
20542 |
ST->isUnindexed()) { |
0 |
| 20543 |
EVT SVT = Value.getOperand(0).getValueType(); |
0 |
20543 |
EVT SVT = Value.getOperand(0).getValueType(); |
0 |
| 20544 |
// If the store is volatile, we only want to change the store type if the |
--- |
20544 |
// If the store is volatile, we only want to change the store type if the |
--- |
| 20545 |
// resulting store is legal. Otherwise we might increase the number of |
--- |
20545 |
// resulting store is legal. Otherwise we might increase the number of |
--- |
| 20546 |
// memory accesses. We don't care if the original type was legal or not |
--- |
20546 |
// memory accesses. We don't care if the original type was legal or not |
--- |
| 20547 |
// as we assume software couldn't rely on the number of accesses of an |
--- |
20547 |
// as we assume software couldn't rely on the number of accesses of an |
--- |
| 20548 |
// illegal type. |
--- |
20548 |
// illegal type. |
--- |
| 20549 |
// TODO: May be able to relax for unordered atomics (see D66309) |
--- |
20549 |
// TODO: May be able to relax for unordered atomics (see D66309) |
--- |
| 20550 |
if (((!LegalOperations && ST->isSimple()) || |
0 |
20550 |
if (((!LegalOperations && ST->isSimple()) || |
0 |
| 20551 |
TLI.isOperationLegal(ISD::STORE, SVT)) && |
0 |
20551 |
TLI.isOperationLegal(ISD::STORE, SVT)) && |
0 |
| 20552 |
TLI.isStoreBitCastBeneficial(Value.getValueType(), SVT, |
0 |
20552 |
TLI.isStoreBitCastBeneficial(Value.getValueType(), SVT, |
0 |
| 20553 |
DAG, *ST->getMemOperand())) { |
0 |
20553 |
DAG, *ST->getMemOperand())) { |
0 |
| 20554 |
return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0), Ptr, |
0 |
20554 |
return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0), Ptr, |
0 |
| 20555 |
ST->getMemOperand()); |
0 |
20555 |
ST->getMemOperand()); |
0 |
| 20556 |
} |
--- |
20556 |
} |
--- |
| 20557 |
} |
--- |
20557 |
} |
--- |
| 20558 |
|
--- |
20558 |
|
--- |
| 20559 |
// Turn 'store undef, Ptr' -> nothing. |
--- |
20559 |
// Turn 'store undef, Ptr' -> nothing. |
--- |
| 20560 |
if (Value.isUndef() && ST->isUnindexed()) |
10 |
20560 |
if (Value.isUndef() && ST->isUnindexed()) |
10 |
| 20561 |
return Chain; |
0 |
20561 |
return Chain; |
0 |
| 20562 |
|
--- |
20562 |
|
--- |
| 20563 |
// Try to infer better alignment information than the store already has. |
--- |
20563 |
// Try to infer better alignment information than the store already has. |
--- |
| 20564 |
if (OptLevel != CodeGenOpt::None && ST->isUnindexed() && !ST->isAtomic()) { |
10 |
20564 |
if (OptLevel != CodeGenOpt::None && ST->isUnindexed() && !ST->isAtomic()) { |
10 |
| 20565 |
if (MaybeAlign Alignment = DAG.InferPtrAlign(Ptr)) { |
0 |
20565 |
if (MaybeAlign Alignment = DAG.InferPtrAlign(Ptr)) { |
0 |
| 20566 |
if (*Alignment > ST->getAlign() && |
0 |
20566 |
if (*Alignment > ST->getAlign() && |
0 |
| 20567 |
isAligned(*Alignment, ST->getSrcValueOffset())) { |
0 |
20567 |
isAligned(*Alignment, ST->getSrcValueOffset())) { |
0 |
| 20568 |
SDValue NewStore = |
--- |
20568 |
SDValue NewStore = |
--- |
| 20569 |
DAG.getTruncStore(Chain, SDLoc(N), Value, Ptr, ST->getPointerInfo(), |
0 |
20569 |
DAG.getTruncStore(Chain, SDLoc(N), Value, Ptr, ST->getPointerInfo(), |
0 |
| 20570 |
ST->getMemoryVT(), *Alignment, |
0 |
20570 |
ST->getMemoryVT(), *Alignment, |
0 |
| 20571 |
ST->getMemOperand()->getFlags(), ST->getAAInfo()); |
0 |
20571 |
ST->getMemOperand()->getFlags(), ST->getAAInfo()); |
0 |
| 20572 |
// NewStore will always be N as we are only refining the alignment |
--- |
20572 |
// NewStore will always be N as we are only refining the alignment |
--- |
| 20573 |
assert(NewStore.getNode() == N); |
0 |
20573 |
assert(NewStore.getNode() == N); |
0 |
| 20574 |
(void)NewStore; |
--- |
20574 |
(void)NewStore; |
--- |
| 20575 |
} |
--- |
20575 |
} |
--- |
| 20576 |
} |
--- |
20576 |
} |
--- |
| 20577 |
} |
--- |
20577 |
} |
--- |
| 20578 |
|
--- |
20578 |
|
--- |
| 20579 |
// Try transforming a pair floating point load / store ops to integer |
--- |
20579 |
// Try transforming a pair floating point load / store ops to integer |
--- |
| 20580 |
// load / store ops. |
--- |
20580 |
// load / store ops. |
--- |
| 20581 |
if (SDValue NewST = TransformFPLoadStorePair(N)) |
10 |
20581 |
if (SDValue NewST = TransformFPLoadStorePair(N)) |
10 |
| 20582 |
return NewST; |
0 |
20582 |
return NewST; |
0 |
| 20583 |
|
--- |
20583 |
|
--- |
| 20584 |
// Try transforming several stores into STORE (BSWAP). |
--- |
20584 |
// Try transforming several stores into STORE (BSWAP). |
--- |
| 20585 |
if (SDValue Store = mergeTruncStores(ST)) |
10 |
20585 |
if (SDValue Store = mergeTruncStores(ST)) |
10 |
| 20586 |
return Store; |
0 |
20586 |
return Store; |
0 |
| 20587 |
|
--- |
20587 |
|
--- |
| 20588 |
if (ST->isUnindexed()) { |
10 |
20588 |
if (ST->isUnindexed()) { |
10 |
| 20589 |
// Walk up chain skipping non-aliasing memory nodes, on this store and any |
--- |
20589 |
// Walk up chain skipping non-aliasing memory nodes, on this store and any |
--- |
| 20590 |
// adjacent stores. |
--- |
20590 |
// adjacent stores. |
--- |
| 20591 |
if (findBetterNeighborChains(ST)) { |
10 |
20591 |
if (findBetterNeighborChains(ST)) { |
10 |
| 20592 |
// replaceStoreChain uses CombineTo, which handled all of the worklist |
--- |
20592 |
// replaceStoreChain uses CombineTo, which handled all of the worklist |
--- |
| 20593 |
// manipulation. Return the original node to not do anything else. |
--- |
20593 |
// manipulation. Return the original node to not do anything else. |
--- |
| 20594 |
return SDValue(ST, 0); |
0 |
20594 |
return SDValue(ST, 0); |
0 |
| 20595 |
} |
--- |
20595 |
} |
--- |
| 20596 |
Chain = ST->getChain(); |
10 |
20596 |
Chain = ST->getChain(); |
10 |
| 20597 |
} |
--- |
20597 |
} |
--- |
| 20598 |
|
--- |
20598 |
|
--- |
| 20599 |
// FIXME: is there such a thing as a truncating indexed store? |
--- |
20599 |
// FIXME: is there such a thing as a truncating indexed store? |
--- |
| 20600 |
if (ST->isTruncatingStore() && ST->isUnindexed() && |
10 |
20600 |
if (ST->isTruncatingStore() && ST->isUnindexed() && |
10 |
| 20601 |
Value.getValueType().isInteger() && |
10 |
20601 |
Value.getValueType().isInteger() && |
10 |
| 20602 |
(!isa(Value) || |
0 |
20602 |
(!isa(Value) || |
0 |
| 20603 |
!cast(Value)->isOpaque())) { |
0 |
20603 |
!cast(Value)->isOpaque())) { |
0 |
| 20604 |
// Convert a truncating store of a extension into a standard store. |
--- |
20604 |
// Convert a truncating store of a extension into a standard store. |
--- |
| 20605 |
if ((Value.getOpcode() == ISD::ZERO_EXTEND || |
0 |
20605 |
if ((Value.getOpcode() == ISD::ZERO_EXTEND || |
0 |
| 20606 |
Value.getOpcode() == ISD::SIGN_EXTEND || |
0 |
20606 |
Value.getOpcode() == ISD::SIGN_EXTEND || |
0 |
| 20607 |
Value.getOpcode() == ISD::ANY_EXTEND) && |
0 |
20607 |
Value.getOpcode() == ISD::ANY_EXTEND) && |
0 |
| 20608 |
Value.getOperand(0).getValueType() == ST->getMemoryVT() && |
0 |
20608 |
Value.getOperand(0).getValueType() == ST->getMemoryVT() && |
0 |
| 20609 |
TLI.isOperationLegalOrCustom(ISD::STORE, ST->getMemoryVT())) |
0 |
20609 |
TLI.isOperationLegalOrCustom(ISD::STORE, ST->getMemoryVT())) |
0 |
| 20610 |
return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0), Ptr, |
0 |
20610 |
return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0), Ptr, |
0 |
| 20611 |
ST->getMemOperand()); |
0 |
20611 |
ST->getMemOperand()); |
0 |
| 20612 |
|
--- |
20612 |
|
--- |
| 20613 |
APInt TruncDemandedBits = |
--- |
20613 |
APInt TruncDemandedBits = |
--- |
| 20614 |
APInt::getLowBitsSet(Value.getScalarValueSizeInBits(), |
0 |
20614 |
APInt::getLowBitsSet(Value.getScalarValueSizeInBits(), |
0 |
| 20615 |
ST->getMemoryVT().getScalarSizeInBits()); |
0 |
20615 |
ST->getMemoryVT().getScalarSizeInBits()); |
0 |
| 20616 |
|
--- |
20616 |
|
--- |
| 20617 |
// See if we can simplify the operation with SimplifyDemandedBits, which |
--- |
20617 |
// See if we can simplify the operation with SimplifyDemandedBits, which |
--- |
| 20618 |
// only works if the value has a single use. |
--- |
20618 |
// only works if the value has a single use. |
--- |
| 20619 |
AddToWorklist(Value.getNode()); |
0 |
20619 |
AddToWorklist(Value.getNode()); |
0 |
| 20620 |
if (SimplifyDemandedBits(Value, TruncDemandedBits)) { |
0 |
20620 |
if (SimplifyDemandedBits(Value, TruncDemandedBits)) { |
0 |
| 20621 |
// Re-visit the store if anything changed and the store hasn't been merged |
--- |
20621 |
// Re-visit the store if anything changed and the store hasn't been merged |
--- |
| 20622 |
// with another node (N is deleted) SimplifyDemandedBits will add Value's |
--- |
20622 |
// with another node (N is deleted) SimplifyDemandedBits will add Value's |
--- |
| 20623 |
// node back to the worklist if necessary, but we also need to re-visit |
--- |
20623 |
// node back to the worklist if necessary, but we also need to re-visit |
--- |
| 20624 |
// the Store node itself. |
--- |
20624 |
// the Store node itself. |
--- |
| 20625 |
if (N->getOpcode() != ISD::DELETED_NODE) |
0 |
20625 |
if (N->getOpcode() != ISD::DELETED_NODE) |
0 |
| 20626 |
AddToWorklist(N); |
0 |
20626 |
AddToWorklist(N); |
0 |
| 20627 |
return SDValue(N, 0); |
0 |
20627 |
return SDValue(N, 0); |
0 |
| 20628 |
} |
--- |
20628 |
} |
--- |
| 20629 |
|
--- |
20629 |
|
--- |
| 20630 |
// Otherwise, see if we can simplify the input to this truncstore with |
--- |
20630 |
// Otherwise, see if we can simplify the input to this truncstore with |
--- |
| 20631 |
// knowledge that only the low bits are being used. For example: |
--- |
20631 |
// knowledge that only the low bits are being used. For example: |
--- |
| 20632 |
// "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" |
--- |
20632 |
// "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" |
--- |
| 20633 |
if (SDValue Shorter = |
0 |
20633 |
if (SDValue Shorter = |
0 |
| 20634 |
TLI.SimplifyMultipleUseDemandedBits(Value, TruncDemandedBits, DAG)) |
0 |
20634 |
TLI.SimplifyMultipleUseDemandedBits(Value, TruncDemandedBits, DAG)) |
0 |
| 20635 |
return DAG.getTruncStore(Chain, SDLoc(N), Shorter, Ptr, ST->getMemoryVT(), |
0 |
20635 |
return DAG.getTruncStore(Chain, SDLoc(N), Shorter, Ptr, ST->getMemoryVT(), |
0 |
| 20636 |
ST->getMemOperand()); |
0 |
20636 |
ST->getMemOperand()); |
0 |
| 20637 |
|
--- |
20637 |
|
--- |
| 20638 |
// If we're storing a truncated constant, see if we can simplify it. |
--- |
20638 |
// If we're storing a truncated constant, see if we can simplify it. |
--- |
| 20639 |
// TODO: Move this to targetShrinkDemandedConstant? |
--- |
20639 |
// TODO: Move this to targetShrinkDemandedConstant? |
--- |
| 20640 |
if (auto *Cst = dyn_cast(Value)) |
0 |
20640 |
if (auto *Cst = dyn_cast(Value)) |
0 |
| 20641 |
if (!Cst->isOpaque()) { |
0 |
20641 |
if (!Cst->isOpaque()) { |
0 |
| 20642 |
const APInt &CValue = Cst->getAPIntValue(); |
0 |
20642 |
const APInt &CValue = Cst->getAPIntValue(); |
0 |
| 20643 |
APInt NewVal = CValue & TruncDemandedBits; |
0 |
20643 |
APInt NewVal = CValue & TruncDemandedBits; |
0 |
| 20644 |
if (NewVal != CValue) { |
0 |
20644 |
if (NewVal != CValue) { |
0 |
| 20645 |
SDValue Shorter = |
--- |
20645 |
SDValue Shorter = |
--- |
| 20646 |
DAG.getConstant(NewVal, SDLoc(N), Value.getValueType()); |
0 |
20646 |
DAG.getConstant(NewVal, SDLoc(N), Value.getValueType()); |
0 |
| 20647 |
return DAG.getTruncStore(Chain, SDLoc(N), Shorter, Ptr, |
0 |
20647 |
return DAG.getTruncStore(Chain, SDLoc(N), Shorter, Ptr, |
0 |
| 20648 |
ST->getMemoryVT(), ST->getMemOperand()); |
0 |
20648 |
ST->getMemoryVT(), ST->getMemOperand()); |
0 |
| 20649 |
} |
--- |
20649 |
} |
--- |
| 20650 |
} |
0 |
20650 |
} |
0 |
| 20651 |
} |
0 |
20651 |
} |
0 |
| 20652 |
|
--- |
20652 |
|
--- |
| 20653 |
// If this is a load followed by a store to the same location, then the store |
--- |
20653 |
// If this is a load followed by a store to the same location, then the store |
--- |
| 20654 |
// is dead/noop. Peek through any truncates if canCombineTruncStore failed. |
--- |
20654 |
// is dead/noop. Peek through any truncates if canCombineTruncStore failed. |
--- |
| 20655 |
// TODO: Add big-endian truncate support with test coverage. |
--- |
20655 |
// TODO: Add big-endian truncate support with test coverage. |
--- |
| 20656 |
// TODO: Can relax for unordered atomics (see D66309) |
--- |
20656 |
// TODO: Can relax for unordered atomics (see D66309) |
--- |
| 20657 |
SDValue TruncVal = DAG.getDataLayout().isLittleEndian() |
10 |
20657 |
SDValue TruncVal = DAG.getDataLayout().isLittleEndian() |
10 |
| 20658 |
? peekThroughTruncates(Value) |
0 |
20658 |
? peekThroughTruncates(Value) |
0 |
| 20659 |
: Value; |
10 |
20659 |
: Value; |
10 |
| 20660 |
if (auto *Ld = dyn_cast(TruncVal)) { |
10 |
20660 |
if (auto *Ld = dyn_cast(TruncVal)) { |
10 |
| 20661 |
if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && |
4 |
20661 |
if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && |
4 |
| 20662 |
ST->isUnindexed() && ST->isSimple() && |
0 |
20662 |
ST->isUnindexed() && ST->isSimple() && |
0 |
| 20663 |
Ld->getAddressSpace() == ST->getAddressSpace() && |
4 |
20663 |
Ld->getAddressSpace() == ST->getAddressSpace() && |
4 |
| 20664 |
// There can't be any side effects between the load and store, such as |
--- |
20664 |
// There can't be any side effects between the load and store, such as |
--- |
| 20665 |
// a call or store. |
--- |
20665 |
// a call or store. |
--- |
| 20666 |
Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { |
4 |
20666 |
Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { |
4 |
| 20667 |
// The store is dead, remove it. |
--- |
20667 |
// The store is dead, remove it. |
--- |
| 20668 |
return Chain; |
0 |
20668 |
return Chain; |
0 |
| 20669 |
} |
--- |
20669 |
} |
--- |
| 20670 |
} |
--- |
20670 |
} |
--- |
| 20671 |
|
--- |
20671 |
|
--- |
| 20672 |
// Try scalarizing vector stores of loads where we only change one element |
--- |
20672 |
// Try scalarizing vector stores of loads where we only change one element |
--- |
| 20673 |
if (SDValue NewST = replaceStoreOfInsertLoad(ST)) |
10 |
20673 |
if (SDValue NewST = replaceStoreOfInsertLoad(ST)) |
10 |
| 20674 |
return NewST; |
0 |
20674 |
return NewST; |
0 |
| 20675 |
|
--- |
20675 |
|
--- |
| 20676 |
// TODO: Can relax for unordered atomics (see D66309) |
--- |
20676 |
// TODO: Can relax for unordered atomics (see D66309) |
--- |
| 20677 |
if (StoreSDNode *ST1 = dyn_cast(Chain)) { |
10 |
20677 |
if (StoreSDNode *ST1 = dyn_cast(Chain)) { |
10 |
| 20678 |
if (ST->isUnindexed() && ST->isSimple() && |
9 |
20678 |
if (ST->isUnindexed() && ST->isSimple() && |
9 |
| 20679 |
ST1->isUnindexed() && ST1->isSimple()) { |
9 |
20679 |
ST1->isUnindexed() && ST1->isSimple()) { |
9 |
| 20680 |
if (OptLevel != CodeGenOpt::None && ST1->getBasePtr() == Ptr && |
0 |
20680 |
if (OptLevel != CodeGenOpt::None && ST1->getBasePtr() == Ptr && |
0 |
| 20681 |
ST1->getValue() == Value && ST->getMemoryVT() == ST1->getMemoryVT() && |
3 |
20681 |
ST1->getValue() == Value && ST->getMemoryVT() == ST1->getMemoryVT() && |
3 |
| 20682 |
ST->getAddressSpace() == ST1->getAddressSpace()) { |
0 |
20682 |
ST->getAddressSpace() == ST1->getAddressSpace()) { |
0 |
| 20683 |
// If this is a store followed by a store with the same value to the |
--- |
20683 |
// If this is a store followed by a store with the same value to the |
--- |
| 20684 |
// same location, then the store is dead/noop. |
--- |
20684 |
// same location, then the store is dead/noop. |
--- |
| 20685 |
return Chain; |
0 |
20685 |
return Chain; |
0 |
| 20686 |
} |
--- |
20686 |
} |
--- |
| 20687 |
|
--- |
20687 |
|
--- |
| 20688 |
if (OptLevel != CodeGenOpt::None && ST1->hasOneUse() && |
0 |
20688 |
if (OptLevel != CodeGenOpt::None && ST1->hasOneUse() && |
0 |
| 20689 |
!ST1->getBasePtr().isUndef() && |
3 |
20689 |
!ST1->getBasePtr().isUndef() && |
3 |
| 20690 |
ST->getAddressSpace() == ST1->getAddressSpace()) { |
0 |
20690 |
ST->getAddressSpace() == ST1->getAddressSpace()) { |
0 |
| 20691 |
// If we consider two stores and one smaller in size is a scalable |
--- |
20691 |
// If we consider two stores and one smaller in size is a scalable |
--- |
| 20692 |
// vector type and another one a bigger size store with a fixed type, |
--- |
20692 |
// vector type and another one a bigger size store with a fixed type, |
--- |
| 20693 |
// then we could not allow the scalable store removal because we don't |
--- |
20693 |
// then we could not allow the scalable store removal because we don't |
--- |
| 20694 |
// know its final size in the end. |
--- |
20694 |
// know its final size in the end. |
--- |
| 20695 |
if (ST->getMemoryVT().isScalableVector() || |
0 |
20695 |
if (ST->getMemoryVT().isScalableVector() || |
0 |
| 20696 |
ST1->getMemoryVT().isScalableVector()) { |
0 |
20696 |
ST1->getMemoryVT().isScalableVector()) { |
0 |
| 20697 |
if (ST1->getBasePtr() == Ptr && |
0 |
20697 |
if (ST1->getBasePtr() == Ptr && |
0 |
| 20698 |
TypeSize::isKnownLE(ST1->getMemoryVT().getStoreSize(), |
0 |
20698 |
TypeSize::isKnownLE(ST1->getMemoryVT().getStoreSize(), |
0 |
| 20699 |
ST->getMemoryVT().getStoreSize())) { |
0 |
20699 |
ST->getMemoryVT().getStoreSize())) { |
0 |
| 20700 |
CombineTo(ST1, ST1->getChain()); |
0 |
20700 |
CombineTo(ST1, ST1->getChain()); |
0 |
| 20701 |
return SDValue(); |
0 |
20701 |
return SDValue(); |
0 |
| 20702 |
} |
--- |
20702 |
} |
--- |
| 20703 |
} else { |
--- |
20703 |
} else { |
--- |
| 20704 |
const BaseIndexOffset STBase = BaseIndexOffset::match(ST, DAG); |
0 |
20704 |
const BaseIndexOffset STBase = BaseIndexOffset::match(ST, DAG); |
0 |
| 20705 |
const BaseIndexOffset ChainBase = BaseIndexOffset::match(ST1, DAG); |
0 |
20705 |
const BaseIndexOffset ChainBase = BaseIndexOffset::match(ST1, DAG); |
0 |
| 20706 |
// If this is a store who's preceding store to a subset of the current |
--- |
20706 |
// If this is a store who's preceding store to a subset of the current |
--- |
| 20707 |
// location and no one other node is chained to that store we can |
--- |
20707 |
// location and no one other node is chained to that store we can |
--- |
| 20708 |
// effectively drop the store. Do not remove stores to undef as they |
--- |
20708 |
// effectively drop the store. Do not remove stores to undef as they |
--- |
| 20709 |
// may be used as data sinks. |
--- |
20709 |
// may be used as data sinks. |
--- |
| 20710 |
if (STBase.contains(DAG, ST->getMemoryVT().getFixedSizeInBits(), |
0 |
20710 |
if (STBase.contains(DAG, ST->getMemoryVT().getFixedSizeInBits(), |
0 |
| 20711 |
ChainBase, |
--- |
20711 |
ChainBase, |
--- |
| 20712 |
ST1->getMemoryVT().getFixedSizeInBits())) { |
0 |
20712 |
ST1->getMemoryVT().getFixedSizeInBits())) { |
0 |
| 20713 |
CombineTo(ST1, ST1->getChain()); |
0 |
20713 |
CombineTo(ST1, ST1->getChain()); |
0 |
| 20714 |
return SDValue(); |
0 |
20714 |
return SDValue(); |
0 |
| 20715 |
} |
--- |
20715 |
} |
--- |
| 20716 |
} |
--- |
20716 |
} |
--- |
| 20717 |
} |
--- |
20717 |
} |
--- |
| 20718 |
} |
--- |
20718 |
} |
--- |
| 20719 |
} |
--- |
20719 |
} |
--- |
| 20720 |
|
--- |
20720 |
|
--- |
| 20721 |
// If this is an FP_ROUND or TRUNC followed by a store, fold this into a |
--- |
20721 |
// If this is an FP_ROUND or TRUNC followed by a store, fold this into a |
--- |
| 20722 |
// truncating store. We can do this even if this is already a truncstore. |
--- |
20722 |
// truncating store. We can do this even if this is already a truncstore. |
--- |
| 20723 |
if ((Value.getOpcode() == ISD::FP_ROUND || |
20 |
20723 |
if ((Value.getOpcode() == ISD::FP_ROUND || |
20 |
| 20724 |
Value.getOpcode() == ISD::TRUNCATE) && |
10 |
20724 |
Value.getOpcode() == ISD::TRUNCATE) && |
10 |
| 20725 |
Value->hasOneUse() && ST->isUnindexed() && |
20 |
20725 |
Value->hasOneUse() && ST->isUnindexed() && |
20 |
| 20726 |
TLI.canCombineTruncStore(Value.getOperand(0).getValueType(), |
0 |
20726 |
TLI.canCombineTruncStore(Value.getOperand(0).getValueType(), |
0 |
| 20727 |
ST->getMemoryVT(), LegalOperations)) { |
0 |
20727 |
ST->getMemoryVT(), LegalOperations)) { |
0 |
| 20728 |
return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0), |
0 |
20728 |
return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0), |
0 |
| 20729 |
Ptr, ST->getMemoryVT(), ST->getMemOperand()); |
0 |
20729 |
Ptr, ST->getMemoryVT(), ST->getMemOperand()); |
0 |
| 20730 |
} |
--- |
20730 |
} |
--- |
| 20731 |
|
--- |
20731 |
|
--- |
| 20732 |
// Always perform this optimization before types are legal. If the target |
--- |
20732 |
// Always perform this optimization before types are legal. If the target |
--- |
| 20733 |
// prefers, also try this after legalization to catch stores that were created |
--- |
20733 |
// prefers, also try this after legalization to catch stores that were created |
--- |
| 20734 |
// by intrinsics or other nodes. |
--- |
20734 |
// by intrinsics or other nodes. |
--- |
| 20735 |
if (!LegalTypes || (TLI.mergeStoresAfterLegalization(ST->getMemoryVT()))) { |
10 |
20735 |
if (!LegalTypes || (TLI.mergeStoresAfterLegalization(ST->getMemoryVT()))) { |
10 |
| 20736 |
while (true) { |
--- |
20736 |
while (true) { |
--- |
| 20737 |
// There can be multiple store sequences on the same chain. |
--- |
20737 |
// There can be multiple store sequences on the same chain. |
--- |
| 20738 |
// Keep trying to merge store sequences until we are unable to do so |
--- |
20738 |
// Keep trying to merge store sequences until we are unable to do so |
--- |
| 20739 |
// or until we merge the last store on the chain. |
--- |
20739 |
// or until we merge the last store on the chain. |
--- |
| 20740 |
bool Changed = mergeConsecutiveStores(ST); |
10 |
20740 |
bool Changed = mergeConsecutiveStores(ST); |
10 |
| 20741 |
if (!Changed) break; |
10 |
20741 |
if (!Changed) break; |
10 |
| 20742 |
// Return N as merge only uses CombineTo and no worklist clean |
--- |
20742 |
// Return N as merge only uses CombineTo and no worklist clean |
--- |
| 20743 |
// up is necessary. |
--- |
20743 |
// up is necessary. |
--- |
| 20744 |
if (N->getOpcode() == ISD::DELETED_NODE || !isa(N)) |
0 |
20744 |
if (N->getOpcode() == ISD::DELETED_NODE || !isa(N)) |
0 |
| 20745 |
return SDValue(N, 0); |
0 |
20745 |
return SDValue(N, 0); |
0 |
| 20746 |
} |
0 |
20746 |
} |
0 |
| 20747 |
} |
--- |
20747 |
} |
--- |
| 20748 |
|
--- |
20748 |
|
--- |
| 20749 |
// Try transforming N to an indexed store. |
--- |
20749 |
// Try transforming N to an indexed store. |
--- |
| 20750 |
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) |
10 |
20750 |
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) |
10 |
| 20751 |
return SDValue(N, 0); |
0 |
20751 |
return SDValue(N, 0); |
0 |
| 20752 |
|
--- |
20752 |
|
--- |
| 20753 |
// Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' |
--- |
20753 |
// Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' |
--- |
| 20754 |
// |
--- |
20754 |
// |
--- |
| 20755 |
// Make sure to do this only after attempting to merge stores in order to |
--- |
20755 |
// Make sure to do this only after attempting to merge stores in order to |
--- |
| 20756 |
// avoid changing the types of some subset of stores due to visit order, |
--- |
20756 |
// avoid changing the types of some subset of stores due to visit order, |
--- |
| 20757 |
// preventing their merging. |
--- |
20757 |
// preventing their merging. |
--- |
| 20758 |
if (isa(ST->getValue())) { |
10 |
20758 |
if (isa(ST->getValue())) { |
10 |
| 20759 |
if (SDValue NewSt = replaceStoreOfFPConstant(ST)) |
0 |
20759 |
if (SDValue NewSt = replaceStoreOfFPConstant(ST)) |
0 |
| 20760 |
return NewSt; |
0 |
20760 |
return NewSt; |
0 |
| 20761 |
} |
--- |
20761 |
} |
--- |
| 20762 |
|
--- |
20762 |
|
--- |
| 20763 |
if (SDValue NewSt = splitMergedValStore(ST)) |
10 |
20763 |
if (SDValue NewSt = splitMergedValStore(ST)) |
10 |
| 20764 |
return NewSt; |
0 |
20764 |
return NewSt; |
0 |
| 20765 |
|
--- |
20765 |
|
--- |
| 20766 |
return ReduceLoadOpStoreWidth(N); |
10 |
20766 |
return ReduceLoadOpStoreWidth(N); |
10 |
| 20767 |
} |
--- |
20767 |
} |
--- |
| 20768 |
|
--- |
20768 |
|
--- |
| 20769 |
SDValue DAGCombiner::visitLIFETIME_END(SDNode *N) { |
0 |
20769 |
SDValue DAGCombiner::visitLIFETIME_END(SDNode *N) { |
0 |
| 20770 |
const auto *LifetimeEnd = cast(N); |
0 |
20770 |
const auto *LifetimeEnd = cast(N); |
0 |
| 20771 |
if (!LifetimeEnd->hasOffset()) |
0 |
20771 |
if (!LifetimeEnd->hasOffset()) |
0 |
| 20772 |
return SDValue(); |
0 |
20772 |
return SDValue(); |
0 |
| 20773 |
|
--- |
20773 |
|
--- |
| 20774 |
const BaseIndexOffset LifetimeEndBase(N->getOperand(1), SDValue(), |
0 |
20774 |
const BaseIndexOffset LifetimeEndBase(N->getOperand(1), SDValue(), |
0 |
| 20775 |
LifetimeEnd->getOffset(), false); |
0 |
20775 |
LifetimeEnd->getOffset(), false); |
0 |
| 20776 |
|
--- |
20776 |
|
--- |
| 20777 |
// We walk up the chains to find stores. |
--- |
20777 |
// We walk up the chains to find stores. |
--- |
| 20778 |
SmallVector Chains = {N->getOperand(0)}; |
0 |
20778 |
SmallVector Chains = {N->getOperand(0)}; |
0 |
| 20779 |
while (!Chains.empty()) { |
0 |
20779 |
while (!Chains.empty()) { |
0 |
| 20780 |
SDValue Chain = Chains.pop_back_val(); |
0 |
20780 |
SDValue Chain = Chains.pop_back_val(); |
0 |
| 20781 |
if (!Chain.hasOneUse()) |
0 |
20781 |
if (!Chain.hasOneUse()) |
0 |
| 20782 |
continue; |
0 |
20782 |
continue; |
0 |
| 20783 |
switch (Chain.getOpcode()) { |
0 |
20783 |
switch (Chain.getOpcode()) { |
0 |
| 20784 |
case ISD::TokenFactor: |
0 |
20784 |
case ISD::TokenFactor: |
0 |
| 20785 |
for (unsigned Nops = Chain.getNumOperands(); Nops;) |
0 |
20785 |
for (unsigned Nops = Chain.getNumOperands(); Nops;) |
0 |
| 20786 |
Chains.push_back(Chain.getOperand(--Nops)); |
0 |
20786 |
Chains.push_back(Chain.getOperand(--Nops)); |
0 |
| 20787 |
break; |
0 |
20787 |
break; |
0 |
| 20788 |
case ISD::LIFETIME_START: |
0 |
20788 |
case ISD::LIFETIME_START: |
0 |
| 20789 |
case ISD::LIFETIME_END: |
--- |
20789 |
case ISD::LIFETIME_END: |
--- |
| 20790 |
// We can forward past any lifetime start/end that can be proven not to |
--- |
20790 |
// We can forward past any lifetime start/end that can be proven not to |
--- |
| 20791 |
// alias the node. |
--- |
20791 |
// alias the node. |
--- |
| 20792 |
if (!mayAlias(Chain.getNode(), N)) |
0 |
20792 |
if (!mayAlias(Chain.getNode(), N)) |
0 |
| 20793 |
Chains.push_back(Chain.getOperand(0)); |
0 |
20793 |
Chains.push_back(Chain.getOperand(0)); |
0 |
| 20794 |
break; |
0 |
20794 |
break; |
0 |
| 20795 |
case ISD::STORE: { |
0 |
20795 |
case ISD::STORE: { |
0 |
| 20796 |
StoreSDNode *ST = dyn_cast(Chain); |
0 |
20796 |
StoreSDNode *ST = dyn_cast(Chain); |
0 |
| 20797 |
// TODO: Can relax for unordered atomics (see D66309) |
--- |
20797 |
// TODO: Can relax for unordered atomics (see D66309) |
--- |
| 20798 |
if (!ST->isSimple() || ST->isIndexed()) |
0 |
20798 |
if (!ST->isSimple() || ST->isIndexed()) |
0 |
| 20799 |
continue; |
0 |
20799 |
continue; |
0 |
| 20800 |
const TypeSize StoreSize = ST->getMemoryVT().getStoreSize(); |
0 |
20800 |
const TypeSize StoreSize = ST->getMemoryVT().getStoreSize(); |
0 |
| 20801 |
// The bounds of a scalable store are not known until runtime, so this |
--- |
20801 |
// The bounds of a scalable store are not known until runtime, so this |
--- |
| 20802 |
// store cannot be elided. |
--- |
20802 |
// store cannot be elided. |
--- |
| 20803 |
if (StoreSize.isScalable()) |
0 |
20803 |
if (StoreSize.isScalable()) |
0 |
| 20804 |
continue; |
0 |
20804 |
continue; |
0 |
| 20805 |
const BaseIndexOffset StoreBase = BaseIndexOffset::match(ST, DAG); |
0 |
20805 |
const BaseIndexOffset StoreBase = BaseIndexOffset::match(ST, DAG); |
0 |
| 20806 |
// If we store purely within object bounds just before its lifetime ends, |
--- |
20806 |
// If we store purely within object bounds just before its lifetime ends, |
--- |
| 20807 |
// we can remove the store. |
--- |
20807 |
// we can remove the store. |
--- |
| 20808 |
if (LifetimeEndBase.contains(DAG, LifetimeEnd->getSize() * 8, StoreBase, |
0 |
20808 |
if (LifetimeEndBase.contains(DAG, LifetimeEnd->getSize() * 8, StoreBase, |
0 |
| 20809 |
StoreSize.getFixedValue() * 8)) { |
0 |
20809 |
StoreSize.getFixedValue() * 8)) { |
0 |
| 20810 |
LLVM_DEBUG(dbgs() << "\nRemoving store:"; StoreBase.dump(); |
0 |
20810 |
LLVM_DEBUG(dbgs() << "\nRemoving store:"; StoreBase.dump(); |
0 |
| 20811 |
dbgs() << "\nwithin LIFETIME_END of : "; |
--- |
20811 |
dbgs() << "\nwithin LIFETIME_END of : "; |
--- |
| 20812 |
LifetimeEndBase.dump(); dbgs() << "\n"); |
--- |
20812 |
LifetimeEndBase.dump(); dbgs() << "\n"); |
--- |
| 20813 |
CombineTo(ST, ST->getChain()); |
0 |
20813 |
CombineTo(ST, ST->getChain()); |
0 |
| 20814 |
return SDValue(N, 0); |
0 |
20814 |
return SDValue(N, 0); |
0 |
| 20815 |
} |
--- |
20815 |
} |
--- |
| 20816 |
} |
--- |
20816 |
} |
--- |
| 20817 |
} |
--- |
20817 |
} |
--- |
| 20818 |
} |
--- |
20818 |
} |
--- |
| 20819 |
return SDValue(); |
0 |
20819 |
return SDValue(); |
0 |
| 20820 |
} |
0 |
20820 |
} |
0 |
| 20821 |
|
--- |
20821 |
|
--- |
| 20822 |
/// For the instruction sequence of store below, F and I values |
--- |
20822 |
/// For the instruction sequence of store below, F and I values |
--- |
| 20823 |
/// are bundled together as an i64 value before being stored into memory. |
--- |
20823 |
/// are bundled together as an i64 value before being stored into memory. |
--- |
| 20824 |
/// Sometimes it is more efficent to generate separate stores for F and I, |
--- |
20824 |
/// Sometimes it is more efficent to generate separate stores for F and I, |
--- |
| 20825 |
/// which can remove the bitwise instructions or sink them to colder places. |
--- |
20825 |
/// which can remove the bitwise instructions or sink them to colder places. |
--- |
| 20826 |
/// |
--- |
20826 |
/// |
--- |
| 20827 |
/// (store (or (zext (bitcast F to i32) to i64), |
--- |
20827 |
/// (store (or (zext (bitcast F to i32) to i64), |
--- |
| 20828 |
/// (shl (zext I to i64), 32)), addr) --> |
--- |
20828 |
/// (shl (zext I to i64), 32)), addr) --> |
--- |
| 20829 |
/// (store F, addr) and (store I, addr+4) |
--- |
20829 |
/// (store F, addr) and (store I, addr+4) |
--- |
| 20830 |
/// |
--- |
20830 |
/// |
--- |
| 20831 |
/// Similarly, splitting for other merged store can also be beneficial, like: |
--- |
20831 |
/// Similarly, splitting for other merged store can also be beneficial, like: |
--- |
| 20832 |
/// For pair of {i32, i32}, i64 store --> two i32 stores. |
--- |
20832 |
/// For pair of {i32, i32}, i64 store --> two i32 stores. |
--- |
| 20833 |
/// For pair of {i32, i16}, i64 store --> two i32 stores. |
--- |
20833 |
/// For pair of {i32, i16}, i64 store --> two i32 stores. |
--- |
| 20834 |
/// For pair of {i16, i16}, i32 store --> two i16 stores. |
--- |
20834 |
/// For pair of {i16, i16}, i32 store --> two i16 stores. |
--- |
| 20835 |
/// For pair of {i16, i8}, i32 store --> two i16 stores. |
--- |
20835 |
/// For pair of {i16, i8}, i32 store --> two i16 stores. |
--- |
| 20836 |
/// For pair of {i8, i8}, i16 store --> two i8 stores. |
--- |
20836 |
/// For pair of {i8, i8}, i16 store --> two i8 stores. |
--- |
| 20837 |
/// |
--- |
20837 |
/// |
--- |
| 20838 |
/// We allow each target to determine specifically which kind of splitting is |
--- |
20838 |
/// We allow each target to determine specifically which kind of splitting is |
--- |
| 20839 |
/// supported. |
--- |
20839 |
/// supported. |
--- |
| 20840 |
/// |
--- |
20840 |
/// |
--- |
| 20841 |
/// The store patterns are commonly seen from the simple code snippet below |
--- |
20841 |
/// The store patterns are commonly seen from the simple code snippet below |
--- |
| 20842 |
/// if only std::make_pair(...) is sroa transformed before inlined into hoo. |
--- |
20842 |
/// if only std::make_pair(...) is sroa transformed before inlined into hoo. |
--- |
| 20843 |
/// void goo(const std::pair &); |
--- |
20843 |
/// void goo(const std::pair &); |
--- |
| 20844 |
/// hoo() { |
--- |
20844 |
/// hoo() { |
--- |
| 20845 |
/// ... |
--- |
20845 |
/// ... |
--- |
| 20846 |
/// goo(std::make_pair(tmp, ftmp)); |
--- |
20846 |
/// goo(std::make_pair(tmp, ftmp)); |
--- |
| 20847 |
/// ... |
--- |
20847 |
/// ... |
--- |
| 20848 |
/// } |
--- |
20848 |
/// } |
--- |
| 20849 |
/// |
--- |
20849 |
/// |
--- |
| 20850 |
SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) { |
10 |
20850 |
SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) { |
10 |
| 20851 |
if (OptLevel == CodeGenOpt::None) |
10 |
20851 |
if (OptLevel == CodeGenOpt::None) |
10 |
| 20852 |
return SDValue(); |
10 |
20852 |
return SDValue(); |
10 |
| 20853 |
|
--- |
20853 |
|
--- |
| 20854 |
// Can't change the number of memory accesses for a volatile store or break |
--- |
20854 |
// Can't change the number of memory accesses for a volatile store or break |
--- |
| 20855 |
// atomicity for an atomic one. |
--- |
20855 |
// atomicity for an atomic one. |
--- |
| 20856 |
if (!ST->isSimple()) |
0 |
20856 |
if (!ST->isSimple()) |
0 |
| 20857 |
return SDValue(); |
0 |
20857 |
return SDValue(); |
0 |
| 20858 |
|
--- |
20858 |
|
--- |
| 20859 |
SDValue Val = ST->getValue(); |
0 |
20859 |
SDValue Val = ST->getValue(); |
0 |
| 20860 |
SDLoc DL(ST); |
0 |
20860 |
SDLoc DL(ST); |
0 |
| 20861 |
|
--- |
20861 |
|
--- |
| 20862 |
// Match OR operand. |
--- |
20862 |
// Match OR operand. |
--- |
| 20863 |
if (!Val.getValueType().isScalarInteger() || Val.getOpcode() != ISD::OR) |
0 |
20863 |
if (!Val.getValueType().isScalarInteger() || Val.getOpcode() != ISD::OR) |
0 |
| 20864 |
return SDValue(); |
0 |
20864 |
return SDValue(); |
0 |
| 20865 |
|
--- |
20865 |
|
--- |
| 20866 |
// Match SHL operand and get Lower and Higher parts of Val. |
--- |
20866 |
// Match SHL operand and get Lower and Higher parts of Val. |
--- |
| 20867 |
SDValue Op1 = Val.getOperand(0); |
0 |
20867 |
SDValue Op1 = Val.getOperand(0); |
0 |
| 20868 |
SDValue Op2 = Val.getOperand(1); |
0 |
20868 |
SDValue Op2 = Val.getOperand(1); |
0 |
| 20869 |
SDValue Lo, Hi; |
0 |
20869 |
SDValue Lo, Hi; |
0 |
| 20870 |
if (Op1.getOpcode() != ISD::SHL) { |
0 |
20870 |
if (Op1.getOpcode() != ISD::SHL) { |
0 |
| 20871 |
std::swap(Op1, Op2); |
0 |
20871 |
std::swap(Op1, Op2); |
0 |
| 20872 |
if (Op1.getOpcode() != ISD::SHL) |
0 |
20872 |
if (Op1.getOpcode() != ISD::SHL) |
0 |
| 20873 |
return SDValue(); |
0 |
20873 |
return SDValue(); |
0 |
| 20874 |
} |
--- |
20874 |
} |
--- |
| 20875 |
Lo = Op2; |
0 |
20875 |
Lo = Op2; |
0 |
| 20876 |
Hi = Op1.getOperand(0); |
0 |
20876 |
Hi = Op1.getOperand(0); |
0 |
| 20877 |
if (!Op1.hasOneUse()) |
0 |
20877 |
if (!Op1.hasOneUse()) |
0 |
| 20878 |
return SDValue(); |
0 |
20878 |
return SDValue(); |
0 |
| 20879 |
|
--- |
20879 |
|
--- |
| 20880 |
// Match shift amount to HalfValBitSize. |
--- |
20880 |
// Match shift amount to HalfValBitSize. |
--- |
| 20881 |
unsigned HalfValBitSize = Val.getValueSizeInBits() / 2; |
0 |
20881 |
unsigned HalfValBitSize = Val.getValueSizeInBits() / 2; |
0 |
| 20882 |
ConstantSDNode *ShAmt = dyn_cast(Op1.getOperand(1)); |
0 |
20882 |
ConstantSDNode *ShAmt = dyn_cast(Op1.getOperand(1)); |
0 |
| 20883 |
if (!ShAmt || ShAmt->getAPIntValue() != HalfValBitSize) |
0 |
20883 |
if (!ShAmt || ShAmt->getAPIntValue() != HalfValBitSize) |
0 |
| 20884 |
return SDValue(); |
0 |
20884 |
return SDValue(); |
0 |
| 20885 |
|
--- |
20885 |
|
--- |
| 20886 |
// Lo and Hi are zero-extended from int with size less equal than 32 |
--- |
20886 |
// Lo and Hi are zero-extended from int with size less equal than 32 |
--- |
| 20887 |
// to i64. |
--- |
20887 |
// to i64. |
--- |
| 20888 |
if (Lo.getOpcode() != ISD::ZERO_EXTEND || !Lo.hasOneUse() || |
0 |
20888 |
if (Lo.getOpcode() != ISD::ZERO_EXTEND || !Lo.hasOneUse() || |
0 |
| 20889 |
!Lo.getOperand(0).getValueType().isScalarInteger() || |
0 |
20889 |
!Lo.getOperand(0).getValueType().isScalarInteger() || |
0 |
| 20890 |
Lo.getOperand(0).getValueSizeInBits() > HalfValBitSize || |
0 |
20890 |
Lo.getOperand(0).getValueSizeInBits() > HalfValBitSize || |
0 |
| 20891 |
Hi.getOpcode() != ISD::ZERO_EXTEND || !Hi.hasOneUse() || |
0 |
20891 |
Hi.getOpcode() != ISD::ZERO_EXTEND || !Hi.hasOneUse() || |
0 |
| 20892 |
!Hi.getOperand(0).getValueType().isScalarInteger() || |
0 |
20892 |
!Hi.getOperand(0).getValueType().isScalarInteger() || |
0 |
| 20893 |
Hi.getOperand(0).getValueSizeInBits() > HalfValBitSize) |
0 |
20893 |
Hi.getOperand(0).getValueSizeInBits() > HalfValBitSize) |
0 |
| 20894 |
return SDValue(); |
0 |
20894 |
return SDValue(); |
0 |
| 20895 |
|
--- |
20895 |
|
--- |
| 20896 |
// Use the EVT of low and high parts before bitcast as the input |
--- |
20896 |
// Use the EVT of low and high parts before bitcast as the input |
--- |
| 20897 |
// of target query. |
--- |
20897 |
// of target query. |
--- |
| 20898 |
EVT LowTy = (Lo.getOperand(0).getOpcode() == ISD::BITCAST) |
0 |
20898 |
EVT LowTy = (Lo.getOperand(0).getOpcode() == ISD::BITCAST) |
0 |
| 20899 |
? Lo.getOperand(0).getValueType() |
0 |
20899 |
? Lo.getOperand(0).getValueType() |
0 |
| 20900 |
: Lo.getValueType(); |
0 |
20900 |
: Lo.getValueType(); |
0 |
| 20901 |
EVT HighTy = (Hi.getOperand(0).getOpcode() == ISD::BITCAST) |
0 |
20901 |
EVT HighTy = (Hi.getOperand(0).getOpcode() == ISD::BITCAST) |
0 |
| 20902 |
? Hi.getOperand(0).getValueType() |
0 |
20902 |
? Hi.getOperand(0).getValueType() |
0 |
| 20903 |
: Hi.getValueType(); |
0 |
20903 |
: Hi.getValueType(); |
0 |
| 20904 |
if (!TLI.isMultiStoresCheaperThanBitsMerge(LowTy, HighTy)) |
0 |
20904 |
if (!TLI.isMultiStoresCheaperThanBitsMerge(LowTy, HighTy)) |
0 |
| 20905 |
return SDValue(); |
0 |
20905 |
return SDValue(); |
0 |
| 20906 |
|
--- |
20906 |
|
--- |
| 20907 |
// Start to split store. |
--- |
20907 |
// Start to split store. |
--- |
| 20908 |
MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags(); |
0 |
20908 |
MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags(); |
0 |
| 20909 |
AAMDNodes AAInfo = ST->getAAInfo(); |
0 |
20909 |
AAMDNodes AAInfo = ST->getAAInfo(); |
0 |
| 20910 |
|
--- |
20910 |
|
--- |
| 20911 |
// Change the sizes of Lo and Hi's value types to HalfValBitSize. |
--- |
20911 |
// Change the sizes of Lo and Hi's value types to HalfValBitSize. |
--- |
| 20912 |
EVT VT = EVT::getIntegerVT(*DAG.getContext(), HalfValBitSize); |
0 |
20912 |
EVT VT = EVT::getIntegerVT(*DAG.getContext(), HalfValBitSize); |
0 |
| 20913 |
Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Lo.getOperand(0)); |
0 |
20913 |
Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Lo.getOperand(0)); |
0 |
| 20914 |
Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Hi.getOperand(0)); |
0 |
20914 |
Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Hi.getOperand(0)); |
0 |
| 20915 |
|
--- |
20915 |
|
--- |
| 20916 |
SDValue Chain = ST->getChain(); |
0 |
20916 |
SDValue Chain = ST->getChain(); |
0 |
| 20917 |
SDValue Ptr = ST->getBasePtr(); |
0 |
20917 |
SDValue Ptr = ST->getBasePtr(); |
0 |
| 20918 |
// Lower value store. |
--- |
20918 |
// Lower value store. |
--- |
| 20919 |
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(), |
0 |
20919 |
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(), |
0 |
| 20920 |
ST->getOriginalAlign(), MMOFlags, AAInfo); |
--- |
20920 |
ST->getOriginalAlign(), MMOFlags, AAInfo); |
--- |
| 20921 |
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(HalfValBitSize / 8), DL); |
0 |
20921 |
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(HalfValBitSize / 8), DL); |
0 |
| 20922 |
// Higher value store. |
--- |
20922 |
// Higher value store. |
--- |
| 20923 |
SDValue St1 = DAG.getStore( |
0 |
20923 |
SDValue St1 = DAG.getStore( |
0 |
| 20924 |
St0, DL, Hi, Ptr, ST->getPointerInfo().getWithOffset(HalfValBitSize / 8), |
0 |
20924 |
St0, DL, Hi, Ptr, ST->getPointerInfo().getWithOffset(HalfValBitSize / 8), |
0 |
| 20925 |
ST->getOriginalAlign(), MMOFlags, AAInfo); |
--- |
20925 |
ST->getOriginalAlign(), MMOFlags, AAInfo); |
--- |
| 20926 |
return St1; |
0 |
20926 |
return St1; |
0 |
| 20927 |
} |
0 |
20927 |
} |
0 |
| 20928 |
|
--- |
20928 |
|
--- |
| 20929 |
// Merge an insertion into an existing shuffle: |
--- |
20929 |
// Merge an insertion into an existing shuffle: |
--- |
| 20930 |
// (insert_vector_elt (vector_shuffle X, Y, Mask), |
--- |
20930 |
// (insert_vector_elt (vector_shuffle X, Y, Mask), |
--- |
| 20931 |
// .(extract_vector_elt X, N), InsIndex) |
--- |
20931 |
// .(extract_vector_elt X, N), InsIndex) |
--- |
| 20932 |
// --> (vector_shuffle X, Y, NewMask) |
--- |
20932 |
// --> (vector_shuffle X, Y, NewMask) |
--- |
| 20933 |
// and variations where shuffle operands may be CONCAT_VECTORS. |
--- |
20933 |
// and variations where shuffle operands may be CONCAT_VECTORS. |
--- |
| 20934 |
static bool mergeEltWithShuffle(SDValue &X, SDValue &Y, ArrayRef Mask, |
0 |
20934 |
static bool mergeEltWithShuffle(SDValue &X, SDValue &Y, ArrayRef Mask, |
0 |
| 20935 |
SmallVectorImpl &NewMask, SDValue Elt, |
--- |
20935 |
SmallVectorImpl &NewMask, SDValue Elt, |
--- |
| 20936 |
unsigned InsIndex) { |
--- |
20936 |
unsigned InsIndex) { |
--- |
| 20937 |
if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT || |
0 |
20937 |
if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT || |
0 |
| 20938 |
!isa(Elt.getOperand(1))) |
0 |
20938 |
!isa(Elt.getOperand(1))) |
0 |
| 20939 |
return false; |
0 |
20939 |
return false; |
0 |
| 20940 |
|
--- |
20940 |
|
--- |
| 20941 |
// Vec's operand 0 is using indices from 0 to N-1 and |
--- |
20941 |
// Vec's operand 0 is using indices from 0 to N-1 and |
--- |
| 20942 |
// operand 1 from N to 2N - 1, where N is the number of |
--- |
20942 |
// operand 1 from N to 2N - 1, where N is the number of |
--- |
| 20943 |
// elements in the vectors. |
--- |
20943 |
// elements in the vectors. |
--- |
| 20944 |
SDValue InsertVal0 = Elt.getOperand(0); |
0 |
20944 |
SDValue InsertVal0 = Elt.getOperand(0); |
0 |
| 20945 |
int ElementOffset = -1; |
0 |
20945 |
int ElementOffset = -1; |
0 |
| 20946 |
|
--- |
20946 |
|
--- |
| 20947 |
// We explore the inputs of the shuffle in order to see if we find the |
--- |
20947 |
// We explore the inputs of the shuffle in order to see if we find the |
--- |
| 20948 |
// source of the extract_vector_elt. If so, we can use it to modify the |
--- |
20948 |
// source of the extract_vector_elt. If so, we can use it to modify the |
--- |
| 20949 |
// shuffle rather than perform an insert_vector_elt. |
--- |
20949 |
// shuffle rather than perform an insert_vector_elt. |
--- |
| 20950 |
SmallVector, 8> ArgWorkList; |
0 |
20950 |
SmallVector, 8> ArgWorkList; |
0 |
| 20951 |
ArgWorkList.emplace_back(Mask.size(), Y); |
0 |
20951 |
ArgWorkList.emplace_back(Mask.size(), Y); |
0 |
| 20952 |
ArgWorkList.emplace_back(0, X); |
0 |
20952 |
ArgWorkList.emplace_back(0, X); |
0 |
| 20953 |
|
--- |
20953 |
|
--- |
| 20954 |
while (!ArgWorkList.empty()) { |
0 |
20954 |
while (!ArgWorkList.empty()) { |
0 |
| 20955 |
int ArgOffset; |
--- |
20955 |
int ArgOffset; |
--- |
| 20956 |
SDValue ArgVal; |
0 |
20956 |
SDValue ArgVal; |
0 |
| 20957 |
std::tie(ArgOffset, ArgVal) = ArgWorkList.pop_back_val(); |
0 |
20957 |
std::tie(ArgOffset, ArgVal) = ArgWorkList.pop_back_val(); |
0 |
| 20958 |
|
--- |
20958 |
|
--- |
| 20959 |
if (ArgVal == InsertVal0) { |
0 |
20959 |
if (ArgVal == InsertVal0) { |
0 |
| 20960 |
ElementOffset = ArgOffset; |
0 |
20960 |
ElementOffset = ArgOffset; |
0 |
| 20961 |
break; |
0 |
20961 |
break; |
0 |
| 20962 |
} |
--- |
20962 |
} |
--- |
| 20963 |
|
--- |
20963 |
|
--- |
| 20964 |
// Peek through concat_vector. |
--- |
20964 |
// Peek through concat_vector. |
--- |
| 20965 |
if (ArgVal.getOpcode() == ISD::CONCAT_VECTORS) { |
0 |
20965 |
if (ArgVal.getOpcode() == ISD::CONCAT_VECTORS) { |
0 |
| 20966 |
int CurrentArgOffset = |
--- |
20966 |
int CurrentArgOffset = |
--- |
| 20967 |
ArgOffset + ArgVal.getValueType().getVectorNumElements(); |
0 |
20967 |
ArgOffset + ArgVal.getValueType().getVectorNumElements(); |
0 |
| 20968 |
int Step = ArgVal.getOperand(0).getValueType().getVectorNumElements(); |
0 |
20968 |
int Step = ArgVal.getOperand(0).getValueType().getVectorNumElements(); |
0 |
| 20969 |
for (SDValue Op : reverse(ArgVal->ops())) { |
0 |
20969 |
for (SDValue Op : reverse(ArgVal->ops())) { |
0 |
| 20970 |
CurrentArgOffset -= Step; |
0 |
20970 |
CurrentArgOffset -= Step; |
0 |
| 20971 |
ArgWorkList.emplace_back(CurrentArgOffset, Op); |
0 |
20971 |
ArgWorkList.emplace_back(CurrentArgOffset, Op); |
0 |
| 20972 |
} |
--- |
20972 |
} |
--- |
| 20973 |
|
--- |
20973 |
|
--- |
| 20974 |
// Make sure we went through all the elements and did not screw up index |
--- |
20974 |
// Make sure we went through all the elements and did not screw up index |
--- |
| 20975 |
// computation. |
--- |
20975 |
// computation. |
--- |
| 20976 |
assert(CurrentArgOffset == ArgOffset); |
0 |
20976 |
assert(CurrentArgOffset == ArgOffset); |
0 |
| 20977 |
} |
--- |
20977 |
} |
--- |
| 20978 |
} |
--- |
20978 |
} |
--- |
| 20979 |
|
--- |
20979 |
|
--- |
| 20980 |
// If we failed to find a match, see if we can replace an UNDEF shuffle |
--- |
20980 |
// If we failed to find a match, see if we can replace an UNDEF shuffle |
--- |
| 20981 |
// operand. |
--- |
20981 |
// operand. |
--- |
| 20982 |
if (ElementOffset == -1) { |
0 |
20982 |
if (ElementOffset == -1) { |
0 |
| 20983 |
if (!Y.isUndef() || InsertVal0.getValueType() != Y.getValueType()) |
0 |
20983 |
if (!Y.isUndef() || InsertVal0.getValueType() != Y.getValueType()) |
0 |
| 20984 |
return false; |
0 |
20984 |
return false; |
0 |
| 20985 |
ElementOffset = Mask.size(); |
0 |
20985 |
ElementOffset = Mask.size(); |
0 |
| 20986 |
Y = InsertVal0; |
0 |
20986 |
Y = InsertVal0; |
0 |
| 20987 |
} |
--- |
20987 |
} |
--- |
| 20988 |
|
--- |
20988 |
|
--- |
| 20989 |
NewMask.assign(Mask.begin(), Mask.end()); |
0 |
20989 |
NewMask.assign(Mask.begin(), Mask.end()); |
0 |
| 20990 |
NewMask[InsIndex] = ElementOffset + Elt.getConstantOperandVal(1); |
0 |
20990 |
NewMask[InsIndex] = ElementOffset + Elt.getConstantOperandVal(1); |
0 |
| 20991 |
assert(NewMask[InsIndex] < (int)(2 * Mask.size()) && NewMask[InsIndex] >= 0 && |
0 |
20991 |
assert(NewMask[InsIndex] < (int)(2 * Mask.size()) && NewMask[InsIndex] >= 0 && |
0 |
| 20992 |
"NewMask[InsIndex] is out of bound"); |
--- |
20992 |
"NewMask[InsIndex] is out of bound"); |
--- |
| 20993 |
return true; |
0 |
20993 |
return true; |
0 |
| 20994 |
} |
0 |
20994 |
} |
0 |
| 20995 |
|
--- |
20995 |
|
--- |
| 20996 |
// Merge an insertion into an existing shuffle: |
--- |
20996 |
// Merge an insertion into an existing shuffle: |
--- |
| 20997 |
// (insert_vector_elt (vector_shuffle X, Y), (extract_vector_elt X, N), |
--- |
20997 |
// (insert_vector_elt (vector_shuffle X, Y), (extract_vector_elt X, N), |
--- |
| 20998 |
// InsIndex) |
--- |
20998 |
// InsIndex) |
--- |
| 20999 |
// --> (vector_shuffle X, Y) and variations where shuffle operands may be |
--- |
20999 |
// --> (vector_shuffle X, Y) and variations where shuffle operands may be |
--- |
| 21000 |
// CONCAT_VECTORS. |
--- |
21000 |
// CONCAT_VECTORS. |
--- |
| 21001 |
SDValue DAGCombiner::mergeInsertEltWithShuffle(SDNode *N, unsigned InsIndex) { |
0 |
21001 |
SDValue DAGCombiner::mergeInsertEltWithShuffle(SDNode *N, unsigned InsIndex) { |
0 |
| 21002 |
assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && |
0 |
21002 |
assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && |
0 |
| 21003 |
"Expected extract_vector_elt"); |
--- |
21003 |
"Expected extract_vector_elt"); |
--- |
| 21004 |
SDValue InsertVal = N->getOperand(1); |
0 |
21004 |
SDValue InsertVal = N->getOperand(1); |
0 |
| 21005 |
SDValue Vec = N->getOperand(0); |
0 |
21005 |
SDValue Vec = N->getOperand(0); |
0 |
| 21006 |
|
--- |
21006 |
|
--- |
| 21007 |
auto *SVN = dyn_cast(Vec); |
0 |
21007 |
auto *SVN = dyn_cast(Vec); |
0 |
| 21008 |
if (!SVN || !Vec.hasOneUse()) |
0 |
21008 |
if (!SVN || !Vec.hasOneUse()) |
0 |
| 21009 |
return SDValue(); |
0 |
21009 |
return SDValue(); |
0 |
| 21010 |
|
--- |
21010 |
|
--- |
| 21011 |
ArrayRef Mask = SVN->getMask(); |
0 |
21011 |
ArrayRef Mask = SVN->getMask(); |
0 |
| 21012 |
SDValue X = Vec.getOperand(0); |
0 |
21012 |
SDValue X = Vec.getOperand(0); |
0 |
| 21013 |
SDValue Y = Vec.getOperand(1); |
0 |
21013 |
SDValue Y = Vec.getOperand(1); |
0 |
| 21014 |
|
--- |
21014 |
|
--- |
| 21015 |
SmallVector NewMask(Mask); |
0 |
21015 |
SmallVector NewMask(Mask); |
0 |
| 21016 |
if (mergeEltWithShuffle(X, Y, Mask, NewMask, InsertVal, InsIndex)) { |
0 |
21016 |
if (mergeEltWithShuffle(X, Y, Mask, NewMask, InsertVal, InsIndex)) { |
0 |
| 21017 |
SDValue LegalShuffle = TLI.buildLegalVectorShuffle( |
0 |
21017 |
SDValue LegalShuffle = TLI.buildLegalVectorShuffle( |
0 |
| 21018 |
Vec.getValueType(), SDLoc(N), X, Y, NewMask, DAG); |
0 |
21018 |
Vec.getValueType(), SDLoc(N), X, Y, NewMask, DAG); |
0 |
| 21019 |
if (LegalShuffle) |
0 |
21019 |
if (LegalShuffle) |
0 |
| 21020 |
return LegalShuffle; |
0 |
21020 |
return LegalShuffle; |
0 |
| 21021 |
} |
--- |
21021 |
} |
--- |
| 21022 |
|
--- |
21022 |
|
--- |
| 21023 |
return SDValue(); |
0 |
21023 |
return SDValue(); |
0 |
| 21024 |
} |
0 |
21024 |
} |
0 |
| 21025 |
|
--- |
21025 |
|
--- |
| 21026 |
// Convert a disguised subvector insertion into a shuffle: |
--- |
21026 |
// Convert a disguised subvector insertion into a shuffle: |
--- |
| 21027 |
// insert_vector_elt V, (bitcast X from vector type), IdxC --> |
--- |
21027 |
// insert_vector_elt V, (bitcast X from vector type), IdxC --> |
--- |
| 21028 |
// bitcast(shuffle (bitcast V), (extended X), Mask) |
--- |
21028 |
// bitcast(shuffle (bitcast V), (extended X), Mask) |
--- |
| 21029 |
// Note: We do not use an insert_subvector node because that requires a |
--- |
21029 |
// Note: We do not use an insert_subvector node because that requires a |
--- |
| 21030 |
// legal subvector type. |
--- |
21030 |
// legal subvector type. |
--- |
| 21031 |
SDValue DAGCombiner::combineInsertEltToShuffle(SDNode *N, unsigned InsIndex) { |
0 |
21031 |
SDValue DAGCombiner::combineInsertEltToShuffle(SDNode *N, unsigned InsIndex) { |
0 |
| 21032 |
assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && |
0 |
21032 |
assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && |
0 |
| 21033 |
"Expected extract_vector_elt"); |
--- |
21033 |
"Expected extract_vector_elt"); |
--- |
| 21034 |
SDValue InsertVal = N->getOperand(1); |
0 |
21034 |
SDValue InsertVal = N->getOperand(1); |
0 |
| 21035 |
|
--- |
21035 |
|
--- |
| 21036 |
if (InsertVal.getOpcode() != ISD::BITCAST || !InsertVal.hasOneUse() || |
0 |
21036 |
if (InsertVal.getOpcode() != ISD::BITCAST || !InsertVal.hasOneUse() || |
0 |
| 21037 |
!InsertVal.getOperand(0).getValueType().isVector()) |
0 |
21037 |
!InsertVal.getOperand(0).getValueType().isVector()) |
0 |
| 21038 |
return SDValue(); |
0 |
21038 |
return SDValue(); |
0 |
| 21039 |
|
--- |
21039 |
|
--- |
| 21040 |
SDValue SubVec = InsertVal.getOperand(0); |
0 |
21040 |
SDValue SubVec = InsertVal.getOperand(0); |
0 |
| 21041 |
SDValue DestVec = N->getOperand(0); |
0 |
21041 |
SDValue DestVec = N->getOperand(0); |
0 |
| 21042 |
EVT SubVecVT = SubVec.getValueType(); |
0 |
21042 |
EVT SubVecVT = SubVec.getValueType(); |
0 |
| 21043 |
EVT VT = DestVec.getValueType(); |
0 |
21043 |
EVT VT = DestVec.getValueType(); |
0 |
| 21044 |
unsigned NumSrcElts = SubVecVT.getVectorNumElements(); |
0 |
21044 |
unsigned NumSrcElts = SubVecVT.getVectorNumElements(); |
0 |
| 21045 |
// If the source only has a single vector element, the cost of creating adding |
--- |
21045 |
// If the source only has a single vector element, the cost of creating adding |
--- |
| 21046 |
// it to a vector is likely to exceed the cost of a insert_vector_elt. |
--- |
21046 |
// it to a vector is likely to exceed the cost of a insert_vector_elt. |
--- |
| 21047 |
if (NumSrcElts == 1) |
0 |
21047 |
if (NumSrcElts == 1) |
0 |
| 21048 |
return SDValue(); |
0 |
21048 |
return SDValue(); |
0 |
| 21049 |
unsigned ExtendRatio = VT.getSizeInBits() / SubVecVT.getSizeInBits(); |
0 |
21049 |
unsigned ExtendRatio = VT.getSizeInBits() / SubVecVT.getSizeInBits(); |
0 |
| 21050 |
unsigned NumMaskVals = ExtendRatio * NumSrcElts; |
0 |
21050 |
unsigned NumMaskVals = ExtendRatio * NumSrcElts; |
0 |
| 21051 |
|
--- |
21051 |
|
--- |
| 21052 |
// Step 1: Create a shuffle mask that implements this insert operation. The |
--- |
21052 |
// Step 1: Create a shuffle mask that implements this insert operation. The |
--- |
| 21053 |
// vector that we are inserting into will be operand 0 of the shuffle, so |
--- |
21053 |
// vector that we are inserting into will be operand 0 of the shuffle, so |
--- |
| 21054 |
// those elements are just 'i'. The inserted subvector is in the first |
--- |
21054 |
// those elements are just 'i'. The inserted subvector is in the first |
--- |
| 21055 |
// positions of operand 1 of the shuffle. Example: |
--- |
21055 |
// positions of operand 1 of the shuffle. Example: |
--- |
| 21056 |
// insert v4i32 V, (v2i16 X), 2 --> shuffle v8i16 V', X', {0,1,2,3,8,9,6,7} |
--- |
21056 |
// insert v4i32 V, (v2i16 X), 2 --> shuffle v8i16 V', X', {0,1,2,3,8,9,6,7} |
--- |
| 21057 |
SmallVector Mask(NumMaskVals); |
0 |
21057 |
SmallVector Mask(NumMaskVals); |
0 |
| 21058 |
for (unsigned i = 0; i != NumMaskVals; ++i) { |
0 |
21058 |
for (unsigned i = 0; i != NumMaskVals; ++i) { |
0 |
| 21059 |
if (i / NumSrcElts == InsIndex) |
0 |
21059 |
if (i / NumSrcElts == InsIndex) |
0 |
| 21060 |
Mask[i] = (i % NumSrcElts) + NumMaskVals; |
0 |
21060 |
Mask[i] = (i % NumSrcElts) + NumMaskVals; |
0 |
| 21061 |
else |
--- |
21061 |
else |
--- |
| 21062 |
Mask[i] = i; |
0 |
21062 |
Mask[i] = i; |
0 |
| 21063 |
} |
--- |
21063 |
} |
--- |
| 21064 |
|
--- |
21064 |
|
--- |
| 21065 |
// Bail out if the target can not handle the shuffle we want to create. |
--- |
21065 |
// Bail out if the target can not handle the shuffle we want to create. |
--- |
| 21066 |
EVT SubVecEltVT = SubVecVT.getVectorElementType(); |
0 |
21066 |
EVT SubVecEltVT = SubVecVT.getVectorElementType(); |
0 |
| 21067 |
EVT ShufVT = EVT::getVectorVT(*DAG.getContext(), SubVecEltVT, NumMaskVals); |
0 |
21067 |
EVT ShufVT = EVT::getVectorVT(*DAG.getContext(), SubVecEltVT, NumMaskVals); |
0 |
| 21068 |
if (!TLI.isShuffleMaskLegal(Mask, ShufVT)) |
0 |
21068 |
if (!TLI.isShuffleMaskLegal(Mask, ShufVT)) |
0 |
| 21069 |
return SDValue(); |
0 |
21069 |
return SDValue(); |
0 |
| 21070 |
|
--- |
21070 |
|
--- |
| 21071 |
// Step 2: Create a wide vector from the inserted source vector by appending |
--- |
21071 |
// Step 2: Create a wide vector from the inserted source vector by appending |
--- |
| 21072 |
// undefined elements. This is the same size as our destination vector. |
--- |
21072 |
// undefined elements. This is the same size as our destination vector. |
--- |
| 21073 |
SDLoc DL(N); |
0 |
21073 |
SDLoc DL(N); |
0 |
| 21074 |
SmallVector ConcatOps(ExtendRatio, DAG.getUNDEF(SubVecVT)); |
0 |
21074 |
SmallVector ConcatOps(ExtendRatio, DAG.getUNDEF(SubVecVT)); |
0 |
| 21075 |
ConcatOps[0] = SubVec; |
0 |
21075 |
ConcatOps[0] = SubVec; |
0 |
| 21076 |
SDValue PaddedSubV = DAG.getNode(ISD::CONCAT_VECTORS, DL, ShufVT, ConcatOps); |
0 |
21076 |
SDValue PaddedSubV = DAG.getNode(ISD::CONCAT_VECTORS, DL, ShufVT, ConcatOps); |
0 |
| 21077 |
|
--- |
21077 |
|
--- |
| 21078 |
// Step 3: Shuffle in the padded subvector. |
--- |
21078 |
// Step 3: Shuffle in the padded subvector. |
--- |
| 21079 |
SDValue DestVecBC = DAG.getBitcast(ShufVT, DestVec); |
0 |
21079 |
SDValue DestVecBC = DAG.getBitcast(ShufVT, DestVec); |
0 |
| 21080 |
SDValue Shuf = DAG.getVectorShuffle(ShufVT, DL, DestVecBC, PaddedSubV, Mask); |
0 |
21080 |
SDValue Shuf = DAG.getVectorShuffle(ShufVT, DL, DestVecBC, PaddedSubV, Mask); |
0 |
| 21081 |
AddToWorklist(PaddedSubV.getNode()); |
0 |
21081 |
AddToWorklist(PaddedSubV.getNode()); |
0 |
| 21082 |
AddToWorklist(DestVecBC.getNode()); |
0 |
21082 |
AddToWorklist(DestVecBC.getNode()); |
0 |
| 21083 |
AddToWorklist(Shuf.getNode()); |
0 |
21083 |
AddToWorklist(Shuf.getNode()); |
0 |
| 21084 |
return DAG.getBitcast(VT, Shuf); |
0 |
21084 |
return DAG.getBitcast(VT, Shuf); |
0 |
| 21085 |
} |
0 |
21085 |
} |
0 |
| 21086 |
|
--- |
21086 |
|
--- |
| 21087 |
// Combine insert(shuffle(load, ), load, 0) into a single load if |
--- |
21087 |
// Combine insert(shuffle(load, ), load, 0) into a single load if |
--- |
| 21088 |
// possible and the new load will be quick. We use more loads but less shuffles |
--- |
21088 |
// possible and the new load will be quick. We use more loads but less shuffles |
--- |
| 21089 |
// and inserts. |
--- |
21089 |
// and inserts. |
--- |
| 21090 |
SDValue DAGCombiner::combineInsertEltToLoad(SDNode *N, unsigned InsIndex) { |
0 |
21090 |
SDValue DAGCombiner::combineInsertEltToLoad(SDNode *N, unsigned InsIndex) { |
0 |
| 21091 |
EVT VT = N->getValueType(0); |
0 |
21091 |
EVT VT = N->getValueType(0); |
0 |
| 21092 |
|
--- |
21092 |
|
--- |
| 21093 |
// InsIndex is expected to be the first of last lane. |
--- |
21093 |
// InsIndex is expected to be the first of last lane. |
--- |
| 21094 |
if (!VT.isFixedLengthVector() || |
0 |
21094 |
if (!VT.isFixedLengthVector() || |
0 |
| 21095 |
(InsIndex != 0 && InsIndex != VT.getVectorNumElements() - 1)) |
0 |
21095 |
(InsIndex != 0 && InsIndex != VT.getVectorNumElements() - 1)) |
0 |
| 21096 |
return SDValue(); |
0 |
21096 |
return SDValue(); |
0 |
| 21097 |
|
--- |
21097 |
|
--- |
| 21098 |
// Look for a shuffle with the mask u,0,1,2,3,4,5,6 or 1,2,3,4,5,6,7,u |
--- |
21098 |
// Look for a shuffle with the mask u,0,1,2,3,4,5,6 or 1,2,3,4,5,6,7,u |
--- |
| 21099 |
// depending on the InsIndex. |
--- |
21099 |
// depending on the InsIndex. |
--- |
| 21100 |
auto *Shuffle = dyn_cast(N->getOperand(0)); |
0 |
21100 |
auto *Shuffle = dyn_cast(N->getOperand(0)); |
0 |
| 21101 |
SDValue Scalar = N->getOperand(1); |
0 |
21101 |
SDValue Scalar = N->getOperand(1); |
0 |
| 21102 |
if (!Shuffle || !all_of(enumerate(Shuffle->getMask()), [&](auto P) { |
0 |
21102 |
if (!Shuffle || !all_of(enumerate(Shuffle->getMask()), [&](auto P) { |
0 |
| 21103 |
return InsIndex == P.index() || P.value() < 0 || |
0 |
21103 |
return InsIndex == P.index() || P.value() < 0 || |
0 |
| 21104 |
(InsIndex == 0 && P.value() == (int)P.index() - 1) || |
0 |
21104 |
(InsIndex == 0 && P.value() == (int)P.index() - 1) || |
0 |
| 21105 |
(InsIndex == VT.getVectorNumElements() - 1 && |
0 |
21105 |
(InsIndex == VT.getVectorNumElements() - 1 && |
0 |
| 21106 |
P.value() == (int)P.index() + 1); |
0 |
21106 |
P.value() == (int)P.index() + 1); |
0 |
| 21107 |
})) |
--- |
21107 |
})) |
--- |
| 21108 |
return SDValue(); |
0 |
21108 |
return SDValue(); |
0 |
| 21109 |
|
--- |
21109 |
|
--- |
| 21110 |
// We optionally skip over an extend so long as both loads are extended in the |
--- |
21110 |
// We optionally skip over an extend so long as both loads are extended in the |
--- |
| 21111 |
// same way from the same type. |
--- |
21111 |
// same way from the same type. |
--- |
| 21112 |
unsigned Extend = 0; |
0 |
21112 |
unsigned Extend = 0; |
0 |
| 21113 |
if (Scalar.getOpcode() == ISD::ZERO_EXTEND || |
0 |
21113 |
if (Scalar.getOpcode() == ISD::ZERO_EXTEND || |
0 |
| 21114 |
Scalar.getOpcode() == ISD::SIGN_EXTEND || |
0 |
21114 |
Scalar.getOpcode() == ISD::SIGN_EXTEND || |
0 |
| 21115 |
Scalar.getOpcode() == ISD::ANY_EXTEND) { |
0 |
21115 |
Scalar.getOpcode() == ISD::ANY_EXTEND) { |
0 |
| 21116 |
Extend = Scalar.getOpcode(); |
0 |
21116 |
Extend = Scalar.getOpcode(); |
0 |
| 21117 |
Scalar = Scalar.getOperand(0); |
0 |
21117 |
Scalar = Scalar.getOperand(0); |
0 |
| 21118 |
} |
--- |
21118 |
} |
--- |
| 21119 |
|
--- |
21119 |
|
--- |
| 21120 |
auto *ScalarLoad = dyn_cast(Scalar); |
0 |
21120 |
auto *ScalarLoad = dyn_cast(Scalar); |
0 |
| 21121 |
if (!ScalarLoad) |
0 |
21121 |
if (!ScalarLoad) |
0 |
| 21122 |
return SDValue(); |
0 |
21122 |
return SDValue(); |
0 |
| 21123 |
|
--- |
21123 |
|
--- |
| 21124 |
SDValue Vec = Shuffle->getOperand(0); |
0 |
21124 |
SDValue Vec = Shuffle->getOperand(0); |
0 |
| 21125 |
if (Extend) { |
0 |
21125 |
if (Extend) { |
0 |
| 21126 |
if (Vec.getOpcode() != Extend) |
0 |
21126 |
if (Vec.getOpcode() != Extend) |
0 |
| 21127 |
return SDValue(); |
0 |
21127 |
return SDValue(); |
0 |
| 21128 |
Vec = Vec.getOperand(0); |
0 |
21128 |
Vec = Vec.getOperand(0); |
0 |
| 21129 |
} |
--- |
21129 |
} |
--- |
| 21130 |
auto *VecLoad = dyn_cast(Vec); |
0 |
21130 |
auto *VecLoad = dyn_cast(Vec); |
0 |
| 21131 |
if (!VecLoad || Vec.getValueType().getScalarType() != Scalar.getValueType()) |
0 |
21131 |
if (!VecLoad || Vec.getValueType().getScalarType() != Scalar.getValueType()) |
0 |
| 21132 |
return SDValue(); |
0 |
21132 |
return SDValue(); |
0 |
| 21133 |
|
--- |
21133 |
|
--- |
| 21134 |
int EltSize = ScalarLoad->getValueType(0).getScalarSizeInBits(); |
0 |
21134 |
int EltSize = ScalarLoad->getValueType(0).getScalarSizeInBits(); |
0 |
| 21135 |
if (EltSize == 0 || EltSize % 8 != 0 || !ScalarLoad->isSimple() || |
0 |
21135 |
if (EltSize == 0 || EltSize % 8 != 0 || !ScalarLoad->isSimple() || |
0 |
| 21136 |
!VecLoad->isSimple() || VecLoad->getExtensionType() != ISD::NON_EXTLOAD || |
0 |
21136 |
!VecLoad->isSimple() || VecLoad->getExtensionType() != ISD::NON_EXTLOAD || |
0 |
| 21137 |
ScalarLoad->getExtensionType() != ISD::NON_EXTLOAD || |
0 |
21137 |
ScalarLoad->getExtensionType() != ISD::NON_EXTLOAD || |
0 |
| 21138 |
ScalarLoad->getAddressSpace() != VecLoad->getAddressSpace()) |
0 |
21138 |
ScalarLoad->getAddressSpace() != VecLoad->getAddressSpace()) |
0 |
| 21139 |
return SDValue(); |
0 |
21139 |
return SDValue(); |
0 |
| 21140 |
|
--- |
21140 |
|
--- |
| 21141 |
// Check that the offset between the pointers to produce a single continuous |
--- |
21141 |
// Check that the offset between the pointers to produce a single continuous |
--- |
| 21142 |
// load. |
--- |
21142 |
// load. |
--- |
| 21143 |
if (InsIndex == 0) { |
0 |
21143 |
if (InsIndex == 0) { |
0 |
| 21144 |
if (!DAG.areNonVolatileConsecutiveLoads(ScalarLoad, VecLoad, EltSize / 8, |
0 |
21144 |
if (!DAG.areNonVolatileConsecutiveLoads(ScalarLoad, VecLoad, EltSize / 8, |
0 |
| 21145 |
-1)) |
--- |
21145 |
-1)) |
--- |
| 21146 |
return SDValue(); |
0 |
21146 |
return SDValue(); |
0 |
| 21147 |
} else { |
--- |
21147 |
} else { |
--- |
| 21148 |
if (!DAG.areNonVolatileConsecutiveLoads( |
0 |
21148 |
if (!DAG.areNonVolatileConsecutiveLoads( |
0 |
| 21149 |
VecLoad, ScalarLoad, VT.getVectorNumElements() * EltSize / 8, -1)) |
0 |
21149 |
VecLoad, ScalarLoad, VT.getVectorNumElements() * EltSize / 8, -1)) |
0 |
| 21150 |
return SDValue(); |
0 |
21150 |
return SDValue(); |
0 |
| 21151 |
} |
--- |
21151 |
} |
--- |
| 21152 |
|
--- |
21152 |
|
--- |
| 21153 |
// And that the new unaligned load will be fast. |
--- |
21153 |
// And that the new unaligned load will be fast. |
--- |
| 21154 |
unsigned IsFast = 0; |
0 |
21154 |
unsigned IsFast = 0; |
0 |
| 21155 |
Align NewAlign = commonAlignment(VecLoad->getAlign(), EltSize / 8); |
0 |
21155 |
Align NewAlign = commonAlignment(VecLoad->getAlign(), EltSize / 8); |
0 |
| 21156 |
if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), |
0 |
21156 |
if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), |
0 |
| 21157 |
Vec.getValueType(), VecLoad->getAddressSpace(), |
--- |
21157 |
Vec.getValueType(), VecLoad->getAddressSpace(), |
--- |
| 21158 |
NewAlign, VecLoad->getMemOperand()->getFlags(), |
0 |
21158 |
NewAlign, VecLoad->getMemOperand()->getFlags(), |
0 |
| 21159 |
&IsFast) || |
0 |
21159 |
&IsFast) || |
0 |
| 21160 |
!IsFast) |
0 |
21160 |
!IsFast) |
0 |
| 21161 |
return SDValue(); |
0 |
21161 |
return SDValue(); |
0 |
| 21162 |
|
--- |
21162 |
|
--- |
| 21163 |
// Calculate the new Ptr and create the new load. |
--- |
21163 |
// Calculate the new Ptr and create the new load. |
--- |
| 21164 |
SDLoc DL(N); |
0 |
21164 |
SDLoc DL(N); |
0 |
| 21165 |
SDValue Ptr = ScalarLoad->getBasePtr(); |
0 |
21165 |
SDValue Ptr = ScalarLoad->getBasePtr(); |
0 |
| 21166 |
if (InsIndex != 0) |
0 |
21166 |
if (InsIndex != 0) |
0 |
| 21167 |
Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), VecLoad->getBasePtr(), |
0 |
21167 |
Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), VecLoad->getBasePtr(), |
0 |
| 21168 |
DAG.getConstant(EltSize / 8, DL, Ptr.getValueType())); |
0 |
21168 |
DAG.getConstant(EltSize / 8, DL, Ptr.getValueType())); |
0 |
| 21169 |
MachinePointerInfo PtrInfo = |
--- |
21169 |
MachinePointerInfo PtrInfo = |
--- |
| 21170 |
InsIndex == 0 ? ScalarLoad->getPointerInfo() |
0 |
21170 |
InsIndex == 0 ? ScalarLoad->getPointerInfo() |
0 |
| 21171 |
: VecLoad->getPointerInfo().getWithOffset(EltSize / 8); |
0 |
21171 |
: VecLoad->getPointerInfo().getWithOffset(EltSize / 8); |
0 |
| 21172 |
|
--- |
21172 |
|
--- |
| 21173 |
SDValue Load = DAG.getLoad(VecLoad->getValueType(0), DL, |
0 |
21173 |
SDValue Load = DAG.getLoad(VecLoad->getValueType(0), DL, |
0 |
| 21174 |
ScalarLoad->getChain(), Ptr, PtrInfo, NewAlign); |
0 |
21174 |
ScalarLoad->getChain(), Ptr, PtrInfo, NewAlign); |
0 |
| 21175 |
DAG.makeEquivalentMemoryOrdering(ScalarLoad, Load.getValue(1)); |
0 |
21175 |
DAG.makeEquivalentMemoryOrdering(ScalarLoad, Load.getValue(1)); |
0 |
| 21176 |
DAG.makeEquivalentMemoryOrdering(VecLoad, Load.getValue(1)); |
0 |
21176 |
DAG.makeEquivalentMemoryOrdering(VecLoad, Load.getValue(1)); |
0 |
| 21177 |
return Extend ? DAG.getNode(Extend, DL, VT, Load) : Load; |
0 |
21177 |
return Extend ? DAG.getNode(Extend, DL, VT, Load) : Load; |
0 |
| 21178 |
} |
0 |
21178 |
} |
0 |
| 21179 |
|
--- |
21179 |
|
--- |
| 21180 |
SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { |
0 |
21180 |
SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { |
0 |
| 21181 |
SDValue InVec = N->getOperand(0); |
0 |
21181 |
SDValue InVec = N->getOperand(0); |
0 |
| 21182 |
SDValue InVal = N->getOperand(1); |
0 |
21182 |
SDValue InVal = N->getOperand(1); |
0 |
| 21183 |
SDValue EltNo = N->getOperand(2); |
0 |
21183 |
SDValue EltNo = N->getOperand(2); |
0 |
| 21184 |
SDLoc DL(N); |
0 |
21184 |
SDLoc DL(N); |
0 |
| 21185 |
|
--- |
21185 |
|
--- |
| 21186 |
EVT VT = InVec.getValueType(); |
0 |
21186 |
EVT VT = InVec.getValueType(); |
0 |
| 21187 |
auto *IndexC = dyn_cast(EltNo); |
0 |
21187 |
auto *IndexC = dyn_cast(EltNo); |
0 |
| 21188 |
|
--- |
21188 |
|
--- |
| 21189 |
// Insert into out-of-bounds element is undefined. |
--- |
21189 |
// Insert into out-of-bounds element is undefined. |
--- |
| 21190 |
if (IndexC && VT.isFixedLengthVector() && |
0 |
21190 |
if (IndexC && VT.isFixedLengthVector() && |
0 |
| 21191 |
IndexC->getZExtValue() >= VT.getVectorNumElements()) |
0 |
21191 |
IndexC->getZExtValue() >= VT.getVectorNumElements()) |
0 |
| 21192 |
return DAG.getUNDEF(VT); |
0 |
21192 |
return DAG.getUNDEF(VT); |
0 |
| 21193 |
|
--- |
21193 |
|
--- |
| 21194 |
// Remove redundant insertions: |
--- |
21194 |
// Remove redundant insertions: |
--- |
| 21195 |
// (insert_vector_elt x (extract_vector_elt x idx) idx) -> x |
--- |
21195 |
// (insert_vector_elt x (extract_vector_elt x idx) idx) -> x |
--- |
| 21196 |
if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
0 |
21196 |
if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
0 |
| 21197 |
InVec == InVal.getOperand(0) && EltNo == InVal.getOperand(1)) |
0 |
21197 |
InVec == InVal.getOperand(0) && EltNo == InVal.getOperand(1)) |
0 |
| 21198 |
return InVec; |
0 |
21198 |
return InVec; |
0 |
| 21199 |
|
--- |
21199 |
|
--- |
| 21200 |
if (!IndexC) { |
0 |
21200 |
if (!IndexC) { |
0 |
| 21201 |
// If this is variable insert to undef vector, it might be better to splat: |
--- |
21201 |
// If this is variable insert to undef vector, it might be better to splat: |
--- |
| 21202 |
// inselt undef, InVal, EltNo --> build_vector < InVal, InVal, ... > |
--- |
21202 |
// inselt undef, InVal, EltNo --> build_vector < InVal, InVal, ... > |
--- |
| 21203 |
if (InVec.isUndef() && TLI.shouldSplatInsEltVarIndex(VT)) |
0 |
21203 |
if (InVec.isUndef() && TLI.shouldSplatInsEltVarIndex(VT)) |
0 |
| 21204 |
return DAG.getSplat(VT, DL, InVal); |
0 |
21204 |
return DAG.getSplat(VT, DL, InVal); |
0 |
| 21205 |
return SDValue(); |
0 |
21205 |
return SDValue(); |
0 |
| 21206 |
} |
--- |
21206 |
} |
--- |
| 21207 |
|
--- |
21207 |
|
--- |
| 21208 |
if (VT.isScalableVector()) |
0 |
21208 |
if (VT.isScalableVector()) |
0 |
| 21209 |
return SDValue(); |
0 |
21209 |
return SDValue(); |
0 |
| 21210 |
|
--- |
21210 |
|
--- |
| 21211 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
21211 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
| 21212 |
|
--- |
21212 |
|
--- |
| 21213 |
// We must know which element is being inserted for folds below here. |
--- |
21213 |
// We must know which element is being inserted for folds below here. |
--- |
| 21214 |
unsigned Elt = IndexC->getZExtValue(); |
0 |
21214 |
unsigned Elt = IndexC->getZExtValue(); |
0 |
| 21215 |
|
--- |
21215 |
|
--- |
| 21216 |
// Handle <1 x ???> vector insertion special cases. |
--- |
21216 |
// Handle <1 x ???> vector insertion special cases. |
--- |
| 21217 |
if (NumElts == 1) { |
0 |
21217 |
if (NumElts == 1) { |
0 |
| 21218 |
// insert_vector_elt(x, extract_vector_elt(y, 0), 0) -> y |
--- |
21218 |
// insert_vector_elt(x, extract_vector_elt(y, 0), 0) -> y |
--- |
| 21219 |
if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
0 |
21219 |
if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
0 |
| 21220 |
InVal.getOperand(0).getValueType() == VT && |
0 |
21220 |
InVal.getOperand(0).getValueType() == VT && |
0 |
| 21221 |
isNullConstant(InVal.getOperand(1))) |
0 |
21221 |
isNullConstant(InVal.getOperand(1))) |
0 |
| 21222 |
return InVal.getOperand(0); |
0 |
21222 |
return InVal.getOperand(0); |
0 |
| 21223 |
} |
--- |
21223 |
} |
--- |
| 21224 |
|
--- |
21224 |
|
--- |
| 21225 |
// Canonicalize insert_vector_elt dag nodes. |
--- |
21225 |
// Canonicalize insert_vector_elt dag nodes. |
--- |
| 21226 |
// Example: |
--- |
21226 |
// Example: |
--- |
| 21227 |
// (insert_vector_elt (insert_vector_elt A, Idx0), Idx1) |
--- |
21227 |
// (insert_vector_elt (insert_vector_elt A, Idx0), Idx1) |
--- |
| 21228 |
// -> (insert_vector_elt (insert_vector_elt A, Idx1), Idx0) |
--- |
21228 |
// -> (insert_vector_elt (insert_vector_elt A, Idx1), Idx0) |
--- |
| 21229 |
// |
--- |
21229 |
// |
--- |
| 21230 |
// Do this only if the child insert_vector node has one use; also |
--- |
21230 |
// Do this only if the child insert_vector node has one use; also |
--- |
| 21231 |
// do this only if indices are both constants and Idx1 < Idx0. |
--- |
21231 |
// do this only if indices are both constants and Idx1 < Idx0. |
--- |
| 21232 |
if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() |
0 |
21232 |
if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() |
0 |
| 21233 |
&& isa(InVec.getOperand(2))) { |
0 |
21233 |
&& isa(InVec.getOperand(2))) { |
0 |
| 21234 |
unsigned OtherElt = InVec.getConstantOperandVal(2); |
0 |
21234 |
unsigned OtherElt = InVec.getConstantOperandVal(2); |
0 |
| 21235 |
if (Elt < OtherElt) { |
0 |
21235 |
if (Elt < OtherElt) { |
0 |
| 21236 |
// Swap nodes. |
--- |
21236 |
// Swap nodes. |
--- |
| 21237 |
SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, |
0 |
21237 |
SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, |
0 |
| 21238 |
InVec.getOperand(0), InVal, EltNo); |
0 |
21238 |
InVec.getOperand(0), InVal, EltNo); |
0 |
| 21239 |
AddToWorklist(NewOp.getNode()); |
0 |
21239 |
AddToWorklist(NewOp.getNode()); |
0 |
| 21240 |
return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()), |
0 |
21240 |
return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()), |
0 |
| 21241 |
VT, NewOp, InVec.getOperand(1), InVec.getOperand(2)); |
0 |
21241 |
VT, NewOp, InVec.getOperand(1), InVec.getOperand(2)); |
0 |
| 21242 |
} |
--- |
21242 |
} |
--- |
| 21243 |
} |
--- |
21243 |
} |
--- |
| 21244 |
|
--- |
21244 |
|
--- |
| 21245 |
if (SDValue Shuf = mergeInsertEltWithShuffle(N, Elt)) |
0 |
21245 |
if (SDValue Shuf = mergeInsertEltWithShuffle(N, Elt)) |
0 |
| 21246 |
return Shuf; |
0 |
21246 |
return Shuf; |
0 |
| 21247 |
|
--- |
21247 |
|
--- |
| 21248 |
if (SDValue Shuf = combineInsertEltToShuffle(N, Elt)) |
0 |
21248 |
if (SDValue Shuf = combineInsertEltToShuffle(N, Elt)) |
0 |
| 21249 |
return Shuf; |
0 |
21249 |
return Shuf; |
0 |
| 21250 |
|
--- |
21250 |
|
--- |
| 21251 |
if (SDValue Shuf = combineInsertEltToLoad(N, Elt)) |
0 |
21251 |
if (SDValue Shuf = combineInsertEltToLoad(N, Elt)) |
0 |
| 21252 |
return Shuf; |
0 |
21252 |
return Shuf; |
0 |
| 21253 |
|
--- |
21253 |
|
--- |
| 21254 |
// Attempt to convert an insert_vector_elt chain into a legal build_vector. |
--- |
21254 |
// Attempt to convert an insert_vector_elt chain into a legal build_vector. |
--- |
| 21255 |
if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { |
0 |
21255 |
if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { |
0 |
| 21256 |
// vXi1 vector - we don't need to recurse. |
--- |
21256 |
// vXi1 vector - we don't need to recurse. |
--- |
| 21257 |
if (NumElts == 1) |
0 |
21257 |
if (NumElts == 1) |
0 |
| 21258 |
return DAG.getBuildVector(VT, DL, {InVal}); |
0 |
21258 |
return DAG.getBuildVector(VT, DL, {InVal}); |
0 |
| 21259 |
|
--- |
21259 |
|
--- |
| 21260 |
// If we haven't already collected the element, insert into the op list. |
--- |
21260 |
// If we haven't already collected the element, insert into the op list. |
--- |
| 21261 |
EVT MaxEltVT = InVal.getValueType(); |
0 |
21261 |
EVT MaxEltVT = InVal.getValueType(); |
0 |
| 21262 |
auto AddBuildVectorOp = [&](SmallVectorImpl &Ops, SDValue Elt, |
0 |
21262 |
auto AddBuildVectorOp = [&](SmallVectorImpl &Ops, SDValue Elt, |
0 |
| 21263 |
unsigned Idx) { |
--- |
21263 |
unsigned Idx) { |
--- |
| 21264 |
if (!Ops[Idx]) { |
0 |
21264 |
if (!Ops[Idx]) { |
0 |
| 21265 |
Ops[Idx] = Elt; |
0 |
21265 |
Ops[Idx] = Elt; |
0 |
| 21266 |
if (VT.isInteger()) { |
0 |
21266 |
if (VT.isInteger()) { |
0 |
| 21267 |
EVT EltVT = Elt.getValueType(); |
0 |
21267 |
EVT EltVT = Elt.getValueType(); |
0 |
| 21268 |
MaxEltVT = MaxEltVT.bitsGE(EltVT) ? MaxEltVT : EltVT; |
0 |
21268 |
MaxEltVT = MaxEltVT.bitsGE(EltVT) ? MaxEltVT : EltVT; |
0 |
| 21269 |
} |
--- |
21269 |
} |
--- |
| 21270 |
} |
--- |
21270 |
} |
--- |
| 21271 |
}; |
0 |
21271 |
}; |
0 |
| 21272 |
|
--- |
21272 |
|
--- |
| 21273 |
// Ensure all the operands are the same value type, fill any missing |
--- |
21273 |
// Ensure all the operands are the same value type, fill any missing |
--- |
| 21274 |
// operands with UNDEF and create the BUILD_VECTOR. |
--- |
21274 |
// operands with UNDEF and create the BUILD_VECTOR. |
--- |
| 21275 |
auto CanonicalizeBuildVector = [&](SmallVectorImpl &Ops) { |
0 |
21275 |
auto CanonicalizeBuildVector = [&](SmallVectorImpl &Ops) { |
0 |
| 21276 |
assert(Ops.size() == NumElts && "Unexpected vector size"); |
0 |
21276 |
assert(Ops.size() == NumElts && "Unexpected vector size"); |
0 |
| 21277 |
for (SDValue &Op : Ops) { |
0 |
21277 |
for (SDValue &Op : Ops) { |
0 |
| 21278 |
if (Op) |
0 |
21278 |
if (Op) |
0 |
| 21279 |
Op = VT.isInteger() ? DAG.getAnyExtOrTrunc(Op, DL, MaxEltVT) : Op; |
0 |
21279 |
Op = VT.isInteger() ? DAG.getAnyExtOrTrunc(Op, DL, MaxEltVT) : Op; |
0 |
| 21280 |
else |
--- |
21280 |
else |
--- |
| 21281 |
Op = DAG.getUNDEF(MaxEltVT); |
0 |
21281 |
Op = DAG.getUNDEF(MaxEltVT); |
0 |
| 21282 |
} |
--- |
21282 |
} |
--- |
| 21283 |
return DAG.getBuildVector(VT, DL, Ops); |
0 |
21283 |
return DAG.getBuildVector(VT, DL, Ops); |
0 |
| 21284 |
}; |
0 |
21284 |
}; |
0 |
| 21285 |
|
--- |
21285 |
|
--- |
| 21286 |
SmallVector Ops(NumElts, SDValue()); |
0 |
21286 |
SmallVector Ops(NumElts, SDValue()); |
0 |
| 21287 |
Ops[Elt] = InVal; |
0 |
21287 |
Ops[Elt] = InVal; |
0 |
| 21288 |
|
--- |
21288 |
|
--- |
| 21289 |
// Recurse up a INSERT_VECTOR_ELT chain to build a BUILD_VECTOR. |
--- |
21289 |
// Recurse up a INSERT_VECTOR_ELT chain to build a BUILD_VECTOR. |
--- |
| 21290 |
for (SDValue CurVec = InVec; CurVec;) { |
0 |
21290 |
for (SDValue CurVec = InVec; CurVec;) { |
0 |
| 21291 |
// UNDEF - build new BUILD_VECTOR from already inserted operands. |
--- |
21291 |
// UNDEF - build new BUILD_VECTOR from already inserted operands. |
--- |
| 21292 |
if (CurVec.isUndef()) |
0 |
21292 |
if (CurVec.isUndef()) |
0 |
| 21293 |
return CanonicalizeBuildVector(Ops); |
0 |
21293 |
return CanonicalizeBuildVector(Ops); |
0 |
| 21294 |
|
--- |
21294 |
|
--- |
| 21295 |
// BUILD_VECTOR - insert unused operands and build new BUILD_VECTOR. |
--- |
21295 |
// BUILD_VECTOR - insert unused operands and build new BUILD_VECTOR. |
--- |
| 21296 |
if (CurVec.getOpcode() == ISD::BUILD_VECTOR && CurVec.hasOneUse()) { |
0 |
21296 |
if (CurVec.getOpcode() == ISD::BUILD_VECTOR && CurVec.hasOneUse()) { |
0 |
| 21297 |
for (unsigned I = 0; I != NumElts; ++I) |
0 |
21297 |
for (unsigned I = 0; I != NumElts; ++I) |
0 |
| 21298 |
AddBuildVectorOp(Ops, CurVec.getOperand(I), I); |
0 |
21298 |
AddBuildVectorOp(Ops, CurVec.getOperand(I), I); |
0 |
| 21299 |
return CanonicalizeBuildVector(Ops); |
0 |
21299 |
return CanonicalizeBuildVector(Ops); |
0 |
| 21300 |
} |
--- |
21300 |
} |
--- |
| 21301 |
|
--- |
21301 |
|
--- |
| 21302 |
// SCALAR_TO_VECTOR - insert unused scalar and build new BUILD_VECTOR. |
--- |
21302 |
// SCALAR_TO_VECTOR - insert unused scalar and build new BUILD_VECTOR. |
--- |
| 21303 |
if (CurVec.getOpcode() == ISD::SCALAR_TO_VECTOR && CurVec.hasOneUse()) { |
0 |
21303 |
if (CurVec.getOpcode() == ISD::SCALAR_TO_VECTOR && CurVec.hasOneUse()) { |
0 |
| 21304 |
AddBuildVectorOp(Ops, CurVec.getOperand(0), 0); |
0 |
21304 |
AddBuildVectorOp(Ops, CurVec.getOperand(0), 0); |
0 |
| 21305 |
return CanonicalizeBuildVector(Ops); |
0 |
21305 |
return CanonicalizeBuildVector(Ops); |
0 |
| 21306 |
} |
--- |
21306 |
} |
--- |
| 21307 |
|
--- |
21307 |
|
--- |
| 21308 |
// INSERT_VECTOR_ELT - insert operand and continue up the chain. |
--- |
21308 |
// INSERT_VECTOR_ELT - insert operand and continue up the chain. |
--- |
| 21309 |
if (CurVec.getOpcode() == ISD::INSERT_VECTOR_ELT && CurVec.hasOneUse()) |
0 |
21309 |
if (CurVec.getOpcode() == ISD::INSERT_VECTOR_ELT && CurVec.hasOneUse()) |
0 |
| 21310 |
if (auto *CurIdx = dyn_cast(CurVec.getOperand(2))) |
0 |
21310 |
if (auto *CurIdx = dyn_cast(CurVec.getOperand(2))) |
0 |
| 21311 |
if (CurIdx->getAPIntValue().ult(NumElts)) { |
0 |
21311 |
if (CurIdx->getAPIntValue().ult(NumElts)) { |
0 |
| 21312 |
unsigned Idx = CurIdx->getZExtValue(); |
0 |
21312 |
unsigned Idx = CurIdx->getZExtValue(); |
0 |
| 21313 |
AddBuildVectorOp(Ops, CurVec.getOperand(1), Idx); |
0 |
21313 |
AddBuildVectorOp(Ops, CurVec.getOperand(1), Idx); |
0 |
| 21314 |
|
--- |
21314 |
|
--- |
| 21315 |
// Found entire BUILD_VECTOR. |
--- |
21315 |
// Found entire BUILD_VECTOR. |
--- |
| 21316 |
if (all_of(Ops, [](SDValue Op) { return !!Op; })) |
0 |
21316 |
if (all_of(Ops, [](SDValue Op) { return !!Op; })) |
0 |
| 21317 |
return CanonicalizeBuildVector(Ops); |
0 |
21317 |
return CanonicalizeBuildVector(Ops); |
0 |
| 21318 |
|
--- |
21318 |
|
--- |
| 21319 |
CurVec = CurVec->getOperand(0); |
0 |
21319 |
CurVec = CurVec->getOperand(0); |
0 |
| 21320 |
continue; |
0 |
21320 |
continue; |
0 |
| 21321 |
} |
0 |
21321 |
} |
0 |
| 21322 |
|
--- |
21322 |
|
--- |
| 21323 |
// VECTOR_SHUFFLE - if all the operands match the shuffle's sources, |
--- |
21323 |
// VECTOR_SHUFFLE - if all the operands match the shuffle's sources, |
--- |
| 21324 |
// update the shuffle mask (and second operand if we started with unary |
--- |
21324 |
// update the shuffle mask (and second operand if we started with unary |
--- |
| 21325 |
// shuffle) and create a new legal shuffle. |
--- |
21325 |
// shuffle) and create a new legal shuffle. |
--- |
| 21326 |
if (CurVec.getOpcode() == ISD::VECTOR_SHUFFLE && CurVec.hasOneUse()) { |
0 |
21326 |
if (CurVec.getOpcode() == ISD::VECTOR_SHUFFLE && CurVec.hasOneUse()) { |
0 |
| 21327 |
auto *SVN = cast(CurVec); |
0 |
21327 |
auto *SVN = cast(CurVec); |
0 |
| 21328 |
SDValue LHS = SVN->getOperand(0); |
0 |
21328 |
SDValue LHS = SVN->getOperand(0); |
0 |
| 21329 |
SDValue RHS = SVN->getOperand(1); |
0 |
21329 |
SDValue RHS = SVN->getOperand(1); |
0 |
| 21330 |
SmallVector Mask(SVN->getMask()); |
0 |
21330 |
SmallVector Mask(SVN->getMask()); |
0 |
| 21331 |
bool Merged = true; |
0 |
21331 |
bool Merged = true; |
0 |
| 21332 |
for (auto I : enumerate(Ops)) { |
0 |
21332 |
for (auto I : enumerate(Ops)) { |
0 |
| 21333 |
SDValue &Op = I.value(); |
0 |
21333 |
SDValue &Op = I.value(); |
0 |
| 21334 |
if (Op) { |
0 |
21334 |
if (Op) { |
0 |
| 21335 |
SmallVector NewMask; |
0 |
21335 |
SmallVector NewMask; |
0 |
| 21336 |
if (!mergeEltWithShuffle(LHS, RHS, Mask, NewMask, Op, I.index())) { |
0 |
21336 |
if (!mergeEltWithShuffle(LHS, RHS, Mask, NewMask, Op, I.index())) { |
0 |
| 21337 |
Merged = false; |
0 |
21337 |
Merged = false; |
0 |
| 21338 |
break; |
0 |
21338 |
break; |
0 |
| 21339 |
} |
--- |
21339 |
} |
--- |
| 21340 |
Mask = std::move(NewMask); |
0 |
21340 |
Mask = std::move(NewMask); |
0 |
| 21341 |
} |
0 |
21341 |
} |
0 |
| 21342 |
} |
--- |
21342 |
} |
--- |
| 21343 |
if (Merged) |
0 |
21343 |
if (Merged) |
0 |
| 21344 |
if (SDValue NewShuffle = |
0 |
21344 |
if (SDValue NewShuffle = |
0 |
| 21345 |
TLI.buildLegalVectorShuffle(VT, DL, LHS, RHS, Mask, DAG)) |
0 |
21345 |
TLI.buildLegalVectorShuffle(VT, DL, LHS, RHS, Mask, DAG)) |
0 |
| 21346 |
return NewShuffle; |
0 |
21346 |
return NewShuffle; |
0 |
| 21347 |
} |
0 |
21347 |
} |
0 |
| 21348 |
|
--- |
21348 |
|
--- |
| 21349 |
// If all insertions are zero value, try to convert to AND mask. |
--- |
21349 |
// If all insertions are zero value, try to convert to AND mask. |
--- |
| 21350 |
// TODO: Do this for -1 with OR mask? |
--- |
21350 |
// TODO: Do this for -1 with OR mask? |
--- |
| 21351 |
if (!LegalOperations && llvm::isNullConstant(InVal) && |
0 |
21351 |
if (!LegalOperations && llvm::isNullConstant(InVal) && |
0 |
| 21352 |
all_of(Ops, [InVal](SDValue Op) { return !Op || Op == InVal; }) && |
0 |
21352 |
all_of(Ops, [InVal](SDValue Op) { return !Op || Op == InVal; }) && |
0 |
| 21353 |
count_if(Ops, [InVal](SDValue Op) { return Op == InVal; }) >= 2) { |
0 |
21353 |
count_if(Ops, [InVal](SDValue Op) { return Op == InVal; }) >= 2) { |
0 |
| 21354 |
SDValue Zero = DAG.getConstant(0, DL, MaxEltVT); |
0 |
21354 |
SDValue Zero = DAG.getConstant(0, DL, MaxEltVT); |
0 |
| 21355 |
SDValue AllOnes = DAG.getAllOnesConstant(DL, MaxEltVT); |
0 |
21355 |
SDValue AllOnes = DAG.getAllOnesConstant(DL, MaxEltVT); |
0 |
| 21356 |
SmallVector Mask(NumElts); |
0 |
21356 |
SmallVector Mask(NumElts); |
0 |
| 21357 |
for (unsigned I = 0; I != NumElts; ++I) |
0 |
21357 |
for (unsigned I = 0; I != NumElts; ++I) |
0 |
| 21358 |
Mask[I] = Ops[I] ? Zero : AllOnes; |
0 |
21358 |
Mask[I] = Ops[I] ? Zero : AllOnes; |
0 |
| 21359 |
return DAG.getNode(ISD::AND, DL, VT, CurVec, |
0 |
21359 |
return DAG.getNode(ISD::AND, DL, VT, CurVec, |
0 |
| 21360 |
DAG.getBuildVector(VT, DL, Mask)); |
0 |
21360 |
DAG.getBuildVector(VT, DL, Mask)); |
0 |
| 21361 |
} |
0 |
21361 |
} |
0 |
| 21362 |
|
--- |
21362 |
|
--- |
| 21363 |
// Failed to find a match in the chain - bail. |
--- |
21363 |
// Failed to find a match in the chain - bail. |
--- |
| 21364 |
break; |
0 |
21364 |
break; |
0 |
| 21365 |
} |
--- |
21365 |
} |
--- |
| 21366 |
|
--- |
21366 |
|
--- |
| 21367 |
// See if we can fill in the missing constant elements as zeros. |
--- |
21367 |
// See if we can fill in the missing constant elements as zeros. |
--- |
| 21368 |
// TODO: Should we do this for any constant? |
--- |
21368 |
// TODO: Should we do this for any constant? |
--- |
| 21369 |
APInt DemandedZeroElts = APInt::getZero(NumElts); |
0 |
21369 |
APInt DemandedZeroElts = APInt::getZero(NumElts); |
0 |
| 21370 |
for (unsigned I = 0; I != NumElts; ++I) |
0 |
21370 |
for (unsigned I = 0; I != NumElts; ++I) |
0 |
| 21371 |
if (!Ops[I]) |
0 |
21371 |
if (!Ops[I]) |
0 |
| 21372 |
DemandedZeroElts.setBit(I); |
0 |
21372 |
DemandedZeroElts.setBit(I); |
0 |
| 21373 |
|
--- |
21373 |
|
--- |
| 21374 |
if (DAG.MaskedVectorIsZero(InVec, DemandedZeroElts)) { |
0 |
21374 |
if (DAG.MaskedVectorIsZero(InVec, DemandedZeroElts)) { |
0 |
| 21375 |
SDValue Zero = VT.isInteger() ? DAG.getConstant(0, DL, MaxEltVT) |
0 |
21375 |
SDValue Zero = VT.isInteger() ? DAG.getConstant(0, DL, MaxEltVT) |
0 |
| 21376 |
: DAG.getConstantFP(0, DL, MaxEltVT); |
0 |
21376 |
: DAG.getConstantFP(0, DL, MaxEltVT); |
0 |
| 21377 |
for (unsigned I = 0; I != NumElts; ++I) |
0 |
21377 |
for (unsigned I = 0; I != NumElts; ++I) |
0 |
| 21378 |
if (!Ops[I]) |
0 |
21378 |
if (!Ops[I]) |
0 |
| 21379 |
Ops[I] = Zero; |
0 |
21379 |
Ops[I] = Zero; |
0 |
| 21380 |
|
--- |
21380 |
|
--- |
| 21381 |
return CanonicalizeBuildVector(Ops); |
0 |
21381 |
return CanonicalizeBuildVector(Ops); |
0 |
| 21382 |
} |
--- |
21382 |
} |
--- |
| 21383 |
} |
0 |
21383 |
} |
0 |
| 21384 |
|
--- |
21384 |
|
--- |
| 21385 |
return SDValue(); |
0 |
21385 |
return SDValue(); |
0 |
| 21386 |
} |
0 |
21386 |
} |
0 |
| 21387 |
|
--- |
21387 |
|
--- |
| 21388 |
SDValue DAGCombiner::scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT, |
0 |
21388 |
SDValue DAGCombiner::scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT, |
0 |
| 21389 |
SDValue EltNo, |
--- |
21389 |
SDValue EltNo, |
--- |
| 21390 |
LoadSDNode *OriginalLoad) { |
--- |
21390 |
LoadSDNode *OriginalLoad) { |
--- |
| 21391 |
assert(OriginalLoad->isSimple()); |
0 |
21391 |
assert(OriginalLoad->isSimple()); |
0 |
| 21392 |
|
--- |
21392 |
|
--- |
| 21393 |
EVT ResultVT = EVE->getValueType(0); |
0 |
21393 |
EVT ResultVT = EVE->getValueType(0); |
0 |
| 21394 |
EVT VecEltVT = InVecVT.getVectorElementType(); |
0 |
21394 |
EVT VecEltVT = InVecVT.getVectorElementType(); |
0 |
| 21395 |
|
--- |
21395 |
|
--- |
| 21396 |
// If the vector element type is not a multiple of a byte then we are unable |
--- |
21396 |
// If the vector element type is not a multiple of a byte then we are unable |
--- |
| 21397 |
// to correctly compute an address to load only the extracted element as a |
--- |
21397 |
// to correctly compute an address to load only the extracted element as a |
--- |
| 21398 |
// scalar. |
--- |
21398 |
// scalar. |
--- |
| 21399 |
if (!VecEltVT.isByteSized()) |
0 |
21399 |
if (!VecEltVT.isByteSized()) |
0 |
| 21400 |
return SDValue(); |
0 |
21400 |
return SDValue(); |
0 |
| 21401 |
|
--- |
21401 |
|
--- |
| 21402 |
ISD::LoadExtType ExtTy = |
--- |
21402 |
ISD::LoadExtType ExtTy = |
--- |
| 21403 |
ResultVT.bitsGT(VecEltVT) ? ISD::NON_EXTLOAD : ISD::EXTLOAD; |
0 |
21403 |
ResultVT.bitsGT(VecEltVT) ? ISD::NON_EXTLOAD : ISD::EXTLOAD; |
0 |
| 21404 |
if (!TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT) || |
0 |
21404 |
if (!TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT) || |
0 |
| 21405 |
!TLI.shouldReduceLoadWidth(OriginalLoad, ExtTy, VecEltVT)) |
0 |
21405 |
!TLI.shouldReduceLoadWidth(OriginalLoad, ExtTy, VecEltVT)) |
0 |
| 21406 |
return SDValue(); |
0 |
21406 |
return SDValue(); |
0 |
| 21407 |
|
--- |
21407 |
|
--- |
| 21408 |
Align Alignment = OriginalLoad->getAlign(); |
0 |
21408 |
Align Alignment = OriginalLoad->getAlign(); |
0 |
| 21409 |
MachinePointerInfo MPI; |
0 |
21409 |
MachinePointerInfo MPI; |
0 |
| 21410 |
SDLoc DL(EVE); |
0 |
21410 |
SDLoc DL(EVE); |
0 |
| 21411 |
if (auto *ConstEltNo = dyn_cast(EltNo)) { |
0 |
21411 |
if (auto *ConstEltNo = dyn_cast(EltNo)) { |
0 |
| 21412 |
int Elt = ConstEltNo->getZExtValue(); |
0 |
21412 |
int Elt = ConstEltNo->getZExtValue(); |
0 |
| 21413 |
unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8; |
0 |
21413 |
unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8; |
0 |
| 21414 |
MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff); |
0 |
21414 |
MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff); |
0 |
| 21415 |
Alignment = commonAlignment(Alignment, PtrOff); |
0 |
21415 |
Alignment = commonAlignment(Alignment, PtrOff); |
0 |
| 21416 |
} else { |
--- |
21416 |
} else { |
--- |
| 21417 |
// Discard the pointer info except the address space because the memory |
--- |
21417 |
// Discard the pointer info except the address space because the memory |
--- |
| 21418 |
// operand can't represent this new access since the offset is variable. |
--- |
21418 |
// operand can't represent this new access since the offset is variable. |
--- |
| 21419 |
MPI = MachinePointerInfo(OriginalLoad->getPointerInfo().getAddrSpace()); |
0 |
21419 |
MPI = MachinePointerInfo(OriginalLoad->getPointerInfo().getAddrSpace()); |
0 |
| 21420 |
Alignment = commonAlignment(Alignment, VecEltVT.getSizeInBits() / 8); |
0 |
21420 |
Alignment = commonAlignment(Alignment, VecEltVT.getSizeInBits() / 8); |
0 |
| 21421 |
} |
--- |
21421 |
} |
--- |
| 21422 |
|
--- |
21422 |
|
--- |
| 21423 |
unsigned IsFast = 0; |
0 |
21423 |
unsigned IsFast = 0; |
0 |
| 21424 |
if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VecEltVT, |
0 |
21424 |
if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VecEltVT, |
0 |
| 21425 |
OriginalLoad->getAddressSpace(), Alignment, |
--- |
21425 |
OriginalLoad->getAddressSpace(), Alignment, |
--- |
| 21426 |
OriginalLoad->getMemOperand()->getFlags(), |
0 |
21426 |
OriginalLoad->getMemOperand()->getFlags(), |
0 |
| 21427 |
&IsFast) || |
0 |
21427 |
&IsFast) || |
0 |
| 21428 |
!IsFast) |
0 |
21428 |
!IsFast) |
0 |
| 21429 |
return SDValue(); |
0 |
21429 |
return SDValue(); |
0 |
| 21430 |
|
--- |
21430 |
|
--- |
| 21431 |
SDValue NewPtr = TLI.getVectorElementPointer(DAG, OriginalLoad->getBasePtr(), |
0 |
21431 |
SDValue NewPtr = TLI.getVectorElementPointer(DAG, OriginalLoad->getBasePtr(), |
0 |
| 21432 |
InVecVT, EltNo); |
--- |
21432 |
InVecVT, EltNo); |
--- |
| 21433 |
|
--- |
21433 |
|
--- |
| 21434 |
// We are replacing a vector load with a scalar load. The new load must have |
--- |
21434 |
// We are replacing a vector load with a scalar load. The new load must have |
--- |
| 21435 |
// identical memory op ordering to the original. |
--- |
21435 |
// identical memory op ordering to the original. |
--- |
| 21436 |
SDValue Load; |
0 |
21436 |
SDValue Load; |
0 |
| 21437 |
if (ResultVT.bitsGT(VecEltVT)) { |
0 |
21437 |
if (ResultVT.bitsGT(VecEltVT)) { |
0 |
| 21438 |
// If the result type of vextract is wider than the load, then issue an |
--- |
21438 |
// If the result type of vextract is wider than the load, then issue an |
--- |
| 21439 |
// extending load instead. |
--- |
21439 |
// extending load instead. |
--- |
| 21440 |
ISD::LoadExtType ExtType = |
--- |
21440 |
ISD::LoadExtType ExtType = |
--- |
| 21441 |
TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT, VecEltVT) ? ISD::ZEXTLOAD |
0 |
21441 |
TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT, VecEltVT) ? ISD::ZEXTLOAD |
0 |
| 21442 |
: ISD::EXTLOAD; |
0 |
21442 |
: ISD::EXTLOAD; |
0 |
| 21443 |
Load = DAG.getExtLoad(ExtType, DL, ResultVT, OriginalLoad->getChain(), |
0 |
21443 |
Load = DAG.getExtLoad(ExtType, DL, ResultVT, OriginalLoad->getChain(), |
0 |
| 21444 |
NewPtr, MPI, VecEltVT, Alignment, |
--- |
21444 |
NewPtr, MPI, VecEltVT, Alignment, |
--- |
| 21445 |
OriginalLoad->getMemOperand()->getFlags(), |
0 |
21445 |
OriginalLoad->getMemOperand()->getFlags(), |
0 |
| 21446 |
OriginalLoad->getAAInfo()); |
0 |
21446 |
OriginalLoad->getAAInfo()); |
0 |
| 21447 |
DAG.makeEquivalentMemoryOrdering(OriginalLoad, Load); |
0 |
21447 |
DAG.makeEquivalentMemoryOrdering(OriginalLoad, Load); |
0 |
| 21448 |
} else { |
--- |
21448 |
} else { |
--- |
| 21449 |
// The result type is narrower or the same width as the vector element |
--- |
21449 |
// The result type is narrower or the same width as the vector element |
--- |
| 21450 |
Load = DAG.getLoad(VecEltVT, DL, OriginalLoad->getChain(), NewPtr, MPI, |
0 |
21450 |
Load = DAG.getLoad(VecEltVT, DL, OriginalLoad->getChain(), NewPtr, MPI, |
0 |
| 21451 |
Alignment, OriginalLoad->getMemOperand()->getFlags(), |
0 |
21451 |
Alignment, OriginalLoad->getMemOperand()->getFlags(), |
0 |
| 21452 |
OriginalLoad->getAAInfo()); |
0 |
21452 |
OriginalLoad->getAAInfo()); |
0 |
| 21453 |
DAG.makeEquivalentMemoryOrdering(OriginalLoad, Load); |
0 |
21453 |
DAG.makeEquivalentMemoryOrdering(OriginalLoad, Load); |
0 |
| 21454 |
if (ResultVT.bitsLT(VecEltVT)) |
0 |
21454 |
if (ResultVT.bitsLT(VecEltVT)) |
0 |
| 21455 |
Load = DAG.getNode(ISD::TRUNCATE, DL, ResultVT, Load); |
0 |
21455 |
Load = DAG.getNode(ISD::TRUNCATE, DL, ResultVT, Load); |
0 |
| 21456 |
else |
--- |
21456 |
else |
--- |
| 21457 |
Load = DAG.getBitcast(ResultVT, Load); |
0 |
21457 |
Load = DAG.getBitcast(ResultVT, Load); |
0 |
| 21458 |
} |
--- |
21458 |
} |
--- |
| 21459 |
++OpsNarrowed; |
0 |
21459 |
++OpsNarrowed; |
0 |
| 21460 |
return Load; |
0 |
21460 |
return Load; |
0 |
| 21461 |
} |
0 |
21461 |
} |
0 |
| 21462 |
|
--- |
21462 |
|
--- |
| 21463 |
/// Transform a vector binary operation into a scalar binary operation by moving |
--- |
21463 |
/// Transform a vector binary operation into a scalar binary operation by moving |
--- |
| 21464 |
/// the math/logic after an extract element of a vector. |
--- |
21464 |
/// the math/logic after an extract element of a vector. |
--- |
| 21465 |
static SDValue scalarizeExtractedBinop(SDNode *ExtElt, SelectionDAG &DAG, |
0 |
21465 |
static SDValue scalarizeExtractedBinop(SDNode *ExtElt, SelectionDAG &DAG, |
0 |
| 21466 |
bool LegalOperations) { |
--- |
21466 |
bool LegalOperations) { |
--- |
| 21467 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
21467 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 21468 |
SDValue Vec = ExtElt->getOperand(0); |
0 |
21468 |
SDValue Vec = ExtElt->getOperand(0); |
0 |
| 21469 |
SDValue Index = ExtElt->getOperand(1); |
0 |
21469 |
SDValue Index = ExtElt->getOperand(1); |
0 |
| 21470 |
auto *IndexC = dyn_cast(Index); |
0 |
21470 |
auto *IndexC = dyn_cast(Index); |
0 |
| 21471 |
if (!IndexC || !TLI.isBinOp(Vec.getOpcode()) || !Vec.hasOneUse() || |
0 |
21471 |
if (!IndexC || !TLI.isBinOp(Vec.getOpcode()) || !Vec.hasOneUse() || |
0 |
| 21472 |
Vec->getNumValues() != 1) |
0 |
21472 |
Vec->getNumValues() != 1) |
0 |
| 21473 |
return SDValue(); |
0 |
21473 |
return SDValue(); |
0 |
| 21474 |
|
--- |
21474 |
|
--- |
| 21475 |
// Targets may want to avoid this to prevent an expensive register transfer. |
--- |
21475 |
// Targets may want to avoid this to prevent an expensive register transfer. |
--- |
| 21476 |
if (!TLI.shouldScalarizeBinop(Vec)) |
0 |
21476 |
if (!TLI.shouldScalarizeBinop(Vec)) |
0 |
| 21477 |
return SDValue(); |
0 |
21477 |
return SDValue(); |
0 |
| 21478 |
|
--- |
21478 |
|
--- |
| 21479 |
// Extracting an element of a vector constant is constant-folded, so this |
--- |
21479 |
// Extracting an element of a vector constant is constant-folded, so this |
--- |
| 21480 |
// transform is just replacing a vector op with a scalar op while moving the |
--- |
21480 |
// transform is just replacing a vector op with a scalar op while moving the |
--- |
| 21481 |
// extract. |
--- |
21481 |
// extract. |
--- |
| 21482 |
SDValue Op0 = Vec.getOperand(0); |
0 |
21482 |
SDValue Op0 = Vec.getOperand(0); |
0 |
| 21483 |
SDValue Op1 = Vec.getOperand(1); |
0 |
21483 |
SDValue Op1 = Vec.getOperand(1); |
0 |
| 21484 |
APInt SplatVal; |
0 |
21484 |
APInt SplatVal; |
0 |
| 21485 |
if (isAnyConstantBuildVector(Op0, true) || |
0 |
21485 |
if (isAnyConstantBuildVector(Op0, true) || |
0 |
| 21486 |
ISD::isConstantSplatVector(Op0.getNode(), SplatVal) || |
0 |
21486 |
ISD::isConstantSplatVector(Op0.getNode(), SplatVal) || |
0 |
| 21487 |
isAnyConstantBuildVector(Op1, true) || |
0 |
21487 |
isAnyConstantBuildVector(Op1, true) || |
0 |
| 21488 |
ISD::isConstantSplatVector(Op1.getNode(), SplatVal)) { |
0 |
21488 |
ISD::isConstantSplatVector(Op1.getNode(), SplatVal)) { |
0 |
| 21489 |
// extractelt (binop X, C), IndexC --> binop (extractelt X, IndexC), C' |
--- |
21489 |
// extractelt (binop X, C), IndexC --> binop (extractelt X, IndexC), C' |
--- |
| 21490 |
// extractelt (binop C, X), IndexC --> binop C', (extractelt X, IndexC) |
--- |
21490 |
// extractelt (binop C, X), IndexC --> binop C', (extractelt X, IndexC) |
--- |
| 21491 |
SDLoc DL(ExtElt); |
0 |
21491 |
SDLoc DL(ExtElt); |
0 |
| 21492 |
EVT VT = ExtElt->getValueType(0); |
0 |
21492 |
EVT VT = ExtElt->getValueType(0); |
0 |
| 21493 |
SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op0, Index); |
0 |
21493 |
SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op0, Index); |
0 |
| 21494 |
SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op1, Index); |
0 |
21494 |
SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op1, Index); |
0 |
| 21495 |
return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); |
0 |
21495 |
return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); |
0 |
| 21496 |
} |
0 |
21496 |
} |
0 |
| 21497 |
|
--- |
21497 |
|
--- |
| 21498 |
return SDValue(); |
0 |
21498 |
return SDValue(); |
0 |
| 21499 |
} |
0 |
21499 |
} |
0 |
| 21500 |
|
--- |
21500 |
|
--- |
| 21501 |
// Given a ISD::EXTRACT_VECTOR_ELT, which is a glorified bit sequence extract, |
--- |
21501 |
// Given a ISD::EXTRACT_VECTOR_ELT, which is a glorified bit sequence extract, |
--- |
| 21502 |
// recursively analyse all of it's users. and try to model themselves as |
--- |
21502 |
// recursively analyse all of it's users. and try to model themselves as |
--- |
| 21503 |
// bit sequence extractions. If all of them agree on the new, narrower element |
--- |
21503 |
// bit sequence extractions. If all of them agree on the new, narrower element |
--- |
| 21504 |
// type, and all of them can be modelled as ISD::EXTRACT_VECTOR_ELT's of that |
--- |
21504 |
// type, and all of them can be modelled as ISD::EXTRACT_VECTOR_ELT's of that |
--- |
| 21505 |
// new element type, do so now. |
--- |
21505 |
// new element type, do so now. |
--- |
| 21506 |
// This is mainly useful to recover from legalization that scalarized |
--- |
21506 |
// This is mainly useful to recover from legalization that scalarized |
--- |
| 21507 |
// the vector as wide elements, but tries to rebuild it with narrower elements. |
--- |
21507 |
// the vector as wide elements, but tries to rebuild it with narrower elements. |
--- |
| 21508 |
// |
--- |
21508 |
// |
--- |
| 21509 |
// Some more nodes could be modelled if that helps cover interesting patterns. |
--- |
21509 |
// Some more nodes could be modelled if that helps cover interesting patterns. |
--- |
| 21510 |
bool DAGCombiner::refineExtractVectorEltIntoMultipleNarrowExtractVectorElts( |
0 |
21510 |
bool DAGCombiner::refineExtractVectorEltIntoMultipleNarrowExtractVectorElts( |
0 |
| 21511 |
SDNode *N) { |
--- |
21511 |
SDNode *N) { |
--- |
| 21512 |
// We perform this optimization post type-legalization because |
--- |
21512 |
// We perform this optimization post type-legalization because |
--- |
| 21513 |
// the type-legalizer often scalarizes integer-promoted vectors. |
--- |
21513 |
// the type-legalizer often scalarizes integer-promoted vectors. |
--- |
| 21514 |
// Performing this optimization before may cause legalizaton cycles. |
--- |
21514 |
// Performing this optimization before may cause legalizaton cycles. |
--- |
| 21515 |
if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) |
0 |
21515 |
if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) |
0 |
| 21516 |
return false; |
0 |
21516 |
return false; |
0 |
| 21517 |
|
--- |
21517 |
|
--- |
| 21518 |
// TODO: Add support for big-endian. |
--- |
21518 |
// TODO: Add support for big-endian. |
--- |
| 21519 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
21519 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
| 21520 |
return false; |
0 |
21520 |
return false; |
0 |
| 21521 |
|
--- |
21521 |
|
--- |
| 21522 |
SDValue VecOp = N->getOperand(0); |
0 |
21522 |
SDValue VecOp = N->getOperand(0); |
0 |
| 21523 |
EVT VecVT = VecOp.getValueType(); |
0 |
21523 |
EVT VecVT = VecOp.getValueType(); |
0 |
| 21524 |
assert(!VecVT.isScalableVector() && "Only for fixed vectors."); |
0 |
21524 |
assert(!VecVT.isScalableVector() && "Only for fixed vectors."); |
0 |
| 21525 |
|
--- |
21525 |
|
--- |
| 21526 |
// We must start with a constant extraction index. |
--- |
21526 |
// We must start with a constant extraction index. |
--- |
| 21527 |
auto *IndexC = dyn_cast(N->getOperand(1)); |
0 |
21527 |
auto *IndexC = dyn_cast(N->getOperand(1)); |
0 |
| 21528 |
if (!IndexC) |
0 |
21528 |
if (!IndexC) |
0 |
| 21529 |
return false; |
0 |
21529 |
return false; |
0 |
| 21530 |
|
--- |
21530 |
|
--- |
| 21531 |
assert(IndexC->getZExtValue() < VecVT.getVectorNumElements() && |
0 |
21531 |
assert(IndexC->getZExtValue() < VecVT.getVectorNumElements() && |
0 |
| 21532 |
"Original ISD::EXTRACT_VECTOR_ELT is undefinend?"); |
--- |
21532 |
"Original ISD::EXTRACT_VECTOR_ELT is undefinend?"); |
--- |
| 21533 |
|
--- |
21533 |
|
--- |
| 21534 |
// TODO: deal with the case of implicit anyext of the extraction. |
--- |
21534 |
// TODO: deal with the case of implicit anyext of the extraction. |
--- |
| 21535 |
unsigned VecEltBitWidth = VecVT.getScalarSizeInBits(); |
0 |
21535 |
unsigned VecEltBitWidth = VecVT.getScalarSizeInBits(); |
0 |
| 21536 |
EVT ScalarVT = N->getValueType(0); |
0 |
21536 |
EVT ScalarVT = N->getValueType(0); |
0 |
| 21537 |
if (VecVT.getScalarType() != ScalarVT) |
0 |
21537 |
if (VecVT.getScalarType() != ScalarVT) |
0 |
| 21538 |
return false; |
0 |
21538 |
return false; |
0 |
| 21539 |
|
--- |
21539 |
|
--- |
| 21540 |
// TODO: deal with the cases other than everything being integer-typed. |
--- |
21540 |
// TODO: deal with the cases other than everything being integer-typed. |
--- |
| 21541 |
if (!ScalarVT.isScalarInteger()) |
0 |
21541 |
if (!ScalarVT.isScalarInteger()) |
0 |
| 21542 |
return false; |
0 |
21542 |
return false; |
0 |
| 21543 |
|
--- |
21543 |
|
--- |
| 21544 |
struct Entry { |
--- |
21544 |
struct Entry { |
--- |
| 21545 |
SDNode *Producer; |
--- |
21545 |
SDNode *Producer; |
--- |
| 21546 |
|
--- |
21546 |
|
--- |
| 21547 |
// Which bits of VecOp does it contain? |
--- |
21547 |
// Which bits of VecOp does it contain? |
--- |
| 21548 |
unsigned BitPos; |
--- |
21548 |
unsigned BitPos; |
--- |
| 21549 |
int NumBits; |
--- |
21549 |
int NumBits; |
--- |
| 21550 |
// NOTE: the actual width of \p Producer may be wider than NumBits! |
--- |
21550 |
// NOTE: the actual width of \p Producer may be wider than NumBits! |
--- |
| 21551 |
|
--- |
21551 |
|
--- |
| 21552 |
Entry(Entry &&) = default; |
--- |
21552 |
Entry(Entry &&) = default; |
--- |
| 21553 |
Entry(SDNode *Producer_, unsigned BitPos_, int NumBits_) |
0 |
21553 |
Entry(SDNode *Producer_, unsigned BitPos_, int NumBits_) |
0 |
| 21554 |
: Producer(Producer_), BitPos(BitPos_), NumBits(NumBits_) {} |
0 |
21554 |
: Producer(Producer_), BitPos(BitPos_), NumBits(NumBits_) {} |
0 |
| 21555 |
|
--- |
21555 |
|
--- |
| 21556 |
Entry() = delete; |
--- |
21556 |
Entry() = delete; |
--- |
| 21557 |
Entry(const Entry &) = delete; |
--- |
21557 |
Entry(const Entry &) = delete; |
--- |
| 21558 |
Entry &operator=(const Entry &) = delete; |
--- |
21558 |
Entry &operator=(const Entry &) = delete; |
--- |
| 21559 |
Entry &operator=(Entry &&) = delete; |
--- |
21559 |
Entry &operator=(Entry &&) = delete; |
--- |
| 21560 |
}; |
--- |
21560 |
}; |
--- |
| 21561 |
SmallVector Worklist; |
0 |
21561 |
SmallVector Worklist; |
0 |
| 21562 |
SmallVector Leafs; |
0 |
21562 |
SmallVector Leafs; |
0 |
| 21563 |
|
--- |
21563 |
|
--- |
| 21564 |
// We start at the "root" ISD::EXTRACT_VECTOR_ELT. |
--- |
21564 |
// We start at the "root" ISD::EXTRACT_VECTOR_ELT. |
--- |
| 21565 |
Worklist.emplace_back(N, /*BitPos=*/VecEltBitWidth * IndexC->getZExtValue(), |
0 |
21565 |
Worklist.emplace_back(N, /*BitPos=*/VecEltBitWidth * IndexC->getZExtValue(), |
0 |
| 21566 |
/*NumBits=*/VecEltBitWidth); |
--- |
21566 |
/*NumBits=*/VecEltBitWidth); |
--- |
| 21567 |
|
--- |
21567 |
|
--- |
| 21568 |
while (!Worklist.empty()) { |
0 |
21568 |
while (!Worklist.empty()) { |
0 |
| 21569 |
Entry E = Worklist.pop_back_val(); |
0 |
21569 |
Entry E = Worklist.pop_back_val(); |
0 |
| 21570 |
// Does the node not even use any of the VecOp bits? |
--- |
21570 |
// Does the node not even use any of the VecOp bits? |
--- |
| 21571 |
if (!(E.NumBits > 0 && E.BitPos < VecVT.getSizeInBits() && |
0 |
21571 |
if (!(E.NumBits > 0 && E.BitPos < VecVT.getSizeInBits() && |
0 |
| 21572 |
E.BitPos + E.NumBits <= VecVT.getSizeInBits())) |
0 |
21572 |
E.BitPos + E.NumBits <= VecVT.getSizeInBits())) |
0 |
| 21573 |
return false; // Let's allow the other combines clean this up first. |
0 |
21573 |
return false; // Let's allow the other combines clean this up first. |
0 |
| 21574 |
// Did we fail to model any of the users of the Producer? |
--- |
21574 |
// Did we fail to model any of the users of the Producer? |
--- |
| 21575 |
bool ProducerIsLeaf = false; |
0 |
21575 |
bool ProducerIsLeaf = false; |
0 |
| 21576 |
// Look at each user of this Producer. |
--- |
21576 |
// Look at each user of this Producer. |
--- |
| 21577 |
for (SDNode *User : E.Producer->uses()) { |
0 |
21577 |
for (SDNode *User : E.Producer->uses()) { |
0 |
| 21578 |
switch (User->getOpcode()) { |
0 |
21578 |
switch (User->getOpcode()) { |
0 |
| 21579 |
// TODO: support ISD::BITCAST |
--- |
21579 |
// TODO: support ISD::BITCAST |
--- |
| 21580 |
// TODO: support ISD::ANY_EXTEND |
--- |
21580 |
// TODO: support ISD::ANY_EXTEND |
--- |
| 21581 |
// TODO: support ISD::ZERO_EXTEND |
--- |
21581 |
// TODO: support ISD::ZERO_EXTEND |
--- |
| 21582 |
// TODO: support ISD::SIGN_EXTEND |
--- |
21582 |
// TODO: support ISD::SIGN_EXTEND |
--- |
| 21583 |
case ISD::TRUNCATE: |
0 |
21583 |
case ISD::TRUNCATE: |
0 |
| 21584 |
// Truncation simply means we keep position, but extract less bits. |
--- |
21584 |
// Truncation simply means we keep position, but extract less bits. |
--- |
| 21585 |
Worklist.emplace_back(User, E.BitPos, |
0 |
21585 |
Worklist.emplace_back(User, E.BitPos, |
0 |
| 21586 |
/*NumBits=*/User->getValueSizeInBits(0)); |
0 |
21586 |
/*NumBits=*/User->getValueSizeInBits(0)); |
0 |
| 21587 |
break; |
0 |
21587 |
break; |
0 |
| 21588 |
// TODO: support ISD::SRA |
--- |
21588 |
// TODO: support ISD::SRA |
--- |
| 21589 |
// TODO: support ISD::SHL |
--- |
21589 |
// TODO: support ISD::SHL |
--- |
| 21590 |
case ISD::SRL: |
0 |
21590 |
case ISD::SRL: |
0 |
| 21591 |
// We should be shifting the Producer by a constant amount. |
--- |
21591 |
// We should be shifting the Producer by a constant amount. |
--- |
| 21592 |
if (auto *ShAmtC = dyn_cast(User->getOperand(1)); |
0 |
21592 |
if (auto *ShAmtC = dyn_cast(User->getOperand(1)); |
0 |
| 21593 |
User->getOperand(0).getNode() == E.Producer && ShAmtC) { |
0 |
21593 |
User->getOperand(0).getNode() == E.Producer && ShAmtC) { |
0 |
| 21594 |
// Logical right-shift means that we start extraction later, |
--- |
21594 |
// Logical right-shift means that we start extraction later, |
--- |
| 21595 |
// but stop it at the same position we did previously. |
--- |
21595 |
// but stop it at the same position we did previously. |
--- |
| 21596 |
unsigned ShAmt = ShAmtC->getZExtValue(); |
0 |
21596 |
unsigned ShAmt = ShAmtC->getZExtValue(); |
0 |
| 21597 |
Worklist.emplace_back(User, E.BitPos + ShAmt, E.NumBits - ShAmt); |
0 |
21597 |
Worklist.emplace_back(User, E.BitPos + ShAmt, E.NumBits - ShAmt); |
0 |
| 21598 |
break; |
0 |
21598 |
break; |
0 |
| 21599 |
} |
--- |
21599 |
} |
--- |
| 21600 |
[[fallthrough]]; |
--- |
21600 |
[[fallthrough]]; |
--- |
| 21601 |
default: |
--- |
21601 |
default: |
--- |
| 21602 |
// We can not model this user of the Producer. |
--- |
21602 |
// We can not model this user of the Producer. |
--- |
| 21603 |
// Which means the current Producer will be a ISD::EXTRACT_VECTOR_ELT. |
--- |
21603 |
// Which means the current Producer will be a ISD::EXTRACT_VECTOR_ELT. |
--- |
| 21604 |
ProducerIsLeaf = true; |
0 |
21604 |
ProducerIsLeaf = true; |
0 |
| 21605 |
// Profitability check: all users that we can not model |
--- |
21605 |
// Profitability check: all users that we can not model |
--- |
| 21606 |
// must be ISD::BUILD_VECTOR's. |
--- |
21606 |
// must be ISD::BUILD_VECTOR's. |
--- |
| 21607 |
if (User->getOpcode() != ISD::BUILD_VECTOR) |
0 |
21607 |
if (User->getOpcode() != ISD::BUILD_VECTOR) |
0 |
| 21608 |
return false; |
0 |
21608 |
return false; |
0 |
| 21609 |
break; |
0 |
21609 |
break; |
0 |
| 21610 |
} |
--- |
21610 |
} |
--- |
| 21611 |
} |
--- |
21611 |
} |
--- |
| 21612 |
if (ProducerIsLeaf) |
0 |
21612 |
if (ProducerIsLeaf) |
0 |
| 21613 |
Leafs.emplace_back(std::move(E)); |
0 |
21613 |
Leafs.emplace_back(std::move(E)); |
0 |
| 21614 |
} |
--- |
21614 |
} |
--- |
| 21615 |
|
--- |
21615 |
|
--- |
| 21616 |
unsigned NewVecEltBitWidth = Leafs.front().NumBits; |
0 |
21616 |
unsigned NewVecEltBitWidth = Leafs.front().NumBits; |
0 |
| 21617 |
|
--- |
21617 |
|
--- |
| 21618 |
// If we are still at the same element granularity, give up, |
--- |
21618 |
// If we are still at the same element granularity, give up, |
--- |
| 21619 |
if (NewVecEltBitWidth == VecEltBitWidth) |
0 |
21619 |
if (NewVecEltBitWidth == VecEltBitWidth) |
0 |
| 21620 |
return false; |
0 |
21620 |
return false; |
0 |
| 21621 |
|
--- |
21621 |
|
--- |
| 21622 |
// The vector width must be a multiple of the new element width. |
--- |
21622 |
// The vector width must be a multiple of the new element width. |
--- |
| 21623 |
if (VecVT.getSizeInBits() % NewVecEltBitWidth != 0) |
0 |
21623 |
if (VecVT.getSizeInBits() % NewVecEltBitWidth != 0) |
0 |
| 21624 |
return false; |
0 |
21624 |
return false; |
0 |
| 21625 |
|
--- |
21625 |
|
--- |
| 21626 |
// All leafs must agree on the new element width. |
--- |
21626 |
// All leafs must agree on the new element width. |
--- |
| 21627 |
// All leafs must not expect any "padding" bits ontop of that width. |
--- |
21627 |
// All leafs must not expect any "padding" bits ontop of that width. |
--- |
| 21628 |
// All leafs must start extraction from multiple of that width. |
--- |
21628 |
// All leafs must start extraction from multiple of that width. |
--- |
| 21629 |
if (!all_of(Leafs, [NewVecEltBitWidth](const Entry &E) { |
0 |
21629 |
if (!all_of(Leafs, [NewVecEltBitWidth](const Entry &E) { |
0 |
| 21630 |
return (unsigned)E.NumBits == NewVecEltBitWidth && |
0 |
21630 |
return (unsigned)E.NumBits == NewVecEltBitWidth && |
0 |
| 21631 |
E.Producer->getValueSizeInBits(0) == NewVecEltBitWidth && |
0 |
21631 |
E.Producer->getValueSizeInBits(0) == NewVecEltBitWidth && |
0 |
| 21632 |
E.BitPos % NewVecEltBitWidth == 0; |
0 |
21632 |
E.BitPos % NewVecEltBitWidth == 0; |
0 |
| 21633 |
})) |
--- |
21633 |
})) |
--- |
| 21634 |
return false; |
0 |
21634 |
return false; |
0 |
| 21635 |
|
--- |
21635 |
|
--- |
| 21636 |
EVT NewScalarVT = EVT::getIntegerVT(*DAG.getContext(), NewVecEltBitWidth); |
0 |
21636 |
EVT NewScalarVT = EVT::getIntegerVT(*DAG.getContext(), NewVecEltBitWidth); |
0 |
| 21637 |
EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewScalarVT, |
0 |
21637 |
EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewScalarVT, |
0 |
| 21638 |
VecVT.getSizeInBits() / NewVecEltBitWidth); |
0 |
21638 |
VecVT.getSizeInBits() / NewVecEltBitWidth); |
0 |
| 21639 |
|
--- |
21639 |
|
--- |
| 21640 |
if (LegalTypes && |
0 |
21640 |
if (LegalTypes && |
0 |
| 21641 |
!(TLI.isTypeLegal(NewScalarVT) && TLI.isTypeLegal(NewVecVT))) |
0 |
21641 |
!(TLI.isTypeLegal(NewScalarVT) && TLI.isTypeLegal(NewVecVT))) |
0 |
| 21642 |
return false; |
0 |
21642 |
return false; |
0 |
| 21643 |
|
--- |
21643 |
|
--- |
| 21644 |
if (LegalOperations && |
0 |
21644 |
if (LegalOperations && |
0 |
| 21645 |
!(TLI.isOperationLegalOrCustom(ISD::BITCAST, NewVecVT) && |
0 |
21645 |
!(TLI.isOperationLegalOrCustom(ISD::BITCAST, NewVecVT) && |
0 |
| 21646 |
TLI.isOperationLegalOrCustom(ISD::EXTRACT_VECTOR_ELT, NewVecVT))) |
0 |
21646 |
TLI.isOperationLegalOrCustom(ISD::EXTRACT_VECTOR_ELT, NewVecVT))) |
0 |
| 21647 |
return false; |
0 |
21647 |
return false; |
0 |
| 21648 |
|
--- |
21648 |
|
--- |
| 21649 |
SDValue NewVecOp = DAG.getBitcast(NewVecVT, VecOp); |
0 |
21649 |
SDValue NewVecOp = DAG.getBitcast(NewVecVT, VecOp); |
0 |
| 21650 |
for (const Entry &E : Leafs) { |
0 |
21650 |
for (const Entry &E : Leafs) { |
0 |
| 21651 |
SDLoc DL(E.Producer); |
0 |
21651 |
SDLoc DL(E.Producer); |
0 |
| 21652 |
unsigned NewIndex = E.BitPos / NewVecEltBitWidth; |
0 |
21652 |
unsigned NewIndex = E.BitPos / NewVecEltBitWidth; |
0 |
| 21653 |
assert(NewIndex < NewVecVT.getVectorNumElements() && |
0 |
21653 |
assert(NewIndex < NewVecVT.getVectorNumElements() && |
0 |
| 21654 |
"Creating out-of-bounds ISD::EXTRACT_VECTOR_ELT?"); |
--- |
21654 |
"Creating out-of-bounds ISD::EXTRACT_VECTOR_ELT?"); |
--- |
| 21655 |
SDValue V = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, NewScalarVT, NewVecOp, |
0 |
21655 |
SDValue V = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, NewScalarVT, NewVecOp, |
0 |
| 21656 |
DAG.getVectorIdxConstant(NewIndex, DL)); |
0 |
21656 |
DAG.getVectorIdxConstant(NewIndex, DL)); |
0 |
| 21657 |
CombineTo(E.Producer, V); |
0 |
21657 |
CombineTo(E.Producer, V); |
0 |
| 21658 |
} |
0 |
21658 |
} |
0 |
| 21659 |
|
--- |
21659 |
|
--- |
| 21660 |
return true; |
0 |
21660 |
return true; |
0 |
| 21661 |
} |
0 |
21661 |
} |
0 |
| 21662 |
|
--- |
21662 |
|
--- |
| 21663 |
SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { |
0 |
21663 |
SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { |
0 |
| 21664 |
SDValue VecOp = N->getOperand(0); |
0 |
21664 |
SDValue VecOp = N->getOperand(0); |
0 |
| 21665 |
SDValue Index = N->getOperand(1); |
0 |
21665 |
SDValue Index = N->getOperand(1); |
0 |
| 21666 |
EVT ScalarVT = N->getValueType(0); |
0 |
21666 |
EVT ScalarVT = N->getValueType(0); |
0 |
| 21667 |
EVT VecVT = VecOp.getValueType(); |
0 |
21667 |
EVT VecVT = VecOp.getValueType(); |
0 |
| 21668 |
if (VecOp.isUndef()) |
0 |
21668 |
if (VecOp.isUndef()) |
0 |
| 21669 |
return DAG.getUNDEF(ScalarVT); |
0 |
21669 |
return DAG.getUNDEF(ScalarVT); |
0 |
| 21670 |
|
--- |
21670 |
|
--- |
| 21671 |
// extract_vector_elt (insert_vector_elt vec, val, idx), idx) -> val |
--- |
21671 |
// extract_vector_elt (insert_vector_elt vec, val, idx), idx) -> val |
--- |
| 21672 |
// |
--- |
21672 |
// |
--- |
| 21673 |
// This only really matters if the index is non-constant since other combines |
--- |
21673 |
// This only really matters if the index is non-constant since other combines |
--- |
| 21674 |
// on the constant elements already work. |
--- |
21674 |
// on the constant elements already work. |
--- |
| 21675 |
SDLoc DL(N); |
0 |
21675 |
SDLoc DL(N); |
0 |
| 21676 |
if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT && |
0 |
21676 |
if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT && |
0 |
| 21677 |
Index == VecOp.getOperand(2)) { |
0 |
21677 |
Index == VecOp.getOperand(2)) { |
0 |
| 21678 |
SDValue Elt = VecOp.getOperand(1); |
0 |
21678 |
SDValue Elt = VecOp.getOperand(1); |
0 |
| 21679 |
return VecVT.isInteger() ? DAG.getAnyExtOrTrunc(Elt, DL, ScalarVT) : Elt; |
0 |
21679 |
return VecVT.isInteger() ? DAG.getAnyExtOrTrunc(Elt, DL, ScalarVT) : Elt; |
0 |
| 21680 |
} |
--- |
21680 |
} |
--- |
| 21681 |
|
--- |
21681 |
|
--- |
| 21682 |
// (vextract (scalar_to_vector val, 0) -> val |
--- |
21682 |
// (vextract (scalar_to_vector val, 0) -> val |
--- |
| 21683 |
if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { |
0 |
21683 |
if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) { |
0 |
| 21684 |
// Only 0'th element of SCALAR_TO_VECTOR is defined. |
--- |
21684 |
// Only 0'th element of SCALAR_TO_VECTOR is defined. |
--- |
| 21685 |
if (DAG.isKnownNeverZero(Index)) |
0 |
21685 |
if (DAG.isKnownNeverZero(Index)) |
0 |
| 21686 |
return DAG.getUNDEF(ScalarVT); |
0 |
21686 |
return DAG.getUNDEF(ScalarVT); |
0 |
| 21687 |
|
--- |
21687 |
|
--- |
| 21688 |
// Check if the result type doesn't match the inserted element type. A |
--- |
21688 |
// Check if the result type doesn't match the inserted element type. A |
--- |
| 21689 |
// SCALAR_TO_VECTOR may truncate the inserted element and the |
--- |
21689 |
// SCALAR_TO_VECTOR may truncate the inserted element and the |
--- |
| 21690 |
// EXTRACT_VECTOR_ELT may widen the extracted vector. |
--- |
21690 |
// EXTRACT_VECTOR_ELT may widen the extracted vector. |
--- |
| 21691 |
SDValue InOp = VecOp.getOperand(0); |
0 |
21691 |
SDValue InOp = VecOp.getOperand(0); |
0 |
| 21692 |
if (InOp.getValueType() != ScalarVT) { |
0 |
21692 |
if (InOp.getValueType() != ScalarVT) { |
0 |
| 21693 |
assert(InOp.getValueType().isInteger() && ScalarVT.isInteger() && |
0 |
21693 |
assert(InOp.getValueType().isInteger() && ScalarVT.isInteger() && |
0 |
| 21694 |
InOp.getValueType().bitsGT(ScalarVT)); |
--- |
21694 |
InOp.getValueType().bitsGT(ScalarVT)); |
--- |
| 21695 |
return DAG.getNode(ISD::TRUNCATE, DL, ScalarVT, InOp); |
0 |
21695 |
return DAG.getNode(ISD::TRUNCATE, DL, ScalarVT, InOp); |
0 |
| 21696 |
} |
--- |
21696 |
} |
--- |
| 21697 |
return InOp; |
0 |
21697 |
return InOp; |
0 |
| 21698 |
} |
--- |
21698 |
} |
--- |
| 21699 |
|
--- |
21699 |
|
--- |
| 21700 |
// extract_vector_elt of out-of-bounds element -> UNDEF |
--- |
21700 |
// extract_vector_elt of out-of-bounds element -> UNDEF |
--- |
| 21701 |
auto *IndexC = dyn_cast(Index); |
0 |
21701 |
auto *IndexC = dyn_cast(Index); |
0 |
| 21702 |
if (IndexC && VecVT.isFixedLengthVector() && |
0 |
21702 |
if (IndexC && VecVT.isFixedLengthVector() && |
0 |
| 21703 |
IndexC->getAPIntValue().uge(VecVT.getVectorNumElements())) |
0 |
21703 |
IndexC->getAPIntValue().uge(VecVT.getVectorNumElements())) |
0 |
| 21704 |
return DAG.getUNDEF(ScalarVT); |
0 |
21704 |
return DAG.getUNDEF(ScalarVT); |
0 |
| 21705 |
|
--- |
21705 |
|
--- |
| 21706 |
// extract_vector_elt(freeze(x)), idx -> freeze(extract_vector_elt(x)), idx |
--- |
21706 |
// extract_vector_elt(freeze(x)), idx -> freeze(extract_vector_elt(x)), idx |
--- |
| 21707 |
if (VecOp.hasOneUse() && VecOp.getOpcode() == ISD::FREEZE) { |
0 |
21707 |
if (VecOp.hasOneUse() && VecOp.getOpcode() == ISD::FREEZE) { |
0 |
| 21708 |
return DAG.getFreeze(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarVT, |
0 |
21708 |
return DAG.getFreeze(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarVT, |
0 |
| 21709 |
VecOp.getOperand(0), Index)); |
0 |
21709 |
VecOp.getOperand(0), Index)); |
0 |
| 21710 |
} |
--- |
21710 |
} |
--- |
| 21711 |
|
--- |
21711 |
|
--- |
| 21712 |
// extract_vector_elt (build_vector x, y), 1 -> y |
--- |
21712 |
// extract_vector_elt (build_vector x, y), 1 -> y |
--- |
| 21713 |
if (((IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR) || |
0 |
21713 |
if (((IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR) || |
0 |
| 21714 |
VecOp.getOpcode() == ISD::SPLAT_VECTOR) && |
0 |
21714 |
VecOp.getOpcode() == ISD::SPLAT_VECTOR) && |
0 |
| 21715 |
TLI.isTypeLegal(VecVT)) { |
0 |
21715 |
TLI.isTypeLegal(VecVT)) { |
0 |
| 21716 |
assert((VecOp.getOpcode() != ISD::BUILD_VECTOR || |
0 |
21716 |
assert((VecOp.getOpcode() != ISD::BUILD_VECTOR || |
0 |
| 21717 |
VecVT.isFixedLengthVector()) && |
--- |
21717 |
VecVT.isFixedLengthVector()) && |
--- |
| 21718 |
"BUILD_VECTOR used for scalable vectors"); |
--- |
21718 |
"BUILD_VECTOR used for scalable vectors"); |
--- |
| 21719 |
unsigned IndexVal = |
--- |
21719 |
unsigned IndexVal = |
--- |
| 21720 |
VecOp.getOpcode() == ISD::BUILD_VECTOR ? IndexC->getZExtValue() : 0; |
0 |
21720 |
VecOp.getOpcode() == ISD::BUILD_VECTOR ? IndexC->getZExtValue() : 0; |
0 |
| 21721 |
SDValue Elt = VecOp.getOperand(IndexVal); |
0 |
21721 |
SDValue Elt = VecOp.getOperand(IndexVal); |
0 |
| 21722 |
EVT InEltVT = Elt.getValueType(); |
0 |
21722 |
EVT InEltVT = Elt.getValueType(); |
0 |
| 21723 |
|
--- |
21723 |
|
--- |
| 21724 |
if (VecOp.hasOneUse() || TLI.aggressivelyPreferBuildVectorSources(VecVT) || |
0 |
21724 |
if (VecOp.hasOneUse() || TLI.aggressivelyPreferBuildVectorSources(VecVT) || |
0 |
| 21725 |
isNullConstant(Elt)) { |
0 |
21725 |
isNullConstant(Elt)) { |
0 |
| 21726 |
// Sometimes build_vector's scalar input types do not match result type. |
--- |
21726 |
// Sometimes build_vector's scalar input types do not match result type. |
--- |
| 21727 |
if (ScalarVT == InEltVT) |
0 |
21727 |
if (ScalarVT == InEltVT) |
0 |
| 21728 |
return Elt; |
0 |
21728 |
return Elt; |
0 |
| 21729 |
|
--- |
21729 |
|
--- |
| 21730 |
// TODO: It may be useful to truncate if free if the build_vector |
--- |
21730 |
// TODO: It may be useful to truncate if free if the build_vector |
--- |
| 21731 |
// implicitly converts. |
--- |
21731 |
// implicitly converts. |
--- |
| 21732 |
} |
--- |
21732 |
} |
--- |
| 21733 |
} |
--- |
21733 |
} |
--- |
| 21734 |
|
--- |
21734 |
|
--- |
| 21735 |
if (SDValue BO = scalarizeExtractedBinop(N, DAG, LegalOperations)) |
0 |
21735 |
if (SDValue BO = scalarizeExtractedBinop(N, DAG, LegalOperations)) |
0 |
| 21736 |
return BO; |
0 |
21736 |
return BO; |
0 |
| 21737 |
|
--- |
21737 |
|
--- |
| 21738 |
if (VecVT.isScalableVector()) |
0 |
21738 |
if (VecVT.isScalableVector()) |
0 |
| 21739 |
return SDValue(); |
0 |
21739 |
return SDValue(); |
0 |
| 21740 |
|
--- |
21740 |
|
--- |
| 21741 |
// All the code from this point onwards assumes fixed width vectors, but it's |
--- |
21741 |
// All the code from this point onwards assumes fixed width vectors, but it's |
--- |
| 21742 |
// possible that some of the combinations could be made to work for scalable |
--- |
21742 |
// possible that some of the combinations could be made to work for scalable |
--- |
| 21743 |
// vectors too. |
--- |
21743 |
// vectors too. |
--- |
| 21744 |
unsigned NumElts = VecVT.getVectorNumElements(); |
0 |
21744 |
unsigned NumElts = VecVT.getVectorNumElements(); |
0 |
| 21745 |
unsigned VecEltBitWidth = VecVT.getScalarSizeInBits(); |
0 |
21745 |
unsigned VecEltBitWidth = VecVT.getScalarSizeInBits(); |
0 |
| 21746 |
|
--- |
21746 |
|
--- |
| 21747 |
// TODO: These transforms should not require the 'hasOneUse' restriction, but |
--- |
21747 |
// TODO: These transforms should not require the 'hasOneUse' restriction, but |
--- |
| 21748 |
// there are regressions on multiple targets without it. We can end up with a |
--- |
21748 |
// there are regressions on multiple targets without it. We can end up with a |
--- |
| 21749 |
// mess of scalar and vector code if we reduce only part of the DAG to scalar. |
--- |
21749 |
// mess of scalar and vector code if we reduce only part of the DAG to scalar. |
--- |
| 21750 |
if (IndexC && VecOp.getOpcode() == ISD::BITCAST && VecVT.isInteger() && |
0 |
21750 |
if (IndexC && VecOp.getOpcode() == ISD::BITCAST && VecVT.isInteger() && |
0 |
| 21751 |
VecOp.hasOneUse()) { |
0 |
21751 |
VecOp.hasOneUse()) { |
0 |
| 21752 |
// The vector index of the LSBs of the source depend on the endian-ness. |
--- |
21752 |
// The vector index of the LSBs of the source depend on the endian-ness. |
--- |
| 21753 |
bool IsLE = DAG.getDataLayout().isLittleEndian(); |
0 |
21753 |
bool IsLE = DAG.getDataLayout().isLittleEndian(); |
0 |
| 21754 |
unsigned ExtractIndex = IndexC->getZExtValue(); |
0 |
21754 |
unsigned ExtractIndex = IndexC->getZExtValue(); |
0 |
| 21755 |
// extract_elt (v2i32 (bitcast i64:x)), BCTruncElt -> i32 (trunc i64:x) |
--- |
21755 |
// extract_elt (v2i32 (bitcast i64:x)), BCTruncElt -> i32 (trunc i64:x) |
--- |
| 21756 |
unsigned BCTruncElt = IsLE ? 0 : NumElts - 1; |
0 |
21756 |
unsigned BCTruncElt = IsLE ? 0 : NumElts - 1; |
0 |
| 21757 |
SDValue BCSrc = VecOp.getOperand(0); |
0 |
21757 |
SDValue BCSrc = VecOp.getOperand(0); |
0 |
| 21758 |
if (ExtractIndex == BCTruncElt && BCSrc.getValueType().isScalarInteger()) |
0 |
21758 |
if (ExtractIndex == BCTruncElt && BCSrc.getValueType().isScalarInteger()) |
0 |
| 21759 |
return DAG.getAnyExtOrTrunc(BCSrc, DL, ScalarVT); |
0 |
21759 |
return DAG.getAnyExtOrTrunc(BCSrc, DL, ScalarVT); |
0 |
| 21760 |
|
--- |
21760 |
|
--- |
| 21761 |
if (LegalTypes && BCSrc.getValueType().isInteger() && |
0 |
21761 |
if (LegalTypes && BCSrc.getValueType().isInteger() && |
0 |
| 21762 |
BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) { |
0 |
21762 |
BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) { |
0 |
| 21763 |
// ext_elt (bitcast (scalar_to_vec i64 X to v2i64) to v4i32), TruncElt --> |
--- |
21763 |
// ext_elt (bitcast (scalar_to_vec i64 X to v2i64) to v4i32), TruncElt --> |
--- |
| 21764 |
// trunc i64 X to i32 |
--- |
21764 |
// trunc i64 X to i32 |
--- |
| 21765 |
SDValue X = BCSrc.getOperand(0); |
0 |
21765 |
SDValue X = BCSrc.getOperand(0); |
0 |
| 21766 |
assert(X.getValueType().isScalarInteger() && ScalarVT.isScalarInteger() && |
0 |
21766 |
assert(X.getValueType().isScalarInteger() && ScalarVT.isScalarInteger() && |
0 |
| 21767 |
"Extract element and scalar to vector can't change element type " |
--- |
21767 |
"Extract element and scalar to vector can't change element type " |
--- |
| 21768 |
"from FP to integer."); |
--- |
21768 |
"from FP to integer."); |
--- |
| 21769 |
unsigned XBitWidth = X.getValueSizeInBits(); |
0 |
21769 |
unsigned XBitWidth = X.getValueSizeInBits(); |
0 |
| 21770 |
BCTruncElt = IsLE ? 0 : XBitWidth / VecEltBitWidth - 1; |
0 |
21770 |
BCTruncElt = IsLE ? 0 : XBitWidth / VecEltBitWidth - 1; |
0 |
| 21771 |
|
--- |
21771 |
|
--- |
| 21772 |
// An extract element return value type can be wider than its vector |
--- |
21772 |
// An extract element return value type can be wider than its vector |
--- |
| 21773 |
// operand element type. In that case, the high bits are undefined, so |
--- |
21773 |
// operand element type. In that case, the high bits are undefined, so |
--- |
| 21774 |
// it's possible that we may need to extend rather than truncate. |
--- |
21774 |
// it's possible that we may need to extend rather than truncate. |
--- |
| 21775 |
if (ExtractIndex == BCTruncElt && XBitWidth > VecEltBitWidth) { |
0 |
21775 |
if (ExtractIndex == BCTruncElt && XBitWidth > VecEltBitWidth) { |
0 |
| 21776 |
assert(XBitWidth % VecEltBitWidth == 0 && |
0 |
21776 |
assert(XBitWidth % VecEltBitWidth == 0 && |
0 |
| 21777 |
"Scalar bitwidth must be a multiple of vector element bitwidth"); |
--- |
21777 |
"Scalar bitwidth must be a multiple of vector element bitwidth"); |
--- |
| 21778 |
return DAG.getAnyExtOrTrunc(X, DL, ScalarVT); |
0 |
21778 |
return DAG.getAnyExtOrTrunc(X, DL, ScalarVT); |
0 |
| 21779 |
} |
--- |
21779 |
} |
--- |
| 21780 |
} |
--- |
21780 |
} |
--- |
| 21781 |
} |
--- |
21781 |
} |
--- |
| 21782 |
|
--- |
21782 |
|
--- |
| 21783 |
// Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. |
--- |
21783 |
// Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. |
--- |
| 21784 |
// We only perform this optimization before the op legalization phase because |
--- |
21784 |
// We only perform this optimization before the op legalization phase because |
--- |
| 21785 |
// we may introduce new vector instructions which are not backed by TD |
--- |
21785 |
// we may introduce new vector instructions which are not backed by TD |
--- |
| 21786 |
// patterns. For example on AVX, extracting elements from a wide vector |
--- |
21786 |
// patterns. For example on AVX, extracting elements from a wide vector |
--- |
| 21787 |
// without using extract_subvector. However, if we can find an underlying |
--- |
21787 |
// without using extract_subvector. However, if we can find an underlying |
--- |
| 21788 |
// scalar value, then we can always use that. |
--- |
21788 |
// scalar value, then we can always use that. |
--- |
| 21789 |
if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { |
0 |
21789 |
if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { |
0 |
| 21790 |
auto *Shuf = cast(VecOp); |
0 |
21790 |
auto *Shuf = cast(VecOp); |
0 |
| 21791 |
// Find the new index to extract from. |
--- |
21791 |
// Find the new index to extract from. |
--- |
| 21792 |
int OrigElt = Shuf->getMaskElt(IndexC->getZExtValue()); |
0 |
21792 |
int OrigElt = Shuf->getMaskElt(IndexC->getZExtValue()); |
0 |
| 21793 |
|
--- |
21793 |
|
--- |
| 21794 |
// Extracting an undef index is undef. |
--- |
21794 |
// Extracting an undef index is undef. |
--- |
| 21795 |
if (OrigElt == -1) |
0 |
21795 |
if (OrigElt == -1) |
0 |
| 21796 |
return DAG.getUNDEF(ScalarVT); |
0 |
21796 |
return DAG.getUNDEF(ScalarVT); |
0 |
| 21797 |
|
--- |
21797 |
|
--- |
| 21798 |
// Select the right vector half to extract from. |
--- |
21798 |
// Select the right vector half to extract from. |
--- |
| 21799 |
SDValue SVInVec; |
0 |
21799 |
SDValue SVInVec; |
0 |
| 21800 |
if (OrigElt < (int)NumElts) { |
0 |
21800 |
if (OrigElt < (int)NumElts) { |
0 |
| 21801 |
SVInVec = VecOp.getOperand(0); |
0 |
21801 |
SVInVec = VecOp.getOperand(0); |
0 |
| 21802 |
} else { |
--- |
21802 |
} else { |
--- |
| 21803 |
SVInVec = VecOp.getOperand(1); |
0 |
21803 |
SVInVec = VecOp.getOperand(1); |
0 |
| 21804 |
OrigElt -= NumElts; |
0 |
21804 |
OrigElt -= NumElts; |
0 |
| 21805 |
} |
--- |
21805 |
} |
--- |
| 21806 |
|
--- |
21806 |
|
--- |
| 21807 |
if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) { |
0 |
21807 |
if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) { |
0 |
| 21808 |
SDValue InOp = SVInVec.getOperand(OrigElt); |
0 |
21808 |
SDValue InOp = SVInVec.getOperand(OrigElt); |
0 |
| 21809 |
if (InOp.getValueType() != ScalarVT) { |
0 |
21809 |
if (InOp.getValueType() != ScalarVT) { |
0 |
| 21810 |
assert(InOp.getValueType().isInteger() && ScalarVT.isInteger()); |
0 |
21810 |
assert(InOp.getValueType().isInteger() && ScalarVT.isInteger()); |
0 |
| 21811 |
InOp = DAG.getSExtOrTrunc(InOp, DL, ScalarVT); |
0 |
21811 |
InOp = DAG.getSExtOrTrunc(InOp, DL, ScalarVT); |
0 |
| 21812 |
} |
--- |
21812 |
} |
--- |
| 21813 |
|
--- |
21813 |
|
--- |
| 21814 |
return InOp; |
0 |
21814 |
return InOp; |
0 |
| 21815 |
} |
--- |
21815 |
} |
--- |
| 21816 |
|
--- |
21816 |
|
--- |
| 21817 |
// FIXME: We should handle recursing on other vector shuffles and |
--- |
21817 |
// FIXME: We should handle recursing on other vector shuffles and |
--- |
| 21818 |
// scalar_to_vector here as well. |
--- |
21818 |
// scalar_to_vector here as well. |
--- |
| 21819 |
|
--- |
21819 |
|
--- |
| 21820 |
if (!LegalOperations || |
0 |
21820 |
if (!LegalOperations || |
0 |
| 21821 |
// FIXME: Should really be just isOperationLegalOrCustom. |
--- |
21821 |
// FIXME: Should really be just isOperationLegalOrCustom. |
--- |
| 21822 |
TLI.isOperationLegal(ISD::EXTRACT_VECTOR_ELT, VecVT) || |
0 |
21822 |
TLI.isOperationLegal(ISD::EXTRACT_VECTOR_ELT, VecVT) || |
0 |
| 21823 |
TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) { |
0 |
21823 |
TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) { |
0 |
| 21824 |
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarVT, SVInVec, |
0 |
21824 |
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarVT, SVInVec, |
0 |
| 21825 |
DAG.getVectorIdxConstant(OrigElt, DL)); |
0 |
21825 |
DAG.getVectorIdxConstant(OrigElt, DL)); |
0 |
| 21826 |
} |
--- |
21826 |
} |
--- |
| 21827 |
} |
--- |
21827 |
} |
--- |
| 21828 |
|
--- |
21828 |
|
--- |
| 21829 |
// If only EXTRACT_VECTOR_ELT nodes use the source vector we can |
--- |
21829 |
// If only EXTRACT_VECTOR_ELT nodes use the source vector we can |
--- |
| 21830 |
// simplify it based on the (valid) extraction indices. |
--- |
21830 |
// simplify it based on the (valid) extraction indices. |
--- |
| 21831 |
if (llvm::all_of(VecOp->uses(), [&](SDNode *Use) { |
0 |
21831 |
if (llvm::all_of(VecOp->uses(), [&](SDNode *Use) { |
0 |
| 21832 |
return Use->getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
0 |
21832 |
return Use->getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
0 |
| 21833 |
Use->getOperand(0) == VecOp && |
0 |
21833 |
Use->getOperand(0) == VecOp && |
0 |
| 21834 |
isa(Use->getOperand(1)); |
0 |
21834 |
isa(Use->getOperand(1)); |
0 |
| 21835 |
})) { |
--- |
21835 |
})) { |
--- |
| 21836 |
APInt DemandedElts = APInt::getZero(NumElts); |
0 |
21836 |
APInt DemandedElts = APInt::getZero(NumElts); |
0 |
| 21837 |
for (SDNode *Use : VecOp->uses()) { |
0 |
21837 |
for (SDNode *Use : VecOp->uses()) { |
0 |
| 21838 |
auto *CstElt = cast(Use->getOperand(1)); |
0 |
21838 |
auto *CstElt = cast(Use->getOperand(1)); |
0 |
| 21839 |
if (CstElt->getAPIntValue().ult(NumElts)) |
0 |
21839 |
if (CstElt->getAPIntValue().ult(NumElts)) |
0 |
| 21840 |
DemandedElts.setBit(CstElt->getZExtValue()); |
0 |
21840 |
DemandedElts.setBit(CstElt->getZExtValue()); |
0 |
| 21841 |
} |
--- |
21841 |
} |
--- |
| 21842 |
if (SimplifyDemandedVectorElts(VecOp, DemandedElts, true)) { |
0 |
21842 |
if (SimplifyDemandedVectorElts(VecOp, DemandedElts, true)) { |
0 |
| 21843 |
// We simplified the vector operand of this extract element. If this |
--- |
21843 |
// We simplified the vector operand of this extract element. If this |
--- |
| 21844 |
// extract is not dead, visit it again so it is folded properly. |
--- |
21844 |
// extract is not dead, visit it again so it is folded properly. |
--- |
| 21845 |
if (N->getOpcode() != ISD::DELETED_NODE) |
0 |
21845 |
if (N->getOpcode() != ISD::DELETED_NODE) |
0 |
| 21846 |
AddToWorklist(N); |
0 |
21846 |
AddToWorklist(N); |
0 |
| 21847 |
return SDValue(N, 0); |
0 |
21847 |
return SDValue(N, 0); |
0 |
| 21848 |
} |
--- |
21848 |
} |
--- |
| 21849 |
APInt DemandedBits = APInt::getAllOnes(VecEltBitWidth); |
0 |
21849 |
APInt DemandedBits = APInt::getAllOnes(VecEltBitWidth); |
0 |
| 21850 |
if (SimplifyDemandedBits(VecOp, DemandedBits, DemandedElts, true)) { |
0 |
21850 |
if (SimplifyDemandedBits(VecOp, DemandedBits, DemandedElts, true)) { |
0 |
| 21851 |
// We simplified the vector operand of this extract element. If this |
--- |
21851 |
// We simplified the vector operand of this extract element. If this |
--- |
| 21852 |
// extract is not dead, visit it again so it is folded properly. |
--- |
21852 |
// extract is not dead, visit it again so it is folded properly. |
--- |
| 21853 |
if (N->getOpcode() != ISD::DELETED_NODE) |
0 |
21853 |
if (N->getOpcode() != ISD::DELETED_NODE) |
0 |
| 21854 |
AddToWorklist(N); |
0 |
21854 |
AddToWorklist(N); |
0 |
| 21855 |
return SDValue(N, 0); |
0 |
21855 |
return SDValue(N, 0); |
0 |
| 21856 |
} |
--- |
21856 |
} |
--- |
| 21857 |
} |
0 |
21857 |
} |
0 |
| 21858 |
|
--- |
21858 |
|
--- |
| 21859 |
if (refineExtractVectorEltIntoMultipleNarrowExtractVectorElts(N)) |
0 |
21859 |
if (refineExtractVectorEltIntoMultipleNarrowExtractVectorElts(N)) |
0 |
| 21860 |
return SDValue(N, 0); |
0 |
21860 |
return SDValue(N, 0); |
0 |
| 21861 |
|
--- |
21861 |
|
--- |
| 21862 |
// Everything under here is trying to match an extract of a loaded value. |
--- |
21862 |
// Everything under here is trying to match an extract of a loaded value. |
--- |
| 21863 |
// If the result of load has to be truncated, then it's not necessarily |
--- |
21863 |
// If the result of load has to be truncated, then it's not necessarily |
--- |
| 21864 |
// profitable. |
--- |
21864 |
// profitable. |
--- |
| 21865 |
bool BCNumEltsChanged = false; |
0 |
21865 |
bool BCNumEltsChanged = false; |
0 |
| 21866 |
EVT ExtVT = VecVT.getVectorElementType(); |
0 |
21866 |
EVT ExtVT = VecVT.getVectorElementType(); |
0 |
| 21867 |
EVT LVT = ExtVT; |
0 |
21867 |
EVT LVT = ExtVT; |
0 |
| 21868 |
if (ScalarVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, ScalarVT)) |
0 |
21868 |
if (ScalarVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, ScalarVT)) |
0 |
| 21869 |
return SDValue(); |
0 |
21869 |
return SDValue(); |
0 |
| 21870 |
|
--- |
21870 |
|
--- |
| 21871 |
if (VecOp.getOpcode() == ISD::BITCAST) { |
0 |
21871 |
if (VecOp.getOpcode() == ISD::BITCAST) { |
0 |
| 21872 |
// Don't duplicate a load with other uses. |
--- |
21872 |
// Don't duplicate a load with other uses. |
--- |
| 21873 |
if (!VecOp.hasOneUse()) |
0 |
21873 |
if (!VecOp.hasOneUse()) |
0 |
| 21874 |
return SDValue(); |
0 |
21874 |
return SDValue(); |
0 |
| 21875 |
|
--- |
21875 |
|
--- |
| 21876 |
EVT BCVT = VecOp.getOperand(0).getValueType(); |
0 |
21876 |
EVT BCVT = VecOp.getOperand(0).getValueType(); |
0 |
| 21877 |
if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) |
0 |
21877 |
if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) |
0 |
| 21878 |
return SDValue(); |
0 |
21878 |
return SDValue(); |
0 |
| 21879 |
if (NumElts != BCVT.getVectorNumElements()) |
0 |
21879 |
if (NumElts != BCVT.getVectorNumElements()) |
0 |
| 21880 |
BCNumEltsChanged = true; |
0 |
21880 |
BCNumEltsChanged = true; |
0 |
| 21881 |
VecOp = VecOp.getOperand(0); |
0 |
21881 |
VecOp = VecOp.getOperand(0); |
0 |
| 21882 |
ExtVT = BCVT.getVectorElementType(); |
0 |
21882 |
ExtVT = BCVT.getVectorElementType(); |
0 |
| 21883 |
} |
--- |
21883 |
} |
--- |
| 21884 |
|
--- |
21884 |
|
--- |
| 21885 |
// extract (vector load $addr), i --> load $addr + i * size |
--- |
21885 |
// extract (vector load $addr), i --> load $addr + i * size |
--- |
| 21886 |
if (!LegalOperations && !IndexC && VecOp.hasOneUse() && |
0 |
21886 |
if (!LegalOperations && !IndexC && VecOp.hasOneUse() && |
0 |
| 21887 |
ISD::isNormalLoad(VecOp.getNode()) && |
0 |
21887 |
ISD::isNormalLoad(VecOp.getNode()) && |
0 |
| 21888 |
!Index->hasPredecessor(VecOp.getNode())) { |
0 |
21888 |
!Index->hasPredecessor(VecOp.getNode())) { |
0 |
| 21889 |
auto *VecLoad = dyn_cast(VecOp); |
0 |
21889 |
auto *VecLoad = dyn_cast(VecOp); |
0 |
| 21890 |
if (VecLoad && VecLoad->isSimple()) |
0 |
21890 |
if (VecLoad && VecLoad->isSimple()) |
0 |
| 21891 |
return scalarizeExtractedVectorLoad(N, VecVT, Index, VecLoad); |
0 |
21891 |
return scalarizeExtractedVectorLoad(N, VecVT, Index, VecLoad); |
0 |
| 21892 |
} |
--- |
21892 |
} |
--- |
| 21893 |
|
--- |
21893 |
|
--- |
| 21894 |
// Perform only after legalization to ensure build_vector / vector_shuffle |
--- |
21894 |
// Perform only after legalization to ensure build_vector / vector_shuffle |
--- |
| 21895 |
// optimizations have already been done. |
--- |
21895 |
// optimizations have already been done. |
--- |
| 21896 |
if (!LegalOperations || !IndexC) |
0 |
21896 |
if (!LegalOperations || !IndexC) |
0 |
| 21897 |
return SDValue(); |
0 |
21897 |
return SDValue(); |
0 |
| 21898 |
|
--- |
21898 |
|
--- |
| 21899 |
// (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) |
--- |
21899 |
// (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) |
--- |
| 21900 |
// (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) |
--- |
21900 |
// (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) |
--- |
| 21901 |
// (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) |
--- |
21901 |
// (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) |
--- |
| 21902 |
int Elt = IndexC->getZExtValue(); |
0 |
21902 |
int Elt = IndexC->getZExtValue(); |
0 |
| 21903 |
LoadSDNode *LN0 = nullptr; |
0 |
21903 |
LoadSDNode *LN0 = nullptr; |
0 |
| 21904 |
if (ISD::isNormalLoad(VecOp.getNode())) { |
0 |
21904 |
if (ISD::isNormalLoad(VecOp.getNode())) { |
0 |
| 21905 |
LN0 = cast(VecOp); |
0 |
21905 |
LN0 = cast(VecOp); |
0 |
| 21906 |
} else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && |
0 |
21906 |
} else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR && |
0 |
| 21907 |
VecOp.getOperand(0).getValueType() == ExtVT && |
0 |
21907 |
VecOp.getOperand(0).getValueType() == ExtVT && |
0 |
| 21908 |
ISD::isNormalLoad(VecOp.getOperand(0).getNode())) { |
0 |
21908 |
ISD::isNormalLoad(VecOp.getOperand(0).getNode())) { |
0 |
| 21909 |
// Don't duplicate a load with other uses. |
--- |
21909 |
// Don't duplicate a load with other uses. |
--- |
| 21910 |
if (!VecOp.hasOneUse()) |
0 |
21910 |
if (!VecOp.hasOneUse()) |
0 |
| 21911 |
return SDValue(); |
0 |
21911 |
return SDValue(); |
0 |
| 21912 |
|
--- |
21912 |
|
--- |
| 21913 |
LN0 = cast(VecOp.getOperand(0)); |
0 |
21913 |
LN0 = cast(VecOp.getOperand(0)); |
0 |
| 21914 |
} |
--- |
21914 |
} |
--- |
| 21915 |
if (auto *Shuf = dyn_cast(VecOp)) { |
0 |
21915 |
if (auto *Shuf = dyn_cast(VecOp)) { |
0 |
| 21916 |
// (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) |
--- |
21916 |
// (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) |
--- |
| 21917 |
// => |
--- |
21917 |
// => |
--- |
| 21918 |
// (load $addr+1*size) |
--- |
21918 |
// (load $addr+1*size) |
--- |
| 21919 |
|
--- |
21919 |
|
--- |
| 21920 |
// Don't duplicate a load with other uses. |
--- |
21920 |
// Don't duplicate a load with other uses. |
--- |
| 21921 |
if (!VecOp.hasOneUse()) |
0 |
21921 |
if (!VecOp.hasOneUse()) |
0 |
| 21922 |
return SDValue(); |
0 |
21922 |
return SDValue(); |
0 |
| 21923 |
|
--- |
21923 |
|
--- |
| 21924 |
// If the bit convert changed the number of elements, it is unsafe |
--- |
21924 |
// If the bit convert changed the number of elements, it is unsafe |
--- |
| 21925 |
// to examine the mask. |
--- |
21925 |
// to examine the mask. |
--- |
| 21926 |
if (BCNumEltsChanged) |
0 |
21926 |
if (BCNumEltsChanged) |
0 |
| 21927 |
return SDValue(); |
0 |
21927 |
return SDValue(); |
0 |
| 21928 |
|
--- |
21928 |
|
--- |
| 21929 |
// Select the input vector, guarding against out of range extract vector. |
--- |
21929 |
// Select the input vector, guarding against out of range extract vector. |
--- |
| 21930 |
int Idx = (Elt > (int)NumElts) ? -1 : Shuf->getMaskElt(Elt); |
0 |
21930 |
int Idx = (Elt > (int)NumElts) ? -1 : Shuf->getMaskElt(Elt); |
0 |
| 21931 |
VecOp = (Idx < (int)NumElts) ? VecOp.getOperand(0) : VecOp.getOperand(1); |
0 |
21931 |
VecOp = (Idx < (int)NumElts) ? VecOp.getOperand(0) : VecOp.getOperand(1); |
0 |
| 21932 |
|
--- |
21932 |
|
--- |
| 21933 |
if (VecOp.getOpcode() == ISD::BITCAST) { |
0 |
21933 |
if (VecOp.getOpcode() == ISD::BITCAST) { |
0 |
| 21934 |
// Don't duplicate a load with other uses. |
--- |
21934 |
// Don't duplicate a load with other uses. |
--- |
| 21935 |
if (!VecOp.hasOneUse()) |
0 |
21935 |
if (!VecOp.hasOneUse()) |
0 |
| 21936 |
return SDValue(); |
0 |
21936 |
return SDValue(); |
0 |
| 21937 |
|
--- |
21937 |
|
--- |
| 21938 |
VecOp = VecOp.getOperand(0); |
0 |
21938 |
VecOp = VecOp.getOperand(0); |
0 |
| 21939 |
} |
--- |
21939 |
} |
--- |
| 21940 |
if (ISD::isNormalLoad(VecOp.getNode())) { |
0 |
21940 |
if (ISD::isNormalLoad(VecOp.getNode())) { |
0 |
| 21941 |
LN0 = cast(VecOp); |
0 |
21941 |
LN0 = cast(VecOp); |
0 |
| 21942 |
Elt = (Idx < (int)NumElts) ? Idx : Idx - (int)NumElts; |
0 |
21942 |
Elt = (Idx < (int)NumElts) ? Idx : Idx - (int)NumElts; |
0 |
| 21943 |
Index = DAG.getConstant(Elt, DL, Index.getValueType()); |
0 |
21943 |
Index = DAG.getConstant(Elt, DL, Index.getValueType()); |
0 |
| 21944 |
} |
--- |
21944 |
} |
--- |
| 21945 |
} else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS && !BCNumEltsChanged && |
0 |
21945 |
} else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS && !BCNumEltsChanged && |
0 |
| 21946 |
VecVT.getVectorElementType() == ScalarVT && |
0 |
21946 |
VecVT.getVectorElementType() == ScalarVT && |
0 |
| 21947 |
(!LegalTypes || |
0 |
21947 |
(!LegalTypes || |
0 |
| 21948 |
TLI.isTypeLegal( |
0 |
21948 |
TLI.isTypeLegal( |
0 |
| 21949 |
VecOp.getOperand(0).getValueType().getVectorElementType()))) { |
0 |
21949 |
VecOp.getOperand(0).getValueType().getVectorElementType()))) { |
0 |
| 21950 |
// extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 0 |
--- |
21950 |
// extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 0 |
--- |
| 21951 |
// -> extract_vector_elt a, 0 |
--- |
21951 |
// -> extract_vector_elt a, 0 |
--- |
| 21952 |
// extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 1 |
--- |
21952 |
// extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 1 |
--- |
| 21953 |
// -> extract_vector_elt a, 1 |
--- |
21953 |
// -> extract_vector_elt a, 1 |
--- |
| 21954 |
// extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 2 |
--- |
21954 |
// extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 2 |
--- |
| 21955 |
// -> extract_vector_elt b, 0 |
--- |
21955 |
// -> extract_vector_elt b, 0 |
--- |
| 21956 |
// extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 3 |
--- |
21956 |
// extract_vector_elt (concat_vectors v2i16:a, v2i16:b), 3 |
--- |
| 21957 |
// -> extract_vector_elt b, 1 |
--- |
21957 |
// -> extract_vector_elt b, 1 |
--- |
| 21958 |
SDLoc SL(N); |
0 |
21958 |
SDLoc SL(N); |
0 |
| 21959 |
EVT ConcatVT = VecOp.getOperand(0).getValueType(); |
0 |
21959 |
EVT ConcatVT = VecOp.getOperand(0).getValueType(); |
0 |
| 21960 |
unsigned ConcatNumElts = ConcatVT.getVectorNumElements(); |
0 |
21960 |
unsigned ConcatNumElts = ConcatVT.getVectorNumElements(); |
0 |
| 21961 |
SDValue NewIdx = DAG.getConstant(Elt % ConcatNumElts, SL, |
0 |
21961 |
SDValue NewIdx = DAG.getConstant(Elt % ConcatNumElts, SL, |
0 |
| 21962 |
Index.getValueType()); |
--- |
21962 |
Index.getValueType()); |
--- |
| 21963 |
|
--- |
21963 |
|
--- |
| 21964 |
SDValue ConcatOp = VecOp.getOperand(Elt / ConcatNumElts); |
0 |
21964 |
SDValue ConcatOp = VecOp.getOperand(Elt / ConcatNumElts); |
0 |
| 21965 |
SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, |
0 |
21965 |
SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, |
0 |
| 21966 |
ConcatVT.getVectorElementType(), |
--- |
21966 |
ConcatVT.getVectorElementType(), |
--- |
| 21967 |
ConcatOp, NewIdx); |
--- |
21967 |
ConcatOp, NewIdx); |
--- |
| 21968 |
return DAG.getNode(ISD::BITCAST, SL, ScalarVT, Elt); |
0 |
21968 |
return DAG.getNode(ISD::BITCAST, SL, ScalarVT, Elt); |
0 |
| 21969 |
} |
0 |
21969 |
} |
0 |
| 21970 |
|
--- |
21970 |
|
--- |
| 21971 |
// Make sure we found a non-volatile load and the extractelement is |
--- |
21971 |
// Make sure we found a non-volatile load and the extractelement is |
--- |
| 21972 |
// the only use. |
--- |
21972 |
// the only use. |
--- |
| 21973 |
if (!LN0 || !LN0->hasNUsesOfValue(1,0) || !LN0->isSimple()) |
0 |
21973 |
if (!LN0 || !LN0->hasNUsesOfValue(1,0) || !LN0->isSimple()) |
0 |
| 21974 |
return SDValue(); |
0 |
21974 |
return SDValue(); |
0 |
| 21975 |
|
--- |
21975 |
|
--- |
| 21976 |
// If Idx was -1 above, Elt is going to be -1, so just return undef. |
--- |
21976 |
// If Idx was -1 above, Elt is going to be -1, so just return undef. |
--- |
| 21977 |
if (Elt == -1) |
0 |
21977 |
if (Elt == -1) |
0 |
| 21978 |
return DAG.getUNDEF(LVT); |
0 |
21978 |
return DAG.getUNDEF(LVT); |
0 |
| 21979 |
|
--- |
21979 |
|
--- |
| 21980 |
return scalarizeExtractedVectorLoad(N, VecVT, Index, LN0); |
0 |
21980 |
return scalarizeExtractedVectorLoad(N, VecVT, Index, LN0); |
0 |
| 21981 |
} |
0 |
21981 |
} |
0 |
| 21982 |
|
--- |
21982 |
|
--- |
| 21983 |
// Simplify (build_vec (ext )) to (bitcast (build_vec )) |
--- |
21983 |
// Simplify (build_vec (ext )) to (bitcast (build_vec )) |
--- |
| 21984 |
SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) { |
0 |
21984 |
SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) { |
0 |
| 21985 |
// We perform this optimization post type-legalization because |
--- |
21985 |
// We perform this optimization post type-legalization because |
--- |
| 21986 |
// the type-legalizer often scalarizes integer-promoted vectors. |
--- |
21986 |
// the type-legalizer often scalarizes integer-promoted vectors. |
--- |
| 21987 |
// Performing this optimization before may create bit-casts which |
--- |
21987 |
// Performing this optimization before may create bit-casts which |
--- |
| 21988 |
// will be type-legalized to complex code sequences. |
--- |
21988 |
// will be type-legalized to complex code sequences. |
--- |
| 21989 |
// We perform this optimization only before the operation legalizer because we |
--- |
21989 |
// We perform this optimization only before the operation legalizer because we |
--- |
| 21990 |
// may introduce illegal operations. |
--- |
21990 |
// may introduce illegal operations. |
--- |
| 21991 |
if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) |
0 |
21991 |
if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) |
0 |
| 21992 |
return SDValue(); |
0 |
21992 |
return SDValue(); |
0 |
| 21993 |
|
--- |
21993 |
|
--- |
| 21994 |
unsigned NumInScalars = N->getNumOperands(); |
0 |
21994 |
unsigned NumInScalars = N->getNumOperands(); |
0 |
| 21995 |
SDLoc DL(N); |
0 |
21995 |
SDLoc DL(N); |
0 |
| 21996 |
EVT VT = N->getValueType(0); |
0 |
21996 |
EVT VT = N->getValueType(0); |
0 |
| 21997 |
|
--- |
21997 |
|
--- |
| 21998 |
// Check to see if this is a BUILD_VECTOR of a bunch of values |
--- |
21998 |
// Check to see if this is a BUILD_VECTOR of a bunch of values |
--- |
| 21999 |
// which come from any_extend or zero_extend nodes. If so, we can create |
--- |
21999 |
// which come from any_extend or zero_extend nodes. If so, we can create |
--- |
| 22000 |
// a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR |
--- |
22000 |
// a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR |
--- |
| 22001 |
// optimizations. We do not handle sign-extend because we can't fill the sign |
--- |
22001 |
// optimizations. We do not handle sign-extend because we can't fill the sign |
--- |
| 22002 |
// using shuffles. |
--- |
22002 |
// using shuffles. |
--- |
| 22003 |
EVT SourceType = MVT::Other; |
0 |
22003 |
EVT SourceType = MVT::Other; |
0 |
| 22004 |
bool AllAnyExt = true; |
0 |
22004 |
bool AllAnyExt = true; |
0 |
| 22005 |
|
--- |
22005 |
|
--- |
| 22006 |
for (unsigned i = 0; i != NumInScalars; ++i) { |
0 |
22006 |
for (unsigned i = 0; i != NumInScalars; ++i) { |
0 |
| 22007 |
SDValue In = N->getOperand(i); |
0 |
22007 |
SDValue In = N->getOperand(i); |
0 |
| 22008 |
// Ignore undef inputs. |
--- |
22008 |
// Ignore undef inputs. |
--- |
| 22009 |
if (In.isUndef()) continue; |
0 |
22009 |
if (In.isUndef()) continue; |
0 |
| 22010 |
|
--- |
22010 |
|
--- |
| 22011 |
bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; |
0 |
22011 |
bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; |
0 |
| 22012 |
bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; |
0 |
22012 |
bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; |
0 |
| 22013 |
|
--- |
22013 |
|
--- |
| 22014 |
// Abort if the element is not an extension. |
--- |
22014 |
// Abort if the element is not an extension. |
--- |
| 22015 |
if (!ZeroExt && !AnyExt) { |
0 |
22015 |
if (!ZeroExt && !AnyExt) { |
0 |
| 22016 |
SourceType = MVT::Other; |
0 |
22016 |
SourceType = MVT::Other; |
0 |
| 22017 |
break; |
0 |
22017 |
break; |
0 |
| 22018 |
} |
--- |
22018 |
} |
--- |
| 22019 |
|
--- |
22019 |
|
--- |
| 22020 |
// The input is a ZeroExt or AnyExt. Check the original type. |
--- |
22020 |
// The input is a ZeroExt or AnyExt. Check the original type. |
--- |
| 22021 |
EVT InTy = In.getOperand(0).getValueType(); |
0 |
22021 |
EVT InTy = In.getOperand(0).getValueType(); |
0 |
| 22022 |
|
--- |
22022 |
|
--- |
| 22023 |
// Check that all of the widened source types are the same. |
--- |
22023 |
// Check that all of the widened source types are the same. |
--- |
| 22024 |
if (SourceType == MVT::Other) |
0 |
22024 |
if (SourceType == MVT::Other) |
0 |
| 22025 |
// First time. |
--- |
22025 |
// First time. |
--- |
| 22026 |
SourceType = InTy; |
0 |
22026 |
SourceType = InTy; |
0 |
| 22027 |
else if (InTy != SourceType) { |
0 |
22027 |
else if (InTy != SourceType) { |
0 |
| 22028 |
// Multiple income types. Abort. |
--- |
22028 |
// Multiple income types. Abort. |
--- |
| 22029 |
SourceType = MVT::Other; |
0 |
22029 |
SourceType = MVT::Other; |
0 |
| 22030 |
break; |
0 |
22030 |
break; |
0 |
| 22031 |
} |
--- |
22031 |
} |
--- |
| 22032 |
|
--- |
22032 |
|
--- |
| 22033 |
// Check if all of the extends are ANY_EXTENDs. |
--- |
22033 |
// Check if all of the extends are ANY_EXTENDs. |
--- |
| 22034 |
AllAnyExt &= AnyExt; |
0 |
22034 |
AllAnyExt &= AnyExt; |
0 |
| 22035 |
} |
--- |
22035 |
} |
--- |
| 22036 |
|
--- |
22036 |
|
--- |
| 22037 |
// In order to have valid types, all of the inputs must be extended from the |
--- |
22037 |
// In order to have valid types, all of the inputs must be extended from the |
--- |
| 22038 |
// same source type and all of the inputs must be any or zero extend. |
--- |
22038 |
// same source type and all of the inputs must be any or zero extend. |
--- |
| 22039 |
// Scalar sizes must be a power of two. |
--- |
22039 |
// Scalar sizes must be a power of two. |
--- |
| 22040 |
EVT OutScalarTy = VT.getScalarType(); |
0 |
22040 |
EVT OutScalarTy = VT.getScalarType(); |
0 |
| 22041 |
bool ValidTypes = |
--- |
22041 |
bool ValidTypes = |
--- |
| 22042 |
SourceType != MVT::Other && |
0 |
22042 |
SourceType != MVT::Other && |
0 |
| 22043 |
llvm::has_single_bit(OutScalarTy.getSizeInBits()) && |
0 |
22043 |
llvm::has_single_bit(OutScalarTy.getSizeInBits()) && |
0 |
| 22044 |
llvm::has_single_bit(SourceType.getSizeInBits()); |
0 |
22044 |
llvm::has_single_bit(SourceType.getSizeInBits()); |
0 |
| 22045 |
|
--- |
22045 |
|
--- |
| 22046 |
// Create a new simpler BUILD_VECTOR sequence which other optimizations can |
--- |
22046 |
// Create a new simpler BUILD_VECTOR sequence which other optimizations can |
--- |
| 22047 |
// turn into a single shuffle instruction. |
--- |
22047 |
// turn into a single shuffle instruction. |
--- |
| 22048 |
if (!ValidTypes) |
0 |
22048 |
if (!ValidTypes) |
0 |
| 22049 |
return SDValue(); |
0 |
22049 |
return SDValue(); |
0 |
| 22050 |
|
--- |
22050 |
|
--- |
| 22051 |
// If we already have a splat buildvector, then don't fold it if it means |
--- |
22051 |
// If we already have a splat buildvector, then don't fold it if it means |
--- |
| 22052 |
// introducing zeros. |
--- |
22052 |
// introducing zeros. |
--- |
| 22053 |
if (!AllAnyExt && DAG.isSplatValue(SDValue(N, 0), /*AllowUndefs*/ true)) |
0 |
22053 |
if (!AllAnyExt && DAG.isSplatValue(SDValue(N, 0), /*AllowUndefs*/ true)) |
0 |
| 22054 |
return SDValue(); |
0 |
22054 |
return SDValue(); |
0 |
| 22055 |
|
--- |
22055 |
|
--- |
| 22056 |
bool isLE = DAG.getDataLayout().isLittleEndian(); |
0 |
22056 |
bool isLE = DAG.getDataLayout().isLittleEndian(); |
0 |
| 22057 |
unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); |
0 |
22057 |
unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); |
0 |
| 22058 |
assert(ElemRatio > 1 && "Invalid element size ratio"); |
0 |
22058 |
assert(ElemRatio > 1 && "Invalid element size ratio"); |
0 |
| 22059 |
SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): |
0 |
22059 |
SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): |
0 |
| 22060 |
DAG.getConstant(0, DL, SourceType); |
0 |
22060 |
DAG.getConstant(0, DL, SourceType); |
0 |
| 22061 |
|
--- |
22061 |
|
--- |
| 22062 |
unsigned NewBVElems = ElemRatio * VT.getVectorNumElements(); |
0 |
22062 |
unsigned NewBVElems = ElemRatio * VT.getVectorNumElements(); |
0 |
| 22063 |
SmallVector Ops(NewBVElems, Filler); |
0 |
22063 |
SmallVector Ops(NewBVElems, Filler); |
0 |
| 22064 |
|
--- |
22064 |
|
--- |
| 22065 |
// Populate the new build_vector |
--- |
22065 |
// Populate the new build_vector |
--- |
| 22066 |
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { |
0 |
22066 |
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { |
0 |
| 22067 |
SDValue Cast = N->getOperand(i); |
0 |
22067 |
SDValue Cast = N->getOperand(i); |
0 |
| 22068 |
assert((Cast.getOpcode() == ISD::ANY_EXTEND || |
0 |
22068 |
assert((Cast.getOpcode() == ISD::ANY_EXTEND || |
0 |
| 22069 |
Cast.getOpcode() == ISD::ZERO_EXTEND || |
--- |
22069 |
Cast.getOpcode() == ISD::ZERO_EXTEND || |
--- |
| 22070 |
Cast.isUndef()) && "Invalid cast opcode"); |
--- |
22070 |
Cast.isUndef()) && "Invalid cast opcode"); |
--- |
| 22071 |
SDValue In; |
0 |
22071 |
SDValue In; |
0 |
| 22072 |
if (Cast.isUndef()) |
0 |
22072 |
if (Cast.isUndef()) |
0 |
| 22073 |
In = DAG.getUNDEF(SourceType); |
0 |
22073 |
In = DAG.getUNDEF(SourceType); |
0 |
| 22074 |
else |
--- |
22074 |
else |
--- |
| 22075 |
In = Cast->getOperand(0); |
0 |
22075 |
In = Cast->getOperand(0); |
0 |
| 22076 |
unsigned Index = isLE ? (i * ElemRatio) : |
0 |
22076 |
unsigned Index = isLE ? (i * ElemRatio) : |
0 |
| 22077 |
(i * ElemRatio + (ElemRatio - 1)); |
0 |
22077 |
(i * ElemRatio + (ElemRatio - 1)); |
0 |
| 22078 |
|
--- |
22078 |
|
--- |
| 22079 |
assert(Index < Ops.size() && "Invalid index"); |
0 |
22079 |
assert(Index < Ops.size() && "Invalid index"); |
0 |
| 22080 |
Ops[Index] = In; |
0 |
22080 |
Ops[Index] = In; |
0 |
| 22081 |
} |
--- |
22081 |
} |
--- |
| 22082 |
|
--- |
22082 |
|
--- |
| 22083 |
// The type of the new BUILD_VECTOR node. |
--- |
22083 |
// The type of the new BUILD_VECTOR node. |
--- |
| 22084 |
EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); |
0 |
22084 |
EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); |
0 |
| 22085 |
assert(VecVT.getSizeInBits() == VT.getSizeInBits() && |
0 |
22085 |
assert(VecVT.getSizeInBits() == VT.getSizeInBits() && |
0 |
| 22086 |
"Invalid vector size"); |
--- |
22086 |
"Invalid vector size"); |
--- |
| 22087 |
// Check if the new vector type is legal. |
--- |
22087 |
// Check if the new vector type is legal. |
--- |
| 22088 |
if (!isTypeLegal(VecVT) || |
0 |
22088 |
if (!isTypeLegal(VecVT) || |
0 |
| 22089 |
(!TLI.isOperationLegal(ISD::BUILD_VECTOR, VecVT) && |
0 |
22089 |
(!TLI.isOperationLegal(ISD::BUILD_VECTOR, VecVT) && |
0 |
| 22090 |
TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))) |
0 |
22090 |
TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))) |
0 |
| 22091 |
return SDValue(); |
0 |
22091 |
return SDValue(); |
0 |
| 22092 |
|
--- |
22092 |
|
--- |
| 22093 |
// Make the new BUILD_VECTOR. |
--- |
22093 |
// Make the new BUILD_VECTOR. |
--- |
| 22094 |
SDValue BV = DAG.getBuildVector(VecVT, DL, Ops); |
0 |
22094 |
SDValue BV = DAG.getBuildVector(VecVT, DL, Ops); |
0 |
| 22095 |
|
--- |
22095 |
|
--- |
| 22096 |
// The new BUILD_VECTOR node has the potential to be further optimized. |
--- |
22096 |
// The new BUILD_VECTOR node has the potential to be further optimized. |
--- |
| 22097 |
AddToWorklist(BV.getNode()); |
0 |
22097 |
AddToWorklist(BV.getNode()); |
0 |
| 22098 |
// Bitcast to the desired type. |
--- |
22098 |
// Bitcast to the desired type. |
--- |
| 22099 |
return DAG.getBitcast(VT, BV); |
0 |
22099 |
return DAG.getBitcast(VT, BV); |
0 |
| 22100 |
} |
0 |
22100 |
} |
0 |
| 22101 |
|
--- |
22101 |
|
--- |
| 22102 |
// Simplify (build_vec (trunc $1) |
--- |
22102 |
// Simplify (build_vec (trunc $1) |
--- |
| 22103 |
// (trunc (srl $1 half-width)) |
--- |
22103 |
// (trunc (srl $1 half-width)) |
--- |
| 22104 |
// (trunc (srl $1 (2 * half-width)))) |
--- |
22104 |
// (trunc (srl $1 (2 * half-width)))) |
--- |
| 22105 |
// to (bitcast $1) |
--- |
22105 |
// to (bitcast $1) |
--- |
| 22106 |
SDValue DAGCombiner::reduceBuildVecTruncToBitCast(SDNode *N) { |
0 |
22106 |
SDValue DAGCombiner::reduceBuildVecTruncToBitCast(SDNode *N) { |
0 |
| 22107 |
assert(N->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); |
0 |
22107 |
assert(N->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); |
0 |
| 22108 |
|
--- |
22108 |
|
--- |
| 22109 |
// Only for little endian |
--- |
22109 |
// Only for little endian |
--- |
| 22110 |
if (!DAG.getDataLayout().isLittleEndian()) |
0 |
22110 |
if (!DAG.getDataLayout().isLittleEndian()) |
0 |
| 22111 |
return SDValue(); |
0 |
22111 |
return SDValue(); |
0 |
| 22112 |
|
--- |
22112 |
|
--- |
| 22113 |
SDLoc DL(N); |
0 |
22113 |
SDLoc DL(N); |
0 |
| 22114 |
EVT VT = N->getValueType(0); |
0 |
22114 |
EVT VT = N->getValueType(0); |
0 |
| 22115 |
EVT OutScalarTy = VT.getScalarType(); |
0 |
22115 |
EVT OutScalarTy = VT.getScalarType(); |
0 |
| 22116 |
uint64_t ScalarTypeBitsize = OutScalarTy.getSizeInBits(); |
0 |
22116 |
uint64_t ScalarTypeBitsize = OutScalarTy.getSizeInBits(); |
0 |
| 22117 |
|
--- |
22117 |
|
--- |
| 22118 |
// Only for power of two types to be sure that bitcast works well |
--- |
22118 |
// Only for power of two types to be sure that bitcast works well |
--- |
| 22119 |
if (!isPowerOf2_64(ScalarTypeBitsize)) |
0 |
22119 |
if (!isPowerOf2_64(ScalarTypeBitsize)) |
0 |
| 22120 |
return SDValue(); |
0 |
22120 |
return SDValue(); |
0 |
| 22121 |
|
--- |
22121 |
|
--- |
| 22122 |
unsigned NumInScalars = N->getNumOperands(); |
0 |
22122 |
unsigned NumInScalars = N->getNumOperands(); |
0 |
| 22123 |
|
--- |
22123 |
|
--- |
| 22124 |
// Look through bitcasts |
--- |
22124 |
// Look through bitcasts |
--- |
| 22125 |
auto PeekThroughBitcast = [](SDValue Op) { |
0 |
22125 |
auto PeekThroughBitcast = [](SDValue Op) { |
0 |
| 22126 |
if (Op.getOpcode() == ISD::BITCAST) |
0 |
22126 |
if (Op.getOpcode() == ISD::BITCAST) |
0 |
| 22127 |
return Op.getOperand(0); |
0 |
22127 |
return Op.getOperand(0); |
0 |
| 22128 |
return Op; |
0 |
22128 |
return Op; |
0 |
| 22129 |
}; |
--- |
22129 |
}; |
--- |
| 22130 |
|
--- |
22130 |
|
--- |
| 22131 |
// The source value where all the parts are extracted. |
--- |
22131 |
// The source value where all the parts are extracted. |
--- |
| 22132 |
SDValue Src; |
0 |
22132 |
SDValue Src; |
0 |
| 22133 |
for (unsigned i = 0; i != NumInScalars; ++i) { |
0 |
22133 |
for (unsigned i = 0; i != NumInScalars; ++i) { |
0 |
| 22134 |
SDValue In = PeekThroughBitcast(N->getOperand(i)); |
0 |
22134 |
SDValue In = PeekThroughBitcast(N->getOperand(i)); |
0 |
| 22135 |
// Ignore undef inputs. |
--- |
22135 |
// Ignore undef inputs. |
--- |
| 22136 |
if (In.isUndef()) continue; |
0 |
22136 |
if (In.isUndef()) continue; |
0 |
| 22137 |
|
--- |
22137 |
|
--- |
| 22138 |
if (In.getOpcode() != ISD::TRUNCATE) |
0 |
22138 |
if (In.getOpcode() != ISD::TRUNCATE) |
0 |
| 22139 |
return SDValue(); |
0 |
22139 |
return SDValue(); |
0 |
| 22140 |
|
--- |
22140 |
|
--- |
| 22141 |
In = PeekThroughBitcast(In.getOperand(0)); |
0 |
22141 |
In = PeekThroughBitcast(In.getOperand(0)); |
0 |
| 22142 |
|
--- |
22142 |
|
--- |
| 22143 |
if (In.getOpcode() != ISD::SRL) { |
0 |
22143 |
if (In.getOpcode() != ISD::SRL) { |
0 |
| 22144 |
// For now only build_vec without shuffling, handle shifts here in the |
--- |
22144 |
// For now only build_vec without shuffling, handle shifts here in the |
--- |
| 22145 |
// future. |
--- |
22145 |
// future. |
--- |
| 22146 |
if (i != 0) |
0 |
22146 |
if (i != 0) |
0 |
| 22147 |
return SDValue(); |
0 |
22147 |
return SDValue(); |
0 |
| 22148 |
|
--- |
22148 |
|
--- |
| 22149 |
Src = In; |
0 |
22149 |
Src = In; |
0 |
| 22150 |
} else { |
--- |
22150 |
} else { |
--- |
| 22151 |
// In is SRL |
--- |
22151 |
// In is SRL |
--- |
| 22152 |
SDValue part = PeekThroughBitcast(In.getOperand(0)); |
0 |
22152 |
SDValue part = PeekThroughBitcast(In.getOperand(0)); |
0 |
| 22153 |
|
--- |
22153 |
|
--- |
| 22154 |
if (!Src) { |
0 |
22154 |
if (!Src) { |
0 |
| 22155 |
Src = part; |
0 |
22155 |
Src = part; |
0 |
| 22156 |
} else if (Src != part) { |
0 |
22156 |
} else if (Src != part) { |
0 |
| 22157 |
// Vector parts do not stem from the same variable |
--- |
22157 |
// Vector parts do not stem from the same variable |
--- |
| 22158 |
return SDValue(); |
0 |
22158 |
return SDValue(); |
0 |
| 22159 |
} |
--- |
22159 |
} |
--- |
| 22160 |
|
--- |
22160 |
|
--- |
| 22161 |
SDValue ShiftAmtVal = In.getOperand(1); |
0 |
22161 |
SDValue ShiftAmtVal = In.getOperand(1); |
0 |
| 22162 |
if (!isa(ShiftAmtVal)) |
0 |
22162 |
if (!isa(ShiftAmtVal)) |
0 |
| 22163 |
return SDValue(); |
0 |
22163 |
return SDValue(); |
0 |
| 22164 |
|
--- |
22164 |
|
--- |
| 22165 |
uint64_t ShiftAmt = In.getConstantOperandVal(1); |
0 |
22165 |
uint64_t ShiftAmt = In.getConstantOperandVal(1); |
0 |
| 22166 |
|
--- |
22166 |
|
--- |
| 22167 |
// The extracted value is not extracted at the right position |
--- |
22167 |
// The extracted value is not extracted at the right position |
--- |
| 22168 |
if (ShiftAmt != i * ScalarTypeBitsize) |
0 |
22168 |
if (ShiftAmt != i * ScalarTypeBitsize) |
0 |
| 22169 |
return SDValue(); |
0 |
22169 |
return SDValue(); |
0 |
| 22170 |
} |
--- |
22170 |
} |
--- |
| 22171 |
} |
--- |
22171 |
} |
--- |
| 22172 |
|
--- |
22172 |
|
--- |
| 22173 |
// Only cast if the size is the same |
--- |
22173 |
// Only cast if the size is the same |
--- |
| 22174 |
if (!Src || Src.getValueType().getSizeInBits() != VT.getSizeInBits()) |
0 |
22174 |
if (!Src || Src.getValueType().getSizeInBits() != VT.getSizeInBits()) |
0 |
| 22175 |
return SDValue(); |
0 |
22175 |
return SDValue(); |
0 |
| 22176 |
|
--- |
22176 |
|
--- |
| 22177 |
return DAG.getBitcast(VT, Src); |
0 |
22177 |
return DAG.getBitcast(VT, Src); |
0 |
| 22178 |
} |
0 |
22178 |
} |
0 |
| 22179 |
|
--- |
22179 |
|
--- |
| 22180 |
SDValue DAGCombiner::createBuildVecShuffle(const SDLoc &DL, SDNode *N, |
0 |
22180 |
SDValue DAGCombiner::createBuildVecShuffle(const SDLoc &DL, SDNode *N, |
0 |
| 22181 |
ArrayRef VectorMask, |
--- |
22181 |
ArrayRef VectorMask, |
--- |
| 22182 |
SDValue VecIn1, SDValue VecIn2, |
--- |
22182 |
SDValue VecIn1, SDValue VecIn2, |
--- |
| 22183 |
unsigned LeftIdx, bool DidSplitVec) { |
--- |
22183 |
unsigned LeftIdx, bool DidSplitVec) { |
--- |
| 22184 |
SDValue ZeroIdx = DAG.getVectorIdxConstant(0, DL); |
0 |
22184 |
SDValue ZeroIdx = DAG.getVectorIdxConstant(0, DL); |
0 |
| 22185 |
|
--- |
22185 |
|
--- |
| 22186 |
EVT VT = N->getValueType(0); |
0 |
22186 |
EVT VT = N->getValueType(0); |
0 |
| 22187 |
EVT InVT1 = VecIn1.getValueType(); |
0 |
22187 |
EVT InVT1 = VecIn1.getValueType(); |
0 |
| 22188 |
EVT InVT2 = VecIn2.getNode() ? VecIn2.getValueType() : InVT1; |
0 |
22188 |
EVT InVT2 = VecIn2.getNode() ? VecIn2.getValueType() : InVT1; |
0 |
| 22189 |
|
--- |
22189 |
|
--- |
| 22190 |
unsigned NumElems = VT.getVectorNumElements(); |
0 |
22190 |
unsigned NumElems = VT.getVectorNumElements(); |
0 |
| 22191 |
unsigned ShuffleNumElems = NumElems; |
0 |
22191 |
unsigned ShuffleNumElems = NumElems; |
0 |
| 22192 |
|
--- |
22192 |
|
--- |
| 22193 |
// If we artificially split a vector in two already, then the offsets in the |
--- |
22193 |
// If we artificially split a vector in two already, then the offsets in the |
--- |
| 22194 |
// operands will all be based off of VecIn1, even those in VecIn2. |
--- |
22194 |
// operands will all be based off of VecIn1, even those in VecIn2. |
--- |
| 22195 |
unsigned Vec2Offset = DidSplitVec ? 0 : InVT1.getVectorNumElements(); |
0 |
22195 |
unsigned Vec2Offset = DidSplitVec ? 0 : InVT1.getVectorNumElements(); |
0 |
| 22196 |
|
--- |
22196 |
|
--- |
| 22197 |
uint64_t VTSize = VT.getFixedSizeInBits(); |
0 |
22197 |
uint64_t VTSize = VT.getFixedSizeInBits(); |
0 |
| 22198 |
uint64_t InVT1Size = InVT1.getFixedSizeInBits(); |
0 |
22198 |
uint64_t InVT1Size = InVT1.getFixedSizeInBits(); |
0 |
| 22199 |
uint64_t InVT2Size = InVT2.getFixedSizeInBits(); |
0 |
22199 |
uint64_t InVT2Size = InVT2.getFixedSizeInBits(); |
0 |
| 22200 |
|
--- |
22200 |
|
--- |
| 22201 |
assert(InVT2Size <= InVT1Size && |
0 |
22201 |
assert(InVT2Size <= InVT1Size && |
0 |
| 22202 |
"Inputs must be sorted to be in non-increasing vector size order."); |
--- |
22202 |
"Inputs must be sorted to be in non-increasing vector size order."); |
--- |
| 22203 |
|
--- |
22203 |
|
--- |
| 22204 |
// We can't generate a shuffle node with mismatched input and output types. |
--- |
22204 |
// We can't generate a shuffle node with mismatched input and output types. |
--- |
| 22205 |
// Try to make the types match the type of the output. |
--- |
22205 |
// Try to make the types match the type of the output. |
--- |
| 22206 |
if (InVT1 != VT || InVT2 != VT) { |
0 |
22206 |
if (InVT1 != VT || InVT2 != VT) { |
0 |
| 22207 |
if ((VTSize % InVT1Size == 0) && InVT1 == InVT2) { |
0 |
22207 |
if ((VTSize % InVT1Size == 0) && InVT1 == InVT2) { |
0 |
| 22208 |
// If the output vector length is a multiple of both input lengths, |
--- |
22208 |
// If the output vector length is a multiple of both input lengths, |
--- |
| 22209 |
// we can concatenate them and pad the rest with undefs. |
--- |
22209 |
// we can concatenate them and pad the rest with undefs. |
--- |
| 22210 |
unsigned NumConcats = VTSize / InVT1Size; |
0 |
22210 |
unsigned NumConcats = VTSize / InVT1Size; |
0 |
| 22211 |
assert(NumConcats >= 2 && "Concat needs at least two inputs!"); |
0 |
22211 |
assert(NumConcats >= 2 && "Concat needs at least two inputs!"); |
0 |
| 22212 |
SmallVector ConcatOps(NumConcats, DAG.getUNDEF(InVT1)); |
0 |
22212 |
SmallVector ConcatOps(NumConcats, DAG.getUNDEF(InVT1)); |
0 |
| 22213 |
ConcatOps[0] = VecIn1; |
0 |
22213 |
ConcatOps[0] = VecIn1; |
0 |
| 22214 |
ConcatOps[1] = VecIn2 ? VecIn2 : DAG.getUNDEF(InVT1); |
0 |
22214 |
ConcatOps[1] = VecIn2 ? VecIn2 : DAG.getUNDEF(InVT1); |
0 |
| 22215 |
VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps); |
0 |
22215 |
VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps); |
0 |
| 22216 |
VecIn2 = SDValue(); |
0 |
22216 |
VecIn2 = SDValue(); |
0 |
| 22217 |
} else if (InVT1Size == VTSize * 2) { |
0 |
22217 |
} else if (InVT1Size == VTSize * 2) { |
0 |
| 22218 |
if (!TLI.isExtractSubvectorCheap(VT, InVT1, NumElems)) |
0 |
22218 |
if (!TLI.isExtractSubvectorCheap(VT, InVT1, NumElems)) |
0 |
| 22219 |
return SDValue(); |
0 |
22219 |
return SDValue(); |
0 |
| 22220 |
|
--- |
22220 |
|
--- |
| 22221 |
if (!VecIn2.getNode()) { |
0 |
22221 |
if (!VecIn2.getNode()) { |
0 |
| 22222 |
// If we only have one input vector, and it's twice the size of the |
--- |
22222 |
// If we only have one input vector, and it's twice the size of the |
--- |
| 22223 |
// output, split it in two. |
--- |
22223 |
// output, split it in two. |
--- |
| 22224 |
VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, VecIn1, |
0 |
22224 |
VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, VecIn1, |
0 |
| 22225 |
DAG.getVectorIdxConstant(NumElems, DL)); |
0 |
22225 |
DAG.getVectorIdxConstant(NumElems, DL)); |
0 |
| 22226 |
VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, VecIn1, ZeroIdx); |
0 |
22226 |
VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, VecIn1, ZeroIdx); |
0 |
| 22227 |
// Since we now have shorter input vectors, adjust the offset of the |
--- |
22227 |
// Since we now have shorter input vectors, adjust the offset of the |
--- |
| 22228 |
// second vector's start. |
--- |
22228 |
// second vector's start. |
--- |
| 22229 |
Vec2Offset = NumElems; |
0 |
22229 |
Vec2Offset = NumElems; |
0 |
| 22230 |
} else { |
--- |
22230 |
} else { |
--- |
| 22231 |
assert(InVT2Size <= InVT1Size && |
0 |
22231 |
assert(InVT2Size <= InVT1Size && |
0 |
| 22232 |
"Second input is not going to be larger than the first one."); |
--- |
22232 |
"Second input is not going to be larger than the first one."); |
--- |
| 22233 |
|
--- |
22233 |
|
--- |
| 22234 |
// VecIn1 is wider than the output, and we have another, possibly |
--- |
22234 |
// VecIn1 is wider than the output, and we have another, possibly |
--- |
| 22235 |
// smaller input. Pad the smaller input with undefs, shuffle at the |
--- |
22235 |
// smaller input. Pad the smaller input with undefs, shuffle at the |
--- |
| 22236 |
// input vector width, and extract the output. |
--- |
22236 |
// input vector width, and extract the output. |
--- |
| 22237 |
// The shuffle type is different than VT, so check legality again. |
--- |
22237 |
// The shuffle type is different than VT, so check legality again. |
--- |
| 22238 |
if (LegalOperations && |
0 |
22238 |
if (LegalOperations && |
0 |
| 22239 |
!TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1)) |
0 |
22239 |
!TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1)) |
0 |
| 22240 |
return SDValue(); |
0 |
22240 |
return SDValue(); |
0 |
| 22241 |
|
--- |
22241 |
|
--- |
| 22242 |
// Legalizing INSERT_SUBVECTOR is tricky - you basically have to |
--- |
22242 |
// Legalizing INSERT_SUBVECTOR is tricky - you basically have to |
--- |
| 22243 |
// lower it back into a BUILD_VECTOR. So if the inserted type is |
--- |
22243 |
// lower it back into a BUILD_VECTOR. So if the inserted type is |
--- |
| 22244 |
// illegal, don't even try. |
--- |
22244 |
// illegal, don't even try. |
--- |
| 22245 |
if (InVT1 != InVT2) { |
0 |
22245 |
if (InVT1 != InVT2) { |
0 |
| 22246 |
if (!TLI.isTypeLegal(InVT2)) |
0 |
22246 |
if (!TLI.isTypeLegal(InVT2)) |
0 |
| 22247 |
return SDValue(); |
0 |
22247 |
return SDValue(); |
0 |
| 22248 |
VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, |
0 |
22248 |
VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, |
0 |
| 22249 |
DAG.getUNDEF(InVT1), VecIn2, ZeroIdx); |
0 |
22249 |
DAG.getUNDEF(InVT1), VecIn2, ZeroIdx); |
0 |
| 22250 |
} |
--- |
22250 |
} |
--- |
| 22251 |
ShuffleNumElems = NumElems * 2; |
0 |
22251 |
ShuffleNumElems = NumElems * 2; |
0 |
| 22252 |
} |
--- |
22252 |
} |
--- |
| 22253 |
} else if (InVT2Size * 2 == VTSize && InVT1Size == VTSize) { |
0 |
22253 |
} else if (InVT2Size * 2 == VTSize && InVT1Size == VTSize) { |
0 |
| 22254 |
SmallVector ConcatOps(2, DAG.getUNDEF(InVT2)); |
0 |
22254 |
SmallVector ConcatOps(2, DAG.getUNDEF(InVT2)); |
0 |
| 22255 |
ConcatOps[0] = VecIn2; |
0 |
22255 |
ConcatOps[0] = VecIn2; |
0 |
| 22256 |
VecIn2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps); |
0 |
22256 |
VecIn2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps); |
0 |
| 22257 |
} else if (InVT1Size / VTSize > 1 && InVT1Size % VTSize == 0) { |
0 |
22257 |
} else if (InVT1Size / VTSize > 1 && InVT1Size % VTSize == 0) { |
0 |
| 22258 |
if (!TLI.isExtractSubvectorCheap(VT, InVT1, NumElems) || |
0 |
22258 |
if (!TLI.isExtractSubvectorCheap(VT, InVT1, NumElems) || |
0 |
| 22259 |
!TLI.isTypeLegal(InVT1) || !TLI.isTypeLegal(InVT2)) |
0 |
22259 |
!TLI.isTypeLegal(InVT1) || !TLI.isTypeLegal(InVT2)) |
0 |
| 22260 |
return SDValue(); |
0 |
22260 |
return SDValue(); |
0 |
| 22261 |
// If dest vector has less than two elements, then use shuffle and extract |
--- |
22261 |
// If dest vector has less than two elements, then use shuffle and extract |
--- |
| 22262 |
// from larger regs will cost even more. |
--- |
22262 |
// from larger regs will cost even more. |
--- |
| 22263 |
if (VT.getVectorNumElements() <= 2 || !VecIn2.getNode()) |
0 |
22263 |
if (VT.getVectorNumElements() <= 2 || !VecIn2.getNode()) |
0 |
| 22264 |
return SDValue(); |
0 |
22264 |
return SDValue(); |
0 |
| 22265 |
assert(InVT2Size <= InVT1Size && |
0 |
22265 |
assert(InVT2Size <= InVT1Size && |
0 |
| 22266 |
"Second input is not going to be larger than the first one."); |
--- |
22266 |
"Second input is not going to be larger than the first one."); |
--- |
| 22267 |
|
--- |
22267 |
|
--- |
| 22268 |
// VecIn1 is wider than the output, and we have another, possibly |
--- |
22268 |
// VecIn1 is wider than the output, and we have another, possibly |
--- |
| 22269 |
// smaller input. Pad the smaller input with undefs, shuffle at the |
--- |
22269 |
// smaller input. Pad the smaller input with undefs, shuffle at the |
--- |
| 22270 |
// input vector width, and extract the output. |
--- |
22270 |
// input vector width, and extract the output. |
--- |
| 22271 |
// The shuffle type is different than VT, so check legality again. |
--- |
22271 |
// The shuffle type is different than VT, so check legality again. |
--- |
| 22272 |
if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1)) |
0 |
22272 |
if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1)) |
0 |
| 22273 |
return SDValue(); |
0 |
22273 |
return SDValue(); |
0 |
| 22274 |
|
--- |
22274 |
|
--- |
| 22275 |
if (InVT1 != InVT2) { |
0 |
22275 |
if (InVT1 != InVT2) { |
0 |
| 22276 |
VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, |
0 |
22276 |
VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, |
0 |
| 22277 |
DAG.getUNDEF(InVT1), VecIn2, ZeroIdx); |
0 |
22277 |
DAG.getUNDEF(InVT1), VecIn2, ZeroIdx); |
0 |
| 22278 |
} |
--- |
22278 |
} |
--- |
| 22279 |
ShuffleNumElems = InVT1Size / VTSize * NumElems; |
0 |
22279 |
ShuffleNumElems = InVT1Size / VTSize * NumElems; |
0 |
| 22280 |
} else { |
--- |
22280 |
} else { |
--- |
| 22281 |
// TODO: Support cases where the length mismatch isn't exactly by a |
--- |
22281 |
// TODO: Support cases where the length mismatch isn't exactly by a |
--- |
| 22282 |
// factor of 2. |
--- |
22282 |
// factor of 2. |
--- |
| 22283 |
// TODO: Move this check upwards, so that if we have bad type |
--- |
22283 |
// TODO: Move this check upwards, so that if we have bad type |
--- |
| 22284 |
// mismatches, we don't create any DAG nodes. |
--- |
22284 |
// mismatches, we don't create any DAG nodes. |
--- |
| 22285 |
return SDValue(); |
0 |
22285 |
return SDValue(); |
0 |
| 22286 |
} |
--- |
22286 |
} |
--- |
| 22287 |
} |
--- |
22287 |
} |
--- |
| 22288 |
|
--- |
22288 |
|
--- |
| 22289 |
// Initialize mask to undef. |
--- |
22289 |
// Initialize mask to undef. |
--- |
| 22290 |
SmallVector Mask(ShuffleNumElems, -1); |
0 |
22290 |
SmallVector Mask(ShuffleNumElems, -1); |
0 |
| 22291 |
|
--- |
22291 |
|
--- |
| 22292 |
// Only need to run up to the number of elements actually used, not the |
--- |
22292 |
// Only need to run up to the number of elements actually used, not the |
--- |
| 22293 |
// total number of elements in the shuffle - if we are shuffling a wider |
--- |
22293 |
// total number of elements in the shuffle - if we are shuffling a wider |
--- |
| 22294 |
// vector, the high lanes should be set to undef. |
--- |
22294 |
// vector, the high lanes should be set to undef. |
--- |
| 22295 |
for (unsigned i = 0; i != NumElems; ++i) { |
0 |
22295 |
for (unsigned i = 0; i != NumElems; ++i) { |
0 |
| 22296 |
if (VectorMask[i] <= 0) |
0 |
22296 |
if (VectorMask[i] <= 0) |
0 |
| 22297 |
continue; |
0 |
22297 |
continue; |
0 |
| 22298 |
|
--- |
22298 |
|
--- |
| 22299 |
unsigned ExtIndex = N->getOperand(i).getConstantOperandVal(1); |
0 |
22299 |
unsigned ExtIndex = N->getOperand(i).getConstantOperandVal(1); |
0 |
| 22300 |
if (VectorMask[i] == (int)LeftIdx) { |
0 |
22300 |
if (VectorMask[i] == (int)LeftIdx) { |
0 |
| 22301 |
Mask[i] = ExtIndex; |
0 |
22301 |
Mask[i] = ExtIndex; |
0 |
| 22302 |
} else if (VectorMask[i] == (int)LeftIdx + 1) { |
0 |
22302 |
} else if (VectorMask[i] == (int)LeftIdx + 1) { |
0 |
| 22303 |
Mask[i] = Vec2Offset + ExtIndex; |
0 |
22303 |
Mask[i] = Vec2Offset + ExtIndex; |
0 |
| 22304 |
} |
--- |
22304 |
} |
--- |
| 22305 |
} |
--- |
22305 |
} |
--- |
| 22306 |
|
--- |
22306 |
|
--- |
| 22307 |
// The type the input vectors may have changed above. |
--- |
22307 |
// The type the input vectors may have changed above. |
--- |
| 22308 |
InVT1 = VecIn1.getValueType(); |
0 |
22308 |
InVT1 = VecIn1.getValueType(); |
0 |
| 22309 |
|
--- |
22309 |
|
--- |
| 22310 |
// If we already have a VecIn2, it should have the same type as VecIn1. |
--- |
22310 |
// If we already have a VecIn2, it should have the same type as VecIn1. |
--- |
| 22311 |
// If we don't, get an undef/zero vector of the appropriate type. |
--- |
22311 |
// If we don't, get an undef/zero vector of the appropriate type. |
--- |
| 22312 |
VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(InVT1); |
0 |
22312 |
VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(InVT1); |
0 |
| 22313 |
assert(InVT1 == VecIn2.getValueType() && "Unexpected second input type."); |
0 |
22313 |
assert(InVT1 == VecIn2.getValueType() && "Unexpected second input type."); |
0 |
| 22314 |
|
--- |
22314 |
|
--- |
| 22315 |
SDValue Shuffle = DAG.getVectorShuffle(InVT1, DL, VecIn1, VecIn2, Mask); |
0 |
22315 |
SDValue Shuffle = DAG.getVectorShuffle(InVT1, DL, VecIn1, VecIn2, Mask); |
0 |
| 22316 |
if (ShuffleNumElems > NumElems) |
0 |
22316 |
if (ShuffleNumElems > NumElems) |
0 |
| 22317 |
Shuffle = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Shuffle, ZeroIdx); |
0 |
22317 |
Shuffle = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Shuffle, ZeroIdx); |
0 |
| 22318 |
|
--- |
22318 |
|
--- |
| 22319 |
return Shuffle; |
0 |
22319 |
return Shuffle; |
0 |
| 22320 |
} |
0 |
22320 |
} |
0 |
| 22321 |
|
--- |
22321 |
|
--- |
| 22322 |
static SDValue reduceBuildVecToShuffleWithZero(SDNode *BV, SelectionDAG &DAG) { |
0 |
22322 |
static SDValue reduceBuildVecToShuffleWithZero(SDNode *BV, SelectionDAG &DAG) { |
0 |
| 22323 |
assert(BV->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); |
0 |
22323 |
assert(BV->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector"); |
0 |
| 22324 |
|
--- |
22324 |
|
--- |
| 22325 |
// First, determine where the build vector is not undef. |
--- |
22325 |
// First, determine where the build vector is not undef. |
--- |
| 22326 |
// TODO: We could extend this to handle zero elements as well as undefs. |
--- |
22326 |
// TODO: We could extend this to handle zero elements as well as undefs. |
--- |
| 22327 |
int NumBVOps = BV->getNumOperands(); |
0 |
22327 |
int NumBVOps = BV->getNumOperands(); |
0 |
| 22328 |
int ZextElt = -1; |
0 |
22328 |
int ZextElt = -1; |
0 |
| 22329 |
for (int i = 0; i != NumBVOps; ++i) { |
0 |
22329 |
for (int i = 0; i != NumBVOps; ++i) { |
0 |
| 22330 |
SDValue Op = BV->getOperand(i); |
0 |
22330 |
SDValue Op = BV->getOperand(i); |
0 |
| 22331 |
if (Op.isUndef()) |
0 |
22331 |
if (Op.isUndef()) |
0 |
| 22332 |
continue; |
0 |
22332 |
continue; |
0 |
| 22333 |
if (ZextElt == -1) |
0 |
22333 |
if (ZextElt == -1) |
0 |
| 22334 |
ZextElt = i; |
0 |
22334 |
ZextElt = i; |
0 |
| 22335 |
else |
--- |
22335 |
else |
--- |
| 22336 |
return SDValue(); |
0 |
22336 |
return SDValue(); |
0 |
| 22337 |
} |
--- |
22337 |
} |
--- |
| 22338 |
// Bail out if there's no non-undef element. |
--- |
22338 |
// Bail out if there's no non-undef element. |
--- |
| 22339 |
if (ZextElt == -1) |
0 |
22339 |
if (ZextElt == -1) |
0 |
| 22340 |
return SDValue(); |
0 |
22340 |
return SDValue(); |
0 |
| 22341 |
|
--- |
22341 |
|
--- |
| 22342 |
// The build vector contains some number of undef elements and exactly |
--- |
22342 |
// The build vector contains some number of undef elements and exactly |
--- |
| 22343 |
// one other element. That other element must be a zero-extended scalar |
--- |
22343 |
// one other element. That other element must be a zero-extended scalar |
--- |
| 22344 |
// extracted from a vector at a constant index to turn this into a shuffle. |
--- |
22344 |
// extracted from a vector at a constant index to turn this into a shuffle. |
--- |
| 22345 |
// Also, require that the build vector does not implicitly truncate/extend |
--- |
22345 |
// Also, require that the build vector does not implicitly truncate/extend |
--- |
| 22346 |
// its elements. |
--- |
22346 |
// its elements. |
--- |
| 22347 |
// TODO: This could be enhanced to allow ANY_EXTEND as well as ZERO_EXTEND. |
--- |
22347 |
// TODO: This could be enhanced to allow ANY_EXTEND as well as ZERO_EXTEND. |
--- |
| 22348 |
EVT VT = BV->getValueType(0); |
0 |
22348 |
EVT VT = BV->getValueType(0); |
0 |
| 22349 |
SDValue Zext = BV->getOperand(ZextElt); |
0 |
22349 |
SDValue Zext = BV->getOperand(ZextElt); |
0 |
| 22350 |
if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() || |
0 |
22350 |
if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() || |
0 |
| 22351 |
Zext.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT || |
0 |
22351 |
Zext.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT || |
0 |
| 22352 |
!isa(Zext.getOperand(0).getOperand(1)) || |
0 |
22352 |
!isa(Zext.getOperand(0).getOperand(1)) || |
0 |
| 22353 |
Zext.getValueSizeInBits() != VT.getScalarSizeInBits()) |
0 |
22353 |
Zext.getValueSizeInBits() != VT.getScalarSizeInBits()) |
0 |
| 22354 |
return SDValue(); |
0 |
22354 |
return SDValue(); |
0 |
| 22355 |
|
--- |
22355 |
|
--- |
| 22356 |
// The zero-extend must be a multiple of the source size, and we must be |
--- |
22356 |
// The zero-extend must be a multiple of the source size, and we must be |
--- |
| 22357 |
// building a vector of the same size as the source of the extract element. |
--- |
22357 |
// building a vector of the same size as the source of the extract element. |
--- |
| 22358 |
SDValue Extract = Zext.getOperand(0); |
0 |
22358 |
SDValue Extract = Zext.getOperand(0); |
0 |
| 22359 |
unsigned DestSize = Zext.getValueSizeInBits(); |
0 |
22359 |
unsigned DestSize = Zext.getValueSizeInBits(); |
0 |
| 22360 |
unsigned SrcSize = Extract.getValueSizeInBits(); |
0 |
22360 |
unsigned SrcSize = Extract.getValueSizeInBits(); |
0 |
| 22361 |
if (DestSize % SrcSize != 0 || |
0 |
22361 |
if (DestSize % SrcSize != 0 || |
0 |
| 22362 |
Extract.getOperand(0).getValueSizeInBits() != VT.getSizeInBits()) |
0 |
22362 |
Extract.getOperand(0).getValueSizeInBits() != VT.getSizeInBits()) |
0 |
| 22363 |
return SDValue(); |
0 |
22363 |
return SDValue(); |
0 |
| 22364 |
|
--- |
22364 |
|
--- |
| 22365 |
// Create a shuffle mask that will combine the extracted element with zeros |
--- |
22365 |
// Create a shuffle mask that will combine the extracted element with zeros |
--- |
| 22366 |
// and undefs. |
--- |
22366 |
// and undefs. |
--- |
| 22367 |
int ZextRatio = DestSize / SrcSize; |
0 |
22367 |
int ZextRatio = DestSize / SrcSize; |
0 |
| 22368 |
int NumMaskElts = NumBVOps * ZextRatio; |
0 |
22368 |
int NumMaskElts = NumBVOps * ZextRatio; |
0 |
| 22369 |
SmallVector ShufMask(NumMaskElts, -1); |
0 |
22369 |
SmallVector ShufMask(NumMaskElts, -1); |
0 |
| 22370 |
for (int i = 0; i != NumMaskElts; ++i) { |
0 |
22370 |
for (int i = 0; i != NumMaskElts; ++i) { |
0 |
| 22371 |
if (i / ZextRatio == ZextElt) { |
0 |
22371 |
if (i / ZextRatio == ZextElt) { |
0 |
| 22372 |
// The low bits of the (potentially translated) extracted element map to |
--- |
22372 |
// The low bits of the (potentially translated) extracted element map to |
--- |
| 22373 |
// the source vector. The high bits map to zero. We will use a zero vector |
--- |
22373 |
// the source vector. The high bits map to zero. We will use a zero vector |
--- |
| 22374 |
// as the 2nd source operand of the shuffle, so use the 1st element of |
--- |
22374 |
// as the 2nd source operand of the shuffle, so use the 1st element of |
--- |
| 22375 |
// that vector (mask value is number-of-elements) for the high bits. |
--- |
22375 |
// that vector (mask value is number-of-elements) for the high bits. |
--- |
| 22376 |
int Low = DAG.getDataLayout().isBigEndian() ? (ZextRatio - 1) : 0; |
0 |
22376 |
int Low = DAG.getDataLayout().isBigEndian() ? (ZextRatio - 1) : 0; |
0 |
| 22377 |
ShufMask[i] = (i % ZextRatio == Low) ? Extract.getConstantOperandVal(1) |
0 |
22377 |
ShufMask[i] = (i % ZextRatio == Low) ? Extract.getConstantOperandVal(1) |
0 |
| 22378 |
: NumMaskElts; |
--- |
22378 |
: NumMaskElts; |
--- |
| 22379 |
} |
--- |
22379 |
} |
--- |
| 22380 |
|
--- |
22380 |
|
--- |
| 22381 |
// Undef elements of the build vector remain undef because we initialize |
--- |
22381 |
// Undef elements of the build vector remain undef because we initialize |
--- |
| 22382 |
// the shuffle mask with -1. |
--- |
22382 |
// the shuffle mask with -1. |
--- |
| 22383 |
} |
--- |
22383 |
} |
--- |
| 22384 |
|
--- |
22384 |
|
--- |
| 22385 |
// buildvec undef, ..., (zext (extractelt V, IndexC)), undef... --> |
--- |
22385 |
// buildvec undef, ..., (zext (extractelt V, IndexC)), undef... --> |
--- |
| 22386 |
// bitcast (shuffle V, ZeroVec, VectorMask) |
--- |
22386 |
// bitcast (shuffle V, ZeroVec, VectorMask) |
--- |
| 22387 |
SDLoc DL(BV); |
0 |
22387 |
SDLoc DL(BV); |
0 |
| 22388 |
EVT VecVT = Extract.getOperand(0).getValueType(); |
0 |
22388 |
EVT VecVT = Extract.getOperand(0).getValueType(); |
0 |
| 22389 |
SDValue ZeroVec = DAG.getConstant(0, DL, VecVT); |
0 |
22389 |
SDValue ZeroVec = DAG.getConstant(0, DL, VecVT); |
0 |
| 22390 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
22390 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 22391 |
SDValue Shuf = TLI.buildLegalVectorShuffle(VecVT, DL, Extract.getOperand(0), |
0 |
22391 |
SDValue Shuf = TLI.buildLegalVectorShuffle(VecVT, DL, Extract.getOperand(0), |
0 |
| 22392 |
ZeroVec, ShufMask, DAG); |
--- |
22392 |
ZeroVec, ShufMask, DAG); |
--- |
| 22393 |
if (!Shuf) |
0 |
22393 |
if (!Shuf) |
0 |
| 22394 |
return SDValue(); |
0 |
22394 |
return SDValue(); |
0 |
| 22395 |
return DAG.getBitcast(VT, Shuf); |
0 |
22395 |
return DAG.getBitcast(VT, Shuf); |
0 |
| 22396 |
} |
0 |
22396 |
} |
0 |
| 22397 |
|
--- |
22397 |
|
--- |
| 22398 |
// FIXME: promote to STLExtras. |
--- |
22398 |
// FIXME: promote to STLExtras. |
--- |
| 22399 |
template |
--- |
22399 |
template |
--- |
| 22400 |
static auto getFirstIndexOf(R &&Range, const T &Val) { |
0 |
22400 |
static auto getFirstIndexOf(R &&Range, const T &Val) { |
0 |
| 22401 |
auto I = find(Range, Val); |
0 |
22401 |
auto I = find(Range, Val); |
0 |
| 22402 |
if (I == Range.end()) |
0 |
22402 |
if (I == Range.end()) |
0 |
| 22403 |
return static_cast(-1); |
0 |
22403 |
return static_cast(-1); |
0 |
| 22404 |
return std::distance(Range.begin(), I); |
0 |
22404 |
return std::distance(Range.begin(), I); |
0 |
| 22405 |
} |
--- |
22405 |
} |
--- |
| 22406 |
|
--- |
22406 |
|
--- |
| 22407 |
// Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT |
--- |
22407 |
// Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT |
--- |
| 22408 |
// operations. If the types of the vectors we're extracting from allow it, |
--- |
22408 |
// operations. If the types of the vectors we're extracting from allow it, |
--- |
| 22409 |
// turn this into a vector_shuffle node. |
--- |
22409 |
// turn this into a vector_shuffle node. |
--- |
| 22410 |
SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) { |
0 |
22410 |
SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) { |
0 |
| 22411 |
SDLoc DL(N); |
0 |
22411 |
SDLoc DL(N); |
0 |
| 22412 |
EVT VT = N->getValueType(0); |
0 |
22412 |
EVT VT = N->getValueType(0); |
0 |
| 22413 |
|
--- |
22413 |
|
--- |
| 22414 |
// Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. |
--- |
22414 |
// Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. |
--- |
| 22415 |
if (!isTypeLegal(VT)) |
0 |
22415 |
if (!isTypeLegal(VT)) |
0 |
| 22416 |
return SDValue(); |
0 |
22416 |
return SDValue(); |
0 |
| 22417 |
|
--- |
22417 |
|
--- |
| 22418 |
if (SDValue V = reduceBuildVecToShuffleWithZero(N, DAG)) |
0 |
22418 |
if (SDValue V = reduceBuildVecToShuffleWithZero(N, DAG)) |
0 |
| 22419 |
return V; |
0 |
22419 |
return V; |
0 |
| 22420 |
|
--- |
22420 |
|
--- |
| 22421 |
// May only combine to shuffle after legalize if shuffle is legal. |
--- |
22421 |
// May only combine to shuffle after legalize if shuffle is legal. |
--- |
| 22422 |
if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT)) |
0 |
22422 |
if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT)) |
0 |
| 22423 |
return SDValue(); |
0 |
22423 |
return SDValue(); |
0 |
| 22424 |
|
--- |
22424 |
|
--- |
| 22425 |
bool UsesZeroVector = false; |
0 |
22425 |
bool UsesZeroVector = false; |
0 |
| 22426 |
unsigned NumElems = N->getNumOperands(); |
0 |
22426 |
unsigned NumElems = N->getNumOperands(); |
0 |
| 22427 |
|
--- |
22427 |
|
--- |
| 22428 |
// Record, for each element of the newly built vector, which input vector |
--- |
22428 |
// Record, for each element of the newly built vector, which input vector |
--- |
| 22429 |
// that element comes from. -1 stands for undef, 0 for the zero vector, |
--- |
22429 |
// that element comes from. -1 stands for undef, 0 for the zero vector, |
--- |
| 22430 |
// and positive values for the input vectors. |
--- |
22430 |
// and positive values for the input vectors. |
--- |
| 22431 |
// VectorMask maps each element to its vector number, and VecIn maps vector |
--- |
22431 |
// VectorMask maps each element to its vector number, and VecIn maps vector |
--- |
| 22432 |
// numbers to their initial SDValues. |
--- |
22432 |
// numbers to their initial SDValues. |
--- |
| 22433 |
|
--- |
22433 |
|
--- |
| 22434 |
SmallVector VectorMask(NumElems, -1); |
0 |
22434 |
SmallVector VectorMask(NumElems, -1); |
0 |
| 22435 |
SmallVector VecIn; |
0 |
22435 |
SmallVector VecIn; |
0 |
| 22436 |
VecIn.push_back(SDValue()); |
0 |
22436 |
VecIn.push_back(SDValue()); |
0 |
| 22437 |
|
--- |
22437 |
|
--- |
| 22438 |
for (unsigned i = 0; i != NumElems; ++i) { |
0 |
22438 |
for (unsigned i = 0; i != NumElems; ++i) { |
0 |
| 22439 |
SDValue Op = N->getOperand(i); |
0 |
22439 |
SDValue Op = N->getOperand(i); |
0 |
| 22440 |
|
--- |
22440 |
|
--- |
| 22441 |
if (Op.isUndef()) |
0 |
22441 |
if (Op.isUndef()) |
0 |
| 22442 |
continue; |
0 |
22442 |
continue; |
0 |
| 22443 |
|
--- |
22443 |
|
--- |
| 22444 |
// See if we can use a blend with a zero vector. |
--- |
22444 |
// See if we can use a blend with a zero vector. |
--- |
| 22445 |
// TODO: Should we generalize this to a blend with an arbitrary constant |
--- |
22445 |
// TODO: Should we generalize this to a blend with an arbitrary constant |
--- |
| 22446 |
// vector? |
--- |
22446 |
// vector? |
--- |
| 22447 |
if (isNullConstant(Op) || isNullFPConstant(Op)) { |
0 |
22447 |
if (isNullConstant(Op) || isNullFPConstant(Op)) { |
0 |
| 22448 |
UsesZeroVector = true; |
0 |
22448 |
UsesZeroVector = true; |
0 |
| 22449 |
VectorMask[i] = 0; |
0 |
22449 |
VectorMask[i] = 0; |
0 |
| 22450 |
continue; |
0 |
22450 |
continue; |
0 |
| 22451 |
} |
--- |
22451 |
} |
--- |
| 22452 |
|
--- |
22452 |
|
--- |
| 22453 |
// Not an undef or zero. If the input is something other than an |
--- |
22453 |
// Not an undef or zero. If the input is something other than an |
--- |
| 22454 |
// EXTRACT_VECTOR_ELT with an in-range constant index, bail out. |
--- |
22454 |
// EXTRACT_VECTOR_ELT with an in-range constant index, bail out. |
--- |
| 22455 |
if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || |
0 |
22455 |
if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || |
0 |
| 22456 |
!isa(Op.getOperand(1))) |
0 |
22456 |
!isa(Op.getOperand(1))) |
0 |
| 22457 |
return SDValue(); |
0 |
22457 |
return SDValue(); |
0 |
| 22458 |
SDValue ExtractedFromVec = Op.getOperand(0); |
0 |
22458 |
SDValue ExtractedFromVec = Op.getOperand(0); |
0 |
| 22459 |
|
--- |
22459 |
|
--- |
| 22460 |
if (ExtractedFromVec.getValueType().isScalableVector()) |
0 |
22460 |
if (ExtractedFromVec.getValueType().isScalableVector()) |
0 |
| 22461 |
return SDValue(); |
0 |
22461 |
return SDValue(); |
0 |
| 22462 |
|
--- |
22462 |
|
--- |
| 22463 |
const APInt &ExtractIdx = Op.getConstantOperandAPInt(1); |
0 |
22463 |
const APInt &ExtractIdx = Op.getConstantOperandAPInt(1); |
0 |
| 22464 |
if (ExtractIdx.uge(ExtractedFromVec.getValueType().getVectorNumElements())) |
0 |
22464 |
if (ExtractIdx.uge(ExtractedFromVec.getValueType().getVectorNumElements())) |
0 |
| 22465 |
return SDValue(); |
0 |
22465 |
return SDValue(); |
0 |
| 22466 |
|
--- |
22466 |
|
--- |
| 22467 |
// All inputs must have the same element type as the output. |
--- |
22467 |
// All inputs must have the same element type as the output. |
--- |
| 22468 |
if (VT.getVectorElementType() != |
0 |
22468 |
if (VT.getVectorElementType() != |
0 |
| 22469 |
ExtractedFromVec.getValueType().getVectorElementType()) |
0 |
22469 |
ExtractedFromVec.getValueType().getVectorElementType()) |
0 |
| 22470 |
return SDValue(); |
0 |
22470 |
return SDValue(); |
0 |
| 22471 |
|
--- |
22471 |
|
--- |
| 22472 |
// Have we seen this input vector before? |
--- |
22472 |
// Have we seen this input vector before? |
--- |
| 22473 |
// The vectors are expected to be tiny (usually 1 or 2 elements), so using |
--- |
22473 |
// The vectors are expected to be tiny (usually 1 or 2 elements), so using |
--- |
| 22474 |
// a map back from SDValues to numbers isn't worth it. |
--- |
22474 |
// a map back from SDValues to numbers isn't worth it. |
--- |
| 22475 |
int Idx = getFirstIndexOf(VecIn, ExtractedFromVec); |
0 |
22475 |
int Idx = getFirstIndexOf(VecIn, ExtractedFromVec); |
0 |
| 22476 |
if (Idx == -1) { // A new source vector? |
0 |
22476 |
if (Idx == -1) { // A new source vector? |
0 |
| 22477 |
Idx = VecIn.size(); |
0 |
22477 |
Idx = VecIn.size(); |
0 |
| 22478 |
VecIn.push_back(ExtractedFromVec); |
0 |
22478 |
VecIn.push_back(ExtractedFromVec); |
0 |
| 22479 |
} |
--- |
22479 |
} |
--- |
| 22480 |
|
--- |
22480 |
|
--- |
| 22481 |
VectorMask[i] = Idx; |
0 |
22481 |
VectorMask[i] = Idx; |
0 |
| 22482 |
} |
--- |
22482 |
} |
--- |
| 22483 |
|
--- |
22483 |
|
--- |
| 22484 |
// If we didn't find at least one input vector, bail out. |
--- |
22484 |
// If we didn't find at least one input vector, bail out. |
--- |
| 22485 |
if (VecIn.size() < 2) |
0 |
22485 |
if (VecIn.size() < 2) |
0 |
| 22486 |
return SDValue(); |
0 |
22486 |
return SDValue(); |
0 |
| 22487 |
|
--- |
22487 |
|
--- |
| 22488 |
// If all the Operands of BUILD_VECTOR extract from same |
--- |
22488 |
// If all the Operands of BUILD_VECTOR extract from same |
--- |
| 22489 |
// vector, then split the vector efficiently based on the maximum |
--- |
22489 |
// vector, then split the vector efficiently based on the maximum |
--- |
| 22490 |
// vector access index and adjust the VectorMask and |
--- |
22490 |
// vector access index and adjust the VectorMask and |
--- |
| 22491 |
// VecIn accordingly. |
--- |
22491 |
// VecIn accordingly. |
--- |
| 22492 |
bool DidSplitVec = false; |
0 |
22492 |
bool DidSplitVec = false; |
0 |
| 22493 |
if (VecIn.size() == 2) { |
0 |
22493 |
if (VecIn.size() == 2) { |
0 |
| 22494 |
unsigned MaxIndex = 0; |
0 |
22494 |
unsigned MaxIndex = 0; |
0 |
| 22495 |
unsigned NearestPow2 = 0; |
0 |
22495 |
unsigned NearestPow2 = 0; |
0 |
| 22496 |
SDValue Vec = VecIn.back(); |
0 |
22496 |
SDValue Vec = VecIn.back(); |
0 |
| 22497 |
EVT InVT = Vec.getValueType(); |
0 |
22497 |
EVT InVT = Vec.getValueType(); |
0 |
| 22498 |
SmallVector IndexVec(NumElems, 0); |
0 |
22498 |
SmallVector IndexVec(NumElems, 0); |
0 |
| 22499 |
|
--- |
22499 |
|
--- |
| 22500 |
for (unsigned i = 0; i < NumElems; i++) { |
0 |
22500 |
for (unsigned i = 0; i < NumElems; i++) { |
0 |
| 22501 |
if (VectorMask[i] <= 0) |
0 |
22501 |
if (VectorMask[i] <= 0) |
0 |
| 22502 |
continue; |
0 |
22502 |
continue; |
0 |
| 22503 |
unsigned Index = N->getOperand(i).getConstantOperandVal(1); |
0 |
22503 |
unsigned Index = N->getOperand(i).getConstantOperandVal(1); |
0 |
| 22504 |
IndexVec[i] = Index; |
0 |
22504 |
IndexVec[i] = Index; |
0 |
| 22505 |
MaxIndex = std::max(MaxIndex, Index); |
0 |
22505 |
MaxIndex = std::max(MaxIndex, Index); |
0 |
| 22506 |
} |
--- |
22506 |
} |
--- |
| 22507 |
|
--- |
22507 |
|
--- |
| 22508 |
NearestPow2 = PowerOf2Ceil(MaxIndex); |
0 |
22508 |
NearestPow2 = PowerOf2Ceil(MaxIndex); |
0 |
| 22509 |
if (InVT.isSimple() && NearestPow2 > 2 && MaxIndex < NearestPow2 && |
0 |
22509 |
if (InVT.isSimple() && NearestPow2 > 2 && MaxIndex < NearestPow2 && |
0 |
| 22510 |
NumElems * 2 < NearestPow2) { |
0 |
22510 |
NumElems * 2 < NearestPow2) { |
0 |
| 22511 |
unsigned SplitSize = NearestPow2 / 2; |
0 |
22511 |
unsigned SplitSize = NearestPow2 / 2; |
0 |
| 22512 |
EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), |
0 |
22512 |
EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), |
0 |
| 22513 |
InVT.getVectorElementType(), SplitSize); |
--- |
22513 |
InVT.getVectorElementType(), SplitSize); |
--- |
| 22514 |
if (TLI.isTypeLegal(SplitVT) && |
0 |
22514 |
if (TLI.isTypeLegal(SplitVT) && |
0 |
| 22515 |
SplitSize + SplitVT.getVectorNumElements() <= |
0 |
22515 |
SplitSize + SplitVT.getVectorNumElements() <= |
0 |
| 22516 |
InVT.getVectorNumElements()) { |
0 |
22516 |
InVT.getVectorNumElements()) { |
0 |
| 22517 |
SDValue VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec, |
0 |
22517 |
SDValue VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec, |
0 |
| 22518 |
DAG.getVectorIdxConstant(SplitSize, DL)); |
0 |
22518 |
DAG.getVectorIdxConstant(SplitSize, DL)); |
0 |
| 22519 |
SDValue VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec, |
0 |
22519 |
SDValue VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec, |
0 |
| 22520 |
DAG.getVectorIdxConstant(0, DL)); |
0 |
22520 |
DAG.getVectorIdxConstant(0, DL)); |
0 |
| 22521 |
VecIn.pop_back(); |
0 |
22521 |
VecIn.pop_back(); |
0 |
| 22522 |
VecIn.push_back(VecIn1); |
0 |
22522 |
VecIn.push_back(VecIn1); |
0 |
| 22523 |
VecIn.push_back(VecIn2); |
0 |
22523 |
VecIn.push_back(VecIn2); |
0 |
| 22524 |
DidSplitVec = true; |
0 |
22524 |
DidSplitVec = true; |
0 |
| 22525 |
|
--- |
22525 |
|
--- |
| 22526 |
for (unsigned i = 0; i < NumElems; i++) { |
0 |
22526 |
for (unsigned i = 0; i < NumElems; i++) { |
0 |
| 22527 |
if (VectorMask[i] <= 0) |
0 |
22527 |
if (VectorMask[i] <= 0) |
0 |
| 22528 |
continue; |
0 |
22528 |
continue; |
0 |
| 22529 |
VectorMask[i] = (IndexVec[i] < SplitSize) ? 1 : 2; |
0 |
22529 |
VectorMask[i] = (IndexVec[i] < SplitSize) ? 1 : 2; |
0 |
| 22530 |
} |
--- |
22530 |
} |
--- |
| 22531 |
} |
--- |
22531 |
} |
--- |
| 22532 |
} |
--- |
22532 |
} |
--- |
| 22533 |
} |
0 |
22533 |
} |
0 |
| 22534 |
|
--- |
22534 |
|
--- |
| 22535 |
// Sort input vectors by decreasing vector element count, |
--- |
22535 |
// Sort input vectors by decreasing vector element count, |
--- |
| 22536 |
// while preserving the relative order of equally-sized vectors. |
--- |
22536 |
// while preserving the relative order of equally-sized vectors. |
--- |
| 22537 |
// Note that we keep the first "implicit zero vector as-is. |
--- |
22537 |
// Note that we keep the first "implicit zero vector as-is. |
--- |
| 22538 |
SmallVector SortedVecIn(VecIn); |
0 |
22538 |
SmallVector SortedVecIn(VecIn); |
0 |
| 22539 |
llvm::stable_sort(MutableArrayRef(SortedVecIn).drop_front(), |
0 |
22539 |
llvm::stable_sort(MutableArrayRef(SortedVecIn).drop_front(), |
0 |
| 22540 |
[](const SDValue &a, const SDValue &b) { |
0 |
22540 |
[](const SDValue &a, const SDValue &b) { |
0 |
| 22541 |
return a.getValueType().getVectorNumElements() > |
0 |
22541 |
return a.getValueType().getVectorNumElements() > |
0 |
| 22542 |
b.getValueType().getVectorNumElements(); |
0 |
22542 |
b.getValueType().getVectorNumElements(); |
0 |
| 22543 |
}); |
--- |
22543 |
}); |
--- |
| 22544 |
|
--- |
22544 |
|
--- |
| 22545 |
// We now also need to rebuild the VectorMask, because it referenced element |
--- |
22545 |
// We now also need to rebuild the VectorMask, because it referenced element |
--- |
| 22546 |
// order in VecIn, and we just sorted them. |
--- |
22546 |
// order in VecIn, and we just sorted them. |
--- |
| 22547 |
for (int &SourceVectorIndex : VectorMask) { |
0 |
22547 |
for (int &SourceVectorIndex : VectorMask) { |
0 |
| 22548 |
if (SourceVectorIndex <= 0) |
0 |
22548 |
if (SourceVectorIndex <= 0) |
0 |
| 22549 |
continue; |
0 |
22549 |
continue; |
0 |
| 22550 |
unsigned Idx = getFirstIndexOf(SortedVecIn, VecIn[SourceVectorIndex]); |
0 |
22550 |
unsigned Idx = getFirstIndexOf(SortedVecIn, VecIn[SourceVectorIndex]); |
0 |
| 22551 |
assert(Idx > 0 && Idx < SortedVecIn.size() && |
0 |
22551 |
assert(Idx > 0 && Idx < SortedVecIn.size() && |
0 |
| 22552 |
VecIn[SourceVectorIndex] == SortedVecIn[Idx] && "Remapping failure"); |
--- |
22552 |
VecIn[SourceVectorIndex] == SortedVecIn[Idx] && "Remapping failure"); |
--- |
| 22553 |
SourceVectorIndex = Idx; |
0 |
22553 |
SourceVectorIndex = Idx; |
0 |
| 22554 |
} |
--- |
22554 |
} |
--- |
| 22555 |
|
--- |
22555 |
|
--- |
| 22556 |
VecIn = std::move(SortedVecIn); |
0 |
22556 |
VecIn = std::move(SortedVecIn); |
0 |
| 22557 |
|
--- |
22557 |
|
--- |
| 22558 |
// TODO: Should this fire if some of the input vectors has illegal type (like |
--- |
22558 |
// TODO: Should this fire if some of the input vectors has illegal type (like |
--- |
| 22559 |
// it does now), or should we let legalization run its course first? |
--- |
22559 |
// it does now), or should we let legalization run its course first? |
--- |
| 22560 |
|
--- |
22560 |
|
--- |
| 22561 |
// Shuffle phase: |
--- |
22561 |
// Shuffle phase: |
--- |
| 22562 |
// Take pairs of vectors, and shuffle them so that the result has elements |
--- |
22562 |
// Take pairs of vectors, and shuffle them so that the result has elements |
--- |
| 22563 |
// from these vectors in the correct places. |
--- |
22563 |
// from these vectors in the correct places. |
--- |
| 22564 |
// For example, given: |
--- |
22564 |
// For example, given: |
--- |
| 22565 |
// t10: i32 = extract_vector_elt t1, Constant:i64<0> |
--- |
22565 |
// t10: i32 = extract_vector_elt t1, Constant:i64<0> |
--- |
| 22566 |
// t11: i32 = extract_vector_elt t2, Constant:i64<0> |
--- |
22566 |
// t11: i32 = extract_vector_elt t2, Constant:i64<0> |
--- |
| 22567 |
// t12: i32 = extract_vector_elt t3, Constant:i64<0> |
--- |
22567 |
// t12: i32 = extract_vector_elt t3, Constant:i64<0> |
--- |
| 22568 |
// t13: i32 = extract_vector_elt t1, Constant:i64<1> |
--- |
22568 |
// t13: i32 = extract_vector_elt t1, Constant:i64<1> |
--- |
| 22569 |
// t14: v4i32 = BUILD_VECTOR t10, t11, t12, t13 |
--- |
22569 |
// t14: v4i32 = BUILD_VECTOR t10, t11, t12, t13 |
--- |
| 22570 |
// We will generate: |
--- |
22570 |
// We will generate: |
--- |
| 22571 |
// t20: v4i32 = vector_shuffle<0,4,u,1> t1, t2 |
--- |
22571 |
// t20: v4i32 = vector_shuffle<0,4,u,1> t1, t2 |
--- |
| 22572 |
// t21: v4i32 = vector_shuffle t3, undef |
--- |
22572 |
// t21: v4i32 = vector_shuffle t3, undef |
--- |
| 22573 |
SmallVector Shuffles; |
0 |
22573 |
SmallVector Shuffles; |
0 |
| 22574 |
for (unsigned In = 0, Len = (VecIn.size() / 2); In < Len; ++In) { |
0 |
22574 |
for (unsigned In = 0, Len = (VecIn.size() / 2); In < Len; ++In) { |
0 |
| 22575 |
unsigned LeftIdx = 2 * In + 1; |
0 |
22575 |
unsigned LeftIdx = 2 * In + 1; |
0 |
| 22576 |
SDValue VecLeft = VecIn[LeftIdx]; |
0 |
22576 |
SDValue VecLeft = VecIn[LeftIdx]; |
0 |
| 22577 |
SDValue VecRight = |
--- |
22577 |
SDValue VecRight = |
--- |
| 22578 |
(LeftIdx + 1) < VecIn.size() ? VecIn[LeftIdx + 1] : SDValue(); |
0 |
22578 |
(LeftIdx + 1) < VecIn.size() ? VecIn[LeftIdx + 1] : SDValue(); |
0 |
| 22579 |
|
--- |
22579 |
|
--- |
| 22580 |
if (SDValue Shuffle = createBuildVecShuffle(DL, N, VectorMask, VecLeft, |
0 |
22580 |
if (SDValue Shuffle = createBuildVecShuffle(DL, N, VectorMask, VecLeft, |
0 |
| 22581 |
VecRight, LeftIdx, DidSplitVec)) |
0 |
22581 |
VecRight, LeftIdx, DidSplitVec)) |
0 |
| 22582 |
Shuffles.push_back(Shuffle); |
0 |
22582 |
Shuffles.push_back(Shuffle); |
0 |
| 22583 |
else |
--- |
22583 |
else |
--- |
| 22584 |
return SDValue(); |
0 |
22584 |
return SDValue(); |
0 |
| 22585 |
} |
--- |
22585 |
} |
--- |
| 22586 |
|
--- |
22586 |
|
--- |
| 22587 |
// If we need the zero vector as an "ingredient" in the blend tree, add it |
--- |
22587 |
// If we need the zero vector as an "ingredient" in the blend tree, add it |
--- |
| 22588 |
// to the list of shuffles. |
--- |
22588 |
// to the list of shuffles. |
--- |
| 22589 |
if (UsesZeroVector) |
0 |
22589 |
if (UsesZeroVector) |
0 |
| 22590 |
Shuffles.push_back(VT.isInteger() ? DAG.getConstant(0, DL, VT) |
0 |
22590 |
Shuffles.push_back(VT.isInteger() ? DAG.getConstant(0, DL, VT) |
0 |
| 22591 |
: DAG.getConstantFP(0.0, DL, VT)); |
0 |
22591 |
: DAG.getConstantFP(0.0, DL, VT)); |
0 |
| 22592 |
|
--- |
22592 |
|
--- |
| 22593 |
// If we only have one shuffle, we're done. |
--- |
22593 |
// If we only have one shuffle, we're done. |
--- |
| 22594 |
if (Shuffles.size() == 1) |
0 |
22594 |
if (Shuffles.size() == 1) |
0 |
| 22595 |
return Shuffles[0]; |
0 |
22595 |
return Shuffles[0]; |
0 |
| 22596 |
|
--- |
22596 |
|
--- |
| 22597 |
// Update the vector mask to point to the post-shuffle vectors. |
--- |
22597 |
// Update the vector mask to point to the post-shuffle vectors. |
--- |
| 22598 |
for (int &Vec : VectorMask) |
0 |
22598 |
for (int &Vec : VectorMask) |
0 |
| 22599 |
if (Vec == 0) |
0 |
22599 |
if (Vec == 0) |
0 |
| 22600 |
Vec = Shuffles.size() - 1; |
0 |
22600 |
Vec = Shuffles.size() - 1; |
0 |
| 22601 |
else |
--- |
22601 |
else |
--- |
| 22602 |
Vec = (Vec - 1) / 2; |
0 |
22602 |
Vec = (Vec - 1) / 2; |
0 |
| 22603 |
|
--- |
22603 |
|
--- |
| 22604 |
// More than one shuffle. Generate a binary tree of blends, e.g. if from |
--- |
22604 |
// More than one shuffle. Generate a binary tree of blends, e.g. if from |
--- |
| 22605 |
// the previous step we got the set of shuffles t10, t11, t12, t13, we will |
--- |
22605 |
// the previous step we got the set of shuffles t10, t11, t12, t13, we will |
--- |
| 22606 |
// generate: |
--- |
22606 |
// generate: |
--- |
| 22607 |
// t10: v8i32 = vector_shuffle<0,8,u,u,u,u,u,u> t1, t2 |
--- |
22607 |
// t10: v8i32 = vector_shuffle<0,8,u,u,u,u,u,u> t1, t2 |
--- |
| 22608 |
// t11: v8i32 = vector_shuffle t3, t4 |
--- |
22608 |
// t11: v8i32 = vector_shuffle t3, t4 |
--- |
| 22609 |
// t12: v8i32 = vector_shuffle t5, t6 |
--- |
22609 |
// t12: v8i32 = vector_shuffle t5, t6 |
--- |
| 22610 |
// t13: v8i32 = vector_shuffle t7, t8 |
--- |
22610 |
// t13: v8i32 = vector_shuffle t7, t8 |
--- |
| 22611 |
// t20: v8i32 = vector_shuffle<0,1,10,11,u,u,u,u> t10, t11 |
--- |
22611 |
// t20: v8i32 = vector_shuffle<0,1,10,11,u,u,u,u> t10, t11 |
--- |
| 22612 |
// t21: v8i32 = vector_shuffle t12, t13 |
--- |
22612 |
// t21: v8i32 = vector_shuffle t12, t13 |
--- |
| 22613 |
// t30: v8i32 = vector_shuffle<0,1,2,3,12,13,14,15> t20, t21 |
--- |
22613 |
// t30: v8i32 = vector_shuffle<0,1,2,3,12,13,14,15> t20, t21 |
--- |
| 22614 |
|
--- |
22614 |
|
--- |
| 22615 |
// Make sure the initial size of the shuffle list is even. |
--- |
22615 |
// Make sure the initial size of the shuffle list is even. |
--- |
| 22616 |
if (Shuffles.size() % 2) |
0 |
22616 |
if (Shuffles.size() % 2) |
0 |
| 22617 |
Shuffles.push_back(DAG.getUNDEF(VT)); |
0 |
22617 |
Shuffles.push_back(DAG.getUNDEF(VT)); |
0 |
| 22618 |
|
--- |
22618 |
|
--- |
| 22619 |
for (unsigned CurSize = Shuffles.size(); CurSize > 1; CurSize /= 2) { |
0 |
22619 |
for (unsigned CurSize = Shuffles.size(); CurSize > 1; CurSize /= 2) { |
0 |
| 22620 |
if (CurSize % 2) { |
0 |
22620 |
if (CurSize % 2) { |
0 |
| 22621 |
Shuffles[CurSize] = DAG.getUNDEF(VT); |
0 |
22621 |
Shuffles[CurSize] = DAG.getUNDEF(VT); |
0 |
| 22622 |
CurSize++; |
0 |
22622 |
CurSize++; |
0 |
| 22623 |
} |
--- |
22623 |
} |
--- |
| 22624 |
for (unsigned In = 0, Len = CurSize / 2; In < Len; ++In) { |
0 |
22624 |
for (unsigned In = 0, Len = CurSize / 2; In < Len; ++In) { |
0 |
| 22625 |
int Left = 2 * In; |
0 |
22625 |
int Left = 2 * In; |
0 |
| 22626 |
int Right = 2 * In + 1; |
0 |
22626 |
int Right = 2 * In + 1; |
0 |
| 22627 |
SmallVector Mask(NumElems, -1); |
0 |
22627 |
SmallVector Mask(NumElems, -1); |
0 |
| 22628 |
SDValue L = Shuffles[Left]; |
0 |
22628 |
SDValue L = Shuffles[Left]; |
0 |
| 22629 |
ArrayRef LMask; |
0 |
22629 |
ArrayRef LMask; |
0 |
| 22630 |
bool IsLeftShuffle = L.getOpcode() == ISD::VECTOR_SHUFFLE && |
0 |
22630 |
bool IsLeftShuffle = L.getOpcode() == ISD::VECTOR_SHUFFLE && |
0 |
| 22631 |
L.use_empty() && L.getOperand(1).isUndef() && |
0 |
22631 |
L.use_empty() && L.getOperand(1).isUndef() && |
0 |
| 22632 |
L.getOperand(0).getValueType() == L.getValueType(); |
0 |
22632 |
L.getOperand(0).getValueType() == L.getValueType(); |
0 |
| 22633 |
if (IsLeftShuffle) { |
0 |
22633 |
if (IsLeftShuffle) { |
0 |
| 22634 |
LMask = cast(L.getNode())->getMask(); |
0 |
22634 |
LMask = cast(L.getNode())->getMask(); |
0 |
| 22635 |
L = L.getOperand(0); |
0 |
22635 |
L = L.getOperand(0); |
0 |
| 22636 |
} |
--- |
22636 |
} |
--- |
| 22637 |
SDValue R = Shuffles[Right]; |
0 |
22637 |
SDValue R = Shuffles[Right]; |
0 |
| 22638 |
ArrayRef RMask; |
0 |
22638 |
ArrayRef RMask; |
0 |
| 22639 |
bool IsRightShuffle = R.getOpcode() == ISD::VECTOR_SHUFFLE && |
0 |
22639 |
bool IsRightShuffle = R.getOpcode() == ISD::VECTOR_SHUFFLE && |
0 |
| 22640 |
R.use_empty() && R.getOperand(1).isUndef() && |
0 |
22640 |
R.use_empty() && R.getOperand(1).isUndef() && |
0 |
| 22641 |
R.getOperand(0).getValueType() == R.getValueType(); |
0 |
22641 |
R.getOperand(0).getValueType() == R.getValueType(); |
0 |
| 22642 |
if (IsRightShuffle) { |
0 |
22642 |
if (IsRightShuffle) { |
0 |
| 22643 |
RMask = cast(R.getNode())->getMask(); |
0 |
22643 |
RMask = cast(R.getNode())->getMask(); |
0 |
| 22644 |
R = R.getOperand(0); |
0 |
22644 |
R = R.getOperand(0); |
0 |
| 22645 |
} |
--- |
22645 |
} |
--- |
| 22646 |
for (unsigned I = 0; I != NumElems; ++I) { |
0 |
22646 |
for (unsigned I = 0; I != NumElems; ++I) { |
0 |
| 22647 |
if (VectorMask[I] == Left) { |
0 |
22647 |
if (VectorMask[I] == Left) { |
0 |
| 22648 |
Mask[I] = I; |
0 |
22648 |
Mask[I] = I; |
0 |
| 22649 |
if (IsLeftShuffle) |
0 |
22649 |
if (IsLeftShuffle) |
0 |
| 22650 |
Mask[I] = LMask[I]; |
0 |
22650 |
Mask[I] = LMask[I]; |
0 |
| 22651 |
VectorMask[I] = In; |
0 |
22651 |
VectorMask[I] = In; |
0 |
| 22652 |
} else if (VectorMask[I] == Right) { |
0 |
22652 |
} else if (VectorMask[I] == Right) { |
0 |
| 22653 |
Mask[I] = I + NumElems; |
0 |
22653 |
Mask[I] = I + NumElems; |
0 |
| 22654 |
if (IsRightShuffle) |
0 |
22654 |
if (IsRightShuffle) |
0 |
| 22655 |
Mask[I] = RMask[I] + NumElems; |
0 |
22655 |
Mask[I] = RMask[I] + NumElems; |
0 |
| 22656 |
VectorMask[I] = In; |
0 |
22656 |
VectorMask[I] = In; |
0 |
| 22657 |
} |
--- |
22657 |
} |
--- |
| 22658 |
} |
--- |
22658 |
} |
--- |
| 22659 |
|
--- |
22659 |
|
--- |
| 22660 |
Shuffles[In] = DAG.getVectorShuffle(VT, DL, L, R, Mask); |
0 |
22660 |
Shuffles[In] = DAG.getVectorShuffle(VT, DL, L, R, Mask); |
0 |
| 22661 |
} |
0 |
22661 |
} |
0 |
| 22662 |
} |
--- |
22662 |
} |
--- |
| 22663 |
return Shuffles[0]; |
0 |
22663 |
return Shuffles[0]; |
0 |
| 22664 |
} |
0 |
22664 |
} |
0 |
| 22665 |
|
--- |
22665 |
|
--- |
| 22666 |
// Try to turn a build vector of zero extends of extract vector elts into a |
--- |
22666 |
// Try to turn a build vector of zero extends of extract vector elts into a |
--- |
| 22667 |
// a vector zero extend and possibly an extract subvector. |
--- |
22667 |
// a vector zero extend and possibly an extract subvector. |
--- |
| 22668 |
// TODO: Support sign extend? |
--- |
22668 |
// TODO: Support sign extend? |
--- |
| 22669 |
// TODO: Allow undef elements? |
--- |
22669 |
// TODO: Allow undef elements? |
--- |
| 22670 |
SDValue DAGCombiner::convertBuildVecZextToZext(SDNode *N) { |
0 |
22670 |
SDValue DAGCombiner::convertBuildVecZextToZext(SDNode *N) { |
0 |
| 22671 |
if (LegalOperations) |
0 |
22671 |
if (LegalOperations) |
0 |
| 22672 |
return SDValue(); |
0 |
22672 |
return SDValue(); |
0 |
| 22673 |
|
--- |
22673 |
|
--- |
| 22674 |
EVT VT = N->getValueType(0); |
0 |
22674 |
EVT VT = N->getValueType(0); |
0 |
| 22675 |
|
--- |
22675 |
|
--- |
| 22676 |
bool FoundZeroExtend = false; |
0 |
22676 |
bool FoundZeroExtend = false; |
0 |
| 22677 |
SDValue Op0 = N->getOperand(0); |
0 |
22677 |
SDValue Op0 = N->getOperand(0); |
0 |
| 22678 |
auto checkElem = [&](SDValue Op) -> int64_t { |
0 |
22678 |
auto checkElem = [&](SDValue Op) -> int64_t { |
0 |
| 22679 |
unsigned Opc = Op.getOpcode(); |
0 |
22679 |
unsigned Opc = Op.getOpcode(); |
0 |
| 22680 |
FoundZeroExtend |= (Opc == ISD::ZERO_EXTEND); |
0 |
22680 |
FoundZeroExtend |= (Opc == ISD::ZERO_EXTEND); |
0 |
| 22681 |
if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND) && |
0 |
22681 |
if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND) && |
0 |
| 22682 |
Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
0 |
22682 |
Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
0 |
| 22683 |
Op0.getOperand(0).getOperand(0) == Op.getOperand(0).getOperand(0)) |
0 |
22683 |
Op0.getOperand(0).getOperand(0) == Op.getOperand(0).getOperand(0)) |
0 |
| 22684 |
if (auto *C = dyn_cast(Op.getOperand(0).getOperand(1))) |
0 |
22684 |
if (auto *C = dyn_cast(Op.getOperand(0).getOperand(1))) |
0 |
| 22685 |
return C->getZExtValue(); |
0 |
22685 |
return C->getZExtValue(); |
0 |
| 22686 |
return -1; |
0 |
22686 |
return -1; |
0 |
| 22687 |
}; |
0 |
22687 |
}; |
0 |
| 22688 |
|
--- |
22688 |
|
--- |
| 22689 |
// Make sure the first element matches |
--- |
22689 |
// Make sure the first element matches |
--- |
| 22690 |
// (zext (extract_vector_elt X, C)) |
--- |
22690 |
// (zext (extract_vector_elt X, C)) |
--- |
| 22691 |
// Offset must be a constant multiple of the |
--- |
22691 |
// Offset must be a constant multiple of the |
--- |
| 22692 |
// known-minimum vector length of the result type. |
--- |
22692 |
// known-minimum vector length of the result type. |
--- |
| 22693 |
int64_t Offset = checkElem(Op0); |
0 |
22693 |
int64_t Offset = checkElem(Op0); |
0 |
| 22694 |
if (Offset < 0 || (Offset % VT.getVectorNumElements()) != 0) |
0 |
22694 |
if (Offset < 0 || (Offset % VT.getVectorNumElements()) != 0) |
0 |
| 22695 |
return SDValue(); |
0 |
22695 |
return SDValue(); |
0 |
| 22696 |
|
--- |
22696 |
|
--- |
| 22697 |
unsigned NumElems = N->getNumOperands(); |
0 |
22697 |
unsigned NumElems = N->getNumOperands(); |
0 |
| 22698 |
SDValue In = Op0.getOperand(0).getOperand(0); |
0 |
22698 |
SDValue In = Op0.getOperand(0).getOperand(0); |
0 |
| 22699 |
EVT InSVT = In.getValueType().getScalarType(); |
0 |
22699 |
EVT InSVT = In.getValueType().getScalarType(); |
0 |
| 22700 |
EVT InVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumElems); |
0 |
22700 |
EVT InVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumElems); |
0 |
| 22701 |
|
--- |
22701 |
|
--- |
| 22702 |
// Don't create an illegal input type after type legalization. |
--- |
22702 |
// Don't create an illegal input type after type legalization. |
--- |
| 22703 |
if (LegalTypes && !TLI.isTypeLegal(InVT)) |
0 |
22703 |
if (LegalTypes && !TLI.isTypeLegal(InVT)) |
0 |
| 22704 |
return SDValue(); |
0 |
22704 |
return SDValue(); |
0 |
| 22705 |
|
--- |
22705 |
|
--- |
| 22706 |
// Ensure all the elements come from the same vector and are adjacent. |
--- |
22706 |
// Ensure all the elements come from the same vector and are adjacent. |
--- |
| 22707 |
for (unsigned i = 1; i != NumElems; ++i) { |
0 |
22707 |
for (unsigned i = 1; i != NumElems; ++i) { |
0 |
| 22708 |
if ((Offset + i) != checkElem(N->getOperand(i))) |
0 |
22708 |
if ((Offset + i) != checkElem(N->getOperand(i))) |
0 |
| 22709 |
return SDValue(); |
0 |
22709 |
return SDValue(); |
0 |
| 22710 |
} |
--- |
22710 |
} |
--- |
| 22711 |
|
--- |
22711 |
|
--- |
| 22712 |
SDLoc DL(N); |
0 |
22712 |
SDLoc DL(N); |
0 |
| 22713 |
In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In, |
0 |
22713 |
In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In, |
0 |
| 22714 |
Op0.getOperand(0).getOperand(1)); |
0 |
22714 |
Op0.getOperand(0).getOperand(1)); |
0 |
| 22715 |
return DAG.getNode(FoundZeroExtend ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, DL, |
0 |
22715 |
return DAG.getNode(FoundZeroExtend ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, DL, |
0 |
| 22716 |
VT, In); |
0 |
22716 |
VT, In); |
0 |
| 22717 |
} |
0 |
22717 |
} |
0 |
| 22718 |
|
--- |
22718 |
|
--- |
| 22719 |
// If this is a very simple BUILD_VECTOR with first element being a ZERO_EXTEND, |
--- |
22719 |
// If this is a very simple BUILD_VECTOR with first element being a ZERO_EXTEND, |
--- |
| 22720 |
// and all other elements being constant zero's, granularize the BUILD_VECTOR's |
--- |
22720 |
// and all other elements being constant zero's, granularize the BUILD_VECTOR's |
--- |
| 22721 |
// element width, absorbing the ZERO_EXTEND, turning it into a constant zero op. |
--- |
22721 |
// element width, absorbing the ZERO_EXTEND, turning it into a constant zero op. |
--- |
| 22722 |
// This patten can appear during legalization. |
--- |
22722 |
// This patten can appear during legalization. |
--- |
| 22723 |
// |
--- |
22723 |
// |
--- |
| 22724 |
// NOTE: This can be generalized to allow more than a single |
--- |
22724 |
// NOTE: This can be generalized to allow more than a single |
--- |
| 22725 |
// non-constant-zero op, UNDEF's, and to be KnownBits-based, |
--- |
22725 |
// non-constant-zero op, UNDEF's, and to be KnownBits-based, |
--- |
| 22726 |
SDValue DAGCombiner::convertBuildVecZextToBuildVecWithZeros(SDNode *N) { |
0 |
22726 |
SDValue DAGCombiner::convertBuildVecZextToBuildVecWithZeros(SDNode *N) { |
0 |
| 22727 |
// Don't run this after legalization. Targets may have other preferences. |
--- |
22727 |
// Don't run this after legalization. Targets may have other preferences. |
--- |
| 22728 |
if (Level >= AfterLegalizeDAG) |
0 |
22728 |
if (Level >= AfterLegalizeDAG) |
0 |
| 22729 |
return SDValue(); |
0 |
22729 |
return SDValue(); |
0 |
| 22730 |
|
--- |
22730 |
|
--- |
| 22731 |
// FIXME: support big-endian. |
--- |
22731 |
// FIXME: support big-endian. |
--- |
| 22732 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
22732 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
| 22733 |
return SDValue(); |
0 |
22733 |
return SDValue(); |
0 |
| 22734 |
|
--- |
22734 |
|
--- |
| 22735 |
EVT VT = N->getValueType(0); |
0 |
22735 |
EVT VT = N->getValueType(0); |
0 |
| 22736 |
EVT OpVT = N->getOperand(0).getValueType(); |
0 |
22736 |
EVT OpVT = N->getOperand(0).getValueType(); |
0 |
| 22737 |
assert(!VT.isScalableVector() && "Encountered scalable BUILD_VECTOR?"); |
0 |
22737 |
assert(!VT.isScalableVector() && "Encountered scalable BUILD_VECTOR?"); |
0 |
| 22738 |
|
--- |
22738 |
|
--- |
| 22739 |
EVT OpIntVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits()); |
0 |
22739 |
EVT OpIntVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits()); |
0 |
| 22740 |
|
--- |
22740 |
|
--- |
| 22741 |
if (!TLI.isTypeLegal(OpIntVT) || |
0 |
22741 |
if (!TLI.isTypeLegal(OpIntVT) || |
0 |
| 22742 |
(LegalOperations && !TLI.isOperationLegalOrCustom(ISD::BITCAST, OpIntVT))) |
0 |
22742 |
(LegalOperations && !TLI.isOperationLegalOrCustom(ISD::BITCAST, OpIntVT))) |
0 |
| 22743 |
return SDValue(); |
0 |
22743 |
return SDValue(); |
0 |
| 22744 |
|
--- |
22744 |
|
--- |
| 22745 |
unsigned EltBitwidth = VT.getScalarSizeInBits(); |
0 |
22745 |
unsigned EltBitwidth = VT.getScalarSizeInBits(); |
0 |
| 22746 |
// NOTE: the actual width of operands may be wider than that! |
--- |
22746 |
// NOTE: the actual width of operands may be wider than that! |
--- |
| 22747 |
|
--- |
22747 |
|
--- |
| 22748 |
// Analyze all operands of this BUILD_VECTOR. What is the largest number of |
--- |
22748 |
// Analyze all operands of this BUILD_VECTOR. What is the largest number of |
--- |
| 22749 |
// active bits they all have? We'll want to truncate them all to that width. |
--- |
22749 |
// active bits they all have? We'll want to truncate them all to that width. |
--- |
| 22750 |
unsigned ActiveBits = 0; |
0 |
22750 |
unsigned ActiveBits = 0; |
0 |
| 22751 |
APInt KnownZeroOps(VT.getVectorNumElements(), 0); |
0 |
22751 |
APInt KnownZeroOps(VT.getVectorNumElements(), 0); |
0 |
| 22752 |
for (auto I : enumerate(N->ops())) { |
0 |
22752 |
for (auto I : enumerate(N->ops())) { |
0 |
| 22753 |
SDValue Op = I.value(); |
0 |
22753 |
SDValue Op = I.value(); |
0 |
| 22754 |
// FIXME: support UNDEF elements? |
--- |
22754 |
// FIXME: support UNDEF elements? |
--- |
| 22755 |
if (auto *Cst = dyn_cast(Op)) { |
0 |
22755 |
if (auto *Cst = dyn_cast(Op)) { |
0 |
| 22756 |
unsigned OpActiveBits = |
--- |
22756 |
unsigned OpActiveBits = |
--- |
| 22757 |
Cst->getAPIntValue().trunc(EltBitwidth).getActiveBits(); |
0 |
22757 |
Cst->getAPIntValue().trunc(EltBitwidth).getActiveBits(); |
0 |
| 22758 |
if (OpActiveBits == 0) { |
0 |
22758 |
if (OpActiveBits == 0) { |
0 |
| 22759 |
KnownZeroOps.setBit(I.index()); |
0 |
22759 |
KnownZeroOps.setBit(I.index()); |
0 |
| 22760 |
continue; |
0 |
22760 |
continue; |
0 |
| 22761 |
} |
--- |
22761 |
} |
--- |
| 22762 |
// Profitability check: don't allow non-zero constant operands. |
--- |
22762 |
// Profitability check: don't allow non-zero constant operands. |
--- |
| 22763 |
return SDValue(); |
0 |
22763 |
return SDValue(); |
0 |
| 22764 |
} |
--- |
22764 |
} |
--- |
| 22765 |
// Profitability check: there must only be a single non-zero operand, |
--- |
22765 |
// Profitability check: there must only be a single non-zero operand, |
--- |
| 22766 |
// and it must be the first operand of the BUILD_VECTOR. |
--- |
22766 |
// and it must be the first operand of the BUILD_VECTOR. |
--- |
| 22767 |
if (I.index() != 0) |
0 |
22767 |
if (I.index() != 0) |
0 |
| 22768 |
return SDValue(); |
0 |
22768 |
return SDValue(); |
0 |
| 22769 |
// The operand must be a zero-extension itself. |
--- |
22769 |
// The operand must be a zero-extension itself. |
--- |
| 22770 |
// FIXME: this could be generalized to known leading zeros check. |
--- |
22770 |
// FIXME: this could be generalized to known leading zeros check. |
--- |
| 22771 |
if (Op.getOpcode() != ISD::ZERO_EXTEND) |
0 |
22771 |
if (Op.getOpcode() != ISD::ZERO_EXTEND) |
0 |
| 22772 |
return SDValue(); |
0 |
22772 |
return SDValue(); |
0 |
| 22773 |
unsigned CurrActiveBits = |
--- |
22773 |
unsigned CurrActiveBits = |
--- |
| 22774 |
Op.getOperand(0).getValueSizeInBits().getFixedValue(); |
0 |
22774 |
Op.getOperand(0).getValueSizeInBits().getFixedValue(); |
0 |
| 22775 |
assert(!ActiveBits && "Already encountered non-constant-zero operand?"); |
0 |
22775 |
assert(!ActiveBits && "Already encountered non-constant-zero operand?"); |
0 |
| 22776 |
ActiveBits = CurrActiveBits; |
0 |
22776 |
ActiveBits = CurrActiveBits; |
0 |
| 22777 |
// We want to at least halve the element size. |
--- |
22777 |
// We want to at least halve the element size. |
--- |
| 22778 |
if (2 * ActiveBits > EltBitwidth) |
0 |
22778 |
if (2 * ActiveBits > EltBitwidth) |
0 |
| 22779 |
return SDValue(); |
0 |
22779 |
return SDValue(); |
0 |
| 22780 |
} |
--- |
22780 |
} |
--- |
| 22781 |
|
--- |
22781 |
|
--- |
| 22782 |
// This BUILD_VECTOR must have at least one non-constant-zero operand. |
--- |
22782 |
// This BUILD_VECTOR must have at least one non-constant-zero operand. |
--- |
| 22783 |
if (ActiveBits == 0) |
0 |
22783 |
if (ActiveBits == 0) |
0 |
| 22784 |
return SDValue(); |
0 |
22784 |
return SDValue(); |
0 |
| 22785 |
|
--- |
22785 |
|
--- |
| 22786 |
// We have EltBitwidth bits, the *minimal* chunk size is ActiveBits, |
--- |
22786 |
// We have EltBitwidth bits, the *minimal* chunk size is ActiveBits, |
--- |
| 22787 |
// into how many chunks can we split our element width? |
--- |
22787 |
// into how many chunks can we split our element width? |
--- |
| 22788 |
EVT NewScalarIntVT, NewIntVT; |
0 |
22788 |
EVT NewScalarIntVT, NewIntVT; |
0 |
| 22789 |
std::optional Factor; |
0 |
22789 |
std::optional Factor; |
0 |
| 22790 |
// We can split the element into at least two chunks, but not into more |
--- |
22790 |
// We can split the element into at least two chunks, but not into more |
--- |
| 22791 |
// than |_ EltBitwidth / ActiveBits _| chunks. Find a largest split factor |
--- |
22791 |
// than |_ EltBitwidth / ActiveBits _| chunks. Find a largest split factor |
--- |
| 22792 |
// for which the element width is a multiple of it, |
--- |
22792 |
// for which the element width is a multiple of it, |
--- |
| 22793 |
// and the resulting types/operations on that chunk width are legal. |
--- |
22793 |
// and the resulting types/operations on that chunk width are legal. |
--- |
| 22794 |
assert(2 * ActiveBits <= EltBitwidth && |
0 |
22794 |
assert(2 * ActiveBits <= EltBitwidth && |
0 |
| 22795 |
"We know that half or less bits of the element are active."); |
--- |
22795 |
"We know that half or less bits of the element are active."); |
--- |
| 22796 |
for (unsigned Scale = EltBitwidth / ActiveBits; Scale >= 2; --Scale) { |
0 |
22796 |
for (unsigned Scale = EltBitwidth / ActiveBits; Scale >= 2; --Scale) { |
0 |
| 22797 |
if (EltBitwidth % Scale != 0) |
0 |
22797 |
if (EltBitwidth % Scale != 0) |
0 |
| 22798 |
continue; |
0 |
22798 |
continue; |
0 |
| 22799 |
unsigned ChunkBitwidth = EltBitwidth / Scale; |
0 |
22799 |
unsigned ChunkBitwidth = EltBitwidth / Scale; |
0 |
| 22800 |
assert(ChunkBitwidth >= ActiveBits && "As per starting point."); |
0 |
22800 |
assert(ChunkBitwidth >= ActiveBits && "As per starting point."); |
0 |
| 22801 |
NewScalarIntVT = EVT::getIntegerVT(*DAG.getContext(), ChunkBitwidth); |
0 |
22801 |
NewScalarIntVT = EVT::getIntegerVT(*DAG.getContext(), ChunkBitwidth); |
0 |
| 22802 |
NewIntVT = EVT::getVectorVT(*DAG.getContext(), NewScalarIntVT, |
0 |
22802 |
NewIntVT = EVT::getVectorVT(*DAG.getContext(), NewScalarIntVT, |
0 |
| 22803 |
Scale * N->getNumOperands()); |
0 |
22803 |
Scale * N->getNumOperands()); |
0 |
| 22804 |
if (!TLI.isTypeLegal(NewScalarIntVT) || !TLI.isTypeLegal(NewIntVT) || |
0 |
22804 |
if (!TLI.isTypeLegal(NewScalarIntVT) || !TLI.isTypeLegal(NewIntVT) || |
0 |
| 22805 |
(LegalOperations && |
0 |
22805 |
(LegalOperations && |
0 |
| 22806 |
!(TLI.isOperationLegalOrCustom(ISD::TRUNCATE, NewScalarIntVT) && |
0 |
22806 |
!(TLI.isOperationLegalOrCustom(ISD::TRUNCATE, NewScalarIntVT) && |
0 |
| 22807 |
TLI.isOperationLegalOrCustom(ISD::BUILD_VECTOR, NewIntVT)))) |
0 |
22807 |
TLI.isOperationLegalOrCustom(ISD::BUILD_VECTOR, NewIntVT)))) |
0 |
| 22808 |
continue; |
0 |
22808 |
continue; |
0 |
| 22809 |
Factor = Scale; |
0 |
22809 |
Factor = Scale; |
0 |
| 22810 |
break; |
0 |
22810 |
break; |
0 |
| 22811 |
} |
--- |
22811 |
} |
--- |
| 22812 |
if (!Factor) |
0 |
22812 |
if (!Factor) |
0 |
| 22813 |
return SDValue(); |
0 |
22813 |
return SDValue(); |
0 |
| 22814 |
|
--- |
22814 |
|
--- |
| 22815 |
SDLoc DL(N); |
0 |
22815 |
SDLoc DL(N); |
0 |
| 22816 |
SDValue ZeroOp = DAG.getConstant(0, DL, NewScalarIntVT); |
0 |
22816 |
SDValue ZeroOp = DAG.getConstant(0, DL, NewScalarIntVT); |
0 |
| 22817 |
|
--- |
22817 |
|
--- |
| 22818 |
// Recreate the BUILD_VECTOR, with elements now being Factor times smaller. |
--- |
22818 |
// Recreate the BUILD_VECTOR, with elements now being Factor times smaller. |
--- |
| 22819 |
SmallVector NewOps; |
0 |
22819 |
SmallVector NewOps; |
0 |
| 22820 |
NewOps.reserve(NewIntVT.getVectorNumElements()); |
0 |
22820 |
NewOps.reserve(NewIntVT.getVectorNumElements()); |
0 |
| 22821 |
for (auto I : enumerate(N->ops())) { |
0 |
22821 |
for (auto I : enumerate(N->ops())) { |
0 |
| 22822 |
SDValue Op = I.value(); |
0 |
22822 |
SDValue Op = I.value(); |
0 |
| 22823 |
assert(!Op.isUndef() && "FIXME: after allowing UNDEF's, handle them here."); |
0 |
22823 |
assert(!Op.isUndef() && "FIXME: after allowing UNDEF's, handle them here."); |
0 |
| 22824 |
unsigned SrcOpIdx = I.index(); |
0 |
22824 |
unsigned SrcOpIdx = I.index(); |
0 |
| 22825 |
if (KnownZeroOps[SrcOpIdx]) { |
0 |
22825 |
if (KnownZeroOps[SrcOpIdx]) { |
0 |
| 22826 |
NewOps.append(*Factor, ZeroOp); |
0 |
22826 |
NewOps.append(*Factor, ZeroOp); |
0 |
| 22827 |
continue; |
0 |
22827 |
continue; |
0 |
| 22828 |
} |
--- |
22828 |
} |
--- |
| 22829 |
Op = DAG.getBitcast(OpIntVT, Op); |
0 |
22829 |
Op = DAG.getBitcast(OpIntVT, Op); |
0 |
| 22830 |
Op = DAG.getNode(ISD::TRUNCATE, DL, NewScalarIntVT, Op); |
0 |
22830 |
Op = DAG.getNode(ISD::TRUNCATE, DL, NewScalarIntVT, Op); |
0 |
| 22831 |
NewOps.emplace_back(Op); |
0 |
22831 |
NewOps.emplace_back(Op); |
0 |
| 22832 |
NewOps.append(*Factor - 1, ZeroOp); |
0 |
22832 |
NewOps.append(*Factor - 1, ZeroOp); |
0 |
| 22833 |
} |
--- |
22833 |
} |
--- |
| 22834 |
assert(NewOps.size() == NewIntVT.getVectorNumElements()); |
0 |
22834 |
assert(NewOps.size() == NewIntVT.getVectorNumElements()); |
0 |
| 22835 |
SDValue NewBV = DAG.getBuildVector(NewIntVT, DL, NewOps); |
0 |
22835 |
SDValue NewBV = DAG.getBuildVector(NewIntVT, DL, NewOps); |
0 |
| 22836 |
NewBV = DAG.getBitcast(VT, NewBV); |
0 |
22836 |
NewBV = DAG.getBitcast(VT, NewBV); |
0 |
| 22837 |
return NewBV; |
0 |
22837 |
return NewBV; |
0 |
| 22838 |
} |
0 |
22838 |
} |
0 |
| 22839 |
|
--- |
22839 |
|
--- |
| 22840 |
SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { |
0 |
22840 |
SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { |
0 |
| 22841 |
EVT VT = N->getValueType(0); |
0 |
22841 |
EVT VT = N->getValueType(0); |
0 |
| 22842 |
|
--- |
22842 |
|
--- |
| 22843 |
// A vector built entirely of undefs is undef. |
--- |
22843 |
// A vector built entirely of undefs is undef. |
--- |
| 22844 |
if (ISD::allOperandsUndef(N)) |
0 |
22844 |
if (ISD::allOperandsUndef(N)) |
0 |
| 22845 |
return DAG.getUNDEF(VT); |
0 |
22845 |
return DAG.getUNDEF(VT); |
0 |
| 22846 |
|
--- |
22846 |
|
--- |
| 22847 |
// If this is a splat of a bitcast from another vector, change to a |
--- |
22847 |
// If this is a splat of a bitcast from another vector, change to a |
--- |
| 22848 |
// concat_vector. |
--- |
22848 |
// concat_vector. |
--- |
| 22849 |
// For example: |
--- |
22849 |
// For example: |
--- |
| 22850 |
// (build_vector (i64 (bitcast (v2i32 X))), (i64 (bitcast (v2i32 X)))) -> |
--- |
22850 |
// (build_vector (i64 (bitcast (v2i32 X))), (i64 (bitcast (v2i32 X)))) -> |
--- |
| 22851 |
// (v2i64 (bitcast (concat_vectors (v2i32 X), (v2i32 X)))) |
--- |
22851 |
// (v2i64 (bitcast (concat_vectors (v2i32 X), (v2i32 X)))) |
--- |
| 22852 |
// |
--- |
22852 |
// |
--- |
| 22853 |
// If X is a build_vector itself, the concat can become a larger build_vector. |
--- |
22853 |
// If X is a build_vector itself, the concat can become a larger build_vector. |
--- |
| 22854 |
// TODO: Maybe this is useful for non-splat too? |
--- |
22854 |
// TODO: Maybe this is useful for non-splat too? |
--- |
| 22855 |
if (!LegalOperations) { |
0 |
22855 |
if (!LegalOperations) { |
0 |
| 22856 |
if (SDValue Splat = cast(N)->getSplatValue()) { |
0 |
22856 |
if (SDValue Splat = cast(N)->getSplatValue()) { |
0 |
| 22857 |
Splat = peekThroughBitcasts(Splat); |
0 |
22857 |
Splat = peekThroughBitcasts(Splat); |
0 |
| 22858 |
EVT SrcVT = Splat.getValueType(); |
0 |
22858 |
EVT SrcVT = Splat.getValueType(); |
0 |
| 22859 |
if (SrcVT.isVector()) { |
0 |
22859 |
if (SrcVT.isVector()) { |
0 |
| 22860 |
unsigned NumElts = N->getNumOperands() * SrcVT.getVectorNumElements(); |
0 |
22860 |
unsigned NumElts = N->getNumOperands() * SrcVT.getVectorNumElements(); |
0 |
| 22861 |
EVT NewVT = EVT::getVectorVT(*DAG.getContext(), |
0 |
22861 |
EVT NewVT = EVT::getVectorVT(*DAG.getContext(), |
0 |
| 22862 |
SrcVT.getVectorElementType(), NumElts); |
--- |
22862 |
SrcVT.getVectorElementType(), NumElts); |
--- |
| 22863 |
if (!LegalTypes || TLI.isTypeLegal(NewVT)) { |
0 |
22863 |
if (!LegalTypes || TLI.isTypeLegal(NewVT)) { |
0 |
| 22864 |
SmallVector Ops(N->getNumOperands(), Splat); |
0 |
22864 |
SmallVector Ops(N->getNumOperands(), Splat); |
0 |
| 22865 |
SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), |
0 |
22865 |
SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), |
0 |
| 22866 |
NewVT, Ops); |
--- |
22866 |
NewVT, Ops); |
--- |
| 22867 |
return DAG.getBitcast(VT, Concat); |
0 |
22867 |
return DAG.getBitcast(VT, Concat); |
0 |
| 22868 |
} |
0 |
22868 |
} |
0 |
| 22869 |
} |
--- |
22869 |
} |
--- |
| 22870 |
} |
--- |
22870 |
} |
--- |
| 22871 |
} |
--- |
22871 |
} |
--- |
| 22872 |
|
--- |
22872 |
|
--- |
| 22873 |
// Check if we can express BUILD VECTOR via subvector extract. |
--- |
22873 |
// Check if we can express BUILD VECTOR via subvector extract. |
--- |
| 22874 |
if (!LegalTypes && (N->getNumOperands() > 1)) { |
0 |
22874 |
if (!LegalTypes && (N->getNumOperands() > 1)) { |
0 |
| 22875 |
SDValue Op0 = N->getOperand(0); |
0 |
22875 |
SDValue Op0 = N->getOperand(0); |
0 |
| 22876 |
auto checkElem = [&](SDValue Op) -> uint64_t { |
0 |
22876 |
auto checkElem = [&](SDValue Op) -> uint64_t { |
0 |
| 22877 |
if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && |
0 |
22877 |
if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && |
0 |
| 22878 |
(Op0.getOperand(0) == Op.getOperand(0))) |
0 |
22878 |
(Op0.getOperand(0) == Op.getOperand(0))) |
0 |
| 22879 |
if (auto CNode = dyn_cast(Op.getOperand(1))) |
0 |
22879 |
if (auto CNode = dyn_cast(Op.getOperand(1))) |
0 |
| 22880 |
return CNode->getZExtValue(); |
0 |
22880 |
return CNode->getZExtValue(); |
0 |
| 22881 |
return -1; |
0 |
22881 |
return -1; |
0 |
| 22882 |
}; |
0 |
22882 |
}; |
0 |
| 22883 |
|
--- |
22883 |
|
--- |
| 22884 |
int Offset = checkElem(Op0); |
0 |
22884 |
int Offset = checkElem(Op0); |
0 |
| 22885 |
for (unsigned i = 0; i < N->getNumOperands(); ++i) { |
0 |
22885 |
for (unsigned i = 0; i < N->getNumOperands(); ++i) { |
0 |
| 22886 |
if (Offset + i != checkElem(N->getOperand(i))) { |
0 |
22886 |
if (Offset + i != checkElem(N->getOperand(i))) { |
0 |
| 22887 |
Offset = -1; |
0 |
22887 |
Offset = -1; |
0 |
| 22888 |
break; |
0 |
22888 |
break; |
0 |
| 22889 |
} |
--- |
22889 |
} |
--- |
| 22890 |
} |
--- |
22890 |
} |
--- |
| 22891 |
|
--- |
22891 |
|
--- |
| 22892 |
if ((Offset == 0) && |
0 |
22892 |
if ((Offset == 0) && |
0 |
| 22893 |
(Op0.getOperand(0).getValueType() == N->getValueType(0))) |
0 |
22893 |
(Op0.getOperand(0).getValueType() == N->getValueType(0))) |
0 |
| 22894 |
return Op0.getOperand(0); |
0 |
22894 |
return Op0.getOperand(0); |
0 |
| 22895 |
if ((Offset != -1) && |
0 |
22895 |
if ((Offset != -1) && |
0 |
| 22896 |
((Offset % N->getValueType(0).getVectorNumElements()) == |
0 |
22896 |
((Offset % N->getValueType(0).getVectorNumElements()) == |
0 |
| 22897 |
0)) // IDX must be multiple of output size. |
--- |
22897 |
0)) // IDX must be multiple of output size. |
--- |
| 22898 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), N->getValueType(0), |
0 |
22898 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), N->getValueType(0), |
0 |
| 22899 |
Op0.getOperand(0), Op0.getOperand(1)); |
0 |
22899 |
Op0.getOperand(0), Op0.getOperand(1)); |
0 |
| 22900 |
} |
--- |
22900 |
} |
--- |
| 22901 |
|
--- |
22901 |
|
--- |
| 22902 |
if (SDValue V = convertBuildVecZextToZext(N)) |
0 |
22902 |
if (SDValue V = convertBuildVecZextToZext(N)) |
0 |
| 22903 |
return V; |
0 |
22903 |
return V; |
0 |
| 22904 |
|
--- |
22904 |
|
--- |
| 22905 |
if (SDValue V = convertBuildVecZextToBuildVecWithZeros(N)) |
0 |
22905 |
if (SDValue V = convertBuildVecZextToBuildVecWithZeros(N)) |
0 |
| 22906 |
return V; |
0 |
22906 |
return V; |
0 |
| 22907 |
|
--- |
22907 |
|
--- |
| 22908 |
if (SDValue V = reduceBuildVecExtToExtBuildVec(N)) |
0 |
22908 |
if (SDValue V = reduceBuildVecExtToExtBuildVec(N)) |
0 |
| 22909 |
return V; |
0 |
22909 |
return V; |
0 |
| 22910 |
|
--- |
22910 |
|
--- |
| 22911 |
if (SDValue V = reduceBuildVecTruncToBitCast(N)) |
0 |
22911 |
if (SDValue V = reduceBuildVecTruncToBitCast(N)) |
0 |
| 22912 |
return V; |
0 |
22912 |
return V; |
0 |
| 22913 |
|
--- |
22913 |
|
--- |
| 22914 |
if (SDValue V = reduceBuildVecToShuffle(N)) |
0 |
22914 |
if (SDValue V = reduceBuildVecToShuffle(N)) |
0 |
| 22915 |
return V; |
0 |
22915 |
return V; |
0 |
| 22916 |
|
--- |
22916 |
|
--- |
| 22917 |
// A splat of a single element is a SPLAT_VECTOR if supported on the target. |
--- |
22917 |
// A splat of a single element is a SPLAT_VECTOR if supported on the target. |
--- |
| 22918 |
// Do this late as some of the above may replace the splat. |
--- |
22918 |
// Do this late as some of the above may replace the splat. |
--- |
| 22919 |
if (TLI.getOperationAction(ISD::SPLAT_VECTOR, VT) != TargetLowering::Expand) |
0 |
22919 |
if (TLI.getOperationAction(ISD::SPLAT_VECTOR, VT) != TargetLowering::Expand) |
0 |
| 22920 |
if (SDValue V = cast(N)->getSplatValue()) { |
0 |
22920 |
if (SDValue V = cast(N)->getSplatValue()) { |
0 |
| 22921 |
assert(!V.isUndef() && "Splat of undef should have been handled earlier"); |
0 |
22921 |
assert(!V.isUndef() && "Splat of undef should have been handled earlier"); |
0 |
| 22922 |
return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, V); |
0 |
22922 |
return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, V); |
0 |
| 22923 |
} |
--- |
22923 |
} |
--- |
| 22924 |
|
--- |
22924 |
|
--- |
| 22925 |
return SDValue(); |
0 |
22925 |
return SDValue(); |
0 |
| 22926 |
} |
--- |
22926 |
} |
--- |
| 22927 |
|
--- |
22927 |
|
--- |
| 22928 |
static SDValue combineConcatVectorOfScalars(SDNode *N, SelectionDAG &DAG) { |
0 |
22928 |
static SDValue combineConcatVectorOfScalars(SDNode *N, SelectionDAG &DAG) { |
0 |
| 22929 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
22929 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 22930 |
EVT OpVT = N->getOperand(0).getValueType(); |
0 |
22930 |
EVT OpVT = N->getOperand(0).getValueType(); |
0 |
| 22931 |
|
--- |
22931 |
|
--- |
| 22932 |
// If the operands are legal vectors, leave them alone. |
--- |
22932 |
// If the operands are legal vectors, leave them alone. |
--- |
| 22933 |
if (TLI.isTypeLegal(OpVT) || OpVT.isScalableVector()) |
0 |
22933 |
if (TLI.isTypeLegal(OpVT) || OpVT.isScalableVector()) |
0 |
| 22934 |
return SDValue(); |
0 |
22934 |
return SDValue(); |
0 |
| 22935 |
|
--- |
22935 |
|
--- |
| 22936 |
SDLoc DL(N); |
0 |
22936 |
SDLoc DL(N); |
0 |
| 22937 |
EVT VT = N->getValueType(0); |
0 |
22937 |
EVT VT = N->getValueType(0); |
0 |
| 22938 |
SmallVector Ops; |
0 |
22938 |
SmallVector Ops; |
0 |
| 22939 |
|
--- |
22939 |
|
--- |
| 22940 |
EVT SVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits()); |
0 |
22940 |
EVT SVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits()); |
0 |
| 22941 |
SDValue ScalarUndef = DAG.getNode(ISD::UNDEF, DL, SVT); |
0 |
22941 |
SDValue ScalarUndef = DAG.getNode(ISD::UNDEF, DL, SVT); |
0 |
| 22942 |
|
--- |
22942 |
|
--- |
| 22943 |
// Keep track of what we encounter. |
--- |
22943 |
// Keep track of what we encounter. |
--- |
| 22944 |
bool AnyInteger = false; |
0 |
22944 |
bool AnyInteger = false; |
0 |
| 22945 |
bool AnyFP = false; |
0 |
22945 |
bool AnyFP = false; |
0 |
| 22946 |
for (const SDValue &Op : N->ops()) { |
0 |
22946 |
for (const SDValue &Op : N->ops()) { |
0 |
| 22947 |
if (ISD::BITCAST == Op.getOpcode() && |
0 |
22947 |
if (ISD::BITCAST == Op.getOpcode() && |
0 |
| 22948 |
!Op.getOperand(0).getValueType().isVector()) |
0 |
22948 |
!Op.getOperand(0).getValueType().isVector()) |
0 |
| 22949 |
Ops.push_back(Op.getOperand(0)); |
0 |
22949 |
Ops.push_back(Op.getOperand(0)); |
0 |
| 22950 |
else if (ISD::UNDEF == Op.getOpcode()) |
0 |
22950 |
else if (ISD::UNDEF == Op.getOpcode()) |
0 |
| 22951 |
Ops.push_back(ScalarUndef); |
0 |
22951 |
Ops.push_back(ScalarUndef); |
0 |
| 22952 |
else |
--- |
22952 |
else |
--- |
| 22953 |
return SDValue(); |
0 |
22953 |
return SDValue(); |
0 |
| 22954 |
|
--- |
22954 |
|
--- |
| 22955 |
// Note whether we encounter an integer or floating point scalar. |
--- |
22955 |
// Note whether we encounter an integer or floating point scalar. |
--- |
| 22956 |
// If it's neither, bail out, it could be something weird like x86mmx. |
--- |
22956 |
// If it's neither, bail out, it could be something weird like x86mmx. |
--- |
| 22957 |
EVT LastOpVT = Ops.back().getValueType(); |
0 |
22957 |
EVT LastOpVT = Ops.back().getValueType(); |
0 |
| 22958 |
if (LastOpVT.isFloatingPoint()) |
0 |
22958 |
if (LastOpVT.isFloatingPoint()) |
0 |
| 22959 |
AnyFP = true; |
0 |
22959 |
AnyFP = true; |
0 |
| 22960 |
else if (LastOpVT.isInteger()) |
0 |
22960 |
else if (LastOpVT.isInteger()) |
0 |
| 22961 |
AnyInteger = true; |
0 |
22961 |
AnyInteger = true; |
0 |
| 22962 |
else |
--- |
22962 |
else |
--- |
| 22963 |
return SDValue(); |
0 |
22963 |
return SDValue(); |
0 |
| 22964 |
} |
--- |
22964 |
} |
--- |
| 22965 |
|
--- |
22965 |
|
--- |
| 22966 |
// If any of the operands is a floating point scalar bitcast to a vector, |
--- |
22966 |
// If any of the operands is a floating point scalar bitcast to a vector, |
--- |
| 22967 |
// use floating point types throughout, and bitcast everything. |
--- |
22967 |
// use floating point types throughout, and bitcast everything. |
--- |
| 22968 |
// Replace UNDEFs by another scalar UNDEF node, of the final desired type. |
--- |
22968 |
// Replace UNDEFs by another scalar UNDEF node, of the final desired type. |
--- |
| 22969 |
if (AnyFP) { |
0 |
22969 |
if (AnyFP) { |
0 |
| 22970 |
SVT = EVT::getFloatingPointVT(OpVT.getSizeInBits()); |
0 |
22970 |
SVT = EVT::getFloatingPointVT(OpVT.getSizeInBits()); |
0 |
| 22971 |
ScalarUndef = DAG.getNode(ISD::UNDEF, DL, SVT); |
0 |
22971 |
ScalarUndef = DAG.getNode(ISD::UNDEF, DL, SVT); |
0 |
| 22972 |
if (AnyInteger) { |
0 |
22972 |
if (AnyInteger) { |
0 |
| 22973 |
for (SDValue &Op : Ops) { |
0 |
22973 |
for (SDValue &Op : Ops) { |
0 |
| 22974 |
if (Op.getValueType() == SVT) |
0 |
22974 |
if (Op.getValueType() == SVT) |
0 |
| 22975 |
continue; |
0 |
22975 |
continue; |
0 |
| 22976 |
if (Op.isUndef()) |
0 |
22976 |
if (Op.isUndef()) |
0 |
| 22977 |
Op = ScalarUndef; |
0 |
22977 |
Op = ScalarUndef; |
0 |
| 22978 |
else |
--- |
22978 |
else |
--- |
| 22979 |
Op = DAG.getBitcast(SVT, Op); |
0 |
22979 |
Op = DAG.getBitcast(SVT, Op); |
0 |
| 22980 |
} |
--- |
22980 |
} |
--- |
| 22981 |
} |
--- |
22981 |
} |
--- |
| 22982 |
} |
--- |
22982 |
} |
--- |
| 22983 |
|
--- |
22983 |
|
--- |
| 22984 |
EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SVT, |
0 |
22984 |
EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SVT, |
0 |
| 22985 |
VT.getSizeInBits() / SVT.getSizeInBits()); |
0 |
22985 |
VT.getSizeInBits() / SVT.getSizeInBits()); |
0 |
| 22986 |
return DAG.getBitcast(VT, DAG.getBuildVector(VecVT, DL, Ops)); |
0 |
22986 |
return DAG.getBitcast(VT, DAG.getBuildVector(VecVT, DL, Ops)); |
0 |
| 22987 |
} |
0 |
22987 |
} |
0 |
| 22988 |
|
--- |
22988 |
|
--- |
| 22989 |
// Attempt to merge nested concat_vectors/undefs. |
--- |
22989 |
// Attempt to merge nested concat_vectors/undefs. |
--- |
| 22990 |
// Fold concat_vectors(concat_vectors(x,y,z,w),u,u,concat_vectors(a,b,c,d)) |
--- |
22990 |
// Fold concat_vectors(concat_vectors(x,y,z,w),u,u,concat_vectors(a,b,c,d)) |
--- |
| 22991 |
// --> concat_vectors(x,y,z,w,u,u,u,u,u,u,u,u,a,b,c,d) |
--- |
22991 |
// --> concat_vectors(x,y,z,w,u,u,u,u,u,u,u,u,a,b,c,d) |
--- |
| 22992 |
static SDValue combineConcatVectorOfConcatVectors(SDNode *N, |
0 |
22992 |
static SDValue combineConcatVectorOfConcatVectors(SDNode *N, |
0 |
| 22993 |
SelectionDAG &DAG) { |
--- |
22993 |
SelectionDAG &DAG) { |
--- |
| 22994 |
EVT VT = N->getValueType(0); |
0 |
22994 |
EVT VT = N->getValueType(0); |
0 |
| 22995 |
|
--- |
22995 |
|
--- |
| 22996 |
// Ensure we're concatenating UNDEF and CONCAT_VECTORS nodes of similar types. |
--- |
22996 |
// Ensure we're concatenating UNDEF and CONCAT_VECTORS nodes of similar types. |
--- |
| 22997 |
EVT SubVT; |
0 |
22997 |
EVT SubVT; |
0 |
| 22998 |
SDValue FirstConcat; |
0 |
22998 |
SDValue FirstConcat; |
0 |
| 22999 |
for (const SDValue &Op : N->ops()) { |
0 |
22999 |
for (const SDValue &Op : N->ops()) { |
0 |
| 23000 |
if (Op.isUndef()) |
0 |
23000 |
if (Op.isUndef()) |
0 |
| 23001 |
continue; |
0 |
23001 |
continue; |
0 |
| 23002 |
if (Op.getOpcode() != ISD::CONCAT_VECTORS) |
0 |
23002 |
if (Op.getOpcode() != ISD::CONCAT_VECTORS) |
0 |
| 23003 |
return SDValue(); |
0 |
23003 |
return SDValue(); |
0 |
| 23004 |
if (!FirstConcat) { |
0 |
23004 |
if (!FirstConcat) { |
0 |
| 23005 |
SubVT = Op.getOperand(0).getValueType(); |
0 |
23005 |
SubVT = Op.getOperand(0).getValueType(); |
0 |
| 23006 |
if (!DAG.getTargetLoweringInfo().isTypeLegal(SubVT)) |
0 |
23006 |
if (!DAG.getTargetLoweringInfo().isTypeLegal(SubVT)) |
0 |
| 23007 |
return SDValue(); |
0 |
23007 |
return SDValue(); |
0 |
| 23008 |
FirstConcat = Op; |
0 |
23008 |
FirstConcat = Op; |
0 |
| 23009 |
continue; |
0 |
23009 |
continue; |
0 |
| 23010 |
} |
--- |
23010 |
} |
--- |
| 23011 |
if (SubVT != Op.getOperand(0).getValueType()) |
0 |
23011 |
if (SubVT != Op.getOperand(0).getValueType()) |
0 |
| 23012 |
return SDValue(); |
0 |
23012 |
return SDValue(); |
0 |
| 23013 |
} |
--- |
23013 |
} |
--- |
| 23014 |
assert(FirstConcat && "Concat of all-undefs found"); |
0 |
23014 |
assert(FirstConcat && "Concat of all-undefs found"); |
0 |
| 23015 |
|
--- |
23015 |
|
--- |
| 23016 |
SmallVector ConcatOps; |
0 |
23016 |
SmallVector ConcatOps; |
0 |
| 23017 |
for (const SDValue &Op : N->ops()) { |
0 |
23017 |
for (const SDValue &Op : N->ops()) { |
0 |
| 23018 |
if (Op.isUndef()) { |
0 |
23018 |
if (Op.isUndef()) { |
0 |
| 23019 |
ConcatOps.append(FirstConcat->getNumOperands(), DAG.getUNDEF(SubVT)); |
0 |
23019 |
ConcatOps.append(FirstConcat->getNumOperands(), DAG.getUNDEF(SubVT)); |
0 |
| 23020 |
continue; |
0 |
23020 |
continue; |
0 |
| 23021 |
} |
--- |
23021 |
} |
--- |
| 23022 |
ConcatOps.append(Op->op_begin(), Op->op_end()); |
0 |
23022 |
ConcatOps.append(Op->op_begin(), Op->op_end()); |
0 |
| 23023 |
} |
--- |
23023 |
} |
--- |
| 23024 |
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, ConcatOps); |
0 |
23024 |
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, ConcatOps); |
0 |
| 23025 |
} |
0 |
23025 |
} |
0 |
| 23026 |
|
--- |
23026 |
|
--- |
| 23027 |
// Check to see if this is a CONCAT_VECTORS of a bunch of EXTRACT_SUBVECTOR |
--- |
23027 |
// Check to see if this is a CONCAT_VECTORS of a bunch of EXTRACT_SUBVECTOR |
--- |
| 23028 |
// operations. If so, and if the EXTRACT_SUBVECTOR vector inputs come from at |
--- |
23028 |
// operations. If so, and if the EXTRACT_SUBVECTOR vector inputs come from at |
--- |
| 23029 |
// most two distinct vectors the same size as the result, attempt to turn this |
--- |
23029 |
// most two distinct vectors the same size as the result, attempt to turn this |
--- |
| 23030 |
// into a legal shuffle. |
--- |
23030 |
// into a legal shuffle. |
--- |
| 23031 |
static SDValue combineConcatVectorOfExtracts(SDNode *N, SelectionDAG &DAG) { |
0 |
23031 |
static SDValue combineConcatVectorOfExtracts(SDNode *N, SelectionDAG &DAG) { |
0 |
| 23032 |
EVT VT = N->getValueType(0); |
0 |
23032 |
EVT VT = N->getValueType(0); |
0 |
| 23033 |
EVT OpVT = N->getOperand(0).getValueType(); |
0 |
23033 |
EVT OpVT = N->getOperand(0).getValueType(); |
0 |
| 23034 |
|
--- |
23034 |
|
--- |
| 23035 |
// We currently can't generate an appropriate shuffle for a scalable vector. |
--- |
23035 |
// We currently can't generate an appropriate shuffle for a scalable vector. |
--- |
| 23036 |
if (VT.isScalableVector()) |
0 |
23036 |
if (VT.isScalableVector()) |
0 |
| 23037 |
return SDValue(); |
0 |
23037 |
return SDValue(); |
0 |
| 23038 |
|
--- |
23038 |
|
--- |
| 23039 |
int NumElts = VT.getVectorNumElements(); |
0 |
23039 |
int NumElts = VT.getVectorNumElements(); |
0 |
| 23040 |
int NumOpElts = OpVT.getVectorNumElements(); |
0 |
23040 |
int NumOpElts = OpVT.getVectorNumElements(); |
0 |
| 23041 |
|
--- |
23041 |
|
--- |
| 23042 |
SDValue SV0 = DAG.getUNDEF(VT), SV1 = DAG.getUNDEF(VT); |
0 |
23042 |
SDValue SV0 = DAG.getUNDEF(VT), SV1 = DAG.getUNDEF(VT); |
0 |
| 23043 |
SmallVector Mask; |
0 |
23043 |
SmallVector Mask; |
0 |
| 23044 |
|
--- |
23044 |
|
--- |
| 23045 |
for (SDValue Op : N->ops()) { |
0 |
23045 |
for (SDValue Op : N->ops()) { |
0 |
| 23046 |
Op = peekThroughBitcasts(Op); |
0 |
23046 |
Op = peekThroughBitcasts(Op); |
0 |
| 23047 |
|
--- |
23047 |
|
--- |
| 23048 |
// UNDEF nodes convert to UNDEF shuffle mask values. |
--- |
23048 |
// UNDEF nodes convert to UNDEF shuffle mask values. |
--- |
| 23049 |
if (Op.isUndef()) { |
0 |
23049 |
if (Op.isUndef()) { |
0 |
| 23050 |
Mask.append((unsigned)NumOpElts, -1); |
0 |
23050 |
Mask.append((unsigned)NumOpElts, -1); |
0 |
| 23051 |
continue; |
0 |
23051 |
continue; |
0 |
| 23052 |
} |
--- |
23052 |
} |
--- |
| 23053 |
|
--- |
23053 |
|
--- |
| 23054 |
if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) |
0 |
23054 |
if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) |
0 |
| 23055 |
return SDValue(); |
0 |
23055 |
return SDValue(); |
0 |
| 23056 |
|
--- |
23056 |
|
--- |
| 23057 |
// What vector are we extracting the subvector from and at what index? |
--- |
23057 |
// What vector are we extracting the subvector from and at what index? |
--- |
| 23058 |
SDValue ExtVec = Op.getOperand(0); |
0 |
23058 |
SDValue ExtVec = Op.getOperand(0); |
0 |
| 23059 |
int ExtIdx = Op.getConstantOperandVal(1); |
0 |
23059 |
int ExtIdx = Op.getConstantOperandVal(1); |
0 |
| 23060 |
|
--- |
23060 |
|
--- |
| 23061 |
// We want the EVT of the original extraction to correctly scale the |
--- |
23061 |
// We want the EVT of the original extraction to correctly scale the |
--- |
| 23062 |
// extraction index. |
--- |
23062 |
// extraction index. |
--- |
| 23063 |
EVT ExtVT = ExtVec.getValueType(); |
0 |
23063 |
EVT ExtVT = ExtVec.getValueType(); |
0 |
| 23064 |
ExtVec = peekThroughBitcasts(ExtVec); |
0 |
23064 |
ExtVec = peekThroughBitcasts(ExtVec); |
0 |
| 23065 |
|
--- |
23065 |
|
--- |
| 23066 |
// UNDEF nodes convert to UNDEF shuffle mask values. |
--- |
23066 |
// UNDEF nodes convert to UNDEF shuffle mask values. |
--- |
| 23067 |
if (ExtVec.isUndef()) { |
0 |
23067 |
if (ExtVec.isUndef()) { |
0 |
| 23068 |
Mask.append((unsigned)NumOpElts, -1); |
0 |
23068 |
Mask.append((unsigned)NumOpElts, -1); |
0 |
| 23069 |
continue; |
0 |
23069 |
continue; |
0 |
| 23070 |
} |
--- |
23070 |
} |
--- |
| 23071 |
|
--- |
23071 |
|
--- |
| 23072 |
// Ensure that we are extracting a subvector from a vector the same |
--- |
23072 |
// Ensure that we are extracting a subvector from a vector the same |
--- |
| 23073 |
// size as the result. |
--- |
23073 |
// size as the result. |
--- |
| 23074 |
if (ExtVT.getSizeInBits() != VT.getSizeInBits()) |
0 |
23074 |
if (ExtVT.getSizeInBits() != VT.getSizeInBits()) |
0 |
| 23075 |
return SDValue(); |
0 |
23075 |
return SDValue(); |
0 |
| 23076 |
|
--- |
23076 |
|
--- |
| 23077 |
// Scale the subvector index to account for any bitcast. |
--- |
23077 |
// Scale the subvector index to account for any bitcast. |
--- |
| 23078 |
int NumExtElts = ExtVT.getVectorNumElements(); |
0 |
23078 |
int NumExtElts = ExtVT.getVectorNumElements(); |
0 |
| 23079 |
if (0 == (NumExtElts % NumElts)) |
0 |
23079 |
if (0 == (NumExtElts % NumElts)) |
0 |
| 23080 |
ExtIdx /= (NumExtElts / NumElts); |
0 |
23080 |
ExtIdx /= (NumExtElts / NumElts); |
0 |
| 23081 |
else if (0 == (NumElts % NumExtElts)) |
0 |
23081 |
else if (0 == (NumElts % NumExtElts)) |
0 |
| 23082 |
ExtIdx *= (NumElts / NumExtElts); |
0 |
23082 |
ExtIdx *= (NumElts / NumExtElts); |
0 |
| 23083 |
else |
--- |
23083 |
else |
--- |
| 23084 |
return SDValue(); |
0 |
23084 |
return SDValue(); |
0 |
| 23085 |
|
--- |
23085 |
|
--- |
| 23086 |
// At most we can reference 2 inputs in the final shuffle. |
--- |
23086 |
// At most we can reference 2 inputs in the final shuffle. |
--- |
| 23087 |
if (SV0.isUndef() || SV0 == ExtVec) { |
0 |
23087 |
if (SV0.isUndef() || SV0 == ExtVec) { |
0 |
| 23088 |
SV0 = ExtVec; |
0 |
23088 |
SV0 = ExtVec; |
0 |
| 23089 |
for (int i = 0; i != NumOpElts; ++i) |
0 |
23089 |
for (int i = 0; i != NumOpElts; ++i) |
0 |
| 23090 |
Mask.push_back(i + ExtIdx); |
0 |
23090 |
Mask.push_back(i + ExtIdx); |
0 |
| 23091 |
} else if (SV1.isUndef() || SV1 == ExtVec) { |
0 |
23091 |
} else if (SV1.isUndef() || SV1 == ExtVec) { |
0 |
| 23092 |
SV1 = ExtVec; |
0 |
23092 |
SV1 = ExtVec; |
0 |
| 23093 |
for (int i = 0; i != NumOpElts; ++i) |
0 |
23093 |
for (int i = 0; i != NumOpElts; ++i) |
0 |
| 23094 |
Mask.push_back(i + ExtIdx + NumElts); |
0 |
23094 |
Mask.push_back(i + ExtIdx + NumElts); |
0 |
| 23095 |
} else { |
--- |
23095 |
} else { |
--- |
| 23096 |
return SDValue(); |
0 |
23096 |
return SDValue(); |
0 |
| 23097 |
} |
--- |
23097 |
} |
--- |
| 23098 |
} |
--- |
23098 |
} |
--- |
| 23099 |
|
--- |
23099 |
|
--- |
| 23100 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
23100 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 23101 |
return TLI.buildLegalVectorShuffle(VT, SDLoc(N), DAG.getBitcast(VT, SV0), |
0 |
23101 |
return TLI.buildLegalVectorShuffle(VT, SDLoc(N), DAG.getBitcast(VT, SV0), |
0 |
| 23102 |
DAG.getBitcast(VT, SV1), Mask, DAG); |
0 |
23102 |
DAG.getBitcast(VT, SV1), Mask, DAG); |
0 |
| 23103 |
} |
0 |
23103 |
} |
0 |
| 23104 |
|
--- |
23104 |
|
--- |
| 23105 |
static SDValue combineConcatVectorOfCasts(SDNode *N, SelectionDAG &DAG) { |
0 |
23105 |
static SDValue combineConcatVectorOfCasts(SDNode *N, SelectionDAG &DAG) { |
0 |
| 23106 |
unsigned CastOpcode = N->getOperand(0).getOpcode(); |
0 |
23106 |
unsigned CastOpcode = N->getOperand(0).getOpcode(); |
0 |
| 23107 |
switch (CastOpcode) { |
0 |
23107 |
switch (CastOpcode) { |
0 |
| 23108 |
case ISD::SINT_TO_FP: |
0 |
23108 |
case ISD::SINT_TO_FP: |
0 |
| 23109 |
case ISD::UINT_TO_FP: |
--- |
23109 |
case ISD::UINT_TO_FP: |
--- |
| 23110 |
case ISD::FP_TO_SINT: |
--- |
23110 |
case ISD::FP_TO_SINT: |
--- |
| 23111 |
case ISD::FP_TO_UINT: |
--- |
23111 |
case ISD::FP_TO_UINT: |
--- |
| 23112 |
// TODO: Allow more opcodes? |
--- |
23112 |
// TODO: Allow more opcodes? |
--- |
| 23113 |
// case ISD::BITCAST: |
--- |
23113 |
// case ISD::BITCAST: |
--- |
| 23114 |
// case ISD::TRUNCATE: |
--- |
23114 |
// case ISD::TRUNCATE: |
--- |
| 23115 |
// case ISD::ZERO_EXTEND: |
--- |
23115 |
// case ISD::ZERO_EXTEND: |
--- |
| 23116 |
// case ISD::SIGN_EXTEND: |
--- |
23116 |
// case ISD::SIGN_EXTEND: |
--- |
| 23117 |
// case ISD::FP_EXTEND: |
--- |
23117 |
// case ISD::FP_EXTEND: |
--- |
| 23118 |
break; |
0 |
23118 |
break; |
0 |
| 23119 |
default: |
0 |
23119 |
default: |
0 |
| 23120 |
return SDValue(); |
0 |
23120 |
return SDValue(); |
0 |
| 23121 |
} |
--- |
23121 |
} |
--- |
| 23122 |
|
--- |
23122 |
|
--- |
| 23123 |
EVT SrcVT = N->getOperand(0).getOperand(0).getValueType(); |
0 |
23123 |
EVT SrcVT = N->getOperand(0).getOperand(0).getValueType(); |
0 |
| 23124 |
if (!SrcVT.isVector()) |
0 |
23124 |
if (!SrcVT.isVector()) |
0 |
| 23125 |
return SDValue(); |
0 |
23125 |
return SDValue(); |
0 |
| 23126 |
|
--- |
23126 |
|
--- |
| 23127 |
// All operands of the concat must be the same kind of cast from the same |
--- |
23127 |
// All operands of the concat must be the same kind of cast from the same |
--- |
| 23128 |
// source type. |
--- |
23128 |
// source type. |
--- |
| 23129 |
SmallVector SrcOps; |
0 |
23129 |
SmallVector SrcOps; |
0 |
| 23130 |
for (SDValue Op : N->ops()) { |
0 |
23130 |
for (SDValue Op : N->ops()) { |
0 |
| 23131 |
if (Op.getOpcode() != CastOpcode || !Op.hasOneUse() || |
0 |
23131 |
if (Op.getOpcode() != CastOpcode || !Op.hasOneUse() || |
0 |
| 23132 |
Op.getOperand(0).getValueType() != SrcVT) |
0 |
23132 |
Op.getOperand(0).getValueType() != SrcVT) |
0 |
| 23133 |
return SDValue(); |
0 |
23133 |
return SDValue(); |
0 |
| 23134 |
SrcOps.push_back(Op.getOperand(0)); |
0 |
23134 |
SrcOps.push_back(Op.getOperand(0)); |
0 |
| 23135 |
} |
--- |
23135 |
} |
--- |
| 23136 |
|
--- |
23136 |
|
--- |
| 23137 |
// The wider cast must be supported by the target. This is unusual because |
--- |
23137 |
// The wider cast must be supported by the target. This is unusual because |
--- |
| 23138 |
// the operation support type parameter depends on the opcode. In addition, |
--- |
23138 |
// the operation support type parameter depends on the opcode. In addition, |
--- |
| 23139 |
// check the other type in the cast to make sure this is really legal. |
--- |
23139 |
// check the other type in the cast to make sure this is really legal. |
--- |
| 23140 |
EVT VT = N->getValueType(0); |
0 |
23140 |
EVT VT = N->getValueType(0); |
0 |
| 23141 |
EVT SrcEltVT = SrcVT.getVectorElementType(); |
0 |
23141 |
EVT SrcEltVT = SrcVT.getVectorElementType(); |
0 |
| 23142 |
ElementCount NumElts = SrcVT.getVectorElementCount() * N->getNumOperands(); |
0 |
23142 |
ElementCount NumElts = SrcVT.getVectorElementCount() * N->getNumOperands(); |
0 |
| 23143 |
EVT ConcatSrcVT = EVT::getVectorVT(*DAG.getContext(), SrcEltVT, NumElts); |
0 |
23143 |
EVT ConcatSrcVT = EVT::getVectorVT(*DAG.getContext(), SrcEltVT, NumElts); |
0 |
| 23144 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
23144 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 23145 |
switch (CastOpcode) { |
0 |
23145 |
switch (CastOpcode) { |
0 |
| 23146 |
case ISD::SINT_TO_FP: |
0 |
23146 |
case ISD::SINT_TO_FP: |
0 |
| 23147 |
case ISD::UINT_TO_FP: |
--- |
23147 |
case ISD::UINT_TO_FP: |
--- |
| 23148 |
if (!TLI.isOperationLegalOrCustom(CastOpcode, ConcatSrcVT) || |
0 |
23148 |
if (!TLI.isOperationLegalOrCustom(CastOpcode, ConcatSrcVT) || |
0 |
| 23149 |
!TLI.isTypeLegal(VT)) |
0 |
23149 |
!TLI.isTypeLegal(VT)) |
0 |
| 23150 |
return SDValue(); |
0 |
23150 |
return SDValue(); |
0 |
| 23151 |
break; |
0 |
23151 |
break; |
0 |
| 23152 |
case ISD::FP_TO_SINT: |
0 |
23152 |
case ISD::FP_TO_SINT: |
0 |
| 23153 |
case ISD::FP_TO_UINT: |
--- |
23153 |
case ISD::FP_TO_UINT: |
--- |
| 23154 |
if (!TLI.isOperationLegalOrCustom(CastOpcode, VT) || |
0 |
23154 |
if (!TLI.isOperationLegalOrCustom(CastOpcode, VT) || |
0 |
| 23155 |
!TLI.isTypeLegal(ConcatSrcVT)) |
0 |
23155 |
!TLI.isTypeLegal(ConcatSrcVT)) |
0 |
| 23156 |
return SDValue(); |
0 |
23156 |
return SDValue(); |
0 |
| 23157 |
break; |
0 |
23157 |
break; |
0 |
| 23158 |
default: |
0 |
23158 |
default: |
0 |
| 23159 |
llvm_unreachable("Unexpected cast opcode"); |
0 |
23159 |
llvm_unreachable("Unexpected cast opcode"); |
0 |
| 23160 |
} |
--- |
23160 |
} |
--- |
| 23161 |
|
--- |
23161 |
|
--- |
| 23162 |
// concat (cast X), (cast Y)... -> cast (concat X, Y...) |
--- |
23162 |
// concat (cast X), (cast Y)... -> cast (concat X, Y...) |
--- |
| 23163 |
SDLoc DL(N); |
0 |
23163 |
SDLoc DL(N); |
0 |
| 23164 |
SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatSrcVT, SrcOps); |
0 |
23164 |
SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatSrcVT, SrcOps); |
0 |
| 23165 |
return DAG.getNode(CastOpcode, DL, VT, NewConcat); |
0 |
23165 |
return DAG.getNode(CastOpcode, DL, VT, NewConcat); |
0 |
| 23166 |
} |
--- |
23166 |
} |
--- |
| 23167 |
|
--- |
23167 |
|
--- |
| 23168 |
// See if this is a simple CONCAT_VECTORS with no UNDEF operands, and if one of |
--- |
23168 |
// See if this is a simple CONCAT_VECTORS with no UNDEF operands, and if one of |
--- |
| 23169 |
// the operands is a SHUFFLE_VECTOR, and all other operands are also operands |
--- |
23169 |
// the operands is a SHUFFLE_VECTOR, and all other operands are also operands |
--- |
| 23170 |
// to that SHUFFLE_VECTOR, create wider SHUFFLE_VECTOR. |
--- |
23170 |
// to that SHUFFLE_VECTOR, create wider SHUFFLE_VECTOR. |
--- |
| 23171 |
static SDValue combineConcatVectorOfShuffleAndItsOperands( |
0 |
23171 |
static SDValue combineConcatVectorOfShuffleAndItsOperands( |
0 |
| 23172 |
SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalTypes, |
--- |
23172 |
SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalTypes, |
--- |
| 23173 |
bool LegalOperations) { |
--- |
23173 |
bool LegalOperations) { |
--- |
| 23174 |
EVT VT = N->getValueType(0); |
0 |
23174 |
EVT VT = N->getValueType(0); |
0 |
| 23175 |
EVT OpVT = N->getOperand(0).getValueType(); |
0 |
23175 |
EVT OpVT = N->getOperand(0).getValueType(); |
0 |
| 23176 |
if (VT.isScalableVector()) |
0 |
23176 |
if (VT.isScalableVector()) |
0 |
| 23177 |
return SDValue(); |
0 |
23177 |
return SDValue(); |
0 |
| 23178 |
|
--- |
23178 |
|
--- |
| 23179 |
// For now, only allow simple 2-operand concatenations. |
--- |
23179 |
// For now, only allow simple 2-operand concatenations. |
--- |
| 23180 |
if (N->getNumOperands() != 2) |
0 |
23180 |
if (N->getNumOperands() != 2) |
0 |
| 23181 |
return SDValue(); |
0 |
23181 |
return SDValue(); |
0 |
| 23182 |
|
--- |
23182 |
|
--- |
| 23183 |
// Don't create illegal types/shuffles when not allowed to. |
--- |
23183 |
// Don't create illegal types/shuffles when not allowed to. |
--- |
| 23184 |
if ((LegalTypes && !TLI.isTypeLegal(VT)) || |
0 |
23184 |
if ((LegalTypes && !TLI.isTypeLegal(VT)) || |
0 |
| 23185 |
(LegalOperations && |
0 |
23185 |
(LegalOperations && |
0 |
| 23186 |
!TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))) |
0 |
23186 |
!TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))) |
0 |
| 23187 |
return SDValue(); |
0 |
23187 |
return SDValue(); |
0 |
| 23188 |
|
--- |
23188 |
|
--- |
| 23189 |
// Analyze all of the operands of the CONCAT_VECTORS. Out of all of them, |
--- |
23189 |
// Analyze all of the operands of the CONCAT_VECTORS. Out of all of them, |
--- |
| 23190 |
// we want to find one that is: (1) a SHUFFLE_VECTOR (2) only used by us, |
--- |
23190 |
// we want to find one that is: (1) a SHUFFLE_VECTOR (2) only used by us, |
--- |
| 23191 |
// and (3) all operands of CONCAT_VECTORS must be either that SHUFFLE_VECTOR, |
--- |
23191 |
// and (3) all operands of CONCAT_VECTORS must be either that SHUFFLE_VECTOR, |
--- |
| 23192 |
// or one of the operands of that SHUFFLE_VECTOR (but not UNDEF!). |
--- |
23192 |
// or one of the operands of that SHUFFLE_VECTOR (but not UNDEF!). |
--- |
| 23193 |
// (4) and for now, the SHUFFLE_VECTOR must be unary. |
--- |
23193 |
// (4) and for now, the SHUFFLE_VECTOR must be unary. |
--- |
| 23194 |
ShuffleVectorSDNode *SVN = nullptr; |
0 |
23194 |
ShuffleVectorSDNode *SVN = nullptr; |
0 |
| 23195 |
for (SDValue Op : N->ops()) { |
0 |
23195 |
for (SDValue Op : N->ops()) { |
0 |
| 23196 |
if (auto *CurSVN = dyn_cast(Op); |
0 |
23196 |
if (auto *CurSVN = dyn_cast(Op); |
0 |
| 23197 |
CurSVN && CurSVN->getOperand(1).isUndef() && N->isOnlyUserOf(CurSVN) && |
0 |
23197 |
CurSVN && CurSVN->getOperand(1).isUndef() && N->isOnlyUserOf(CurSVN) && |
0 |
| 23198 |
all_of(N->ops(), [CurSVN](SDValue Op) { |
0 |
23198 |
all_of(N->ops(), [CurSVN](SDValue Op) { |
0 |
| 23199 |
// FIXME: can we allow UNDEF operands? |
--- |
23199 |
// FIXME: can we allow UNDEF operands? |
--- |
| 23200 |
return !Op.isUndef() && |
0 |
23200 |
return !Op.isUndef() && |
0 |
| 23201 |
(Op.getNode() == CurSVN || is_contained(CurSVN->ops(), Op)); |
0 |
23201 |
(Op.getNode() == CurSVN || is_contained(CurSVN->ops(), Op)); |
0 |
| 23202 |
})) { |
--- |
23202 |
})) { |
--- |
| 23203 |
SVN = CurSVN; |
0 |
23203 |
SVN = CurSVN; |
0 |
| 23204 |
break; |
0 |
23204 |
break; |
0 |
| 23205 |
} |
--- |
23205 |
} |
--- |
| 23206 |
} |
--- |
23206 |
} |
--- |
| 23207 |
if (!SVN) |
0 |
23207 |
if (!SVN) |
0 |
| 23208 |
return SDValue(); |
0 |
23208 |
return SDValue(); |
0 |
| 23209 |
|
--- |
23209 |
|
--- |
| 23210 |
// We are going to pad the shuffle operands, so any indice, that was picking |
--- |
23210 |
// We are going to pad the shuffle operands, so any indice, that was picking |
--- |
| 23211 |
// from the second operand, must be adjusted. |
--- |
23211 |
// from the second operand, must be adjusted. |
--- |
| 23212 |
SmallVector AdjustedMask; |
0 |
23212 |
SmallVector AdjustedMask; |
0 |
| 23213 |
AdjustedMask.reserve(SVN->getMask().size()); |
0 |
23213 |
AdjustedMask.reserve(SVN->getMask().size()); |
0 |
| 23214 |
assert(SVN->getOperand(1).isUndef() && "Expected unary shuffle!"); |
0 |
23214 |
assert(SVN->getOperand(1).isUndef() && "Expected unary shuffle!"); |
0 |
| 23215 |
append_range(AdjustedMask, SVN->getMask()); |
0 |
23215 |
append_range(AdjustedMask, SVN->getMask()); |
0 |
| 23216 |
|
--- |
23216 |
|
--- |
| 23217 |
// Identity masks for the operands of the (padded) shuffle. |
--- |
23217 |
// Identity masks for the operands of the (padded) shuffle. |
--- |
| 23218 |
SmallVector IdentityMask(2 * OpVT.getVectorNumElements()); |
0 |
23218 |
SmallVector IdentityMask(2 * OpVT.getVectorNumElements()); |
0 |
| 23219 |
MutableArrayRef FirstShufOpIdentityMask = |
--- |
23219 |
MutableArrayRef FirstShufOpIdentityMask = |
--- |
| 23220 |
MutableArrayRef(IdentityMask) |
0 |
23220 |
MutableArrayRef(IdentityMask) |
0 |
| 23221 |
.take_front(OpVT.getVectorNumElements()); |
0 |
23221 |
.take_front(OpVT.getVectorNumElements()); |
0 |
| 23222 |
MutableArrayRef SecondShufOpIdentityMask = |
--- |
23222 |
MutableArrayRef SecondShufOpIdentityMask = |
--- |
| 23223 |
MutableArrayRef(IdentityMask).take_back(OpVT.getVectorNumElements()); |
0 |
23223 |
MutableArrayRef(IdentityMask).take_back(OpVT.getVectorNumElements()); |
0 |
| 23224 |
std::iota(FirstShufOpIdentityMask.begin(), FirstShufOpIdentityMask.end(), 0); |
0 |
23224 |
std::iota(FirstShufOpIdentityMask.begin(), FirstShufOpIdentityMask.end(), 0); |
0 |
| 23225 |
std::iota(SecondShufOpIdentityMask.begin(), SecondShufOpIdentityMask.end(), |
0 |
23225 |
std::iota(SecondShufOpIdentityMask.begin(), SecondShufOpIdentityMask.end(), |
0 |
| 23226 |
VT.getVectorNumElements()); |
--- |
23226 |
VT.getVectorNumElements()); |
--- |
| 23227 |
|
--- |
23227 |
|
--- |
| 23228 |
// New combined shuffle mask. |
--- |
23228 |
// New combined shuffle mask. |
--- |
| 23229 |
SmallVector Mask; |
0 |
23229 |
SmallVector Mask; |
0 |
| 23230 |
Mask.reserve(VT.getVectorNumElements()); |
0 |
23230 |
Mask.reserve(VT.getVectorNumElements()); |
0 |
| 23231 |
for (SDValue Op : N->ops()) { |
0 |
23231 |
for (SDValue Op : N->ops()) { |
0 |
| 23232 |
assert(!Op.isUndef() && "Not expecting to concatenate UNDEF."); |
0 |
23232 |
assert(!Op.isUndef() && "Not expecting to concatenate UNDEF."); |
0 |
| 23233 |
if (Op.getNode() == SVN) { |
0 |
23233 |
if (Op.getNode() == SVN) { |
0 |
| 23234 |
append_range(Mask, AdjustedMask); |
0 |
23234 |
append_range(Mask, AdjustedMask); |
0 |
| 23235 |
continue; |
0 |
23235 |
continue; |
0 |
| 23236 |
} |
--- |
23236 |
} |
--- |
| 23237 |
if (Op == SVN->getOperand(0)) { |
0 |
23237 |
if (Op == SVN->getOperand(0)) { |
0 |
| 23238 |
append_range(Mask, FirstShufOpIdentityMask); |
0 |
23238 |
append_range(Mask, FirstShufOpIdentityMask); |
0 |
| 23239 |
continue; |
0 |
23239 |
continue; |
0 |
| 23240 |
} |
--- |
23240 |
} |
--- |
| 23241 |
if (Op == SVN->getOperand(1)) { |
0 |
23241 |
if (Op == SVN->getOperand(1)) { |
0 |
| 23242 |
append_range(Mask, SecondShufOpIdentityMask); |
0 |
23242 |
append_range(Mask, SecondShufOpIdentityMask); |
0 |
| 23243 |
continue; |
0 |
23243 |
continue; |
0 |
| 23244 |
} |
--- |
23244 |
} |
--- |
| 23245 |
llvm_unreachable("Unexpected operand!"); |
0 |
23245 |
llvm_unreachable("Unexpected operand!"); |
0 |
| 23246 |
} |
--- |
23246 |
} |
--- |
| 23247 |
|
--- |
23247 |
|
--- |
| 23248 |
// Don't create illegal shuffle masks. |
--- |
23248 |
// Don't create illegal shuffle masks. |
--- |
| 23249 |
if (!TLI.isShuffleMaskLegal(Mask, VT)) |
0 |
23249 |
if (!TLI.isShuffleMaskLegal(Mask, VT)) |
0 |
| 23250 |
return SDValue(); |
0 |
23250 |
return SDValue(); |
0 |
| 23251 |
|
--- |
23251 |
|
--- |
| 23252 |
// Pad the shuffle operands with UNDEF. |
--- |
23252 |
// Pad the shuffle operands with UNDEF. |
--- |
| 23253 |
SDLoc dl(N); |
0 |
23253 |
SDLoc dl(N); |
0 |
| 23254 |
std::array ShufOps; |
0 |
23254 |
std::array ShufOps; |
0 |
| 23255 |
for (auto I : zip(SVN->ops(), ShufOps)) { |
0 |
23255 |
for (auto I : zip(SVN->ops(), ShufOps)) { |
0 |
| 23256 |
SDValue ShufOp = std::get<0>(I); |
0 |
23256 |
SDValue ShufOp = std::get<0>(I); |
0 |
| 23257 |
SDValue &NewShufOp = std::get<1>(I); |
0 |
23257 |
SDValue &NewShufOp = std::get<1>(I); |
0 |
| 23258 |
if (ShufOp.isUndef()) |
0 |
23258 |
if (ShufOp.isUndef()) |
0 |
| 23259 |
NewShufOp = DAG.getUNDEF(VT); |
0 |
23259 |
NewShufOp = DAG.getUNDEF(VT); |
0 |
| 23260 |
else { |
--- |
23260 |
else { |
--- |
| 23261 |
SmallVector ShufOpParts(N->getNumOperands(), |
0 |
23261 |
SmallVector ShufOpParts(N->getNumOperands(), |
0 |
| 23262 |
DAG.getUNDEF(OpVT)); |
0 |
23262 |
DAG.getUNDEF(OpVT)); |
0 |
| 23263 |
ShufOpParts[0] = ShufOp; |
0 |
23263 |
ShufOpParts[0] = ShufOp; |
0 |
| 23264 |
NewShufOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, ShufOpParts); |
0 |
23264 |
NewShufOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, ShufOpParts); |
0 |
| 23265 |
} |
0 |
23265 |
} |
0 |
| 23266 |
} |
--- |
23266 |
} |
--- |
| 23267 |
// Finally, create the new wide shuffle. |
--- |
23267 |
// Finally, create the new wide shuffle. |
--- |
| 23268 |
return DAG.getVectorShuffle(VT, dl, ShufOps[0], ShufOps[1], Mask); |
0 |
23268 |
return DAG.getVectorShuffle(VT, dl, ShufOps[0], ShufOps[1], Mask); |
0 |
| 23269 |
} |
0 |
23269 |
} |
0 |
| 23270 |
|
--- |
23270 |
|
--- |
| 23271 |
SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { |
0 |
23271 |
SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { |
0 |
| 23272 |
// If we only have one input vector, we don't need to do any concatenation. |
--- |
23272 |
// If we only have one input vector, we don't need to do any concatenation. |
--- |
| 23273 |
if (N->getNumOperands() == 1) |
0 |
23273 |
if (N->getNumOperands() == 1) |
0 |
| 23274 |
return N->getOperand(0); |
0 |
23274 |
return N->getOperand(0); |
0 |
| 23275 |
|
--- |
23275 |
|
--- |
| 23276 |
// Check if all of the operands are undefs. |
--- |
23276 |
// Check if all of the operands are undefs. |
--- |
| 23277 |
EVT VT = N->getValueType(0); |
0 |
23277 |
EVT VT = N->getValueType(0); |
0 |
| 23278 |
if (ISD::allOperandsUndef(N)) |
0 |
23278 |
if (ISD::allOperandsUndef(N)) |
0 |
| 23279 |
return DAG.getUNDEF(VT); |
0 |
23279 |
return DAG.getUNDEF(VT); |
0 |
| 23280 |
|
--- |
23280 |
|
--- |
| 23281 |
// Optimize concat_vectors where all but the first of the vectors are undef. |
--- |
23281 |
// Optimize concat_vectors where all but the first of the vectors are undef. |
--- |
| 23282 |
if (all_of(drop_begin(N->ops()), |
0 |
23282 |
if (all_of(drop_begin(N->ops()), |
0 |
| 23283 |
[](const SDValue &Op) { return Op.isUndef(); })) { |
0 |
23283 |
[](const SDValue &Op) { return Op.isUndef(); })) { |
0 |
| 23284 |
SDValue In = N->getOperand(0); |
0 |
23284 |
SDValue In = N->getOperand(0); |
0 |
| 23285 |
assert(In.getValueType().isVector() && "Must concat vectors"); |
0 |
23285 |
assert(In.getValueType().isVector() && "Must concat vectors"); |
0 |
| 23286 |
|
--- |
23286 |
|
--- |
| 23287 |
// If the input is a concat_vectors, just make a larger concat by padding |
--- |
23287 |
// If the input is a concat_vectors, just make a larger concat by padding |
--- |
| 23288 |
// with smaller undefs. |
--- |
23288 |
// with smaller undefs. |
--- |
| 23289 |
// |
--- |
23289 |
// |
--- |
| 23290 |
// Legalizing in AArch64TargetLowering::LowerCONCAT_VECTORS() and combining |
--- |
23290 |
// Legalizing in AArch64TargetLowering::LowerCONCAT_VECTORS() and combining |
--- |
| 23291 |
// here could cause an infinite loop. That legalizing happens when LegalDAG |
--- |
23291 |
// here could cause an infinite loop. That legalizing happens when LegalDAG |
--- |
| 23292 |
// is true and input of AArch64TargetLowering::LowerCONCAT_VECTORS() is |
--- |
23292 |
// is true and input of AArch64TargetLowering::LowerCONCAT_VECTORS() is |
--- |
| 23293 |
// scalable. |
--- |
23293 |
// scalable. |
--- |
| 23294 |
if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse() && |
0 |
23294 |
if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse() && |
0 |
| 23295 |
!(LegalDAG && In.getValueType().isScalableVector())) { |
0 |
23295 |
!(LegalDAG && In.getValueType().isScalableVector())) { |
0 |
| 23296 |
unsigned NumOps = N->getNumOperands() * In.getNumOperands(); |
0 |
23296 |
unsigned NumOps = N->getNumOperands() * In.getNumOperands(); |
0 |
| 23297 |
SmallVector Ops(In->op_begin(), In->op_end()); |
0 |
23297 |
SmallVector Ops(In->op_begin(), In->op_end()); |
0 |
| 23298 |
Ops.resize(NumOps, DAG.getUNDEF(Ops[0].getValueType())); |
0 |
23298 |
Ops.resize(NumOps, DAG.getUNDEF(Ops[0].getValueType())); |
0 |
| 23299 |
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops); |
0 |
23299 |
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops); |
0 |
| 23300 |
} |
0 |
23300 |
} |
0 |
| 23301 |
|
--- |
23301 |
|
--- |
| 23302 |
SDValue Scalar = peekThroughOneUseBitcasts(In); |
0 |
23302 |
SDValue Scalar = peekThroughOneUseBitcasts(In); |
0 |
| 23303 |
|
--- |
23303 |
|
--- |
| 23304 |
// concat_vectors(scalar_to_vector(scalar), undef) -> |
--- |
23304 |
// concat_vectors(scalar_to_vector(scalar), undef) -> |
--- |
| 23305 |
// scalar_to_vector(scalar) |
--- |
23305 |
// scalar_to_vector(scalar) |
--- |
| 23306 |
if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && |
0 |
23306 |
if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR && |
0 |
| 23307 |
Scalar.hasOneUse()) { |
0 |
23307 |
Scalar.hasOneUse()) { |
0 |
| 23308 |
EVT SVT = Scalar.getValueType().getVectorElementType(); |
0 |
23308 |
EVT SVT = Scalar.getValueType().getVectorElementType(); |
0 |
| 23309 |
if (SVT == Scalar.getOperand(0).getValueType()) |
0 |
23309 |
if (SVT == Scalar.getOperand(0).getValueType()) |
0 |
| 23310 |
Scalar = Scalar.getOperand(0); |
0 |
23310 |
Scalar = Scalar.getOperand(0); |
0 |
| 23311 |
} |
--- |
23311 |
} |
--- |
| 23312 |
|
--- |
23312 |
|
--- |
| 23313 |
// concat_vectors(scalar, undef) -> scalar_to_vector(scalar) |
--- |
23313 |
// concat_vectors(scalar, undef) -> scalar_to_vector(scalar) |
--- |
| 23314 |
if (!Scalar.getValueType().isVector()) { |
0 |
23314 |
if (!Scalar.getValueType().isVector()) { |
0 |
| 23315 |
// If the bitcast type isn't legal, it might be a trunc of a legal type; |
--- |
23315 |
// If the bitcast type isn't legal, it might be a trunc of a legal type; |
--- |
| 23316 |
// look through the trunc so we can still do the transform: |
--- |
23316 |
// look through the trunc so we can still do the transform: |
--- |
| 23317 |
// concat_vectors(trunc(scalar), undef) -> scalar_to_vector(scalar) |
--- |
23317 |
// concat_vectors(trunc(scalar), undef) -> scalar_to_vector(scalar) |
--- |
| 23318 |
if (Scalar->getOpcode() == ISD::TRUNCATE && |
0 |
23318 |
if (Scalar->getOpcode() == ISD::TRUNCATE && |
0 |
| 23319 |
!TLI.isTypeLegal(Scalar.getValueType()) && |
0 |
23319 |
!TLI.isTypeLegal(Scalar.getValueType()) && |
0 |
| 23320 |
TLI.isTypeLegal(Scalar->getOperand(0).getValueType())) |
0 |
23320 |
TLI.isTypeLegal(Scalar->getOperand(0).getValueType())) |
0 |
| 23321 |
Scalar = Scalar->getOperand(0); |
0 |
23321 |
Scalar = Scalar->getOperand(0); |
0 |
| 23322 |
|
--- |
23322 |
|
--- |
| 23323 |
EVT SclTy = Scalar.getValueType(); |
0 |
23323 |
EVT SclTy = Scalar.getValueType(); |
0 |
| 23324 |
|
--- |
23324 |
|
--- |
| 23325 |
if (!SclTy.isFloatingPoint() && !SclTy.isInteger()) |
0 |
23325 |
if (!SclTy.isFloatingPoint() && !SclTy.isInteger()) |
0 |
| 23326 |
return SDValue(); |
0 |
23326 |
return SDValue(); |
0 |
| 23327 |
|
--- |
23327 |
|
--- |
| 23328 |
// Bail out if the vector size is not a multiple of the scalar size. |
--- |
23328 |
// Bail out if the vector size is not a multiple of the scalar size. |
--- |
| 23329 |
if (VT.getSizeInBits() % SclTy.getSizeInBits()) |
0 |
23329 |
if (VT.getSizeInBits() % SclTy.getSizeInBits()) |
0 |
| 23330 |
return SDValue(); |
0 |
23330 |
return SDValue(); |
0 |
| 23331 |
|
--- |
23331 |
|
--- |
| 23332 |
unsigned VNTNumElms = VT.getSizeInBits() / SclTy.getSizeInBits(); |
0 |
23332 |
unsigned VNTNumElms = VT.getSizeInBits() / SclTy.getSizeInBits(); |
0 |
| 23333 |
if (VNTNumElms < 2) |
0 |
23333 |
if (VNTNumElms < 2) |
0 |
| 23334 |
return SDValue(); |
0 |
23334 |
return SDValue(); |
0 |
| 23335 |
|
--- |
23335 |
|
--- |
| 23336 |
EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy, VNTNumElms); |
0 |
23336 |
EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy, VNTNumElms); |
0 |
| 23337 |
if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType())) |
0 |
23337 |
if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType())) |
0 |
| 23338 |
return SDValue(); |
0 |
23338 |
return SDValue(); |
0 |
| 23339 |
|
--- |
23339 |
|
--- |
| 23340 |
SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), NVT, Scalar); |
0 |
23340 |
SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), NVT, Scalar); |
0 |
| 23341 |
return DAG.getBitcast(VT, Res); |
0 |
23341 |
return DAG.getBitcast(VT, Res); |
0 |
| 23342 |
} |
--- |
23342 |
} |
--- |
| 23343 |
} |
--- |
23343 |
} |
--- |
| 23344 |
|
--- |
23344 |
|
--- |
| 23345 |
// Fold any combination of BUILD_VECTOR or UNDEF nodes into one BUILD_VECTOR. |
--- |
23345 |
// Fold any combination of BUILD_VECTOR or UNDEF nodes into one BUILD_VECTOR. |
--- |
| 23346 |
// We have already tested above for an UNDEF only concatenation. |
--- |
23346 |
// We have already tested above for an UNDEF only concatenation. |
--- |
| 23347 |
// fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...)) |
--- |
23347 |
// fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...)) |
--- |
| 23348 |
// -> (BUILD_VECTOR A, B, ..., C, D, ...) |
--- |
23348 |
// -> (BUILD_VECTOR A, B, ..., C, D, ...) |
--- |
| 23349 |
auto IsBuildVectorOrUndef = [](const SDValue &Op) { |
0 |
23349 |
auto IsBuildVectorOrUndef = [](const SDValue &Op) { |
0 |
| 23350 |
return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode(); |
0 |
23350 |
return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode(); |
0 |
| 23351 |
}; |
--- |
23351 |
}; |
--- |
| 23352 |
if (llvm::all_of(N->ops(), IsBuildVectorOrUndef)) { |
0 |
23352 |
if (llvm::all_of(N->ops(), IsBuildVectorOrUndef)) { |
0 |
| 23353 |
SmallVector Opnds; |
0 |
23353 |
SmallVector Opnds; |
0 |
| 23354 |
EVT SVT = VT.getScalarType(); |
0 |
23354 |
EVT SVT = VT.getScalarType(); |
0 |
| 23355 |
|
--- |
23355 |
|
--- |
| 23356 |
EVT MinVT = SVT; |
0 |
23356 |
EVT MinVT = SVT; |
0 |
| 23357 |
if (!SVT.isFloatingPoint()) { |
0 |
23357 |
if (!SVT.isFloatingPoint()) { |
0 |
| 23358 |
// If BUILD_VECTOR are from built from integer, they may have different |
--- |
23358 |
// If BUILD_VECTOR are from built from integer, they may have different |
--- |
| 23359 |
// operand types. Get the smallest type and truncate all operands to it. |
--- |
23359 |
// operand types. Get the smallest type and truncate all operands to it. |
--- |
| 23360 |
bool FoundMinVT = false; |
0 |
23360 |
bool FoundMinVT = false; |
0 |
| 23361 |
for (const SDValue &Op : N->ops()) |
0 |
23361 |
for (const SDValue &Op : N->ops()) |
0 |
| 23362 |
if (ISD::BUILD_VECTOR == Op.getOpcode()) { |
0 |
23362 |
if (ISD::BUILD_VECTOR == Op.getOpcode()) { |
0 |
| 23363 |
EVT OpSVT = Op.getOperand(0).getValueType(); |
0 |
23363 |
EVT OpSVT = Op.getOperand(0).getValueType(); |
0 |
| 23364 |
MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT; |
0 |
23364 |
MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT; |
0 |
| 23365 |
FoundMinVT = true; |
0 |
23365 |
FoundMinVT = true; |
0 |
| 23366 |
} |
--- |
23366 |
} |
--- |
| 23367 |
assert(FoundMinVT && "Concat vector type mismatch"); |
0 |
23367 |
assert(FoundMinVT && "Concat vector type mismatch"); |
0 |
| 23368 |
} |
--- |
23368 |
} |
--- |
| 23369 |
|
--- |
23369 |
|
--- |
| 23370 |
for (const SDValue &Op : N->ops()) { |
0 |
23370 |
for (const SDValue &Op : N->ops()) { |
0 |
| 23371 |
EVT OpVT = Op.getValueType(); |
0 |
23371 |
EVT OpVT = Op.getValueType(); |
0 |
| 23372 |
unsigned NumElts = OpVT.getVectorNumElements(); |
0 |
23372 |
unsigned NumElts = OpVT.getVectorNumElements(); |
0 |
| 23373 |
|
--- |
23373 |
|
--- |
| 23374 |
if (ISD::UNDEF == Op.getOpcode()) |
0 |
23374 |
if (ISD::UNDEF == Op.getOpcode()) |
0 |
| 23375 |
Opnds.append(NumElts, DAG.getUNDEF(MinVT)); |
0 |
23375 |
Opnds.append(NumElts, DAG.getUNDEF(MinVT)); |
0 |
| 23376 |
|
--- |
23376 |
|
--- |
| 23377 |
if (ISD::BUILD_VECTOR == Op.getOpcode()) { |
0 |
23377 |
if (ISD::BUILD_VECTOR == Op.getOpcode()) { |
0 |
| 23378 |
if (SVT.isFloatingPoint()) { |
0 |
23378 |
if (SVT.isFloatingPoint()) { |
0 |
| 23379 |
assert(SVT == OpVT.getScalarType() && "Concat vector type mismatch"); |
0 |
23379 |
assert(SVT == OpVT.getScalarType() && "Concat vector type mismatch"); |
0 |
| 23380 |
Opnds.append(Op->op_begin(), Op->op_begin() + NumElts); |
0 |
23380 |
Opnds.append(Op->op_begin(), Op->op_begin() + NumElts); |
0 |
| 23381 |
} else { |
--- |
23381 |
} else { |
--- |
| 23382 |
for (unsigned i = 0; i != NumElts; ++i) |
0 |
23382 |
for (unsigned i = 0; i != NumElts; ++i) |
0 |
| 23383 |
Opnds.push_back( |
0 |
23383 |
Opnds.push_back( |
0 |
| 23384 |
DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinVT, Op.getOperand(i))); |
0 |
23384 |
DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinVT, Op.getOperand(i))); |
0 |
| 23385 |
} |
--- |
23385 |
} |
--- |
| 23386 |
} |
--- |
23386 |
} |
--- |
| 23387 |
} |
--- |
23387 |
} |
--- |
| 23388 |
|
--- |
23388 |
|
--- |
| 23389 |
assert(VT.getVectorNumElements() == Opnds.size() && |
0 |
23389 |
assert(VT.getVectorNumElements() == Opnds.size() && |
0 |
| 23390 |
"Concat vector type mismatch"); |
--- |
23390 |
"Concat vector type mismatch"); |
--- |
| 23391 |
return DAG.getBuildVector(VT, SDLoc(N), Opnds); |
0 |
23391 |
return DAG.getBuildVector(VT, SDLoc(N), Opnds); |
0 |
| 23392 |
} |
0 |
23392 |
} |
0 |
| 23393 |
|
--- |
23393 |
|
--- |
| 23394 |
// Fold CONCAT_VECTORS of only bitcast scalars (or undef) to BUILD_VECTOR. |
--- |
23394 |
// Fold CONCAT_VECTORS of only bitcast scalars (or undef) to BUILD_VECTOR. |
--- |
| 23395 |
// FIXME: Add support for concat_vectors(bitcast(vec0),bitcast(vec1),...). |
--- |
23395 |
// FIXME: Add support for concat_vectors(bitcast(vec0),bitcast(vec1),...). |
--- |
| 23396 |
if (SDValue V = combineConcatVectorOfScalars(N, DAG)) |
0 |
23396 |
if (SDValue V = combineConcatVectorOfScalars(N, DAG)) |
0 |
| 23397 |
return V; |
0 |
23397 |
return V; |
0 |
| 23398 |
|
--- |
23398 |
|
--- |
| 23399 |
if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT)) { |
0 |
23399 |
if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT)) { |
0 |
| 23400 |
// Fold CONCAT_VECTORS of CONCAT_VECTORS (or undef) to VECTOR_SHUFFLE. |
--- |
23400 |
// Fold CONCAT_VECTORS of CONCAT_VECTORS (or undef) to VECTOR_SHUFFLE. |
--- |
| 23401 |
if (SDValue V = combineConcatVectorOfConcatVectors(N, DAG)) |
0 |
23401 |
if (SDValue V = combineConcatVectorOfConcatVectors(N, DAG)) |
0 |
| 23402 |
return V; |
0 |
23402 |
return V; |
0 |
| 23403 |
|
--- |
23403 |
|
--- |
| 23404 |
// Fold CONCAT_VECTORS of EXTRACT_SUBVECTOR (or undef) to VECTOR_SHUFFLE. |
--- |
23404 |
// Fold CONCAT_VECTORS of EXTRACT_SUBVECTOR (or undef) to VECTOR_SHUFFLE. |
--- |
| 23405 |
if (SDValue V = combineConcatVectorOfExtracts(N, DAG)) |
0 |
23405 |
if (SDValue V = combineConcatVectorOfExtracts(N, DAG)) |
0 |
| 23406 |
return V; |
0 |
23406 |
return V; |
0 |
| 23407 |
} |
--- |
23407 |
} |
--- |
| 23408 |
|
--- |
23408 |
|
--- |
| 23409 |
if (SDValue V = combineConcatVectorOfCasts(N, DAG)) |
0 |
23409 |
if (SDValue V = combineConcatVectorOfCasts(N, DAG)) |
0 |
| 23410 |
return V; |
0 |
23410 |
return V; |
0 |
| 23411 |
|
--- |
23411 |
|
--- |
| 23412 |
if (SDValue V = combineConcatVectorOfShuffleAndItsOperands( |
0 |
23412 |
if (SDValue V = combineConcatVectorOfShuffleAndItsOperands( |
0 |
| 23413 |
N, DAG, TLI, LegalTypes, LegalOperations)) |
0 |
23413 |
N, DAG, TLI, LegalTypes, LegalOperations)) |
0 |
| 23414 |
return V; |
0 |
23414 |
return V; |
0 |
| 23415 |
|
--- |
23415 |
|
--- |
| 23416 |
// Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR |
--- |
23416 |
// Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR |
--- |
| 23417 |
// nodes often generate nop CONCAT_VECTOR nodes. Scan the CONCAT_VECTOR |
--- |
23417 |
// nodes often generate nop CONCAT_VECTOR nodes. Scan the CONCAT_VECTOR |
--- |
| 23418 |
// operands and look for a CONCAT operations that place the incoming vectors |
--- |
23418 |
// operands and look for a CONCAT operations that place the incoming vectors |
--- |
| 23419 |
// at the exact same location. |
--- |
23419 |
// at the exact same location. |
--- |
| 23420 |
// |
--- |
23420 |
// |
--- |
| 23421 |
// For scalable vectors, EXTRACT_SUBVECTOR indexes are implicitly scaled. |
--- |
23421 |
// For scalable vectors, EXTRACT_SUBVECTOR indexes are implicitly scaled. |
--- |
| 23422 |
SDValue SingleSource = SDValue(); |
0 |
23422 |
SDValue SingleSource = SDValue(); |
0 |
| 23423 |
unsigned PartNumElem = |
--- |
23423 |
unsigned PartNumElem = |
--- |
| 23424 |
N->getOperand(0).getValueType().getVectorMinNumElements(); |
0 |
23424 |
N->getOperand(0).getValueType().getVectorMinNumElements(); |
0 |
| 23425 |
|
--- |
23425 |
|
--- |
| 23426 |
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { |
0 |
23426 |
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { |
0 |
| 23427 |
SDValue Op = N->getOperand(i); |
0 |
23427 |
SDValue Op = N->getOperand(i); |
0 |
| 23428 |
|
--- |
23428 |
|
--- |
| 23429 |
if (Op.isUndef()) |
0 |
23429 |
if (Op.isUndef()) |
0 |
| 23430 |
continue; |
0 |
23430 |
continue; |
0 |
| 23431 |
|
--- |
23431 |
|
--- |
| 23432 |
// Check if this is the identity extract: |
--- |
23432 |
// Check if this is the identity extract: |
--- |
| 23433 |
if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) |
0 |
23433 |
if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) |
0 |
| 23434 |
return SDValue(); |
0 |
23434 |
return SDValue(); |
0 |
| 23435 |
|
--- |
23435 |
|
--- |
| 23436 |
// Find the single incoming vector for the extract_subvector. |
--- |
23436 |
// Find the single incoming vector for the extract_subvector. |
--- |
| 23437 |
if (SingleSource.getNode()) { |
0 |
23437 |
if (SingleSource.getNode()) { |
0 |
| 23438 |
if (Op.getOperand(0) != SingleSource) |
0 |
23438 |
if (Op.getOperand(0) != SingleSource) |
0 |
| 23439 |
return SDValue(); |
0 |
23439 |
return SDValue(); |
0 |
| 23440 |
} else { |
--- |
23440 |
} else { |
--- |
| 23441 |
SingleSource = Op.getOperand(0); |
0 |
23441 |
SingleSource = Op.getOperand(0); |
0 |
| 23442 |
|
--- |
23442 |
|
--- |
| 23443 |
// Check the source type is the same as the type of the result. |
--- |
23443 |
// Check the source type is the same as the type of the result. |
--- |
| 23444 |
// If not, this concat may extend the vector, so we can not |
--- |
23444 |
// If not, this concat may extend the vector, so we can not |
--- |
| 23445 |
// optimize it away. |
--- |
23445 |
// optimize it away. |
--- |
| 23446 |
if (SingleSource.getValueType() != N->getValueType(0)) |
0 |
23446 |
if (SingleSource.getValueType() != N->getValueType(0)) |
0 |
| 23447 |
return SDValue(); |
0 |
23447 |
return SDValue(); |
0 |
| 23448 |
} |
--- |
23448 |
} |
--- |
| 23449 |
|
--- |
23449 |
|
--- |
| 23450 |
// Check that we are reading from the identity index. |
--- |
23450 |
// Check that we are reading from the identity index. |
--- |
| 23451 |
unsigned IdentityIndex = i * PartNumElem; |
0 |
23451 |
unsigned IdentityIndex = i * PartNumElem; |
0 |
| 23452 |
if (Op.getConstantOperandAPInt(1) != IdentityIndex) |
0 |
23452 |
if (Op.getConstantOperandAPInt(1) != IdentityIndex) |
0 |
| 23453 |
return SDValue(); |
0 |
23453 |
return SDValue(); |
0 |
| 23454 |
} |
--- |
23454 |
} |
--- |
| 23455 |
|
--- |
23455 |
|
--- |
| 23456 |
if (SingleSource.getNode()) |
0 |
23456 |
if (SingleSource.getNode()) |
0 |
| 23457 |
return SingleSource; |
0 |
23457 |
return SingleSource; |
0 |
| 23458 |
|
--- |
23458 |
|
--- |
| 23459 |
return SDValue(); |
0 |
23459 |
return SDValue(); |
0 |
| 23460 |
} |
--- |
23460 |
} |
--- |
| 23461 |
|
--- |
23461 |
|
--- |
| 23462 |
// Helper that peeks through INSERT_SUBVECTOR/CONCAT_VECTORS to find |
--- |
23462 |
// Helper that peeks through INSERT_SUBVECTOR/CONCAT_VECTORS to find |
--- |
| 23463 |
// if the subvector can be sourced for free. |
--- |
23463 |
// if the subvector can be sourced for free. |
--- |
| 23464 |
static SDValue getSubVectorSrc(SDValue V, SDValue Index, EVT SubVT) { |
0 |
23464 |
static SDValue getSubVectorSrc(SDValue V, SDValue Index, EVT SubVT) { |
0 |
| 23465 |
if (V.getOpcode() == ISD::INSERT_SUBVECTOR && |
0 |
23465 |
if (V.getOpcode() == ISD::INSERT_SUBVECTOR && |
0 |
| 23466 |
V.getOperand(1).getValueType() == SubVT && V.getOperand(2) == Index) { |
0 |
23466 |
V.getOperand(1).getValueType() == SubVT && V.getOperand(2) == Index) { |
0 |
| 23467 |
return V.getOperand(1); |
0 |
23467 |
return V.getOperand(1); |
0 |
| 23468 |
} |
--- |
23468 |
} |
--- |
| 23469 |
auto *IndexC = dyn_cast(Index); |
0 |
23469 |
auto *IndexC = dyn_cast(Index); |
0 |
| 23470 |
if (IndexC && V.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
23470 |
if (IndexC && V.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
| 23471 |
V.getOperand(0).getValueType() == SubVT && |
0 |
23471 |
V.getOperand(0).getValueType() == SubVT && |
0 |
| 23472 |
(IndexC->getZExtValue() % SubVT.getVectorMinNumElements()) == 0) { |
0 |
23472 |
(IndexC->getZExtValue() % SubVT.getVectorMinNumElements()) == 0) { |
0 |
| 23473 |
uint64_t SubIdx = IndexC->getZExtValue() / SubVT.getVectorMinNumElements(); |
0 |
23473 |
uint64_t SubIdx = IndexC->getZExtValue() / SubVT.getVectorMinNumElements(); |
0 |
| 23474 |
return V.getOperand(SubIdx); |
0 |
23474 |
return V.getOperand(SubIdx); |
0 |
| 23475 |
} |
--- |
23475 |
} |
--- |
| 23476 |
return SDValue(); |
0 |
23476 |
return SDValue(); |
0 |
| 23477 |
} |
--- |
23477 |
} |
--- |
| 23478 |
|
--- |
23478 |
|
--- |
| 23479 |
static SDValue narrowInsertExtractVectorBinOp(SDNode *Extract, |
0 |
23479 |
static SDValue narrowInsertExtractVectorBinOp(SDNode *Extract, |
0 |
| 23480 |
SelectionDAG &DAG, |
--- |
23480 |
SelectionDAG &DAG, |
--- |
| 23481 |
bool LegalOperations) { |
--- |
23481 |
bool LegalOperations) { |
--- |
| 23482 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
23482 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 23483 |
SDValue BinOp = Extract->getOperand(0); |
0 |
23483 |
SDValue BinOp = Extract->getOperand(0); |
0 |
| 23484 |
unsigned BinOpcode = BinOp.getOpcode(); |
0 |
23484 |
unsigned BinOpcode = BinOp.getOpcode(); |
0 |
| 23485 |
if (!TLI.isBinOp(BinOpcode) || BinOp->getNumValues() != 1) |
0 |
23485 |
if (!TLI.isBinOp(BinOpcode) || BinOp->getNumValues() != 1) |
0 |
| 23486 |
return SDValue(); |
0 |
23486 |
return SDValue(); |
0 |
| 23487 |
|
--- |
23487 |
|
--- |
| 23488 |
EVT VecVT = BinOp.getValueType(); |
0 |
23488 |
EVT VecVT = BinOp.getValueType(); |
0 |
| 23489 |
SDValue Bop0 = BinOp.getOperand(0), Bop1 = BinOp.getOperand(1); |
0 |
23489 |
SDValue Bop0 = BinOp.getOperand(0), Bop1 = BinOp.getOperand(1); |
0 |
| 23490 |
if (VecVT != Bop0.getValueType() || VecVT != Bop1.getValueType()) |
0 |
23490 |
if (VecVT != Bop0.getValueType() || VecVT != Bop1.getValueType()) |
0 |
| 23491 |
return SDValue(); |
0 |
23491 |
return SDValue(); |
0 |
| 23492 |
|
--- |
23492 |
|
--- |
| 23493 |
SDValue Index = Extract->getOperand(1); |
0 |
23493 |
SDValue Index = Extract->getOperand(1); |
0 |
| 23494 |
EVT SubVT = Extract->getValueType(0); |
0 |
23494 |
EVT SubVT = Extract->getValueType(0); |
0 |
| 23495 |
if (!TLI.isOperationLegalOrCustom(BinOpcode, SubVT, LegalOperations)) |
0 |
23495 |
if (!TLI.isOperationLegalOrCustom(BinOpcode, SubVT, LegalOperations)) |
0 |
| 23496 |
return SDValue(); |
0 |
23496 |
return SDValue(); |
0 |
| 23497 |
|
--- |
23497 |
|
--- |
| 23498 |
SDValue Sub0 = getSubVectorSrc(Bop0, Index, SubVT); |
0 |
23498 |
SDValue Sub0 = getSubVectorSrc(Bop0, Index, SubVT); |
0 |
| 23499 |
SDValue Sub1 = getSubVectorSrc(Bop1, Index, SubVT); |
0 |
23499 |
SDValue Sub1 = getSubVectorSrc(Bop1, Index, SubVT); |
0 |
| 23500 |
|
--- |
23500 |
|
--- |
| 23501 |
// TODO: We could handle the case where only 1 operand is being inserted by |
--- |
23501 |
// TODO: We could handle the case where only 1 operand is being inserted by |
--- |
| 23502 |
// creating an extract of the other operand, but that requires checking |
--- |
23502 |
// creating an extract of the other operand, but that requires checking |
--- |
| 23503 |
// number of uses and/or costs. |
--- |
23503 |
// number of uses and/or costs. |
--- |
| 23504 |
if (!Sub0 || !Sub1) |
0 |
23504 |
if (!Sub0 || !Sub1) |
0 |
| 23505 |
return SDValue(); |
0 |
23505 |
return SDValue(); |
0 |
| 23506 |
|
--- |
23506 |
|
--- |
| 23507 |
// We are inserting both operands of the wide binop only to extract back |
--- |
23507 |
// We are inserting both operands of the wide binop only to extract back |
--- |
| 23508 |
// to the narrow vector size. Eliminate all of the insert/extract: |
--- |
23508 |
// to the narrow vector size. Eliminate all of the insert/extract: |
--- |
| 23509 |
// ext (binop (ins ?, X, Index), (ins ?, Y, Index)), Index --> binop X, Y |
--- |
23509 |
// ext (binop (ins ?, X, Index), (ins ?, Y, Index)), Index --> binop X, Y |
--- |
| 23510 |
return DAG.getNode(BinOpcode, SDLoc(Extract), SubVT, Sub0, Sub1, |
0 |
23510 |
return DAG.getNode(BinOpcode, SDLoc(Extract), SubVT, Sub0, Sub1, |
0 |
| 23511 |
BinOp->getFlags()); |
0 |
23511 |
BinOp->getFlags()); |
0 |
| 23512 |
} |
--- |
23512 |
} |
--- |
| 23513 |
|
--- |
23513 |
|
--- |
| 23514 |
/// If we are extracting a subvector produced by a wide binary operator try |
--- |
23514 |
/// If we are extracting a subvector produced by a wide binary operator try |
--- |
| 23515 |
/// to use a narrow binary operator and/or avoid concatenation and extraction. |
--- |
23515 |
/// to use a narrow binary operator and/or avoid concatenation and extraction. |
--- |
| 23516 |
static SDValue narrowExtractedVectorBinOp(SDNode *Extract, SelectionDAG &DAG, |
0 |
23516 |
static SDValue narrowExtractedVectorBinOp(SDNode *Extract, SelectionDAG &DAG, |
0 |
| 23517 |
bool LegalOperations) { |
--- |
23517 |
bool LegalOperations) { |
--- |
| 23518 |
// TODO: Refactor with the caller (visitEXTRACT_SUBVECTOR), so we can share |
--- |
23518 |
// TODO: Refactor with the caller (visitEXTRACT_SUBVECTOR), so we can share |
--- |
| 23519 |
// some of these bailouts with other transforms. |
--- |
23519 |
// some of these bailouts with other transforms. |
--- |
| 23520 |
|
--- |
23520 |
|
--- |
| 23521 |
if (SDValue V = narrowInsertExtractVectorBinOp(Extract, DAG, LegalOperations)) |
0 |
23521 |
if (SDValue V = narrowInsertExtractVectorBinOp(Extract, DAG, LegalOperations)) |
0 |
| 23522 |
return V; |
0 |
23522 |
return V; |
0 |
| 23523 |
|
--- |
23523 |
|
--- |
| 23524 |
// The extract index must be a constant, so we can map it to a concat operand. |
--- |
23524 |
// The extract index must be a constant, so we can map it to a concat operand. |
--- |
| 23525 |
auto *ExtractIndexC = dyn_cast(Extract->getOperand(1)); |
0 |
23525 |
auto *ExtractIndexC = dyn_cast(Extract->getOperand(1)); |
0 |
| 23526 |
if (!ExtractIndexC) |
0 |
23526 |
if (!ExtractIndexC) |
0 |
| 23527 |
return SDValue(); |
0 |
23527 |
return SDValue(); |
0 |
| 23528 |
|
--- |
23528 |
|
--- |
| 23529 |
// We are looking for an optionally bitcasted wide vector binary operator |
--- |
23529 |
// We are looking for an optionally bitcasted wide vector binary operator |
--- |
| 23530 |
// feeding an extract subvector. |
--- |
23530 |
// feeding an extract subvector. |
--- |
| 23531 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
23531 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 23532 |
SDValue BinOp = peekThroughBitcasts(Extract->getOperand(0)); |
0 |
23532 |
SDValue BinOp = peekThroughBitcasts(Extract->getOperand(0)); |
0 |
| 23533 |
unsigned BOpcode = BinOp.getOpcode(); |
0 |
23533 |
unsigned BOpcode = BinOp.getOpcode(); |
0 |
| 23534 |
if (!TLI.isBinOp(BOpcode) || BinOp->getNumValues() != 1) |
0 |
23534 |
if (!TLI.isBinOp(BOpcode) || BinOp->getNumValues() != 1) |
0 |
| 23535 |
return SDValue(); |
0 |
23535 |
return SDValue(); |
0 |
| 23536 |
|
--- |
23536 |
|
--- |
| 23537 |
// Exclude the fake form of fneg (fsub -0.0, x) because that is likely to be |
--- |
23537 |
// Exclude the fake form of fneg (fsub -0.0, x) because that is likely to be |
--- |
| 23538 |
// reduced to the unary fneg when it is visited, and we probably want to deal |
--- |
23538 |
// reduced to the unary fneg when it is visited, and we probably want to deal |
--- |
| 23539 |
// with fneg in a target-specific way. |
--- |
23539 |
// with fneg in a target-specific way. |
--- |
| 23540 |
if (BOpcode == ISD::FSUB) { |
0 |
23540 |
if (BOpcode == ISD::FSUB) { |
0 |
| 23541 |
auto *C = isConstOrConstSplatFP(BinOp.getOperand(0), /*AllowUndefs*/ true); |
0 |
23541 |
auto *C = isConstOrConstSplatFP(BinOp.getOperand(0), /*AllowUndefs*/ true); |
0 |
| 23542 |
if (C && C->getValueAPF().isNegZero()) |
0 |
23542 |
if (C && C->getValueAPF().isNegZero()) |
0 |
| 23543 |
return SDValue(); |
0 |
23543 |
return SDValue(); |
0 |
| 23544 |
} |
--- |
23544 |
} |
--- |
| 23545 |
|
--- |
23545 |
|
--- |
| 23546 |
// The binop must be a vector type, so we can extract some fraction of it. |
--- |
23546 |
// The binop must be a vector type, so we can extract some fraction of it. |
--- |
| 23547 |
EVT WideBVT = BinOp.getValueType(); |
0 |
23547 |
EVT WideBVT = BinOp.getValueType(); |
0 |
| 23548 |
// The optimisations below currently assume we are dealing with fixed length |
--- |
23548 |
// The optimisations below currently assume we are dealing with fixed length |
--- |
| 23549 |
// vectors. It is possible to add support for scalable vectors, but at the |
--- |
23549 |
// vectors. It is possible to add support for scalable vectors, but at the |
--- |
| 23550 |
// moment we've done no analysis to prove whether they are profitable or not. |
--- |
23550 |
// moment we've done no analysis to prove whether they are profitable or not. |
--- |
| 23551 |
if (!WideBVT.isFixedLengthVector()) |
0 |
23551 |
if (!WideBVT.isFixedLengthVector()) |
0 |
| 23552 |
return SDValue(); |
0 |
23552 |
return SDValue(); |
0 |
| 23553 |
|
--- |
23553 |
|
--- |
| 23554 |
EVT VT = Extract->getValueType(0); |
0 |
23554 |
EVT VT = Extract->getValueType(0); |
0 |
| 23555 |
unsigned ExtractIndex = ExtractIndexC->getZExtValue(); |
0 |
23555 |
unsigned ExtractIndex = ExtractIndexC->getZExtValue(); |
0 |
| 23556 |
assert(ExtractIndex % VT.getVectorNumElements() == 0 && |
0 |
23556 |
assert(ExtractIndex % VT.getVectorNumElements() == 0 && |
0 |
| 23557 |
"Extract index is not a multiple of the vector length."); |
--- |
23557 |
"Extract index is not a multiple of the vector length."); |
--- |
| 23558 |
|
--- |
23558 |
|
--- |
| 23559 |
// Bail out if this is not a proper multiple width extraction. |
--- |
23559 |
// Bail out if this is not a proper multiple width extraction. |
--- |
| 23560 |
unsigned WideWidth = WideBVT.getSizeInBits(); |
0 |
23560 |
unsigned WideWidth = WideBVT.getSizeInBits(); |
0 |
| 23561 |
unsigned NarrowWidth = VT.getSizeInBits(); |
0 |
23561 |
unsigned NarrowWidth = VT.getSizeInBits(); |
0 |
| 23562 |
if (WideWidth % NarrowWidth != 0) |
0 |
23562 |
if (WideWidth % NarrowWidth != 0) |
0 |
| 23563 |
return SDValue(); |
0 |
23563 |
return SDValue(); |
0 |
| 23564 |
|
--- |
23564 |
|
--- |
| 23565 |
// Bail out if we are extracting a fraction of a single operation. This can |
--- |
23565 |
// Bail out if we are extracting a fraction of a single operation. This can |
--- |
| 23566 |
// occur because we potentially looked through a bitcast of the binop. |
--- |
23566 |
// occur because we potentially looked through a bitcast of the binop. |
--- |
| 23567 |
unsigned NarrowingRatio = WideWidth / NarrowWidth; |
0 |
23567 |
unsigned NarrowingRatio = WideWidth / NarrowWidth; |
0 |
| 23568 |
unsigned WideNumElts = WideBVT.getVectorNumElements(); |
0 |
23568 |
unsigned WideNumElts = WideBVT.getVectorNumElements(); |
0 |
| 23569 |
if (WideNumElts % NarrowingRatio != 0) |
0 |
23569 |
if (WideNumElts % NarrowingRatio != 0) |
0 |
| 23570 |
return SDValue(); |
0 |
23570 |
return SDValue(); |
0 |
| 23571 |
|
--- |
23571 |
|
--- |
| 23572 |
// Bail out if the target does not support a narrower version of the binop. |
--- |
23572 |
// Bail out if the target does not support a narrower version of the binop. |
--- |
| 23573 |
EVT NarrowBVT = EVT::getVectorVT(*DAG.getContext(), WideBVT.getScalarType(), |
0 |
23573 |
EVT NarrowBVT = EVT::getVectorVT(*DAG.getContext(), WideBVT.getScalarType(), |
0 |
| 23574 |
WideNumElts / NarrowingRatio); |
--- |
23574 |
WideNumElts / NarrowingRatio); |
--- |
| 23575 |
if (!TLI.isOperationLegalOrCustomOrPromote(BOpcode, NarrowBVT)) |
0 |
23575 |
if (!TLI.isOperationLegalOrCustomOrPromote(BOpcode, NarrowBVT)) |
0 |
| 23576 |
return SDValue(); |
0 |
23576 |
return SDValue(); |
0 |
| 23577 |
|
--- |
23577 |
|
--- |
| 23578 |
// If extraction is cheap, we don't need to look at the binop operands |
--- |
23578 |
// If extraction is cheap, we don't need to look at the binop operands |
--- |
| 23579 |
// for concat ops. The narrow binop alone makes this transform profitable. |
--- |
23579 |
// for concat ops. The narrow binop alone makes this transform profitable. |
--- |
| 23580 |
// We can't just reuse the original extract index operand because we may have |
--- |
23580 |
// We can't just reuse the original extract index operand because we may have |
--- |
| 23581 |
// bitcasted. |
--- |
23581 |
// bitcasted. |
--- |
| 23582 |
unsigned ConcatOpNum = ExtractIndex / VT.getVectorNumElements(); |
0 |
23582 |
unsigned ConcatOpNum = ExtractIndex / VT.getVectorNumElements(); |
0 |
| 23583 |
unsigned ExtBOIdx = ConcatOpNum * NarrowBVT.getVectorNumElements(); |
0 |
23583 |
unsigned ExtBOIdx = ConcatOpNum * NarrowBVT.getVectorNumElements(); |
0 |
| 23584 |
if (TLI.isExtractSubvectorCheap(NarrowBVT, WideBVT, ExtBOIdx) && |
0 |
23584 |
if (TLI.isExtractSubvectorCheap(NarrowBVT, WideBVT, ExtBOIdx) && |
0 |
| 23585 |
BinOp.hasOneUse() && Extract->getOperand(0)->hasOneUse()) { |
0 |
23585 |
BinOp.hasOneUse() && Extract->getOperand(0)->hasOneUse()) { |
0 |
| 23586 |
// extract (binop B0, B1), N --> binop (extract B0, N), (extract B1, N) |
--- |
23586 |
// extract (binop B0, B1), N --> binop (extract B0, N), (extract B1, N) |
--- |
| 23587 |
SDLoc DL(Extract); |
0 |
23587 |
SDLoc DL(Extract); |
0 |
| 23588 |
SDValue NewExtIndex = DAG.getVectorIdxConstant(ExtBOIdx, DL); |
0 |
23588 |
SDValue NewExtIndex = DAG.getVectorIdxConstant(ExtBOIdx, DL); |
0 |
| 23589 |
SDValue X = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NarrowBVT, |
0 |
23589 |
SDValue X = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NarrowBVT, |
0 |
| 23590 |
BinOp.getOperand(0), NewExtIndex); |
0 |
23590 |
BinOp.getOperand(0), NewExtIndex); |
0 |
| 23591 |
SDValue Y = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NarrowBVT, |
0 |
23591 |
SDValue Y = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NarrowBVT, |
0 |
| 23592 |
BinOp.getOperand(1), NewExtIndex); |
0 |
23592 |
BinOp.getOperand(1), NewExtIndex); |
0 |
| 23593 |
SDValue NarrowBinOp = |
--- |
23593 |
SDValue NarrowBinOp = |
--- |
| 23594 |
DAG.getNode(BOpcode, DL, NarrowBVT, X, Y, BinOp->getFlags()); |
0 |
23594 |
DAG.getNode(BOpcode, DL, NarrowBVT, X, Y, BinOp->getFlags()); |
0 |
| 23595 |
return DAG.getBitcast(VT, NarrowBinOp); |
0 |
23595 |
return DAG.getBitcast(VT, NarrowBinOp); |
0 |
| 23596 |
} |
0 |
23596 |
} |
0 |
| 23597 |
|
--- |
23597 |
|
--- |
| 23598 |
// Only handle the case where we are doubling and then halving. A larger ratio |
--- |
23598 |
// Only handle the case where we are doubling and then halving. A larger ratio |
--- |
| 23599 |
// may require more than two narrow binops to replace the wide binop. |
--- |
23599 |
// may require more than two narrow binops to replace the wide binop. |
--- |
| 23600 |
if (NarrowingRatio != 2) |
0 |
23600 |
if (NarrowingRatio != 2) |
0 |
| 23601 |
return SDValue(); |
0 |
23601 |
return SDValue(); |
0 |
| 23602 |
|
--- |
23602 |
|
--- |
| 23603 |
// TODO: The motivating case for this transform is an x86 AVX1 target. That |
--- |
23603 |
// TODO: The motivating case for this transform is an x86 AVX1 target. That |
--- |
| 23604 |
// target has temptingly almost legal versions of bitwise logic ops in 256-bit |
--- |
23604 |
// target has temptingly almost legal versions of bitwise logic ops in 256-bit |
--- |
| 23605 |
// flavors, but no other 256-bit integer support. This could be extended to |
--- |
23605 |
// flavors, but no other 256-bit integer support. This could be extended to |
--- |
| 23606 |
// handle any binop, but that may require fixing/adding other folds to avoid |
--- |
23606 |
// handle any binop, but that may require fixing/adding other folds to avoid |
--- |
| 23607 |
// codegen regressions. |
--- |
23607 |
// codegen regressions. |
--- |
| 23608 |
if (BOpcode != ISD::AND && BOpcode != ISD::OR && BOpcode != ISD::XOR) |
0 |
23608 |
if (BOpcode != ISD::AND && BOpcode != ISD::OR && BOpcode != ISD::XOR) |
0 |
| 23609 |
return SDValue(); |
0 |
23609 |
return SDValue(); |
0 |
| 23610 |
|
--- |
23610 |
|
--- |
| 23611 |
// We need at least one concatenation operation of a binop operand to make |
--- |
23611 |
// We need at least one concatenation operation of a binop operand to make |
--- |
| 23612 |
// this transform worthwhile. The concat must double the input vector sizes. |
--- |
23612 |
// this transform worthwhile. The concat must double the input vector sizes. |
--- |
| 23613 |
auto GetSubVector = [ConcatOpNum](SDValue V) -> SDValue { |
0 |
23613 |
auto GetSubVector = [ConcatOpNum](SDValue V) -> SDValue { |
0 |
| 23614 |
if (V.getOpcode() == ISD::CONCAT_VECTORS && V.getNumOperands() == 2) |
0 |
23614 |
if (V.getOpcode() == ISD::CONCAT_VECTORS && V.getNumOperands() == 2) |
0 |
| 23615 |
return V.getOperand(ConcatOpNum); |
0 |
23615 |
return V.getOperand(ConcatOpNum); |
0 |
| 23616 |
return SDValue(); |
0 |
23616 |
return SDValue(); |
0 |
| 23617 |
}; |
0 |
23617 |
}; |
0 |
| 23618 |
SDValue SubVecL = GetSubVector(peekThroughBitcasts(BinOp.getOperand(0))); |
0 |
23618 |
SDValue SubVecL = GetSubVector(peekThroughBitcasts(BinOp.getOperand(0))); |
0 |
| 23619 |
SDValue SubVecR = GetSubVector(peekThroughBitcasts(BinOp.getOperand(1))); |
0 |
23619 |
SDValue SubVecR = GetSubVector(peekThroughBitcasts(BinOp.getOperand(1))); |
0 |
| 23620 |
|
--- |
23620 |
|
--- |
| 23621 |
if (SubVecL || SubVecR) { |
0 |
23621 |
if (SubVecL || SubVecR) { |
0 |
| 23622 |
// If a binop operand was not the result of a concat, we must extract a |
--- |
23622 |
// If a binop operand was not the result of a concat, we must extract a |
--- |
| 23623 |
// half-sized operand for our new narrow binop: |
--- |
23623 |
// half-sized operand for our new narrow binop: |
--- |
| 23624 |
// extract (binop (concat X1, X2), (concat Y1, Y2)), N --> binop XN, YN |
--- |
23624 |
// extract (binop (concat X1, X2), (concat Y1, Y2)), N --> binop XN, YN |
--- |
| 23625 |
// extract (binop (concat X1, X2), Y), N --> binop XN, (extract Y, IndexC) |
--- |
23625 |
// extract (binop (concat X1, X2), Y), N --> binop XN, (extract Y, IndexC) |
--- |
| 23626 |
// extract (binop X, (concat Y1, Y2)), N --> binop (extract X, IndexC), YN |
--- |
23626 |
// extract (binop X, (concat Y1, Y2)), N --> binop (extract X, IndexC), YN |
--- |
| 23627 |
SDLoc DL(Extract); |
0 |
23627 |
SDLoc DL(Extract); |
0 |
| 23628 |
SDValue IndexC = DAG.getVectorIdxConstant(ExtBOIdx, DL); |
0 |
23628 |
SDValue IndexC = DAG.getVectorIdxConstant(ExtBOIdx, DL); |
0 |
| 23629 |
SDValue X = SubVecL ? DAG.getBitcast(NarrowBVT, SubVecL) |
0 |
23629 |
SDValue X = SubVecL ? DAG.getBitcast(NarrowBVT, SubVecL) |
0 |
| 23630 |
: DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NarrowBVT, |
0 |
23630 |
: DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NarrowBVT, |
0 |
| 23631 |
BinOp.getOperand(0), IndexC); |
0 |
23631 |
BinOp.getOperand(0), IndexC); |
0 |
| 23632 |
|
--- |
23632 |
|
--- |
| 23633 |
SDValue Y = SubVecR ? DAG.getBitcast(NarrowBVT, SubVecR) |
0 |
23633 |
SDValue Y = SubVecR ? DAG.getBitcast(NarrowBVT, SubVecR) |
0 |
| 23634 |
: DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NarrowBVT, |
0 |
23634 |
: DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NarrowBVT, |
0 |
| 23635 |
BinOp.getOperand(1), IndexC); |
0 |
23635 |
BinOp.getOperand(1), IndexC); |
0 |
| 23636 |
|
--- |
23636 |
|
--- |
| 23637 |
SDValue NarrowBinOp = DAG.getNode(BOpcode, DL, NarrowBVT, X, Y); |
0 |
23637 |
SDValue NarrowBinOp = DAG.getNode(BOpcode, DL, NarrowBVT, X, Y); |
0 |
| 23638 |
return DAG.getBitcast(VT, NarrowBinOp); |
0 |
23638 |
return DAG.getBitcast(VT, NarrowBinOp); |
0 |
| 23639 |
} |
0 |
23639 |
} |
0 |
| 23640 |
|
--- |
23640 |
|
--- |
| 23641 |
return SDValue(); |
0 |
23641 |
return SDValue(); |
0 |
| 23642 |
} |
--- |
23642 |
} |
--- |
| 23643 |
|
--- |
23643 |
|
--- |
| 23644 |
/// If we are extracting a subvector from a wide vector load, convert to a |
--- |
23644 |
/// If we are extracting a subvector from a wide vector load, convert to a |
--- |
| 23645 |
/// narrow load to eliminate the extraction: |
--- |
23645 |
/// narrow load to eliminate the extraction: |
--- |
| 23646 |
/// (extract_subvector (load wide vector)) --> (load narrow vector) |
--- |
23646 |
/// (extract_subvector (load wide vector)) --> (load narrow vector) |
--- |
| 23647 |
static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) { |
0 |
23647 |
static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) { |
0 |
| 23648 |
// TODO: Add support for big-endian. The offset calculation must be adjusted. |
--- |
23648 |
// TODO: Add support for big-endian. The offset calculation must be adjusted. |
--- |
| 23649 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
23649 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
| 23650 |
return SDValue(); |
0 |
23650 |
return SDValue(); |
0 |
| 23651 |
|
--- |
23651 |
|
--- |
| 23652 |
auto *Ld = dyn_cast(Extract->getOperand(0)); |
0 |
23652 |
auto *Ld = dyn_cast(Extract->getOperand(0)); |
0 |
| 23653 |
if (!Ld || Ld->getExtensionType() || !Ld->isSimple()) |
0 |
23653 |
if (!Ld || Ld->getExtensionType() || !Ld->isSimple()) |
0 |
| 23654 |
return SDValue(); |
0 |
23654 |
return SDValue(); |
0 |
| 23655 |
|
--- |
23655 |
|
--- |
| 23656 |
// Allow targets to opt-out. |
--- |
23656 |
// Allow targets to opt-out. |
--- |
| 23657 |
EVT VT = Extract->getValueType(0); |
0 |
23657 |
EVT VT = Extract->getValueType(0); |
0 |
| 23658 |
|
--- |
23658 |
|
--- |
| 23659 |
// We can only create byte sized loads. |
--- |
23659 |
// We can only create byte sized loads. |
--- |
| 23660 |
if (!VT.isByteSized()) |
0 |
23660 |
if (!VT.isByteSized()) |
0 |
| 23661 |
return SDValue(); |
0 |
23661 |
return SDValue(); |
0 |
| 23662 |
|
--- |
23662 |
|
--- |
| 23663 |
unsigned Index = Extract->getConstantOperandVal(1); |
0 |
23663 |
unsigned Index = Extract->getConstantOperandVal(1); |
0 |
| 23664 |
unsigned NumElts = VT.getVectorMinNumElements(); |
0 |
23664 |
unsigned NumElts = VT.getVectorMinNumElements(); |
0 |
| 23665 |
|
--- |
23665 |
|
--- |
| 23666 |
// The definition of EXTRACT_SUBVECTOR states that the index must be a |
--- |
23666 |
// The definition of EXTRACT_SUBVECTOR states that the index must be a |
--- |
| 23667 |
// multiple of the minimum number of elements in the result type. |
--- |
23667 |
// multiple of the minimum number of elements in the result type. |
--- |
| 23668 |
assert(Index % NumElts == 0 && "The extract subvector index is not a " |
0 |
23668 |
assert(Index % NumElts == 0 && "The extract subvector index is not a " |
0 |
| 23669 |
"multiple of the result's element count"); |
--- |
23669 |
"multiple of the result's element count"); |
--- |
| 23670 |
|
--- |
23670 |
|
--- |
| 23671 |
// It's fine to use TypeSize here as we know the offset will not be negative. |
--- |
23671 |
// It's fine to use TypeSize here as we know the offset will not be negative. |
--- |
| 23672 |
TypeSize Offset = VT.getStoreSize() * (Index / NumElts); |
0 |
23672 |
TypeSize Offset = VT.getStoreSize() * (Index / NumElts); |
0 |
| 23673 |
|
--- |
23673 |
|
--- |
| 23674 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
23674 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 23675 |
if (!TLI.shouldReduceLoadWidth(Ld, Ld->getExtensionType(), VT)) |
0 |
23675 |
if (!TLI.shouldReduceLoadWidth(Ld, Ld->getExtensionType(), VT)) |
0 |
| 23676 |
return SDValue(); |
0 |
23676 |
return SDValue(); |
0 |
| 23677 |
|
--- |
23677 |
|
--- |
| 23678 |
// The narrow load will be offset from the base address of the old load if |
--- |
23678 |
// The narrow load will be offset from the base address of the old load if |
--- |
| 23679 |
// we are extracting from something besides index 0 (little-endian). |
--- |
23679 |
// we are extracting from something besides index 0 (little-endian). |
--- |
| 23680 |
SDLoc DL(Extract); |
0 |
23680 |
SDLoc DL(Extract); |
0 |
| 23681 |
|
--- |
23681 |
|
--- |
| 23682 |
// TODO: Use "BaseIndexOffset" to make this more effective. |
--- |
23682 |
// TODO: Use "BaseIndexOffset" to make this more effective. |
--- |
| 23683 |
SDValue NewAddr = DAG.getMemBasePlusOffset(Ld->getBasePtr(), Offset, DL); |
0 |
23683 |
SDValue NewAddr = DAG.getMemBasePlusOffset(Ld->getBasePtr(), Offset, DL); |
0 |
| 23684 |
|
--- |
23684 |
|
--- |
| 23685 |
uint64_t StoreSize = MemoryLocation::getSizeOrUnknown(VT.getStoreSize()); |
0 |
23685 |
uint64_t StoreSize = MemoryLocation::getSizeOrUnknown(VT.getStoreSize()); |
0 |
| 23686 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
23686 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 23687 |
MachineMemOperand *MMO; |
--- |
23687 |
MachineMemOperand *MMO; |
--- |
| 23688 |
if (Offset.isScalable()) { |
0 |
23688 |
if (Offset.isScalable()) { |
0 |
| 23689 |
MachinePointerInfo MPI = |
--- |
23689 |
MachinePointerInfo MPI = |
--- |
| 23690 |
MachinePointerInfo(Ld->getPointerInfo().getAddrSpace()); |
0 |
23690 |
MachinePointerInfo(Ld->getPointerInfo().getAddrSpace()); |
0 |
| 23691 |
MMO = MF.getMachineMemOperand(Ld->getMemOperand(), MPI, StoreSize); |
0 |
23691 |
MMO = MF.getMachineMemOperand(Ld->getMemOperand(), MPI, StoreSize); |
0 |
| 23692 |
} else |
--- |
23692 |
} else |
--- |
| 23693 |
MMO = MF.getMachineMemOperand(Ld->getMemOperand(), Offset.getFixedValue(), |
0 |
23693 |
MMO = MF.getMachineMemOperand(Ld->getMemOperand(), Offset.getFixedValue(), |
0 |
| 23694 |
StoreSize); |
--- |
23694 |
StoreSize); |
--- |
| 23695 |
|
--- |
23695 |
|
--- |
| 23696 |
SDValue NewLd = DAG.getLoad(VT, DL, Ld->getChain(), NewAddr, MMO); |
0 |
23696 |
SDValue NewLd = DAG.getLoad(VT, DL, Ld->getChain(), NewAddr, MMO); |
0 |
| 23697 |
DAG.makeEquivalentMemoryOrdering(Ld, NewLd); |
0 |
23697 |
DAG.makeEquivalentMemoryOrdering(Ld, NewLd); |
0 |
| 23698 |
return NewLd; |
0 |
23698 |
return NewLd; |
0 |
| 23699 |
} |
0 |
23699 |
} |
0 |
| 23700 |
|
--- |
23700 |
|
--- |
| 23701 |
/// Given EXTRACT_SUBVECTOR(VECTOR_SHUFFLE(Op0, Op1, Mask)), |
--- |
23701 |
/// Given EXTRACT_SUBVECTOR(VECTOR_SHUFFLE(Op0, Op1, Mask)), |
--- |
| 23702 |
/// try to produce VECTOR_SHUFFLE(EXTRACT_SUBVECTOR(Op?, ?), |
--- |
23702 |
/// try to produce VECTOR_SHUFFLE(EXTRACT_SUBVECTOR(Op?, ?), |
--- |
| 23703 |
/// EXTRACT_SUBVECTOR(Op?, ?), |
--- |
23703 |
/// EXTRACT_SUBVECTOR(Op?, ?), |
--- |
| 23704 |
/// Mask')) |
--- |
23704 |
/// Mask')) |
--- |
| 23705 |
/// iff it is legal and profitable to do so. Notably, the trimmed mask |
--- |
23705 |
/// iff it is legal and profitable to do so. Notably, the trimmed mask |
--- |
| 23706 |
/// (containing only the elements that are extracted) |
--- |
23706 |
/// (containing only the elements that are extracted) |
--- |
| 23707 |
/// must reference at most two subvectors. |
--- |
23707 |
/// must reference at most two subvectors. |
--- |
| 23708 |
static SDValue foldExtractSubvectorFromShuffleVector(SDNode *N, |
0 |
23708 |
static SDValue foldExtractSubvectorFromShuffleVector(SDNode *N, |
0 |
| 23709 |
SelectionDAG &DAG, |
--- |
23709 |
SelectionDAG &DAG, |
--- |
| 23710 |
const TargetLowering &TLI, |
--- |
23710 |
const TargetLowering &TLI, |
--- |
| 23711 |
bool LegalOperations) { |
--- |
23711 |
bool LegalOperations) { |
--- |
| 23712 |
assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR && |
0 |
23712 |
assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR && |
0 |
| 23713 |
"Must only be called on EXTRACT_SUBVECTOR's"); |
--- |
23713 |
"Must only be called on EXTRACT_SUBVECTOR's"); |
--- |
| 23714 |
|
--- |
23714 |
|
--- |
| 23715 |
SDValue N0 = N->getOperand(0); |
0 |
23715 |
SDValue N0 = N->getOperand(0); |
0 |
| 23716 |
|
--- |
23716 |
|
--- |
| 23717 |
// Only deal with non-scalable vectors. |
--- |
23717 |
// Only deal with non-scalable vectors. |
--- |
| 23718 |
EVT NarrowVT = N->getValueType(0); |
0 |
23718 |
EVT NarrowVT = N->getValueType(0); |
0 |
| 23719 |
EVT WideVT = N0.getValueType(); |
0 |
23719 |
EVT WideVT = N0.getValueType(); |
0 |
| 23720 |
if (!NarrowVT.isFixedLengthVector() || !WideVT.isFixedLengthVector()) |
0 |
23720 |
if (!NarrowVT.isFixedLengthVector() || !WideVT.isFixedLengthVector()) |
0 |
| 23721 |
return SDValue(); |
0 |
23721 |
return SDValue(); |
0 |
| 23722 |
|
--- |
23722 |
|
--- |
| 23723 |
// The operand must be a shufflevector. |
--- |
23723 |
// The operand must be a shufflevector. |
--- |
| 23724 |
auto *WideShuffleVector = dyn_cast(N0); |
0 |
23724 |
auto *WideShuffleVector = dyn_cast(N0); |
0 |
| 23725 |
if (!WideShuffleVector) |
0 |
23725 |
if (!WideShuffleVector) |
0 |
| 23726 |
return SDValue(); |
0 |
23726 |
return SDValue(); |
0 |
| 23727 |
|
--- |
23727 |
|
--- |
| 23728 |
// The old shuffleneeds to go away. |
--- |
23728 |
// The old shuffleneeds to go away. |
--- |
| 23729 |
if (!WideShuffleVector->hasOneUse()) |
0 |
23729 |
if (!WideShuffleVector->hasOneUse()) |
0 |
| 23730 |
return SDValue(); |
0 |
23730 |
return SDValue(); |
0 |
| 23731 |
|
--- |
23731 |
|
--- |
| 23732 |
// And the narrow shufflevector that we'll form must be legal. |
--- |
23732 |
// And the narrow shufflevector that we'll form must be legal. |
--- |
| 23733 |
if (LegalOperations && |
0 |
23733 |
if (LegalOperations && |
0 |
| 23734 |
!TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, NarrowVT)) |
0 |
23734 |
!TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, NarrowVT)) |
0 |
| 23735 |
return SDValue(); |
0 |
23735 |
return SDValue(); |
0 |
| 23736 |
|
--- |
23736 |
|
--- |
| 23737 |
uint64_t FirstExtractedEltIdx = N->getConstantOperandVal(1); |
0 |
23737 |
uint64_t FirstExtractedEltIdx = N->getConstantOperandVal(1); |
0 |
| 23738 |
int NumEltsExtracted = NarrowVT.getVectorNumElements(); |
0 |
23738 |
int NumEltsExtracted = NarrowVT.getVectorNumElements(); |
0 |
| 23739 |
assert((FirstExtractedEltIdx % NumEltsExtracted) == 0 && |
0 |
23739 |
assert((FirstExtractedEltIdx % NumEltsExtracted) == 0 && |
0 |
| 23740 |
"Extract index is not a multiple of the output vector length."); |
--- |
23740 |
"Extract index is not a multiple of the output vector length."); |
--- |
| 23741 |
|
--- |
23741 |
|
--- |
| 23742 |
int WideNumElts = WideVT.getVectorNumElements(); |
0 |
23742 |
int WideNumElts = WideVT.getVectorNumElements(); |
0 |
| 23743 |
|
--- |
23743 |
|
--- |
| 23744 |
SmallVector NewMask; |
0 |
23744 |
SmallVector NewMask; |
0 |
| 23745 |
NewMask.reserve(NumEltsExtracted); |
0 |
23745 |
NewMask.reserve(NumEltsExtracted); |
0 |
| 23746 |
SmallSetVector, 2> |
--- |
23746 |
SmallSetVector, 2> |
--- |
| 23747 |
DemandedSubvectors; |
0 |
23747 |
DemandedSubvectors; |
0 |
| 23748 |
|
--- |
23748 |
|
--- |
| 23749 |
// Try to decode the wide mask into narrow mask from at most two subvectors. |
--- |
23749 |
// Try to decode the wide mask into narrow mask from at most two subvectors. |
--- |
| 23750 |
for (int M : WideShuffleVector->getMask().slice(FirstExtractedEltIdx, |
0 |
23750 |
for (int M : WideShuffleVector->getMask().slice(FirstExtractedEltIdx, |
0 |
| 23751 |
NumEltsExtracted)) { |
0 |
23751 |
NumEltsExtracted)) { |
0 |
| 23752 |
assert((M >= -1) && (M < (2 * WideNumElts)) && |
0 |
23752 |
assert((M >= -1) && (M < (2 * WideNumElts)) && |
0 |
| 23753 |
"Out-of-bounds shuffle mask?"); |
--- |
23753 |
"Out-of-bounds shuffle mask?"); |
--- |
| 23754 |
|
--- |
23754 |
|
--- |
| 23755 |
if (M < 0) { |
0 |
23755 |
if (M < 0) { |
0 |
| 23756 |
// Does not depend on operands, does not require adjustment. |
--- |
23756 |
// Does not depend on operands, does not require adjustment. |
--- |
| 23757 |
NewMask.emplace_back(M); |
0 |
23757 |
NewMask.emplace_back(M); |
0 |
| 23758 |
continue; |
0 |
23758 |
continue; |
0 |
| 23759 |
} |
--- |
23759 |
} |
--- |
| 23760 |
|
--- |
23760 |
|
--- |
| 23761 |
// From which operand of the shuffle does this shuffle mask element pick? |
--- |
23761 |
// From which operand of the shuffle does this shuffle mask element pick? |
--- |
| 23762 |
int WideShufOpIdx = M / WideNumElts; |
0 |
23762 |
int WideShufOpIdx = M / WideNumElts; |
0 |
| 23763 |
// Which element of that operand is picked? |
--- |
23763 |
// Which element of that operand is picked? |
--- |
| 23764 |
int OpEltIdx = M % WideNumElts; |
0 |
23764 |
int OpEltIdx = M % WideNumElts; |
0 |
| 23765 |
|
--- |
23765 |
|
--- |
| 23766 |
assert((OpEltIdx + WideShufOpIdx * WideNumElts) == M && |
0 |
23766 |
assert((OpEltIdx + WideShufOpIdx * WideNumElts) == M && |
0 |
| 23767 |
"Shuffle mask vector decomposition failure."); |
--- |
23767 |
"Shuffle mask vector decomposition failure."); |
--- |
| 23768 |
|
--- |
23768 |
|
--- |
| 23769 |
// And which NumEltsExtracted-sized subvector of that operand is that? |
--- |
23769 |
// And which NumEltsExtracted-sized subvector of that operand is that? |
--- |
| 23770 |
int OpSubvecIdx = OpEltIdx / NumEltsExtracted; |
0 |
23770 |
int OpSubvecIdx = OpEltIdx / NumEltsExtracted; |
0 |
| 23771 |
// And which element within that subvector of that operand is that? |
--- |
23771 |
// And which element within that subvector of that operand is that? |
--- |
| 23772 |
int OpEltIdxInSubvec = OpEltIdx % NumEltsExtracted; |
0 |
23772 |
int OpEltIdxInSubvec = OpEltIdx % NumEltsExtracted; |
0 |
| 23773 |
|
--- |
23773 |
|
--- |
| 23774 |
assert((OpEltIdxInSubvec + OpSubvecIdx * NumEltsExtracted) == OpEltIdx && |
0 |
23774 |
assert((OpEltIdxInSubvec + OpSubvecIdx * NumEltsExtracted) == OpEltIdx && |
0 |
| 23775 |
"Shuffle mask subvector decomposition failure."); |
--- |
23775 |
"Shuffle mask subvector decomposition failure."); |
--- |
| 23776 |
|
--- |
23776 |
|
--- |
| 23777 |
assert((OpEltIdxInSubvec + OpSubvecIdx * NumEltsExtracted + |
0 |
23777 |
assert((OpEltIdxInSubvec + OpSubvecIdx * NumEltsExtracted + |
0 |
| 23778 |
WideShufOpIdx * WideNumElts) == M && |
--- |
23778 |
WideShufOpIdx * WideNumElts) == M && |
--- |
| 23779 |
"Shuffle mask full decomposition failure."); |
--- |
23779 |
"Shuffle mask full decomposition failure."); |
--- |
| 23780 |
|
--- |
23780 |
|
--- |
| 23781 |
SDValue Op = WideShuffleVector->getOperand(WideShufOpIdx); |
0 |
23781 |
SDValue Op = WideShuffleVector->getOperand(WideShufOpIdx); |
0 |
| 23782 |
|
--- |
23782 |
|
--- |
| 23783 |
if (Op.isUndef()) { |
0 |
23783 |
if (Op.isUndef()) { |
0 |
| 23784 |
// Picking from an undef operand. Let's adjust mask instead. |
--- |
23784 |
// Picking from an undef operand. Let's adjust mask instead. |
--- |
| 23785 |
NewMask.emplace_back(-1); |
0 |
23785 |
NewMask.emplace_back(-1); |
0 |
| 23786 |
continue; |
0 |
23786 |
continue; |
0 |
| 23787 |
} |
--- |
23787 |
} |
--- |
| 23788 |
|
--- |
23788 |
|
--- |
| 23789 |
const std::pair DemandedSubvector = |
--- |
23789 |
const std::pair DemandedSubvector = |
--- |
| 23790 |
std::make_pair(Op, OpSubvecIdx); |
0 |
23790 |
std::make_pair(Op, OpSubvecIdx); |
0 |
| 23791 |
|
--- |
23791 |
|
--- |
| 23792 |
if (DemandedSubvectors.insert(DemandedSubvector)) { |
0 |
23792 |
if (DemandedSubvectors.insert(DemandedSubvector)) { |
0 |
| 23793 |
if (DemandedSubvectors.size() > 2) |
0 |
23793 |
if (DemandedSubvectors.size() > 2) |
0 |
| 23794 |
return SDValue(); // We can't handle more than two subvectors. |
0 |
23794 |
return SDValue(); // We can't handle more than two subvectors. |
0 |
| 23795 |
// How many elements into the WideVT does this subvector start? |
--- |
23795 |
// How many elements into the WideVT does this subvector start? |
--- |
| 23796 |
int Index = NumEltsExtracted * OpSubvecIdx; |
0 |
23796 |
int Index = NumEltsExtracted * OpSubvecIdx; |
0 |
| 23797 |
// Bail out if the extraction isn't going to be cheap. |
--- |
23797 |
// Bail out if the extraction isn't going to be cheap. |
--- |
| 23798 |
if (!TLI.isExtractSubvectorCheap(NarrowVT, WideVT, Index)) |
0 |
23798 |
if (!TLI.isExtractSubvectorCheap(NarrowVT, WideVT, Index)) |
0 |
| 23799 |
return SDValue(); |
0 |
23799 |
return SDValue(); |
0 |
| 23800 |
} |
--- |
23800 |
} |
--- |
| 23801 |
|
--- |
23801 |
|
--- |
| 23802 |
// Ok, but from which operand of the new shuffle will this element pick? |
--- |
23802 |
// Ok, but from which operand of the new shuffle will this element pick? |
--- |
| 23803 |
int NewOpIdx = |
--- |
23803 |
int NewOpIdx = |
--- |
| 23804 |
getFirstIndexOf(DemandedSubvectors.getArrayRef(), DemandedSubvector); |
0 |
23804 |
getFirstIndexOf(DemandedSubvectors.getArrayRef(), DemandedSubvector); |
0 |
| 23805 |
assert((NewOpIdx == 0 || NewOpIdx == 1) && "Unexpected operand index."); |
0 |
23805 |
assert((NewOpIdx == 0 || NewOpIdx == 1) && "Unexpected operand index."); |
0 |
| 23806 |
|
--- |
23806 |
|
--- |
| 23807 |
int AdjM = OpEltIdxInSubvec + NewOpIdx * NumEltsExtracted; |
0 |
23807 |
int AdjM = OpEltIdxInSubvec + NewOpIdx * NumEltsExtracted; |
0 |
| 23808 |
NewMask.emplace_back(AdjM); |
0 |
23808 |
NewMask.emplace_back(AdjM); |
0 |
| 23809 |
} |
--- |
23809 |
} |
--- |
| 23810 |
assert(NewMask.size() == (unsigned)NumEltsExtracted && "Produced bad mask."); |
0 |
23810 |
assert(NewMask.size() == (unsigned)NumEltsExtracted && "Produced bad mask."); |
0 |
| 23811 |
assert(DemandedSubvectors.size() <= 2 && |
0 |
23811 |
assert(DemandedSubvectors.size() <= 2 && |
0 |
| 23812 |
"Should have ended up demanding at most two subvectors."); |
--- |
23812 |
"Should have ended up demanding at most two subvectors."); |
--- |
| 23813 |
|
--- |
23813 |
|
--- |
| 23814 |
// Did we discover that the shuffle does not actually depend on operands? |
--- |
23814 |
// Did we discover that the shuffle does not actually depend on operands? |
--- |
| 23815 |
if (DemandedSubvectors.empty()) |
0 |
23815 |
if (DemandedSubvectors.empty()) |
0 |
| 23816 |
return DAG.getUNDEF(NarrowVT); |
0 |
23816 |
return DAG.getUNDEF(NarrowVT); |
0 |
| 23817 |
|
--- |
23817 |
|
--- |
| 23818 |
// Profitability check: only deal with extractions from the first subvector |
--- |
23818 |
// Profitability check: only deal with extractions from the first subvector |
--- |
| 23819 |
// unless the mask becomes an identity mask. |
--- |
23819 |
// unless the mask becomes an identity mask. |
--- |
| 23820 |
if (!ShuffleVectorInst::isIdentityMask(NewMask) || |
0 |
23820 |
if (!ShuffleVectorInst::isIdentityMask(NewMask) || |
0 |
| 23821 |
any_of(NewMask, [](int M) { return M < 0; })) |
0 |
23821 |
any_of(NewMask, [](int M) { return M < 0; })) |
0 |
| 23822 |
for (auto &DemandedSubvector : DemandedSubvectors) |
0 |
23822 |
for (auto &DemandedSubvector : DemandedSubvectors) |
0 |
| 23823 |
if (DemandedSubvector.second != 0) |
0 |
23823 |
if (DemandedSubvector.second != 0) |
0 |
| 23824 |
return SDValue(); |
0 |
23824 |
return SDValue(); |
0 |
| 23825 |
|
--- |
23825 |
|
--- |
| 23826 |
// We still perform the exact same EXTRACT_SUBVECTOR, just on different |
--- |
23826 |
// We still perform the exact same EXTRACT_SUBVECTOR, just on different |
--- |
| 23827 |
// operand[s]/index[es], so there is no point in checking for it's legality. |
--- |
23827 |
// operand[s]/index[es], so there is no point in checking for it's legality. |
--- |
| 23828 |
|
--- |
23828 |
|
--- |
| 23829 |
// Do not turn a legal shuffle into an illegal one. |
--- |
23829 |
// Do not turn a legal shuffle into an illegal one. |
--- |
| 23830 |
if (TLI.isShuffleMaskLegal(WideShuffleVector->getMask(), WideVT) && |
0 |
23830 |
if (TLI.isShuffleMaskLegal(WideShuffleVector->getMask(), WideVT) && |
0 |
| 23831 |
!TLI.isShuffleMaskLegal(NewMask, NarrowVT)) |
0 |
23831 |
!TLI.isShuffleMaskLegal(NewMask, NarrowVT)) |
0 |
| 23832 |
return SDValue(); |
0 |
23832 |
return SDValue(); |
0 |
| 23833 |
|
--- |
23833 |
|
--- |
| 23834 |
SDLoc DL(N); |
0 |
23834 |
SDLoc DL(N); |
0 |
| 23835 |
|
--- |
23835 |
|
--- |
| 23836 |
SmallVector NewOps; |
0 |
23836 |
SmallVector NewOps; |
0 |
| 23837 |
for (const std::pair |
0 |
23837 |
for (const std::pair |
0 |
| 23838 |
&DemandedSubvector : DemandedSubvectors) { |
0 |
23838 |
&DemandedSubvector : DemandedSubvectors) { |
0 |
| 23839 |
// How many elements into the WideVT does this subvector start? |
--- |
23839 |
// How many elements into the WideVT does this subvector start? |
--- |
| 23840 |
int Index = NumEltsExtracted * DemandedSubvector.second; |
0 |
23840 |
int Index = NumEltsExtracted * DemandedSubvector.second; |
0 |
| 23841 |
SDValue IndexC = DAG.getVectorIdxConstant(Index, DL); |
0 |
23841 |
SDValue IndexC = DAG.getVectorIdxConstant(Index, DL); |
0 |
| 23842 |
NewOps.emplace_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NarrowVT, |
0 |
23842 |
NewOps.emplace_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NarrowVT, |
0 |
| 23843 |
DemandedSubvector.first, IndexC)); |
--- |
23843 |
DemandedSubvector.first, IndexC)); |
--- |
| 23844 |
} |
--- |
23844 |
} |
--- |
| 23845 |
assert((NewOps.size() == 1 || NewOps.size() == 2) && |
0 |
23845 |
assert((NewOps.size() == 1 || NewOps.size() == 2) && |
0 |
| 23846 |
"Should end up with either one or two ops"); |
--- |
23846 |
"Should end up with either one or two ops"); |
--- |
| 23847 |
|
--- |
23847 |
|
--- |
| 23848 |
// If we ended up with only one operand, pad with an undef. |
--- |
23848 |
// If we ended up with only one operand, pad with an undef. |
--- |
| 23849 |
if (NewOps.size() == 1) |
0 |
23849 |
if (NewOps.size() == 1) |
0 |
| 23850 |
NewOps.emplace_back(DAG.getUNDEF(NarrowVT)); |
0 |
23850 |
NewOps.emplace_back(DAG.getUNDEF(NarrowVT)); |
0 |
| 23851 |
|
--- |
23851 |
|
--- |
| 23852 |
return DAG.getVectorShuffle(NarrowVT, DL, NewOps[0], NewOps[1], NewMask); |
0 |
23852 |
return DAG.getVectorShuffle(NarrowVT, DL, NewOps[0], NewOps[1], NewMask); |
0 |
| 23853 |
} |
0 |
23853 |
} |
0 |
| 23854 |
|
--- |
23854 |
|
--- |
| 23855 |
SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) { |
0 |
23855 |
SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) { |
0 |
| 23856 |
EVT NVT = N->getValueType(0); |
0 |
23856 |
EVT NVT = N->getValueType(0); |
0 |
| 23857 |
SDValue V = N->getOperand(0); |
0 |
23857 |
SDValue V = N->getOperand(0); |
0 |
| 23858 |
uint64_t ExtIdx = N->getConstantOperandVal(1); |
0 |
23858 |
uint64_t ExtIdx = N->getConstantOperandVal(1); |
0 |
| 23859 |
|
--- |
23859 |
|
--- |
| 23860 |
// Extract from UNDEF is UNDEF. |
--- |
23860 |
// Extract from UNDEF is UNDEF. |
--- |
| 23861 |
if (V.isUndef()) |
0 |
23861 |
if (V.isUndef()) |
0 |
| 23862 |
return DAG.getUNDEF(NVT); |
0 |
23862 |
return DAG.getUNDEF(NVT); |
0 |
| 23863 |
|
--- |
23863 |
|
--- |
| 23864 |
if (TLI.isOperationLegalOrCustomOrPromote(ISD::LOAD, NVT)) |
0 |
23864 |
if (TLI.isOperationLegalOrCustomOrPromote(ISD::LOAD, NVT)) |
0 |
| 23865 |
if (SDValue NarrowLoad = narrowExtractedVectorLoad(N, DAG)) |
0 |
23865 |
if (SDValue NarrowLoad = narrowExtractedVectorLoad(N, DAG)) |
0 |
| 23866 |
return NarrowLoad; |
0 |
23866 |
return NarrowLoad; |
0 |
| 23867 |
|
--- |
23867 |
|
--- |
| 23868 |
// Combine an extract of an extract into a single extract_subvector. |
--- |
23868 |
// Combine an extract of an extract into a single extract_subvector. |
--- |
| 23869 |
// ext (ext X, C), 0 --> ext X, C |
--- |
23869 |
// ext (ext X, C), 0 --> ext X, C |
--- |
| 23870 |
if (ExtIdx == 0 && V.getOpcode() == ISD::EXTRACT_SUBVECTOR && V.hasOneUse()) { |
0 |
23870 |
if (ExtIdx == 0 && V.getOpcode() == ISD::EXTRACT_SUBVECTOR && V.hasOneUse()) { |
0 |
| 23871 |
if (TLI.isExtractSubvectorCheap(NVT, V.getOperand(0).getValueType(), |
0 |
23871 |
if (TLI.isExtractSubvectorCheap(NVT, V.getOperand(0).getValueType(), |
0 |
| 23872 |
V.getConstantOperandVal(1)) && |
0 |
23872 |
V.getConstantOperandVal(1)) && |
0 |
| 23873 |
TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NVT)) { |
0 |
23873 |
TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NVT)) { |
0 |
| 23874 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, V.getOperand(0), |
0 |
23874 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, V.getOperand(0), |
0 |
| 23875 |
V.getOperand(1)); |
0 |
23875 |
V.getOperand(1)); |
0 |
| 23876 |
} |
--- |
23876 |
} |
--- |
| 23877 |
} |
--- |
23877 |
} |
--- |
| 23878 |
|
--- |
23878 |
|
--- |
| 23879 |
// ty1 extract_vector(ty2 splat(V))) -> ty1 splat(V) |
--- |
23879 |
// ty1 extract_vector(ty2 splat(V))) -> ty1 splat(V) |
--- |
| 23880 |
if (V.getOpcode() == ISD::SPLAT_VECTOR) |
0 |
23880 |
if (V.getOpcode() == ISD::SPLAT_VECTOR) |
0 |
| 23881 |
if (DAG.isConstantValueOfAnyType(V.getOperand(0)) || V.hasOneUse()) |
0 |
23881 |
if (DAG.isConstantValueOfAnyType(V.getOperand(0)) || V.hasOneUse()) |
0 |
| 23882 |
if (!LegalOperations || TLI.isOperationLegal(ISD::SPLAT_VECTOR, NVT)) |
0 |
23882 |
if (!LegalOperations || TLI.isOperationLegal(ISD::SPLAT_VECTOR, NVT)) |
0 |
| 23883 |
return DAG.getSplatVector(NVT, SDLoc(N), V.getOperand(0)); |
0 |
23883 |
return DAG.getSplatVector(NVT, SDLoc(N), V.getOperand(0)); |
0 |
| 23884 |
|
--- |
23884 |
|
--- |
| 23885 |
// Try to move vector bitcast after extract_subv by scaling extraction index: |
--- |
23885 |
// Try to move vector bitcast after extract_subv by scaling extraction index: |
--- |
| 23886 |
// extract_subv (bitcast X), Index --> bitcast (extract_subv X, Index') |
--- |
23886 |
// extract_subv (bitcast X), Index --> bitcast (extract_subv X, Index') |
--- |
| 23887 |
if (V.getOpcode() == ISD::BITCAST && |
0 |
23887 |
if (V.getOpcode() == ISD::BITCAST && |
0 |
| 23888 |
V.getOperand(0).getValueType().isVector() && |
0 |
23888 |
V.getOperand(0).getValueType().isVector() && |
0 |
| 23889 |
(!LegalOperations || TLI.isOperationLegal(ISD::BITCAST, NVT))) { |
0 |
23889 |
(!LegalOperations || TLI.isOperationLegal(ISD::BITCAST, NVT))) { |
0 |
| 23890 |
SDValue SrcOp = V.getOperand(0); |
0 |
23890 |
SDValue SrcOp = V.getOperand(0); |
0 |
| 23891 |
EVT SrcVT = SrcOp.getValueType(); |
0 |
23891 |
EVT SrcVT = SrcOp.getValueType(); |
0 |
| 23892 |
unsigned SrcNumElts = SrcVT.getVectorMinNumElements(); |
0 |
23892 |
unsigned SrcNumElts = SrcVT.getVectorMinNumElements(); |
0 |
| 23893 |
unsigned DestNumElts = V.getValueType().getVectorMinNumElements(); |
0 |
23893 |
unsigned DestNumElts = V.getValueType().getVectorMinNumElements(); |
0 |
| 23894 |
if ((SrcNumElts % DestNumElts) == 0) { |
0 |
23894 |
if ((SrcNumElts % DestNumElts) == 0) { |
0 |
| 23895 |
unsigned SrcDestRatio = SrcNumElts / DestNumElts; |
0 |
23895 |
unsigned SrcDestRatio = SrcNumElts / DestNumElts; |
0 |
| 23896 |
ElementCount NewExtEC = NVT.getVectorElementCount() * SrcDestRatio; |
0 |
23896 |
ElementCount NewExtEC = NVT.getVectorElementCount() * SrcDestRatio; |
0 |
| 23897 |
EVT NewExtVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(), |
0 |
23897 |
EVT NewExtVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(), |
0 |
| 23898 |
NewExtEC); |
--- |
23898 |
NewExtEC); |
--- |
| 23899 |
if (TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NewExtVT)) { |
0 |
23899 |
if (TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NewExtVT)) { |
0 |
| 23900 |
SDLoc DL(N); |
0 |
23900 |
SDLoc DL(N); |
0 |
| 23901 |
SDValue NewIndex = DAG.getVectorIdxConstant(ExtIdx * SrcDestRatio, DL); |
0 |
23901 |
SDValue NewIndex = DAG.getVectorIdxConstant(ExtIdx * SrcDestRatio, DL); |
0 |
| 23902 |
SDValue NewExtract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewExtVT, |
0 |
23902 |
SDValue NewExtract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewExtVT, |
0 |
| 23903 |
V.getOperand(0), NewIndex); |
0 |
23903 |
V.getOperand(0), NewIndex); |
0 |
| 23904 |
return DAG.getBitcast(NVT, NewExtract); |
0 |
23904 |
return DAG.getBitcast(NVT, NewExtract); |
0 |
| 23905 |
} |
0 |
23905 |
} |
0 |
| 23906 |
} |
--- |
23906 |
} |
--- |
| 23907 |
if ((DestNumElts % SrcNumElts) == 0) { |
0 |
23907 |
if ((DestNumElts % SrcNumElts) == 0) { |
0 |
| 23908 |
unsigned DestSrcRatio = DestNumElts / SrcNumElts; |
0 |
23908 |
unsigned DestSrcRatio = DestNumElts / SrcNumElts; |
0 |
| 23909 |
if (NVT.getVectorElementCount().isKnownMultipleOf(DestSrcRatio)) { |
0 |
23909 |
if (NVT.getVectorElementCount().isKnownMultipleOf(DestSrcRatio)) { |
0 |
| 23910 |
ElementCount NewExtEC = |
--- |
23910 |
ElementCount NewExtEC = |
--- |
| 23911 |
NVT.getVectorElementCount().divideCoefficientBy(DestSrcRatio); |
0 |
23911 |
NVT.getVectorElementCount().divideCoefficientBy(DestSrcRatio); |
0 |
| 23912 |
EVT ScalarVT = SrcVT.getScalarType(); |
0 |
23912 |
EVT ScalarVT = SrcVT.getScalarType(); |
0 |
| 23913 |
if ((ExtIdx % DestSrcRatio) == 0) { |
0 |
23913 |
if ((ExtIdx % DestSrcRatio) == 0) { |
0 |
| 23914 |
SDLoc DL(N); |
0 |
23914 |
SDLoc DL(N); |
0 |
| 23915 |
unsigned IndexValScaled = ExtIdx / DestSrcRatio; |
0 |
23915 |
unsigned IndexValScaled = ExtIdx / DestSrcRatio; |
0 |
| 23916 |
EVT NewExtVT = |
--- |
23916 |
EVT NewExtVT = |
--- |
| 23917 |
EVT::getVectorVT(*DAG.getContext(), ScalarVT, NewExtEC); |
0 |
23917 |
EVT::getVectorVT(*DAG.getContext(), ScalarVT, NewExtEC); |
0 |
| 23918 |
if (TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NewExtVT)) { |
0 |
23918 |
if (TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NewExtVT)) { |
0 |
| 23919 |
SDValue NewIndex = DAG.getVectorIdxConstant(IndexValScaled, DL); |
0 |
23919 |
SDValue NewIndex = DAG.getVectorIdxConstant(IndexValScaled, DL); |
0 |
| 23920 |
SDValue NewExtract = |
--- |
23920 |
SDValue NewExtract = |
--- |
| 23921 |
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewExtVT, |
0 |
23921 |
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewExtVT, |
0 |
| 23922 |
V.getOperand(0), NewIndex); |
0 |
23922 |
V.getOperand(0), NewIndex); |
0 |
| 23923 |
return DAG.getBitcast(NVT, NewExtract); |
0 |
23923 |
return DAG.getBitcast(NVT, NewExtract); |
0 |
| 23924 |
} |
--- |
23924 |
} |
--- |
| 23925 |
if (NewExtEC.isScalar() && |
0 |
23925 |
if (NewExtEC.isScalar() && |
0 |
| 23926 |
TLI.isOperationLegalOrCustom(ISD::EXTRACT_VECTOR_ELT, ScalarVT)) { |
0 |
23926 |
TLI.isOperationLegalOrCustom(ISD::EXTRACT_VECTOR_ELT, ScalarVT)) { |
0 |
| 23927 |
SDValue NewIndex = DAG.getVectorIdxConstant(IndexValScaled, DL); |
0 |
23927 |
SDValue NewIndex = DAG.getVectorIdxConstant(IndexValScaled, DL); |
0 |
| 23928 |
SDValue NewExtract = |
--- |
23928 |
SDValue NewExtract = |
--- |
| 23929 |
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarVT, |
0 |
23929 |
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarVT, |
0 |
| 23930 |
V.getOperand(0), NewIndex); |
0 |
23930 |
V.getOperand(0), NewIndex); |
0 |
| 23931 |
return DAG.getBitcast(NVT, NewExtract); |
0 |
23931 |
return DAG.getBitcast(NVT, NewExtract); |
0 |
| 23932 |
} |
--- |
23932 |
} |
--- |
| 23933 |
} |
0 |
23933 |
} |
0 |
| 23934 |
} |
--- |
23934 |
} |
--- |
| 23935 |
} |
--- |
23935 |
} |
--- |
| 23936 |
} |
--- |
23936 |
} |
--- |
| 23937 |
|
--- |
23937 |
|
--- |
| 23938 |
if (V.getOpcode() == ISD::CONCAT_VECTORS) { |
0 |
23938 |
if (V.getOpcode() == ISD::CONCAT_VECTORS) { |
0 |
| 23939 |
unsigned ExtNumElts = NVT.getVectorMinNumElements(); |
0 |
23939 |
unsigned ExtNumElts = NVT.getVectorMinNumElements(); |
0 |
| 23940 |
EVT ConcatSrcVT = V.getOperand(0).getValueType(); |
0 |
23940 |
EVT ConcatSrcVT = V.getOperand(0).getValueType(); |
0 |
| 23941 |
assert(ConcatSrcVT.getVectorElementType() == NVT.getVectorElementType() && |
0 |
23941 |
assert(ConcatSrcVT.getVectorElementType() == NVT.getVectorElementType() && |
0 |
| 23942 |
"Concat and extract subvector do not change element type"); |
--- |
23942 |
"Concat and extract subvector do not change element type"); |
--- |
| 23943 |
assert((ExtIdx % ExtNumElts) == 0 && |
0 |
23943 |
assert((ExtIdx % ExtNumElts) == 0 && |
0 |
| 23944 |
"Extract index is not a multiple of the input vector length."); |
--- |
23944 |
"Extract index is not a multiple of the input vector length."); |
--- |
| 23945 |
|
--- |
23945 |
|
--- |
| 23946 |
unsigned ConcatSrcNumElts = ConcatSrcVT.getVectorMinNumElements(); |
0 |
23946 |
unsigned ConcatSrcNumElts = ConcatSrcVT.getVectorMinNumElements(); |
0 |
| 23947 |
unsigned ConcatOpIdx = ExtIdx / ConcatSrcNumElts; |
0 |
23947 |
unsigned ConcatOpIdx = ExtIdx / ConcatSrcNumElts; |
0 |
| 23948 |
|
--- |
23948 |
|
--- |
| 23949 |
// If the concatenated source types match this extract, it's a direct |
--- |
23949 |
// If the concatenated source types match this extract, it's a direct |
--- |
| 23950 |
// simplification: |
--- |
23950 |
// simplification: |
--- |
| 23951 |
// extract_subvec (concat V1, V2, ...), i --> Vi |
--- |
23951 |
// extract_subvec (concat V1, V2, ...), i --> Vi |
--- |
| 23952 |
if (NVT.getVectorElementCount() == ConcatSrcVT.getVectorElementCount()) |
0 |
23952 |
if (NVT.getVectorElementCount() == ConcatSrcVT.getVectorElementCount()) |
0 |
| 23953 |
return V.getOperand(ConcatOpIdx); |
0 |
23953 |
return V.getOperand(ConcatOpIdx); |
0 |
| 23954 |
|
--- |
23954 |
|
--- |
| 23955 |
// If the concatenated source vectors are a multiple length of this extract, |
--- |
23955 |
// If the concatenated source vectors are a multiple length of this extract, |
--- |
| 23956 |
// then extract a fraction of one of those source vectors directly from a |
--- |
23956 |
// then extract a fraction of one of those source vectors directly from a |
--- |
| 23957 |
// concat operand. Example: |
--- |
23957 |
// concat operand. Example: |
--- |
| 23958 |
// v2i8 extract_subvec (v16i8 concat (v8i8 X), (v8i8 Y), 14 --> |
--- |
23958 |
// v2i8 extract_subvec (v16i8 concat (v8i8 X), (v8i8 Y), 14 --> |
--- |
| 23959 |
// v2i8 extract_subvec v8i8 Y, 6 |
--- |
23959 |
// v2i8 extract_subvec v8i8 Y, 6 |
--- |
| 23960 |
if (NVT.isFixedLengthVector() && ConcatSrcVT.isFixedLengthVector() && |
0 |
23960 |
if (NVT.isFixedLengthVector() && ConcatSrcVT.isFixedLengthVector() && |
0 |
| 23961 |
ConcatSrcNumElts % ExtNumElts == 0) { |
0 |
23961 |
ConcatSrcNumElts % ExtNumElts == 0) { |
0 |
| 23962 |
SDLoc DL(N); |
0 |
23962 |
SDLoc DL(N); |
0 |
| 23963 |
unsigned NewExtIdx = ExtIdx - ConcatOpIdx * ConcatSrcNumElts; |
0 |
23963 |
unsigned NewExtIdx = ExtIdx - ConcatOpIdx * ConcatSrcNumElts; |
0 |
| 23964 |
assert(NewExtIdx + ExtNumElts <= ConcatSrcNumElts && |
0 |
23964 |
assert(NewExtIdx + ExtNumElts <= ConcatSrcNumElts && |
0 |
| 23965 |
"Trying to extract from >1 concat operand?"); |
--- |
23965 |
"Trying to extract from >1 concat operand?"); |
--- |
| 23966 |
assert(NewExtIdx % ExtNumElts == 0 && |
0 |
23966 |
assert(NewExtIdx % ExtNumElts == 0 && |
0 |
| 23967 |
"Extract index is not a multiple of the input vector length."); |
--- |
23967 |
"Extract index is not a multiple of the input vector length."); |
--- |
| 23968 |
SDValue NewIndexC = DAG.getVectorIdxConstant(NewExtIdx, DL); |
0 |
23968 |
SDValue NewIndexC = DAG.getVectorIdxConstant(NewExtIdx, DL); |
0 |
| 23969 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NVT, |
0 |
23969 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NVT, |
0 |
| 23970 |
V.getOperand(ConcatOpIdx), NewIndexC); |
0 |
23970 |
V.getOperand(ConcatOpIdx), NewIndexC); |
0 |
| 23971 |
} |
0 |
23971 |
} |
0 |
| 23972 |
} |
--- |
23972 |
} |
--- |
| 23973 |
|
--- |
23973 |
|
--- |
| 23974 |
if (SDValue V = |
0 |
23974 |
if (SDValue V = |
0 |
| 23975 |
foldExtractSubvectorFromShuffleVector(N, DAG, TLI, LegalOperations)) |
0 |
23975 |
foldExtractSubvectorFromShuffleVector(N, DAG, TLI, LegalOperations)) |
0 |
| 23976 |
return V; |
0 |
23976 |
return V; |
0 |
| 23977 |
|
--- |
23977 |
|
--- |
| 23978 |
V = peekThroughBitcasts(V); |
0 |
23978 |
V = peekThroughBitcasts(V); |
0 |
| 23979 |
|
--- |
23979 |
|
--- |
| 23980 |
// If the input is a build vector. Try to make a smaller build vector. |
--- |
23980 |
// If the input is a build vector. Try to make a smaller build vector. |
--- |
| 23981 |
if (V.getOpcode() == ISD::BUILD_VECTOR) { |
0 |
23981 |
if (V.getOpcode() == ISD::BUILD_VECTOR) { |
0 |
| 23982 |
EVT InVT = V.getValueType(); |
0 |
23982 |
EVT InVT = V.getValueType(); |
0 |
| 23983 |
unsigned ExtractSize = NVT.getSizeInBits(); |
0 |
23983 |
unsigned ExtractSize = NVT.getSizeInBits(); |
0 |
| 23984 |
unsigned EltSize = InVT.getScalarSizeInBits(); |
0 |
23984 |
unsigned EltSize = InVT.getScalarSizeInBits(); |
0 |
| 23985 |
// Only do this if we won't split any elements. |
--- |
23985 |
// Only do this if we won't split any elements. |
--- |
| 23986 |
if (ExtractSize % EltSize == 0) { |
0 |
23986 |
if (ExtractSize % EltSize == 0) { |
0 |
| 23987 |
unsigned NumElems = ExtractSize / EltSize; |
0 |
23987 |
unsigned NumElems = ExtractSize / EltSize; |
0 |
| 23988 |
EVT EltVT = InVT.getVectorElementType(); |
0 |
23988 |
EVT EltVT = InVT.getVectorElementType(); |
0 |
| 23989 |
EVT ExtractVT = |
--- |
23989 |
EVT ExtractVT = |
--- |
| 23990 |
NumElems == 1 ? EltVT |
--- |
23990 |
NumElems == 1 ? EltVT |
--- |
| 23991 |
: EVT::getVectorVT(*DAG.getContext(), EltVT, NumElems); |
0 |
23991 |
: EVT::getVectorVT(*DAG.getContext(), EltVT, NumElems); |
0 |
| 23992 |
if ((Level < AfterLegalizeDAG || |
0 |
23992 |
if ((Level < AfterLegalizeDAG || |
0 |
| 23993 |
(NumElems == 1 || |
0 |
23993 |
(NumElems == 1 || |
0 |
| 23994 |
TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT))) && |
0 |
23994 |
TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT))) && |
0 |
| 23995 |
(!LegalTypes || TLI.isTypeLegal(ExtractVT))) { |
0 |
23995 |
(!LegalTypes || TLI.isTypeLegal(ExtractVT))) { |
0 |
| 23996 |
unsigned IdxVal = (ExtIdx * NVT.getScalarSizeInBits()) / EltSize; |
0 |
23996 |
unsigned IdxVal = (ExtIdx * NVT.getScalarSizeInBits()) / EltSize; |
0 |
| 23997 |
|
--- |
23997 |
|
--- |
| 23998 |
if (NumElems == 1) { |
0 |
23998 |
if (NumElems == 1) { |
0 |
| 23999 |
SDValue Src = V->getOperand(IdxVal); |
0 |
23999 |
SDValue Src = V->getOperand(IdxVal); |
0 |
| 24000 |
if (EltVT != Src.getValueType()) |
0 |
24000 |
if (EltVT != Src.getValueType()) |
0 |
| 24001 |
Src = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Src); |
0 |
24001 |
Src = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Src); |
0 |
| 24002 |
return DAG.getBitcast(NVT, Src); |
0 |
24002 |
return DAG.getBitcast(NVT, Src); |
0 |
| 24003 |
} |
--- |
24003 |
} |
--- |
| 24004 |
|
--- |
24004 |
|
--- |
| 24005 |
// Extract the pieces from the original build_vector. |
--- |
24005 |
// Extract the pieces from the original build_vector. |
--- |
| 24006 |
SDValue BuildVec = DAG.getBuildVector(ExtractVT, SDLoc(N), |
0 |
24006 |
SDValue BuildVec = DAG.getBuildVector(ExtractVT, SDLoc(N), |
0 |
| 24007 |
V->ops().slice(IdxVal, NumElems)); |
0 |
24007 |
V->ops().slice(IdxVal, NumElems)); |
0 |
| 24008 |
return DAG.getBitcast(NVT, BuildVec); |
0 |
24008 |
return DAG.getBitcast(NVT, BuildVec); |
0 |
| 24009 |
} |
--- |
24009 |
} |
--- |
| 24010 |
} |
--- |
24010 |
} |
--- |
| 24011 |
} |
--- |
24011 |
} |
--- |
| 24012 |
|
--- |
24012 |
|
--- |
| 24013 |
if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { |
0 |
24013 |
if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { |
0 |
| 24014 |
// Handle only simple case where vector being inserted and vector |
--- |
24014 |
// Handle only simple case where vector being inserted and vector |
--- |
| 24015 |
// being extracted are of same size. |
--- |
24015 |
// being extracted are of same size. |
--- |
| 24016 |
EVT SmallVT = V.getOperand(1).getValueType(); |
0 |
24016 |
EVT SmallVT = V.getOperand(1).getValueType(); |
0 |
| 24017 |
if (!NVT.bitsEq(SmallVT)) |
0 |
24017 |
if (!NVT.bitsEq(SmallVT)) |
0 |
| 24018 |
return SDValue(); |
0 |
24018 |
return SDValue(); |
0 |
| 24019 |
|
--- |
24019 |
|
--- |
| 24020 |
// Combine: |
--- |
24020 |
// Combine: |
--- |
| 24021 |
// (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) |
--- |
24021 |
// (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) |
--- |
| 24022 |
// Into: |
--- |
24022 |
// Into: |
--- |
| 24023 |
// indices are equal or bit offsets are equal => V1 |
--- |
24023 |
// indices are equal or bit offsets are equal => V1 |
--- |
| 24024 |
// otherwise => (extract_subvec V1, ExtIdx) |
--- |
24024 |
// otherwise => (extract_subvec V1, ExtIdx) |
--- |
| 24025 |
uint64_t InsIdx = V.getConstantOperandVal(2); |
0 |
24025 |
uint64_t InsIdx = V.getConstantOperandVal(2); |
0 |
| 24026 |
if (InsIdx * SmallVT.getScalarSizeInBits() == |
0 |
24026 |
if (InsIdx * SmallVT.getScalarSizeInBits() == |
0 |
| 24027 |
ExtIdx * NVT.getScalarSizeInBits()) { |
0 |
24027 |
ExtIdx * NVT.getScalarSizeInBits()) { |
0 |
| 24028 |
if (LegalOperations && !TLI.isOperationLegal(ISD::BITCAST, NVT)) |
0 |
24028 |
if (LegalOperations && !TLI.isOperationLegal(ISD::BITCAST, NVT)) |
0 |
| 24029 |
return SDValue(); |
0 |
24029 |
return SDValue(); |
0 |
| 24030 |
|
--- |
24030 |
|
--- |
| 24031 |
return DAG.getBitcast(NVT, V.getOperand(1)); |
0 |
24031 |
return DAG.getBitcast(NVT, V.getOperand(1)); |
0 |
| 24032 |
} |
--- |
24032 |
} |
--- |
| 24033 |
return DAG.getNode( |
0 |
24033 |
return DAG.getNode( |
0 |
| 24034 |
ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, |
0 |
24034 |
ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, |
0 |
| 24035 |
DAG.getBitcast(N->getOperand(0).getValueType(), V.getOperand(0)), |
0 |
24035 |
DAG.getBitcast(N->getOperand(0).getValueType(), V.getOperand(0)), |
0 |
| 24036 |
N->getOperand(1)); |
0 |
24036 |
N->getOperand(1)); |
0 |
| 24037 |
} |
--- |
24037 |
} |
--- |
| 24038 |
|
--- |
24038 |
|
--- |
| 24039 |
if (SDValue NarrowBOp = narrowExtractedVectorBinOp(N, DAG, LegalOperations)) |
0 |
24039 |
if (SDValue NarrowBOp = narrowExtractedVectorBinOp(N, DAG, LegalOperations)) |
0 |
| 24040 |
return NarrowBOp; |
0 |
24040 |
return NarrowBOp; |
0 |
| 24041 |
|
--- |
24041 |
|
--- |
| 24042 |
if (SimplifyDemandedVectorElts(SDValue(N, 0))) |
0 |
24042 |
if (SimplifyDemandedVectorElts(SDValue(N, 0))) |
0 |
| 24043 |
return SDValue(N, 0); |
0 |
24043 |
return SDValue(N, 0); |
0 |
| 24044 |
|
--- |
24044 |
|
--- |
| 24045 |
return SDValue(); |
0 |
24045 |
return SDValue(); |
0 |
| 24046 |
} |
--- |
24046 |
} |
--- |
| 24047 |
|
--- |
24047 |
|
--- |
| 24048 |
/// Try to convert a wide shuffle of concatenated vectors into 2 narrow shuffles |
--- |
24048 |
/// Try to convert a wide shuffle of concatenated vectors into 2 narrow shuffles |
--- |
| 24049 |
/// followed by concatenation. Narrow vector ops may have better performance |
--- |
24049 |
/// followed by concatenation. Narrow vector ops may have better performance |
--- |
| 24050 |
/// than wide ops, and this can unlock further narrowing of other vector ops. |
--- |
24050 |
/// than wide ops, and this can unlock further narrowing of other vector ops. |
--- |
| 24051 |
/// Targets can invert this transform later if it is not profitable. |
--- |
24051 |
/// Targets can invert this transform later if it is not profitable. |
--- |
| 24052 |
static SDValue foldShuffleOfConcatUndefs(ShuffleVectorSDNode *Shuf, |
0 |
24052 |
static SDValue foldShuffleOfConcatUndefs(ShuffleVectorSDNode *Shuf, |
0 |
| 24053 |
SelectionDAG &DAG) { |
--- |
24053 |
SelectionDAG &DAG) { |
--- |
| 24054 |
SDValue N0 = Shuf->getOperand(0), N1 = Shuf->getOperand(1); |
0 |
24054 |
SDValue N0 = Shuf->getOperand(0), N1 = Shuf->getOperand(1); |
0 |
| 24055 |
if (N0.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 || |
0 |
24055 |
if (N0.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 || |
0 |
| 24056 |
N1.getOpcode() != ISD::CONCAT_VECTORS || N1.getNumOperands() != 2 || |
0 |
24056 |
N1.getOpcode() != ISD::CONCAT_VECTORS || N1.getNumOperands() != 2 || |
0 |
| 24057 |
!N0.getOperand(1).isUndef() || !N1.getOperand(1).isUndef()) |
0 |
24057 |
!N0.getOperand(1).isUndef() || !N1.getOperand(1).isUndef()) |
0 |
| 24058 |
return SDValue(); |
0 |
24058 |
return SDValue(); |
0 |
| 24059 |
|
--- |
24059 |
|
--- |
| 24060 |
// Split the wide shuffle mask into halves. Any mask element that is accessing |
--- |
24060 |
// Split the wide shuffle mask into halves. Any mask element that is accessing |
--- |
| 24061 |
// operand 1 is offset down to account for narrowing of the vectors. |
--- |
24061 |
// operand 1 is offset down to account for narrowing of the vectors. |
--- |
| 24062 |
ArrayRef Mask = Shuf->getMask(); |
0 |
24062 |
ArrayRef Mask = Shuf->getMask(); |
0 |
| 24063 |
EVT VT = Shuf->getValueType(0); |
0 |
24063 |
EVT VT = Shuf->getValueType(0); |
0 |
| 24064 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
24064 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
| 24065 |
unsigned HalfNumElts = NumElts / 2; |
0 |
24065 |
unsigned HalfNumElts = NumElts / 2; |
0 |
| 24066 |
SmallVector Mask0(HalfNumElts, -1); |
0 |
24066 |
SmallVector Mask0(HalfNumElts, -1); |
0 |
| 24067 |
SmallVector Mask1(HalfNumElts, -1); |
0 |
24067 |
SmallVector Mask1(HalfNumElts, -1); |
0 |
| 24068 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
24068 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
| 24069 |
if (Mask[i] == -1) |
0 |
24069 |
if (Mask[i] == -1) |
0 |
| 24070 |
continue; |
0 |
24070 |
continue; |
0 |
| 24071 |
// If we reference the upper (undef) subvector then the element is undef. |
--- |
24071 |
// If we reference the upper (undef) subvector then the element is undef. |
--- |
| 24072 |
if ((Mask[i] % NumElts) >= HalfNumElts) |
0 |
24072 |
if ((Mask[i] % NumElts) >= HalfNumElts) |
0 |
| 24073 |
continue; |
0 |
24073 |
continue; |
0 |
| 24074 |
int M = Mask[i] < (int)NumElts ? Mask[i] : Mask[i] - (int)HalfNumElts; |
0 |
24074 |
int M = Mask[i] < (int)NumElts ? Mask[i] : Mask[i] - (int)HalfNumElts; |
0 |
| 24075 |
if (i < HalfNumElts) |
0 |
24075 |
if (i < HalfNumElts) |
0 |
| 24076 |
Mask0[i] = M; |
0 |
24076 |
Mask0[i] = M; |
0 |
| 24077 |
else |
--- |
24077 |
else |
--- |
| 24078 |
Mask1[i - HalfNumElts] = M; |
0 |
24078 |
Mask1[i - HalfNumElts] = M; |
0 |
| 24079 |
} |
--- |
24079 |
} |
--- |
| 24080 |
|
--- |
24080 |
|
--- |
| 24081 |
// Ask the target if this is a valid transform. |
--- |
24081 |
// Ask the target if this is a valid transform. |
--- |
| 24082 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
24082 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 24083 |
EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), |
0 |
24083 |
EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), |
0 |
| 24084 |
HalfNumElts); |
--- |
24084 |
HalfNumElts); |
--- |
| 24085 |
if (!TLI.isShuffleMaskLegal(Mask0, HalfVT) || |
0 |
24085 |
if (!TLI.isShuffleMaskLegal(Mask0, HalfVT) || |
0 |
| 24086 |
!TLI.isShuffleMaskLegal(Mask1, HalfVT)) |
0 |
24086 |
!TLI.isShuffleMaskLegal(Mask1, HalfVT)) |
0 |
| 24087 |
return SDValue(); |
0 |
24087 |
return SDValue(); |
0 |
| 24088 |
|
--- |
24088 |
|
--- |
| 24089 |
// shuffle (concat X, undef), (concat Y, undef), Mask --> |
--- |
24089 |
// shuffle (concat X, undef), (concat Y, undef), Mask --> |
--- |
| 24090 |
// concat (shuffle X, Y, Mask0), (shuffle X, Y, Mask1) |
--- |
24090 |
// concat (shuffle X, Y, Mask0), (shuffle X, Y, Mask1) |
--- |
| 24091 |
SDValue X = N0.getOperand(0), Y = N1.getOperand(0); |
0 |
24091 |
SDValue X = N0.getOperand(0), Y = N1.getOperand(0); |
0 |
| 24092 |
SDLoc DL(Shuf); |
0 |
24092 |
SDLoc DL(Shuf); |
0 |
| 24093 |
SDValue Shuf0 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask0); |
0 |
24093 |
SDValue Shuf0 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask0); |
0 |
| 24094 |
SDValue Shuf1 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask1); |
0 |
24094 |
SDValue Shuf1 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask1); |
0 |
| 24095 |
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Shuf0, Shuf1); |
0 |
24095 |
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Shuf0, Shuf1); |
0 |
| 24096 |
} |
0 |
24096 |
} |
0 |
| 24097 |
|
--- |
24097 |
|
--- |
| 24098 |
// Tries to turn a shuffle of two CONCAT_VECTORS into a single concat, |
--- |
24098 |
// Tries to turn a shuffle of two CONCAT_VECTORS into a single concat, |
--- |
| 24099 |
// or turn a shuffle of a single concat into simpler shuffle then concat. |
--- |
24099 |
// or turn a shuffle of a single concat into simpler shuffle then concat. |
--- |
| 24100 |
static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) { |
0 |
24100 |
static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) { |
0 |
| 24101 |
EVT VT = N->getValueType(0); |
0 |
24101 |
EVT VT = N->getValueType(0); |
0 |
| 24102 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
24102 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
| 24103 |
|
--- |
24103 |
|
--- |
| 24104 |
SDValue N0 = N->getOperand(0); |
0 |
24104 |
SDValue N0 = N->getOperand(0); |
0 |
| 24105 |
SDValue N1 = N->getOperand(1); |
0 |
24105 |
SDValue N1 = N->getOperand(1); |
0 |
| 24106 |
ShuffleVectorSDNode *SVN = cast(N); |
0 |
24106 |
ShuffleVectorSDNode *SVN = cast(N); |
0 |
| 24107 |
ArrayRef Mask = SVN->getMask(); |
0 |
24107 |
ArrayRef Mask = SVN->getMask(); |
0 |
| 24108 |
|
--- |
24108 |
|
--- |
| 24109 |
SmallVector Ops; |
0 |
24109 |
SmallVector Ops; |
0 |
| 24110 |
EVT ConcatVT = N0.getOperand(0).getValueType(); |
0 |
24110 |
EVT ConcatVT = N0.getOperand(0).getValueType(); |
0 |
| 24111 |
unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements(); |
0 |
24111 |
unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements(); |
0 |
| 24112 |
unsigned NumConcats = NumElts / NumElemsPerConcat; |
0 |
24112 |
unsigned NumConcats = NumElts / NumElemsPerConcat; |
0 |
| 24113 |
|
--- |
24113 |
|
--- |
| 24114 |
auto IsUndefMaskElt = [](int i) { return i == -1; }; |
0 |
24114 |
auto IsUndefMaskElt = [](int i) { return i == -1; }; |
0 |
| 24115 |
|
--- |
24115 |
|
--- |
| 24116 |
// Special case: shuffle(concat(A,B)) can be more efficiently represented |
--- |
24116 |
// Special case: shuffle(concat(A,B)) can be more efficiently represented |
--- |
| 24117 |
// as concat(shuffle(A,B),UNDEF) if the shuffle doesn't set any of the high |
--- |
24117 |
// as concat(shuffle(A,B),UNDEF) if the shuffle doesn't set any of the high |
--- |
| 24118 |
// half vector elements. |
--- |
24118 |
// half vector elements. |
--- |
| 24119 |
if (NumElemsPerConcat * 2 == NumElts && N1.isUndef() && |
0 |
24119 |
if (NumElemsPerConcat * 2 == NumElts && N1.isUndef() && |
0 |
| 24120 |
llvm::all_of(Mask.slice(NumElemsPerConcat, NumElemsPerConcat), |
0 |
24120 |
llvm::all_of(Mask.slice(NumElemsPerConcat, NumElemsPerConcat), |
0 |
| 24121 |
IsUndefMaskElt)) { |
--- |
24121 |
IsUndefMaskElt)) { |
--- |
| 24122 |
N0 = DAG.getVectorShuffle(ConcatVT, SDLoc(N), N0.getOperand(0), |
0 |
24122 |
N0 = DAG.getVectorShuffle(ConcatVT, SDLoc(N), N0.getOperand(0), |
0 |
| 24123 |
N0.getOperand(1), |
0 |
24123 |
N0.getOperand(1), |
0 |
| 24124 |
Mask.slice(0, NumElemsPerConcat)); |
--- |
24124 |
Mask.slice(0, NumElemsPerConcat)); |
--- |
| 24125 |
N1 = DAG.getUNDEF(ConcatVT); |
0 |
24125 |
N1 = DAG.getUNDEF(ConcatVT); |
0 |
| 24126 |
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, N0, N1); |
0 |
24126 |
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, N0, N1); |
0 |
| 24127 |
} |
--- |
24127 |
} |
--- |
| 24128 |
|
--- |
24128 |
|
--- |
| 24129 |
// Look at every vector that's inserted. We're looking for exact |
--- |
24129 |
// Look at every vector that's inserted. We're looking for exact |
--- |
| 24130 |
// subvector-sized copies from a concatenated vector |
--- |
24130 |
// subvector-sized copies from a concatenated vector |
--- |
| 24131 |
for (unsigned I = 0; I != NumConcats; ++I) { |
0 |
24131 |
for (unsigned I = 0; I != NumConcats; ++I) { |
0 |
| 24132 |
unsigned Begin = I * NumElemsPerConcat; |
0 |
24132 |
unsigned Begin = I * NumElemsPerConcat; |
0 |
| 24133 |
ArrayRef SubMask = Mask.slice(Begin, NumElemsPerConcat); |
0 |
24133 |
ArrayRef SubMask = Mask.slice(Begin, NumElemsPerConcat); |
0 |
| 24134 |
|
--- |
24134 |
|
--- |
| 24135 |
// Make sure we're dealing with a copy. |
--- |
24135 |
// Make sure we're dealing with a copy. |
--- |
| 24136 |
if (llvm::all_of(SubMask, IsUndefMaskElt)) { |
0 |
24136 |
if (llvm::all_of(SubMask, IsUndefMaskElt)) { |
0 |
| 24137 |
Ops.push_back(DAG.getUNDEF(ConcatVT)); |
0 |
24137 |
Ops.push_back(DAG.getUNDEF(ConcatVT)); |
0 |
| 24138 |
continue; |
0 |
24138 |
continue; |
0 |
| 24139 |
} |
--- |
24139 |
} |
--- |
| 24140 |
|
--- |
24140 |
|
--- |
| 24141 |
int OpIdx = -1; |
0 |
24141 |
int OpIdx = -1; |
0 |
| 24142 |
for (int i = 0; i != (int)NumElemsPerConcat; ++i) { |
0 |
24142 |
for (int i = 0; i != (int)NumElemsPerConcat; ++i) { |
0 |
| 24143 |
if (IsUndefMaskElt(SubMask[i])) |
0 |
24143 |
if (IsUndefMaskElt(SubMask[i])) |
0 |
| 24144 |
continue; |
0 |
24144 |
continue; |
0 |
| 24145 |
if ((SubMask[i] % (int)NumElemsPerConcat) != i) |
0 |
24145 |
if ((SubMask[i] % (int)NumElemsPerConcat) != i) |
0 |
| 24146 |
return SDValue(); |
0 |
24146 |
return SDValue(); |
0 |
| 24147 |
int EltOpIdx = SubMask[i] / NumElemsPerConcat; |
0 |
24147 |
int EltOpIdx = SubMask[i] / NumElemsPerConcat; |
0 |
| 24148 |
if (0 <= OpIdx && EltOpIdx != OpIdx) |
0 |
24148 |
if (0 <= OpIdx && EltOpIdx != OpIdx) |
0 |
| 24149 |
return SDValue(); |
0 |
24149 |
return SDValue(); |
0 |
| 24150 |
OpIdx = EltOpIdx; |
0 |
24150 |
OpIdx = EltOpIdx; |
0 |
| 24151 |
} |
--- |
24151 |
} |
--- |
| 24152 |
assert(0 <= OpIdx && "Unknown concat_vectors op"); |
0 |
24152 |
assert(0 <= OpIdx && "Unknown concat_vectors op"); |
0 |
| 24153 |
|
--- |
24153 |
|
--- |
| 24154 |
if (OpIdx < (int)N0.getNumOperands()) |
0 |
24154 |
if (OpIdx < (int)N0.getNumOperands()) |
0 |
| 24155 |
Ops.push_back(N0.getOperand(OpIdx)); |
0 |
24155 |
Ops.push_back(N0.getOperand(OpIdx)); |
0 |
| 24156 |
else |
--- |
24156 |
else |
--- |
| 24157 |
Ops.push_back(N1.getOperand(OpIdx - N0.getNumOperands())); |
0 |
24157 |
Ops.push_back(N1.getOperand(OpIdx - N0.getNumOperands())); |
0 |
| 24158 |
} |
--- |
24158 |
} |
--- |
| 24159 |
|
--- |
24159 |
|
--- |
| 24160 |
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops); |
0 |
24160 |
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops); |
0 |
| 24161 |
} |
0 |
24161 |
} |
0 |
| 24162 |
|
--- |
24162 |
|
--- |
| 24163 |
// Attempt to combine a shuffle of 2 inputs of 'scalar sources' - |
--- |
24163 |
// Attempt to combine a shuffle of 2 inputs of 'scalar sources' - |
--- |
| 24164 |
// BUILD_VECTOR or SCALAR_TO_VECTOR into a single BUILD_VECTOR. |
--- |
24164 |
// BUILD_VECTOR or SCALAR_TO_VECTOR into a single BUILD_VECTOR. |
--- |
| 24165 |
// |
--- |
24165 |
// |
--- |
| 24166 |
// SHUFFLE(BUILD_VECTOR(), BUILD_VECTOR()) -> BUILD_VECTOR() is always |
--- |
24166 |
// SHUFFLE(BUILD_VECTOR(), BUILD_VECTOR()) -> BUILD_VECTOR() is always |
--- |
| 24167 |
// a simplification in some sense, but it isn't appropriate in general: some |
--- |
24167 |
// a simplification in some sense, but it isn't appropriate in general: some |
--- |
| 24168 |
// BUILD_VECTORs are substantially cheaper than others. The general case |
--- |
24168 |
// BUILD_VECTORs are substantially cheaper than others. The general case |
--- |
| 24169 |
// of a BUILD_VECTOR requires inserting each element individually (or |
--- |
24169 |
// of a BUILD_VECTOR requires inserting each element individually (or |
--- |
| 24170 |
// performing the equivalent in a temporary stack variable). A BUILD_VECTOR of |
--- |
24170 |
// performing the equivalent in a temporary stack variable). A BUILD_VECTOR of |
--- |
| 24171 |
// all constants is a single constant pool load. A BUILD_VECTOR where each |
--- |
24171 |
// all constants is a single constant pool load. A BUILD_VECTOR where each |
--- |
| 24172 |
// element is identical is a splat. A BUILD_VECTOR where most of the operands |
--- |
24172 |
// element is identical is a splat. A BUILD_VECTOR where most of the operands |
--- |
| 24173 |
// are undef lowers to a small number of element insertions. |
--- |
24173 |
// are undef lowers to a small number of element insertions. |
--- |
| 24174 |
// |
--- |
24174 |
// |
--- |
| 24175 |
// To deal with this, we currently use a bunch of mostly arbitrary heuristics. |
--- |
24175 |
// To deal with this, we currently use a bunch of mostly arbitrary heuristics. |
--- |
| 24176 |
// We don't fold shuffles where one side is a non-zero constant, and we don't |
--- |
24176 |
// We don't fold shuffles where one side is a non-zero constant, and we don't |
--- |
| 24177 |
// fold shuffles if the resulting (non-splat) BUILD_VECTOR would have duplicate |
--- |
24177 |
// fold shuffles if the resulting (non-splat) BUILD_VECTOR would have duplicate |
--- |
| 24178 |
// non-constant operands. This seems to work out reasonably well in practice. |
--- |
24178 |
// non-constant operands. This seems to work out reasonably well in practice. |
--- |
| 24179 |
static SDValue combineShuffleOfScalars(ShuffleVectorSDNode *SVN, |
0 |
24179 |
static SDValue combineShuffleOfScalars(ShuffleVectorSDNode *SVN, |
0 |
| 24180 |
SelectionDAG &DAG, |
--- |
24180 |
SelectionDAG &DAG, |
--- |
| 24181 |
const TargetLowering &TLI) { |
--- |
24181 |
const TargetLowering &TLI) { |
--- |
| 24182 |
EVT VT = SVN->getValueType(0); |
0 |
24182 |
EVT VT = SVN->getValueType(0); |
0 |
| 24183 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
24183 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
| 24184 |
SDValue N0 = SVN->getOperand(0); |
0 |
24184 |
SDValue N0 = SVN->getOperand(0); |
0 |
| 24185 |
SDValue N1 = SVN->getOperand(1); |
0 |
24185 |
SDValue N1 = SVN->getOperand(1); |
0 |
| 24186 |
|
--- |
24186 |
|
--- |
| 24187 |
if (!N0->hasOneUse()) |
0 |
24187 |
if (!N0->hasOneUse()) |
0 |
| 24188 |
return SDValue(); |
0 |
24188 |
return SDValue(); |
0 |
| 24189 |
|
--- |
24189 |
|
--- |
| 24190 |
// If only one of N1,N2 is constant, bail out if it is not ALL_ZEROS as |
--- |
24190 |
// If only one of N1,N2 is constant, bail out if it is not ALL_ZEROS as |
--- |
| 24191 |
// discussed above. |
--- |
24191 |
// discussed above. |
--- |
| 24192 |
if (!N1.isUndef()) { |
0 |
24192 |
if (!N1.isUndef()) { |
0 |
| 24193 |
if (!N1->hasOneUse()) |
0 |
24193 |
if (!N1->hasOneUse()) |
0 |
| 24194 |
return SDValue(); |
0 |
24194 |
return SDValue(); |
0 |
| 24195 |
|
--- |
24195 |
|
--- |
| 24196 |
bool N0AnyConst = isAnyConstantBuildVector(N0); |
0 |
24196 |
bool N0AnyConst = isAnyConstantBuildVector(N0); |
0 |
| 24197 |
bool N1AnyConst = isAnyConstantBuildVector(N1); |
0 |
24197 |
bool N1AnyConst = isAnyConstantBuildVector(N1); |
0 |
| 24198 |
if (N0AnyConst && !N1AnyConst && !ISD::isBuildVectorAllZeros(N0.getNode())) |
0 |
24198 |
if (N0AnyConst && !N1AnyConst && !ISD::isBuildVectorAllZeros(N0.getNode())) |
0 |
| 24199 |
return SDValue(); |
0 |
24199 |
return SDValue(); |
0 |
| 24200 |
if (!N0AnyConst && N1AnyConst && !ISD::isBuildVectorAllZeros(N1.getNode())) |
0 |
24200 |
if (!N0AnyConst && N1AnyConst && !ISD::isBuildVectorAllZeros(N1.getNode())) |
0 |
| 24201 |
return SDValue(); |
0 |
24201 |
return SDValue(); |
0 |
| 24202 |
} |
--- |
24202 |
} |
--- |
| 24203 |
|
--- |
24203 |
|
--- |
| 24204 |
// If both inputs are splats of the same value then we can safely merge this |
--- |
24204 |
// If both inputs are splats of the same value then we can safely merge this |
--- |
| 24205 |
// to a single BUILD_VECTOR with undef elements based on the shuffle mask. |
--- |
24205 |
// to a single BUILD_VECTOR with undef elements based on the shuffle mask. |
--- |
| 24206 |
bool IsSplat = false; |
0 |
24206 |
bool IsSplat = false; |
0 |
| 24207 |
auto *BV0 = dyn_cast(N0); |
0 |
24207 |
auto *BV0 = dyn_cast(N0); |
0 |
| 24208 |
auto *BV1 = dyn_cast(N1); |
0 |
24208 |
auto *BV1 = dyn_cast(N1); |
0 |
| 24209 |
if (BV0 && BV1) |
0 |
24209 |
if (BV0 && BV1) |
0 |
| 24210 |
if (SDValue Splat0 = BV0->getSplatValue()) |
0 |
24210 |
if (SDValue Splat0 = BV0->getSplatValue()) |
0 |
| 24211 |
IsSplat = (Splat0 == BV1->getSplatValue()); |
0 |
24211 |
IsSplat = (Splat0 == BV1->getSplatValue()); |
0 |
| 24212 |
|
--- |
24212 |
|
--- |
| 24213 |
SmallVector Ops; |
0 |
24213 |
SmallVector Ops; |
0 |
| 24214 |
SmallSet DuplicateOps; |
0 |
24214 |
SmallSet DuplicateOps; |
0 |
| 24215 |
for (int M : SVN->getMask()) { |
0 |
24215 |
for (int M : SVN->getMask()) { |
0 |
| 24216 |
SDValue Op = DAG.getUNDEF(VT.getScalarType()); |
0 |
24216 |
SDValue Op = DAG.getUNDEF(VT.getScalarType()); |
0 |
| 24217 |
if (M >= 0) { |
0 |
24217 |
if (M >= 0) { |
0 |
| 24218 |
int Idx = M < (int)NumElts ? M : M - NumElts; |
0 |
24218 |
int Idx = M < (int)NumElts ? M : M - NumElts; |
0 |
| 24219 |
SDValue &S = (M < (int)NumElts ? N0 : N1); |
0 |
24219 |
SDValue &S = (M < (int)NumElts ? N0 : N1); |
0 |
| 24220 |
if (S.getOpcode() == ISD::BUILD_VECTOR) { |
0 |
24220 |
if (S.getOpcode() == ISD::BUILD_VECTOR) { |
0 |
| 24221 |
Op = S.getOperand(Idx); |
0 |
24221 |
Op = S.getOperand(Idx); |
0 |
| 24222 |
} else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { |
0 |
24222 |
} else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) { |
0 |
| 24223 |
SDValue Op0 = S.getOperand(0); |
0 |
24223 |
SDValue Op0 = S.getOperand(0); |
0 |
| 24224 |
Op = Idx == 0 ? Op0 : DAG.getUNDEF(Op0.getValueType()); |
0 |
24224 |
Op = Idx == 0 ? Op0 : DAG.getUNDEF(Op0.getValueType()); |
0 |
| 24225 |
} else { |
--- |
24225 |
} else { |
--- |
| 24226 |
// Operand can't be combined - bail out. |
--- |
24226 |
// Operand can't be combined - bail out. |
--- |
| 24227 |
return SDValue(); |
0 |
24227 |
return SDValue(); |
0 |
| 24228 |
} |
--- |
24228 |
} |
--- |
| 24229 |
} |
--- |
24229 |
} |
--- |
| 24230 |
|
--- |
24230 |
|
--- |
| 24231 |
// Don't duplicate a non-constant BUILD_VECTOR operand unless we're |
--- |
24231 |
// Don't duplicate a non-constant BUILD_VECTOR operand unless we're |
--- |
| 24232 |
// generating a splat; semantically, this is fine, but it's likely to |
--- |
24232 |
// generating a splat; semantically, this is fine, but it's likely to |
--- |
| 24233 |
// generate low-quality code if the target can't reconstruct an appropriate |
--- |
24233 |
// generate low-quality code if the target can't reconstruct an appropriate |
--- |
| 24234 |
// shuffle. |
--- |
24234 |
// shuffle. |
--- |
| 24235 |
if (!Op.isUndef() && !isIntOrFPConstant(Op)) |
0 |
24235 |
if (!Op.isUndef() && !isIntOrFPConstant(Op)) |
0 |
| 24236 |
if (!IsSplat && !DuplicateOps.insert(Op).second) |
0 |
24236 |
if (!IsSplat && !DuplicateOps.insert(Op).second) |
0 |
| 24237 |
return SDValue(); |
0 |
24237 |
return SDValue(); |
0 |
| 24238 |
|
--- |
24238 |
|
--- |
| 24239 |
Ops.push_back(Op); |
0 |
24239 |
Ops.push_back(Op); |
0 |
| 24240 |
} |
--- |
24240 |
} |
--- |
| 24241 |
|
--- |
24241 |
|
--- |
| 24242 |
// BUILD_VECTOR requires all inputs to be of the same type, find the |
--- |
24242 |
// BUILD_VECTOR requires all inputs to be of the same type, find the |
--- |
| 24243 |
// maximum type and extend them all. |
--- |
24243 |
// maximum type and extend them all. |
--- |
| 24244 |
EVT SVT = VT.getScalarType(); |
0 |
24244 |
EVT SVT = VT.getScalarType(); |
0 |
| 24245 |
if (SVT.isInteger()) |
0 |
24245 |
if (SVT.isInteger()) |
0 |
| 24246 |
for (SDValue &Op : Ops) |
0 |
24246 |
for (SDValue &Op : Ops) |
0 |
| 24247 |
SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT); |
0 |
24247 |
SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT); |
0 |
| 24248 |
if (SVT != VT.getScalarType()) |
0 |
24248 |
if (SVT != VT.getScalarType()) |
0 |
| 24249 |
for (SDValue &Op : Ops) |
0 |
24249 |
for (SDValue &Op : Ops) |
0 |
| 24250 |
Op = Op.isUndef() ? DAG.getUNDEF(SVT) |
0 |
24250 |
Op = Op.isUndef() ? DAG.getUNDEF(SVT) |
0 |
| 24251 |
: (TLI.isZExtFree(Op.getValueType(), SVT) |
0 |
24251 |
: (TLI.isZExtFree(Op.getValueType(), SVT) |
0 |
| 24252 |
? DAG.getZExtOrTrunc(Op, SDLoc(SVN), SVT) |
0 |
24252 |
? DAG.getZExtOrTrunc(Op, SDLoc(SVN), SVT) |
0 |
| 24253 |
: DAG.getSExtOrTrunc(Op, SDLoc(SVN), SVT)); |
0 |
24253 |
: DAG.getSExtOrTrunc(Op, SDLoc(SVN), SVT)); |
0 |
| 24254 |
return DAG.getBuildVector(VT, SDLoc(SVN), Ops); |
0 |
24254 |
return DAG.getBuildVector(VT, SDLoc(SVN), Ops); |
0 |
| 24255 |
} |
0 |
24255 |
} |
0 |
| 24256 |
|
--- |
24256 |
|
--- |
| 24257 |
// Match shuffles that can be converted to *_vector_extend_in_reg. |
--- |
24257 |
// Match shuffles that can be converted to *_vector_extend_in_reg. |
--- |
| 24258 |
// This is often generated during legalization. |
--- |
24258 |
// This is often generated during legalization. |
--- |
| 24259 |
// e.g. v4i32 <0,u,1,u> -> (v2i64 any_vector_extend_in_reg(v4i32 src)), |
--- |
24259 |
// e.g. v4i32 <0,u,1,u> -> (v2i64 any_vector_extend_in_reg(v4i32 src)), |
--- |
| 24260 |
// and returns the EVT to which the extension should be performed. |
--- |
24260 |
// and returns the EVT to which the extension should be performed. |
--- |
| 24261 |
// NOTE: this assumes that the src is the first operand of the shuffle. |
--- |
24261 |
// NOTE: this assumes that the src is the first operand of the shuffle. |
--- |
| 24262 |
static std::optional canCombineShuffleToExtendVectorInreg( |
0 |
24262 |
static std::optional canCombineShuffleToExtendVectorInreg( |
0 |
| 24263 |
unsigned Opcode, EVT VT, std::function Match, |
--- |
24263 |
unsigned Opcode, EVT VT, std::function Match, |
--- |
| 24264 |
SelectionDAG &DAG, const TargetLowering &TLI, bool LegalTypes, |
--- |
24264 |
SelectionDAG &DAG, const TargetLowering &TLI, bool LegalTypes, |
--- |
| 24265 |
bool LegalOperations) { |
--- |
24265 |
bool LegalOperations) { |
--- |
| 24266 |
bool IsBigEndian = DAG.getDataLayout().isBigEndian(); |
0 |
24266 |
bool IsBigEndian = DAG.getDataLayout().isBigEndian(); |
0 |
| 24267 |
|
--- |
24267 |
|
--- |
| 24268 |
// TODO Add support for big-endian when we have a test case. |
--- |
24268 |
// TODO Add support for big-endian when we have a test case. |
--- |
| 24269 |
if (!VT.isInteger() || IsBigEndian) |
0 |
24269 |
if (!VT.isInteger() || IsBigEndian) |
0 |
| 24270 |
return std::nullopt; |
0 |
24270 |
return std::nullopt; |
0 |
| 24271 |
|
--- |
24271 |
|
--- |
| 24272 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
24272 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
| 24273 |
unsigned EltSizeInBits = VT.getScalarSizeInBits(); |
0 |
24273 |
unsigned EltSizeInBits = VT.getScalarSizeInBits(); |
0 |
| 24274 |
|
--- |
24274 |
|
--- |
| 24275 |
// Attempt to match a '*_extend_vector_inreg' shuffle, we just search for |
--- |
24275 |
// Attempt to match a '*_extend_vector_inreg' shuffle, we just search for |
--- |
| 24276 |
// power-of-2 extensions as they are the most likely. |
--- |
24276 |
// power-of-2 extensions as they are the most likely. |
--- |
| 24277 |
// FIXME: should try Scale == NumElts case too, |
--- |
24277 |
// FIXME: should try Scale == NumElts case too, |
--- |
| 24278 |
for (unsigned Scale = 2; Scale < NumElts; Scale *= 2) { |
0 |
24278 |
for (unsigned Scale = 2; Scale < NumElts; Scale *= 2) { |
0 |
| 24279 |
// The vector width must be a multiple of Scale. |
--- |
24279 |
// The vector width must be a multiple of Scale. |
--- |
| 24280 |
if (NumElts % Scale != 0) |
0 |
24280 |
if (NumElts % Scale != 0) |
0 |
| 24281 |
continue; |
0 |
24281 |
continue; |
0 |
| 24282 |
|
--- |
24282 |
|
--- |
| 24283 |
EVT OutSVT = EVT::getIntegerVT(*DAG.getContext(), EltSizeInBits * Scale); |
0 |
24283 |
EVT OutSVT = EVT::getIntegerVT(*DAG.getContext(), EltSizeInBits * Scale); |
0 |
| 24284 |
EVT OutVT = EVT::getVectorVT(*DAG.getContext(), OutSVT, NumElts / Scale); |
0 |
24284 |
EVT OutVT = EVT::getVectorVT(*DAG.getContext(), OutSVT, NumElts / Scale); |
0 |
| 24285 |
|
--- |
24285 |
|
--- |
| 24286 |
if ((LegalTypes && !TLI.isTypeLegal(OutVT)) || |
0 |
24286 |
if ((LegalTypes && !TLI.isTypeLegal(OutVT)) || |
0 |
| 24287 |
(LegalOperations && !TLI.isOperationLegalOrCustom(Opcode, OutVT))) |
0 |
24287 |
(LegalOperations && !TLI.isOperationLegalOrCustom(Opcode, OutVT))) |
0 |
| 24288 |
continue; |
0 |
24288 |
continue; |
0 |
| 24289 |
|
--- |
24289 |
|
--- |
| 24290 |
if (Match(Scale)) |
0 |
24290 |
if (Match(Scale)) |
0 |
| 24291 |
return OutVT; |
0 |
24291 |
return OutVT; |
0 |
| 24292 |
} |
--- |
24292 |
} |
--- |
| 24293 |
|
--- |
24293 |
|
--- |
| 24294 |
return std::nullopt; |
0 |
24294 |
return std::nullopt; |
0 |
| 24295 |
} |
--- |
24295 |
} |
--- |
| 24296 |
|
--- |
24296 |
|
--- |
| 24297 |
// Match shuffles that can be converted to any_vector_extend_in_reg. |
--- |
24297 |
// Match shuffles that can be converted to any_vector_extend_in_reg. |
--- |
| 24298 |
// This is often generated during legalization. |
--- |
24298 |
// This is often generated during legalization. |
--- |
| 24299 |
// e.g. v4i32 <0,u,1,u> -> (v2i64 any_vector_extend_in_reg(v4i32 src)) |
--- |
24299 |
// e.g. v4i32 <0,u,1,u> -> (v2i64 any_vector_extend_in_reg(v4i32 src)) |
--- |
| 24300 |
static SDValue combineShuffleToAnyExtendVectorInreg(ShuffleVectorSDNode *SVN, |
0 |
24300 |
static SDValue combineShuffleToAnyExtendVectorInreg(ShuffleVectorSDNode *SVN, |
0 |
| 24301 |
SelectionDAG &DAG, |
--- |
24301 |
SelectionDAG &DAG, |
--- |
| 24302 |
const TargetLowering &TLI, |
--- |
24302 |
const TargetLowering &TLI, |
--- |
| 24303 |
bool LegalOperations) { |
--- |
24303 |
bool LegalOperations) { |
--- |
| 24304 |
EVT VT = SVN->getValueType(0); |
0 |
24304 |
EVT VT = SVN->getValueType(0); |
0 |
| 24305 |
bool IsBigEndian = DAG.getDataLayout().isBigEndian(); |
0 |
24305 |
bool IsBigEndian = DAG.getDataLayout().isBigEndian(); |
0 |
| 24306 |
|
--- |
24306 |
|
--- |
| 24307 |
// TODO Add support for big-endian when we have a test case. |
--- |
24307 |
// TODO Add support for big-endian when we have a test case. |
--- |
| 24308 |
if (!VT.isInteger() || IsBigEndian) |
0 |
24308 |
if (!VT.isInteger() || IsBigEndian) |
0 |
| 24309 |
return SDValue(); |
0 |
24309 |
return SDValue(); |
0 |
| 24310 |
|
--- |
24310 |
|
--- |
| 24311 |
// shuffle<0,-1,1,-1> == (v2i64 anyextend_vector_inreg(v4i32)) |
--- |
24311 |
// shuffle<0,-1,1,-1> == (v2i64 anyextend_vector_inreg(v4i32)) |
--- |
| 24312 |
auto isAnyExtend = [NumElts = VT.getVectorNumElements(), |
0 |
24312 |
auto isAnyExtend = [NumElts = VT.getVectorNumElements(), |
0 |
| 24313 |
Mask = SVN->getMask()](unsigned Scale) { |
0 |
24313 |
Mask = SVN->getMask()](unsigned Scale) { |
0 |
| 24314 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
24314 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
| 24315 |
if (Mask[i] < 0) |
0 |
24315 |
if (Mask[i] < 0) |
0 |
| 24316 |
continue; |
0 |
24316 |
continue; |
0 |
| 24317 |
if ((i % Scale) == 0 && Mask[i] == (int)(i / Scale)) |
0 |
24317 |
if ((i % Scale) == 0 && Mask[i] == (int)(i / Scale)) |
0 |
| 24318 |
continue; |
0 |
24318 |
continue; |
0 |
| 24319 |
return false; |
0 |
24319 |
return false; |
0 |
| 24320 |
} |
--- |
24320 |
} |
--- |
| 24321 |
return true; |
0 |
24321 |
return true; |
0 |
| 24322 |
}; |
0 |
24322 |
}; |
0 |
| 24323 |
|
--- |
24323 |
|
--- |
| 24324 |
unsigned Opcode = ISD::ANY_EXTEND_VECTOR_INREG; |
0 |
24324 |
unsigned Opcode = ISD::ANY_EXTEND_VECTOR_INREG; |
0 |
| 24325 |
SDValue N0 = SVN->getOperand(0); |
0 |
24325 |
SDValue N0 = SVN->getOperand(0); |
0 |
| 24326 |
// Never create an illegal type. Only create unsupported operations if we |
--- |
24326 |
// Never create an illegal type. Only create unsupported operations if we |
--- |
| 24327 |
// are pre-legalization. |
--- |
24327 |
// are pre-legalization. |
--- |
| 24328 |
std::optional OutVT = canCombineShuffleToExtendVectorInreg( |
0 |
24328 |
std::optional OutVT = canCombineShuffleToExtendVectorInreg( |
0 |
| 24329 |
Opcode, VT, isAnyExtend, DAG, TLI, /*LegalTypes=*/true, LegalOperations); |
--- |
24329 |
Opcode, VT, isAnyExtend, DAG, TLI, /*LegalTypes=*/true, LegalOperations); |
--- |
| 24330 |
if (!OutVT) |
0 |
24330 |
if (!OutVT) |
0 |
| 24331 |
return SDValue(); |
0 |
24331 |
return SDValue(); |
0 |
| 24332 |
return DAG.getBitcast(VT, DAG.getNode(Opcode, SDLoc(SVN), *OutVT, N0)); |
0 |
24332 |
return DAG.getBitcast(VT, DAG.getNode(Opcode, SDLoc(SVN), *OutVT, N0)); |
0 |
| 24333 |
} |
--- |
24333 |
} |
--- |
| 24334 |
|
--- |
24334 |
|
--- |
| 24335 |
// Match shuffles that can be converted to zero_extend_vector_inreg. |
--- |
24335 |
// Match shuffles that can be converted to zero_extend_vector_inreg. |
--- |
| 24336 |
// This is often generated during legalization. |
--- |
24336 |
// This is often generated during legalization. |
--- |
| 24337 |
// e.g. v4i32 <0,z,1,u> -> (v2i64 zero_extend_vector_inreg(v4i32 src)) |
--- |
24337 |
// e.g. v4i32 <0,z,1,u> -> (v2i64 zero_extend_vector_inreg(v4i32 src)) |
--- |
| 24338 |
static SDValue combineShuffleToZeroExtendVectorInReg(ShuffleVectorSDNode *SVN, |
0 |
24338 |
static SDValue combineShuffleToZeroExtendVectorInReg(ShuffleVectorSDNode *SVN, |
0 |
| 24339 |
SelectionDAG &DAG, |
--- |
24339 |
SelectionDAG &DAG, |
--- |
| 24340 |
const TargetLowering &TLI, |
--- |
24340 |
const TargetLowering &TLI, |
--- |
| 24341 |
bool LegalOperations) { |
--- |
24341 |
bool LegalOperations) { |
--- |
| 24342 |
bool LegalTypes = true; |
0 |
24342 |
bool LegalTypes = true; |
0 |
| 24343 |
EVT VT = SVN->getValueType(0); |
0 |
24343 |
EVT VT = SVN->getValueType(0); |
0 |
| 24344 |
assert(!VT.isScalableVector() && "Encountered scalable shuffle?"); |
0 |
24344 |
assert(!VT.isScalableVector() && "Encountered scalable shuffle?"); |
0 |
| 24345 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
24345 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
| 24346 |
unsigned EltSizeInBits = VT.getScalarSizeInBits(); |
0 |
24346 |
unsigned EltSizeInBits = VT.getScalarSizeInBits(); |
0 |
| 24347 |
|
--- |
24347 |
|
--- |
| 24348 |
// TODO: add support for big-endian when we have a test case. |
--- |
24348 |
// TODO: add support for big-endian when we have a test case. |
--- |
| 24349 |
bool IsBigEndian = DAG.getDataLayout().isBigEndian(); |
0 |
24349 |
bool IsBigEndian = DAG.getDataLayout().isBigEndian(); |
0 |
| 24350 |
if (!VT.isInteger() || IsBigEndian) |
0 |
24350 |
if (!VT.isInteger() || IsBigEndian) |
0 |
| 24351 |
return SDValue(); |
0 |
24351 |
return SDValue(); |
0 |
| 24352 |
|
--- |
24352 |
|
--- |
| 24353 |
SmallVector Mask(SVN->getMask().begin(), SVN->getMask().end()); |
0 |
24353 |
SmallVector Mask(SVN->getMask().begin(), SVN->getMask().end()); |
0 |
| 24354 |
auto ForEachDecomposedIndice = [NumElts, &Mask](auto Fn) { |
0 |
24354 |
auto ForEachDecomposedIndice = [NumElts, &Mask](auto Fn) { |
0 |
| 24355 |
for (int &Indice : Mask) { |
0 |
24355 |
for (int &Indice : Mask) { |
0 |
| 24356 |
if (Indice < 0) |
0 |
24356 |
if (Indice < 0) |
0 |
| 24357 |
continue; |
0 |
24357 |
continue; |
0 |
| 24358 |
int OpIdx = (unsigned)Indice < NumElts ? 0 : 1; |
0 |
24358 |
int OpIdx = (unsigned)Indice < NumElts ? 0 : 1; |
0 |
| 24359 |
int OpEltIdx = (unsigned)Indice < NumElts ? Indice : Indice - NumElts; |
0 |
24359 |
int OpEltIdx = (unsigned)Indice < NumElts ? Indice : Indice - NumElts; |
0 |
| 24360 |
Fn(Indice, OpIdx, OpEltIdx); |
0 |
24360 |
Fn(Indice, OpIdx, OpEltIdx); |
0 |
| 24361 |
} |
--- |
24361 |
} |
--- |
| 24362 |
}; |
0 |
24362 |
}; |
0 |
| 24363 |
|
--- |
24363 |
|
--- |
| 24364 |
// Which elements of which operand does this shuffle demand? |
--- |
24364 |
// Which elements of which operand does this shuffle demand? |
--- |
| 24365 |
std::array OpsDemandedElts; |
0 |
24365 |
std::array OpsDemandedElts; |
0 |
| 24366 |
for (APInt &OpDemandedElts : OpsDemandedElts) |
0 |
24366 |
for (APInt &OpDemandedElts : OpsDemandedElts) |
0 |
| 24367 |
OpDemandedElts = APInt::getZero(NumElts); |
0 |
24367 |
OpDemandedElts = APInt::getZero(NumElts); |
0 |
| 24368 |
ForEachDecomposedIndice( |
0 |
24368 |
ForEachDecomposedIndice( |
0 |
| 24369 |
[&OpsDemandedElts](int &Indice, int OpIdx, int OpEltIdx) { |
0 |
24369 |
[&OpsDemandedElts](int &Indice, int OpIdx, int OpEltIdx) { |
0 |
| 24370 |
OpsDemandedElts[OpIdx].setBit(OpEltIdx); |
0 |
24370 |
OpsDemandedElts[OpIdx].setBit(OpEltIdx); |
0 |
| 24371 |
}); |
0 |
24371 |
}); |
0 |
| 24372 |
|
--- |
24372 |
|
--- |
| 24373 |
// Element-wise(!), which of these demanded elements are know to be zero? |
--- |
24373 |
// Element-wise(!), which of these demanded elements are know to be zero? |
--- |
| 24374 |
std::array OpsKnownZeroElts; |
0 |
24374 |
std::array OpsKnownZeroElts; |
0 |
| 24375 |
for (auto I : zip(SVN->ops(), OpsDemandedElts, OpsKnownZeroElts)) |
0 |
24375 |
for (auto I : zip(SVN->ops(), OpsDemandedElts, OpsKnownZeroElts)) |
0 |
| 24376 |
std::get<2>(I) = |
0 |
24376 |
std::get<2>(I) = |
0 |
| 24377 |
DAG.computeVectorKnownZeroElements(std::get<0>(I), std::get<1>(I)); |
0 |
24377 |
DAG.computeVectorKnownZeroElements(std::get<0>(I), std::get<1>(I)); |
0 |
| 24378 |
|
--- |
24378 |
|
--- |
| 24379 |
// Manifest zeroable element knowledge in the shuffle mask. |
--- |
24379 |
// Manifest zeroable element knowledge in the shuffle mask. |
--- |
| 24380 |
// NOTE: we don't have 'zeroable' sentinel value in generic DAG, |
--- |
24380 |
// NOTE: we don't have 'zeroable' sentinel value in generic DAG, |
--- |
| 24381 |
// this is a local invention, but it won't leak into DAG. |
--- |
24381 |
// this is a local invention, but it won't leak into DAG. |
--- |
| 24382 |
// FIXME: should we not manifest them, but just check when matching? |
--- |
24382 |
// FIXME: should we not manifest them, but just check when matching? |
--- |
| 24383 |
bool HadZeroableElts = false; |
0 |
24383 |
bool HadZeroableElts = false; |
0 |
| 24384 |
ForEachDecomposedIndice([&OpsKnownZeroElts, &HadZeroableElts]( |
0 |
24384 |
ForEachDecomposedIndice([&OpsKnownZeroElts, &HadZeroableElts]( |
0 |
| 24385 |
int &Indice, int OpIdx, int OpEltIdx) { |
0 |
24385 |
int &Indice, int OpIdx, int OpEltIdx) { |
0 |
| 24386 |
if (OpsKnownZeroElts[OpIdx][OpEltIdx]) { |
0 |
24386 |
if (OpsKnownZeroElts[OpIdx][OpEltIdx]) { |
0 |
| 24387 |
Indice = -2; // Zeroable element. |
0 |
24387 |
Indice = -2; // Zeroable element. |
0 |
| 24388 |
HadZeroableElts = true; |
0 |
24388 |
HadZeroableElts = true; |
0 |
| 24389 |
} |
--- |
24389 |
} |
--- |
| 24390 |
}); |
0 |
24390 |
}); |
0 |
| 24391 |
|
--- |
24391 |
|
--- |
| 24392 |
// Don't proceed unless we've refined at least one zeroable mask indice. |
--- |
24392 |
// Don't proceed unless we've refined at least one zeroable mask indice. |
--- |
| 24393 |
// If we didn't, then we are still trying to match the same shuffle mask |
--- |
24393 |
// If we didn't, then we are still trying to match the same shuffle mask |
--- |
| 24394 |
// we previously tried to match as ISD::ANY_EXTEND_VECTOR_INREG, |
--- |
24394 |
// we previously tried to match as ISD::ANY_EXTEND_VECTOR_INREG, |
--- |
| 24395 |
// and evidently failed. Proceeding will lead to endless combine loops. |
--- |
24395 |
// and evidently failed. Proceeding will lead to endless combine loops. |
--- |
| 24396 |
if (!HadZeroableElts) |
0 |
24396 |
if (!HadZeroableElts) |
0 |
| 24397 |
return SDValue(); |
0 |
24397 |
return SDValue(); |
0 |
| 24398 |
|
--- |
24398 |
|
--- |
| 24399 |
// The shuffle may be more fine-grained than we want. Widen elements first. |
--- |
24399 |
// The shuffle may be more fine-grained than we want. Widen elements first. |
--- |
| 24400 |
// FIXME: should we do this before manifesting zeroable shuffle mask indices? |
--- |
24400 |
// FIXME: should we do this before manifesting zeroable shuffle mask indices? |
--- |
| 24401 |
SmallVector ScaledMask; |
0 |
24401 |
SmallVector ScaledMask; |
0 |
| 24402 |
getShuffleMaskWithWidestElts(Mask, ScaledMask); |
0 |
24402 |
getShuffleMaskWithWidestElts(Mask, ScaledMask); |
0 |
| 24403 |
assert(Mask.size() >= ScaledMask.size() && |
0 |
24403 |
assert(Mask.size() >= ScaledMask.size() && |
0 |
| 24404 |
Mask.size() % ScaledMask.size() == 0 && "Unexpected mask widening."); |
--- |
24404 |
Mask.size() % ScaledMask.size() == 0 && "Unexpected mask widening."); |
--- |
| 24405 |
int Prescale = Mask.size() / ScaledMask.size(); |
0 |
24405 |
int Prescale = Mask.size() / ScaledMask.size(); |
0 |
| 24406 |
|
--- |
24406 |
|
--- |
| 24407 |
NumElts = ScaledMask.size(); |
0 |
24407 |
NumElts = ScaledMask.size(); |
0 |
| 24408 |
EltSizeInBits *= Prescale; |
0 |
24408 |
EltSizeInBits *= Prescale; |
0 |
| 24409 |
|
--- |
24409 |
|
--- |
| 24410 |
EVT PrescaledVT = EVT::getVectorVT( |
0 |
24410 |
EVT PrescaledVT = EVT::getVectorVT( |
0 |
| 24411 |
*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), EltSizeInBits), |
0 |
24411 |
*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), EltSizeInBits), |
0 |
| 24412 |
NumElts); |
--- |
24412 |
NumElts); |
--- |
| 24413 |
|
--- |
24413 |
|
--- |
| 24414 |
if (LegalTypes && !TLI.isTypeLegal(PrescaledVT) && TLI.isTypeLegal(VT)) |
0 |
24414 |
if (LegalTypes && !TLI.isTypeLegal(PrescaledVT) && TLI.isTypeLegal(VT)) |
0 |
| 24415 |
return SDValue(); |
0 |
24415 |
return SDValue(); |
0 |
| 24416 |
|
--- |
24416 |
|
--- |
| 24417 |
// For example, |
--- |
24417 |
// For example, |
--- |
| 24418 |
// shuffle<0,z,1,-1> == (v2i64 zero_extend_vector_inreg(v4i32)) |
--- |
24418 |
// shuffle<0,z,1,-1> == (v2i64 zero_extend_vector_inreg(v4i32)) |
--- |
| 24419 |
// But not shuffle and not shuffle<0,z,z,-1> ! (for same types) |
--- |
24419 |
// But not shuffle and not shuffle<0,z,z,-1> ! (for same types) |
--- |
| 24420 |
auto isZeroExtend = [NumElts, &ScaledMask](unsigned Scale) { |
0 |
24420 |
auto isZeroExtend = [NumElts, &ScaledMask](unsigned Scale) { |
0 |
| 24421 |
assert(Scale >= 2 && Scale <= NumElts && NumElts % Scale == 0 && |
0 |
24421 |
assert(Scale >= 2 && Scale <= NumElts && NumElts % Scale == 0 && |
0 |
| 24422 |
"Unexpected mask scaling factor."); |
--- |
24422 |
"Unexpected mask scaling factor."); |
--- |
| 24423 |
ArrayRef Mask = ScaledMask; |
0 |
24423 |
ArrayRef Mask = ScaledMask; |
0 |
| 24424 |
for (unsigned SrcElt = 0, NumSrcElts = NumElts / Scale; |
0 |
24424 |
for (unsigned SrcElt = 0, NumSrcElts = NumElts / Scale; |
0 |
| 24425 |
SrcElt != NumSrcElts; ++SrcElt) { |
0 |
24425 |
SrcElt != NumSrcElts; ++SrcElt) { |
0 |
| 24426 |
// Analyze the shuffle mask in Scale-sized chunks. |
--- |
24426 |
// Analyze the shuffle mask in Scale-sized chunks. |
--- |
| 24427 |
ArrayRef MaskChunk = Mask.take_front(Scale); |
0 |
24427 |
ArrayRef MaskChunk = Mask.take_front(Scale); |
0 |
| 24428 |
assert(MaskChunk.size() == Scale && "Unexpected mask size."); |
0 |
24428 |
assert(MaskChunk.size() == Scale && "Unexpected mask size."); |
0 |
| 24429 |
Mask = Mask.drop_front(MaskChunk.size()); |
0 |
24429 |
Mask = Mask.drop_front(MaskChunk.size()); |
0 |
| 24430 |
// The first indice in this chunk must be SrcElt, but not zero! |
--- |
24430 |
// The first indice in this chunk must be SrcElt, but not zero! |
--- |
| 24431 |
// FIXME: undef should be fine, but that results in more-defined result. |
--- |
24431 |
// FIXME: undef should be fine, but that results in more-defined result. |
--- |
| 24432 |
if (int FirstIndice = MaskChunk[0]; (unsigned)FirstIndice != SrcElt) |
0 |
24432 |
if (int FirstIndice = MaskChunk[0]; (unsigned)FirstIndice != SrcElt) |
0 |
| 24433 |
return false; |
0 |
24433 |
return false; |
0 |
| 24434 |
// The rest of the indices in this chunk must be zeros. |
--- |
24434 |
// The rest of the indices in this chunk must be zeros. |
--- |
| 24435 |
// FIXME: undef should be fine, but that results in more-defined result. |
--- |
24435 |
// FIXME: undef should be fine, but that results in more-defined result. |
--- |
| 24436 |
if (!all_of(MaskChunk.drop_front(1), |
0 |
24436 |
if (!all_of(MaskChunk.drop_front(1), |
0 |
| 24437 |
[](int Indice) { return Indice == -2; })) |
0 |
24437 |
[](int Indice) { return Indice == -2; })) |
0 |
| 24438 |
return false; |
0 |
24438 |
return false; |
0 |
| 24439 |
} |
--- |
24439 |
} |
--- |
| 24440 |
assert(Mask.empty() && "Did not process the whole mask?"); |
0 |
24440 |
assert(Mask.empty() && "Did not process the whole mask?"); |
0 |
| 24441 |
return true; |
0 |
24441 |
return true; |
0 |
| 24442 |
}; |
0 |
24442 |
}; |
0 |
| 24443 |
|
--- |
24443 |
|
--- |
| 24444 |
unsigned Opcode = ISD::ZERO_EXTEND_VECTOR_INREG; |
0 |
24444 |
unsigned Opcode = ISD::ZERO_EXTEND_VECTOR_INREG; |
0 |
| 24445 |
for (bool Commuted : {false, true}) { |
0 |
24445 |
for (bool Commuted : {false, true}) { |
0 |
| 24446 |
SDValue Op = SVN->getOperand(!Commuted ? 0 : 1); |
0 |
24446 |
SDValue Op = SVN->getOperand(!Commuted ? 0 : 1); |
0 |
| 24447 |
if (Commuted) |
0 |
24447 |
if (Commuted) |
0 |
| 24448 |
ShuffleVectorSDNode::commuteMask(ScaledMask); |
0 |
24448 |
ShuffleVectorSDNode::commuteMask(ScaledMask); |
0 |
| 24449 |
std::optional OutVT = canCombineShuffleToExtendVectorInreg( |
0 |
24449 |
std::optional OutVT = canCombineShuffleToExtendVectorInreg( |
0 |
| 24450 |
Opcode, PrescaledVT, isZeroExtend, DAG, TLI, LegalTypes, |
--- |
24450 |
Opcode, PrescaledVT, isZeroExtend, DAG, TLI, LegalTypes, |
--- |
| 24451 |
LegalOperations); |
--- |
24451 |
LegalOperations); |
--- |
| 24452 |
if (OutVT) |
0 |
24452 |
if (OutVT) |
0 |
| 24453 |
return DAG.getBitcast(VT, DAG.getNode(Opcode, SDLoc(SVN), *OutVT, |
0 |
24453 |
return DAG.getBitcast(VT, DAG.getNode(Opcode, SDLoc(SVN), *OutVT, |
0 |
| 24454 |
DAG.getBitcast(PrescaledVT, Op))); |
0 |
24454 |
DAG.getBitcast(PrescaledVT, Op))); |
0 |
| 24455 |
} |
--- |
24455 |
} |
--- |
| 24456 |
return SDValue(); |
0 |
24456 |
return SDValue(); |
0 |
| 24457 |
} |
0 |
24457 |
} |
0 |
| 24458 |
|
--- |
24458 |
|
--- |
| 24459 |
// Detect 'truncate_vector_inreg' style shuffles that pack the lower parts of |
--- |
24459 |
// Detect 'truncate_vector_inreg' style shuffles that pack the lower parts of |
--- |
| 24460 |
// each source element of a large type into the lowest elements of a smaller |
--- |
24460 |
// each source element of a large type into the lowest elements of a smaller |
--- |
| 24461 |
// destination type. This is often generated during legalization. |
--- |
24461 |
// destination type. This is often generated during legalization. |
--- |
| 24462 |
// If the source node itself was a '*_extend_vector_inreg' node then we should |
--- |
24462 |
// If the source node itself was a '*_extend_vector_inreg' node then we should |
--- |
| 24463 |
// then be able to remove it. |
--- |
24463 |
// then be able to remove it. |
--- |
| 24464 |
static SDValue combineTruncationShuffle(ShuffleVectorSDNode *SVN, |
0 |
24464 |
static SDValue combineTruncationShuffle(ShuffleVectorSDNode *SVN, |
0 |
| 24465 |
SelectionDAG &DAG) { |
--- |
24465 |
SelectionDAG &DAG) { |
--- |
| 24466 |
EVT VT = SVN->getValueType(0); |
0 |
24466 |
EVT VT = SVN->getValueType(0); |
0 |
| 24467 |
bool IsBigEndian = DAG.getDataLayout().isBigEndian(); |
0 |
24467 |
bool IsBigEndian = DAG.getDataLayout().isBigEndian(); |
0 |
| 24468 |
|
--- |
24468 |
|
--- |
| 24469 |
// TODO Add support for big-endian when we have a test case. |
--- |
24469 |
// TODO Add support for big-endian when we have a test case. |
--- |
| 24470 |
if (!VT.isInteger() || IsBigEndian) |
0 |
24470 |
if (!VT.isInteger() || IsBigEndian) |
0 |
| 24471 |
return SDValue(); |
0 |
24471 |
return SDValue(); |
0 |
| 24472 |
|
--- |
24472 |
|
--- |
| 24473 |
SDValue N0 = peekThroughBitcasts(SVN->getOperand(0)); |
0 |
24473 |
SDValue N0 = peekThroughBitcasts(SVN->getOperand(0)); |
0 |
| 24474 |
|
--- |
24474 |
|
--- |
| 24475 |
unsigned Opcode = N0.getOpcode(); |
0 |
24475 |
unsigned Opcode = N0.getOpcode(); |
0 |
| 24476 |
if (!ISD::isExtVecInRegOpcode(Opcode)) |
0 |
24476 |
if (!ISD::isExtVecInRegOpcode(Opcode)) |
0 |
| 24477 |
return SDValue(); |
0 |
24477 |
return SDValue(); |
0 |
| 24478 |
|
--- |
24478 |
|
--- |
| 24479 |
SDValue N00 = N0.getOperand(0); |
0 |
24479 |
SDValue N00 = N0.getOperand(0); |
0 |
| 24480 |
ArrayRef Mask = SVN->getMask(); |
0 |
24480 |
ArrayRef Mask = SVN->getMask(); |
0 |
| 24481 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
24481 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
| 24482 |
unsigned EltSizeInBits = VT.getScalarSizeInBits(); |
0 |
24482 |
unsigned EltSizeInBits = VT.getScalarSizeInBits(); |
0 |
| 24483 |
unsigned ExtSrcSizeInBits = N00.getScalarValueSizeInBits(); |
0 |
24483 |
unsigned ExtSrcSizeInBits = N00.getScalarValueSizeInBits(); |
0 |
| 24484 |
unsigned ExtDstSizeInBits = N0.getScalarValueSizeInBits(); |
0 |
24484 |
unsigned ExtDstSizeInBits = N0.getScalarValueSizeInBits(); |
0 |
| 24485 |
|
--- |
24485 |
|
--- |
| 24486 |
if (ExtDstSizeInBits % ExtSrcSizeInBits != 0) |
0 |
24486 |
if (ExtDstSizeInBits % ExtSrcSizeInBits != 0) |
0 |
| 24487 |
return SDValue(); |
0 |
24487 |
return SDValue(); |
0 |
| 24488 |
unsigned ExtScale = ExtDstSizeInBits / ExtSrcSizeInBits; |
0 |
24488 |
unsigned ExtScale = ExtDstSizeInBits / ExtSrcSizeInBits; |
0 |
| 24489 |
|
--- |
24489 |
|
--- |
| 24490 |
// (v4i32 truncate_vector_inreg(v2i64)) == shuffle<0,2-1,-1> |
--- |
24490 |
// (v4i32 truncate_vector_inreg(v2i64)) == shuffle<0,2-1,-1> |
--- |
| 24491 |
// (v8i16 truncate_vector_inreg(v4i32)) == shuffle<0,2,4,6,-1,-1,-1,-1> |
--- |
24491 |
// (v8i16 truncate_vector_inreg(v4i32)) == shuffle<0,2,4,6,-1,-1,-1,-1> |
--- |
| 24492 |
// (v8i16 truncate_vector_inreg(v2i64)) == shuffle<0,4,-1,-1,-1,-1,-1,-1> |
--- |
24492 |
// (v8i16 truncate_vector_inreg(v2i64)) == shuffle<0,4,-1,-1,-1,-1,-1,-1> |
--- |
| 24493 |
auto isTruncate = [&Mask, &NumElts](unsigned Scale) { |
0 |
24493 |
auto isTruncate = [&Mask, &NumElts](unsigned Scale) { |
0 |
| 24494 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
24494 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
| 24495 |
if (Mask[i] < 0) |
0 |
24495 |
if (Mask[i] < 0) |
0 |
| 24496 |
continue; |
0 |
24496 |
continue; |
0 |
| 24497 |
if ((i * Scale) < NumElts && Mask[i] == (int)(i * Scale)) |
0 |
24497 |
if ((i * Scale) < NumElts && Mask[i] == (int)(i * Scale)) |
0 |
| 24498 |
continue; |
0 |
24498 |
continue; |
0 |
| 24499 |
return false; |
0 |
24499 |
return false; |
0 |
| 24500 |
} |
--- |
24500 |
} |
--- |
| 24501 |
return true; |
0 |
24501 |
return true; |
0 |
| 24502 |
}; |
0 |
24502 |
}; |
0 |
| 24503 |
|
--- |
24503 |
|
--- |
| 24504 |
// At the moment we just handle the case where we've truncated back to the |
--- |
24504 |
// At the moment we just handle the case where we've truncated back to the |
--- |
| 24505 |
// same size as before the extension. |
--- |
24505 |
// same size as before the extension. |
--- |
| 24506 |
// TODO: handle more extension/truncation cases as cases arise. |
--- |
24506 |
// TODO: handle more extension/truncation cases as cases arise. |
--- |
| 24507 |
if (EltSizeInBits != ExtSrcSizeInBits) |
0 |
24507 |
if (EltSizeInBits != ExtSrcSizeInBits) |
0 |
| 24508 |
return SDValue(); |
0 |
24508 |
return SDValue(); |
0 |
| 24509 |
|
--- |
24509 |
|
--- |
| 24510 |
// We can remove *extend_vector_inreg only if the truncation happens at |
--- |
24510 |
// We can remove *extend_vector_inreg only if the truncation happens at |
--- |
| 24511 |
// the same scale as the extension. |
--- |
24511 |
// the same scale as the extension. |
--- |
| 24512 |
if (isTruncate(ExtScale)) |
0 |
24512 |
if (isTruncate(ExtScale)) |
0 |
| 24513 |
return DAG.getBitcast(VT, N00); |
0 |
24513 |
return DAG.getBitcast(VT, N00); |
0 |
| 24514 |
|
--- |
24514 |
|
--- |
| 24515 |
return SDValue(); |
0 |
24515 |
return SDValue(); |
0 |
| 24516 |
} |
--- |
24516 |
} |
--- |
| 24517 |
|
--- |
24517 |
|
--- |
| 24518 |
// Combine shuffles of splat-shuffles of the form: |
--- |
24518 |
// Combine shuffles of splat-shuffles of the form: |
--- |
| 24519 |
// shuffle (shuffle V, undef, splat-mask), undef, M |
--- |
24519 |
// shuffle (shuffle V, undef, splat-mask), undef, M |
--- |
| 24520 |
// If splat-mask contains undef elements, we need to be careful about |
--- |
24520 |
// If splat-mask contains undef elements, we need to be careful about |
--- |
| 24521 |
// introducing undef's in the folded mask which are not the result of composing |
--- |
24521 |
// introducing undef's in the folded mask which are not the result of composing |
--- |
| 24522 |
// the masks of the shuffles. |
--- |
24522 |
// the masks of the shuffles. |
--- |
| 24523 |
static SDValue combineShuffleOfSplatVal(ShuffleVectorSDNode *Shuf, |
0 |
24523 |
static SDValue combineShuffleOfSplatVal(ShuffleVectorSDNode *Shuf, |
0 |
| 24524 |
SelectionDAG &DAG) { |
--- |
24524 |
SelectionDAG &DAG) { |
--- |
| 24525 |
EVT VT = Shuf->getValueType(0); |
0 |
24525 |
EVT VT = Shuf->getValueType(0); |
0 |
| 24526 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
24526 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
| 24527 |
|
--- |
24527 |
|
--- |
| 24528 |
if (!Shuf->getOperand(1).isUndef()) |
0 |
24528 |
if (!Shuf->getOperand(1).isUndef()) |
0 |
| 24529 |
return SDValue(); |
0 |
24529 |
return SDValue(); |
0 |
| 24530 |
|
--- |
24530 |
|
--- |
| 24531 |
// See if this unary non-splat shuffle actually *is* a splat shuffle, |
--- |
24531 |
// See if this unary non-splat shuffle actually *is* a splat shuffle, |
--- |
| 24532 |
// in disguise, with all demanded elements being identical. |
--- |
24532 |
// in disguise, with all demanded elements being identical. |
--- |
| 24533 |
// FIXME: this can be done per-operand. |
--- |
24533 |
// FIXME: this can be done per-operand. |
--- |
| 24534 |
if (!Shuf->isSplat()) { |
0 |
24534 |
if (!Shuf->isSplat()) { |
0 |
| 24535 |
APInt DemandedElts(NumElts, 0); |
0 |
24535 |
APInt DemandedElts(NumElts, 0); |
0 |
| 24536 |
for (int Idx : Shuf->getMask()) { |
0 |
24536 |
for (int Idx : Shuf->getMask()) { |
0 |
| 24537 |
if (Idx < 0) |
0 |
24537 |
if (Idx < 0) |
0 |
| 24538 |
continue; // Ignore sentinel indices. |
0 |
24538 |
continue; // Ignore sentinel indices. |
0 |
| 24539 |
assert((unsigned)Idx < NumElts && "Out-of-bounds shuffle indice?"); |
0 |
24539 |
assert((unsigned)Idx < NumElts && "Out-of-bounds shuffle indice?"); |
0 |
| 24540 |
DemandedElts.setBit(Idx); |
0 |
24540 |
DemandedElts.setBit(Idx); |
0 |
| 24541 |
} |
--- |
24541 |
} |
--- |
| 24542 |
assert(DemandedElts.popcount() > 1 && "Is a splat shuffle already?"); |
0 |
24542 |
assert(DemandedElts.popcount() > 1 && "Is a splat shuffle already?"); |
0 |
| 24543 |
APInt UndefElts; |
0 |
24543 |
APInt UndefElts; |
0 |
| 24544 |
if (DAG.isSplatValue(Shuf->getOperand(0), DemandedElts, UndefElts)) { |
0 |
24544 |
if (DAG.isSplatValue(Shuf->getOperand(0), DemandedElts, UndefElts)) { |
0 |
| 24545 |
// Even if all demanded elements are splat, some of them could be undef. |
--- |
24545 |
// Even if all demanded elements are splat, some of them could be undef. |
--- |
| 24546 |
// Which lowest demanded element is *not* known-undef? |
--- |
24546 |
// Which lowest demanded element is *not* known-undef? |
--- |
| 24547 |
std::optional MinNonUndefIdx; |
0 |
24547 |
std::optional MinNonUndefIdx; |
0 |
| 24548 |
for (int Idx : Shuf->getMask()) { |
0 |
24548 |
for (int Idx : Shuf->getMask()) { |
0 |
| 24549 |
if (Idx < 0 || UndefElts[Idx]) |
0 |
24549 |
if (Idx < 0 || UndefElts[Idx]) |
0 |
| 24550 |
continue; // Ignore sentinel indices, and undef elements. |
0 |
24550 |
continue; // Ignore sentinel indices, and undef elements. |
0 |
| 24551 |
MinNonUndefIdx = std::min(Idx, MinNonUndefIdx.value_or(~0U)); |
0 |
24551 |
MinNonUndefIdx = std::min(Idx, MinNonUndefIdx.value_or(~0U)); |
0 |
| 24552 |
} |
--- |
24552 |
} |
--- |
| 24553 |
if (!MinNonUndefIdx) |
0 |
24553 |
if (!MinNonUndefIdx) |
0 |
| 24554 |
return DAG.getUNDEF(VT); // All undef - result is undef. |
0 |
24554 |
return DAG.getUNDEF(VT); // All undef - result is undef. |
0 |
| 24555 |
assert(*MinNonUndefIdx < NumElts && "Expected valid element index."); |
0 |
24555 |
assert(*MinNonUndefIdx < NumElts && "Expected valid element index."); |
0 |
| 24556 |
SmallVector SplatMask(Shuf->getMask().begin(), |
0 |
24556 |
SmallVector SplatMask(Shuf->getMask().begin(), |
0 |
| 24557 |
Shuf->getMask().end()); |
0 |
24557 |
Shuf->getMask().end()); |
0 |
| 24558 |
for (int &Idx : SplatMask) { |
0 |
24558 |
for (int &Idx : SplatMask) { |
0 |
| 24559 |
if (Idx < 0) |
0 |
24559 |
if (Idx < 0) |
0 |
| 24560 |
continue; // Passthrough sentinel indices. |
0 |
24560 |
continue; // Passthrough sentinel indices. |
0 |
| 24561 |
// Otherwise, just pick the lowest demanded non-undef element. |
--- |
24561 |
// Otherwise, just pick the lowest demanded non-undef element. |
--- |
| 24562 |
// Or sentinel undef, if we know we'd pick a known-undef element. |
--- |
24562 |
// Or sentinel undef, if we know we'd pick a known-undef element. |
--- |
| 24563 |
Idx = UndefElts[Idx] ? -1 : *MinNonUndefIdx; |
0 |
24563 |
Idx = UndefElts[Idx] ? -1 : *MinNonUndefIdx; |
0 |
| 24564 |
} |
--- |
24564 |
} |
--- |
| 24565 |
assert(SplatMask != Shuf->getMask() && "Expected mask to change!"); |
0 |
24565 |
assert(SplatMask != Shuf->getMask() && "Expected mask to change!"); |
0 |
| 24566 |
return DAG.getVectorShuffle(VT, SDLoc(Shuf), Shuf->getOperand(0), |
0 |
24566 |
return DAG.getVectorShuffle(VT, SDLoc(Shuf), Shuf->getOperand(0), |
0 |
| 24567 |
Shuf->getOperand(1), SplatMask); |
0 |
24567 |
Shuf->getOperand(1), SplatMask); |
0 |
| 24568 |
} |
0 |
24568 |
} |
0 |
| 24569 |
} |
0 |
24569 |
} |
0 |
| 24570 |
|
--- |
24570 |
|
--- |
| 24571 |
// If the inner operand is a known splat with no undefs, just return that directly. |
--- |
24571 |
// If the inner operand is a known splat with no undefs, just return that directly. |
--- |
| 24572 |
// TODO: Create DemandedElts mask from Shuf's mask. |
--- |
24572 |
// TODO: Create DemandedElts mask from Shuf's mask. |
--- |
| 24573 |
// TODO: Allow undef elements and merge with the shuffle code below. |
--- |
24573 |
// TODO: Allow undef elements and merge with the shuffle code below. |
--- |
| 24574 |
if (DAG.isSplatValue(Shuf->getOperand(0), /*AllowUndefs*/ false)) |
0 |
24574 |
if (DAG.isSplatValue(Shuf->getOperand(0), /*AllowUndefs*/ false)) |
0 |
| 24575 |
return Shuf->getOperand(0); |
0 |
24575 |
return Shuf->getOperand(0); |
0 |
| 24576 |
|
--- |
24576 |
|
--- |
| 24577 |
auto *Splat = dyn_cast(Shuf->getOperand(0)); |
0 |
24577 |
auto *Splat = dyn_cast(Shuf->getOperand(0)); |
0 |
| 24578 |
if (!Splat || !Splat->isSplat()) |
0 |
24578 |
if (!Splat || !Splat->isSplat()) |
0 |
| 24579 |
return SDValue(); |
0 |
24579 |
return SDValue(); |
0 |
| 24580 |
|
--- |
24580 |
|
--- |
| 24581 |
ArrayRef ShufMask = Shuf->getMask(); |
0 |
24581 |
ArrayRef ShufMask = Shuf->getMask(); |
0 |
| 24582 |
ArrayRef SplatMask = Splat->getMask(); |
0 |
24582 |
ArrayRef SplatMask = Splat->getMask(); |
0 |
| 24583 |
assert(ShufMask.size() == SplatMask.size() && "Mask length mismatch"); |
0 |
24583 |
assert(ShufMask.size() == SplatMask.size() && "Mask length mismatch"); |
0 |
| 24584 |
|
--- |
24584 |
|
--- |
| 24585 |
// Prefer simplifying to the splat-shuffle, if possible. This is legal if |
--- |
24585 |
// Prefer simplifying to the splat-shuffle, if possible. This is legal if |
--- |
| 24586 |
// every undef mask element in the splat-shuffle has a corresponding undef |
--- |
24586 |
// every undef mask element in the splat-shuffle has a corresponding undef |
--- |
| 24587 |
// element in the user-shuffle's mask or if the composition of mask elements |
--- |
24587 |
// element in the user-shuffle's mask or if the composition of mask elements |
--- |
| 24588 |
// would result in undef. |
--- |
24588 |
// would result in undef. |
--- |
| 24589 |
// Examples for (shuffle (shuffle v, undef, SplatMask), undef, UserMask): |
--- |
24589 |
// Examples for (shuffle (shuffle v, undef, SplatMask), undef, UserMask): |
--- |
| 24590 |
// * UserMask=[0,2,u,u], SplatMask=[2,u,2,u] -> [2,2,u,u] |
--- |
24590 |
// * UserMask=[0,2,u,u], SplatMask=[2,u,2,u] -> [2,2,u,u] |
--- |
| 24591 |
// In this case it is not legal to simplify to the splat-shuffle because we |
--- |
24591 |
// In this case it is not legal to simplify to the splat-shuffle because we |
--- |
| 24592 |
// may be exposing the users of the shuffle an undef element at index 1 |
--- |
24592 |
// may be exposing the users of the shuffle an undef element at index 1 |
--- |
| 24593 |
// which was not there before the combine. |
--- |
24593 |
// which was not there before the combine. |
--- |
| 24594 |
// * UserMask=[0,u,2,u], SplatMask=[2,u,2,u] -> [2,u,2,u] |
--- |
24594 |
// * UserMask=[0,u,2,u], SplatMask=[2,u,2,u] -> [2,u,2,u] |
--- |
| 24595 |
// In this case the composition of masks yields SplatMask, so it's ok to |
--- |
24595 |
// In this case the composition of masks yields SplatMask, so it's ok to |
--- |
| 24596 |
// simplify to the splat-shuffle. |
--- |
24596 |
// simplify to the splat-shuffle. |
--- |
| 24597 |
// * UserMask=[3,u,2,u], SplatMask=[2,u,2,u] -> [u,u,2,u] |
--- |
24597 |
// * UserMask=[3,u,2,u], SplatMask=[2,u,2,u] -> [u,u,2,u] |
--- |
| 24598 |
// In this case the composed mask includes all undef elements of SplatMask |
--- |
24598 |
// In this case the composed mask includes all undef elements of SplatMask |
--- |
| 24599 |
// and in addition sets element zero to undef. It is safe to simplify to |
--- |
24599 |
// and in addition sets element zero to undef. It is safe to simplify to |
--- |
| 24600 |
// the splat-shuffle. |
--- |
24600 |
// the splat-shuffle. |
--- |
| 24601 |
auto CanSimplifyToExistingSplat = [](ArrayRef UserMask, |
0 |
24601 |
auto CanSimplifyToExistingSplat = [](ArrayRef UserMask, |
0 |
| 24602 |
ArrayRef SplatMask) { |
--- |
24602 |
ArrayRef SplatMask) { |
--- |
| 24603 |
for (unsigned i = 0, e = UserMask.size(); i != e; ++i) |
0 |
24603 |
for (unsigned i = 0, e = UserMask.size(); i != e; ++i) |
0 |
| 24604 |
if (UserMask[i] != -1 && SplatMask[i] == -1 && |
0 |
24604 |
if (UserMask[i] != -1 && SplatMask[i] == -1 && |
0 |
| 24605 |
SplatMask[UserMask[i]] != -1) |
0 |
24605 |
SplatMask[UserMask[i]] != -1) |
0 |
| 24606 |
return false; |
0 |
24606 |
return false; |
0 |
| 24607 |
return true; |
0 |
24607 |
return true; |
0 |
| 24608 |
}; |
--- |
24608 |
}; |
--- |
| 24609 |
if (CanSimplifyToExistingSplat(ShufMask, SplatMask)) |
0 |
24609 |
if (CanSimplifyToExistingSplat(ShufMask, SplatMask)) |
0 |
| 24610 |
return Shuf->getOperand(0); |
0 |
24610 |
return Shuf->getOperand(0); |
0 |
| 24611 |
|
--- |
24611 |
|
--- |
| 24612 |
// Create a new shuffle with a mask that is composed of the two shuffles' |
--- |
24612 |
// Create a new shuffle with a mask that is composed of the two shuffles' |
--- |
| 24613 |
// masks. |
--- |
24613 |
// masks. |
--- |
| 24614 |
SmallVector NewMask; |
0 |
24614 |
SmallVector NewMask; |
0 |
| 24615 |
for (int Idx : ShufMask) |
0 |
24615 |
for (int Idx : ShufMask) |
0 |
| 24616 |
NewMask.push_back(Idx == -1 ? -1 : SplatMask[Idx]); |
0 |
24616 |
NewMask.push_back(Idx == -1 ? -1 : SplatMask[Idx]); |
0 |
| 24617 |
|
--- |
24617 |
|
--- |
| 24618 |
return DAG.getVectorShuffle(Splat->getValueType(0), SDLoc(Splat), |
0 |
24618 |
return DAG.getVectorShuffle(Splat->getValueType(0), SDLoc(Splat), |
0 |
| 24619 |
Splat->getOperand(0), Splat->getOperand(1), |
0 |
24619 |
Splat->getOperand(0), Splat->getOperand(1), |
0 |
| 24620 |
NewMask); |
0 |
24620 |
NewMask); |
0 |
| 24621 |
} |
0 |
24621 |
} |
0 |
| 24622 |
|
--- |
24622 |
|
--- |
| 24623 |
// Combine shuffles of bitcasts into a shuffle of the bitcast type, providing |
--- |
24623 |
// Combine shuffles of bitcasts into a shuffle of the bitcast type, providing |
--- |
| 24624 |
// the mask can be treated as a larger type. |
--- |
24624 |
// the mask can be treated as a larger type. |
--- |
| 24625 |
static SDValue combineShuffleOfBitcast(ShuffleVectorSDNode *SVN, |
0 |
24625 |
static SDValue combineShuffleOfBitcast(ShuffleVectorSDNode *SVN, |
0 |
| 24626 |
SelectionDAG &DAG, |
--- |
24626 |
SelectionDAG &DAG, |
--- |
| 24627 |
const TargetLowering &TLI, |
--- |
24627 |
const TargetLowering &TLI, |
--- |
| 24628 |
bool LegalOperations) { |
--- |
24628 |
bool LegalOperations) { |
--- |
| 24629 |
SDValue Op0 = SVN->getOperand(0); |
0 |
24629 |
SDValue Op0 = SVN->getOperand(0); |
0 |
| 24630 |
SDValue Op1 = SVN->getOperand(1); |
0 |
24630 |
SDValue Op1 = SVN->getOperand(1); |
0 |
| 24631 |
EVT VT = SVN->getValueType(0); |
0 |
24631 |
EVT VT = SVN->getValueType(0); |
0 |
| 24632 |
if (Op0.getOpcode() != ISD::BITCAST) |
0 |
24632 |
if (Op0.getOpcode() != ISD::BITCAST) |
0 |
| 24633 |
return SDValue(); |
0 |
24633 |
return SDValue(); |
0 |
| 24634 |
EVT InVT = Op0.getOperand(0).getValueType(); |
0 |
24634 |
EVT InVT = Op0.getOperand(0).getValueType(); |
0 |
| 24635 |
if (!InVT.isVector() || |
0 |
24635 |
if (!InVT.isVector() || |
0 |
| 24636 |
(!Op1.isUndef() && (Op1.getOpcode() != ISD::BITCAST || |
0 |
24636 |
(!Op1.isUndef() && (Op1.getOpcode() != ISD::BITCAST || |
0 |
| 24637 |
Op1.getOperand(0).getValueType() != InVT))) |
0 |
24637 |
Op1.getOperand(0).getValueType() != InVT))) |
0 |
| 24638 |
return SDValue(); |
0 |
24638 |
return SDValue(); |
0 |
| 24639 |
if (isAnyConstantBuildVector(Op0.getOperand(0)) && |
0 |
24639 |
if (isAnyConstantBuildVector(Op0.getOperand(0)) && |
0 |
| 24640 |
(Op1.isUndef() || isAnyConstantBuildVector(Op1.getOperand(0)))) |
0 |
24640 |
(Op1.isUndef() || isAnyConstantBuildVector(Op1.getOperand(0)))) |
0 |
| 24641 |
return SDValue(); |
0 |
24641 |
return SDValue(); |
0 |
| 24642 |
|
--- |
24642 |
|
--- |
| 24643 |
int VTLanes = VT.getVectorNumElements(); |
0 |
24643 |
int VTLanes = VT.getVectorNumElements(); |
0 |
| 24644 |
int InLanes = InVT.getVectorNumElements(); |
0 |
24644 |
int InLanes = InVT.getVectorNumElements(); |
0 |
| 24645 |
if (VTLanes <= InLanes || VTLanes % InLanes != 0 || |
0 |
24645 |
if (VTLanes <= InLanes || VTLanes % InLanes != 0 || |
0 |
| 24646 |
(LegalOperations && |
0 |
24646 |
(LegalOperations && |
0 |
| 24647 |
!TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, InVT))) |
0 |
24647 |
!TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, InVT))) |
0 |
| 24648 |
return SDValue(); |
0 |
24648 |
return SDValue(); |
0 |
| 24649 |
int Factor = VTLanes / InLanes; |
0 |
24649 |
int Factor = VTLanes / InLanes; |
0 |
| 24650 |
|
--- |
24650 |
|
--- |
| 24651 |
// Check that each group of lanes in the mask are either undef or make a valid |
--- |
24651 |
// Check that each group of lanes in the mask are either undef or make a valid |
--- |
| 24652 |
// mask for the wider lane type. |
--- |
24652 |
// mask for the wider lane type. |
--- |
| 24653 |
ArrayRef Mask = SVN->getMask(); |
0 |
24653 |
ArrayRef Mask = SVN->getMask(); |
0 |
| 24654 |
SmallVector NewMask; |
0 |
24654 |
SmallVector NewMask; |
0 |
| 24655 |
if (!widenShuffleMaskElts(Factor, Mask, NewMask)) |
0 |
24655 |
if (!widenShuffleMaskElts(Factor, Mask, NewMask)) |
0 |
| 24656 |
return SDValue(); |
0 |
24656 |
return SDValue(); |
0 |
| 24657 |
|
--- |
24657 |
|
--- |
| 24658 |
if (!TLI.isShuffleMaskLegal(NewMask, InVT)) |
0 |
24658 |
if (!TLI.isShuffleMaskLegal(NewMask, InVT)) |
0 |
| 24659 |
return SDValue(); |
0 |
24659 |
return SDValue(); |
0 |
| 24660 |
|
--- |
24660 |
|
--- |
| 24661 |
// Create the new shuffle with the new mask and bitcast it back to the |
--- |
24661 |
// Create the new shuffle with the new mask and bitcast it back to the |
--- |
| 24662 |
// original type. |
--- |
24662 |
// original type. |
--- |
| 24663 |
SDLoc DL(SVN); |
0 |
24663 |
SDLoc DL(SVN); |
0 |
| 24664 |
Op0 = Op0.getOperand(0); |
0 |
24664 |
Op0 = Op0.getOperand(0); |
0 |
| 24665 |
Op1 = Op1.isUndef() ? DAG.getUNDEF(InVT) : Op1.getOperand(0); |
0 |
24665 |
Op1 = Op1.isUndef() ? DAG.getUNDEF(InVT) : Op1.getOperand(0); |
0 |
| 24666 |
SDValue NewShuf = DAG.getVectorShuffle(InVT, DL, Op0, Op1, NewMask); |
0 |
24666 |
SDValue NewShuf = DAG.getVectorShuffle(InVT, DL, Op0, Op1, NewMask); |
0 |
| 24667 |
return DAG.getBitcast(VT, NewShuf); |
0 |
24667 |
return DAG.getBitcast(VT, NewShuf); |
0 |
| 24668 |
} |
0 |
24668 |
} |
0 |
| 24669 |
|
--- |
24669 |
|
--- |
| 24670 |
/// Combine shuffle of shuffle of the form: |
--- |
24670 |
/// Combine shuffle of shuffle of the form: |
--- |
| 24671 |
/// shuf (shuf X, undef, InnerMask), undef, OuterMask --> splat X |
--- |
24671 |
/// shuf (shuf X, undef, InnerMask), undef, OuterMask --> splat X |
--- |
| 24672 |
static SDValue formSplatFromShuffles(ShuffleVectorSDNode *OuterShuf, |
0 |
24672 |
static SDValue formSplatFromShuffles(ShuffleVectorSDNode *OuterShuf, |
0 |
| 24673 |
SelectionDAG &DAG) { |
--- |
24673 |
SelectionDAG &DAG) { |
--- |
| 24674 |
if (!OuterShuf->getOperand(1).isUndef()) |
0 |
24674 |
if (!OuterShuf->getOperand(1).isUndef()) |
0 |
| 24675 |
return SDValue(); |
0 |
24675 |
return SDValue(); |
0 |
| 24676 |
auto *InnerShuf = dyn_cast(OuterShuf->getOperand(0)); |
0 |
24676 |
auto *InnerShuf = dyn_cast(OuterShuf->getOperand(0)); |
0 |
| 24677 |
if (!InnerShuf || !InnerShuf->getOperand(1).isUndef()) |
0 |
24677 |
if (!InnerShuf || !InnerShuf->getOperand(1).isUndef()) |
0 |
| 24678 |
return SDValue(); |
0 |
24678 |
return SDValue(); |
0 |
| 24679 |
|
--- |
24679 |
|
--- |
| 24680 |
ArrayRef OuterMask = OuterShuf->getMask(); |
0 |
24680 |
ArrayRef OuterMask = OuterShuf->getMask(); |
0 |
| 24681 |
ArrayRef InnerMask = InnerShuf->getMask(); |
0 |
24681 |
ArrayRef InnerMask = InnerShuf->getMask(); |
0 |
| 24682 |
unsigned NumElts = OuterMask.size(); |
0 |
24682 |
unsigned NumElts = OuterMask.size(); |
0 |
| 24683 |
assert(NumElts == InnerMask.size() && "Mask length mismatch"); |
0 |
24683 |
assert(NumElts == InnerMask.size() && "Mask length mismatch"); |
0 |
| 24684 |
SmallVector CombinedMask(NumElts, -1); |
0 |
24684 |
SmallVector CombinedMask(NumElts, -1); |
0 |
| 24685 |
int SplatIndex = -1; |
0 |
24685 |
int SplatIndex = -1; |
0 |
| 24686 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
24686 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
| 24687 |
// Undef lanes remain undef. |
--- |
24687 |
// Undef lanes remain undef. |
--- |
| 24688 |
int OuterMaskElt = OuterMask[i]; |
0 |
24688 |
int OuterMaskElt = OuterMask[i]; |
0 |
| 24689 |
if (OuterMaskElt == -1) |
0 |
24689 |
if (OuterMaskElt == -1) |
0 |
| 24690 |
continue; |
0 |
24690 |
continue; |
0 |
| 24691 |
|
--- |
24691 |
|
--- |
| 24692 |
// Peek through the shuffle masks to get the underlying source element. |
--- |
24692 |
// Peek through the shuffle masks to get the underlying source element. |
--- |
| 24693 |
int InnerMaskElt = InnerMask[OuterMaskElt]; |
0 |
24693 |
int InnerMaskElt = InnerMask[OuterMaskElt]; |
0 |
| 24694 |
if (InnerMaskElt == -1) |
0 |
24694 |
if (InnerMaskElt == -1) |
0 |
| 24695 |
continue; |
0 |
24695 |
continue; |
0 |
| 24696 |
|
--- |
24696 |
|
--- |
| 24697 |
// Initialize the splatted element. |
--- |
24697 |
// Initialize the splatted element. |
--- |
| 24698 |
if (SplatIndex == -1) |
0 |
24698 |
if (SplatIndex == -1) |
0 |
| 24699 |
SplatIndex = InnerMaskElt; |
0 |
24699 |
SplatIndex = InnerMaskElt; |
0 |
| 24700 |
|
--- |
24700 |
|
--- |
| 24701 |
// Non-matching index - this is not a splat. |
--- |
24701 |
// Non-matching index - this is not a splat. |
--- |
| 24702 |
if (SplatIndex != InnerMaskElt) |
0 |
24702 |
if (SplatIndex != InnerMaskElt) |
0 |
| 24703 |
return SDValue(); |
0 |
24703 |
return SDValue(); |
0 |
| 24704 |
|
--- |
24704 |
|
--- |
| 24705 |
CombinedMask[i] = InnerMaskElt; |
0 |
24705 |
CombinedMask[i] = InnerMaskElt; |
0 |
| 24706 |
} |
--- |
24706 |
} |
--- |
| 24707 |
assert((all_of(CombinedMask, [](int M) { return M == -1; }) || |
0 |
24707 |
assert((all_of(CombinedMask, [](int M) { return M == -1; }) || |
0 |
| 24708 |
getSplatIndex(CombinedMask) != -1) && |
--- |
24708 |
getSplatIndex(CombinedMask) != -1) && |
--- |
| 24709 |
"Expected a splat mask"); |
--- |
24709 |
"Expected a splat mask"); |
--- |
| 24710 |
|
--- |
24710 |
|
--- |
| 24711 |
// TODO: The transform may be a win even if the mask is not legal. |
--- |
24711 |
// TODO: The transform may be a win even if the mask is not legal. |
--- |
| 24712 |
EVT VT = OuterShuf->getValueType(0); |
0 |
24712 |
EVT VT = OuterShuf->getValueType(0); |
0 |
| 24713 |
assert(VT == InnerShuf->getValueType(0) && "Expected matching shuffle types"); |
0 |
24713 |
assert(VT == InnerShuf->getValueType(0) && "Expected matching shuffle types"); |
0 |
| 24714 |
if (!DAG.getTargetLoweringInfo().isShuffleMaskLegal(CombinedMask, VT)) |
0 |
24714 |
if (!DAG.getTargetLoweringInfo().isShuffleMaskLegal(CombinedMask, VT)) |
0 |
| 24715 |
return SDValue(); |
0 |
24715 |
return SDValue(); |
0 |
| 24716 |
|
--- |
24716 |
|
--- |
| 24717 |
return DAG.getVectorShuffle(VT, SDLoc(OuterShuf), InnerShuf->getOperand(0), |
0 |
24717 |
return DAG.getVectorShuffle(VT, SDLoc(OuterShuf), InnerShuf->getOperand(0), |
0 |
| 24718 |
InnerShuf->getOperand(1), CombinedMask); |
0 |
24718 |
InnerShuf->getOperand(1), CombinedMask); |
0 |
| 24719 |
} |
0 |
24719 |
} |
0 |
| 24720 |
|
--- |
24720 |
|
--- |
| 24721 |
/// If the shuffle mask is taking exactly one element from the first vector |
--- |
24721 |
/// If the shuffle mask is taking exactly one element from the first vector |
--- |
| 24722 |
/// operand and passing through all other elements from the second vector |
--- |
24722 |
/// operand and passing through all other elements from the second vector |
--- |
| 24723 |
/// operand, return the index of the mask element that is choosing an element |
--- |
24723 |
/// operand, return the index of the mask element that is choosing an element |
--- |
| 24724 |
/// from the first operand. Otherwise, return -1. |
--- |
24724 |
/// from the first operand. Otherwise, return -1. |
--- |
| 24725 |
static int getShuffleMaskIndexOfOneElementFromOp0IntoOp1(ArrayRef Mask) { |
0 |
24725 |
static int getShuffleMaskIndexOfOneElementFromOp0IntoOp1(ArrayRef Mask) { |
0 |
| 24726 |
int MaskSize = Mask.size(); |
0 |
24726 |
int MaskSize = Mask.size(); |
0 |
| 24727 |
int EltFromOp0 = -1; |
0 |
24727 |
int EltFromOp0 = -1; |
0 |
| 24728 |
// TODO: This does not match if there are undef elements in the shuffle mask. |
--- |
24728 |
// TODO: This does not match if there are undef elements in the shuffle mask. |
--- |
| 24729 |
// Should we ignore undefs in the shuffle mask instead? The trade-off is |
--- |
24729 |
// Should we ignore undefs in the shuffle mask instead? The trade-off is |
--- |
| 24730 |
// removing an instruction (a shuffle), but losing the knowledge that some |
--- |
24730 |
// removing an instruction (a shuffle), but losing the knowledge that some |
--- |
| 24731 |
// vector lanes are not needed. |
--- |
24731 |
// vector lanes are not needed. |
--- |
| 24732 |
for (int i = 0; i != MaskSize; ++i) { |
0 |
24732 |
for (int i = 0; i != MaskSize; ++i) { |
0 |
| 24733 |
if (Mask[i] >= 0 && Mask[i] < MaskSize) { |
0 |
24733 |
if (Mask[i] >= 0 && Mask[i] < MaskSize) { |
0 |
| 24734 |
// We're looking for a shuffle of exactly one element from operand 0. |
--- |
24734 |
// We're looking for a shuffle of exactly one element from operand 0. |
--- |
| 24735 |
if (EltFromOp0 != -1) |
0 |
24735 |
if (EltFromOp0 != -1) |
0 |
| 24736 |
return -1; |
0 |
24736 |
return -1; |
0 |
| 24737 |
EltFromOp0 = i; |
0 |
24737 |
EltFromOp0 = i; |
0 |
| 24738 |
} else if (Mask[i] != i + MaskSize) { |
0 |
24738 |
} else if (Mask[i] != i + MaskSize) { |
0 |
| 24739 |
// Nothing from operand 1 can change lanes. |
--- |
24739 |
// Nothing from operand 1 can change lanes. |
--- |
| 24740 |
return -1; |
0 |
24740 |
return -1; |
0 |
| 24741 |
} |
--- |
24741 |
} |
--- |
| 24742 |
} |
--- |
24742 |
} |
--- |
| 24743 |
return EltFromOp0; |
0 |
24743 |
return EltFromOp0; |
0 |
| 24744 |
} |
--- |
24744 |
} |
--- |
| 24745 |
|
--- |
24745 |
|
--- |
| 24746 |
/// If a shuffle inserts exactly one element from a source vector operand into |
--- |
24746 |
/// If a shuffle inserts exactly one element from a source vector operand into |
--- |
| 24747 |
/// another vector operand and we can access the specified element as a scalar, |
--- |
24747 |
/// another vector operand and we can access the specified element as a scalar, |
--- |
| 24748 |
/// then we can eliminate the shuffle. |
--- |
24748 |
/// then we can eliminate the shuffle. |
--- |
| 24749 |
static SDValue replaceShuffleOfInsert(ShuffleVectorSDNode *Shuf, |
0 |
24749 |
static SDValue replaceShuffleOfInsert(ShuffleVectorSDNode *Shuf, |
0 |
| 24750 |
SelectionDAG &DAG) { |
--- |
24750 |
SelectionDAG &DAG) { |
--- |
| 24751 |
// First, check if we are taking one element of a vector and shuffling that |
--- |
24751 |
// First, check if we are taking one element of a vector and shuffling that |
--- |
| 24752 |
// element into another vector. |
--- |
24752 |
// element into another vector. |
--- |
| 24753 |
ArrayRef Mask = Shuf->getMask(); |
0 |
24753 |
ArrayRef Mask = Shuf->getMask(); |
0 |
| 24754 |
SmallVector CommutedMask(Mask); |
0 |
24754 |
SmallVector CommutedMask(Mask); |
0 |
| 24755 |
SDValue Op0 = Shuf->getOperand(0); |
0 |
24755 |
SDValue Op0 = Shuf->getOperand(0); |
0 |
| 24756 |
SDValue Op1 = Shuf->getOperand(1); |
0 |
24756 |
SDValue Op1 = Shuf->getOperand(1); |
0 |
| 24757 |
int ShufOp0Index = getShuffleMaskIndexOfOneElementFromOp0IntoOp1(Mask); |
0 |
24757 |
int ShufOp0Index = getShuffleMaskIndexOfOneElementFromOp0IntoOp1(Mask); |
0 |
| 24758 |
if (ShufOp0Index == -1) { |
0 |
24758 |
if (ShufOp0Index == -1) { |
0 |
| 24759 |
// Commute mask and check again. |
--- |
24759 |
// Commute mask and check again. |
--- |
| 24760 |
ShuffleVectorSDNode::commuteMask(CommutedMask); |
0 |
24760 |
ShuffleVectorSDNode::commuteMask(CommutedMask); |
0 |
| 24761 |
ShufOp0Index = getShuffleMaskIndexOfOneElementFromOp0IntoOp1(CommutedMask); |
0 |
24761 |
ShufOp0Index = getShuffleMaskIndexOfOneElementFromOp0IntoOp1(CommutedMask); |
0 |
| 24762 |
if (ShufOp0Index == -1) |
0 |
24762 |
if (ShufOp0Index == -1) |
0 |
| 24763 |
return SDValue(); |
0 |
24763 |
return SDValue(); |
0 |
| 24764 |
// Commute operands to match the commuted shuffle mask. |
--- |
24764 |
// Commute operands to match the commuted shuffle mask. |
--- |
| 24765 |
std::swap(Op0, Op1); |
0 |
24765 |
std::swap(Op0, Op1); |
0 |
| 24766 |
Mask = CommutedMask; |
0 |
24766 |
Mask = CommutedMask; |
0 |
| 24767 |
} |
--- |
24767 |
} |
--- |
| 24768 |
|
--- |
24768 |
|
--- |
| 24769 |
// The shuffle inserts exactly one element from operand 0 into operand 1. |
--- |
24769 |
// The shuffle inserts exactly one element from operand 0 into operand 1. |
--- |
| 24770 |
// Now see if we can access that element as a scalar via a real insert element |
--- |
24770 |
// Now see if we can access that element as a scalar via a real insert element |
--- |
| 24771 |
// instruction. |
--- |
24771 |
// instruction. |
--- |
| 24772 |
// TODO: We can try harder to locate the element as a scalar. Examples: it |
--- |
24772 |
// TODO: We can try harder to locate the element as a scalar. Examples: it |
--- |
| 24773 |
// could be an operand of SCALAR_TO_VECTOR, BUILD_VECTOR, or a constant. |
--- |
24773 |
// could be an operand of SCALAR_TO_VECTOR, BUILD_VECTOR, or a constant. |
--- |
| 24774 |
assert(Mask[ShufOp0Index] >= 0 && Mask[ShufOp0Index] < (int)Mask.size() && |
0 |
24774 |
assert(Mask[ShufOp0Index] >= 0 && Mask[ShufOp0Index] < (int)Mask.size() && |
0 |
| 24775 |
"Shuffle mask value must be from operand 0"); |
--- |
24775 |
"Shuffle mask value must be from operand 0"); |
--- |
| 24776 |
if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT) |
0 |
24776 |
if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT) |
0 |
| 24777 |
return SDValue(); |
0 |
24777 |
return SDValue(); |
0 |
| 24778 |
|
--- |
24778 |
|
--- |
| 24779 |
auto *InsIndexC = dyn_cast(Op0.getOperand(2)); |
0 |
24779 |
auto *InsIndexC = dyn_cast(Op0.getOperand(2)); |
0 |
| 24780 |
if (!InsIndexC || InsIndexC->getSExtValue() != Mask[ShufOp0Index]) |
0 |
24780 |
if (!InsIndexC || InsIndexC->getSExtValue() != Mask[ShufOp0Index]) |
0 |
| 24781 |
return SDValue(); |
0 |
24781 |
return SDValue(); |
0 |
| 24782 |
|
--- |
24782 |
|
--- |
| 24783 |
// There's an existing insertelement with constant insertion index, so we |
--- |
24783 |
// There's an existing insertelement with constant insertion index, so we |
--- |
| 24784 |
// don't need to check the legality/profitability of a replacement operation |
--- |
24784 |
// don't need to check the legality/profitability of a replacement operation |
--- |
| 24785 |
// that differs at most in the constant value. The target should be able to |
--- |
24785 |
// that differs at most in the constant value. The target should be able to |
--- |
| 24786 |
// lower any of those in a similar way. If not, legalization will expand this |
--- |
24786 |
// lower any of those in a similar way. If not, legalization will expand this |
--- |
| 24787 |
// to a scalar-to-vector plus shuffle. |
--- |
24787 |
// to a scalar-to-vector plus shuffle. |
--- |
| 24788 |
// |
--- |
24788 |
// |
--- |
| 24789 |
// Note that the shuffle may move the scalar from the position that the insert |
--- |
24789 |
// Note that the shuffle may move the scalar from the position that the insert |
--- |
| 24790 |
// element used. Therefore, our new insert element occurs at the shuffle's |
--- |
24790 |
// element used. Therefore, our new insert element occurs at the shuffle's |
--- |
| 24791 |
// mask index value, not the insert's index value. |
--- |
24791 |
// mask index value, not the insert's index value. |
--- |
| 24792 |
// shuffle (insertelt v1, x, C), v2, mask --> insertelt v2, x, C' |
--- |
24792 |
// shuffle (insertelt v1, x, C), v2, mask --> insertelt v2, x, C' |
--- |
| 24793 |
SDValue NewInsIndex = DAG.getVectorIdxConstant(ShufOp0Index, SDLoc(Shuf)); |
0 |
24793 |
SDValue NewInsIndex = DAG.getVectorIdxConstant(ShufOp0Index, SDLoc(Shuf)); |
0 |
| 24794 |
return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Shuf), Op0.getValueType(), |
0 |
24794 |
return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Shuf), Op0.getValueType(), |
0 |
| 24795 |
Op1, Op0.getOperand(1), NewInsIndex); |
0 |
24795 |
Op1, Op0.getOperand(1), NewInsIndex); |
0 |
| 24796 |
} |
0 |
24796 |
} |
0 |
| 24797 |
|
--- |
24797 |
|
--- |
| 24798 |
/// If we have a unary shuffle of a shuffle, see if it can be folded away |
--- |
24798 |
/// If we have a unary shuffle of a shuffle, see if it can be folded away |
--- |
| 24799 |
/// completely. This has the potential to lose undef knowledge because the first |
--- |
24799 |
/// completely. This has the potential to lose undef knowledge because the first |
--- |
| 24800 |
/// shuffle may not have an undef mask element where the second one does. So |
--- |
24800 |
/// shuffle may not have an undef mask element where the second one does. So |
--- |
| 24801 |
/// only call this after doing simplifications based on demanded elements. |
--- |
24801 |
/// only call this after doing simplifications based on demanded elements. |
--- |
| 24802 |
static SDValue simplifyShuffleOfShuffle(ShuffleVectorSDNode *Shuf) { |
0 |
24802 |
static SDValue simplifyShuffleOfShuffle(ShuffleVectorSDNode *Shuf) { |
0 |
| 24803 |
// shuf (shuf0 X, Y, Mask0), undef, Mask |
--- |
24803 |
// shuf (shuf0 X, Y, Mask0), undef, Mask |
--- |
| 24804 |
auto *Shuf0 = dyn_cast(Shuf->getOperand(0)); |
0 |
24804 |
auto *Shuf0 = dyn_cast(Shuf->getOperand(0)); |
0 |
| 24805 |
if (!Shuf0 || !Shuf->getOperand(1).isUndef()) |
0 |
24805 |
if (!Shuf0 || !Shuf->getOperand(1).isUndef()) |
0 |
| 24806 |
return SDValue(); |
0 |
24806 |
return SDValue(); |
0 |
| 24807 |
|
--- |
24807 |
|
--- |
| 24808 |
ArrayRef Mask = Shuf->getMask(); |
0 |
24808 |
ArrayRef Mask = Shuf->getMask(); |
0 |
| 24809 |
ArrayRef Mask0 = Shuf0->getMask(); |
0 |
24809 |
ArrayRef Mask0 = Shuf0->getMask(); |
0 |
| 24810 |
for (int i = 0, e = (int)Mask.size(); i != e; ++i) { |
0 |
24810 |
for (int i = 0, e = (int)Mask.size(); i != e; ++i) { |
0 |
| 24811 |
// Ignore undef elements. |
--- |
24811 |
// Ignore undef elements. |
--- |
| 24812 |
if (Mask[i] == -1) |
0 |
24812 |
if (Mask[i] == -1) |
0 |
| 24813 |
continue; |
0 |
24813 |
continue; |
0 |
| 24814 |
assert(Mask[i] >= 0 && Mask[i] < e && "Unexpected shuffle mask value"); |
0 |
24814 |
assert(Mask[i] >= 0 && Mask[i] < e && "Unexpected shuffle mask value"); |
0 |
| 24815 |
|
--- |
24815 |
|
--- |
| 24816 |
// Is the element of the shuffle operand chosen by this shuffle the same as |
--- |
24816 |
// Is the element of the shuffle operand chosen by this shuffle the same as |
--- |
| 24817 |
// the element chosen by the shuffle operand itself? |
--- |
24817 |
// the element chosen by the shuffle operand itself? |
--- |
| 24818 |
if (Mask0[Mask[i]] != Mask0[i]) |
0 |
24818 |
if (Mask0[Mask[i]] != Mask0[i]) |
0 |
| 24819 |
return SDValue(); |
0 |
24819 |
return SDValue(); |
0 |
| 24820 |
} |
--- |
24820 |
} |
--- |
| 24821 |
// Every element of this shuffle is identical to the result of the previous |
--- |
24821 |
// Every element of this shuffle is identical to the result of the previous |
--- |
| 24822 |
// shuffle, so we can replace this value. |
--- |
24822 |
// shuffle, so we can replace this value. |
--- |
| 24823 |
return Shuf->getOperand(0); |
0 |
24823 |
return Shuf->getOperand(0); |
0 |
| 24824 |
} |
--- |
24824 |
} |
--- |
| 24825 |
|
--- |
24825 |
|
--- |
| 24826 |
SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { |
0 |
24826 |
SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { |
0 |
| 24827 |
EVT VT = N->getValueType(0); |
0 |
24827 |
EVT VT = N->getValueType(0); |
0 |
| 24828 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
24828 |
unsigned NumElts = VT.getVectorNumElements(); |
0 |
| 24829 |
|
--- |
24829 |
|
--- |
| 24830 |
SDValue N0 = N->getOperand(0); |
0 |
24830 |
SDValue N0 = N->getOperand(0); |
0 |
| 24831 |
SDValue N1 = N->getOperand(1); |
0 |
24831 |
SDValue N1 = N->getOperand(1); |
0 |
| 24832 |
|
--- |
24832 |
|
--- |
| 24833 |
assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); |
0 |
24833 |
assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); |
0 |
| 24834 |
|
--- |
24834 |
|
--- |
| 24835 |
// Canonicalize shuffle undef, undef -> undef |
--- |
24835 |
// Canonicalize shuffle undef, undef -> undef |
--- |
| 24836 |
if (N0.isUndef() && N1.isUndef()) |
0 |
24836 |
if (N0.isUndef() && N1.isUndef()) |
0 |
| 24837 |
return DAG.getUNDEF(VT); |
0 |
24837 |
return DAG.getUNDEF(VT); |
0 |
| 24838 |
|
--- |
24838 |
|
--- |
| 24839 |
ShuffleVectorSDNode *SVN = cast(N); |
0 |
24839 |
ShuffleVectorSDNode *SVN = cast(N); |
0 |
| 24840 |
|
--- |
24840 |
|
--- |
| 24841 |
// Canonicalize shuffle v, v -> v, undef |
--- |
24841 |
// Canonicalize shuffle v, v -> v, undef |
--- |
| 24842 |
if (N0 == N1) |
0 |
24842 |
if (N0 == N1) |
0 |
| 24843 |
return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT), |
0 |
24843 |
return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT), |
0 |
| 24844 |
createUnaryMask(SVN->getMask(), NumElts)); |
0 |
24844 |
createUnaryMask(SVN->getMask(), NumElts)); |
0 |
| 24845 |
|
--- |
24845 |
|
--- |
| 24846 |
// Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. |
--- |
24846 |
// Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. |
--- |
| 24847 |
if (N0.isUndef()) |
0 |
24847 |
if (N0.isUndef()) |
0 |
| 24848 |
return DAG.getCommutedVectorShuffle(*SVN); |
0 |
24848 |
return DAG.getCommutedVectorShuffle(*SVN); |
0 |
| 24849 |
|
--- |
24849 |
|
--- |
| 24850 |
// Remove references to rhs if it is undef |
--- |
24850 |
// Remove references to rhs if it is undef |
--- |
| 24851 |
if (N1.isUndef()) { |
0 |
24851 |
if (N1.isUndef()) { |
0 |
| 24852 |
bool Changed = false; |
0 |
24852 |
bool Changed = false; |
0 |
| 24853 |
SmallVector NewMask; |
0 |
24853 |
SmallVector NewMask; |
0 |
| 24854 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
24854 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
| 24855 |
int Idx = SVN->getMaskElt(i); |
0 |
24855 |
int Idx = SVN->getMaskElt(i); |
0 |
| 24856 |
if (Idx >= (int)NumElts) { |
0 |
24856 |
if (Idx >= (int)NumElts) { |
0 |
| 24857 |
Idx = -1; |
0 |
24857 |
Idx = -1; |
0 |
| 24858 |
Changed = true; |
0 |
24858 |
Changed = true; |
0 |
| 24859 |
} |
--- |
24859 |
} |
--- |
| 24860 |
NewMask.push_back(Idx); |
0 |
24860 |
NewMask.push_back(Idx); |
0 |
| 24861 |
} |
--- |
24861 |
} |
--- |
| 24862 |
if (Changed) |
0 |
24862 |
if (Changed) |
0 |
| 24863 |
return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, NewMask); |
0 |
24863 |
return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, NewMask); |
0 |
| 24864 |
} |
0 |
24864 |
} |
0 |
| 24865 |
|
--- |
24865 |
|
--- |
| 24866 |
if (SDValue InsElt = replaceShuffleOfInsert(SVN, DAG)) |
0 |
24866 |
if (SDValue InsElt = replaceShuffleOfInsert(SVN, DAG)) |
0 |
| 24867 |
return InsElt; |
0 |
24867 |
return InsElt; |
0 |
| 24868 |
|
--- |
24868 |
|
--- |
| 24869 |
// A shuffle of a single vector that is a splatted value can always be folded. |
--- |
24869 |
// A shuffle of a single vector that is a splatted value can always be folded. |
--- |
| 24870 |
if (SDValue V = combineShuffleOfSplatVal(SVN, DAG)) |
0 |
24870 |
if (SDValue V = combineShuffleOfSplatVal(SVN, DAG)) |
0 |
| 24871 |
return V; |
0 |
24871 |
return V; |
0 |
| 24872 |
|
--- |
24872 |
|
--- |
| 24873 |
if (SDValue V = formSplatFromShuffles(SVN, DAG)) |
0 |
24873 |
if (SDValue V = formSplatFromShuffles(SVN, DAG)) |
0 |
| 24874 |
return V; |
0 |
24874 |
return V; |
0 |
| 24875 |
|
--- |
24875 |
|
--- |
| 24876 |
// If it is a splat, check if the argument vector is another splat or a |
--- |
24876 |
// If it is a splat, check if the argument vector is another splat or a |
--- |
| 24877 |
// build_vector. |
--- |
24877 |
// build_vector. |
--- |
| 24878 |
if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { |
0 |
24878 |
if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { |
0 |
| 24879 |
int SplatIndex = SVN->getSplatIndex(); |
0 |
24879 |
int SplatIndex = SVN->getSplatIndex(); |
0 |
| 24880 |
if (N0.hasOneUse() && TLI.isExtractVecEltCheap(VT, SplatIndex) && |
0 |
24880 |
if (N0.hasOneUse() && TLI.isExtractVecEltCheap(VT, SplatIndex) && |
0 |
| 24881 |
TLI.isBinOp(N0.getOpcode()) && N0->getNumValues() == 1) { |
0 |
24881 |
TLI.isBinOp(N0.getOpcode()) && N0->getNumValues() == 1) { |
0 |
| 24882 |
// splat (vector_bo L, R), Index --> |
--- |
24882 |
// splat (vector_bo L, R), Index --> |
--- |
| 24883 |
// splat (scalar_bo (extelt L, Index), (extelt R, Index)) |
--- |
24883 |
// splat (scalar_bo (extelt L, Index), (extelt R, Index)) |
--- |
| 24884 |
SDValue L = N0.getOperand(0), R = N0.getOperand(1); |
0 |
24884 |
SDValue L = N0.getOperand(0), R = N0.getOperand(1); |
0 |
| 24885 |
SDLoc DL(N); |
0 |
24885 |
SDLoc DL(N); |
0 |
| 24886 |
EVT EltVT = VT.getScalarType(); |
0 |
24886 |
EVT EltVT = VT.getScalarType(); |
0 |
| 24887 |
SDValue Index = DAG.getVectorIdxConstant(SplatIndex, DL); |
0 |
24887 |
SDValue Index = DAG.getVectorIdxConstant(SplatIndex, DL); |
0 |
| 24888 |
SDValue ExtL = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, L, Index); |
0 |
24888 |
SDValue ExtL = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, L, Index); |
0 |
| 24889 |
SDValue ExtR = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, R, Index); |
0 |
24889 |
SDValue ExtR = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, R, Index); |
0 |
| 24890 |
SDValue NewBO = |
--- |
24890 |
SDValue NewBO = |
--- |
| 24891 |
DAG.getNode(N0.getOpcode(), DL, EltVT, ExtL, ExtR, N0->getFlags()); |
0 |
24891 |
DAG.getNode(N0.getOpcode(), DL, EltVT, ExtL, ExtR, N0->getFlags()); |
0 |
| 24892 |
SDValue Insert = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, NewBO); |
0 |
24892 |
SDValue Insert = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, NewBO); |
0 |
| 24893 |
SmallVector ZeroMask(VT.getVectorNumElements(), 0); |
0 |
24893 |
SmallVector ZeroMask(VT.getVectorNumElements(), 0); |
0 |
| 24894 |
return DAG.getVectorShuffle(VT, DL, Insert, DAG.getUNDEF(VT), ZeroMask); |
0 |
24894 |
return DAG.getVectorShuffle(VT, DL, Insert, DAG.getUNDEF(VT), ZeroMask); |
0 |
| 24895 |
} |
0 |
24895 |
} |
0 |
| 24896 |
|
--- |
24896 |
|
--- |
| 24897 |
// splat(scalar_to_vector(x), 0) -> build_vector(x,...,x) |
--- |
24897 |
// splat(scalar_to_vector(x), 0) -> build_vector(x,...,x) |
--- |
| 24898 |
// splat(insert_vector_elt(v, x, c), c) -> build_vector(x,...,x) |
--- |
24898 |
// splat(insert_vector_elt(v, x, c), c) -> build_vector(x,...,x) |
--- |
| 24899 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) && |
0 |
24899 |
if ((!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) && |
0 |
| 24900 |
N0.hasOneUse()) { |
0 |
24900 |
N0.hasOneUse()) { |
0 |
| 24901 |
if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && SplatIndex == 0) |
0 |
24901 |
if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && SplatIndex == 0) |
0 |
| 24902 |
return DAG.getSplatBuildVector(VT, SDLoc(N), N0.getOperand(0)); |
0 |
24902 |
return DAG.getSplatBuildVector(VT, SDLoc(N), N0.getOperand(0)); |
0 |
| 24903 |
|
--- |
24903 |
|
--- |
| 24904 |
if (N0.getOpcode() == ISD::INSERT_VECTOR_ELT) |
0 |
24904 |
if (N0.getOpcode() == ISD::INSERT_VECTOR_ELT) |
0 |
| 24905 |
if (auto *Idx = dyn_cast(N0.getOperand(2))) |
0 |
24905 |
if (auto *Idx = dyn_cast(N0.getOperand(2))) |
0 |
| 24906 |
if (Idx->getAPIntValue() == SplatIndex) |
0 |
24906 |
if (Idx->getAPIntValue() == SplatIndex) |
0 |
| 24907 |
return DAG.getSplatBuildVector(VT, SDLoc(N), N0.getOperand(1)); |
0 |
24907 |
return DAG.getSplatBuildVector(VT, SDLoc(N), N0.getOperand(1)); |
0 |
| 24908 |
|
--- |
24908 |
|
--- |
| 24909 |
// Look through a bitcast if LE and splatting lane 0, through to a |
--- |
24909 |
// Look through a bitcast if LE and splatting lane 0, through to a |
--- |
| 24910 |
// scalar_to_vector or a build_vector. |
--- |
24910 |
// scalar_to_vector or a build_vector. |
--- |
| 24911 |
if (N0.getOpcode() == ISD::BITCAST && N0.getOperand(0).hasOneUse() && |
0 |
24911 |
if (N0.getOpcode() == ISD::BITCAST && N0.getOperand(0).hasOneUse() && |
0 |
| 24912 |
SplatIndex == 0 && DAG.getDataLayout().isLittleEndian() && |
0 |
24912 |
SplatIndex == 0 && DAG.getDataLayout().isLittleEndian() && |
0 |
| 24913 |
(N0.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR || |
0 |
24913 |
(N0.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR || |
0 |
| 24914 |
N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR)) { |
0 |
24914 |
N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR)) { |
0 |
| 24915 |
EVT N00VT = N0.getOperand(0).getValueType(); |
0 |
24915 |
EVT N00VT = N0.getOperand(0).getValueType(); |
0 |
| 24916 |
if (VT.getScalarSizeInBits() <= N00VT.getScalarSizeInBits() && |
0 |
24916 |
if (VT.getScalarSizeInBits() <= N00VT.getScalarSizeInBits() && |
0 |
| 24917 |
VT.isInteger() && N00VT.isInteger()) { |
0 |
24917 |
VT.isInteger() && N00VT.isInteger()) { |
0 |
| 24918 |
EVT InVT = |
--- |
24918 |
EVT InVT = |
--- |
| 24919 |
TLI.getTypeToTransformTo(*DAG.getContext(), VT.getScalarType()); |
0 |
24919 |
TLI.getTypeToTransformTo(*DAG.getContext(), VT.getScalarType()); |
0 |
| 24920 |
SDValue Op = DAG.getZExtOrTrunc(N0.getOperand(0).getOperand(0), |
0 |
24920 |
SDValue Op = DAG.getZExtOrTrunc(N0.getOperand(0).getOperand(0), |
0 |
| 24921 |
SDLoc(N), InVT); |
0 |
24921 |
SDLoc(N), InVT); |
0 |
| 24922 |
return DAG.getSplatBuildVector(VT, SDLoc(N), Op); |
0 |
24922 |
return DAG.getSplatBuildVector(VT, SDLoc(N), Op); |
0 |
| 24923 |
} |
--- |
24923 |
} |
--- |
| 24924 |
} |
--- |
24924 |
} |
--- |
| 24925 |
} |
--- |
24925 |
} |
--- |
| 24926 |
|
--- |
24926 |
|
--- |
| 24927 |
// If this is a bit convert that changes the element type of the vector but |
--- |
24927 |
// If this is a bit convert that changes the element type of the vector but |
--- |
| 24928 |
// not the number of vector elements, look through it. Be careful not to |
--- |
24928 |
// not the number of vector elements, look through it. Be careful not to |
--- |
| 24929 |
// look though conversions that change things like v4f32 to v2f64. |
--- |
24929 |
// look though conversions that change things like v4f32 to v2f64. |
--- |
| 24930 |
SDNode *V = N0.getNode(); |
0 |
24930 |
SDNode *V = N0.getNode(); |
0 |
| 24931 |
if (V->getOpcode() == ISD::BITCAST) { |
0 |
24931 |
if (V->getOpcode() == ISD::BITCAST) { |
0 |
| 24932 |
SDValue ConvInput = V->getOperand(0); |
0 |
24932 |
SDValue ConvInput = V->getOperand(0); |
0 |
| 24933 |
if (ConvInput.getValueType().isVector() && |
0 |
24933 |
if (ConvInput.getValueType().isVector() && |
0 |
| 24934 |
ConvInput.getValueType().getVectorNumElements() == NumElts) |
0 |
24934 |
ConvInput.getValueType().getVectorNumElements() == NumElts) |
0 |
| 24935 |
V = ConvInput.getNode(); |
0 |
24935 |
V = ConvInput.getNode(); |
0 |
| 24936 |
} |
--- |
24936 |
} |
--- |
| 24937 |
|
--- |
24937 |
|
--- |
| 24938 |
if (V->getOpcode() == ISD::BUILD_VECTOR) { |
0 |
24938 |
if (V->getOpcode() == ISD::BUILD_VECTOR) { |
0 |
| 24939 |
assert(V->getNumOperands() == NumElts && |
0 |
24939 |
assert(V->getNumOperands() == NumElts && |
0 |
| 24940 |
"BUILD_VECTOR has wrong number of operands"); |
--- |
24940 |
"BUILD_VECTOR has wrong number of operands"); |
--- |
| 24941 |
SDValue Base; |
0 |
24941 |
SDValue Base; |
0 |
| 24942 |
bool AllSame = true; |
0 |
24942 |
bool AllSame = true; |
0 |
| 24943 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
24943 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
| 24944 |
if (!V->getOperand(i).isUndef()) { |
0 |
24944 |
if (!V->getOperand(i).isUndef()) { |
0 |
| 24945 |
Base = V->getOperand(i); |
0 |
24945 |
Base = V->getOperand(i); |
0 |
| 24946 |
break; |
0 |
24946 |
break; |
0 |
| 24947 |
} |
--- |
24947 |
} |
--- |
| 24948 |
} |
--- |
24948 |
} |
--- |
| 24949 |
// Splat of , return |
--- |
24949 |
// Splat of , return |
--- |
| 24950 |
if (!Base.getNode()) |
0 |
24950 |
if (!Base.getNode()) |
0 |
| 24951 |
return N0; |
0 |
24951 |
return N0; |
0 |
| 24952 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
24952 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
| 24953 |
if (V->getOperand(i) != Base) { |
0 |
24953 |
if (V->getOperand(i) != Base) { |
0 |
| 24954 |
AllSame = false; |
0 |
24954 |
AllSame = false; |
0 |
| 24955 |
break; |
0 |
24955 |
break; |
0 |
| 24956 |
} |
--- |
24956 |
} |
--- |
| 24957 |
} |
--- |
24957 |
} |
--- |
| 24958 |
// Splat of , return |
--- |
24958 |
// Splat of , return |
--- |
| 24959 |
if (AllSame) |
0 |
24959 |
if (AllSame) |
0 |
| 24960 |
return N0; |
0 |
24960 |
return N0; |
0 |
| 24961 |
|
--- |
24961 |
|
--- |
| 24962 |
// Canonicalize any other splat as a build_vector. |
--- |
24962 |
// Canonicalize any other splat as a build_vector. |
--- |
| 24963 |
SDValue Splatted = V->getOperand(SplatIndex); |
0 |
24963 |
SDValue Splatted = V->getOperand(SplatIndex); |
0 |
| 24964 |
SmallVector Ops(NumElts, Splatted); |
0 |
24964 |
SmallVector Ops(NumElts, Splatted); |
0 |
| 24965 |
SDValue NewBV = DAG.getBuildVector(V->getValueType(0), SDLoc(N), Ops); |
0 |
24965 |
SDValue NewBV = DAG.getBuildVector(V->getValueType(0), SDLoc(N), Ops); |
0 |
| 24966 |
|
--- |
24966 |
|
--- |
| 24967 |
// We may have jumped through bitcasts, so the type of the |
--- |
24967 |
// We may have jumped through bitcasts, so the type of the |
--- |
| 24968 |
// BUILD_VECTOR may not match the type of the shuffle. |
--- |
24968 |
// BUILD_VECTOR may not match the type of the shuffle. |
--- |
| 24969 |
if (V->getValueType(0) != VT) |
0 |
24969 |
if (V->getValueType(0) != VT) |
0 |
| 24970 |
NewBV = DAG.getBitcast(VT, NewBV); |
0 |
24970 |
NewBV = DAG.getBitcast(VT, NewBV); |
0 |
| 24971 |
return NewBV; |
0 |
24971 |
return NewBV; |
0 |
| 24972 |
} |
0 |
24972 |
} |
0 |
| 24973 |
} |
--- |
24973 |
} |
--- |
| 24974 |
|
--- |
24974 |
|
--- |
| 24975 |
// Simplify source operands based on shuffle mask. |
--- |
24975 |
// Simplify source operands based on shuffle mask. |
--- |
| 24976 |
if (SimplifyDemandedVectorElts(SDValue(N, 0))) |
0 |
24976 |
if (SimplifyDemandedVectorElts(SDValue(N, 0))) |
0 |
| 24977 |
return SDValue(N, 0); |
0 |
24977 |
return SDValue(N, 0); |
0 |
| 24978 |
|
--- |
24978 |
|
--- |
| 24979 |
// This is intentionally placed after demanded elements simplification because |
--- |
24979 |
// This is intentionally placed after demanded elements simplification because |
--- |
| 24980 |
// it could eliminate knowledge of undef elements created by this shuffle. |
--- |
24980 |
// it could eliminate knowledge of undef elements created by this shuffle. |
--- |
| 24981 |
if (SDValue ShufOp = simplifyShuffleOfShuffle(SVN)) |
0 |
24981 |
if (SDValue ShufOp = simplifyShuffleOfShuffle(SVN)) |
0 |
| 24982 |
return ShufOp; |
0 |
24982 |
return ShufOp; |
0 |
| 24983 |
|
--- |
24983 |
|
--- |
| 24984 |
// Match shuffles that can be converted to any_vector_extend_in_reg. |
--- |
24984 |
// Match shuffles that can be converted to any_vector_extend_in_reg. |
--- |
| 24985 |
if (SDValue V = |
0 |
24985 |
if (SDValue V = |
0 |
| 24986 |
combineShuffleToAnyExtendVectorInreg(SVN, DAG, TLI, LegalOperations)) |
0 |
24986 |
combineShuffleToAnyExtendVectorInreg(SVN, DAG, TLI, LegalOperations)) |
0 |
| 24987 |
return V; |
0 |
24987 |
return V; |
0 |
| 24988 |
|
--- |
24988 |
|
--- |
| 24989 |
// Combine "truncate_vector_in_reg" style shuffles. |
--- |
24989 |
// Combine "truncate_vector_in_reg" style shuffles. |
--- |
| 24990 |
if (SDValue V = combineTruncationShuffle(SVN, DAG)) |
0 |
24990 |
if (SDValue V = combineTruncationShuffle(SVN, DAG)) |
0 |
| 24991 |
return V; |
0 |
24991 |
return V; |
0 |
| 24992 |
|
--- |
24992 |
|
--- |
| 24993 |
if (N0.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
24993 |
if (N0.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
| 24994 |
Level < AfterLegalizeVectorOps && |
0 |
24994 |
Level < AfterLegalizeVectorOps && |
0 |
| 24995 |
(N1.isUndef() || |
0 |
24995 |
(N1.isUndef() || |
0 |
| 24996 |
(N1.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
24996 |
(N1.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
| 24997 |
N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) { |
0 |
24997 |
N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) { |
0 |
| 24998 |
if (SDValue V = partitionShuffleOfConcats(N, DAG)) |
0 |
24998 |
if (SDValue V = partitionShuffleOfConcats(N, DAG)) |
0 |
| 24999 |
return V; |
0 |
24999 |
return V; |
0 |
| 25000 |
} |
--- |
25000 |
} |
--- |
| 25001 |
|
--- |
25001 |
|
--- |
| 25002 |
// A shuffle of a concat of the same narrow vector can be reduced to use |
--- |
25002 |
// A shuffle of a concat of the same narrow vector can be reduced to use |
--- |
| 25003 |
// only low-half elements of a concat with undef: |
--- |
25003 |
// only low-half elements of a concat with undef: |
--- |
| 25004 |
// shuf (concat X, X), undef, Mask --> shuf (concat X, undef), undef, Mask' |
--- |
25004 |
// shuf (concat X, X), undef, Mask --> shuf (concat X, undef), undef, Mask' |
--- |
| 25005 |
if (N0.getOpcode() == ISD::CONCAT_VECTORS && N1.isUndef() && |
0 |
25005 |
if (N0.getOpcode() == ISD::CONCAT_VECTORS && N1.isUndef() && |
0 |
| 25006 |
N0.getNumOperands() == 2 && |
0 |
25006 |
N0.getNumOperands() == 2 && |
0 |
| 25007 |
N0.getOperand(0) == N0.getOperand(1)) { |
0 |
25007 |
N0.getOperand(0) == N0.getOperand(1)) { |
0 |
| 25008 |
int HalfNumElts = (int)NumElts / 2; |
0 |
25008 |
int HalfNumElts = (int)NumElts / 2; |
0 |
| 25009 |
SmallVector NewMask; |
0 |
25009 |
SmallVector NewMask; |
0 |
| 25010 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
25010 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
| 25011 |
int Idx = SVN->getMaskElt(i); |
0 |
25011 |
int Idx = SVN->getMaskElt(i); |
0 |
| 25012 |
if (Idx >= HalfNumElts) { |
0 |
25012 |
if (Idx >= HalfNumElts) { |
0 |
| 25013 |
assert(Idx < (int)NumElts && "Shuffle mask chooses undef op"); |
0 |
25013 |
assert(Idx < (int)NumElts && "Shuffle mask chooses undef op"); |
0 |
| 25014 |
Idx -= HalfNumElts; |
0 |
25014 |
Idx -= HalfNumElts; |
0 |
| 25015 |
} |
--- |
25015 |
} |
--- |
| 25016 |
NewMask.push_back(Idx); |
0 |
25016 |
NewMask.push_back(Idx); |
0 |
| 25017 |
} |
--- |
25017 |
} |
--- |
| 25018 |
if (TLI.isShuffleMaskLegal(NewMask, VT)) { |
0 |
25018 |
if (TLI.isShuffleMaskLegal(NewMask, VT)) { |
0 |
| 25019 |
SDValue UndefVec = DAG.getUNDEF(N0.getOperand(0).getValueType()); |
0 |
25019 |
SDValue UndefVec = DAG.getUNDEF(N0.getOperand(0).getValueType()); |
0 |
| 25020 |
SDValue NewCat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, |
0 |
25020 |
SDValue NewCat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, |
0 |
| 25021 |
N0.getOperand(0), UndefVec); |
0 |
25021 |
N0.getOperand(0), UndefVec); |
0 |
| 25022 |
return DAG.getVectorShuffle(VT, SDLoc(N), NewCat, N1, NewMask); |
0 |
25022 |
return DAG.getVectorShuffle(VT, SDLoc(N), NewCat, N1, NewMask); |
0 |
| 25023 |
} |
--- |
25023 |
} |
--- |
| 25024 |
} |
0 |
25024 |
} |
0 |
| 25025 |
|
--- |
25025 |
|
--- |
| 25026 |
// See if we can replace a shuffle with an insert_subvector. |
--- |
25026 |
// See if we can replace a shuffle with an insert_subvector. |
--- |
| 25027 |
// e.g. v2i32 into v8i32: |
--- |
25027 |
// e.g. v2i32 into v8i32: |
--- |
| 25028 |
// shuffle(lhs,concat(rhs0,rhs1,rhs2,rhs3),0,1,2,3,10,11,6,7). |
--- |
25028 |
// shuffle(lhs,concat(rhs0,rhs1,rhs2,rhs3),0,1,2,3,10,11,6,7). |
--- |
| 25029 |
// --> insert_subvector(lhs,rhs1,4). |
--- |
25029 |
// --> insert_subvector(lhs,rhs1,4). |
--- |
| 25030 |
if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT) && |
0 |
25030 |
if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT) && |
0 |
| 25031 |
TLI.isOperationLegalOrCustom(ISD::INSERT_SUBVECTOR, VT)) { |
0 |
25031 |
TLI.isOperationLegalOrCustom(ISD::INSERT_SUBVECTOR, VT)) { |
0 |
| 25032 |
auto ShuffleToInsert = [&](SDValue LHS, SDValue RHS, ArrayRef Mask) { |
0 |
25032 |
auto ShuffleToInsert = [&](SDValue LHS, SDValue RHS, ArrayRef Mask) { |
0 |
| 25033 |
// Ensure RHS subvectors are legal. |
--- |
25033 |
// Ensure RHS subvectors are legal. |
--- |
| 25034 |
assert(RHS.getOpcode() == ISD::CONCAT_VECTORS && "Can't find subvectors"); |
0 |
25034 |
assert(RHS.getOpcode() == ISD::CONCAT_VECTORS && "Can't find subvectors"); |
0 |
| 25035 |
EVT SubVT = RHS.getOperand(0).getValueType(); |
0 |
25035 |
EVT SubVT = RHS.getOperand(0).getValueType(); |
0 |
| 25036 |
int NumSubVecs = RHS.getNumOperands(); |
0 |
25036 |
int NumSubVecs = RHS.getNumOperands(); |
0 |
| 25037 |
int NumSubElts = SubVT.getVectorNumElements(); |
0 |
25037 |
int NumSubElts = SubVT.getVectorNumElements(); |
0 |
| 25038 |
assert((NumElts % NumSubElts) == 0 && "Subvector mismatch"); |
0 |
25038 |
assert((NumElts % NumSubElts) == 0 && "Subvector mismatch"); |
0 |
| 25039 |
if (!TLI.isTypeLegal(SubVT)) |
0 |
25039 |
if (!TLI.isTypeLegal(SubVT)) |
0 |
| 25040 |
return SDValue(); |
0 |
25040 |
return SDValue(); |
0 |
| 25041 |
|
--- |
25041 |
|
--- |
| 25042 |
// Don't bother if we have an unary shuffle (matches undef + LHS elts). |
--- |
25042 |
// Don't bother if we have an unary shuffle (matches undef + LHS elts). |
--- |
| 25043 |
if (all_of(Mask, [NumElts](int M) { return M < (int)NumElts; })) |
0 |
25043 |
if (all_of(Mask, [NumElts](int M) { return M < (int)NumElts; })) |
0 |
| 25044 |
return SDValue(); |
0 |
25044 |
return SDValue(); |
0 |
| 25045 |
|
--- |
25045 |
|
--- |
| 25046 |
// Search [NumSubElts] spans for RHS sequence. |
--- |
25046 |
// Search [NumSubElts] spans for RHS sequence. |
--- |
| 25047 |
// TODO: Can we avoid nested loops to increase performance? |
--- |
25047 |
// TODO: Can we avoid nested loops to increase performance? |
--- |
| 25048 |
SmallVector InsertionMask(NumElts); |
0 |
25048 |
SmallVector InsertionMask(NumElts); |
0 |
| 25049 |
for (int SubVec = 0; SubVec != NumSubVecs; ++SubVec) { |
0 |
25049 |
for (int SubVec = 0; SubVec != NumSubVecs; ++SubVec) { |
0 |
| 25050 |
for (int SubIdx = 0; SubIdx != (int)NumElts; SubIdx += NumSubElts) { |
0 |
25050 |
for (int SubIdx = 0; SubIdx != (int)NumElts; SubIdx += NumSubElts) { |
0 |
| 25051 |
// Reset mask to identity. |
--- |
25051 |
// Reset mask to identity. |
--- |
| 25052 |
std::iota(InsertionMask.begin(), InsertionMask.end(), 0); |
0 |
25052 |
std::iota(InsertionMask.begin(), InsertionMask.end(), 0); |
0 |
| 25053 |
|
--- |
25053 |
|
--- |
| 25054 |
// Add subvector insertion. |
--- |
25054 |
// Add subvector insertion. |
--- |
| 25055 |
std::iota(InsertionMask.begin() + SubIdx, |
0 |
25055 |
std::iota(InsertionMask.begin() + SubIdx, |
0 |
| 25056 |
InsertionMask.begin() + SubIdx + NumSubElts, |
0 |
25056 |
InsertionMask.begin() + SubIdx + NumSubElts, |
0 |
| 25057 |
NumElts + (SubVec * NumSubElts)); |
0 |
25057 |
NumElts + (SubVec * NumSubElts)); |
0 |
| 25058 |
|
--- |
25058 |
|
--- |
| 25059 |
// See if the shuffle mask matches the reference insertion mask. |
--- |
25059 |
// See if the shuffle mask matches the reference insertion mask. |
--- |
| 25060 |
bool MatchingShuffle = true; |
0 |
25060 |
bool MatchingShuffle = true; |
0 |
| 25061 |
for (int i = 0; i != (int)NumElts; ++i) { |
0 |
25061 |
for (int i = 0; i != (int)NumElts; ++i) { |
0 |
| 25062 |
int ExpectIdx = InsertionMask[i]; |
0 |
25062 |
int ExpectIdx = InsertionMask[i]; |
0 |
| 25063 |
int ActualIdx = Mask[i]; |
0 |
25063 |
int ActualIdx = Mask[i]; |
0 |
| 25064 |
if (0 <= ActualIdx && ExpectIdx != ActualIdx) { |
0 |
25064 |
if (0 <= ActualIdx && ExpectIdx != ActualIdx) { |
0 |
| 25065 |
MatchingShuffle = false; |
0 |
25065 |
MatchingShuffle = false; |
0 |
| 25066 |
break; |
0 |
25066 |
break; |
0 |
| 25067 |
} |
--- |
25067 |
} |
--- |
| 25068 |
} |
--- |
25068 |
} |
--- |
| 25069 |
|
--- |
25069 |
|
--- |
| 25070 |
if (MatchingShuffle) |
0 |
25070 |
if (MatchingShuffle) |
0 |
| 25071 |
return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, LHS, |
0 |
25071 |
return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, LHS, |
0 |
| 25072 |
RHS.getOperand(SubVec), |
0 |
25072 |
RHS.getOperand(SubVec), |
0 |
| 25073 |
DAG.getVectorIdxConstant(SubIdx, SDLoc(N))); |
0 |
25073 |
DAG.getVectorIdxConstant(SubIdx, SDLoc(N))); |
0 |
| 25074 |
} |
--- |
25074 |
} |
--- |
| 25075 |
} |
--- |
25075 |
} |
--- |
| 25076 |
return SDValue(); |
0 |
25076 |
return SDValue(); |
0 |
| 25077 |
}; |
0 |
25077 |
}; |
0 |
| 25078 |
ArrayRef Mask = SVN->getMask(); |
0 |
25078 |
ArrayRef Mask = SVN->getMask(); |
0 |
| 25079 |
if (N1.getOpcode() == ISD::CONCAT_VECTORS) |
0 |
25079 |
if (N1.getOpcode() == ISD::CONCAT_VECTORS) |
0 |
| 25080 |
if (SDValue InsertN1 = ShuffleToInsert(N0, N1, Mask)) |
0 |
25080 |
if (SDValue InsertN1 = ShuffleToInsert(N0, N1, Mask)) |
0 |
| 25081 |
return InsertN1; |
0 |
25081 |
return InsertN1; |
0 |
| 25082 |
if (N0.getOpcode() == ISD::CONCAT_VECTORS) { |
0 |
25082 |
if (N0.getOpcode() == ISD::CONCAT_VECTORS) { |
0 |
| 25083 |
SmallVector CommuteMask(Mask); |
0 |
25083 |
SmallVector CommuteMask(Mask); |
0 |
| 25084 |
ShuffleVectorSDNode::commuteMask(CommuteMask); |
0 |
25084 |
ShuffleVectorSDNode::commuteMask(CommuteMask); |
0 |
| 25085 |
if (SDValue InsertN0 = ShuffleToInsert(N1, N0, CommuteMask)) |
0 |
25085 |
if (SDValue InsertN0 = ShuffleToInsert(N1, N0, CommuteMask)) |
0 |
| 25086 |
return InsertN0; |
0 |
25086 |
return InsertN0; |
0 |
| 25087 |
} |
0 |
25087 |
} |
0 |
| 25088 |
} |
--- |
25088 |
} |
--- |
| 25089 |
|
--- |
25089 |
|
--- |
| 25090 |
// If we're not performing a select/blend shuffle, see if we can convert the |
--- |
25090 |
// If we're not performing a select/blend shuffle, see if we can convert the |
--- |
| 25091 |
// shuffle into a AND node, with all the out-of-lane elements are known zero. |
--- |
25091 |
// shuffle into a AND node, with all the out-of-lane elements are known zero. |
--- |
| 25092 |
if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT)) { |
0 |
25092 |
if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT)) { |
0 |
| 25093 |
bool IsInLaneMask = true; |
0 |
25093 |
bool IsInLaneMask = true; |
0 |
| 25094 |
ArrayRef Mask = SVN->getMask(); |
0 |
25094 |
ArrayRef Mask = SVN->getMask(); |
0 |
| 25095 |
SmallVector ClearMask(NumElts, -1); |
0 |
25095 |
SmallVector ClearMask(NumElts, -1); |
0 |
| 25096 |
APInt DemandedLHS = APInt::getZero(NumElts); |
0 |
25096 |
APInt DemandedLHS = APInt::getZero(NumElts); |
0 |
| 25097 |
APInt DemandedRHS = APInt::getZero(NumElts); |
0 |
25097 |
APInt DemandedRHS = APInt::getZero(NumElts); |
0 |
| 25098 |
for (int I = 0; I != (int)NumElts; ++I) { |
0 |
25098 |
for (int I = 0; I != (int)NumElts; ++I) { |
0 |
| 25099 |
int M = Mask[I]; |
0 |
25099 |
int M = Mask[I]; |
0 |
| 25100 |
if (M < 0) |
0 |
25100 |
if (M < 0) |
0 |
| 25101 |
continue; |
0 |
25101 |
continue; |
0 |
| 25102 |
ClearMask[I] = M == I ? I : (I + NumElts); |
0 |
25102 |
ClearMask[I] = M == I ? I : (I + NumElts); |
0 |
| 25103 |
IsInLaneMask &= (M == I) || (M == (int)(I + NumElts)); |
0 |
25103 |
IsInLaneMask &= (M == I) || (M == (int)(I + NumElts)); |
0 |
| 25104 |
if (M != I) { |
0 |
25104 |
if (M != I) { |
0 |
| 25105 |
APInt &Demanded = M < (int)NumElts ? DemandedLHS : DemandedRHS; |
0 |
25105 |
APInt &Demanded = M < (int)NumElts ? DemandedLHS : DemandedRHS; |
0 |
| 25106 |
Demanded.setBit(M % NumElts); |
0 |
25106 |
Demanded.setBit(M % NumElts); |
0 |
| 25107 |
} |
--- |
25107 |
} |
--- |
| 25108 |
} |
--- |
25108 |
} |
--- |
| 25109 |
// TODO: Should we try to mask with N1 as well? |
--- |
25109 |
// TODO: Should we try to mask with N1 as well? |
--- |
| 25110 |
if (!IsInLaneMask && (!DemandedLHS.isZero() || !DemandedRHS.isZero()) && |
0 |
25110 |
if (!IsInLaneMask && (!DemandedLHS.isZero() || !DemandedRHS.isZero()) && |
0 |
| 25111 |
(DemandedLHS.isZero() || DAG.MaskedVectorIsZero(N0, DemandedLHS)) && |
0 |
25111 |
(DemandedLHS.isZero() || DAG.MaskedVectorIsZero(N0, DemandedLHS)) && |
0 |
| 25112 |
(DemandedRHS.isZero() || DAG.MaskedVectorIsZero(N1, DemandedRHS))) { |
0 |
25112 |
(DemandedRHS.isZero() || DAG.MaskedVectorIsZero(N1, DemandedRHS))) { |
0 |
| 25113 |
SDLoc DL(N); |
0 |
25113 |
SDLoc DL(N); |
0 |
| 25114 |
EVT IntVT = VT.changeVectorElementTypeToInteger(); |
0 |
25114 |
EVT IntVT = VT.changeVectorElementTypeToInteger(); |
0 |
| 25115 |
EVT IntSVT = VT.getVectorElementType().changeTypeToInteger(); |
0 |
25115 |
EVT IntSVT = VT.getVectorElementType().changeTypeToInteger(); |
0 |
| 25116 |
// Transform the type to a legal type so that the buildvector constant |
--- |
25116 |
// Transform the type to a legal type so that the buildvector constant |
--- |
| 25117 |
// elements are not illegal. Make sure that the result is larger than the |
--- |
25117 |
// elements are not illegal. Make sure that the result is larger than the |
--- |
| 25118 |
// original type, incase the value is split into two (eg i64->i32). |
--- |
25118 |
// original type, incase the value is split into two (eg i64->i32). |
--- |
| 25119 |
if (!TLI.isTypeLegal(IntSVT) && LegalTypes) |
0 |
25119 |
if (!TLI.isTypeLegal(IntSVT) && LegalTypes) |
0 |
| 25120 |
IntSVT = TLI.getTypeToTransformTo(*DAG.getContext(), IntSVT); |
0 |
25120 |
IntSVT = TLI.getTypeToTransformTo(*DAG.getContext(), IntSVT); |
0 |
| 25121 |
if (IntSVT.getSizeInBits() >= IntVT.getScalarSizeInBits()) { |
0 |
25121 |
if (IntSVT.getSizeInBits() >= IntVT.getScalarSizeInBits()) { |
0 |
| 25122 |
SDValue ZeroElt = DAG.getConstant(0, DL, IntSVT); |
0 |
25122 |
SDValue ZeroElt = DAG.getConstant(0, DL, IntSVT); |
0 |
| 25123 |
SDValue AllOnesElt = DAG.getAllOnesConstant(DL, IntSVT); |
0 |
25123 |
SDValue AllOnesElt = DAG.getAllOnesConstant(DL, IntSVT); |
0 |
| 25124 |
SmallVector AndMask(NumElts, DAG.getUNDEF(IntSVT)); |
0 |
25124 |
SmallVector AndMask(NumElts, DAG.getUNDEF(IntSVT)); |
0 |
| 25125 |
for (int I = 0; I != (int)NumElts; ++I) |
0 |
25125 |
for (int I = 0; I != (int)NumElts; ++I) |
0 |
| 25126 |
if (0 <= Mask[I]) |
0 |
25126 |
if (0 <= Mask[I]) |
0 |
| 25127 |
AndMask[I] = Mask[I] == I ? AllOnesElt : ZeroElt; |
0 |
25127 |
AndMask[I] = Mask[I] == I ? AllOnesElt : ZeroElt; |
0 |
| 25128 |
|
--- |
25128 |
|
--- |
| 25129 |
// See if a clear mask is legal instead of going via |
--- |
25129 |
// See if a clear mask is legal instead of going via |
--- |
| 25130 |
// XformToShuffleWithZero which loses UNDEF mask elements. |
--- |
25130 |
// XformToShuffleWithZero which loses UNDEF mask elements. |
--- |
| 25131 |
if (TLI.isVectorClearMaskLegal(ClearMask, IntVT)) |
0 |
25131 |
if (TLI.isVectorClearMaskLegal(ClearMask, IntVT)) |
0 |
| 25132 |
return DAG.getBitcast( |
0 |
25132 |
return DAG.getBitcast( |
0 |
| 25133 |
VT, DAG.getVectorShuffle(IntVT, DL, DAG.getBitcast(IntVT, N0), |
0 |
25133 |
VT, DAG.getVectorShuffle(IntVT, DL, DAG.getBitcast(IntVT, N0), |
0 |
| 25134 |
DAG.getConstant(0, DL, IntVT), ClearMask)); |
0 |
25134 |
DAG.getConstant(0, DL, IntVT), ClearMask)); |
0 |
| 25135 |
|
--- |
25135 |
|
--- |
| 25136 |
if (TLI.isOperationLegalOrCustom(ISD::AND, IntVT)) |
0 |
25136 |
if (TLI.isOperationLegalOrCustom(ISD::AND, IntVT)) |
0 |
| 25137 |
return DAG.getBitcast( |
0 |
25137 |
return DAG.getBitcast( |
0 |
| 25138 |
VT, DAG.getNode(ISD::AND, DL, IntVT, DAG.getBitcast(IntVT, N0), |
0 |
25138 |
VT, DAG.getNode(ISD::AND, DL, IntVT, DAG.getBitcast(IntVT, N0), |
0 |
| 25139 |
DAG.getBuildVector(IntVT, DL, AndMask))); |
0 |
25139 |
DAG.getBuildVector(IntVT, DL, AndMask))); |
0 |
| 25140 |
} |
0 |
25140 |
} |
0 |
| 25141 |
} |
0 |
25141 |
} |
0 |
| 25142 |
} |
0 |
25142 |
} |
0 |
| 25143 |
|
--- |
25143 |
|
--- |
| 25144 |
// Attempt to combine a shuffle of 2 inputs of 'scalar sources' - |
--- |
25144 |
// Attempt to combine a shuffle of 2 inputs of 'scalar sources' - |
--- |
| 25145 |
// BUILD_VECTOR or SCALAR_TO_VECTOR into a single BUILD_VECTOR. |
--- |
25145 |
// BUILD_VECTOR or SCALAR_TO_VECTOR into a single BUILD_VECTOR. |
--- |
| 25146 |
if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT)) |
0 |
25146 |
if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT)) |
0 |
| 25147 |
if (SDValue Res = combineShuffleOfScalars(SVN, DAG, TLI)) |
0 |
25147 |
if (SDValue Res = combineShuffleOfScalars(SVN, DAG, TLI)) |
0 |
| 25148 |
return Res; |
0 |
25148 |
return Res; |
0 |
| 25149 |
|
--- |
25149 |
|
--- |
| 25150 |
// If this shuffle only has a single input that is a bitcasted shuffle, |
--- |
25150 |
// If this shuffle only has a single input that is a bitcasted shuffle, |
--- |
| 25151 |
// attempt to merge the 2 shuffles and suitably bitcast the inputs/output |
--- |
25151 |
// attempt to merge the 2 shuffles and suitably bitcast the inputs/output |
--- |
| 25152 |
// back to their original types. |
--- |
25152 |
// back to their original types. |
--- |
| 25153 |
if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && |
0 |
25153 |
if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && |
0 |
| 25154 |
N1.isUndef() && Level < AfterLegalizeVectorOps && |
0 |
25154 |
N1.isUndef() && Level < AfterLegalizeVectorOps && |
0 |
| 25155 |
TLI.isTypeLegal(VT)) { |
0 |
25155 |
TLI.isTypeLegal(VT)) { |
0 |
| 25156 |
|
--- |
25156 |
|
--- |
| 25157 |
SDValue BC0 = peekThroughOneUseBitcasts(N0); |
0 |
25157 |
SDValue BC0 = peekThroughOneUseBitcasts(N0); |
0 |
| 25158 |
if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) { |
0 |
25158 |
if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) { |
0 |
| 25159 |
EVT SVT = VT.getScalarType(); |
0 |
25159 |
EVT SVT = VT.getScalarType(); |
0 |
| 25160 |
EVT InnerVT = BC0->getValueType(0); |
0 |
25160 |
EVT InnerVT = BC0->getValueType(0); |
0 |
| 25161 |
EVT InnerSVT = InnerVT.getScalarType(); |
0 |
25161 |
EVT InnerSVT = InnerVT.getScalarType(); |
0 |
| 25162 |
|
--- |
25162 |
|
--- |
| 25163 |
// Determine which shuffle works with the smaller scalar type. |
--- |
25163 |
// Determine which shuffle works with the smaller scalar type. |
--- |
| 25164 |
EVT ScaleVT = SVT.bitsLT(InnerSVT) ? VT : InnerVT; |
0 |
25164 |
EVT ScaleVT = SVT.bitsLT(InnerSVT) ? VT : InnerVT; |
0 |
| 25165 |
EVT ScaleSVT = ScaleVT.getScalarType(); |
0 |
25165 |
EVT ScaleSVT = ScaleVT.getScalarType(); |
0 |
| 25166 |
|
--- |
25166 |
|
--- |
| 25167 |
if (TLI.isTypeLegal(ScaleVT) && |
0 |
25167 |
if (TLI.isTypeLegal(ScaleVT) && |
0 |
| 25168 |
0 == (InnerSVT.getSizeInBits() % ScaleSVT.getSizeInBits()) && |
0 |
25168 |
0 == (InnerSVT.getSizeInBits() % ScaleSVT.getSizeInBits()) && |
0 |
| 25169 |
0 == (SVT.getSizeInBits() % ScaleSVT.getSizeInBits())) { |
0 |
25169 |
0 == (SVT.getSizeInBits() % ScaleSVT.getSizeInBits())) { |
0 |
| 25170 |
int InnerScale = InnerSVT.getSizeInBits() / ScaleSVT.getSizeInBits(); |
0 |
25170 |
int InnerScale = InnerSVT.getSizeInBits() / ScaleSVT.getSizeInBits(); |
0 |
| 25171 |
int OuterScale = SVT.getSizeInBits() / ScaleSVT.getSizeInBits(); |
0 |
25171 |
int OuterScale = SVT.getSizeInBits() / ScaleSVT.getSizeInBits(); |
0 |
| 25172 |
|
--- |
25172 |
|
--- |
| 25173 |
// Scale the shuffle masks to the smaller scalar type. |
--- |
25173 |
// Scale the shuffle masks to the smaller scalar type. |
--- |
| 25174 |
ShuffleVectorSDNode *InnerSVN = cast(BC0); |
0 |
25174 |
ShuffleVectorSDNode *InnerSVN = cast(BC0); |
0 |
| 25175 |
SmallVector InnerMask; |
0 |
25175 |
SmallVector InnerMask; |
0 |
| 25176 |
SmallVector OuterMask; |
0 |
25176 |
SmallVector OuterMask; |
0 |
| 25177 |
narrowShuffleMaskElts(InnerScale, InnerSVN->getMask(), InnerMask); |
0 |
25177 |
narrowShuffleMaskElts(InnerScale, InnerSVN->getMask(), InnerMask); |
0 |
| 25178 |
narrowShuffleMaskElts(OuterScale, SVN->getMask(), OuterMask); |
0 |
25178 |
narrowShuffleMaskElts(OuterScale, SVN->getMask(), OuterMask); |
0 |
| 25179 |
|
--- |
25179 |
|
--- |
| 25180 |
// Merge the shuffle masks. |
--- |
25180 |
// Merge the shuffle masks. |
--- |
| 25181 |
SmallVector NewMask; |
0 |
25181 |
SmallVector NewMask; |
0 |
| 25182 |
for (int M : OuterMask) |
0 |
25182 |
for (int M : OuterMask) |
0 |
| 25183 |
NewMask.push_back(M < 0 ? -1 : InnerMask[M]); |
0 |
25183 |
NewMask.push_back(M < 0 ? -1 : InnerMask[M]); |
0 |
| 25184 |
|
--- |
25184 |
|
--- |
| 25185 |
// Test for shuffle mask legality over both commutations. |
--- |
25185 |
// Test for shuffle mask legality over both commutations. |
--- |
| 25186 |
SDValue SV0 = BC0->getOperand(0); |
0 |
25186 |
SDValue SV0 = BC0->getOperand(0); |
0 |
| 25187 |
SDValue SV1 = BC0->getOperand(1); |
0 |
25187 |
SDValue SV1 = BC0->getOperand(1); |
0 |
| 25188 |
bool LegalMask = TLI.isShuffleMaskLegal(NewMask, ScaleVT); |
0 |
25188 |
bool LegalMask = TLI.isShuffleMaskLegal(NewMask, ScaleVT); |
0 |
| 25189 |
if (!LegalMask) { |
0 |
25189 |
if (!LegalMask) { |
0 |
| 25190 |
std::swap(SV0, SV1); |
0 |
25190 |
std::swap(SV0, SV1); |
0 |
| 25191 |
ShuffleVectorSDNode::commuteMask(NewMask); |
0 |
25191 |
ShuffleVectorSDNode::commuteMask(NewMask); |
0 |
| 25192 |
LegalMask = TLI.isShuffleMaskLegal(NewMask, ScaleVT); |
0 |
25192 |
LegalMask = TLI.isShuffleMaskLegal(NewMask, ScaleVT); |
0 |
| 25193 |
} |
--- |
25193 |
} |
--- |
| 25194 |
|
--- |
25194 |
|
--- |
| 25195 |
if (LegalMask) { |
0 |
25195 |
if (LegalMask) { |
0 |
| 25196 |
SV0 = DAG.getBitcast(ScaleVT, SV0); |
0 |
25196 |
SV0 = DAG.getBitcast(ScaleVT, SV0); |
0 |
| 25197 |
SV1 = DAG.getBitcast(ScaleVT, SV1); |
0 |
25197 |
SV1 = DAG.getBitcast(ScaleVT, SV1); |
0 |
| 25198 |
return DAG.getBitcast( |
0 |
25198 |
return DAG.getBitcast( |
0 |
| 25199 |
VT, DAG.getVectorShuffle(ScaleVT, SDLoc(N), SV0, SV1, NewMask)); |
0 |
25199 |
VT, DAG.getVectorShuffle(ScaleVT, SDLoc(N), SV0, SV1, NewMask)); |
0 |
| 25200 |
} |
--- |
25200 |
} |
--- |
| 25201 |
} |
0 |
25201 |
} |
0 |
| 25202 |
} |
--- |
25202 |
} |
--- |
| 25203 |
} |
--- |
25203 |
} |
--- |
| 25204 |
|
--- |
25204 |
|
--- |
| 25205 |
// Match shuffles of bitcasts, so long as the mask can be treated as the |
--- |
25205 |
// Match shuffles of bitcasts, so long as the mask can be treated as the |
--- |
| 25206 |
// larger type. |
--- |
25206 |
// larger type. |
--- |
| 25207 |
if (SDValue V = combineShuffleOfBitcast(SVN, DAG, TLI, LegalOperations)) |
0 |
25207 |
if (SDValue V = combineShuffleOfBitcast(SVN, DAG, TLI, LegalOperations)) |
0 |
| 25208 |
return V; |
0 |
25208 |
return V; |
0 |
| 25209 |
|
--- |
25209 |
|
--- |
| 25210 |
// Compute the combined shuffle mask for a shuffle with SV0 as the first |
--- |
25210 |
// Compute the combined shuffle mask for a shuffle with SV0 as the first |
--- |
| 25211 |
// operand, and SV1 as the second operand. |
--- |
25211 |
// operand, and SV1 as the second operand. |
--- |
| 25212 |
// i.e. Merge SVN(OtherSVN, N1) -> shuffle(SV0, SV1, Mask) iff Commute = false |
--- |
25212 |
// i.e. Merge SVN(OtherSVN, N1) -> shuffle(SV0, SV1, Mask) iff Commute = false |
--- |
| 25213 |
// Merge SVN(N1, OtherSVN) -> shuffle(SV0, SV1, Mask') iff Commute = true |
--- |
25213 |
// Merge SVN(N1, OtherSVN) -> shuffle(SV0, SV1, Mask') iff Commute = true |
--- |
| 25214 |
auto MergeInnerShuffle = |
--- |
25214 |
auto MergeInnerShuffle = |
--- |
| 25215 |
[NumElts, &VT](bool Commute, ShuffleVectorSDNode *SVN, |
0 |
25215 |
[NumElts, &VT](bool Commute, ShuffleVectorSDNode *SVN, |
0 |
| 25216 |
ShuffleVectorSDNode *OtherSVN, SDValue N1, |
--- |
25216 |
ShuffleVectorSDNode *OtherSVN, SDValue N1, |
--- |
| 25217 |
const TargetLowering &TLI, SDValue &SV0, SDValue &SV1, |
--- |
25217 |
const TargetLowering &TLI, SDValue &SV0, SDValue &SV1, |
--- |
| 25218 |
SmallVectorImpl &Mask) -> bool { |
0 |
25218 |
SmallVectorImpl &Mask) -> bool { |
0 |
| 25219 |
// Don't try to fold splats; they're likely to simplify somehow, or they |
--- |
25219 |
// Don't try to fold splats; they're likely to simplify somehow, or they |
--- |
| 25220 |
// might be free. |
--- |
25220 |
// might be free. |
--- |
| 25221 |
if (OtherSVN->isSplat()) |
0 |
25221 |
if (OtherSVN->isSplat()) |
0 |
| 25222 |
return false; |
0 |
25222 |
return false; |
0 |
| 25223 |
|
--- |
25223 |
|
--- |
| 25224 |
SV0 = SV1 = SDValue(); |
0 |
25224 |
SV0 = SV1 = SDValue(); |
0 |
| 25225 |
Mask.clear(); |
0 |
25225 |
Mask.clear(); |
0 |
| 25226 |
|
--- |
25226 |
|
--- |
| 25227 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
25227 |
for (unsigned i = 0; i != NumElts; ++i) { |
0 |
| 25228 |
int Idx = SVN->getMaskElt(i); |
0 |
25228 |
int Idx = SVN->getMaskElt(i); |
0 |
| 25229 |
if (Idx < 0) { |
0 |
25229 |
if (Idx < 0) { |
0 |
| 25230 |
// Propagate Undef. |
--- |
25230 |
// Propagate Undef. |
--- |
| 25231 |
Mask.push_back(Idx); |
0 |
25231 |
Mask.push_back(Idx); |
0 |
| 25232 |
continue; |
0 |
25232 |
continue; |
0 |
| 25233 |
} |
--- |
25233 |
} |
--- |
| 25234 |
|
--- |
25234 |
|
--- |
| 25235 |
if (Commute) |
0 |
25235 |
if (Commute) |
0 |
| 25236 |
Idx = (Idx < (int)NumElts) ? (Idx + NumElts) : (Idx - NumElts); |
0 |
25236 |
Idx = (Idx < (int)NumElts) ? (Idx + NumElts) : (Idx - NumElts); |
0 |
| 25237 |
|
--- |
25237 |
|
--- |
| 25238 |
SDValue CurrentVec; |
0 |
25238 |
SDValue CurrentVec; |
0 |
| 25239 |
if (Idx < (int)NumElts) { |
0 |
25239 |
if (Idx < (int)NumElts) { |
0 |
| 25240 |
// This shuffle index refers to the inner shuffle N0. Lookup the inner |
--- |
25240 |
// This shuffle index refers to the inner shuffle N0. Lookup the inner |
--- |
| 25241 |
// shuffle mask to identify which vector is actually referenced. |
--- |
25241 |
// shuffle mask to identify which vector is actually referenced. |
--- |
| 25242 |
Idx = OtherSVN->getMaskElt(Idx); |
0 |
25242 |
Idx = OtherSVN->getMaskElt(Idx); |
0 |
| 25243 |
if (Idx < 0) { |
0 |
25243 |
if (Idx < 0) { |
0 |
| 25244 |
// Propagate Undef. |
--- |
25244 |
// Propagate Undef. |
--- |
| 25245 |
Mask.push_back(Idx); |
0 |
25245 |
Mask.push_back(Idx); |
0 |
| 25246 |
continue; |
0 |
25246 |
continue; |
0 |
| 25247 |
} |
--- |
25247 |
} |
--- |
| 25248 |
CurrentVec = (Idx < (int)NumElts) ? OtherSVN->getOperand(0) |
0 |
25248 |
CurrentVec = (Idx < (int)NumElts) ? OtherSVN->getOperand(0) |
0 |
| 25249 |
: OtherSVN->getOperand(1); |
0 |
25249 |
: OtherSVN->getOperand(1); |
0 |
| 25250 |
} else { |
--- |
25250 |
} else { |
--- |
| 25251 |
// This shuffle index references an element within N1. |
--- |
25251 |
// This shuffle index references an element within N1. |
--- |
| 25252 |
CurrentVec = N1; |
0 |
25252 |
CurrentVec = N1; |
0 |
| 25253 |
} |
--- |
25253 |
} |
--- |
| 25254 |
|
--- |
25254 |
|
--- |
| 25255 |
// Simple case where 'CurrentVec' is UNDEF. |
--- |
25255 |
// Simple case where 'CurrentVec' is UNDEF. |
--- |
| 25256 |
if (CurrentVec.isUndef()) { |
0 |
25256 |
if (CurrentVec.isUndef()) { |
0 |
| 25257 |
Mask.push_back(-1); |
0 |
25257 |
Mask.push_back(-1); |
0 |
| 25258 |
continue; |
0 |
25258 |
continue; |
0 |
| 25259 |
} |
--- |
25259 |
} |
--- |
| 25260 |
|
--- |
25260 |
|
--- |
| 25261 |
// Canonicalize the shuffle index. We don't know yet if CurrentVec |
--- |
25261 |
// Canonicalize the shuffle index. We don't know yet if CurrentVec |
--- |
| 25262 |
// will be the first or second operand of the combined shuffle. |
--- |
25262 |
// will be the first or second operand of the combined shuffle. |
--- |
| 25263 |
Idx = Idx % NumElts; |
0 |
25263 |
Idx = Idx % NumElts; |
0 |
| 25264 |
if (!SV0.getNode() || SV0 == CurrentVec) { |
0 |
25264 |
if (!SV0.getNode() || SV0 == CurrentVec) { |
0 |
| 25265 |
// Ok. CurrentVec is the left hand side. |
--- |
25265 |
// Ok. CurrentVec is the left hand side. |
--- |
| 25266 |
// Update the mask accordingly. |
--- |
25266 |
// Update the mask accordingly. |
--- |
| 25267 |
SV0 = CurrentVec; |
0 |
25267 |
SV0 = CurrentVec; |
0 |
| 25268 |
Mask.push_back(Idx); |
0 |
25268 |
Mask.push_back(Idx); |
0 |
| 25269 |
continue; |
0 |
25269 |
continue; |
0 |
| 25270 |
} |
--- |
25270 |
} |
--- |
| 25271 |
if (!SV1.getNode() || SV1 == CurrentVec) { |
0 |
25271 |
if (!SV1.getNode() || SV1 == CurrentVec) { |
0 |
| 25272 |
// Ok. CurrentVec is the right hand side. |
--- |
25272 |
// Ok. CurrentVec is the right hand side. |
--- |
| 25273 |
// Update the mask accordingly. |
--- |
25273 |
// Update the mask accordingly. |
--- |
| 25274 |
SV1 = CurrentVec; |
0 |
25274 |
SV1 = CurrentVec; |
0 |
| 25275 |
Mask.push_back(Idx + NumElts); |
0 |
25275 |
Mask.push_back(Idx + NumElts); |
0 |
| 25276 |
continue; |
0 |
25276 |
continue; |
0 |
| 25277 |
} |
--- |
25277 |
} |
--- |
| 25278 |
|
--- |
25278 |
|
--- |
| 25279 |
// Last chance - see if the vector is another shuffle and if it |
--- |
25279 |
// Last chance - see if the vector is another shuffle and if it |
--- |
| 25280 |
// uses one of the existing candidate shuffle ops. |
--- |
25280 |
// uses one of the existing candidate shuffle ops. |
--- |
| 25281 |
if (auto *CurrentSVN = dyn_cast(CurrentVec)) { |
0 |
25281 |
if (auto *CurrentSVN = dyn_cast(CurrentVec)) { |
0 |
| 25282 |
int InnerIdx = CurrentSVN->getMaskElt(Idx); |
0 |
25282 |
int InnerIdx = CurrentSVN->getMaskElt(Idx); |
0 |
| 25283 |
if (InnerIdx < 0) { |
0 |
25283 |
if (InnerIdx < 0) { |
0 |
| 25284 |
Mask.push_back(-1); |
0 |
25284 |
Mask.push_back(-1); |
0 |
| 25285 |
continue; |
0 |
25285 |
continue; |
0 |
| 25286 |
} |
--- |
25286 |
} |
--- |
| 25287 |
SDValue InnerVec = (InnerIdx < (int)NumElts) |
0 |
25287 |
SDValue InnerVec = (InnerIdx < (int)NumElts) |
0 |
| 25288 |
? CurrentSVN->getOperand(0) |
0 |
25288 |
? CurrentSVN->getOperand(0) |
0 |
| 25289 |
: CurrentSVN->getOperand(1); |
0 |
25289 |
: CurrentSVN->getOperand(1); |
0 |
| 25290 |
if (InnerVec.isUndef()) { |
0 |
25290 |
if (InnerVec.isUndef()) { |
0 |
| 25291 |
Mask.push_back(-1); |
0 |
25291 |
Mask.push_back(-1); |
0 |
| 25292 |
continue; |
0 |
25292 |
continue; |
0 |
| 25293 |
} |
--- |
25293 |
} |
--- |
| 25294 |
InnerIdx %= NumElts; |
0 |
25294 |
InnerIdx %= NumElts; |
0 |
| 25295 |
if (InnerVec == SV0) { |
0 |
25295 |
if (InnerVec == SV0) { |
0 |
| 25296 |
Mask.push_back(InnerIdx); |
0 |
25296 |
Mask.push_back(InnerIdx); |
0 |
| 25297 |
continue; |
0 |
25297 |
continue; |
0 |
| 25298 |
} |
--- |
25298 |
} |
--- |
| 25299 |
if (InnerVec == SV1) { |
0 |
25299 |
if (InnerVec == SV1) { |
0 |
| 25300 |
Mask.push_back(InnerIdx + NumElts); |
0 |
25300 |
Mask.push_back(InnerIdx + NumElts); |
0 |
| 25301 |
continue; |
0 |
25301 |
continue; |
0 |
| 25302 |
} |
--- |
25302 |
} |
--- |
| 25303 |
} |
--- |
25303 |
} |
--- |
| 25304 |
|
--- |
25304 |
|
--- |
| 25305 |
// Bail out if we cannot convert the shuffle pair into a single shuffle. |
--- |
25305 |
// Bail out if we cannot convert the shuffle pair into a single shuffle. |
--- |
| 25306 |
return false; |
0 |
25306 |
return false; |
0 |
| 25307 |
} |
--- |
25307 |
} |
--- |
| 25308 |
|
--- |
25308 |
|
--- |
| 25309 |
if (llvm::all_of(Mask, [](int M) { return M < 0; })) |
0 |
25309 |
if (llvm::all_of(Mask, [](int M) { return M < 0; })) |
0 |
| 25310 |
return true; |
0 |
25310 |
return true; |
0 |
| 25311 |
|
--- |
25311 |
|
--- |
| 25312 |
// Avoid introducing shuffles with illegal mask. |
--- |
25312 |
// Avoid introducing shuffles with illegal mask. |
--- |
| 25313 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2) |
--- |
25313 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2) |
--- |
| 25314 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2) |
--- |
25314 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2) |
--- |
| 25315 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2) |
--- |
25315 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2) |
--- |
| 25316 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, A, M2) |
--- |
25316 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, A, M2) |
--- |
| 25317 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, A, M2) |
--- |
25317 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, A, M2) |
--- |
| 25318 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, B, M2) |
--- |
25318 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, B, M2) |
--- |
| 25319 |
if (TLI.isShuffleMaskLegal(Mask, VT)) |
0 |
25319 |
if (TLI.isShuffleMaskLegal(Mask, VT)) |
0 |
| 25320 |
return true; |
0 |
25320 |
return true; |
0 |
| 25321 |
|
--- |
25321 |
|
--- |
| 25322 |
std::swap(SV0, SV1); |
0 |
25322 |
std::swap(SV0, SV1); |
0 |
| 25323 |
ShuffleVectorSDNode::commuteMask(Mask); |
0 |
25323 |
ShuffleVectorSDNode::commuteMask(Mask); |
0 |
| 25324 |
return TLI.isShuffleMaskLegal(Mask, VT); |
0 |
25324 |
return TLI.isShuffleMaskLegal(Mask, VT); |
0 |
| 25325 |
}; |
0 |
25325 |
}; |
0 |
| 25326 |
|
--- |
25326 |
|
--- |
| 25327 |
if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT)) { |
0 |
25327 |
if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT)) { |
0 |
| 25328 |
// Canonicalize shuffles according to rules: |
--- |
25328 |
// Canonicalize shuffles according to rules: |
--- |
| 25329 |
// shuffle(A, shuffle(A, B)) -> shuffle(shuffle(A,B), A) |
--- |
25329 |
// shuffle(A, shuffle(A, B)) -> shuffle(shuffle(A,B), A) |
--- |
| 25330 |
// shuffle(B, shuffle(A, B)) -> shuffle(shuffle(A,B), B) |
--- |
25330 |
// shuffle(B, shuffle(A, B)) -> shuffle(shuffle(A,B), B) |
--- |
| 25331 |
// shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B) |
--- |
25331 |
// shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B) |
--- |
| 25332 |
if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && |
0 |
25332 |
if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && |
0 |
| 25333 |
N0.getOpcode() != ISD::VECTOR_SHUFFLE) { |
0 |
25333 |
N0.getOpcode() != ISD::VECTOR_SHUFFLE) { |
0 |
| 25334 |
// The incoming shuffle must be of the same type as the result of the |
--- |
25334 |
// The incoming shuffle must be of the same type as the result of the |
--- |
| 25335 |
// current shuffle. |
--- |
25335 |
// current shuffle. |
--- |
| 25336 |
assert(N1->getOperand(0).getValueType() == VT && |
0 |
25336 |
assert(N1->getOperand(0).getValueType() == VT && |
0 |
| 25337 |
"Shuffle types don't match"); |
--- |
25337 |
"Shuffle types don't match"); |
--- |
| 25338 |
|
--- |
25338 |
|
--- |
| 25339 |
SDValue SV0 = N1->getOperand(0); |
0 |
25339 |
SDValue SV0 = N1->getOperand(0); |
0 |
| 25340 |
SDValue SV1 = N1->getOperand(1); |
0 |
25340 |
SDValue SV1 = N1->getOperand(1); |
0 |
| 25341 |
bool HasSameOp0 = N0 == SV0; |
0 |
25341 |
bool HasSameOp0 = N0 == SV0; |
0 |
| 25342 |
bool IsSV1Undef = SV1.isUndef(); |
0 |
25342 |
bool IsSV1Undef = SV1.isUndef(); |
0 |
| 25343 |
if (HasSameOp0 || IsSV1Undef || N0 == SV1) |
0 |
25343 |
if (HasSameOp0 || IsSV1Undef || N0 == SV1) |
0 |
| 25344 |
// Commute the operands of this shuffle so merging below will trigger. |
--- |
25344 |
// Commute the operands of this shuffle so merging below will trigger. |
--- |
| 25345 |
return DAG.getCommutedVectorShuffle(*SVN); |
0 |
25345 |
return DAG.getCommutedVectorShuffle(*SVN); |
0 |
| 25346 |
} |
--- |
25346 |
} |
--- |
| 25347 |
|
--- |
25347 |
|
--- |
| 25348 |
// Canonicalize splat shuffles to the RHS to improve merging below. |
--- |
25348 |
// Canonicalize splat shuffles to the RHS to improve merging below. |
--- |
| 25349 |
// shuffle(splat(A,u), shuffle(C,D)) -> shuffle'(shuffle(C,D), splat(A,u)) |
--- |
25349 |
// shuffle(splat(A,u), shuffle(C,D)) -> shuffle'(shuffle(C,D), splat(A,u)) |
--- |
| 25350 |
if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && |
0 |
25350 |
if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && |
0 |
| 25351 |
N1.getOpcode() == ISD::VECTOR_SHUFFLE && |
0 |
25351 |
N1.getOpcode() == ISD::VECTOR_SHUFFLE && |
0 |
| 25352 |
cast(N0)->isSplat() && |
0 |
25352 |
cast(N0)->isSplat() && |
0 |
| 25353 |
!cast(N1)->isSplat()) { |
0 |
25353 |
!cast(N1)->isSplat()) { |
0 |
| 25354 |
return DAG.getCommutedVectorShuffle(*SVN); |
0 |
25354 |
return DAG.getCommutedVectorShuffle(*SVN); |
0 |
| 25355 |
} |
--- |
25355 |
} |
--- |
| 25356 |
|
--- |
25356 |
|
--- |
| 25357 |
// Try to fold according to rules: |
--- |
25357 |
// Try to fold according to rules: |
--- |
| 25358 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2) |
--- |
25358 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2) |
--- |
| 25359 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2) |
--- |
25359 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2) |
--- |
| 25360 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2) |
--- |
25360 |
// shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2) |
--- |
| 25361 |
// Don't try to fold shuffles with illegal type. |
--- |
25361 |
// Don't try to fold shuffles with illegal type. |
--- |
| 25362 |
// Only fold if this shuffle is the only user of the other shuffle. |
--- |
25362 |
// Only fold if this shuffle is the only user of the other shuffle. |
--- |
| 25363 |
// Try matching shuffle(C,shuffle(A,B)) commutted patterns as well. |
--- |
25363 |
// Try matching shuffle(C,shuffle(A,B)) commutted patterns as well. |
--- |
| 25364 |
for (int i = 0; i != 2; ++i) { |
0 |
25364 |
for (int i = 0; i != 2; ++i) { |
0 |
| 25365 |
if (N->getOperand(i).getOpcode() == ISD::VECTOR_SHUFFLE && |
0 |
25365 |
if (N->getOperand(i).getOpcode() == ISD::VECTOR_SHUFFLE && |
0 |
| 25366 |
N->isOnlyUserOf(N->getOperand(i).getNode())) { |
0 |
25366 |
N->isOnlyUserOf(N->getOperand(i).getNode())) { |
0 |
| 25367 |
// The incoming shuffle must be of the same type as the result of the |
--- |
25367 |
// The incoming shuffle must be of the same type as the result of the |
--- |
| 25368 |
// current shuffle. |
--- |
25368 |
// current shuffle. |
--- |
| 25369 |
auto *OtherSV = cast(N->getOperand(i)); |
0 |
25369 |
auto *OtherSV = cast(N->getOperand(i)); |
0 |
| 25370 |
assert(OtherSV->getOperand(0).getValueType() == VT && |
0 |
25370 |
assert(OtherSV->getOperand(0).getValueType() == VT && |
0 |
| 25371 |
"Shuffle types don't match"); |
--- |
25371 |
"Shuffle types don't match"); |
--- |
| 25372 |
|
--- |
25372 |
|
--- |
| 25373 |
SDValue SV0, SV1; |
0 |
25373 |
SDValue SV0, SV1; |
0 |
| 25374 |
SmallVector Mask; |
0 |
25374 |
SmallVector Mask; |
0 |
| 25375 |
if (MergeInnerShuffle(i != 0, SVN, OtherSV, N->getOperand(1 - i), TLI, |
0 |
25375 |
if (MergeInnerShuffle(i != 0, SVN, OtherSV, N->getOperand(1 - i), TLI, |
0 |
| 25376 |
SV0, SV1, Mask)) { |
--- |
25376 |
SV0, SV1, Mask)) { |
--- |
| 25377 |
// Check if all indices in Mask are Undef. In case, propagate Undef. |
--- |
25377 |
// Check if all indices in Mask are Undef. In case, propagate Undef. |
--- |
| 25378 |
if (llvm::all_of(Mask, [](int M) { return M < 0; })) |
0 |
25378 |
if (llvm::all_of(Mask, [](int M) { return M < 0; })) |
0 |
| 25379 |
return DAG.getUNDEF(VT); |
0 |
25379 |
return DAG.getUNDEF(VT); |
0 |
| 25380 |
|
--- |
25380 |
|
--- |
| 25381 |
return DAG.getVectorShuffle(VT, SDLoc(N), |
0 |
25381 |
return DAG.getVectorShuffle(VT, SDLoc(N), |
0 |
| 25382 |
SV0 ? SV0 : DAG.getUNDEF(VT), |
0 |
25382 |
SV0 ? SV0 : DAG.getUNDEF(VT), |
0 |
| 25383 |
SV1 ? SV1 : DAG.getUNDEF(VT), Mask); |
0 |
25383 |
SV1 ? SV1 : DAG.getUNDEF(VT), Mask); |
0 |
| 25384 |
} |
--- |
25384 |
} |
--- |
| 25385 |
} |
0 |
25385 |
} |
0 |
| 25386 |
} |
--- |
25386 |
} |
--- |
| 25387 |
|
--- |
25387 |
|
--- |
| 25388 |
// Merge shuffles through binops if we are able to merge it with at least |
--- |
25388 |
// Merge shuffles through binops if we are able to merge it with at least |
--- |
| 25389 |
// one other shuffles. |
--- |
25389 |
// one other shuffles. |
--- |
| 25390 |
// shuffle(bop(shuffle(x,y),shuffle(z,w)),undef) |
--- |
25390 |
// shuffle(bop(shuffle(x,y),shuffle(z,w)),undef) |
--- |
| 25391 |
// shuffle(bop(shuffle(x,y),shuffle(z,w)),bop(shuffle(a,b),shuffle(c,d))) |
--- |
25391 |
// shuffle(bop(shuffle(x,y),shuffle(z,w)),bop(shuffle(a,b),shuffle(c,d))) |
--- |
| 25392 |
unsigned SrcOpcode = N0.getOpcode(); |
0 |
25392 |
unsigned SrcOpcode = N0.getOpcode(); |
0 |
| 25393 |
if (TLI.isBinOp(SrcOpcode) && N->isOnlyUserOf(N0.getNode()) && |
0 |
25393 |
if (TLI.isBinOp(SrcOpcode) && N->isOnlyUserOf(N0.getNode()) && |
0 |
| 25394 |
(N1.isUndef() || |
0 |
25394 |
(N1.isUndef() || |
0 |
| 25395 |
(SrcOpcode == N1.getOpcode() && N->isOnlyUserOf(N1.getNode())))) { |
0 |
25395 |
(SrcOpcode == N1.getOpcode() && N->isOnlyUserOf(N1.getNode())))) { |
0 |
| 25396 |
// Get binop source ops, or just pass on the undef. |
--- |
25396 |
// Get binop source ops, or just pass on the undef. |
--- |
| 25397 |
SDValue Op00 = N0.getOperand(0); |
0 |
25397 |
SDValue Op00 = N0.getOperand(0); |
0 |
| 25398 |
SDValue Op01 = N0.getOperand(1); |
0 |
25398 |
SDValue Op01 = N0.getOperand(1); |
0 |
| 25399 |
SDValue Op10 = N1.isUndef() ? N1 : N1.getOperand(0); |
0 |
25399 |
SDValue Op10 = N1.isUndef() ? N1 : N1.getOperand(0); |
0 |
| 25400 |
SDValue Op11 = N1.isUndef() ? N1 : N1.getOperand(1); |
0 |
25400 |
SDValue Op11 = N1.isUndef() ? N1 : N1.getOperand(1); |
0 |
| 25401 |
// TODO: We might be able to relax the VT check but we don't currently |
--- |
25401 |
// TODO: We might be able to relax the VT check but we don't currently |
--- |
| 25402 |
// have any isBinOp() that has different result/ops VTs so play safe until |
--- |
25402 |
// have any isBinOp() that has different result/ops VTs so play safe until |
--- |
| 25403 |
// we have test coverage. |
--- |
25403 |
// we have test coverage. |
--- |
| 25404 |
if (Op00.getValueType() == VT && Op10.getValueType() == VT && |
0 |
25404 |
if (Op00.getValueType() == VT && Op10.getValueType() == VT && |
0 |
| 25405 |
Op01.getValueType() == VT && Op11.getValueType() == VT && |
0 |
25405 |
Op01.getValueType() == VT && Op11.getValueType() == VT && |
0 |
| 25406 |
(Op00.getOpcode() == ISD::VECTOR_SHUFFLE || |
0 |
25406 |
(Op00.getOpcode() == ISD::VECTOR_SHUFFLE || |
0 |
| 25407 |
Op10.getOpcode() == ISD::VECTOR_SHUFFLE || |
0 |
25407 |
Op10.getOpcode() == ISD::VECTOR_SHUFFLE || |
0 |
| 25408 |
Op01.getOpcode() == ISD::VECTOR_SHUFFLE || |
0 |
25408 |
Op01.getOpcode() == ISD::VECTOR_SHUFFLE || |
0 |
| 25409 |
Op11.getOpcode() == ISD::VECTOR_SHUFFLE)) { |
0 |
25409 |
Op11.getOpcode() == ISD::VECTOR_SHUFFLE)) { |
0 |
| 25410 |
auto CanMergeInnerShuffle = [&](SDValue &SV0, SDValue &SV1, |
0 |
25410 |
auto CanMergeInnerShuffle = [&](SDValue &SV0, SDValue &SV1, |
0 |
| 25411 |
SmallVectorImpl &Mask, bool LeftOp, |
--- |
25411 |
SmallVectorImpl &Mask, bool LeftOp, |
--- |
| 25412 |
bool Commute) { |
--- |
25412 |
bool Commute) { |
--- |
| 25413 |
SDValue InnerN = Commute ? N1 : N0; |
0 |
25413 |
SDValue InnerN = Commute ? N1 : N0; |
0 |
| 25414 |
SDValue Op0 = LeftOp ? Op00 : Op01; |
0 |
25414 |
SDValue Op0 = LeftOp ? Op00 : Op01; |
0 |
| 25415 |
SDValue Op1 = LeftOp ? Op10 : Op11; |
0 |
25415 |
SDValue Op1 = LeftOp ? Op10 : Op11; |
0 |
| 25416 |
if (Commute) |
0 |
25416 |
if (Commute) |
0 |
| 25417 |
std::swap(Op0, Op1); |
0 |
25417 |
std::swap(Op0, Op1); |
0 |
| 25418 |
// Only accept the merged shuffle if we don't introduce undef elements, |
--- |
25418 |
// Only accept the merged shuffle if we don't introduce undef elements, |
--- |
| 25419 |
// or the inner shuffle already contained undef elements. |
--- |
25419 |
// or the inner shuffle already contained undef elements. |
--- |
| 25420 |
auto *SVN0 = dyn_cast(Op0); |
0 |
25420 |
auto *SVN0 = dyn_cast(Op0); |
0 |
| 25421 |
return SVN0 && InnerN->isOnlyUserOf(SVN0) && |
0 |
25421 |
return SVN0 && InnerN->isOnlyUserOf(SVN0) && |
0 |
| 25422 |
MergeInnerShuffle(Commute, SVN, SVN0, Op1, TLI, SV0, SV1, |
0 |
25422 |
MergeInnerShuffle(Commute, SVN, SVN0, Op1, TLI, SV0, SV1, |
0 |
| 25423 |
Mask) && |
0 |
25423 |
Mask) && |
0 |
| 25424 |
(llvm::any_of(SVN0->getMask(), [](int M) { return M < 0; }) || |
0 |
25424 |
(llvm::any_of(SVN0->getMask(), [](int M) { return M < 0; }) || |
0 |
| 25425 |
llvm::none_of(Mask, [](int M) { return M < 0; })); |
0 |
25425 |
llvm::none_of(Mask, [](int M) { return M < 0; })); |
0 |
| 25426 |
}; |
0 |
25426 |
}; |
0 |
| 25427 |
|
--- |
25427 |
|
--- |
| 25428 |
// Ensure we don't increase the number of shuffles - we must merge a |
--- |
25428 |
// Ensure we don't increase the number of shuffles - we must merge a |
--- |
| 25429 |
// shuffle from at least one of the LHS and RHS ops. |
--- |
25429 |
// shuffle from at least one of the LHS and RHS ops. |
--- |
| 25430 |
bool MergedLeft = false; |
0 |
25430 |
bool MergedLeft = false; |
0 |
| 25431 |
SDValue LeftSV0, LeftSV1; |
0 |
25431 |
SDValue LeftSV0, LeftSV1; |
0 |
| 25432 |
SmallVector LeftMask; |
0 |
25432 |
SmallVector LeftMask; |
0 |
| 25433 |
if (CanMergeInnerShuffle(LeftSV0, LeftSV1, LeftMask, true, false) || |
0 |
25433 |
if (CanMergeInnerShuffle(LeftSV0, LeftSV1, LeftMask, true, false) || |
0 |
| 25434 |
CanMergeInnerShuffle(LeftSV0, LeftSV1, LeftMask, true, true)) { |
0 |
25434 |
CanMergeInnerShuffle(LeftSV0, LeftSV1, LeftMask, true, true)) { |
0 |
| 25435 |
MergedLeft = true; |
0 |
25435 |
MergedLeft = true; |
0 |
| 25436 |
} else { |
--- |
25436 |
} else { |
--- |
| 25437 |
LeftMask.assign(SVN->getMask().begin(), SVN->getMask().end()); |
0 |
25437 |
LeftMask.assign(SVN->getMask().begin(), SVN->getMask().end()); |
0 |
| 25438 |
LeftSV0 = Op00, LeftSV1 = Op10; |
0 |
25438 |
LeftSV0 = Op00, LeftSV1 = Op10; |
0 |
| 25439 |
} |
--- |
25439 |
} |
--- |
| 25440 |
|
--- |
25440 |
|
--- |
| 25441 |
bool MergedRight = false; |
0 |
25441 |
bool MergedRight = false; |
0 |
| 25442 |
SDValue RightSV0, RightSV1; |
0 |
25442 |
SDValue RightSV0, RightSV1; |
0 |
| 25443 |
SmallVector RightMask; |
0 |
25443 |
SmallVector RightMask; |
0 |
| 25444 |
if (CanMergeInnerShuffle(RightSV0, RightSV1, RightMask, false, false) || |
0 |
25444 |
if (CanMergeInnerShuffle(RightSV0, RightSV1, RightMask, false, false) || |
0 |
| 25445 |
CanMergeInnerShuffle(RightSV0, RightSV1, RightMask, false, true)) { |
0 |
25445 |
CanMergeInnerShuffle(RightSV0, RightSV1, RightMask, false, true)) { |
0 |
| 25446 |
MergedRight = true; |
0 |
25446 |
MergedRight = true; |
0 |
| 25447 |
} else { |
--- |
25447 |
} else { |
--- |
| 25448 |
RightMask.assign(SVN->getMask().begin(), SVN->getMask().end()); |
0 |
25448 |
RightMask.assign(SVN->getMask().begin(), SVN->getMask().end()); |
0 |
| 25449 |
RightSV0 = Op01, RightSV1 = Op11; |
0 |
25449 |
RightSV0 = Op01, RightSV1 = Op11; |
0 |
| 25450 |
} |
--- |
25450 |
} |
--- |
| 25451 |
|
--- |
25451 |
|
--- |
| 25452 |
if (MergedLeft || MergedRight) { |
0 |
25452 |
if (MergedLeft || MergedRight) { |
0 |
| 25453 |
SDLoc DL(N); |
0 |
25453 |
SDLoc DL(N); |
0 |
| 25454 |
SDValue LHS = DAG.getVectorShuffle( |
0 |
25454 |
SDValue LHS = DAG.getVectorShuffle( |
0 |
| 25455 |
VT, DL, LeftSV0 ? LeftSV0 : DAG.getUNDEF(VT), |
0 |
25455 |
VT, DL, LeftSV0 ? LeftSV0 : DAG.getUNDEF(VT), |
0 |
| 25456 |
LeftSV1 ? LeftSV1 : DAG.getUNDEF(VT), LeftMask); |
0 |
25456 |
LeftSV1 ? LeftSV1 : DAG.getUNDEF(VT), LeftMask); |
0 |
| 25457 |
SDValue RHS = DAG.getVectorShuffle( |
0 |
25457 |
SDValue RHS = DAG.getVectorShuffle( |
0 |
| 25458 |
VT, DL, RightSV0 ? RightSV0 : DAG.getUNDEF(VT), |
0 |
25458 |
VT, DL, RightSV0 ? RightSV0 : DAG.getUNDEF(VT), |
0 |
| 25459 |
RightSV1 ? RightSV1 : DAG.getUNDEF(VT), RightMask); |
0 |
25459 |
RightSV1 ? RightSV1 : DAG.getUNDEF(VT), RightMask); |
0 |
| 25460 |
return DAG.getNode(SrcOpcode, DL, VT, LHS, RHS); |
0 |
25460 |
return DAG.getNode(SrcOpcode, DL, VT, LHS, RHS); |
0 |
| 25461 |
} |
0 |
25461 |
} |
0 |
| 25462 |
} |
0 |
25462 |
} |
0 |
| 25463 |
} |
--- |
25463 |
} |
--- |
| 25464 |
} |
--- |
25464 |
} |
--- |
| 25465 |
|
--- |
25465 |
|
--- |
| 25466 |
if (SDValue V = foldShuffleOfConcatUndefs(SVN, DAG)) |
0 |
25466 |
if (SDValue V = foldShuffleOfConcatUndefs(SVN, DAG)) |
0 |
| 25467 |
return V; |
0 |
25467 |
return V; |
0 |
| 25468 |
|
--- |
25468 |
|
--- |
| 25469 |
// Match shuffles that can be converted to ISD::ZERO_EXTEND_VECTOR_INREG. |
--- |
25469 |
// Match shuffles that can be converted to ISD::ZERO_EXTEND_VECTOR_INREG. |
--- |
| 25470 |
// Perform this really late, because it could eliminate knowledge |
--- |
25470 |
// Perform this really late, because it could eliminate knowledge |
--- |
| 25471 |
// of undef elements created by this shuffle. |
--- |
25471 |
// of undef elements created by this shuffle. |
--- |
| 25472 |
if (Level < AfterLegalizeTypes) |
0 |
25472 |
if (Level < AfterLegalizeTypes) |
0 |
| 25473 |
if (SDValue V = combineShuffleToZeroExtendVectorInReg(SVN, DAG, TLI, |
0 |
25473 |
if (SDValue V = combineShuffleToZeroExtendVectorInReg(SVN, DAG, TLI, |
0 |
| 25474 |
LegalOperations)) |
0 |
25474 |
LegalOperations)) |
0 |
| 25475 |
return V; |
0 |
25475 |
return V; |
0 |
| 25476 |
|
--- |
25476 |
|
--- |
| 25477 |
return SDValue(); |
0 |
25477 |
return SDValue(); |
0 |
| 25478 |
} |
--- |
25478 |
} |
--- |
| 25479 |
|
--- |
25479 |
|
--- |
| 25480 |
SDValue DAGCombiner::visitSCALAR_TO_VECTOR(SDNode *N) { |
0 |
25480 |
SDValue DAGCombiner::visitSCALAR_TO_VECTOR(SDNode *N) { |
0 |
| 25481 |
EVT VT = N->getValueType(0); |
0 |
25481 |
EVT VT = N->getValueType(0); |
0 |
| 25482 |
if (!VT.isFixedLengthVector()) |
0 |
25482 |
if (!VT.isFixedLengthVector()) |
0 |
| 25483 |
return SDValue(); |
0 |
25483 |
return SDValue(); |
0 |
| 25484 |
|
--- |
25484 |
|
--- |
| 25485 |
// Try to convert a scalar binop with an extracted vector element to a vector |
--- |
25485 |
// Try to convert a scalar binop with an extracted vector element to a vector |
--- |
| 25486 |
// binop. This is intended to reduce potentially expensive register moves. |
--- |
25486 |
// binop. This is intended to reduce potentially expensive register moves. |
--- |
| 25487 |
// TODO: Check if both operands are extracted. |
--- |
25487 |
// TODO: Check if both operands are extracted. |
--- |
| 25488 |
// TODO: Generalize this, so it can be called from visitINSERT_VECTOR_ELT(). |
--- |
25488 |
// TODO: Generalize this, so it can be called from visitINSERT_VECTOR_ELT(). |
--- |
| 25489 |
SDValue Scalar = N->getOperand(0); |
0 |
25489 |
SDValue Scalar = N->getOperand(0); |
0 |
| 25490 |
unsigned Opcode = Scalar.getOpcode(); |
0 |
25490 |
unsigned Opcode = Scalar.getOpcode(); |
0 |
| 25491 |
EVT VecEltVT = VT.getScalarType(); |
0 |
25491 |
EVT VecEltVT = VT.getScalarType(); |
0 |
| 25492 |
if (Scalar.hasOneUse() && Scalar->getNumValues() == 1 && |
0 |
25492 |
if (Scalar.hasOneUse() && Scalar->getNumValues() == 1 && |
0 |
| 25493 |
TLI.isBinOp(Opcode) && Scalar.getValueType() == VecEltVT && |
0 |
25493 |
TLI.isBinOp(Opcode) && Scalar.getValueType() == VecEltVT && |
0 |
| 25494 |
Scalar.getOperand(0).getValueType() == VecEltVT && |
0 |
25494 |
Scalar.getOperand(0).getValueType() == VecEltVT && |
0 |
| 25495 |
Scalar.getOperand(1).getValueType() == VecEltVT && |
0 |
25495 |
Scalar.getOperand(1).getValueType() == VecEltVT && |
0 |
| 25496 |
DAG.isSafeToSpeculativelyExecute(Opcode) && hasOperation(Opcode, VT)) { |
0 |
25496 |
DAG.isSafeToSpeculativelyExecute(Opcode) && hasOperation(Opcode, VT)) { |
0 |
| 25497 |
// Match an extract element and get a shuffle mask equivalent. |
--- |
25497 |
// Match an extract element and get a shuffle mask equivalent. |
--- |
| 25498 |
SmallVector ShufMask(VT.getVectorNumElements(), -1); |
0 |
25498 |
SmallVector ShufMask(VT.getVectorNumElements(), -1); |
0 |
| 25499 |
|
--- |
25499 |
|
--- |
| 25500 |
for (int i : {0, 1}) { |
0 |
25500 |
for (int i : {0, 1}) { |
0 |
| 25501 |
// s2v (bo (extelt V, Idx), C) --> shuffle (bo V, C'), {Idx, -1, -1...} |
--- |
25501 |
// s2v (bo (extelt V, Idx), C) --> shuffle (bo V, C'), {Idx, -1, -1...} |
--- |
| 25502 |
// s2v (bo C, (extelt V, Idx)) --> shuffle (bo C', V), {Idx, -1, -1...} |
--- |
25502 |
// s2v (bo C, (extelt V, Idx)) --> shuffle (bo C', V), {Idx, -1, -1...} |
--- |
| 25503 |
SDValue EE = Scalar.getOperand(i); |
0 |
25503 |
SDValue EE = Scalar.getOperand(i); |
0 |
| 25504 |
auto *C = dyn_cast(Scalar.getOperand(i ? 0 : 1)); |
0 |
25504 |
auto *C = dyn_cast(Scalar.getOperand(i ? 0 : 1)); |
0 |
| 25505 |
if (C && EE.getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
0 |
25505 |
if (C && EE.getOpcode() == ISD::EXTRACT_VECTOR_ELT && |
0 |
| 25506 |
EE.getOperand(0).getValueType() == VT && |
0 |
25506 |
EE.getOperand(0).getValueType() == VT && |
0 |
| 25507 |
isa(EE.getOperand(1))) { |
0 |
25507 |
isa(EE.getOperand(1))) { |
0 |
| 25508 |
// Mask = {ExtractIndex, undef, undef....} |
--- |
25508 |
// Mask = {ExtractIndex, undef, undef....} |
--- |
| 25509 |
ShufMask[0] = EE.getConstantOperandVal(1); |
0 |
25509 |
ShufMask[0] = EE.getConstantOperandVal(1); |
0 |
| 25510 |
// Make sure the shuffle is legal if we are crossing lanes. |
--- |
25510 |
// Make sure the shuffle is legal if we are crossing lanes. |
--- |
| 25511 |
if (TLI.isShuffleMaskLegal(ShufMask, VT)) { |
0 |
25511 |
if (TLI.isShuffleMaskLegal(ShufMask, VT)) { |
0 |
| 25512 |
SDLoc DL(N); |
0 |
25512 |
SDLoc DL(N); |
0 |
| 25513 |
SDValue V[] = {EE.getOperand(0), |
0 |
25513 |
SDValue V[] = {EE.getOperand(0), |
0 |
| 25514 |
DAG.getConstant(C->getAPIntValue(), DL, VT)}; |
0 |
25514 |
DAG.getConstant(C->getAPIntValue(), DL, VT)}; |
0 |
| 25515 |
SDValue VecBO = DAG.getNode(Opcode, DL, VT, V[i], V[1 - i]); |
0 |
25515 |
SDValue VecBO = DAG.getNode(Opcode, DL, VT, V[i], V[1 - i]); |
0 |
| 25516 |
return DAG.getVectorShuffle(VT, DL, VecBO, DAG.getUNDEF(VT), |
0 |
25516 |
return DAG.getVectorShuffle(VT, DL, VecBO, DAG.getUNDEF(VT), |
0 |
| 25517 |
ShufMask); |
0 |
25517 |
ShufMask); |
0 |
| 25518 |
} |
0 |
25518 |
} |
0 |
| 25519 |
} |
--- |
25519 |
} |
--- |
| 25520 |
} |
--- |
25520 |
} |
--- |
| 25521 |
} |
0 |
25521 |
} |
0 |
| 25522 |
|
--- |
25522 |
|
--- |
| 25523 |
// Replace a SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(V,C0)) pattern |
--- |
25523 |
// Replace a SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(V,C0)) pattern |
--- |
| 25524 |
// with a VECTOR_SHUFFLE and possible truncate. |
--- |
25524 |
// with a VECTOR_SHUFFLE and possible truncate. |
--- |
| 25525 |
if (Opcode != ISD::EXTRACT_VECTOR_ELT || |
0 |
25525 |
if (Opcode != ISD::EXTRACT_VECTOR_ELT || |
0 |
| 25526 |
!Scalar.getOperand(0).getValueType().isFixedLengthVector()) |
0 |
25526 |
!Scalar.getOperand(0).getValueType().isFixedLengthVector()) |
0 |
| 25527 |
return SDValue(); |
0 |
25527 |
return SDValue(); |
0 |
| 25528 |
|
--- |
25528 |
|
--- |
| 25529 |
// If we have an implicit truncate, truncate here if it is legal. |
--- |
25529 |
// If we have an implicit truncate, truncate here if it is legal. |
--- |
| 25530 |
if (VecEltVT != Scalar.getValueType() && |
0 |
25530 |
if (VecEltVT != Scalar.getValueType() && |
0 |
| 25531 |
Scalar.getValueType().isScalarInteger() && isTypeLegal(VecEltVT)) { |
0 |
25531 |
Scalar.getValueType().isScalarInteger() && isTypeLegal(VecEltVT)) { |
0 |
| 25532 |
SDValue Val = DAG.getNode(ISD::TRUNCATE, SDLoc(Scalar), VecEltVT, Scalar); |
0 |
25532 |
SDValue Val = DAG.getNode(ISD::TRUNCATE, SDLoc(Scalar), VecEltVT, Scalar); |
0 |
| 25533 |
return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Val); |
0 |
25533 |
return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Val); |
0 |
| 25534 |
} |
--- |
25534 |
} |
--- |
| 25535 |
|
--- |
25535 |
|
--- |
| 25536 |
auto *ExtIndexC = dyn_cast(Scalar.getOperand(1)); |
0 |
25536 |
auto *ExtIndexC = dyn_cast(Scalar.getOperand(1)); |
0 |
| 25537 |
if (!ExtIndexC) |
0 |
25537 |
if (!ExtIndexC) |
0 |
| 25538 |
return SDValue(); |
0 |
25538 |
return SDValue(); |
0 |
| 25539 |
|
--- |
25539 |
|
--- |
| 25540 |
SDValue SrcVec = Scalar.getOperand(0); |
0 |
25540 |
SDValue SrcVec = Scalar.getOperand(0); |
0 |
| 25541 |
EVT SrcVT = SrcVec.getValueType(); |
0 |
25541 |
EVT SrcVT = SrcVec.getValueType(); |
0 |
| 25542 |
unsigned SrcNumElts = SrcVT.getVectorNumElements(); |
0 |
25542 |
unsigned SrcNumElts = SrcVT.getVectorNumElements(); |
0 |
| 25543 |
unsigned VTNumElts = VT.getVectorNumElements(); |
0 |
25543 |
unsigned VTNumElts = VT.getVectorNumElements(); |
0 |
| 25544 |
if (VecEltVT == SrcVT.getScalarType() && VTNumElts <= SrcNumElts) { |
0 |
25544 |
if (VecEltVT == SrcVT.getScalarType() && VTNumElts <= SrcNumElts) { |
0 |
| 25545 |
// Create a shuffle equivalent for scalar-to-vector: {ExtIndex, -1, -1, ...} |
--- |
25545 |
// Create a shuffle equivalent for scalar-to-vector: {ExtIndex, -1, -1, ...} |
--- |
| 25546 |
SmallVector Mask(SrcNumElts, -1); |
0 |
25546 |
SmallVector Mask(SrcNumElts, -1); |
0 |
| 25547 |
Mask[0] = ExtIndexC->getZExtValue(); |
0 |
25547 |
Mask[0] = ExtIndexC->getZExtValue(); |
0 |
| 25548 |
SDValue LegalShuffle = TLI.buildLegalVectorShuffle( |
0 |
25548 |
SDValue LegalShuffle = TLI.buildLegalVectorShuffle( |
0 |
| 25549 |
SrcVT, SDLoc(N), SrcVec, DAG.getUNDEF(SrcVT), Mask, DAG); |
0 |
25549 |
SrcVT, SDLoc(N), SrcVec, DAG.getUNDEF(SrcVT), Mask, DAG); |
0 |
| 25550 |
if (!LegalShuffle) |
0 |
25550 |
if (!LegalShuffle) |
0 |
| 25551 |
return SDValue(); |
0 |
25551 |
return SDValue(); |
0 |
| 25552 |
|
--- |
25552 |
|
--- |
| 25553 |
// If the initial vector is the same size, the shuffle is the result. |
--- |
25553 |
// If the initial vector is the same size, the shuffle is the result. |
--- |
| 25554 |
if (VT == SrcVT) |
0 |
25554 |
if (VT == SrcVT) |
0 |
| 25555 |
return LegalShuffle; |
0 |
25555 |
return LegalShuffle; |
0 |
| 25556 |
|
--- |
25556 |
|
--- |
| 25557 |
// If not, shorten the shuffled vector. |
--- |
25557 |
// If not, shorten the shuffled vector. |
--- |
| 25558 |
if (VTNumElts != SrcNumElts) { |
0 |
25558 |
if (VTNumElts != SrcNumElts) { |
0 |
| 25559 |
SDValue ZeroIdx = DAG.getVectorIdxConstant(0, SDLoc(N)); |
0 |
25559 |
SDValue ZeroIdx = DAG.getVectorIdxConstant(0, SDLoc(N)); |
0 |
| 25560 |
EVT SubVT = EVT::getVectorVT(*DAG.getContext(), |
0 |
25560 |
EVT SubVT = EVT::getVectorVT(*DAG.getContext(), |
0 |
| 25561 |
SrcVT.getVectorElementType(), VTNumElts); |
--- |
25561 |
SrcVT.getVectorElementType(), VTNumElts); |
--- |
| 25562 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), SubVT, LegalShuffle, |
0 |
25562 |
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), SubVT, LegalShuffle, |
0 |
| 25563 |
ZeroIdx); |
0 |
25563 |
ZeroIdx); |
0 |
| 25564 |
} |
--- |
25564 |
} |
--- |
| 25565 |
} |
0 |
25565 |
} |
0 |
| 25566 |
|
--- |
25566 |
|
--- |
| 25567 |
return SDValue(); |
0 |
25567 |
return SDValue(); |
0 |
| 25568 |
} |
--- |
25568 |
} |
--- |
| 25569 |
|
--- |
25569 |
|
--- |
| 25570 |
SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) { |
0 |
25570 |
SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) { |
0 |
| 25571 |
EVT VT = N->getValueType(0); |
0 |
25571 |
EVT VT = N->getValueType(0); |
0 |
| 25572 |
SDValue N0 = N->getOperand(0); |
0 |
25572 |
SDValue N0 = N->getOperand(0); |
0 |
| 25573 |
SDValue N1 = N->getOperand(1); |
0 |
25573 |
SDValue N1 = N->getOperand(1); |
0 |
| 25574 |
SDValue N2 = N->getOperand(2); |
0 |
25574 |
SDValue N2 = N->getOperand(2); |
0 |
| 25575 |
uint64_t InsIdx = N->getConstantOperandVal(2); |
0 |
25575 |
uint64_t InsIdx = N->getConstantOperandVal(2); |
0 |
| 25576 |
|
--- |
25576 |
|
--- |
| 25577 |
// If inserting an UNDEF, just return the original vector. |
--- |
25577 |
// If inserting an UNDEF, just return the original vector. |
--- |
| 25578 |
if (N1.isUndef()) |
0 |
25578 |
if (N1.isUndef()) |
0 |
| 25579 |
return N0; |
0 |
25579 |
return N0; |
0 |
| 25580 |
|
--- |
25580 |
|
--- |
| 25581 |
// If this is an insert of an extracted vector into an undef vector, we can |
--- |
25581 |
// If this is an insert of an extracted vector into an undef vector, we can |
--- |
| 25582 |
// just use the input to the extract. |
--- |
25582 |
// just use the input to the extract. |
--- |
| 25583 |
if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && |
0 |
25583 |
if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && |
0 |
| 25584 |
N1.getOperand(1) == N2 && N1.getOperand(0).getValueType() == VT) |
0 |
25584 |
N1.getOperand(1) == N2 && N1.getOperand(0).getValueType() == VT) |
0 |
| 25585 |
return N1.getOperand(0); |
0 |
25585 |
return N1.getOperand(0); |
0 |
| 25586 |
|
--- |
25586 |
|
--- |
| 25587 |
// Simplify scalar inserts into an undef vector: |
--- |
25587 |
// Simplify scalar inserts into an undef vector: |
--- |
| 25588 |
// insert_subvector undef, (splat X), N2 -> splat X |
--- |
25588 |
// insert_subvector undef, (splat X), N2 -> splat X |
--- |
| 25589 |
if (N0.isUndef() && N1.getOpcode() == ISD::SPLAT_VECTOR) |
0 |
25589 |
if (N0.isUndef() && N1.getOpcode() == ISD::SPLAT_VECTOR) |
0 |
| 25590 |
return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, N1.getOperand(0)); |
0 |
25590 |
return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, N1.getOperand(0)); |
0 |
| 25591 |
|
--- |
25591 |
|
--- |
| 25592 |
// If we are inserting a bitcast value into an undef, with the same |
--- |
25592 |
// If we are inserting a bitcast value into an undef, with the same |
--- |
| 25593 |
// number of elements, just use the bitcast input of the extract. |
--- |
25593 |
// number of elements, just use the bitcast input of the extract. |
--- |
| 25594 |
// i.e. INSERT_SUBVECTOR UNDEF (BITCAST N1) N2 -> |
--- |
25594 |
// i.e. INSERT_SUBVECTOR UNDEF (BITCAST N1) N2 -> |
--- |
| 25595 |
// BITCAST (INSERT_SUBVECTOR UNDEF N1 N2) |
--- |
25595 |
// BITCAST (INSERT_SUBVECTOR UNDEF N1 N2) |
--- |
| 25596 |
if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST && |
0 |
25596 |
if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST && |
0 |
| 25597 |
N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR && |
0 |
25597 |
N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR && |
0 |
| 25598 |
N1.getOperand(0).getOperand(1) == N2 && |
0 |
25598 |
N1.getOperand(0).getOperand(1) == N2 && |
0 |
| 25599 |
N1.getOperand(0).getOperand(0).getValueType().getVectorElementCount() == |
0 |
25599 |
N1.getOperand(0).getOperand(0).getValueType().getVectorElementCount() == |
0 |
| 25600 |
VT.getVectorElementCount() && |
0 |
25600 |
VT.getVectorElementCount() && |
0 |
| 25601 |
N1.getOperand(0).getOperand(0).getValueType().getSizeInBits() == |
0 |
25601 |
N1.getOperand(0).getOperand(0).getValueType().getSizeInBits() == |
0 |
| 25602 |
VT.getSizeInBits()) { |
0 |
25602 |
VT.getSizeInBits()) { |
0 |
| 25603 |
return DAG.getBitcast(VT, N1.getOperand(0).getOperand(0)); |
0 |
25603 |
return DAG.getBitcast(VT, N1.getOperand(0).getOperand(0)); |
0 |
| 25604 |
} |
--- |
25604 |
} |
--- |
| 25605 |
|
--- |
25605 |
|
--- |
| 25606 |
// If both N1 and N2 are bitcast values on which insert_subvector |
--- |
25606 |
// If both N1 and N2 are bitcast values on which insert_subvector |
--- |
| 25607 |
// would makes sense, pull the bitcast through. |
--- |
25607 |
// would makes sense, pull the bitcast through. |
--- |
| 25608 |
// i.e. INSERT_SUBVECTOR (BITCAST N0) (BITCAST N1) N2 -> |
--- |
25608 |
// i.e. INSERT_SUBVECTOR (BITCAST N0) (BITCAST N1) N2 -> |
--- |
| 25609 |
// BITCAST (INSERT_SUBVECTOR N0 N1 N2) |
--- |
25609 |
// BITCAST (INSERT_SUBVECTOR N0 N1 N2) |
--- |
| 25610 |
if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) { |
0 |
25610 |
if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) { |
0 |
| 25611 |
SDValue CN0 = N0.getOperand(0); |
0 |
25611 |
SDValue CN0 = N0.getOperand(0); |
0 |
| 25612 |
SDValue CN1 = N1.getOperand(0); |
0 |
25612 |
SDValue CN1 = N1.getOperand(0); |
0 |
| 25613 |
EVT CN0VT = CN0.getValueType(); |
0 |
25613 |
EVT CN0VT = CN0.getValueType(); |
0 |
| 25614 |
EVT CN1VT = CN1.getValueType(); |
0 |
25614 |
EVT CN1VT = CN1.getValueType(); |
0 |
| 25615 |
if (CN0VT.isVector() && CN1VT.isVector() && |
0 |
25615 |
if (CN0VT.isVector() && CN1VT.isVector() && |
0 |
| 25616 |
CN0VT.getVectorElementType() == CN1VT.getVectorElementType() && |
0 |
25616 |
CN0VT.getVectorElementType() == CN1VT.getVectorElementType() && |
0 |
| 25617 |
CN0VT.getVectorElementCount() == VT.getVectorElementCount()) { |
0 |
25617 |
CN0VT.getVectorElementCount() == VT.getVectorElementCount()) { |
0 |
| 25618 |
SDValue NewINSERT = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), |
0 |
25618 |
SDValue NewINSERT = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), |
0 |
| 25619 |
CN0.getValueType(), CN0, CN1, N2); |
--- |
25619 |
CN0.getValueType(), CN0, CN1, N2); |
--- |
| 25620 |
return DAG.getBitcast(VT, NewINSERT); |
0 |
25620 |
return DAG.getBitcast(VT, NewINSERT); |
0 |
| 25621 |
} |
--- |
25621 |
} |
--- |
| 25622 |
} |
--- |
25622 |
} |
--- |
| 25623 |
|
--- |
25623 |
|
--- |
| 25624 |
// Combine INSERT_SUBVECTORs where we are inserting to the same index. |
--- |
25624 |
// Combine INSERT_SUBVECTORs where we are inserting to the same index. |
--- |
| 25625 |
// INSERT_SUBVECTOR( INSERT_SUBVECTOR( Vec, SubOld, Idx ), SubNew, Idx ) |
--- |
25625 |
// INSERT_SUBVECTOR( INSERT_SUBVECTOR( Vec, SubOld, Idx ), SubNew, Idx ) |
--- |
| 25626 |
// --> INSERT_SUBVECTOR( Vec, SubNew, Idx ) |
--- |
25626 |
// --> INSERT_SUBVECTOR( Vec, SubNew, Idx ) |
--- |
| 25627 |
if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && |
0 |
25627 |
if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && |
0 |
| 25628 |
N0.getOperand(1).getValueType() == N1.getValueType() && |
0 |
25628 |
N0.getOperand(1).getValueType() == N1.getValueType() && |
0 |
| 25629 |
N0.getOperand(2) == N2) |
0 |
25629 |
N0.getOperand(2) == N2) |
0 |
| 25630 |
return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0.getOperand(0), |
0 |
25630 |
return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0.getOperand(0), |
0 |
| 25631 |
N1, N2); |
0 |
25631 |
N1, N2); |
0 |
| 25632 |
|
--- |
25632 |
|
--- |
| 25633 |
// Eliminate an intermediate insert into an undef vector: |
--- |
25633 |
// Eliminate an intermediate insert into an undef vector: |
--- |
| 25634 |
// insert_subvector undef, (insert_subvector undef, X, 0), N2 --> |
--- |
25634 |
// insert_subvector undef, (insert_subvector undef, X, 0), N2 --> |
--- |
| 25635 |
// insert_subvector undef, X, N2 |
--- |
25635 |
// insert_subvector undef, X, N2 |
--- |
| 25636 |
if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && |
0 |
25636 |
if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && |
0 |
| 25637 |
N1.getOperand(0).isUndef() && isNullConstant(N1.getOperand(2))) |
0 |
25637 |
N1.getOperand(0).isUndef() && isNullConstant(N1.getOperand(2))) |
0 |
| 25638 |
return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0, |
0 |
25638 |
return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0, |
0 |
| 25639 |
N1.getOperand(1), N2); |
0 |
25639 |
N1.getOperand(1), N2); |
0 |
| 25640 |
|
--- |
25640 |
|
--- |
| 25641 |
// Push subvector bitcasts to the output, adjusting the index as we go. |
--- |
25641 |
// Push subvector bitcasts to the output, adjusting the index as we go. |
--- |
| 25642 |
// insert_subvector(bitcast(v), bitcast(s), c1) |
--- |
25642 |
// insert_subvector(bitcast(v), bitcast(s), c1) |
--- |
| 25643 |
// -> bitcast(insert_subvector(v, s, c2)) |
--- |
25643 |
// -> bitcast(insert_subvector(v, s, c2)) |
--- |
| 25644 |
if ((N0.isUndef() || N0.getOpcode() == ISD::BITCAST) && |
0 |
25644 |
if ((N0.isUndef() || N0.getOpcode() == ISD::BITCAST) && |
0 |
| 25645 |
N1.getOpcode() == ISD::BITCAST) { |
0 |
25645 |
N1.getOpcode() == ISD::BITCAST) { |
0 |
| 25646 |
SDValue N0Src = peekThroughBitcasts(N0); |
0 |
25646 |
SDValue N0Src = peekThroughBitcasts(N0); |
0 |
| 25647 |
SDValue N1Src = peekThroughBitcasts(N1); |
0 |
25647 |
SDValue N1Src = peekThroughBitcasts(N1); |
0 |
| 25648 |
EVT N0SrcSVT = N0Src.getValueType().getScalarType(); |
0 |
25648 |
EVT N0SrcSVT = N0Src.getValueType().getScalarType(); |
0 |
| 25649 |
EVT N1SrcSVT = N1Src.getValueType().getScalarType(); |
0 |
25649 |
EVT N1SrcSVT = N1Src.getValueType().getScalarType(); |
0 |
| 25650 |
if ((N0.isUndef() || N0SrcSVT == N1SrcSVT) && |
0 |
25650 |
if ((N0.isUndef() || N0SrcSVT == N1SrcSVT) && |
0 |
| 25651 |
N0Src.getValueType().isVector() && N1Src.getValueType().isVector()) { |
0 |
25651 |
N0Src.getValueType().isVector() && N1Src.getValueType().isVector()) { |
0 |
| 25652 |
EVT NewVT; |
0 |
25652 |
EVT NewVT; |
0 |
| 25653 |
SDLoc DL(N); |
0 |
25653 |
SDLoc DL(N); |
0 |
| 25654 |
SDValue NewIdx; |
0 |
25654 |
SDValue NewIdx; |
0 |
| 25655 |
LLVMContext &Ctx = *DAG.getContext(); |
0 |
25655 |
LLVMContext &Ctx = *DAG.getContext(); |
0 |
| 25656 |
ElementCount NumElts = VT.getVectorElementCount(); |
0 |
25656 |
ElementCount NumElts = VT.getVectorElementCount(); |
0 |
| 25657 |
unsigned EltSizeInBits = VT.getScalarSizeInBits(); |
0 |
25657 |
unsigned EltSizeInBits = VT.getScalarSizeInBits(); |
0 |
| 25658 |
if ((EltSizeInBits % N1SrcSVT.getSizeInBits()) == 0) { |
0 |
25658 |
if ((EltSizeInBits % N1SrcSVT.getSizeInBits()) == 0) { |
0 |
| 25659 |
unsigned Scale = EltSizeInBits / N1SrcSVT.getSizeInBits(); |
0 |
25659 |
unsigned Scale = EltSizeInBits / N1SrcSVT.getSizeInBits(); |
0 |
| 25660 |
NewVT = EVT::getVectorVT(Ctx, N1SrcSVT, NumElts * Scale); |
0 |
25660 |
NewVT = EVT::getVectorVT(Ctx, N1SrcSVT, NumElts * Scale); |
0 |
| 25661 |
NewIdx = DAG.getVectorIdxConstant(InsIdx * Scale, DL); |
0 |
25661 |
NewIdx = DAG.getVectorIdxConstant(InsIdx * Scale, DL); |
0 |
| 25662 |
} else if ((N1SrcSVT.getSizeInBits() % EltSizeInBits) == 0) { |
0 |
25662 |
} else if ((N1SrcSVT.getSizeInBits() % EltSizeInBits) == 0) { |
0 |
| 25663 |
unsigned Scale = N1SrcSVT.getSizeInBits() / EltSizeInBits; |
0 |
25663 |
unsigned Scale = N1SrcSVT.getSizeInBits() / EltSizeInBits; |
0 |
| 25664 |
if (NumElts.isKnownMultipleOf(Scale) && (InsIdx % Scale) == 0) { |
0 |
25664 |
if (NumElts.isKnownMultipleOf(Scale) && (InsIdx % Scale) == 0) { |
0 |
| 25665 |
NewVT = EVT::getVectorVT(Ctx, N1SrcSVT, |
0 |
25665 |
NewVT = EVT::getVectorVT(Ctx, N1SrcSVT, |
0 |
| 25666 |
NumElts.divideCoefficientBy(Scale)); |
--- |
25666 |
NumElts.divideCoefficientBy(Scale)); |
--- |
| 25667 |
NewIdx = DAG.getVectorIdxConstant(InsIdx / Scale, DL); |
0 |
25667 |
NewIdx = DAG.getVectorIdxConstant(InsIdx / Scale, DL); |
0 |
| 25668 |
} |
--- |
25668 |
} |
--- |
| 25669 |
} |
--- |
25669 |
} |
--- |
| 25670 |
if (NewIdx && hasOperation(ISD::INSERT_SUBVECTOR, NewVT)) { |
0 |
25670 |
if (NewIdx && hasOperation(ISD::INSERT_SUBVECTOR, NewVT)) { |
0 |
| 25671 |
SDValue Res = DAG.getBitcast(NewVT, N0Src); |
0 |
25671 |
SDValue Res = DAG.getBitcast(NewVT, N0Src); |
0 |
| 25672 |
Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, NewVT, Res, N1Src, NewIdx); |
0 |
25672 |
Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, NewVT, Res, N1Src, NewIdx); |
0 |
| 25673 |
return DAG.getBitcast(VT, Res); |
0 |
25673 |
return DAG.getBitcast(VT, Res); |
0 |
| 25674 |
} |
--- |
25674 |
} |
--- |
| 25675 |
} |
0 |
25675 |
} |
0 |
| 25676 |
} |
--- |
25676 |
} |
--- |
| 25677 |
|
--- |
25677 |
|
--- |
| 25678 |
// Canonicalize insert_subvector dag nodes. |
--- |
25678 |
// Canonicalize insert_subvector dag nodes. |
--- |
| 25679 |
// Example: |
--- |
25679 |
// Example: |
--- |
| 25680 |
// (insert_subvector (insert_subvector A, Idx0), Idx1) |
--- |
25680 |
// (insert_subvector (insert_subvector A, Idx0), Idx1) |
--- |
| 25681 |
// -> (insert_subvector (insert_subvector A, Idx1), Idx0) |
--- |
25681 |
// -> (insert_subvector (insert_subvector A, Idx1), Idx0) |
--- |
| 25682 |
if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() && |
0 |
25682 |
if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() && |
0 |
| 25683 |
N1.getValueType() == N0.getOperand(1).getValueType()) { |
0 |
25683 |
N1.getValueType() == N0.getOperand(1).getValueType()) { |
0 |
| 25684 |
unsigned OtherIdx = N0.getConstantOperandVal(2); |
0 |
25684 |
unsigned OtherIdx = N0.getConstantOperandVal(2); |
0 |
| 25685 |
if (InsIdx < OtherIdx) { |
0 |
25685 |
if (InsIdx < OtherIdx) { |
0 |
| 25686 |
// Swap nodes. |
--- |
25686 |
// Swap nodes. |
--- |
| 25687 |
SDValue NewOp = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, |
0 |
25687 |
SDValue NewOp = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, |
0 |
| 25688 |
N0.getOperand(0), N1, N2); |
0 |
25688 |
N0.getOperand(0), N1, N2); |
0 |
| 25689 |
AddToWorklist(NewOp.getNode()); |
0 |
25689 |
AddToWorklist(NewOp.getNode()); |
0 |
| 25690 |
return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N0.getNode()), |
0 |
25690 |
return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N0.getNode()), |
0 |
| 25691 |
VT, NewOp, N0.getOperand(1), N0.getOperand(2)); |
0 |
25691 |
VT, NewOp, N0.getOperand(1), N0.getOperand(2)); |
0 |
| 25692 |
} |
--- |
25692 |
} |
--- |
| 25693 |
} |
--- |
25693 |
} |
--- |
| 25694 |
|
--- |
25694 |
|
--- |
| 25695 |
// If the input vector is a concatenation, and the insert replaces |
--- |
25695 |
// If the input vector is a concatenation, and the insert replaces |
--- |
| 25696 |
// one of the pieces, we can optimize into a single concat_vectors. |
--- |
25696 |
// one of the pieces, we can optimize into a single concat_vectors. |
--- |
| 25697 |
if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() && |
0 |
25697 |
if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() && |
0 |
| 25698 |
N0.getOperand(0).getValueType() == N1.getValueType() && |
0 |
25698 |
N0.getOperand(0).getValueType() == N1.getValueType() && |
0 |
| 25699 |
N0.getOperand(0).getValueType().isScalableVector() == |
0 |
25699 |
N0.getOperand(0).getValueType().isScalableVector() == |
0 |
| 25700 |
N1.getValueType().isScalableVector()) { |
0 |
25700 |
N1.getValueType().isScalableVector()) { |
0 |
| 25701 |
unsigned Factor = N1.getValueType().getVectorMinNumElements(); |
0 |
25701 |
unsigned Factor = N1.getValueType().getVectorMinNumElements(); |
0 |
| 25702 |
SmallVector Ops(N0->op_begin(), N0->op_end()); |
0 |
25702 |
SmallVector Ops(N0->op_begin(), N0->op_end()); |
0 |
| 25703 |
Ops[InsIdx / Factor] = N1; |
0 |
25703 |
Ops[InsIdx / Factor] = N1; |
0 |
| 25704 |
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops); |
0 |
25704 |
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops); |
0 |
| 25705 |
} |
0 |
25705 |
} |
0 |
| 25706 |
|
--- |
25706 |
|
--- |
| 25707 |
// Simplify source operands based on insertion. |
--- |
25707 |
// Simplify source operands based on insertion. |
--- |
| 25708 |
if (SimplifyDemandedVectorElts(SDValue(N, 0))) |
0 |
25708 |
if (SimplifyDemandedVectorElts(SDValue(N, 0))) |
0 |
| 25709 |
return SDValue(N, 0); |
0 |
25709 |
return SDValue(N, 0); |
0 |
| 25710 |
|
--- |
25710 |
|
--- |
| 25711 |
return SDValue(); |
0 |
25711 |
return SDValue(); |
0 |
| 25712 |
} |
--- |
25712 |
} |
--- |
| 25713 |
|
--- |
25713 |
|
--- |
| 25714 |
SDValue DAGCombiner::visitFP_TO_FP16(SDNode *N) { |
0 |
25714 |
SDValue DAGCombiner::visitFP_TO_FP16(SDNode *N) { |
0 |
| 25715 |
SDValue N0 = N->getOperand(0); |
0 |
25715 |
SDValue N0 = N->getOperand(0); |
0 |
| 25716 |
|
--- |
25716 |
|
--- |
| 25717 |
// fold (fp_to_fp16 (fp16_to_fp op)) -> op |
--- |
25717 |
// fold (fp_to_fp16 (fp16_to_fp op)) -> op |
--- |
| 25718 |
if (N0->getOpcode() == ISD::FP16_TO_FP) |
0 |
25718 |
if (N0->getOpcode() == ISD::FP16_TO_FP) |
0 |
| 25719 |
return N0->getOperand(0); |
0 |
25719 |
return N0->getOperand(0); |
0 |
| 25720 |
|
--- |
25720 |
|
--- |
| 25721 |
return SDValue(); |
0 |
25721 |
return SDValue(); |
0 |
| 25722 |
} |
--- |
25722 |
} |
--- |
| 25723 |
|
--- |
25723 |
|
--- |
| 25724 |
SDValue DAGCombiner::visitFP16_TO_FP(SDNode *N) { |
0 |
25724 |
SDValue DAGCombiner::visitFP16_TO_FP(SDNode *N) { |
0 |
| 25725 |
SDValue N0 = N->getOperand(0); |
0 |
25725 |
SDValue N0 = N->getOperand(0); |
0 |
| 25726 |
|
--- |
25726 |
|
--- |
| 25727 |
// fold fp16_to_fp(op & 0xffff) -> fp16_to_fp(op) |
--- |
25727 |
// fold fp16_to_fp(op & 0xffff) -> fp16_to_fp(op) |
--- |
| 25728 |
if (!TLI.shouldKeepZExtForFP16Conv() && N0->getOpcode() == ISD::AND) { |
0 |
25728 |
if (!TLI.shouldKeepZExtForFP16Conv() && N0->getOpcode() == ISD::AND) { |
0 |
| 25729 |
ConstantSDNode *AndConst = getAsNonOpaqueConstant(N0.getOperand(1)); |
0 |
25729 |
ConstantSDNode *AndConst = getAsNonOpaqueConstant(N0.getOperand(1)); |
0 |
| 25730 |
if (AndConst && AndConst->getAPIntValue() == 0xffff) { |
0 |
25730 |
if (AndConst && AndConst->getAPIntValue() == 0xffff) { |
0 |
| 25731 |
return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), N->getValueType(0), |
0 |
25731 |
return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), N->getValueType(0), |
0 |
| 25732 |
N0.getOperand(0)); |
0 |
25732 |
N0.getOperand(0)); |
0 |
| 25733 |
} |
--- |
25733 |
} |
--- |
| 25734 |
} |
--- |
25734 |
} |
--- |
| 25735 |
|
--- |
25735 |
|
--- |
| 25736 |
return SDValue(); |
0 |
25736 |
return SDValue(); |
0 |
| 25737 |
} |
--- |
25737 |
} |
--- |
| 25738 |
|
--- |
25738 |
|
--- |
| 25739 |
SDValue DAGCombiner::visitFP_TO_BF16(SDNode *N) { |
0 |
25739 |
SDValue DAGCombiner::visitFP_TO_BF16(SDNode *N) { |
0 |
| 25740 |
SDValue N0 = N->getOperand(0); |
0 |
25740 |
SDValue N0 = N->getOperand(0); |
0 |
| 25741 |
|
--- |
25741 |
|
--- |
| 25742 |
// fold (fp_to_bf16 (bf16_to_fp op)) -> op |
--- |
25742 |
// fold (fp_to_bf16 (bf16_to_fp op)) -> op |
--- |
| 25743 |
if (N0->getOpcode() == ISD::BF16_TO_FP) |
0 |
25743 |
if (N0->getOpcode() == ISD::BF16_TO_FP) |
0 |
| 25744 |
return N0->getOperand(0); |
0 |
25744 |
return N0->getOperand(0); |
0 |
| 25745 |
|
--- |
25745 |
|
--- |
| 25746 |
return SDValue(); |
0 |
25746 |
return SDValue(); |
0 |
| 25747 |
} |
--- |
25747 |
} |
--- |
| 25748 |
|
--- |
25748 |
|
--- |
| 25749 |
SDValue DAGCombiner::visitVECREDUCE(SDNode *N) { |
0 |
25749 |
SDValue DAGCombiner::visitVECREDUCE(SDNode *N) { |
0 |
| 25750 |
SDValue N0 = N->getOperand(0); |
0 |
25750 |
SDValue N0 = N->getOperand(0); |
0 |
| 25751 |
EVT VT = N0.getValueType(); |
0 |
25751 |
EVT VT = N0.getValueType(); |
0 |
| 25752 |
unsigned Opcode = N->getOpcode(); |
0 |
25752 |
unsigned Opcode = N->getOpcode(); |
0 |
| 25753 |
|
--- |
25753 |
|
--- |
| 25754 |
// VECREDUCE over 1-element vector is just an extract. |
--- |
25754 |
// VECREDUCE over 1-element vector is just an extract. |
--- |
| 25755 |
if (VT.getVectorElementCount().isScalar()) { |
0 |
25755 |
if (VT.getVectorElementCount().isScalar()) { |
0 |
| 25756 |
SDLoc dl(N); |
0 |
25756 |
SDLoc dl(N); |
0 |
| 25757 |
SDValue Res = |
--- |
25757 |
SDValue Res = |
--- |
| 25758 |
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getVectorElementType(), N0, |
0 |
25758 |
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getVectorElementType(), N0, |
0 |
| 25759 |
DAG.getVectorIdxConstant(0, dl)); |
0 |
25759 |
DAG.getVectorIdxConstant(0, dl)); |
0 |
| 25760 |
if (Res.getValueType() != N->getValueType(0)) |
0 |
25760 |
if (Res.getValueType() != N->getValueType(0)) |
0 |
| 25761 |
Res = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Res); |
0 |
25761 |
Res = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Res); |
0 |
| 25762 |
return Res; |
0 |
25762 |
return Res; |
0 |
| 25763 |
} |
0 |
25763 |
} |
0 |
| 25764 |
|
--- |
25764 |
|
--- |
| 25765 |
// On an boolean vector an and/or reduction is the same as a umin/umax |
--- |
25765 |
// On an boolean vector an and/or reduction is the same as a umin/umax |
--- |
| 25766 |
// reduction. Convert them if the latter is legal while the former isn't. |
--- |
25766 |
// reduction. Convert them if the latter is legal while the former isn't. |
--- |
| 25767 |
if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) { |
0 |
25767 |
if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) { |
0 |
| 25768 |
unsigned NewOpcode = Opcode == ISD::VECREDUCE_AND |
0 |
25768 |
unsigned NewOpcode = Opcode == ISD::VECREDUCE_AND |
0 |
| 25769 |
? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX; |
0 |
25769 |
? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX; |
0 |
| 25770 |
if (!TLI.isOperationLegalOrCustom(Opcode, VT) && |
0 |
25770 |
if (!TLI.isOperationLegalOrCustom(Opcode, VT) && |
0 |
| 25771 |
TLI.isOperationLegalOrCustom(NewOpcode, VT) && |
0 |
25771 |
TLI.isOperationLegalOrCustom(NewOpcode, VT) && |
0 |
| 25772 |
DAG.ComputeNumSignBits(N0) == VT.getScalarSizeInBits()) |
0 |
25772 |
DAG.ComputeNumSignBits(N0) == VT.getScalarSizeInBits()) |
0 |
| 25773 |
return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), N0); |
0 |
25773 |
return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), N0); |
0 |
| 25774 |
} |
--- |
25774 |
} |
--- |
| 25775 |
|
--- |
25775 |
|
--- |
| 25776 |
// vecreduce_or(insert_subvector(zero or undef, val)) -> vecreduce_or(val) |
--- |
25776 |
// vecreduce_or(insert_subvector(zero or undef, val)) -> vecreduce_or(val) |
--- |
| 25777 |
// vecreduce_and(insert_subvector(ones or undef, val)) -> vecreduce_and(val) |
--- |
25777 |
// vecreduce_and(insert_subvector(ones or undef, val)) -> vecreduce_and(val) |
--- |
| 25778 |
if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && |
0 |
25778 |
if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && |
0 |
| 25779 |
TLI.isTypeLegal(N0.getOperand(1).getValueType())) { |
0 |
25779 |
TLI.isTypeLegal(N0.getOperand(1).getValueType())) { |
0 |
| 25780 |
SDValue Vec = N0.getOperand(0); |
0 |
25780 |
SDValue Vec = N0.getOperand(0); |
0 |
| 25781 |
SDValue Subvec = N0.getOperand(1); |
0 |
25781 |
SDValue Subvec = N0.getOperand(1); |
0 |
| 25782 |
if ((Opcode == ISD::VECREDUCE_OR && |
0 |
25782 |
if ((Opcode == ISD::VECREDUCE_OR && |
0 |
| 25783 |
(N0.getOperand(0).isUndef() || isNullOrNullSplat(Vec))) || |
0 |
25783 |
(N0.getOperand(0).isUndef() || isNullOrNullSplat(Vec))) || |
0 |
| 25784 |
(Opcode == ISD::VECREDUCE_AND && |
0 |
25784 |
(Opcode == ISD::VECREDUCE_AND && |
0 |
| 25785 |
(N0.getOperand(0).isUndef() || isAllOnesOrAllOnesSplat(Vec)))) |
0 |
25785 |
(N0.getOperand(0).isUndef() || isAllOnesOrAllOnesSplat(Vec)))) |
0 |
| 25786 |
return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), Subvec); |
0 |
25786 |
return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), Subvec); |
0 |
| 25787 |
} |
--- |
25787 |
} |
--- |
| 25788 |
|
--- |
25788 |
|
--- |
| 25789 |
return SDValue(); |
0 |
25789 |
return SDValue(); |
0 |
| 25790 |
} |
--- |
25790 |
} |
--- |
| 25791 |
|
--- |
25791 |
|
--- |
| 25792 |
SDValue DAGCombiner::visitVP_FSUB(SDNode *N) { |
0 |
25792 |
SDValue DAGCombiner::visitVP_FSUB(SDNode *N) { |
0 |
| 25793 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
25793 |
SelectionDAG::FlagInserter FlagsInserter(DAG, N); |
0 |
| 25794 |
|
--- |
25794 |
|
--- |
| 25795 |
// FSUB -> FMA combines: |
--- |
25795 |
// FSUB -> FMA combines: |
--- |
| 25796 |
if (SDValue Fused = visitFSUBForFMACombine(N)) { |
0 |
25796 |
if (SDValue Fused = visitFSUBForFMACombine(N)) { |
0 |
| 25797 |
AddToWorklist(Fused.getNode()); |
0 |
25797 |
AddToWorklist(Fused.getNode()); |
0 |
| 25798 |
return Fused; |
0 |
25798 |
return Fused; |
0 |
| 25799 |
} |
--- |
25799 |
} |
--- |
| 25800 |
return SDValue(); |
0 |
25800 |
return SDValue(); |
0 |
| 25801 |
} |
0 |
25801 |
} |
0 |
| 25802 |
|
--- |
25802 |
|
--- |
| 25803 |
SDValue DAGCombiner::visitVPOp(SDNode *N) { |
0 |
25803 |
SDValue DAGCombiner::visitVPOp(SDNode *N) { |
0 |
| 25804 |
|
--- |
25804 |
|
--- |
| 25805 |
if (N->getOpcode() == ISD::VP_GATHER) |
0 |
25805 |
if (N->getOpcode() == ISD::VP_GATHER) |
0 |
| 25806 |
if (SDValue SD = visitVPGATHER(N)) |
0 |
25806 |
if (SDValue SD = visitVPGATHER(N)) |
0 |
| 25807 |
return SD; |
0 |
25807 |
return SD; |
0 |
| 25808 |
|
--- |
25808 |
|
--- |
| 25809 |
if (N->getOpcode() == ISD::VP_SCATTER) |
0 |
25809 |
if (N->getOpcode() == ISD::VP_SCATTER) |
0 |
| 25810 |
if (SDValue SD = visitVPSCATTER(N)) |
0 |
25810 |
if (SDValue SD = visitVPSCATTER(N)) |
0 |
| 25811 |
return SD; |
0 |
25811 |
return SD; |
0 |
| 25812 |
|
--- |
25812 |
|
--- |
| 25813 |
// VP operations in which all vector elements are disabled - either by |
--- |
25813 |
// VP operations in which all vector elements are disabled - either by |
--- |
| 25814 |
// determining that the mask is all false or that the EVL is 0 - can be |
--- |
25814 |
// determining that the mask is all false or that the EVL is 0 - can be |
--- |
| 25815 |
// eliminated. |
--- |
25815 |
// eliminated. |
--- |
| 25816 |
bool AreAllEltsDisabled = false; |
0 |
25816 |
bool AreAllEltsDisabled = false; |
0 |
| 25817 |
if (auto EVLIdx = ISD::getVPExplicitVectorLengthIdx(N->getOpcode())) |
0 |
25817 |
if (auto EVLIdx = ISD::getVPExplicitVectorLengthIdx(N->getOpcode())) |
0 |
| 25818 |
AreAllEltsDisabled |= isNullConstant(N->getOperand(*EVLIdx)); |
0 |
25818 |
AreAllEltsDisabled |= isNullConstant(N->getOperand(*EVLIdx)); |
0 |
| 25819 |
if (auto MaskIdx = ISD::getVPMaskIdx(N->getOpcode())) |
0 |
25819 |
if (auto MaskIdx = ISD::getVPMaskIdx(N->getOpcode())) |
0 |
| 25820 |
AreAllEltsDisabled |= |
0 |
25820 |
AreAllEltsDisabled |= |
0 |
| 25821 |
ISD::isConstantSplatVectorAllZeros(N->getOperand(*MaskIdx).getNode()); |
0 |
25821 |
ISD::isConstantSplatVectorAllZeros(N->getOperand(*MaskIdx).getNode()); |
0 |
| 25822 |
|
--- |
25822 |
|
--- |
| 25823 |
// This is the only generic VP combine we support for now. |
--- |
25823 |
// This is the only generic VP combine we support for now. |
--- |
| 25824 |
if (!AreAllEltsDisabled) { |
0 |
25824 |
if (!AreAllEltsDisabled) { |
0 |
| 25825 |
switch (N->getOpcode()) { |
0 |
25825 |
switch (N->getOpcode()) { |
0 |
| 25826 |
case ISD::VP_FADD: |
0 |
25826 |
case ISD::VP_FADD: |
0 |
| 25827 |
return visitVP_FADD(N); |
0 |
25827 |
return visitVP_FADD(N); |
0 |
| 25828 |
case ISD::VP_FSUB: |
0 |
25828 |
case ISD::VP_FSUB: |
0 |
| 25829 |
return visitVP_FSUB(N); |
0 |
25829 |
return visitVP_FSUB(N); |
0 |
| 25830 |
case ISD::VP_FMA: |
0 |
25830 |
case ISD::VP_FMA: |
0 |
| 25831 |
return visitFMA(N); |
0 |
25831 |
return visitFMA(N); |
0 |
| 25832 |
} |
--- |
25832 |
} |
--- |
| 25833 |
return SDValue(); |
0 |
25833 |
return SDValue(); |
0 |
| 25834 |
} |
--- |
25834 |
} |
--- |
| 25835 |
|
--- |
25835 |
|
--- |
| 25836 |
// Binary operations can be replaced by UNDEF. |
--- |
25836 |
// Binary operations can be replaced by UNDEF. |
--- |
| 25837 |
if (ISD::isVPBinaryOp(N->getOpcode())) |
0 |
25837 |
if (ISD::isVPBinaryOp(N->getOpcode())) |
0 |
| 25838 |
return DAG.getUNDEF(N->getValueType(0)); |
0 |
25838 |
return DAG.getUNDEF(N->getValueType(0)); |
0 |
| 25839 |
|
--- |
25839 |
|
--- |
| 25840 |
// VP Memory operations can be replaced by either the chain (stores) or the |
--- |
25840 |
// VP Memory operations can be replaced by either the chain (stores) or the |
--- |
| 25841 |
// chain + undef (loads). |
--- |
25841 |
// chain + undef (loads). |
--- |
| 25842 |
if (const auto *MemSD = dyn_cast(N)) { |
0 |
25842 |
if (const auto *MemSD = dyn_cast(N)) { |
0 |
| 25843 |
if (MemSD->writeMem()) |
0 |
25843 |
if (MemSD->writeMem()) |
0 |
| 25844 |
return MemSD->getChain(); |
0 |
25844 |
return MemSD->getChain(); |
0 |
| 25845 |
return CombineTo(N, DAG.getUNDEF(N->getValueType(0)), MemSD->getChain()); |
0 |
25845 |
return CombineTo(N, DAG.getUNDEF(N->getValueType(0)), MemSD->getChain()); |
0 |
| 25846 |
} |
--- |
25846 |
} |
--- |
| 25847 |
|
--- |
25847 |
|
--- |
| 25848 |
// Reduction operations return the start operand when no elements are active. |
--- |
25848 |
// Reduction operations return the start operand when no elements are active. |
--- |
| 25849 |
if (ISD::isVPReduction(N->getOpcode())) |
0 |
25849 |
if (ISD::isVPReduction(N->getOpcode())) |
0 |
| 25850 |
return N->getOperand(0); |
0 |
25850 |
return N->getOperand(0); |
0 |
| 25851 |
|
--- |
25851 |
|
--- |
| 25852 |
return SDValue(); |
0 |
25852 |
return SDValue(); |
0 |
| 25853 |
} |
--- |
25853 |
} |
--- |
| 25854 |
|
--- |
25854 |
|
--- |
| 25855 |
SDValue DAGCombiner::visitGET_FPENV_MEM(SDNode *N) { |
0 |
25855 |
SDValue DAGCombiner::visitGET_FPENV_MEM(SDNode *N) { |
0 |
| 25856 |
SDValue Chain = N->getOperand(0); |
0 |
25856 |
SDValue Chain = N->getOperand(0); |
0 |
| 25857 |
SDValue Ptr = N->getOperand(1); |
0 |
25857 |
SDValue Ptr = N->getOperand(1); |
0 |
| 25858 |
EVT MemVT = cast(N)->getMemoryVT(); |
0 |
25858 |
EVT MemVT = cast(N)->getMemoryVT(); |
0 |
| 25859 |
|
--- |
25859 |
|
--- |
| 25860 |
// Check if the memory, where FP state is written to, is used only in a single |
--- |
25860 |
// Check if the memory, where FP state is written to, is used only in a single |
--- |
| 25861 |
// load operation. |
--- |
25861 |
// load operation. |
--- |
| 25862 |
LoadSDNode *LdNode = nullptr; |
0 |
25862 |
LoadSDNode *LdNode = nullptr; |
0 |
| 25863 |
for (auto *U : Ptr->uses()) { |
0 |
25863 |
for (auto *U : Ptr->uses()) { |
0 |
| 25864 |
if (U == N) |
0 |
25864 |
if (U == N) |
0 |
| 25865 |
continue; |
0 |
25865 |
continue; |
0 |
| 25866 |
if (auto *Ld = dyn_cast(U)) { |
0 |
25866 |
if (auto *Ld = dyn_cast(U)) { |
0 |
| 25867 |
if (LdNode && LdNode != Ld) |
0 |
25867 |
if (LdNode && LdNode != Ld) |
0 |
| 25868 |
return SDValue(); |
0 |
25868 |
return SDValue(); |
0 |
| 25869 |
LdNode = Ld; |
0 |
25869 |
LdNode = Ld; |
0 |
| 25870 |
continue; |
0 |
25870 |
continue; |
0 |
| 25871 |
} |
--- |
25871 |
} |
--- |
| 25872 |
return SDValue(); |
0 |
25872 |
return SDValue(); |
0 |
| 25873 |
} |
--- |
25873 |
} |
--- |
| 25874 |
if (!LdNode || !LdNode->isSimple() || LdNode->isIndexed() || |
0 |
25874 |
if (!LdNode || !LdNode->isSimple() || LdNode->isIndexed() || |
0 |
| 25875 |
!LdNode->getOffset().isUndef() || LdNode->getMemoryVT() != MemVT || |
0 |
25875 |
!LdNode->getOffset().isUndef() || LdNode->getMemoryVT() != MemVT || |
0 |
| 25876 |
!LdNode->getChain().reachesChainWithoutSideEffects(SDValue(N, 0))) |
0 |
25876 |
!LdNode->getChain().reachesChainWithoutSideEffects(SDValue(N, 0))) |
0 |
| 25877 |
return SDValue(); |
0 |
25877 |
return SDValue(); |
0 |
| 25878 |
|
--- |
25878 |
|
--- |
| 25879 |
// Check if the loaded value is used only in a store operation. |
--- |
25879 |
// Check if the loaded value is used only in a store operation. |
--- |
| 25880 |
StoreSDNode *StNode = nullptr; |
0 |
25880 |
StoreSDNode *StNode = nullptr; |
0 |
| 25881 |
for (auto I = LdNode->use_begin(), E = LdNode->use_end(); I != E; ++I) { |
0 |
25881 |
for (auto I = LdNode->use_begin(), E = LdNode->use_end(); I != E; ++I) { |
0 |
| 25882 |
SDUse &U = I.getUse(); |
0 |
25882 |
SDUse &U = I.getUse(); |
0 |
| 25883 |
if (U.getResNo() == 0) { |
0 |
25883 |
if (U.getResNo() == 0) { |
0 |
| 25884 |
if (auto *St = dyn_cast(U.getUser())) { |
0 |
25884 |
if (auto *St = dyn_cast(U.getUser())) { |
0 |
| 25885 |
if (StNode) |
0 |
25885 |
if (StNode) |
0 |
| 25886 |
return SDValue(); |
0 |
25886 |
return SDValue(); |
0 |
| 25887 |
StNode = St; |
0 |
25887 |
StNode = St; |
0 |
| 25888 |
} else { |
--- |
25888 |
} else { |
--- |
| 25889 |
return SDValue(); |
0 |
25889 |
return SDValue(); |
0 |
| 25890 |
} |
--- |
25890 |
} |
--- |
| 25891 |
} |
--- |
25891 |
} |
--- |
| 25892 |
} |
--- |
25892 |
} |
--- |
| 25893 |
if (!StNode || !StNode->isSimple() || StNode->isIndexed() || |
0 |
25893 |
if (!StNode || !StNode->isSimple() || StNode->isIndexed() || |
0 |
| 25894 |
!StNode->getOffset().isUndef() || StNode->getMemoryVT() != MemVT || |
0 |
25894 |
!StNode->getOffset().isUndef() || StNode->getMemoryVT() != MemVT || |
0 |
| 25895 |
!StNode->getChain().reachesChainWithoutSideEffects(SDValue(LdNode, 1))) |
0 |
25895 |
!StNode->getChain().reachesChainWithoutSideEffects(SDValue(LdNode, 1))) |
0 |
| 25896 |
return SDValue(); |
0 |
25896 |
return SDValue(); |
0 |
| 25897 |
|
--- |
25897 |
|
--- |
| 25898 |
// Create new node GET_FPENV_MEM, which uses the store address to write FP |
--- |
25898 |
// Create new node GET_FPENV_MEM, which uses the store address to write FP |
--- |
| 25899 |
// environment. |
--- |
25899 |
// environment. |
--- |
| 25900 |
SDValue Res = DAG.getGetFPEnv(Chain, SDLoc(N), StNode->getBasePtr(), MemVT, |
0 |
25900 |
SDValue Res = DAG.getGetFPEnv(Chain, SDLoc(N), StNode->getBasePtr(), MemVT, |
0 |
| 25901 |
StNode->getMemOperand()); |
--- |
25901 |
StNode->getMemOperand()); |
--- |
| 25902 |
CombineTo(StNode, Res, false); |
0 |
25902 |
CombineTo(StNode, Res, false); |
0 |
| 25903 |
return Res; |
0 |
25903 |
return Res; |
0 |
| 25904 |
} |
--- |
25904 |
} |
--- |
| 25905 |
|
--- |
25905 |
|
--- |
| 25906 |
SDValue DAGCombiner::visitSET_FPENV_MEM(SDNode *N) { |
0 |
25906 |
SDValue DAGCombiner::visitSET_FPENV_MEM(SDNode *N) { |
0 |
| 25907 |
SDValue Chain = N->getOperand(0); |
0 |
25907 |
SDValue Chain = N->getOperand(0); |
0 |
| 25908 |
SDValue Ptr = N->getOperand(1); |
0 |
25908 |
SDValue Ptr = N->getOperand(1); |
0 |
| 25909 |
EVT MemVT = cast(N)->getMemoryVT(); |
0 |
25909 |
EVT MemVT = cast(N)->getMemoryVT(); |
0 |
| 25910 |
|
--- |
25910 |
|
--- |
| 25911 |
// Check if the address of FP state is used also in a store operation only. |
--- |
25911 |
// Check if the address of FP state is used also in a store operation only. |
--- |
| 25912 |
StoreSDNode *StNode = nullptr; |
0 |
25912 |
StoreSDNode *StNode = nullptr; |
0 |
| 25913 |
for (auto *U : Ptr->uses()) { |
0 |
25913 |
for (auto *U : Ptr->uses()) { |
0 |
| 25914 |
if (U == N) |
0 |
25914 |
if (U == N) |
0 |
| 25915 |
continue; |
0 |
25915 |
continue; |
0 |
| 25916 |
if (auto *St = dyn_cast(U)) { |
0 |
25916 |
if (auto *St = dyn_cast(U)) { |
0 |
| 25917 |
if (StNode && StNode != St) |
0 |
25917 |
if (StNode && StNode != St) |
0 |
| 25918 |
return SDValue(); |
0 |
25918 |
return SDValue(); |
0 |
| 25919 |
StNode = St; |
0 |
25919 |
StNode = St; |
0 |
| 25920 |
continue; |
0 |
25920 |
continue; |
0 |
| 25921 |
} |
--- |
25921 |
} |
--- |
| 25922 |
return SDValue(); |
0 |
25922 |
return SDValue(); |
0 |
| 25923 |
} |
--- |
25923 |
} |
--- |
| 25924 |
if (!StNode || !StNode->isSimple() || StNode->isIndexed() || |
0 |
25924 |
if (!StNode || !StNode->isSimple() || StNode->isIndexed() || |
0 |
| 25925 |
!StNode->getOffset().isUndef() || StNode->getMemoryVT() != MemVT || |
0 |
25925 |
!StNode->getOffset().isUndef() || StNode->getMemoryVT() != MemVT || |
0 |
| 25926 |
!Chain.reachesChainWithoutSideEffects(SDValue(StNode, 0))) |
0 |
25926 |
!Chain.reachesChainWithoutSideEffects(SDValue(StNode, 0))) |
0 |
| 25927 |
return SDValue(); |
0 |
25927 |
return SDValue(); |
0 |
| 25928 |
|
--- |
25928 |
|
--- |
| 25929 |
// Check if the stored value is loaded from some location and the loaded |
--- |
25929 |
// Check if the stored value is loaded from some location and the loaded |
--- |
| 25930 |
// value is used only in the store operation. |
--- |
25930 |
// value is used only in the store operation. |
--- |
| 25931 |
SDValue StValue = StNode->getValue(); |
0 |
25931 |
SDValue StValue = StNode->getValue(); |
0 |
| 25932 |
auto *LdNode = dyn_cast(StValue); |
0 |
25932 |
auto *LdNode = dyn_cast(StValue); |
0 |
| 25933 |
if (!LdNode || !LdNode->isSimple() || LdNode->isIndexed() || |
0 |
25933 |
if (!LdNode || !LdNode->isSimple() || LdNode->isIndexed() || |
0 |
| 25934 |
!LdNode->getOffset().isUndef() || LdNode->getMemoryVT() != MemVT || |
0 |
25934 |
!LdNode->getOffset().isUndef() || LdNode->getMemoryVT() != MemVT || |
0 |
| 25935 |
!StNode->getChain().reachesChainWithoutSideEffects(SDValue(LdNode, 1))) |
0 |
25935 |
!StNode->getChain().reachesChainWithoutSideEffects(SDValue(LdNode, 1))) |
0 |
| 25936 |
return SDValue(); |
0 |
25936 |
return SDValue(); |
0 |
| 25937 |
|
--- |
25937 |
|
--- |
| 25938 |
// Create new node SET_FPENV_MEM, which uses the load address to read FP |
--- |
25938 |
// Create new node SET_FPENV_MEM, which uses the load address to read FP |
--- |
| 25939 |
// environment. |
--- |
25939 |
// environment. |
--- |
| 25940 |
SDValue Res = |
--- |
25940 |
SDValue Res = |
--- |
| 25941 |
DAG.getSetFPEnv(LdNode->getChain(), SDLoc(N), LdNode->getBasePtr(), MemVT, |
0 |
25941 |
DAG.getSetFPEnv(LdNode->getChain(), SDLoc(N), LdNode->getBasePtr(), MemVT, |
0 |
| 25942 |
LdNode->getMemOperand()); |
--- |
25942 |
LdNode->getMemOperand()); |
--- |
| 25943 |
return Res; |
0 |
25943 |
return Res; |
0 |
| 25944 |
} |
--- |
25944 |
} |
--- |
| 25945 |
|
--- |
25945 |
|
--- |
| 25946 |
/// Returns a vector_shuffle if it able to transform an AND to a vector_shuffle |
--- |
25946 |
/// Returns a vector_shuffle if it able to transform an AND to a vector_shuffle |
--- |
| 25947 |
/// with the destination vector and a zero vector. |
--- |
25947 |
/// with the destination vector and a zero vector. |
--- |
| 25948 |
/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> |
--- |
25948 |
/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> |
--- |
| 25949 |
/// vector_shuffle V, Zero, <0, 4, 2, 4> |
--- |
25949 |
/// vector_shuffle V, Zero, <0, 4, 2, 4> |
--- |
| 25950 |
SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { |
0 |
25950 |
SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { |
0 |
| 25951 |
assert(N->getOpcode() == ISD::AND && "Unexpected opcode!"); |
0 |
25951 |
assert(N->getOpcode() == ISD::AND && "Unexpected opcode!"); |
0 |
| 25952 |
|
--- |
25952 |
|
--- |
| 25953 |
EVT VT = N->getValueType(0); |
0 |
25953 |
EVT VT = N->getValueType(0); |
0 |
| 25954 |
SDValue LHS = N->getOperand(0); |
0 |
25954 |
SDValue LHS = N->getOperand(0); |
0 |
| 25955 |
SDValue RHS = peekThroughBitcasts(N->getOperand(1)); |
0 |
25955 |
SDValue RHS = peekThroughBitcasts(N->getOperand(1)); |
0 |
| 25956 |
SDLoc DL(N); |
0 |
25956 |
SDLoc DL(N); |
0 |
| 25957 |
|
--- |
25957 |
|
--- |
| 25958 |
// Make sure we're not running after operation legalization where it |
--- |
25958 |
// Make sure we're not running after operation legalization where it |
--- |
| 25959 |
// may have custom lowered the vector shuffles. |
--- |
25959 |
// may have custom lowered the vector shuffles. |
--- |
| 25960 |
if (LegalOperations) |
0 |
25960 |
if (LegalOperations) |
0 |
| 25961 |
return SDValue(); |
0 |
25961 |
return SDValue(); |
0 |
| 25962 |
|
--- |
25962 |
|
--- |
| 25963 |
if (RHS.getOpcode() != ISD::BUILD_VECTOR) |
0 |
25963 |
if (RHS.getOpcode() != ISD::BUILD_VECTOR) |
0 |
| 25964 |
return SDValue(); |
0 |
25964 |
return SDValue(); |
0 |
| 25965 |
|
--- |
25965 |
|
--- |
| 25966 |
EVT RVT = RHS.getValueType(); |
0 |
25966 |
EVT RVT = RHS.getValueType(); |
0 |
| 25967 |
unsigned NumElts = RHS.getNumOperands(); |
0 |
25967 |
unsigned NumElts = RHS.getNumOperands(); |
0 |
| 25968 |
|
--- |
25968 |
|
--- |
| 25969 |
// Attempt to create a valid clear mask, splitting the mask into |
--- |
25969 |
// Attempt to create a valid clear mask, splitting the mask into |
--- |
| 25970 |
// sub elements and checking to see if each is |
--- |
25970 |
// sub elements and checking to see if each is |
--- |
| 25971 |
// all zeros or all ones - suitable for shuffle masking. |
--- |
25971 |
// all zeros or all ones - suitable for shuffle masking. |
--- |
| 25972 |
auto BuildClearMask = [&](int Split) { |
0 |
25972 |
auto BuildClearMask = [&](int Split) { |
0 |
| 25973 |
int NumSubElts = NumElts * Split; |
0 |
25973 |
int NumSubElts = NumElts * Split; |
0 |
| 25974 |
int NumSubBits = RVT.getScalarSizeInBits() / Split; |
0 |
25974 |
int NumSubBits = RVT.getScalarSizeInBits() / Split; |
0 |
| 25975 |
|
--- |
25975 |
|
--- |
| 25976 |
SmallVector Indices; |
0 |
25976 |
SmallVector Indices; |
0 |
| 25977 |
for (int i = 0; i != NumSubElts; ++i) { |
0 |
25977 |
for (int i = 0; i != NumSubElts; ++i) { |
0 |
| 25978 |
int EltIdx = i / Split; |
0 |
25978 |
int EltIdx = i / Split; |
0 |
| 25979 |
int SubIdx = i % Split; |
0 |
25979 |
int SubIdx = i % Split; |
0 |
| 25980 |
SDValue Elt = RHS.getOperand(EltIdx); |
0 |
25980 |
SDValue Elt = RHS.getOperand(EltIdx); |
0 |
| 25981 |
// X & undef --> 0 (not undef). So this lane must be converted to choose |
--- |
25981 |
// X & undef --> 0 (not undef). So this lane must be converted to choose |
--- |
| 25982 |
// from the zero constant vector (same as if the element had all 0-bits). |
--- |
25982 |
// from the zero constant vector (same as if the element had all 0-bits). |
--- |
| 25983 |
if (Elt.isUndef()) { |
0 |
25983 |
if (Elt.isUndef()) { |
0 |
| 25984 |
Indices.push_back(i + NumSubElts); |
0 |
25984 |
Indices.push_back(i + NumSubElts); |
0 |
| 25985 |
continue; |
0 |
25985 |
continue; |
0 |
| 25986 |
} |
--- |
25986 |
} |
--- |
| 25987 |
|
--- |
25987 |
|
--- |
| 25988 |
APInt Bits; |
0 |
25988 |
APInt Bits; |
0 |
| 25989 |
if (isa(Elt)) |
0 |
25989 |
if (isa(Elt)) |
0 |
| 25990 |
Bits = cast(Elt)->getAPIntValue(); |
0 |
25990 |
Bits = cast(Elt)->getAPIntValue(); |
0 |
| 25991 |
else if (isa(Elt)) |
0 |
25991 |
else if (isa(Elt)) |
0 |
| 25992 |
Bits = cast(Elt)->getValueAPF().bitcastToAPInt(); |
0 |
25992 |
Bits = cast(Elt)->getValueAPF().bitcastToAPInt(); |
0 |
| 25993 |
else |
--- |
25993 |
else |
--- |
| 25994 |
return SDValue(); |
0 |
25994 |
return SDValue(); |
0 |
| 25995 |
|
--- |
25995 |
|
--- |
| 25996 |
// Extract the sub element from the constant bit mask. |
--- |
25996 |
// Extract the sub element from the constant bit mask. |
--- |
| 25997 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
25997 |
if (DAG.getDataLayout().isBigEndian()) |
0 |
| 25998 |
Bits = Bits.extractBits(NumSubBits, (Split - SubIdx - 1) * NumSubBits); |
0 |
25998 |
Bits = Bits.extractBits(NumSubBits, (Split - SubIdx - 1) * NumSubBits); |
0 |
| 25999 |
else |
--- |
25999 |
else |
--- |
| 26000 |
Bits = Bits.extractBits(NumSubBits, SubIdx * NumSubBits); |
0 |
26000 |
Bits = Bits.extractBits(NumSubBits, SubIdx * NumSubBits); |
0 |
| 26001 |
|
--- |
26001 |
|
--- |
| 26002 |
if (Bits.isAllOnes()) |
0 |
26002 |
if (Bits.isAllOnes()) |
0 |
| 26003 |
Indices.push_back(i); |
0 |
26003 |
Indices.push_back(i); |
0 |
| 26004 |
else if (Bits == 0) |
0 |
26004 |
else if (Bits == 0) |
0 |
| 26005 |
Indices.push_back(i + NumSubElts); |
0 |
26005 |
Indices.push_back(i + NumSubElts); |
0 |
| 26006 |
else |
--- |
26006 |
else |
--- |
| 26007 |
return SDValue(); |
0 |
26007 |
return SDValue(); |
0 |
| 26008 |
} |
0 |
26008 |
} |
0 |
| 26009 |
|
--- |
26009 |
|
--- |
| 26010 |
// Let's see if the target supports this vector_shuffle. |
--- |
26010 |
// Let's see if the target supports this vector_shuffle. |
--- |
| 26011 |
EVT ClearSVT = EVT::getIntegerVT(*DAG.getContext(), NumSubBits); |
0 |
26011 |
EVT ClearSVT = EVT::getIntegerVT(*DAG.getContext(), NumSubBits); |
0 |
| 26012 |
EVT ClearVT = EVT::getVectorVT(*DAG.getContext(), ClearSVT, NumSubElts); |
0 |
26012 |
EVT ClearVT = EVT::getVectorVT(*DAG.getContext(), ClearSVT, NumSubElts); |
0 |
| 26013 |
if (!TLI.isVectorClearMaskLegal(Indices, ClearVT)) |
0 |
26013 |
if (!TLI.isVectorClearMaskLegal(Indices, ClearVT)) |
0 |
| 26014 |
return SDValue(); |
0 |
26014 |
return SDValue(); |
0 |
| 26015 |
|
--- |
26015 |
|
--- |
| 26016 |
SDValue Zero = DAG.getConstant(0, DL, ClearVT); |
0 |
26016 |
SDValue Zero = DAG.getConstant(0, DL, ClearVT); |
0 |
| 26017 |
return DAG.getBitcast(VT, DAG.getVectorShuffle(ClearVT, DL, |
0 |
26017 |
return DAG.getBitcast(VT, DAG.getVectorShuffle(ClearVT, DL, |
0 |
| 26018 |
DAG.getBitcast(ClearVT, LHS), |
0 |
26018 |
DAG.getBitcast(ClearVT, LHS), |
0 |
| 26019 |
Zero, Indices)); |
0 |
26019 |
Zero, Indices)); |
0 |
| 26020 |
}; |
0 |
26020 |
}; |
0 |
| 26021 |
|
--- |
26021 |
|
--- |
| 26022 |
// Determine maximum split level (byte level masking). |
--- |
26022 |
// Determine maximum split level (byte level masking). |
--- |
| 26023 |
int MaxSplit = 1; |
0 |
26023 |
int MaxSplit = 1; |
0 |
| 26024 |
if (RVT.getScalarSizeInBits() % 8 == 0) |
0 |
26024 |
if (RVT.getScalarSizeInBits() % 8 == 0) |
0 |
| 26025 |
MaxSplit = RVT.getScalarSizeInBits() / 8; |
0 |
26025 |
MaxSplit = RVT.getScalarSizeInBits() / 8; |
0 |
| 26026 |
|
--- |
26026 |
|
--- |
| 26027 |
for (int Split = 1; Split <= MaxSplit; ++Split) |
0 |
26027 |
for (int Split = 1; Split <= MaxSplit; ++Split) |
0 |
| 26028 |
if (RVT.getScalarSizeInBits() % Split == 0) |
0 |
26028 |
if (RVT.getScalarSizeInBits() % Split == 0) |
0 |
| 26029 |
if (SDValue S = BuildClearMask(Split)) |
0 |
26029 |
if (SDValue S = BuildClearMask(Split)) |
0 |
| 26030 |
return S; |
0 |
26030 |
return S; |
0 |
| 26031 |
|
--- |
26031 |
|
--- |
| 26032 |
return SDValue(); |
0 |
26032 |
return SDValue(); |
0 |
| 26033 |
} |
0 |
26033 |
} |
0 |
| 26034 |
|
--- |
26034 |
|
--- |
| 26035 |
/// If a vector binop is performed on splat values, it may be profitable to |
--- |
26035 |
/// If a vector binop is performed on splat values, it may be profitable to |
--- |
| 26036 |
/// extract, scalarize, and insert/splat. |
--- |
26036 |
/// extract, scalarize, and insert/splat. |
--- |
| 26037 |
static SDValue scalarizeBinOpOfSplats(SDNode *N, SelectionDAG &DAG, |
0 |
26037 |
static SDValue scalarizeBinOpOfSplats(SDNode *N, SelectionDAG &DAG, |
0 |
| 26038 |
const SDLoc &DL) { |
--- |
26038 |
const SDLoc &DL) { |
--- |
| 26039 |
SDValue N0 = N->getOperand(0); |
0 |
26039 |
SDValue N0 = N->getOperand(0); |
0 |
| 26040 |
SDValue N1 = N->getOperand(1); |
0 |
26040 |
SDValue N1 = N->getOperand(1); |
0 |
| 26041 |
unsigned Opcode = N->getOpcode(); |
0 |
26041 |
unsigned Opcode = N->getOpcode(); |
0 |
| 26042 |
EVT VT = N->getValueType(0); |
0 |
26042 |
EVT VT = N->getValueType(0); |
0 |
| 26043 |
EVT EltVT = VT.getVectorElementType(); |
0 |
26043 |
EVT EltVT = VT.getVectorElementType(); |
0 |
| 26044 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
26044 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 26045 |
|
--- |
26045 |
|
--- |
| 26046 |
// TODO: Remove/replace the extract cost check? If the elements are available |
--- |
26046 |
// TODO: Remove/replace the extract cost check? If the elements are available |
--- |
| 26047 |
// as scalars, then there may be no extract cost. Should we ask if |
--- |
26047 |
// as scalars, then there may be no extract cost. Should we ask if |
--- |
| 26048 |
// inserting a scalar back into a vector is cheap instead? |
--- |
26048 |
// inserting a scalar back into a vector is cheap instead? |
--- |
| 26049 |
int Index0, Index1; |
--- |
26049 |
int Index0, Index1; |
--- |
| 26050 |
SDValue Src0 = DAG.getSplatSourceVector(N0, Index0); |
0 |
26050 |
SDValue Src0 = DAG.getSplatSourceVector(N0, Index0); |
0 |
| 26051 |
SDValue Src1 = DAG.getSplatSourceVector(N1, Index1); |
0 |
26051 |
SDValue Src1 = DAG.getSplatSourceVector(N1, Index1); |
0 |
| 26052 |
// Extract element from splat_vector should be free. |
--- |
26052 |
// Extract element from splat_vector should be free. |
--- |
| 26053 |
// TODO: use DAG.isSplatValue instead? |
--- |
26053 |
// TODO: use DAG.isSplatValue instead? |
--- |
| 26054 |
bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR && |
0 |
26054 |
bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR && |
0 |
| 26055 |
N1.getOpcode() == ISD::SPLAT_VECTOR; |
0 |
26055 |
N1.getOpcode() == ISD::SPLAT_VECTOR; |
0 |
| 26056 |
if (!Src0 || !Src1 || Index0 != Index1 || |
0 |
26056 |
if (!Src0 || !Src1 || Index0 != Index1 || |
0 |
| 26057 |
Src0.getValueType().getVectorElementType() != EltVT || |
0 |
26057 |
Src0.getValueType().getVectorElementType() != EltVT || |
0 |
| 26058 |
Src1.getValueType().getVectorElementType() != EltVT || |
0 |
26058 |
Src1.getValueType().getVectorElementType() != EltVT || |
0 |
| 26059 |
!(IsBothSplatVector || TLI.isExtractVecEltCheap(VT, Index0)) || |
0 |
26059 |
!(IsBothSplatVector || TLI.isExtractVecEltCheap(VT, Index0)) || |
0 |
| 26060 |
!TLI.isOperationLegalOrCustom(Opcode, EltVT)) |
0 |
26060 |
!TLI.isOperationLegalOrCustom(Opcode, EltVT)) |
0 |
| 26061 |
return SDValue(); |
0 |
26061 |
return SDValue(); |
0 |
| 26062 |
|
--- |
26062 |
|
--- |
| 26063 |
SDValue IndexC = DAG.getVectorIdxConstant(Index0, DL); |
0 |
26063 |
SDValue IndexC = DAG.getVectorIdxConstant(Index0, DL); |
0 |
| 26064 |
SDValue X = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Src0, IndexC); |
0 |
26064 |
SDValue X = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Src0, IndexC); |
0 |
| 26065 |
SDValue Y = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Src1, IndexC); |
0 |
26065 |
SDValue Y = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Src1, IndexC); |
0 |
| 26066 |
SDValue ScalarBO = DAG.getNode(Opcode, DL, EltVT, X, Y, N->getFlags()); |
0 |
26066 |
SDValue ScalarBO = DAG.getNode(Opcode, DL, EltVT, X, Y, N->getFlags()); |
0 |
| 26067 |
|
--- |
26067 |
|
--- |
| 26068 |
// If all lanes but 1 are undefined, no need to splat the scalar result. |
--- |
26068 |
// If all lanes but 1 are undefined, no need to splat the scalar result. |
--- |
| 26069 |
// TODO: Keep track of undefs and use that info in the general case. |
--- |
26069 |
// TODO: Keep track of undefs and use that info in the general case. |
--- |
| 26070 |
if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() && |
0 |
26070 |
if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() && |
0 |
| 26071 |
count_if(N0->ops(), [](SDValue V) { return !V.isUndef(); }) == 1 && |
0 |
26071 |
count_if(N0->ops(), [](SDValue V) { return !V.isUndef(); }) == 1 && |
0 |
| 26072 |
count_if(N1->ops(), [](SDValue V) { return !V.isUndef(); }) == 1) { |
0 |
26072 |
count_if(N1->ops(), [](SDValue V) { return !V.isUndef(); }) == 1) { |
0 |
| 26073 |
// bo (build_vec ..undef, X, undef...), (build_vec ..undef, Y, undef...) --> |
--- |
26073 |
// bo (build_vec ..undef, X, undef...), (build_vec ..undef, Y, undef...) --> |
--- |
| 26074 |
// build_vec ..undef, (bo X, Y), undef... |
--- |
26074 |
// build_vec ..undef, (bo X, Y), undef... |
--- |
| 26075 |
SmallVector Ops(VT.getVectorNumElements(), DAG.getUNDEF(EltVT)); |
0 |
26075 |
SmallVector Ops(VT.getVectorNumElements(), DAG.getUNDEF(EltVT)); |
0 |
| 26076 |
Ops[Index0] = ScalarBO; |
0 |
26076 |
Ops[Index0] = ScalarBO; |
0 |
| 26077 |
return DAG.getBuildVector(VT, DL, Ops); |
0 |
26077 |
return DAG.getBuildVector(VT, DL, Ops); |
0 |
| 26078 |
} |
0 |
26078 |
} |
0 |
| 26079 |
|
--- |
26079 |
|
--- |
| 26080 |
// bo (splat X, Index), (splat Y, Index) --> splat (bo X, Y), Index |
--- |
26080 |
// bo (splat X, Index), (splat Y, Index) --> splat (bo X, Y), Index |
--- |
| 26081 |
return DAG.getSplat(VT, DL, ScalarBO); |
0 |
26081 |
return DAG.getSplat(VT, DL, ScalarBO); |
0 |
| 26082 |
} |
--- |
26082 |
} |
--- |
| 26083 |
|
--- |
26083 |
|
--- |
| 26084 |
/// Visit a vector cast operation, like FP_EXTEND. |
--- |
26084 |
/// Visit a vector cast operation, like FP_EXTEND. |
--- |
| 26085 |
SDValue DAGCombiner::SimplifyVCastOp(SDNode *N, const SDLoc &DL) { |
0 |
26085 |
SDValue DAGCombiner::SimplifyVCastOp(SDNode *N, const SDLoc &DL) { |
0 |
| 26086 |
EVT VT = N->getValueType(0); |
0 |
26086 |
EVT VT = N->getValueType(0); |
0 |
| 26087 |
assert(VT.isVector() && "SimplifyVCastOp only works on vectors!"); |
0 |
26087 |
assert(VT.isVector() && "SimplifyVCastOp only works on vectors!"); |
0 |
| 26088 |
EVT EltVT = VT.getVectorElementType(); |
0 |
26088 |
EVT EltVT = VT.getVectorElementType(); |
0 |
| 26089 |
unsigned Opcode = N->getOpcode(); |
0 |
26089 |
unsigned Opcode = N->getOpcode(); |
0 |
| 26090 |
|
--- |
26090 |
|
--- |
| 26091 |
SDValue N0 = N->getOperand(0); |
0 |
26091 |
SDValue N0 = N->getOperand(0); |
0 |
| 26092 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
26092 |
const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
0 |
| 26093 |
|
--- |
26093 |
|
--- |
| 26094 |
// TODO: promote operation might be also good here? |
--- |
26094 |
// TODO: promote operation might be also good here? |
--- |
| 26095 |
int Index0; |
--- |
26095 |
int Index0; |
--- |
| 26096 |
SDValue Src0 = DAG.getSplatSourceVector(N0, Index0); |
0 |
26096 |
SDValue Src0 = DAG.getSplatSourceVector(N0, Index0); |
0 |
| 26097 |
if (Src0 && |
0 |
26097 |
if (Src0 && |
0 |
| 26098 |
(N0.getOpcode() == ISD::SPLAT_VECTOR || |
0 |
26098 |
(N0.getOpcode() == ISD::SPLAT_VECTOR || |
0 |
| 26099 |
TLI.isExtractVecEltCheap(VT, Index0)) && |
0 |
26099 |
TLI.isExtractVecEltCheap(VT, Index0)) && |
0 |
| 26100 |
TLI.isOperationLegalOrCustom(Opcode, EltVT) && |
0 |
26100 |
TLI.isOperationLegalOrCustom(Opcode, EltVT) && |
0 |
| 26101 |
TLI.preferScalarizeSplat(N)) { |
0 |
26101 |
TLI.preferScalarizeSplat(N)) { |
0 |
| 26102 |
EVT SrcVT = N0.getValueType(); |
0 |
26102 |
EVT SrcVT = N0.getValueType(); |
0 |
| 26103 |
EVT SrcEltVT = SrcVT.getVectorElementType(); |
0 |
26103 |
EVT SrcEltVT = SrcVT.getVectorElementType(); |
0 |
| 26104 |
SDValue IndexC = DAG.getVectorIdxConstant(Index0, DL); |
0 |
26104 |
SDValue IndexC = DAG.getVectorIdxConstant(Index0, DL); |
0 |
| 26105 |
SDValue Elt = |
--- |
26105 |
SDValue Elt = |
--- |
| 26106 |
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SrcEltVT, Src0, IndexC); |
0 |
26106 |
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SrcEltVT, Src0, IndexC); |
0 |
| 26107 |
SDValue ScalarBO = DAG.getNode(Opcode, DL, EltVT, Elt, N->getFlags()); |
0 |
26107 |
SDValue ScalarBO = DAG.getNode(Opcode, DL, EltVT, Elt, N->getFlags()); |
0 |
| 26108 |
if (VT.isScalableVector()) |
0 |
26108 |
if (VT.isScalableVector()) |
0 |
| 26109 |
return DAG.getSplatVector(VT, DL, ScalarBO); |
0 |
26109 |
return DAG.getSplatVector(VT, DL, ScalarBO); |
0 |
| 26110 |
SmallVector Ops(VT.getVectorNumElements(), ScalarBO); |
0 |
26110 |
SmallVector Ops(VT.getVectorNumElements(), ScalarBO); |
0 |
| 26111 |
return DAG.getBuildVector(VT, DL, Ops); |
0 |
26111 |
return DAG.getBuildVector(VT, DL, Ops); |
0 |
| 26112 |
} |
0 |
26112 |
} |
0 |
| 26113 |
|
--- |
26113 |
|
--- |
| 26114 |
return SDValue(); |
0 |
26114 |
return SDValue(); |
0 |
| 26115 |
} |
--- |
26115 |
} |
--- |
| 26116 |
|
--- |
26116 |
|
--- |
| 26117 |
/// Visit a binary vector operation, like ADD. |
--- |
26117 |
/// Visit a binary vector operation, like ADD. |
--- |
| 26118 |
SDValue DAGCombiner::SimplifyVBinOp(SDNode *N, const SDLoc &DL) { |
0 |
26118 |
SDValue DAGCombiner::SimplifyVBinOp(SDNode *N, const SDLoc &DL) { |
0 |
| 26119 |
EVT VT = N->getValueType(0); |
0 |
26119 |
EVT VT = N->getValueType(0); |
0 |
| 26120 |
assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); |
0 |
26120 |
assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); |
0 |
| 26121 |
|
--- |
26121 |
|
--- |
| 26122 |
SDValue LHS = N->getOperand(0); |
0 |
26122 |
SDValue LHS = N->getOperand(0); |
0 |
| 26123 |
SDValue RHS = N->getOperand(1); |
0 |
26123 |
SDValue RHS = N->getOperand(1); |
0 |
| 26124 |
unsigned Opcode = N->getOpcode(); |
0 |
26124 |
unsigned Opcode = N->getOpcode(); |
0 |
| 26125 |
SDNodeFlags Flags = N->getFlags(); |
0 |
26125 |
SDNodeFlags Flags = N->getFlags(); |
0 |
| 26126 |
|
--- |
26126 |
|
--- |
| 26127 |
// Move unary shuffles with identical masks after a vector binop: |
--- |
26127 |
// Move unary shuffles with identical masks after a vector binop: |
--- |
| 26128 |
// VBinOp (shuffle A, Undef, Mask), (shuffle B, Undef, Mask)) |
--- |
26128 |
// VBinOp (shuffle A, Undef, Mask), (shuffle B, Undef, Mask)) |
--- |
| 26129 |
// --> shuffle (VBinOp A, B), Undef, Mask |
--- |
26129 |
// --> shuffle (VBinOp A, B), Undef, Mask |
--- |
| 26130 |
// This does not require type legality checks because we are creating the |
--- |
26130 |
// This does not require type legality checks because we are creating the |
--- |
| 26131 |
// same types of operations that are in the original sequence. We do have to |
--- |
26131 |
// same types of operations that are in the original sequence. We do have to |
--- |
| 26132 |
// restrict ops like integer div that have immediate UB (eg, div-by-zero) |
--- |
26132 |
// restrict ops like integer div that have immediate UB (eg, div-by-zero) |
--- |
| 26133 |
// though. This code is adapted from the identical transform in instcombine. |
--- |
26133 |
// though. This code is adapted from the identical transform in instcombine. |
--- |
| 26134 |
if (DAG.isSafeToSpeculativelyExecute(Opcode)) { |
0 |
26134 |
if (DAG.isSafeToSpeculativelyExecute(Opcode)) { |
0 |
| 26135 |
auto *Shuf0 = dyn_cast(LHS); |
0 |
26135 |
auto *Shuf0 = dyn_cast(LHS); |
0 |
| 26136 |
auto *Shuf1 = dyn_cast(RHS); |
0 |
26136 |
auto *Shuf1 = dyn_cast(RHS); |
0 |
| 26137 |
if (Shuf0 && Shuf1 && Shuf0->getMask().equals(Shuf1->getMask()) && |
0 |
26137 |
if (Shuf0 && Shuf1 && Shuf0->getMask().equals(Shuf1->getMask()) && |
0 |
| 26138 |
LHS.getOperand(1).isUndef() && RHS.getOperand(1).isUndef() && |
0 |
26138 |
LHS.getOperand(1).isUndef() && RHS.getOperand(1).isUndef() && |
0 |
| 26139 |
(LHS.hasOneUse() || RHS.hasOneUse() || LHS == RHS)) { |
0 |
26139 |
(LHS.hasOneUse() || RHS.hasOneUse() || LHS == RHS)) { |
0 |
| 26140 |
SDValue NewBinOp = DAG.getNode(Opcode, DL, VT, LHS.getOperand(0), |
0 |
26140 |
SDValue NewBinOp = DAG.getNode(Opcode, DL, VT, LHS.getOperand(0), |
0 |
| 26141 |
RHS.getOperand(0), Flags); |
0 |
26141 |
RHS.getOperand(0), Flags); |
0 |
| 26142 |
SDValue UndefV = LHS.getOperand(1); |
0 |
26142 |
SDValue UndefV = LHS.getOperand(1); |
0 |
| 26143 |
return DAG.getVectorShuffle(VT, DL, NewBinOp, UndefV, Shuf0->getMask()); |
0 |
26143 |
return DAG.getVectorShuffle(VT, DL, NewBinOp, UndefV, Shuf0->getMask()); |
0 |
| 26144 |
} |
--- |
26144 |
} |
--- |
| 26145 |
|
--- |
26145 |
|
--- |
| 26146 |
// Try to sink a splat shuffle after a binop with a uniform constant. |
--- |
26146 |
// Try to sink a splat shuffle after a binop with a uniform constant. |
--- |
| 26147 |
// This is limited to cases where neither the shuffle nor the constant have |
--- |
26147 |
// This is limited to cases where neither the shuffle nor the constant have |
--- |
| 26148 |
// undefined elements because that could be poison-unsafe or inhibit |
--- |
26148 |
// undefined elements because that could be poison-unsafe or inhibit |
--- |
| 26149 |
// demanded elements analysis. It is further limited to not change a splat |
--- |
26149 |
// demanded elements analysis. It is further limited to not change a splat |
--- |
| 26150 |
// of an inserted scalar because that may be optimized better by |
--- |
26150 |
// of an inserted scalar because that may be optimized better by |
--- |
| 26151 |
// load-folding or other target-specific behaviors. |
--- |
26151 |
// load-folding or other target-specific behaviors. |
--- |
| 26152 |
if (isConstOrConstSplat(RHS) && Shuf0 && all_equal(Shuf0->getMask()) && |
0 |
26152 |
if (isConstOrConstSplat(RHS) && Shuf0 && all_equal(Shuf0->getMask()) && |
0 |
| 26153 |
Shuf0->hasOneUse() && Shuf0->getOperand(1).isUndef() && |
0 |
26153 |
Shuf0->hasOneUse() && Shuf0->getOperand(1).isUndef() && |
0 |
| 26154 |
Shuf0->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { |
0 |
26154 |
Shuf0->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { |
0 |
| 26155 |
// binop (splat X), (splat C) --> splat (binop X, C) |
--- |
26155 |
// binop (splat X), (splat C) --> splat (binop X, C) |
--- |
| 26156 |
SDValue X = Shuf0->getOperand(0); |
0 |
26156 |
SDValue X = Shuf0->getOperand(0); |
0 |
| 26157 |
SDValue NewBinOp = DAG.getNode(Opcode, DL, VT, X, RHS, Flags); |
0 |
26157 |
SDValue NewBinOp = DAG.getNode(Opcode, DL, VT, X, RHS, Flags); |
0 |
| 26158 |
return DAG.getVectorShuffle(VT, DL, NewBinOp, DAG.getUNDEF(VT), |
0 |
26158 |
return DAG.getVectorShuffle(VT, DL, NewBinOp, DAG.getUNDEF(VT), |
0 |
| 26159 |
Shuf0->getMask()); |
0 |
26159 |
Shuf0->getMask()); |
0 |
| 26160 |
} |
--- |
26160 |
} |
--- |
| 26161 |
if (isConstOrConstSplat(LHS) && Shuf1 && all_equal(Shuf1->getMask()) && |
0 |
26161 |
if (isConstOrConstSplat(LHS) && Shuf1 && all_equal(Shuf1->getMask()) && |
0 |
| 26162 |
Shuf1->hasOneUse() && Shuf1->getOperand(1).isUndef() && |
0 |
26162 |
Shuf1->hasOneUse() && Shuf1->getOperand(1).isUndef() && |
0 |
| 26163 |
Shuf1->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { |
0 |
26163 |
Shuf1->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) { |
0 |
| 26164 |
// binop (splat C), (splat X) --> splat (binop C, X) |
--- |
26164 |
// binop (splat C), (splat X) --> splat (binop C, X) |
--- |
| 26165 |
SDValue X = Shuf1->getOperand(0); |
0 |
26165 |
SDValue X = Shuf1->getOperand(0); |
0 |
| 26166 |
SDValue NewBinOp = DAG.getNode(Opcode, DL, VT, LHS, X, Flags); |
0 |
26166 |
SDValue NewBinOp = DAG.getNode(Opcode, DL, VT, LHS, X, Flags); |
0 |
| 26167 |
return DAG.getVectorShuffle(VT, DL, NewBinOp, DAG.getUNDEF(VT), |
0 |
26167 |
return DAG.getVectorShuffle(VT, DL, NewBinOp, DAG.getUNDEF(VT), |
0 |
| 26168 |
Shuf1->getMask()); |
0 |
26168 |
Shuf1->getMask()); |
0 |
| 26169 |
} |
--- |
26169 |
} |
--- |
| 26170 |
} |
--- |
26170 |
} |
--- |
| 26171 |
|
--- |
26171 |
|
--- |
| 26172 |
// The following pattern is likely to emerge with vector reduction ops. Moving |
--- |
26172 |
// The following pattern is likely to emerge with vector reduction ops. Moving |
--- |
| 26173 |
// the binary operation ahead of insertion may allow using a narrower vector |
--- |
26173 |
// the binary operation ahead of insertion may allow using a narrower vector |
--- |
| 26174 |
// instruction that has better performance than the wide version of the op: |
--- |
26174 |
// instruction that has better performance than the wide version of the op: |
--- |
| 26175 |
// VBinOp (ins undef, X, Z), (ins undef, Y, Z) --> ins VecC, (VBinOp X, Y), Z |
--- |
26175 |
// VBinOp (ins undef, X, Z), (ins undef, Y, Z) --> ins VecC, (VBinOp X, Y), Z |
--- |
| 26176 |
if (LHS.getOpcode() == ISD::INSERT_SUBVECTOR && LHS.getOperand(0).isUndef() && |
0 |
26176 |
if (LHS.getOpcode() == ISD::INSERT_SUBVECTOR && LHS.getOperand(0).isUndef() && |
0 |
| 26177 |
RHS.getOpcode() == ISD::INSERT_SUBVECTOR && RHS.getOperand(0).isUndef() && |
0 |
26177 |
RHS.getOpcode() == ISD::INSERT_SUBVECTOR && RHS.getOperand(0).isUndef() && |
0 |
| 26178 |
LHS.getOperand(2) == RHS.getOperand(2) && |
0 |
26178 |
LHS.getOperand(2) == RHS.getOperand(2) && |
0 |
| 26179 |
(LHS.hasOneUse() || RHS.hasOneUse())) { |
0 |
26179 |
(LHS.hasOneUse() || RHS.hasOneUse())) { |
0 |
| 26180 |
SDValue X = LHS.getOperand(1); |
0 |
26180 |
SDValue X = LHS.getOperand(1); |
0 |
| 26181 |
SDValue Y = RHS.getOperand(1); |
0 |
26181 |
SDValue Y = RHS.getOperand(1); |
0 |
| 26182 |
SDValue Z = LHS.getOperand(2); |
0 |
26182 |
SDValue Z = LHS.getOperand(2); |
0 |
| 26183 |
EVT NarrowVT = X.getValueType(); |
0 |
26183 |
EVT NarrowVT = X.getValueType(); |
0 |
| 26184 |
if (NarrowVT == Y.getValueType() && |
0 |
26184 |
if (NarrowVT == Y.getValueType() && |
0 |
| 26185 |
TLI.isOperationLegalOrCustomOrPromote(Opcode, NarrowVT, |
0 |
26185 |
TLI.isOperationLegalOrCustomOrPromote(Opcode, NarrowVT, |
0 |
| 26186 |
LegalOperations)) { |
0 |
26186 |
LegalOperations)) { |
0 |
| 26187 |
// (binop undef, undef) may not return undef, so compute that result. |
--- |
26187 |
// (binop undef, undef) may not return undef, so compute that result. |
--- |
| 26188 |
SDValue VecC = |
--- |
26188 |
SDValue VecC = |
--- |
| 26189 |
DAG.getNode(Opcode, DL, VT, DAG.getUNDEF(VT), DAG.getUNDEF(VT)); |
0 |
26189 |
DAG.getNode(Opcode, DL, VT, DAG.getUNDEF(VT), DAG.getUNDEF(VT)); |
0 |
| 26190 |
SDValue NarrowBO = DAG.getNode(Opcode, DL, NarrowVT, X, Y); |
0 |
26190 |
SDValue NarrowBO = DAG.getNode(Opcode, DL, NarrowVT, X, Y); |
0 |
| 26191 |
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, VecC, NarrowBO, Z); |
0 |
26191 |
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, VecC, NarrowBO, Z); |
0 |
| 26192 |
} |
--- |
26192 |
} |
--- |
| 26193 |
} |
--- |
26193 |
} |
--- |
| 26194 |
|
--- |
26194 |
|
--- |
| 26195 |
// Make sure all but the first op are undef or constant. |
--- |
26195 |
// Make sure all but the first op are undef or constant. |
--- |
| 26196 |
auto ConcatWithConstantOrUndef = [](SDValue Concat) { |
0 |
26196 |
auto ConcatWithConstantOrUndef = [](SDValue Concat) { |
0 |
| 26197 |
return Concat.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
26197 |
return Concat.getOpcode() == ISD::CONCAT_VECTORS && |
0 |
| 26198 |
all_of(drop_begin(Concat->ops()), [](const SDValue &Op) { |
0 |
26198 |
all_of(drop_begin(Concat->ops()), [](const SDValue &Op) { |
0 |
| 26199 |
return Op.isUndef() || |
0 |
26199 |
return Op.isUndef() || |
0 |
| 26200 |
ISD::isBuildVectorOfConstantSDNodes(Op.getNode()); |
0 |
26200 |
ISD::isBuildVectorOfConstantSDNodes(Op.getNode()); |
0 |
| 26201 |
}); |
0 |
26201 |
}); |
0 |
| 26202 |
}; |
--- |
26202 |
}; |
--- |
| 26203 |
|
--- |
26203 |
|
--- |
| 26204 |
// The following pattern is likely to emerge with vector reduction ops. Moving |
--- |
26204 |
// The following pattern is likely to emerge with vector reduction ops. Moving |
--- |
| 26205 |
// the binary operation ahead of the concat may allow using a narrower vector |
--- |
26205 |
// the binary operation ahead of the concat may allow using a narrower vector |
--- |
| 26206 |
// instruction that has better performance than the wide version of the op: |
--- |
26206 |
// instruction that has better performance than the wide version of the op: |
--- |
| 26207 |
// VBinOp (concat X, undef/constant), (concat Y, undef/constant) --> |
--- |
26207 |
// VBinOp (concat X, undef/constant), (concat Y, undef/constant) --> |
--- |
| 26208 |
// concat (VBinOp X, Y), VecC |
--- |
26208 |
// concat (VBinOp X, Y), VecC |
--- |
| 26209 |
if (ConcatWithConstantOrUndef(LHS) && ConcatWithConstantOrUndef(RHS) && |
0 |
26209 |
if (ConcatWithConstantOrUndef(LHS) && ConcatWithConstantOrUndef(RHS) && |
0 |
| 26210 |
(LHS.hasOneUse() || RHS.hasOneUse())) { |
0 |
26210 |
(LHS.hasOneUse() || RHS.hasOneUse())) { |
0 |
| 26211 |
EVT NarrowVT = LHS.getOperand(0).getValueType(); |
0 |
26211 |
EVT NarrowVT = LHS.getOperand(0).getValueType(); |
0 |
| 26212 |
if (NarrowVT == RHS.getOperand(0).getValueType() && |
0 |
26212 |
if (NarrowVT == RHS.getOperand(0).getValueType() && |
0 |
| 26213 |
TLI.isOperationLegalOrCustomOrPromote(Opcode, NarrowVT)) { |
0 |
26213 |
TLI.isOperationLegalOrCustomOrPromote(Opcode, NarrowVT)) { |
0 |
| 26214 |
unsigned NumOperands = LHS.getNumOperands(); |
0 |
26214 |
unsigned NumOperands = LHS.getNumOperands(); |
0 |
| 26215 |
SmallVector ConcatOps; |
0 |
26215 |
SmallVector ConcatOps; |
0 |
| 26216 |
for (unsigned i = 0; i != NumOperands; ++i) { |
0 |
26216 |
for (unsigned i = 0; i != NumOperands; ++i) { |
0 |
| 26217 |
// This constant fold for operands 1 and up. |
--- |
26217 |
// This constant fold for operands 1 and up. |
--- |
| 26218 |
ConcatOps.push_back(DAG.getNode(Opcode, DL, NarrowVT, LHS.getOperand(i), |
0 |
26218 |
ConcatOps.push_back(DAG.getNode(Opcode, DL, NarrowVT, LHS.getOperand(i), |
0 |
| 26219 |
RHS.getOperand(i))); |
0 |
26219 |
RHS.getOperand(i))); |
0 |
| 26220 |
} |
--- |
26220 |
} |
--- |
| 26221 |
|
--- |
26221 |
|
--- |
| 26222 |
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps); |
0 |
26222 |
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps); |
0 |
| 26223 |
} |
0 |
26223 |
} |
0 |
| 26224 |
} |
--- |
26224 |
} |
--- |
| 26225 |
|
--- |
26225 |
|
--- |
| 26226 |
if (SDValue V = scalarizeBinOpOfSplats(N, DAG, DL)) |
0 |
26226 |
if (SDValue V = scalarizeBinOpOfSplats(N, DAG, DL)) |
0 |
| 26227 |
return V; |
0 |
26227 |
return V; |
0 |
| 26228 |
|
--- |
26228 |
|
--- |
| 26229 |
return SDValue(); |
0 |
26229 |
return SDValue(); |
0 |
| 26230 |
} |
--- |
26230 |
} |
--- |
| 26231 |
|
--- |
26231 |
|
--- |
| 26232 |
SDValue DAGCombiner::SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, |
0 |
26232 |
SDValue DAGCombiner::SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, |
0 |
| 26233 |
SDValue N2) { |
--- |
26233 |
SDValue N2) { |
--- |
| 26234 |
assert(N0.getOpcode() == ISD::SETCC && |
0 |
26234 |
assert(N0.getOpcode() == ISD::SETCC && |
0 |
| 26235 |
"First argument must be a SetCC node!"); |
--- |
26235 |
"First argument must be a SetCC node!"); |
--- |
| 26236 |
|
--- |
26236 |
|
--- |
| 26237 |
SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, |
0 |
26237 |
SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, |
0 |
| 26238 |
cast(N0.getOperand(2))->get()); |
--- |
26238 |
cast(N0.getOperand(2))->get()); |
--- |
| 26239 |
|
--- |
26239 |
|
--- |
| 26240 |
// If we got a simplified select_cc node back from SimplifySelectCC, then |
--- |
26240 |
// If we got a simplified select_cc node back from SimplifySelectCC, then |
--- |
| 26241 |
// break it down into a new SETCC node, and a new SELECT node, and then return |
--- |
26241 |
// break it down into a new SETCC node, and a new SELECT node, and then return |
--- |
| 26242 |
// the SELECT node, since we were called with a SELECT node. |
--- |
26242 |
// the SELECT node, since we were called with a SELECT node. |
--- |
| 26243 |
if (SCC.getNode()) { |
0 |
26243 |
if (SCC.getNode()) { |
0 |
| 26244 |
// Check to see if we got a select_cc back (to turn into setcc/select). |
--- |
26244 |
// Check to see if we got a select_cc back (to turn into setcc/select). |
--- |
| 26245 |
// Otherwise, just return whatever node we got back, like fabs. |
--- |
26245 |
// Otherwise, just return whatever node we got back, like fabs. |
--- |
| 26246 |
if (SCC.getOpcode() == ISD::SELECT_CC) { |
0 |
26246 |
if (SCC.getOpcode() == ISD::SELECT_CC) { |
0 |
| 26247 |
const SDNodeFlags Flags = N0->getFlags(); |
0 |
26247 |
const SDNodeFlags Flags = N0->getFlags(); |
0 |
| 26248 |
SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0), |
0 |
26248 |
SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0), |
0 |
| 26249 |
N0.getValueType(), |
--- |
26249 |
N0.getValueType(), |
--- |
| 26250 |
SCC.getOperand(0), SCC.getOperand(1), |
0 |
26250 |
SCC.getOperand(0), SCC.getOperand(1), |
0 |
| 26251 |
SCC.getOperand(4), Flags); |
0 |
26251 |
SCC.getOperand(4), Flags); |
0 |
| 26252 |
AddToWorklist(SETCC.getNode()); |
0 |
26252 |
AddToWorklist(SETCC.getNode()); |
0 |
| 26253 |
SDValue SelectNode = DAG.getSelect(SDLoc(SCC), SCC.getValueType(), SETCC, |
0 |
26253 |
SDValue SelectNode = DAG.getSelect(SDLoc(SCC), SCC.getValueType(), SETCC, |
0 |
| 26254 |
SCC.getOperand(2), SCC.getOperand(3)); |
0 |
26254 |
SCC.getOperand(2), SCC.getOperand(3)); |
0 |
| 26255 |
SelectNode->setFlags(Flags); |
0 |
26255 |
SelectNode->setFlags(Flags); |
0 |
| 26256 |
return SelectNode; |
0 |
26256 |
return SelectNode; |
0 |
| 26257 |
} |
--- |
26257 |
} |
--- |
| 26258 |
|
--- |
26258 |
|
--- |
| 26259 |
return SCC; |
0 |
26259 |
return SCC; |
0 |
| 26260 |
} |
--- |
26260 |
} |
--- |
| 26261 |
return SDValue(); |
0 |
26261 |
return SDValue(); |
0 |
| 26262 |
} |
--- |
26262 |
} |
--- |
| 26263 |
|
--- |
26263 |
|
--- |
| 26264 |
/// Given a SELECT or a SELECT_CC node, where LHS and RHS are the two values |
--- |
26264 |
/// Given a SELECT or a SELECT_CC node, where LHS and RHS are the two values |
--- |
| 26265 |
/// being selected between, see if we can simplify the select. Callers of this |
--- |
26265 |
/// being selected between, see if we can simplify the select. Callers of this |
--- |
| 26266 |
/// should assume that TheSelect is deleted if this returns true. As such, they |
--- |
26266 |
/// should assume that TheSelect is deleted if this returns true. As such, they |
--- |
| 26267 |
/// should return the appropriate thing (e.g. the node) back to the top-level of |
--- |
26267 |
/// should return the appropriate thing (e.g. the node) back to the top-level of |
--- |
| 26268 |
/// the DAG combiner loop to avoid it being looked at. |
--- |
26268 |
/// the DAG combiner loop to avoid it being looked at. |
--- |
| 26269 |
bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, |
0 |
26269 |
bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, |
0 |
| 26270 |
SDValue RHS) { |
--- |
26270 |
SDValue RHS) { |
--- |
| 26271 |
// fold (select (setcc x, [+-]0.0, *lt), NaN, (fsqrt x)) |
--- |
26271 |
// fold (select (setcc x, [+-]0.0, *lt), NaN, (fsqrt x)) |
--- |
| 26272 |
// The select + setcc is redundant, because fsqrt returns NaN for X < 0. |
--- |
26272 |
// The select + setcc is redundant, because fsqrt returns NaN for X < 0. |
--- |
| 26273 |
if (const ConstantFPSDNode *NaN = isConstOrConstSplatFP(LHS)) { |
0 |
26273 |
if (const ConstantFPSDNode *NaN = isConstOrConstSplatFP(LHS)) { |
0 |
| 26274 |
if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) { |
0 |
26274 |
if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) { |
0 |
| 26275 |
// We have: (select (setcc ?, ?, ?), NaN, (fsqrt ?)) |
--- |
26275 |
// We have: (select (setcc ?, ?, ?), NaN, (fsqrt ?)) |
--- |
| 26276 |
SDValue Sqrt = RHS; |
0 |
26276 |
SDValue Sqrt = RHS; |
0 |
| 26277 |
ISD::CondCode CC; |
--- |
26277 |
ISD::CondCode CC; |
--- |
| 26278 |
SDValue CmpLHS; |
0 |
26278 |
SDValue CmpLHS; |
0 |
| 26279 |
const ConstantFPSDNode *Zero = nullptr; |
0 |
26279 |
const ConstantFPSDNode *Zero = nullptr; |
0 |
| 26280 |
|
--- |
26280 |
|
--- |
| 26281 |
if (TheSelect->getOpcode() == ISD::SELECT_CC) { |
0 |
26281 |
if (TheSelect->getOpcode() == ISD::SELECT_CC) { |
0 |
| 26282 |
CC = cast(TheSelect->getOperand(4))->get(); |
0 |
26282 |
CC = cast(TheSelect->getOperand(4))->get(); |
0 |
| 26283 |
CmpLHS = TheSelect->getOperand(0); |
0 |
26283 |
CmpLHS = TheSelect->getOperand(0); |
0 |
| 26284 |
Zero = isConstOrConstSplatFP(TheSelect->getOperand(1)); |
0 |
26284 |
Zero = isConstOrConstSplatFP(TheSelect->getOperand(1)); |
0 |
| 26285 |
} else { |
--- |
26285 |
} else { |
--- |
| 26286 |
// SELECT or VSELECT |
--- |
26286 |
// SELECT or VSELECT |
--- |
| 26287 |
SDValue Cmp = TheSelect->getOperand(0); |
0 |
26287 |
SDValue Cmp = TheSelect->getOperand(0); |
0 |
| 26288 |
if (Cmp.getOpcode() == ISD::SETCC) { |
0 |
26288 |
if (Cmp.getOpcode() == ISD::SETCC) { |
0 |
| 26289 |
CC = cast(Cmp.getOperand(2))->get(); |
0 |
26289 |
CC = cast(Cmp.getOperand(2))->get(); |
0 |
| 26290 |
CmpLHS = Cmp.getOperand(0); |
0 |
26290 |
CmpLHS = Cmp.getOperand(0); |
0 |
| 26291 |
Zero = isConstOrConstSplatFP(Cmp.getOperand(1)); |
0 |
26291 |
Zero = isConstOrConstSplatFP(Cmp.getOperand(1)); |
0 |
| 26292 |
} |
--- |
26292 |
} |
--- |
| 26293 |
} |
--- |
26293 |
} |
--- |
| 26294 |
if (Zero && Zero->isZero() && |
0 |
26294 |
if (Zero && Zero->isZero() && |
0 |
| 26295 |
Sqrt.getOperand(0) == CmpLHS && (CC == ISD::SETOLT || |
0 |
26295 |
Sqrt.getOperand(0) == CmpLHS && (CC == ISD::SETOLT || |
0 |
| 26296 |
CC == ISD::SETULT || CC == ISD::SETLT)) { |
0 |
26296 |
CC == ISD::SETULT || CC == ISD::SETLT)) { |
0 |
| 26297 |
// We have: (select (setcc x, [+-]0.0, *lt), NaN, (fsqrt x)) |
--- |
26297 |
// We have: (select (setcc x, [+-]0.0, *lt), NaN, (fsqrt x)) |
--- |
| 26298 |
CombineTo(TheSelect, Sqrt); |
0 |
26298 |
CombineTo(TheSelect, Sqrt); |
0 |
| 26299 |
return true; |
0 |
26299 |
return true; |
0 |
| 26300 |
} |
--- |
26300 |
} |
--- |
| 26301 |
} |
--- |
26301 |
} |
--- |
| 26302 |
} |
--- |
26302 |
} |
--- |
| 26303 |
// Cannot simplify select with vector condition |
--- |
26303 |
// Cannot simplify select with vector condition |
--- |
| 26304 |
if (TheSelect->getOperand(0).getValueType().isVector()) return false; |
0 |
26304 |
if (TheSelect->getOperand(0).getValueType().isVector()) return false; |
0 |
| 26305 |
|
--- |
26305 |
|
--- |
| 26306 |
// If this is a select from two identical things, try to pull the operation |
--- |
26306 |
// If this is a select from two identical things, try to pull the operation |
--- |
| 26307 |
// through the select. |
--- |
26307 |
// through the select. |
--- |
| 26308 |
if (LHS.getOpcode() != RHS.getOpcode() || |
0 |
26308 |
if (LHS.getOpcode() != RHS.getOpcode() || |
0 |
| 26309 |
!LHS.hasOneUse() || !RHS.hasOneUse()) |
0 |
26309 |
!LHS.hasOneUse() || !RHS.hasOneUse()) |
0 |
| 26310 |
return false; |
0 |
26310 |
return false; |
0 |
| 26311 |
|
--- |
26311 |
|
--- |
| 26312 |
// If this is a load and the token chain is identical, replace the select |
--- |
26312 |
// If this is a load and the token chain is identical, replace the select |
--- |
| 26313 |
// of two loads with a load through a select of the address to load from. |
--- |
26313 |
// of two loads with a load through a select of the address to load from. |
--- |
| 26314 |
// This triggers in things like "select bool X, 10.0, 123.0" after the FP |
--- |
26314 |
// This triggers in things like "select bool X, 10.0, 123.0" after the FP |
--- |
| 26315 |
// constants have been dropped into the constant pool. |
--- |
26315 |
// constants have been dropped into the constant pool. |
--- |
| 26316 |
if (LHS.getOpcode() == ISD::LOAD) { |
0 |
26316 |
if (LHS.getOpcode() == ISD::LOAD) { |
0 |
| 26317 |
LoadSDNode *LLD = cast(LHS); |
0 |
26317 |
LoadSDNode *LLD = cast(LHS); |
0 |
| 26318 |
LoadSDNode *RLD = cast(RHS); |
0 |
26318 |
LoadSDNode *RLD = cast(RHS); |
0 |
| 26319 |
|
--- |
26319 |
|
--- |
| 26320 |
// Token chains must be identical. |
--- |
26320 |
// Token chains must be identical. |
--- |
| 26321 |
if (LHS.getOperand(0) != RHS.getOperand(0) || |
0 |
26321 |
if (LHS.getOperand(0) != RHS.getOperand(0) || |
0 |
| 26322 |
// Do not let this transformation reduce the number of volatile loads. |
--- |
26322 |
// Do not let this transformation reduce the number of volatile loads. |
--- |
| 26323 |
// Be conservative for atomics for the moment |
--- |
26323 |
// Be conservative for atomics for the moment |
--- |
| 26324 |
// TODO: This does appear to be legal for unordered atomics (see D66309) |
--- |
26324 |
// TODO: This does appear to be legal for unordered atomics (see D66309) |
--- |
| 26325 |
!LLD->isSimple() || !RLD->isSimple() || |
0 |
26325 |
!LLD->isSimple() || !RLD->isSimple() || |
0 |
| 26326 |
// FIXME: If either is a pre/post inc/dec load, |
--- |
26326 |
// FIXME: If either is a pre/post inc/dec load, |
--- |
| 26327 |
// we'd need to split out the address adjustment. |
--- |
26327 |
// we'd need to split out the address adjustment. |
--- |
| 26328 |
LLD->isIndexed() || RLD->isIndexed() || |
0 |
26328 |
LLD->isIndexed() || RLD->isIndexed() || |
0 |
| 26329 |
// If this is an EXTLOAD, the VT's must match. |
--- |
26329 |
// If this is an EXTLOAD, the VT's must match. |
--- |
| 26330 |
LLD->getMemoryVT() != RLD->getMemoryVT() || |
0 |
26330 |
LLD->getMemoryVT() != RLD->getMemoryVT() || |
0 |
| 26331 |
// If this is an EXTLOAD, the kind of extension must match. |
--- |
26331 |
// If this is an EXTLOAD, the kind of extension must match. |
--- |
| 26332 |
(LLD->getExtensionType() != RLD->getExtensionType() && |
0 |
26332 |
(LLD->getExtensionType() != RLD->getExtensionType() && |
0 |
| 26333 |
// The only exception is if one of the extensions is anyext. |
--- |
26333 |
// The only exception is if one of the extensions is anyext. |
--- |
| 26334 |
LLD->getExtensionType() != ISD::EXTLOAD && |
0 |
26334 |
LLD->getExtensionType() != ISD::EXTLOAD && |
0 |
| 26335 |
RLD->getExtensionType() != ISD::EXTLOAD) || |
0 |
26335 |
RLD->getExtensionType() != ISD::EXTLOAD) || |
0 |
| 26336 |
// FIXME: this discards src value information. This is |
--- |
26336 |
// FIXME: this discards src value information. This is |
--- |
| 26337 |
// over-conservative. It would be beneficial to be able to remember |
--- |
26337 |
// over-conservative. It would be beneficial to be able to remember |
--- |
| 26338 |
// both potential memory locations. Since we are discarding |
--- |
26338 |
// both potential memory locations. Since we are discarding |
--- |
| 26339 |
// src value info, don't do the transformation if the memory |
--- |
26339 |
// src value info, don't do the transformation if the memory |
--- |
| 26340 |
// locations are not in the default address space. |
--- |
26340 |
// locations are not in the default address space. |
--- |
| 26341 |
LLD->getPointerInfo().getAddrSpace() != 0 || |
0 |
26341 |
LLD->getPointerInfo().getAddrSpace() != 0 || |
0 |
| 26342 |
RLD->getPointerInfo().getAddrSpace() != 0 || |
0 |
26342 |
RLD->getPointerInfo().getAddrSpace() != 0 || |
0 |
| 26343 |
// We can't produce a CMOV of a TargetFrameIndex since we won't |
--- |
26343 |
// We can't produce a CMOV of a TargetFrameIndex since we won't |
--- |
| 26344 |
// generate the address generation required. |
--- |
26344 |
// generate the address generation required. |
--- |
| 26345 |
LLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || |
0 |
26345 |
LLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || |
0 |
| 26346 |
RLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || |
0 |
26346 |
RLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex || |
0 |
| 26347 |
!TLI.isOperationLegalOrCustom(TheSelect->getOpcode(), |
0 |
26347 |
!TLI.isOperationLegalOrCustom(TheSelect->getOpcode(), |
0 |
| 26348 |
LLD->getBasePtr().getValueType())) |
0 |
26348 |
LLD->getBasePtr().getValueType())) |
0 |
| 26349 |
return false; |
0 |
26349 |
return false; |
0 |
| 26350 |
|
--- |
26350 |
|
--- |
| 26351 |
// The loads must not depend on one another. |
--- |
26351 |
// The loads must not depend on one another. |
--- |
| 26352 |
if (LLD->isPredecessorOf(RLD) || RLD->isPredecessorOf(LLD)) |
0 |
26352 |
if (LLD->isPredecessorOf(RLD) || RLD->isPredecessorOf(LLD)) |
0 |
| 26353 |
return false; |
0 |
26353 |
return false; |
0 |
| 26354 |
|
--- |
26354 |
|
--- |
| 26355 |
// Check that the select condition doesn't reach either load. If so, |
--- |
26355 |
// Check that the select condition doesn't reach either load. If so, |
--- |
| 26356 |
// folding this will induce a cycle into the DAG. If not, this is safe to |
--- |
26356 |
// folding this will induce a cycle into the DAG. If not, this is safe to |
--- |
| 26357 |
// xform, so create a select of the addresses. |
--- |
26357 |
// xform, so create a select of the addresses. |
--- |
| 26358 |
|
--- |
26358 |
|
--- |
| 26359 |
SmallPtrSet Visited; |
0 |
26359 |
SmallPtrSet Visited; |
0 |
| 26360 |
SmallVector Worklist; |
0 |
26360 |
SmallVector Worklist; |
0 |
| 26361 |
|
--- |
26361 |
|
--- |
| 26362 |
// Always fail if LLD and RLD are not independent. TheSelect is a |
--- |
26362 |
// Always fail if LLD and RLD are not independent. TheSelect is a |
--- |
| 26363 |
// predecessor to all Nodes in question so we need not search past it. |
--- |
26363 |
// predecessor to all Nodes in question so we need not search past it. |
--- |
| 26364 |
|
--- |
26364 |
|
--- |
| 26365 |
Visited.insert(TheSelect); |
0 |
26365 |
Visited.insert(TheSelect); |
0 |
| 26366 |
Worklist.push_back(LLD); |
0 |
26366 |
Worklist.push_back(LLD); |
0 |
| 26367 |
Worklist.push_back(RLD); |
0 |
26367 |
Worklist.push_back(RLD); |
0 |
| 26368 |
|
--- |
26368 |
|
--- |
| 26369 |
if (SDNode::hasPredecessorHelper(LLD, Visited, Worklist) || |
0 |
26369 |
if (SDNode::hasPredecessorHelper(LLD, Visited, Worklist) || |
0 |
| 26370 |
SDNode::hasPredecessorHelper(RLD, Visited, Worklist)) |
0 |
26370 |
SDNode::hasPredecessorHelper(RLD, Visited, Worklist)) |
0 |
| 26371 |
return false; |
0 |
26371 |
return false; |
0 |
| 26372 |
|
--- |
26372 |
|
--- |
| 26373 |
SDValue Addr; |
0 |
26373 |
SDValue Addr; |
0 |
| 26374 |
if (TheSelect->getOpcode() == ISD::SELECT) { |
0 |
26374 |
if (TheSelect->getOpcode() == ISD::SELECT) { |
0 |
| 26375 |
// We cannot do this optimization if any pair of {RLD, LLD} is a |
--- |
26375 |
// We cannot do this optimization if any pair of {RLD, LLD} is a |
--- |
| 26376 |
// predecessor to {RLD, LLD, CondNode}. As we've already compared the |
--- |
26376 |
// predecessor to {RLD, LLD, CondNode}. As we've already compared the |
--- |
| 26377 |
// Loads, we only need to check if CondNode is a successor to one of the |
--- |
26377 |
// Loads, we only need to check if CondNode is a successor to one of the |
--- |
| 26378 |
// loads. We can further avoid this if there's no use of their chain |
--- |
26378 |
// loads. We can further avoid this if there's no use of their chain |
--- |
| 26379 |
// value. |
--- |
26379 |
// value. |
--- |
| 26380 |
SDNode *CondNode = TheSelect->getOperand(0).getNode(); |
0 |
26380 |
SDNode *CondNode = TheSelect->getOperand(0).getNode(); |
0 |
| 26381 |
Worklist.push_back(CondNode); |
0 |
26381 |
Worklist.push_back(CondNode); |
0 |
| 26382 |
|
--- |
26382 |
|
--- |
| 26383 |
if ((LLD->hasAnyUseOfValue(1) && |
0 |
26383 |
if ((LLD->hasAnyUseOfValue(1) && |
0 |
| 26384 |
SDNode::hasPredecessorHelper(LLD, Visited, Worklist)) || |
0 |
26384 |
SDNode::hasPredecessorHelper(LLD, Visited, Worklist)) || |
0 |
| 26385 |
(RLD->hasAnyUseOfValue(1) && |
0 |
26385 |
(RLD->hasAnyUseOfValue(1) && |
0 |
| 26386 |
SDNode::hasPredecessorHelper(RLD, Visited, Worklist))) |
0 |
26386 |
SDNode::hasPredecessorHelper(RLD, Visited, Worklist))) |
0 |
| 26387 |
return false; |
0 |
26387 |
return false; |
0 |
| 26388 |
|
--- |
26388 |
|
--- |
| 26389 |
Addr = DAG.getSelect(SDLoc(TheSelect), |
0 |
26389 |
Addr = DAG.getSelect(SDLoc(TheSelect), |
0 |
| 26390 |
LLD->getBasePtr().getValueType(), |
0 |
26390 |
LLD->getBasePtr().getValueType(), |
0 |
| 26391 |
TheSelect->getOperand(0), LLD->getBasePtr(), |
0 |
26391 |
TheSelect->getOperand(0), LLD->getBasePtr(), |
0 |
| 26392 |
RLD->getBasePtr()); |
0 |
26392 |
RLD->getBasePtr()); |
0 |
| 26393 |
} else { // Otherwise SELECT_CC |
--- |
26393 |
} else { // Otherwise SELECT_CC |
--- |
| 26394 |
// We cannot do this optimization if any pair of {RLD, LLD} is a |
--- |
26394 |
// We cannot do this optimization if any pair of {RLD, LLD} is a |
--- |
| 26395 |
// predecessor to {RLD, LLD, CondLHS, CondRHS}. As we've already compared |
--- |
26395 |
// predecessor to {RLD, LLD, CondLHS, CondRHS}. As we've already compared |
--- |
| 26396 |
// the Loads, we only need to check if CondLHS/CondRHS is a successor to |
--- |
26396 |
// the Loads, we only need to check if CondLHS/CondRHS is a successor to |
--- |
| 26397 |
// one of the loads. We can further avoid this if there's no use of their |
--- |
26397 |
// one of the loads. We can further avoid this if there's no use of their |
--- |
| 26398 |
// chain value. |
--- |
26398 |
// chain value. |
--- |
| 26399 |
|
--- |
26399 |
|
--- |
| 26400 |
SDNode *CondLHS = TheSelect->getOperand(0).getNode(); |
0 |
26400 |
SDNode *CondLHS = TheSelect->getOperand(0).getNode(); |
0 |
| 26401 |
SDNode *CondRHS = TheSelect->getOperand(1).getNode(); |
0 |
26401 |
SDNode *CondRHS = TheSelect->getOperand(1).getNode(); |
0 |
| 26402 |
Worklist.push_back(CondLHS); |
0 |
26402 |
Worklist.push_back(CondLHS); |
0 |
| 26403 |
Worklist.push_back(CondRHS); |
0 |
26403 |
Worklist.push_back(CondRHS); |
0 |
| 26404 |
|
--- |
26404 |
|
--- |
| 26405 |
if ((LLD->hasAnyUseOfValue(1) && |
0 |
26405 |
if ((LLD->hasAnyUseOfValue(1) && |
0 |
| 26406 |
SDNode::hasPredecessorHelper(LLD, Visited, Worklist)) || |
0 |
26406 |
SDNode::hasPredecessorHelper(LLD, Visited, Worklist)) || |
0 |
| 26407 |
(RLD->hasAnyUseOfValue(1) && |
0 |
26407 |
(RLD->hasAnyUseOfValue(1) && |
0 |
| 26408 |
SDNode::hasPredecessorHelper(RLD, Visited, Worklist))) |
0 |
26408 |
SDNode::hasPredecessorHelper(RLD, Visited, Worklist))) |
0 |
| 26409 |
return false; |
0 |
26409 |
return false; |
0 |
| 26410 |
|
--- |
26410 |
|
--- |
| 26411 |
Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect), |
0 |
26411 |
Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect), |
0 |
| 26412 |
LLD->getBasePtr().getValueType(), |
0 |
26412 |
LLD->getBasePtr().getValueType(), |
0 |
| 26413 |
TheSelect->getOperand(0), |
0 |
26413 |
TheSelect->getOperand(0), |
0 |
| 26414 |
TheSelect->getOperand(1), |
0 |
26414 |
TheSelect->getOperand(1), |
0 |
| 26415 |
LLD->getBasePtr(), RLD->getBasePtr(), |
0 |
26415 |
LLD->getBasePtr(), RLD->getBasePtr(), |
0 |
| 26416 |
TheSelect->getOperand(4)); |
0 |
26416 |
TheSelect->getOperand(4)); |
0 |
| 26417 |
} |
--- |
26417 |
} |
--- |
| 26418 |
|
--- |
26418 |
|
--- |
| 26419 |
SDValue Load; |
0 |
26419 |
SDValue Load; |
0 |
| 26420 |
// It is safe to replace the two loads if they have different alignments, |
--- |
26420 |
// It is safe to replace the two loads if they have different alignments, |
--- |
| 26421 |
// but the new load must be the minimum (most restrictive) alignment of the |
--- |
26421 |
// but the new load must be the minimum (most restrictive) alignment of the |
--- |
| 26422 |
// inputs. |
--- |
26422 |
// inputs. |
--- |
| 26423 |
Align Alignment = std::min(LLD->getAlign(), RLD->getAlign()); |
0 |
26423 |
Align Alignment = std::min(LLD->getAlign(), RLD->getAlign()); |
0 |
| 26424 |
MachineMemOperand::Flags MMOFlags = LLD->getMemOperand()->getFlags(); |
0 |
26424 |
MachineMemOperand::Flags MMOFlags = LLD->getMemOperand()->getFlags(); |
0 |
| 26425 |
if (!RLD->isInvariant()) |
0 |
26425 |
if (!RLD->isInvariant()) |
0 |
| 26426 |
MMOFlags &= ~MachineMemOperand::MOInvariant; |
0 |
26426 |
MMOFlags &= ~MachineMemOperand::MOInvariant; |
0 |
| 26427 |
if (!RLD->isDereferenceable()) |
0 |
26427 |
if (!RLD->isDereferenceable()) |
0 |
| 26428 |
MMOFlags &= ~MachineMemOperand::MODereferenceable; |
0 |
26428 |
MMOFlags &= ~MachineMemOperand::MODereferenceable; |
0 |
| 26429 |
if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { |
0 |
26429 |
if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { |
0 |
| 26430 |
// FIXME: Discards pointer and AA info. |
--- |
26430 |
// FIXME: Discards pointer and AA info. |
--- |
| 26431 |
Load = DAG.getLoad(TheSelect->getValueType(0), SDLoc(TheSelect), |
0 |
26431 |
Load = DAG.getLoad(TheSelect->getValueType(0), SDLoc(TheSelect), |
0 |
| 26432 |
LLD->getChain(), Addr, MachinePointerInfo(), Alignment, |
0 |
26432 |
LLD->getChain(), Addr, MachinePointerInfo(), Alignment, |
0 |
| 26433 |
MMOFlags); |
--- |
26433 |
MMOFlags); |
--- |
| 26434 |
} else { |
--- |
26434 |
} else { |
--- |
| 26435 |
// FIXME: Discards pointer and AA info. |
--- |
26435 |
// FIXME: Discards pointer and AA info. |
--- |
| 26436 |
Load = DAG.getExtLoad( |
0 |
26436 |
Load = DAG.getExtLoad( |
0 |
| 26437 |
LLD->getExtensionType() == ISD::EXTLOAD ? RLD->getExtensionType() |
0 |
26437 |
LLD->getExtensionType() == ISD::EXTLOAD ? RLD->getExtensionType() |
0 |
| 26438 |
: LLD->getExtensionType(), |
0 |
26438 |
: LLD->getExtensionType(), |
0 |
| 26439 |
SDLoc(TheSelect), TheSelect->getValueType(0), LLD->getChain(), Addr, |
0 |
26439 |
SDLoc(TheSelect), TheSelect->getValueType(0), LLD->getChain(), Addr, |
0 |
| 26440 |
MachinePointerInfo(), LLD->getMemoryVT(), Alignment, MMOFlags); |
--- |
26440 |
MachinePointerInfo(), LLD->getMemoryVT(), Alignment, MMOFlags); |
--- |
| 26441 |
} |
--- |
26441 |
} |
--- |
| 26442 |
|
--- |
26442 |
|
--- |
| 26443 |
// Users of the select now use the result of the load. |
--- |
26443 |
// Users of the select now use the result of the load. |
--- |
| 26444 |
CombineTo(TheSelect, Load); |
0 |
26444 |
CombineTo(TheSelect, Load); |
0 |
| 26445 |
|
--- |
26445 |
|
--- |
| 26446 |
// Users of the old loads now use the new load's chain. We know the |
--- |
26446 |
// Users of the old loads now use the new load's chain. We know the |
--- |
| 26447 |
// old-load value is dead now. |
--- |
26447 |
// old-load value is dead now. |
--- |
| 26448 |
CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); |
0 |
26448 |
CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); |
0 |
| 26449 |
CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); |
0 |
26449 |
CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); |
0 |
| 26450 |
return true; |
0 |
26450 |
return true; |
0 |
| 26451 |
} |
0 |
26451 |
} |
0 |
| 26452 |
|
--- |
26452 |
|
--- |
| 26453 |
return false; |
0 |
26453 |
return false; |
0 |
| 26454 |
} |
--- |
26454 |
} |
--- |
| 26455 |
|
--- |
26455 |
|
--- |
| 26456 |
/// Try to fold an expression of the form (N0 cond N1) ? N2 : N3 to a shift and |
--- |
26456 |
/// Try to fold an expression of the form (N0 cond N1) ? N2 : N3 to a shift and |
--- |
| 26457 |
/// bitwise 'and'. |
--- |
26457 |
/// bitwise 'and'. |
--- |
| 26458 |
SDValue DAGCombiner::foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, |
0 |
26458 |
SDValue DAGCombiner::foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, |
0 |
| 26459 |
SDValue N1, SDValue N2, SDValue N3, |
--- |
26459 |
SDValue N1, SDValue N2, SDValue N3, |
--- |
| 26460 |
ISD::CondCode CC) { |
--- |
26460 |
ISD::CondCode CC) { |
--- |
| 26461 |
// If this is a select where the false operand is zero and the compare is a |
--- |
26461 |
// If this is a select where the false operand is zero and the compare is a |
--- |
| 26462 |
// check of the sign bit, see if we can perform the "gzip trick": |
--- |
26462 |
// check of the sign bit, see if we can perform the "gzip trick": |
--- |
| 26463 |
// select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A |
--- |
26463 |
// select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A |
--- |
| 26464 |
// select_cc setgt X, 0, A, 0 -> and (not (sra X, size(X)-1)), A |
--- |
26464 |
// select_cc setgt X, 0, A, 0 -> and (not (sra X, size(X)-1)), A |
--- |
| 26465 |
EVT XType = N0.getValueType(); |
0 |
26465 |
EVT XType = N0.getValueType(); |
0 |
| 26466 |
EVT AType = N2.getValueType(); |
0 |
26466 |
EVT AType = N2.getValueType(); |
0 |
| 26467 |
if (!isNullConstant(N3) || !XType.bitsGE(AType)) |
0 |
26467 |
if (!isNullConstant(N3) || !XType.bitsGE(AType)) |
0 |
| 26468 |
return SDValue(); |
0 |
26468 |
return SDValue(); |
0 |
| 26469 |
|
--- |
26469 |
|
--- |
| 26470 |
// If the comparison is testing for a positive value, we have to invert |
--- |
26470 |
// If the comparison is testing for a positive value, we have to invert |
--- |
| 26471 |
// the sign bit mask, so only do that transform if the target has a bitwise |
--- |
26471 |
// the sign bit mask, so only do that transform if the target has a bitwise |
--- |
| 26472 |
// 'and not' instruction (the invert is free). |
--- |
26472 |
// 'and not' instruction (the invert is free). |
--- |
| 26473 |
if (CC == ISD::SETGT && TLI.hasAndNot(N2)) { |
0 |
26473 |
if (CC == ISD::SETGT && TLI.hasAndNot(N2)) { |
0 |
| 26474 |
// (X > -1) ? A : 0 |
--- |
26474 |
// (X > -1) ? A : 0 |
--- |
| 26475 |
// (X > 0) ? X : 0 <-- This is canonical signed max. |
--- |
26475 |
// (X > 0) ? X : 0 <-- This is canonical signed max. |
--- |
| 26476 |
if (!(isAllOnesConstant(N1) || (isNullConstant(N1) && N0 == N2))) |
0 |
26476 |
if (!(isAllOnesConstant(N1) || (isNullConstant(N1) && N0 == N2))) |
0 |
| 26477 |
return SDValue(); |
0 |
26477 |
return SDValue(); |
0 |
| 26478 |
} else if (CC == ISD::SETLT) { |
0 |
26478 |
} else if (CC == ISD::SETLT) { |
0 |
| 26479 |
// (X < 0) ? A : 0 |
--- |
26479 |
// (X < 0) ? A : 0 |
--- |
| 26480 |
// (X < 1) ? X : 0 <-- This is un-canonicalized signed min. |
--- |
26480 |
// (X < 1) ? X : 0 <-- This is un-canonicalized signed min. |
--- |
| 26481 |
if (!(isNullConstant(N1) || (isOneConstant(N1) && N0 == N2))) |
0 |
26481 |
if (!(isNullConstant(N1) || (isOneConstant(N1) && N0 == N2))) |
0 |
| 26482 |
return SDValue(); |
0 |
26482 |
return SDValue(); |
0 |
| 26483 |
} else { |
--- |
26483 |
} else { |
--- |
| 26484 |
return SDValue(); |
0 |
26484 |
return SDValue(); |
0 |
| 26485 |
} |
--- |
26485 |
} |
--- |
| 26486 |
|
--- |
26486 |
|
--- |
| 26487 |
// and (sra X, size(X)-1), A -> "and (srl X, C2), A" iff A is a single-bit |
--- |
26487 |
// and (sra X, size(X)-1), A -> "and (srl X, C2), A" iff A is a single-bit |
--- |
| 26488 |
// constant. |
--- |
26488 |
// constant. |
--- |
| 26489 |
EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType()); |
0 |
26489 |
EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType()); |
0 |
| 26490 |
auto *N2C = dyn_cast(N2.getNode()); |
0 |
26490 |
auto *N2C = dyn_cast(N2.getNode()); |
0 |
| 26491 |
if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue() - 1)) == 0)) { |
0 |
26491 |
if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue() - 1)) == 0)) { |
0 |
| 26492 |
unsigned ShCt = XType.getSizeInBits() - N2C->getAPIntValue().logBase2() - 1; |
0 |
26492 |
unsigned ShCt = XType.getSizeInBits() - N2C->getAPIntValue().logBase2() - 1; |
0 |
| 26493 |
if (!TLI.shouldAvoidTransformToShift(XType, ShCt)) { |
0 |
26493 |
if (!TLI.shouldAvoidTransformToShift(XType, ShCt)) { |
0 |
| 26494 |
SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy); |
0 |
26494 |
SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy); |
0 |
| 26495 |
SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt); |
0 |
26495 |
SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt); |
0 |
| 26496 |
AddToWorklist(Shift.getNode()); |
0 |
26496 |
AddToWorklist(Shift.getNode()); |
0 |
| 26497 |
|
--- |
26497 |
|
--- |
| 26498 |
if (XType.bitsGT(AType)) { |
0 |
26498 |
if (XType.bitsGT(AType)) { |
0 |
| 26499 |
Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); |
0 |
26499 |
Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); |
0 |
| 26500 |
AddToWorklist(Shift.getNode()); |
0 |
26500 |
AddToWorklist(Shift.getNode()); |
0 |
| 26501 |
} |
--- |
26501 |
} |
--- |
| 26502 |
|
--- |
26502 |
|
--- |
| 26503 |
if (CC == ISD::SETGT) |
0 |
26503 |
if (CC == ISD::SETGT) |
0 |
| 26504 |
Shift = DAG.getNOT(DL, Shift, AType); |
0 |
26504 |
Shift = DAG.getNOT(DL, Shift, AType); |
0 |
| 26505 |
|
--- |
26505 |
|
--- |
| 26506 |
return DAG.getNode(ISD::AND, DL, AType, Shift, N2); |
0 |
26506 |
return DAG.getNode(ISD::AND, DL, AType, Shift, N2); |
0 |
| 26507 |
} |
--- |
26507 |
} |
--- |
| 26508 |
} |
--- |
26508 |
} |
--- |
| 26509 |
|
--- |
26509 |
|
--- |
| 26510 |
unsigned ShCt = XType.getSizeInBits() - 1; |
0 |
26510 |
unsigned ShCt = XType.getSizeInBits() - 1; |
0 |
| 26511 |
if (TLI.shouldAvoidTransformToShift(XType, ShCt)) |
0 |
26511 |
if (TLI.shouldAvoidTransformToShift(XType, ShCt)) |
0 |
| 26512 |
return SDValue(); |
0 |
26512 |
return SDValue(); |
0 |
| 26513 |
|
--- |
26513 |
|
--- |
| 26514 |
SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy); |
0 |
26514 |
SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy); |
0 |
| 26515 |
SDValue Shift = DAG.getNode(ISD::SRA, DL, XType, N0, ShiftAmt); |
0 |
26515 |
SDValue Shift = DAG.getNode(ISD::SRA, DL, XType, N0, ShiftAmt); |
0 |
| 26516 |
AddToWorklist(Shift.getNode()); |
0 |
26516 |
AddToWorklist(Shift.getNode()); |
0 |
| 26517 |
|
--- |
26517 |
|
--- |
| 26518 |
if (XType.bitsGT(AType)) { |
0 |
26518 |
if (XType.bitsGT(AType)) { |
0 |
| 26519 |
Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); |
0 |
26519 |
Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); |
0 |
| 26520 |
AddToWorklist(Shift.getNode()); |
0 |
26520 |
AddToWorklist(Shift.getNode()); |
0 |
| 26521 |
} |
--- |
26521 |
} |
--- |
| 26522 |
|
--- |
26522 |
|
--- |
| 26523 |
if (CC == ISD::SETGT) |
0 |
26523 |
if (CC == ISD::SETGT) |
0 |
| 26524 |
Shift = DAG.getNOT(DL, Shift, AType); |
0 |
26524 |
Shift = DAG.getNOT(DL, Shift, AType); |
0 |
| 26525 |
|
--- |
26525 |
|
--- |
| 26526 |
return DAG.getNode(ISD::AND, DL, AType, Shift, N2); |
0 |
26526 |
return DAG.getNode(ISD::AND, DL, AType, Shift, N2); |
0 |
| 26527 |
} |
--- |
26527 |
} |
--- |
| 26528 |
|
--- |
26528 |
|
--- |
| 26529 |
// Fold select(cc, binop(), binop()) -> binop(select(), select()) etc. |
--- |
26529 |
// Fold select(cc, binop(), binop()) -> binop(select(), select()) etc. |
--- |
| 26530 |
SDValue DAGCombiner::foldSelectOfBinops(SDNode *N) { |
0 |
26530 |
SDValue DAGCombiner::foldSelectOfBinops(SDNode *N) { |
0 |
| 26531 |
SDValue N0 = N->getOperand(0); |
0 |
26531 |
SDValue N0 = N->getOperand(0); |
0 |
| 26532 |
SDValue N1 = N->getOperand(1); |
0 |
26532 |
SDValue N1 = N->getOperand(1); |
0 |
| 26533 |
SDValue N2 = N->getOperand(2); |
0 |
26533 |
SDValue N2 = N->getOperand(2); |
0 |
| 26534 |
EVT VT = N->getValueType(0); |
0 |
26534 |
EVT VT = N->getValueType(0); |
0 |
| 26535 |
SDLoc DL(N); |
0 |
26535 |
SDLoc DL(N); |
0 |
| 26536 |
|
--- |
26536 |
|
--- |
| 26537 |
unsigned BinOpc = N1.getOpcode(); |
0 |
26537 |
unsigned BinOpc = N1.getOpcode(); |
0 |
| 26538 |
if (!TLI.isBinOp(BinOpc) || (N2.getOpcode() != BinOpc)) |
0 |
26538 |
if (!TLI.isBinOp(BinOpc) || (N2.getOpcode() != BinOpc)) |
0 |
| 26539 |
return SDValue(); |
0 |
26539 |
return SDValue(); |
0 |
| 26540 |
|
--- |
26540 |
|
--- |
| 26541 |
// The use checks are intentionally on SDNode because we may be dealing |
--- |
26541 |
// The use checks are intentionally on SDNode because we may be dealing |
--- |
| 26542 |
// with opcodes that produce more than one SDValue. |
--- |
26542 |
// with opcodes that produce more than one SDValue. |
--- |
| 26543 |
// TODO: Do we really need to check N0 (the condition operand of the select)? |
--- |
26543 |
// TODO: Do we really need to check N0 (the condition operand of the select)? |
--- |
| 26544 |
// But removing that clause could cause an infinite loop... |
--- |
26544 |
// But removing that clause could cause an infinite loop... |
--- |
| 26545 |
if (!N0->hasOneUse() || !N1->hasOneUse() || !N2->hasOneUse()) |
0 |
26545 |
if (!N0->hasOneUse() || !N1->hasOneUse() || !N2->hasOneUse()) |
0 |
| 26546 |
return SDValue(); |
0 |
26546 |
return SDValue(); |
0 |
| 26547 |
|
--- |
26547 |
|
--- |
| 26548 |
// Binops may include opcodes that return multiple values, so all values |
--- |
26548 |
// Binops may include opcodes that return multiple values, so all values |
--- |
| 26549 |
// must be created/propagated from the newly created binops below. |
--- |
26549 |
// must be created/propagated from the newly created binops below. |
--- |
| 26550 |
SDVTList OpVTs = N1->getVTList(); |
0 |
26550 |
SDVTList OpVTs = N1->getVTList(); |
0 |
| 26551 |
|
--- |
26551 |
|
--- |
| 26552 |
// Fold select(cond, binop(x, y), binop(z, y)) |
--- |
26552 |
// Fold select(cond, binop(x, y), binop(z, y)) |
--- |
| 26553 |
// --> binop(select(cond, x, z), y) |
--- |
26553 |
// --> binop(select(cond, x, z), y) |
--- |
| 26554 |
if (N1.getOperand(1) == N2.getOperand(1)) { |
0 |
26554 |
if (N1.getOperand(1) == N2.getOperand(1)) { |
0 |
| 26555 |
SDValue NewSel = |
--- |
26555 |
SDValue NewSel = |
--- |
| 26556 |
DAG.getSelect(DL, VT, N0, N1.getOperand(0), N2.getOperand(0)); |
0 |
26556 |
DAG.getSelect(DL, VT, N0, N1.getOperand(0), N2.getOperand(0)); |
0 |
| 26557 |
SDValue NewBinOp = DAG.getNode(BinOpc, DL, OpVTs, NewSel, N1.getOperand(1)); |
0 |
26557 |
SDValue NewBinOp = DAG.getNode(BinOpc, DL, OpVTs, NewSel, N1.getOperand(1)); |
0 |
| 26558 |
NewBinOp->setFlags(N1->getFlags()); |
0 |
26558 |
NewBinOp->setFlags(N1->getFlags()); |
0 |
| 26559 |
NewBinOp->intersectFlagsWith(N2->getFlags()); |
0 |
26559 |
NewBinOp->intersectFlagsWith(N2->getFlags()); |
0 |
| 26560 |
return NewBinOp; |
0 |
26560 |
return NewBinOp; |
0 |
| 26561 |
} |
--- |
26561 |
} |
--- |
| 26562 |
|
--- |
26562 |
|
--- |
| 26563 |
// Fold select(cond, binop(x, y), binop(x, z)) |
--- |
26563 |
// Fold select(cond, binop(x, y), binop(x, z)) |
--- |
| 26564 |
// --> binop(x, select(cond, y, z)) |
--- |
26564 |
// --> binop(x, select(cond, y, z)) |
--- |
| 26565 |
// Second op VT might be different (e.g. shift amount type) |
--- |
26565 |
// Second op VT might be different (e.g. shift amount type) |
--- |
| 26566 |
if (N1.getOperand(0) == N2.getOperand(0) && |
0 |
26566 |
if (N1.getOperand(0) == N2.getOperand(0) && |
0 |
| 26567 |
VT == N1.getOperand(1).getValueType() && |
0 |
26567 |
VT == N1.getOperand(1).getValueType() && |
0 |
| 26568 |
VT == N2.getOperand(1).getValueType()) { |
0 |
26568 |
VT == N2.getOperand(1).getValueType()) { |
0 |
| 26569 |
SDValue NewSel = |
--- |
26569 |
SDValue NewSel = |
--- |
| 26570 |
DAG.getSelect(DL, VT, N0, N1.getOperand(1), N2.getOperand(1)); |
0 |
26570 |
DAG.getSelect(DL, VT, N0, N1.getOperand(1), N2.getOperand(1)); |
0 |
| 26571 |
SDValue NewBinOp = DAG.getNode(BinOpc, DL, OpVTs, N1.getOperand(0), NewSel); |
0 |
26571 |
SDValue NewBinOp = DAG.getNode(BinOpc, DL, OpVTs, N1.getOperand(0), NewSel); |
0 |
| 26572 |
NewBinOp->setFlags(N1->getFlags()); |
0 |
26572 |
NewBinOp->setFlags(N1->getFlags()); |
0 |
| 26573 |
NewBinOp->intersectFlagsWith(N2->getFlags()); |
0 |
26573 |
NewBinOp->intersectFlagsWith(N2->getFlags()); |
0 |
| 26574 |
return NewBinOp; |
0 |
26574 |
return NewBinOp; |
0 |
| 26575 |
} |
--- |
26575 |
} |
--- |
| 26576 |
|
--- |
26576 |
|
--- |
| 26577 |
// TODO: Handle isCommutativeBinOp patterns as well? |
--- |
26577 |
// TODO: Handle isCommutativeBinOp patterns as well? |
--- |
| 26578 |
return SDValue(); |
0 |
26578 |
return SDValue(); |
0 |
| 26579 |
} |
0 |
26579 |
} |
0 |
| 26580 |
|
--- |
26580 |
|
--- |
| 26581 |
// Transform (fneg/fabs (bitconvert x)) to avoid loading constant pool values. |
--- |
26581 |
// Transform (fneg/fabs (bitconvert x)) to avoid loading constant pool values. |
--- |
| 26582 |
SDValue DAGCombiner::foldSignChangeInBitcast(SDNode *N) { |
0 |
26582 |
SDValue DAGCombiner::foldSignChangeInBitcast(SDNode *N) { |
0 |
| 26583 |
SDValue N0 = N->getOperand(0); |
0 |
26583 |
SDValue N0 = N->getOperand(0); |
0 |
| 26584 |
EVT VT = N->getValueType(0); |
0 |
26584 |
EVT VT = N->getValueType(0); |
0 |
| 26585 |
bool IsFabs = N->getOpcode() == ISD::FABS; |
0 |
26585 |
bool IsFabs = N->getOpcode() == ISD::FABS; |
0 |
| 26586 |
bool IsFree = IsFabs ? TLI.isFAbsFree(VT) : TLI.isFNegFree(VT); |
0 |
26586 |
bool IsFree = IsFabs ? TLI.isFAbsFree(VT) : TLI.isFNegFree(VT); |
0 |
| 26587 |
|
--- |
26587 |
|
--- |
| 26588 |
if (IsFree || N0.getOpcode() != ISD::BITCAST || !N0.hasOneUse()) |
0 |
26588 |
if (IsFree || N0.getOpcode() != ISD::BITCAST || !N0.hasOneUse()) |
0 |
| 26589 |
return SDValue(); |
0 |
26589 |
return SDValue(); |
0 |
| 26590 |
|
--- |
26590 |
|
--- |
| 26591 |
SDValue Int = N0.getOperand(0); |
0 |
26591 |
SDValue Int = N0.getOperand(0); |
0 |
| 26592 |
EVT IntVT = Int.getValueType(); |
0 |
26592 |
EVT IntVT = Int.getValueType(); |
0 |
| 26593 |
|
--- |
26593 |
|
--- |
| 26594 |
// The operand to cast should be integer. |
--- |
26594 |
// The operand to cast should be integer. |
--- |
| 26595 |
if (!IntVT.isInteger() || IntVT.isVector()) |
0 |
26595 |
if (!IntVT.isInteger() || IntVT.isVector()) |
0 |
| 26596 |
return SDValue(); |
0 |
26596 |
return SDValue(); |
0 |
| 26597 |
|
--- |
26597 |
|
--- |
| 26598 |
// (fneg (bitconvert x)) -> (bitconvert (xor x sign)) |
--- |
26598 |
// (fneg (bitconvert x)) -> (bitconvert (xor x sign)) |
--- |
| 26599 |
// (fabs (bitconvert x)) -> (bitconvert (and x ~sign)) |
--- |
26599 |
// (fabs (bitconvert x)) -> (bitconvert (and x ~sign)) |
--- |
| 26600 |
APInt SignMask; |
0 |
26600 |
APInt SignMask; |
0 |
| 26601 |
if (N0.getValueType().isVector()) { |
0 |
26601 |
if (N0.getValueType().isVector()) { |
0 |
| 26602 |
// For vector, create a sign mask (0x80...) or its inverse (for fabs, |
--- |
26602 |
// For vector, create a sign mask (0x80...) or its inverse (for fabs, |
--- |
| 26603 |
// 0x7f...) per element and splat it. |
--- |
26603 |
// 0x7f...) per element and splat it. |
--- |
| 26604 |
SignMask = APInt::getSignMask(N0.getScalarValueSizeInBits()); |
0 |
26604 |
SignMask = APInt::getSignMask(N0.getScalarValueSizeInBits()); |
0 |
| 26605 |
if (IsFabs) |
0 |
26605 |
if (IsFabs) |
0 |
| 26606 |
SignMask = ~SignMask; |
0 |
26606 |
SignMask = ~SignMask; |
0 |
| 26607 |
SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); |
0 |
26607 |
SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); |
0 |
| 26608 |
} else { |
--- |
26608 |
} else { |
--- |
| 26609 |
// For scalar, just use the sign mask (0x80... or the inverse, 0x7f...) |
--- |
26609 |
// For scalar, just use the sign mask (0x80... or the inverse, 0x7f...) |
--- |
| 26610 |
SignMask = APInt::getSignMask(IntVT.getSizeInBits()); |
0 |
26610 |
SignMask = APInt::getSignMask(IntVT.getSizeInBits()); |
0 |
| 26611 |
if (IsFabs) |
0 |
26611 |
if (IsFabs) |
0 |
| 26612 |
SignMask = ~SignMask; |
0 |
26612 |
SignMask = ~SignMask; |
0 |
| 26613 |
} |
--- |
26613 |
} |
--- |
| 26614 |
SDLoc DL(N0); |
0 |
26614 |
SDLoc DL(N0); |
0 |
| 26615 |
Int = DAG.getNode(IsFabs ? ISD::AND : ISD::XOR, DL, IntVT, Int, |
0 |
26615 |
Int = DAG.getNode(IsFabs ? ISD::AND : ISD::XOR, DL, IntVT, Int, |
0 |
| 26616 |
DAG.getConstant(SignMask, DL, IntVT)); |
0 |
26616 |
DAG.getConstant(SignMask, DL, IntVT)); |
0 |
| 26617 |
AddToWorklist(Int.getNode()); |
0 |
26617 |
AddToWorklist(Int.getNode()); |
0 |
| 26618 |
return DAG.getBitcast(VT, Int); |
0 |
26618 |
return DAG.getBitcast(VT, Int); |
0 |
| 26619 |
} |
0 |
26619 |
} |
0 |
| 26620 |
|
--- |
26620 |
|
--- |
| 26621 |
/// Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" |
--- |
26621 |
/// Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" |
--- |
| 26622 |
/// where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 |
--- |
26622 |
/// where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 |
--- |
| 26623 |
/// in it. This may be a win when the constant is not otherwise available |
--- |
26623 |
/// in it. This may be a win when the constant is not otherwise available |
--- |
| 26624 |
/// because it replaces two constant pool loads with one. |
--- |
26624 |
/// because it replaces two constant pool loads with one. |
--- |
| 26625 |
SDValue DAGCombiner::convertSelectOfFPConstantsToLoadOffset( |
0 |
26625 |
SDValue DAGCombiner::convertSelectOfFPConstantsToLoadOffset( |
0 |
| 26626 |
const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, |
--- |
26626 |
const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, |
--- |
| 26627 |
ISD::CondCode CC) { |
--- |
26627 |
ISD::CondCode CC) { |
--- |
| 26628 |
if (!TLI.reduceSelectOfFPConstantLoads(N0.getValueType())) |
0 |
26628 |
if (!TLI.reduceSelectOfFPConstantLoads(N0.getValueType())) |
0 |
| 26629 |
return SDValue(); |
0 |
26629 |
return SDValue(); |
0 |
| 26630 |
|
--- |
26630 |
|
--- |
| 26631 |
// If we are before legalize types, we want the other legalization to happen |
--- |
26631 |
// If we are before legalize types, we want the other legalization to happen |
--- |
| 26632 |
// first (for example, to avoid messing with soft float). |
--- |
26632 |
// first (for example, to avoid messing with soft float). |
--- |
| 26633 |
auto *TV = dyn_cast(N2); |
0 |
26633 |
auto *TV = dyn_cast(N2); |
0 |
| 26634 |
auto *FV = dyn_cast(N3); |
0 |
26634 |
auto *FV = dyn_cast(N3); |
0 |
| 26635 |
EVT VT = N2.getValueType(); |
0 |
26635 |
EVT VT = N2.getValueType(); |
0 |
| 26636 |
if (!TV || !FV || !TLI.isTypeLegal(VT)) |
0 |
26636 |
if (!TV || !FV || !TLI.isTypeLegal(VT)) |
0 |
| 26637 |
return SDValue(); |
0 |
26637 |
return SDValue(); |
0 |
| 26638 |
|
--- |
26638 |
|
--- |
| 26639 |
// If a constant can be materialized without loads, this does not make sense. |
--- |
26639 |
// If a constant can be materialized without loads, this does not make sense. |
--- |
| 26640 |
if (TLI.getOperationAction(ISD::ConstantFP, VT) == TargetLowering::Legal || |
0 |
26640 |
if (TLI.getOperationAction(ISD::ConstantFP, VT) == TargetLowering::Legal || |
0 |
| 26641 |
TLI.isFPImmLegal(TV->getValueAPF(), TV->getValueType(0), ForCodeSize) || |
0 |
26641 |
TLI.isFPImmLegal(TV->getValueAPF(), TV->getValueType(0), ForCodeSize) || |
0 |
| 26642 |
TLI.isFPImmLegal(FV->getValueAPF(), FV->getValueType(0), ForCodeSize)) |
0 |
26642 |
TLI.isFPImmLegal(FV->getValueAPF(), FV->getValueType(0), ForCodeSize)) |
0 |
| 26643 |
return SDValue(); |
0 |
26643 |
return SDValue(); |
0 |
| 26644 |
|
--- |
26644 |
|
--- |
| 26645 |
// If both constants have multiple uses, then we won't need to do an extra |
--- |
26645 |
// If both constants have multiple uses, then we won't need to do an extra |
--- |
| 26646 |
// load. The values are likely around in registers for other users. |
--- |
26646 |
// load. The values are likely around in registers for other users. |
--- |
| 26647 |
if (!TV->hasOneUse() && !FV->hasOneUse()) |
0 |
26647 |
if (!TV->hasOneUse() && !FV->hasOneUse()) |
0 |
| 26648 |
return SDValue(); |
0 |
26648 |
return SDValue(); |
0 |
| 26649 |
|
--- |
26649 |
|
--- |
| 26650 |
Constant *Elts[] = { const_cast(FV->getConstantFPValue()), |
0 |
26650 |
Constant *Elts[] = { const_cast(FV->getConstantFPValue()), |
0 |
| 26651 |
const_cast(TV->getConstantFPValue()) }; |
0 |
26651 |
const_cast(TV->getConstantFPValue()) }; |
0 |
| 26652 |
Type *FPTy = Elts[0]->getType(); |
0 |
26652 |
Type *FPTy = Elts[0]->getType(); |
0 |
| 26653 |
const DataLayout &TD = DAG.getDataLayout(); |
0 |
26653 |
const DataLayout &TD = DAG.getDataLayout(); |
0 |
| 26654 |
|
--- |
26654 |
|
--- |
| 26655 |
// Create a ConstantArray of the two constants. |
--- |
26655 |
// Create a ConstantArray of the two constants. |
--- |
| 26656 |
Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); |
0 |
26656 |
Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); |
0 |
| 26657 |
SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(DAG.getDataLayout()), |
0 |
26657 |
SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(DAG.getDataLayout()), |
0 |
| 26658 |
TD.getPrefTypeAlign(FPTy)); |
--- |
26658 |
TD.getPrefTypeAlign(FPTy)); |
--- |
| 26659 |
Align Alignment = cast(CPIdx)->getAlign(); |
0 |
26659 |
Align Alignment = cast(CPIdx)->getAlign(); |
0 |
| 26660 |
|
--- |
26660 |
|
--- |
| 26661 |
// Get offsets to the 0 and 1 elements of the array, so we can select between |
--- |
26661 |
// Get offsets to the 0 and 1 elements of the array, so we can select between |
--- |
| 26662 |
// them. |
--- |
26662 |
// them. |
--- |
| 26663 |
SDValue Zero = DAG.getIntPtrConstant(0, DL); |
0 |
26663 |
SDValue Zero = DAG.getIntPtrConstant(0, DL); |
0 |
| 26664 |
unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); |
0 |
26664 |
unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); |
0 |
| 26665 |
SDValue One = DAG.getIntPtrConstant(EltSize, SDLoc(FV)); |
0 |
26665 |
SDValue One = DAG.getIntPtrConstant(EltSize, SDLoc(FV)); |
0 |
| 26666 |
SDValue Cond = |
--- |
26666 |
SDValue Cond = |
--- |
| 26667 |
DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()), N0, N1, CC); |
0 |
26667 |
DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()), N0, N1, CC); |
0 |
| 26668 |
AddToWorklist(Cond.getNode()); |
0 |
26668 |
AddToWorklist(Cond.getNode()); |
0 |
| 26669 |
SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(), Cond, One, Zero); |
0 |
26669 |
SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(), Cond, One, Zero); |
0 |
| 26670 |
AddToWorklist(CstOffset.getNode()); |
0 |
26670 |
AddToWorklist(CstOffset.getNode()); |
0 |
| 26671 |
CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx, CstOffset); |
0 |
26671 |
CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx, CstOffset); |
0 |
| 26672 |
AddToWorklist(CPIdx.getNode()); |
0 |
26672 |
AddToWorklist(CPIdx.getNode()); |
0 |
| 26673 |
return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, |
0 |
26673 |
return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, |
0 |
| 26674 |
MachinePointerInfo::getConstantPool( |
--- |
26674 |
MachinePointerInfo::getConstantPool( |
--- |
| 26675 |
DAG.getMachineFunction()), Alignment); |
0 |
26675 |
DAG.getMachineFunction()), Alignment); |
0 |
| 26676 |
} |
--- |
26676 |
} |
--- |
| 26677 |
|
--- |
26677 |
|
--- |
| 26678 |
/// Simplify an expression of the form (N0 cond N1) ? N2 : N3 |
--- |
26678 |
/// Simplify an expression of the form (N0 cond N1) ? N2 : N3 |
--- |
| 26679 |
/// where 'cond' is the comparison specified by CC. |
--- |
26679 |
/// where 'cond' is the comparison specified by CC. |
--- |
| 26680 |
SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1, |
0 |
26680 |
SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1, |
0 |
| 26681 |
SDValue N2, SDValue N3, ISD::CondCode CC, |
--- |
26681 |
SDValue N2, SDValue N3, ISD::CondCode CC, |
--- |
| 26682 |
bool NotExtCompare) { |
--- |
26682 |
bool NotExtCompare) { |
--- |
| 26683 |
// (x ? y : y) -> y. |
--- |
26683 |
// (x ? y : y) -> y. |
--- |
| 26684 |
if (N2 == N3) return N2; |
0 |
26684 |
if (N2 == N3) return N2; |
0 |
| 26685 |
|
--- |
26685 |
|
--- |
| 26686 |
EVT CmpOpVT = N0.getValueType(); |
0 |
26686 |
EVT CmpOpVT = N0.getValueType(); |
0 |
| 26687 |
EVT CmpResVT = getSetCCResultType(CmpOpVT); |
0 |
26687 |
EVT CmpResVT = getSetCCResultType(CmpOpVT); |
0 |
| 26688 |
EVT VT = N2.getValueType(); |
0 |
26688 |
EVT VT = N2.getValueType(); |
0 |
| 26689 |
auto *N1C = dyn_cast(N1.getNode()); |
0 |
26689 |
auto *N1C = dyn_cast(N1.getNode()); |
0 |
| 26690 |
auto *N2C = dyn_cast(N2.getNode()); |
0 |
26690 |
auto *N2C = dyn_cast(N2.getNode()); |
0 |
| 26691 |
auto *N3C = dyn_cast(N3.getNode()); |
0 |
26691 |
auto *N3C = dyn_cast(N3.getNode()); |
0 |
| 26692 |
|
--- |
26692 |
|
--- |
| 26693 |
// Determine if the condition we're dealing with is constant. |
--- |
26693 |
// Determine if the condition we're dealing with is constant. |
--- |
| 26694 |
if (SDValue SCC = DAG.FoldSetCC(CmpResVT, N0, N1, CC, DL)) { |
0 |
26694 |
if (SDValue SCC = DAG.FoldSetCC(CmpResVT, N0, N1, CC, DL)) { |
0 |
| 26695 |
AddToWorklist(SCC.getNode()); |
0 |
26695 |
AddToWorklist(SCC.getNode()); |
0 |
| 26696 |
if (auto *SCCC = dyn_cast(SCC)) { |
0 |
26696 |
if (auto *SCCC = dyn_cast(SCC)) { |
0 |
| 26697 |
// fold select_cc true, x, y -> x |
--- |
26697 |
// fold select_cc true, x, y -> x |
--- |
| 26698 |
// fold select_cc false, x, y -> y |
--- |
26698 |
// fold select_cc false, x, y -> y |
--- |
| 26699 |
return !(SCCC->isZero()) ? N2 : N3; |
0 |
26699 |
return !(SCCC->isZero()) ? N2 : N3; |
0 |
| 26700 |
} |
--- |
26700 |
} |
--- |
| 26701 |
} |
--- |
26701 |
} |
--- |
| 26702 |
|
--- |
26702 |
|
--- |
| 26703 |
if (SDValue V = |
0 |
26703 |
if (SDValue V = |
0 |
| 26704 |
convertSelectOfFPConstantsToLoadOffset(DL, N0, N1, N2, N3, CC)) |
0 |
26704 |
convertSelectOfFPConstantsToLoadOffset(DL, N0, N1, N2, N3, CC)) |
0 |
| 26705 |
return V; |
0 |
26705 |
return V; |
0 |
| 26706 |
|
--- |
26706 |
|
--- |
| 26707 |
if (SDValue V = foldSelectCCToShiftAnd(DL, N0, N1, N2, N3, CC)) |
0 |
26707 |
if (SDValue V = foldSelectCCToShiftAnd(DL, N0, N1, N2, N3, CC)) |
0 |
| 26708 |
return V; |
0 |
26708 |
return V; |
0 |
| 26709 |
|
--- |
26709 |
|
--- |
| 26710 |
// fold (select_cc seteq (and x, y), 0, 0, A) -> (and (sra (shl x)) A) |
--- |
26710 |
// fold (select_cc seteq (and x, y), 0, 0, A) -> (and (sra (shl x)) A) |
--- |
| 26711 |
// where y is has a single bit set. |
--- |
26711 |
// where y is has a single bit set. |
--- |
| 26712 |
// A plaintext description would be, we can turn the SELECT_CC into an AND |
--- |
26712 |
// A plaintext description would be, we can turn the SELECT_CC into an AND |
--- |
| 26713 |
// when the condition can be materialized as an all-ones register. Any |
--- |
26713 |
// when the condition can be materialized as an all-ones register. Any |
--- |
| 26714 |
// single bit-test can be materialized as an all-ones register with |
--- |
26714 |
// single bit-test can be materialized as an all-ones register with |
--- |
| 26715 |
// shift-left and shift-right-arith. |
--- |
26715 |
// shift-left and shift-right-arith. |
--- |
| 26716 |
if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && |
0 |
26716 |
if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && |
0 |
| 26717 |
N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) { |
0 |
26717 |
N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) { |
0 |
| 26718 |
SDValue AndLHS = N0->getOperand(0); |
0 |
26718 |
SDValue AndLHS = N0->getOperand(0); |
0 |
| 26719 |
auto *ConstAndRHS = dyn_cast(N0->getOperand(1)); |
0 |
26719 |
auto *ConstAndRHS = dyn_cast(N0->getOperand(1)); |
0 |
| 26720 |
if (ConstAndRHS && ConstAndRHS->getAPIntValue().popcount() == 1) { |
0 |
26720 |
if (ConstAndRHS && ConstAndRHS->getAPIntValue().popcount() == 1) { |
0 |
| 26721 |
// Shift the tested bit over the sign bit. |
--- |
26721 |
// Shift the tested bit over the sign bit. |
--- |
| 26722 |
const APInt &AndMask = ConstAndRHS->getAPIntValue(); |
0 |
26722 |
const APInt &AndMask = ConstAndRHS->getAPIntValue(); |
0 |
| 26723 |
unsigned ShCt = AndMask.getBitWidth() - 1; |
0 |
26723 |
unsigned ShCt = AndMask.getBitWidth() - 1; |
0 |
| 26724 |
if (!TLI.shouldAvoidTransformToShift(VT, ShCt)) { |
0 |
26724 |
if (!TLI.shouldAvoidTransformToShift(VT, ShCt)) { |
0 |
| 26725 |
SDValue ShlAmt = |
--- |
26725 |
SDValue ShlAmt = |
--- |
| 26726 |
DAG.getConstant(AndMask.countl_zero(), SDLoc(AndLHS), |
0 |
26726 |
DAG.getConstant(AndMask.countl_zero(), SDLoc(AndLHS), |
0 |
| 26727 |
getShiftAmountTy(AndLHS.getValueType())); |
--- |
26727 |
getShiftAmountTy(AndLHS.getValueType())); |
--- |
| 26728 |
SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt); |
0 |
26728 |
SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt); |
0 |
| 26729 |
|
--- |
26729 |
|
--- |
| 26730 |
// Now arithmetic right shift it all the way over, so the result is |
--- |
26730 |
// Now arithmetic right shift it all the way over, so the result is |
--- |
| 26731 |
// either all-ones, or zero. |
--- |
26731 |
// either all-ones, or zero. |
--- |
| 26732 |
SDValue ShrAmt = |
--- |
26732 |
SDValue ShrAmt = |
--- |
| 26733 |
DAG.getConstant(ShCt, SDLoc(Shl), |
0 |
26733 |
DAG.getConstant(ShCt, SDLoc(Shl), |
0 |
| 26734 |
getShiftAmountTy(Shl.getValueType())); |
--- |
26734 |
getShiftAmountTy(Shl.getValueType())); |
--- |
| 26735 |
SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt); |
0 |
26735 |
SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt); |
0 |
| 26736 |
|
--- |
26736 |
|
--- |
| 26737 |
return DAG.getNode(ISD::AND, DL, VT, Shr, N3); |
0 |
26737 |
return DAG.getNode(ISD::AND, DL, VT, Shr, N3); |
0 |
| 26738 |
} |
--- |
26738 |
} |
--- |
| 26739 |
} |
--- |
26739 |
} |
--- |
| 26740 |
} |
--- |
26740 |
} |
--- |
| 26741 |
|
--- |
26741 |
|
--- |
| 26742 |
// fold select C, 16, 0 -> shl C, 4 |
--- |
26742 |
// fold select C, 16, 0 -> shl C, 4 |
--- |
| 26743 |
bool Fold = N2C && isNullConstant(N3) && N2C->getAPIntValue().isPowerOf2(); |
0 |
26743 |
bool Fold = N2C && isNullConstant(N3) && N2C->getAPIntValue().isPowerOf2(); |
0 |
| 26744 |
bool Swap = N3C && isNullConstant(N2) && N3C->getAPIntValue().isPowerOf2(); |
0 |
26744 |
bool Swap = N3C && isNullConstant(N2) && N3C->getAPIntValue().isPowerOf2(); |
0 |
| 26745 |
|
--- |
26745 |
|
--- |
| 26746 |
if ((Fold || Swap) && |
0 |
26746 |
if ((Fold || Swap) && |
0 |
| 26747 |
TLI.getBooleanContents(CmpOpVT) == |
0 |
26747 |
TLI.getBooleanContents(CmpOpVT) == |
0 |
| 26748 |
TargetLowering::ZeroOrOneBooleanContent && |
0 |
26748 |
TargetLowering::ZeroOrOneBooleanContent && |
0 |
| 26749 |
(!LegalOperations || TLI.isOperationLegal(ISD::SETCC, CmpOpVT))) { |
0 |
26749 |
(!LegalOperations || TLI.isOperationLegal(ISD::SETCC, CmpOpVT))) { |
0 |
| 26750 |
|
--- |
26750 |
|
--- |
| 26751 |
if (Swap) { |
0 |
26751 |
if (Swap) { |
0 |
| 26752 |
CC = ISD::getSetCCInverse(CC, CmpOpVT); |
0 |
26752 |
CC = ISD::getSetCCInverse(CC, CmpOpVT); |
0 |
| 26753 |
std::swap(N2C, N3C); |
0 |
26753 |
std::swap(N2C, N3C); |
0 |
| 26754 |
} |
--- |
26754 |
} |
--- |
| 26755 |
|
--- |
26755 |
|
--- |
| 26756 |
// If the caller doesn't want us to simplify this into a zext of a compare, |
--- |
26756 |
// If the caller doesn't want us to simplify this into a zext of a compare, |
--- |
| 26757 |
// don't do it. |
--- |
26757 |
// don't do it. |
--- |
| 26758 |
if (NotExtCompare && N2C->isOne()) |
0 |
26758 |
if (NotExtCompare && N2C->isOne()) |
0 |
| 26759 |
return SDValue(); |
0 |
26759 |
return SDValue(); |
0 |
| 26760 |
|
--- |
26760 |
|
--- |
| 26761 |
SDValue Temp, SCC; |
0 |
26761 |
SDValue Temp, SCC; |
0 |
| 26762 |
// zext (setcc n0, n1) |
--- |
26762 |
// zext (setcc n0, n1) |
--- |
| 26763 |
if (LegalTypes) { |
0 |
26763 |
if (LegalTypes) { |
0 |
| 26764 |
SCC = DAG.getSetCC(DL, CmpResVT, N0, N1, CC); |
0 |
26764 |
SCC = DAG.getSetCC(DL, CmpResVT, N0, N1, CC); |
0 |
| 26765 |
if (VT.bitsLT(SCC.getValueType())) |
0 |
26765 |
if (VT.bitsLT(SCC.getValueType())) |
0 |
| 26766 |
Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2), VT); |
0 |
26766 |
Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2), VT); |
0 |
| 26767 |
else |
--- |
26767 |
else |
--- |
| 26768 |
Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC); |
0 |
26768 |
Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC); |
0 |
| 26769 |
} else { |
--- |
26769 |
} else { |
--- |
| 26770 |
SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC); |
0 |
26770 |
SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC); |
0 |
| 26771 |
Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC); |
0 |
26771 |
Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC); |
0 |
| 26772 |
} |
--- |
26772 |
} |
--- |
| 26773 |
|
--- |
26773 |
|
--- |
| 26774 |
AddToWorklist(SCC.getNode()); |
0 |
26774 |
AddToWorklist(SCC.getNode()); |
0 |
| 26775 |
AddToWorklist(Temp.getNode()); |
0 |
26775 |
AddToWorklist(Temp.getNode()); |
0 |
| 26776 |
|
--- |
26776 |
|
--- |
| 26777 |
if (N2C->isOne()) |
0 |
26777 |
if (N2C->isOne()) |
0 |
| 26778 |
return Temp; |
0 |
26778 |
return Temp; |
0 |
| 26779 |
|
--- |
26779 |
|
--- |
| 26780 |
unsigned ShCt = N2C->getAPIntValue().logBase2(); |
0 |
26780 |
unsigned ShCt = N2C->getAPIntValue().logBase2(); |
0 |
| 26781 |
if (TLI.shouldAvoidTransformToShift(VT, ShCt)) |
0 |
26781 |
if (TLI.shouldAvoidTransformToShift(VT, ShCt)) |
0 |
| 26782 |
return SDValue(); |
0 |
26782 |
return SDValue(); |
0 |
| 26783 |
|
--- |
26783 |
|
--- |
| 26784 |
// shl setcc result by log2 n2c |
--- |
26784 |
// shl setcc result by log2 n2c |
--- |
| 26785 |
return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, |
0 |
26785 |
return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, |
0 |
| 26786 |
DAG.getConstant(ShCt, SDLoc(Temp), |
0 |
26786 |
DAG.getConstant(ShCt, SDLoc(Temp), |
0 |
| 26787 |
getShiftAmountTy(Temp.getValueType()))); |
0 |
26787 |
getShiftAmountTy(Temp.getValueType()))); |
0 |
| 26788 |
} |
--- |
26788 |
} |
--- |
| 26789 |
|
--- |
26789 |
|
--- |
| 26790 |
// select_cc seteq X, 0, sizeof(X), ctlz(X) -> ctlz(X) |
--- |
26790 |
// select_cc seteq X, 0, sizeof(X), ctlz(X) -> ctlz(X) |
--- |
| 26791 |
// select_cc seteq X, 0, sizeof(X), ctlz_zero_undef(X) -> ctlz(X) |
--- |
26791 |
// select_cc seteq X, 0, sizeof(X), ctlz_zero_undef(X) -> ctlz(X) |
--- |
| 26792 |
// select_cc seteq X, 0, sizeof(X), cttz(X) -> cttz(X) |
--- |
26792 |
// select_cc seteq X, 0, sizeof(X), cttz(X) -> cttz(X) |
--- |
| 26793 |
// select_cc seteq X, 0, sizeof(X), cttz_zero_undef(X) -> cttz(X) |
--- |
26793 |
// select_cc seteq X, 0, sizeof(X), cttz_zero_undef(X) -> cttz(X) |
--- |
| 26794 |
// select_cc setne X, 0, ctlz(X), sizeof(X) -> ctlz(X) |
--- |
26794 |
// select_cc setne X, 0, ctlz(X), sizeof(X) -> ctlz(X) |
--- |
| 26795 |
// select_cc setne X, 0, ctlz_zero_undef(X), sizeof(X) -> ctlz(X) |
--- |
26795 |
// select_cc setne X, 0, ctlz_zero_undef(X), sizeof(X) -> ctlz(X) |
--- |
| 26796 |
// select_cc setne X, 0, cttz(X), sizeof(X) -> cttz(X) |
--- |
26796 |
// select_cc setne X, 0, cttz(X), sizeof(X) -> cttz(X) |
--- |
| 26797 |
// select_cc setne X, 0, cttz_zero_undef(X), sizeof(X) -> cttz(X) |
--- |
26797 |
// select_cc setne X, 0, cttz_zero_undef(X), sizeof(X) -> cttz(X) |
--- |
| 26798 |
if (N1C && N1C->isZero() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { |
0 |
26798 |
if (N1C && N1C->isZero() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { |
0 |
| 26799 |
SDValue ValueOnZero = N2; |
0 |
26799 |
SDValue ValueOnZero = N2; |
0 |
| 26800 |
SDValue Count = N3; |
0 |
26800 |
SDValue Count = N3; |
0 |
| 26801 |
// If the condition is NE instead of E, swap the operands. |
--- |
26801 |
// If the condition is NE instead of E, swap the operands. |
--- |
| 26802 |
if (CC == ISD::SETNE) |
0 |
26802 |
if (CC == ISD::SETNE) |
0 |
| 26803 |
std::swap(ValueOnZero, Count); |
0 |
26803 |
std::swap(ValueOnZero, Count); |
0 |
| 26804 |
// Check if the value on zero is a constant equal to the bits in the type. |
--- |
26804 |
// Check if the value on zero is a constant equal to the bits in the type. |
--- |
| 26805 |
if (auto *ValueOnZeroC = dyn_cast(ValueOnZero)) { |
0 |
26805 |
if (auto *ValueOnZeroC = dyn_cast(ValueOnZero)) { |
0 |
| 26806 |
if (ValueOnZeroC->getAPIntValue() == VT.getSizeInBits()) { |
0 |
26806 |
if (ValueOnZeroC->getAPIntValue() == VT.getSizeInBits()) { |
0 |
| 26807 |
// If the other operand is cttz/cttz_zero_undef of N0, and cttz is |
--- |
26807 |
// If the other operand is cttz/cttz_zero_undef of N0, and cttz is |
--- |
| 26808 |
// legal, combine to just cttz. |
--- |
26808 |
// legal, combine to just cttz. |
--- |
| 26809 |
if ((Count.getOpcode() == ISD::CTTZ || |
0 |
26809 |
if ((Count.getOpcode() == ISD::CTTZ || |
0 |
| 26810 |
Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) && |
0 |
26810 |
Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) && |
0 |
| 26811 |
N0 == Count.getOperand(0) && |
0 |
26811 |
N0 == Count.getOperand(0) && |
0 |
| 26812 |
(!LegalOperations || TLI.isOperationLegal(ISD::CTTZ, VT))) |
0 |
26812 |
(!LegalOperations || TLI.isOperationLegal(ISD::CTTZ, VT))) |
0 |
| 26813 |
return DAG.getNode(ISD::CTTZ, DL, VT, N0); |
0 |
26813 |
return DAG.getNode(ISD::CTTZ, DL, VT, N0); |
0 |
| 26814 |
// If the other operand is ctlz/ctlz_zero_undef of N0, and ctlz is |
--- |
26814 |
// If the other operand is ctlz/ctlz_zero_undef of N0, and ctlz is |
--- |
| 26815 |
// legal, combine to just ctlz. |
--- |
26815 |
// legal, combine to just ctlz. |
--- |
| 26816 |
if ((Count.getOpcode() == ISD::CTLZ || |
0 |
26816 |
if ((Count.getOpcode() == ISD::CTLZ || |
0 |
| 26817 |
Count.getOpcode() == ISD::CTLZ_ZERO_UNDEF) && |
0 |
26817 |
Count.getOpcode() == ISD::CTLZ_ZERO_UNDEF) && |
0 |
| 26818 |
N0 == Count.getOperand(0) && |
0 |
26818 |
N0 == Count.getOperand(0) && |
0 |
| 26819 |
(!LegalOperations || TLI.isOperationLegal(ISD::CTLZ, VT))) |
0 |
26819 |
(!LegalOperations || TLI.isOperationLegal(ISD::CTLZ, VT))) |
0 |
| 26820 |
return DAG.getNode(ISD::CTLZ, DL, VT, N0); |
0 |
26820 |
return DAG.getNode(ISD::CTLZ, DL, VT, N0); |
0 |
| 26821 |
} |
--- |
26821 |
} |
--- |
| 26822 |
} |
--- |
26822 |
} |
--- |
| 26823 |
} |
--- |
26823 |
} |
--- |
| 26824 |
|
--- |
26824 |
|
--- |
| 26825 |
// Fold select_cc setgt X, -1, C, ~C -> xor (ashr X, BW-1), C |
--- |
26825 |
// Fold select_cc setgt X, -1, C, ~C -> xor (ashr X, BW-1), C |
--- |
| 26826 |
// Fold select_cc setlt X, 0, C, ~C -> xor (ashr X, BW-1), ~C |
--- |
26826 |
// Fold select_cc setlt X, 0, C, ~C -> xor (ashr X, BW-1), ~C |
--- |
| 26827 |
if (!NotExtCompare && N1C && N2C && N3C && |
0 |
26827 |
if (!NotExtCompare && N1C && N2C && N3C && |
0 |
| 26828 |
N2C->getAPIntValue() == ~N3C->getAPIntValue() && |
0 |
26828 |
N2C->getAPIntValue() == ~N3C->getAPIntValue() && |
0 |
| 26829 |
((N1C->isAllOnes() && CC == ISD::SETGT) || |
0 |
26829 |
((N1C->isAllOnes() && CC == ISD::SETGT) || |
0 |
| 26830 |
(N1C->isZero() && CC == ISD::SETLT)) && |
0 |
26830 |
(N1C->isZero() && CC == ISD::SETLT)) && |
0 |
| 26831 |
!TLI.shouldAvoidTransformToShift(VT, CmpOpVT.getScalarSizeInBits() - 1)) { |
0 |
26831 |
!TLI.shouldAvoidTransformToShift(VT, CmpOpVT.getScalarSizeInBits() - 1)) { |
0 |
| 26832 |
SDValue ASR = DAG.getNode( |
0 |
26832 |
SDValue ASR = DAG.getNode( |
0 |
| 26833 |
ISD::SRA, DL, CmpOpVT, N0, |
--- |
26833 |
ISD::SRA, DL, CmpOpVT, N0, |
--- |
| 26834 |
DAG.getConstant(CmpOpVT.getScalarSizeInBits() - 1, DL, CmpOpVT)); |
0 |
26834 |
DAG.getConstant(CmpOpVT.getScalarSizeInBits() - 1, DL, CmpOpVT)); |
0 |
| 26835 |
return DAG.getNode(ISD::XOR, DL, VT, DAG.getSExtOrTrunc(ASR, DL, VT), |
0 |
26835 |
return DAG.getNode(ISD::XOR, DL, VT, DAG.getSExtOrTrunc(ASR, DL, VT), |
0 |
| 26836 |
DAG.getSExtOrTrunc(CC == ISD::SETLT ? N3 : N2, DL, VT)); |
0 |
26836 |
DAG.getSExtOrTrunc(CC == ISD::SETLT ? N3 : N2, DL, VT)); |
0 |
| 26837 |
} |
--- |
26837 |
} |
--- |
| 26838 |
|
--- |
26838 |
|
--- |
| 26839 |
if (SDValue S = PerformMinMaxFpToSatCombine(N0, N1, N2, N3, CC, DAG)) |
0 |
26839 |
if (SDValue S = PerformMinMaxFpToSatCombine(N0, N1, N2, N3, CC, DAG)) |
0 |
| 26840 |
return S; |
0 |
26840 |
return S; |
0 |
| 26841 |
if (SDValue S = PerformUMinFpToSatCombine(N0, N1, N2, N3, CC, DAG)) |
0 |
26841 |
if (SDValue S = PerformUMinFpToSatCombine(N0, N1, N2, N3, CC, DAG)) |
0 |
| 26842 |
return S; |
0 |
26842 |
return S; |
0 |
| 26843 |
|
--- |
26843 |
|
--- |
| 26844 |
return SDValue(); |
0 |
26844 |
return SDValue(); |
0 |
| 26845 |
} |
--- |
26845 |
} |
--- |
| 26846 |
|
--- |
26846 |
|
--- |
| 26847 |
/// This is a stub for TargetLowering::SimplifySetCC. |
--- |
26847 |
/// This is a stub for TargetLowering::SimplifySetCC. |
--- |
| 26848 |
SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, |
3 |
26848 |
SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, |
3 |
| 26849 |
ISD::CondCode Cond, const SDLoc &DL, |
--- |
26849 |
ISD::CondCode Cond, const SDLoc &DL, |
--- |
| 26850 |
bool foldBooleans) { |
--- |
26850 |
bool foldBooleans) { |
--- |
| 26851 |
TargetLowering::DAGCombinerInfo |
--- |
26851 |
TargetLowering::DAGCombinerInfo |
--- |
| 26852 |
DagCombineInfo(DAG, Level, false, this); |
3 |
26852 |
DagCombineInfo(DAG, Level, false, this); |
3 |
| 26853 |
return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); |
3 |
26853 |
return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); |
3 |
| 26854 |
} |
--- |
26854 |
} |
--- |
| 26855 |
|
--- |
26855 |
|
--- |
| 26856 |
/// Given an ISD::SDIV node expressing a divide by constant, return |
--- |
26856 |
/// Given an ISD::SDIV node expressing a divide by constant, return |
--- |
| 26857 |
/// a DAG expression to select that will generate the same value by multiplying |
--- |
26857 |
/// a DAG expression to select that will generate the same value by multiplying |
--- |
| 26858 |
/// by a magic number. |
--- |
26858 |
/// by a magic number. |
--- |
| 26859 |
/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide". |
--- |
26859 |
/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide". |
--- |
| 26860 |
SDValue DAGCombiner::BuildSDIV(SDNode *N) { |
0 |
26860 |
SDValue DAGCombiner::BuildSDIV(SDNode *N) { |
0 |
| 26861 |
// when optimising for minimum size, we don't want to expand a div to a mul |
--- |
26861 |
// when optimising for minimum size, we don't want to expand a div to a mul |
--- |
| 26862 |
// and a shift. |
--- |
26862 |
// and a shift. |
--- |
| 26863 |
if (DAG.getMachineFunction().getFunction().hasMinSize()) |
0 |
26863 |
if (DAG.getMachineFunction().getFunction().hasMinSize()) |
0 |
| 26864 |
return SDValue(); |
0 |
26864 |
return SDValue(); |
0 |
| 26865 |
|
--- |
26865 |
|
--- |
| 26866 |
SmallVector Built; |
0 |
26866 |
SmallVector Built; |
0 |
| 26867 |
if (SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, Built)) { |
0 |
26867 |
if (SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, Built)) { |
0 |
| 26868 |
for (SDNode *N : Built) |
0 |
26868 |
for (SDNode *N : Built) |
0 |
| 26869 |
AddToWorklist(N); |
0 |
26869 |
AddToWorklist(N); |
0 |
| 26870 |
return S; |
0 |
26870 |
return S; |
0 |
| 26871 |
} |
--- |
26871 |
} |
--- |
| 26872 |
|
--- |
26872 |
|
--- |
| 26873 |
return SDValue(); |
0 |
26873 |
return SDValue(); |
0 |
| 26874 |
} |
0 |
26874 |
} |
0 |
| 26875 |
|
--- |
26875 |
|
--- |
| 26876 |
/// Given an ISD::SDIV node expressing a divide by constant power of 2, return a |
--- |
26876 |
/// Given an ISD::SDIV node expressing a divide by constant power of 2, return a |
--- |
| 26877 |
/// DAG expression that will generate the same value by right shifting. |
--- |
26877 |
/// DAG expression that will generate the same value by right shifting. |
--- |
| 26878 |
SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) { |
0 |
26878 |
SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) { |
0 |
| 26879 |
ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1)); |
0 |
26879 |
ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1)); |
0 |
| 26880 |
if (!C) |
0 |
26880 |
if (!C) |
0 |
| 26881 |
return SDValue(); |
0 |
26881 |
return SDValue(); |
0 |
| 26882 |
|
--- |
26882 |
|
--- |
| 26883 |
// Avoid division by zero. |
--- |
26883 |
// Avoid division by zero. |
--- |
| 26884 |
if (C->isZero()) |
0 |
26884 |
if (C->isZero()) |
0 |
| 26885 |
return SDValue(); |
0 |
26885 |
return SDValue(); |
0 |
| 26886 |
|
--- |
26886 |
|
--- |
| 26887 |
SmallVector Built; |
0 |
26887 |
SmallVector Built; |
0 |
| 26888 |
if (SDValue S = TLI.BuildSDIVPow2(N, C->getAPIntValue(), DAG, Built)) { |
0 |
26888 |
if (SDValue S = TLI.BuildSDIVPow2(N, C->getAPIntValue(), DAG, Built)) { |
0 |
| 26889 |
for (SDNode *N : Built) |
0 |
26889 |
for (SDNode *N : Built) |
0 |
| 26890 |
AddToWorklist(N); |
0 |
26890 |
AddToWorklist(N); |
0 |
| 26891 |
return S; |
0 |
26891 |
return S; |
0 |
| 26892 |
} |
--- |
26892 |
} |
--- |
| 26893 |
|
--- |
26893 |
|
--- |
| 26894 |
return SDValue(); |
0 |
26894 |
return SDValue(); |
0 |
| 26895 |
} |
0 |
26895 |
} |
0 |
| 26896 |
|
--- |
26896 |
|
--- |
| 26897 |
/// Given an ISD::UDIV node expressing a divide by constant, return a DAG |
--- |
26897 |
/// Given an ISD::UDIV node expressing a divide by constant, return a DAG |
--- |
| 26898 |
/// expression that will generate the same value by multiplying by a magic |
--- |
26898 |
/// expression that will generate the same value by multiplying by a magic |
--- |
| 26899 |
/// number. |
--- |
26899 |
/// number. |
--- |
| 26900 |
/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide". |
--- |
26900 |
/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide". |
--- |
| 26901 |
SDValue DAGCombiner::BuildUDIV(SDNode *N) { |
0 |
26901 |
SDValue DAGCombiner::BuildUDIV(SDNode *N) { |
0 |
| 26902 |
// when optimising for minimum size, we don't want to expand a div to a mul |
--- |
26902 |
// when optimising for minimum size, we don't want to expand a div to a mul |
--- |
| 26903 |
// and a shift. |
--- |
26903 |
// and a shift. |
--- |
| 26904 |
if (DAG.getMachineFunction().getFunction().hasMinSize()) |
0 |
26904 |
if (DAG.getMachineFunction().getFunction().hasMinSize()) |
0 |
| 26905 |
return SDValue(); |
0 |
26905 |
return SDValue(); |
0 |
| 26906 |
|
--- |
26906 |
|
--- |
| 26907 |
SmallVector Built; |
0 |
26907 |
SmallVector Built; |
0 |
| 26908 |
if (SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, Built)) { |
0 |
26908 |
if (SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, Built)) { |
0 |
| 26909 |
for (SDNode *N : Built) |
0 |
26909 |
for (SDNode *N : Built) |
0 |
| 26910 |
AddToWorklist(N); |
0 |
26910 |
AddToWorklist(N); |
0 |
| 26911 |
return S; |
0 |
26911 |
return S; |
0 |
| 26912 |
} |
--- |
26912 |
} |
--- |
| 26913 |
|
--- |
26913 |
|
--- |
| 26914 |
return SDValue(); |
0 |
26914 |
return SDValue(); |
0 |
| 26915 |
} |
0 |
26915 |
} |
0 |
| 26916 |
|
--- |
26916 |
|
--- |
| 26917 |
/// Given an ISD::SREM node expressing a remainder by constant power of 2, |
--- |
26917 |
/// Given an ISD::SREM node expressing a remainder by constant power of 2, |
--- |
| 26918 |
/// return a DAG expression that will generate the same value. |
--- |
26918 |
/// return a DAG expression that will generate the same value. |
--- |
| 26919 |
SDValue DAGCombiner::BuildSREMPow2(SDNode *N) { |
0 |
26919 |
SDValue DAGCombiner::BuildSREMPow2(SDNode *N) { |
0 |
| 26920 |
ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1)); |
0 |
26920 |
ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1)); |
0 |
| 26921 |
if (!C) |
0 |
26921 |
if (!C) |
0 |
| 26922 |
return SDValue(); |
0 |
26922 |
return SDValue(); |
0 |
| 26923 |
|
--- |
26923 |
|
--- |
| 26924 |
// Avoid division by zero. |
--- |
26924 |
// Avoid division by zero. |
--- |
| 26925 |
if (C->isZero()) |
0 |
26925 |
if (C->isZero()) |
0 |
| 26926 |
return SDValue(); |
0 |
26926 |
return SDValue(); |
0 |
| 26927 |
|
--- |
26927 |
|
--- |
| 26928 |
SmallVector Built; |
0 |
26928 |
SmallVector Built; |
0 |
| 26929 |
if (SDValue S = TLI.BuildSREMPow2(N, C->getAPIntValue(), DAG, Built)) { |
0 |
26929 |
if (SDValue S = TLI.BuildSREMPow2(N, C->getAPIntValue(), DAG, Built)) { |
0 |
| 26930 |
for (SDNode *N : Built) |
0 |
26930 |
for (SDNode *N : Built) |
0 |
| 26931 |
AddToWorklist(N); |
0 |
26931 |
AddToWorklist(N); |
0 |
| 26932 |
return S; |
0 |
26932 |
return S; |
0 |
| 26933 |
} |
--- |
26933 |
} |
--- |
| 26934 |
|
--- |
26934 |
|
--- |
| 26935 |
return SDValue(); |
0 |
26935 |
return SDValue(); |
0 |
| 26936 |
} |
0 |
26936 |
} |
0 |
| 26937 |
|
--- |
26937 |
|
--- |
| 26938 |
/// Determines the LogBase2 value for a non-null input value using the |
--- |
26938 |
/// Determines the LogBase2 value for a non-null input value using the |
--- |
| 26939 |
/// transform: LogBase2(V) = (EltBits - 1) - ctlz(V). |
--- |
26939 |
/// transform: LogBase2(V) = (EltBits - 1) - ctlz(V). |
--- |
| 26940 |
SDValue DAGCombiner::BuildLogBase2(SDValue V, const SDLoc &DL) { |
0 |
26940 |
SDValue DAGCombiner::BuildLogBase2(SDValue V, const SDLoc &DL) { |
0 |
| 26941 |
EVT VT = V.getValueType(); |
0 |
26941 |
EVT VT = V.getValueType(); |
0 |
| 26942 |
SDValue Ctlz = DAG.getNode(ISD::CTLZ, DL, VT, V); |
0 |
26942 |
SDValue Ctlz = DAG.getNode(ISD::CTLZ, DL, VT, V); |
0 |
| 26943 |
SDValue Base = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); |
0 |
26943 |
SDValue Base = DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT); |
0 |
| 26944 |
SDValue LogBase2 = DAG.getNode(ISD::SUB, DL, VT, Base, Ctlz); |
0 |
26944 |
SDValue LogBase2 = DAG.getNode(ISD::SUB, DL, VT, Base, Ctlz); |
0 |
| 26945 |
return LogBase2; |
0 |
26945 |
return LogBase2; |
0 |
| 26946 |
} |
--- |
26946 |
} |
--- |
| 26947 |
|
--- |
26947 |
|
--- |
| 26948 |
/// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i) |
--- |
26948 |
/// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i) |
--- |
| 26949 |
/// For the reciprocal, we need to find the zero of the function: |
--- |
26949 |
/// For the reciprocal, we need to find the zero of the function: |
--- |
| 26950 |
/// F(X) = 1/X - A [which has a zero at X = 1/A] |
--- |
26950 |
/// F(X) = 1/X - A [which has a zero at X = 1/A] |
--- |
| 26951 |
/// => |
--- |
26951 |
/// => |
--- |
| 26952 |
/// X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form |
--- |
26952 |
/// X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form |
--- |
| 26953 |
/// does not require additional intermediate precision] |
--- |
26953 |
/// does not require additional intermediate precision] |
--- |
| 26954 |
/// For the last iteration, put numerator N into it to gain more precision: |
--- |
26954 |
/// For the last iteration, put numerator N into it to gain more precision: |
--- |
| 26955 |
/// Result = N X_i + X_i (N - N A X_i) |
--- |
26955 |
/// Result = N X_i + X_i (N - N A X_i) |
--- |
| 26956 |
SDValue DAGCombiner::BuildDivEstimate(SDValue N, SDValue Op, |
0 |
26956 |
SDValue DAGCombiner::BuildDivEstimate(SDValue N, SDValue Op, |
0 |
| 26957 |
SDNodeFlags Flags) { |
--- |
26957 |
SDNodeFlags Flags) { |
--- |
| 26958 |
if (LegalDAG) |
0 |
26958 |
if (LegalDAG) |
0 |
| 26959 |
return SDValue(); |
0 |
26959 |
return SDValue(); |
0 |
| 26960 |
|
--- |
26960 |
|
--- |
| 26961 |
// TODO: Handle extended types? |
--- |
26961 |
// TODO: Handle extended types? |
--- |
| 26962 |
EVT VT = Op.getValueType(); |
0 |
26962 |
EVT VT = Op.getValueType(); |
0 |
| 26963 |
if (VT.getScalarType() != MVT::f16 && VT.getScalarType() != MVT::f32 && |
0 |
26963 |
if (VT.getScalarType() != MVT::f16 && VT.getScalarType() != MVT::f32 && |
0 |
| 26964 |
VT.getScalarType() != MVT::f64) |
0 |
26964 |
VT.getScalarType() != MVT::f64) |
0 |
| 26965 |
return SDValue(); |
0 |
26965 |
return SDValue(); |
0 |
| 26966 |
|
--- |
26966 |
|
--- |
| 26967 |
// If estimates are explicitly disabled for this function, we're done. |
--- |
26967 |
// If estimates are explicitly disabled for this function, we're done. |
--- |
| 26968 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
26968 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 26969 |
int Enabled = TLI.getRecipEstimateDivEnabled(VT, MF); |
0 |
26969 |
int Enabled = TLI.getRecipEstimateDivEnabled(VT, MF); |
0 |
| 26970 |
if (Enabled == TLI.ReciprocalEstimate::Disabled) |
0 |
26970 |
if (Enabled == TLI.ReciprocalEstimate::Disabled) |
0 |
| 26971 |
return SDValue(); |
0 |
26971 |
return SDValue(); |
0 |
| 26972 |
|
--- |
26972 |
|
--- |
| 26973 |
// Estimates may be explicitly enabled for this type with a custom number of |
--- |
26973 |
// Estimates may be explicitly enabled for this type with a custom number of |
--- |
| 26974 |
// refinement steps. |
--- |
26974 |
// refinement steps. |
--- |
| 26975 |
int Iterations = TLI.getDivRefinementSteps(VT, MF); |
0 |
26975 |
int Iterations = TLI.getDivRefinementSteps(VT, MF); |
0 |
| 26976 |
if (SDValue Est = TLI.getRecipEstimate(Op, DAG, Enabled, Iterations)) { |
0 |
26976 |
if (SDValue Est = TLI.getRecipEstimate(Op, DAG, Enabled, Iterations)) { |
0 |
| 26977 |
AddToWorklist(Est.getNode()); |
0 |
26977 |
AddToWorklist(Est.getNode()); |
0 |
| 26978 |
|
--- |
26978 |
|
--- |
| 26979 |
SDLoc DL(Op); |
0 |
26979 |
SDLoc DL(Op); |
0 |
| 26980 |
if (Iterations) { |
0 |
26980 |
if (Iterations) { |
0 |
| 26981 |
SDValue FPOne = DAG.getConstantFP(1.0, DL, VT); |
0 |
26981 |
SDValue FPOne = DAG.getConstantFP(1.0, DL, VT); |
0 |
| 26982 |
|
--- |
26982 |
|
--- |
| 26983 |
// Newton iterations: Est = Est + Est (N - Arg * Est) |
--- |
26983 |
// Newton iterations: Est = Est + Est (N - Arg * Est) |
--- |
| 26984 |
// If this is the last iteration, also multiply by the numerator. |
--- |
26984 |
// If this is the last iteration, also multiply by the numerator. |
--- |
| 26985 |
for (int i = 0; i < Iterations; ++i) { |
0 |
26985 |
for (int i = 0; i < Iterations; ++i) { |
0 |
| 26986 |
SDValue MulEst = Est; |
0 |
26986 |
SDValue MulEst = Est; |
0 |
| 26987 |
|
--- |
26987 |
|
--- |
| 26988 |
if (i == Iterations - 1) { |
0 |
26988 |
if (i == Iterations - 1) { |
0 |
| 26989 |
MulEst = DAG.getNode(ISD::FMUL, DL, VT, N, Est, Flags); |
0 |
26989 |
MulEst = DAG.getNode(ISD::FMUL, DL, VT, N, Est, Flags); |
0 |
| 26990 |
AddToWorklist(MulEst.getNode()); |
0 |
26990 |
AddToWorklist(MulEst.getNode()); |
0 |
| 26991 |
} |
--- |
26991 |
} |
--- |
| 26992 |
|
--- |
26992 |
|
--- |
| 26993 |
SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Op, MulEst, Flags); |
0 |
26993 |
SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Op, MulEst, Flags); |
0 |
| 26994 |
AddToWorklist(NewEst.getNode()); |
0 |
26994 |
AddToWorklist(NewEst.getNode()); |
0 |
| 26995 |
|
--- |
26995 |
|
--- |
| 26996 |
NewEst = DAG.getNode(ISD::FSUB, DL, VT, |
0 |
26996 |
NewEst = DAG.getNode(ISD::FSUB, DL, VT, |
0 |
| 26997 |
(i == Iterations - 1 ? N : FPOne), NewEst, Flags); |
0 |
26997 |
(i == Iterations - 1 ? N : FPOne), NewEst, Flags); |
0 |
| 26998 |
AddToWorklist(NewEst.getNode()); |
0 |
26998 |
AddToWorklist(NewEst.getNode()); |
0 |
| 26999 |
|
--- |
26999 |
|
--- |
| 27000 |
NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst, Flags); |
0 |
27000 |
NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst, Flags); |
0 |
| 27001 |
AddToWorklist(NewEst.getNode()); |
0 |
27001 |
AddToWorklist(NewEst.getNode()); |
0 |
| 27002 |
|
--- |
27002 |
|
--- |
| 27003 |
Est = DAG.getNode(ISD::FADD, DL, VT, MulEst, NewEst, Flags); |
0 |
27003 |
Est = DAG.getNode(ISD::FADD, DL, VT, MulEst, NewEst, Flags); |
0 |
| 27004 |
AddToWorklist(Est.getNode()); |
0 |
27004 |
AddToWorklist(Est.getNode()); |
0 |
| 27005 |
} |
--- |
27005 |
} |
--- |
| 27006 |
} else { |
--- |
27006 |
} else { |
--- |
| 27007 |
// If no iterations are available, multiply with N. |
--- |
27007 |
// If no iterations are available, multiply with N. |
--- |
| 27008 |
Est = DAG.getNode(ISD::FMUL, DL, VT, Est, N, Flags); |
0 |
27008 |
Est = DAG.getNode(ISD::FMUL, DL, VT, Est, N, Flags); |
0 |
| 27009 |
AddToWorklist(Est.getNode()); |
0 |
27009 |
AddToWorklist(Est.getNode()); |
0 |
| 27010 |
} |
--- |
27010 |
} |
--- |
| 27011 |
|
--- |
27011 |
|
--- |
| 27012 |
return Est; |
0 |
27012 |
return Est; |
0 |
| 27013 |
} |
0 |
27013 |
} |
0 |
| 27014 |
|
--- |
27014 |
|
--- |
| 27015 |
return SDValue(); |
0 |
27015 |
return SDValue(); |
0 |
| 27016 |
} |
--- |
27016 |
} |
--- |
| 27017 |
|
--- |
27017 |
|
--- |
| 27018 |
/// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i) |
--- |
27018 |
/// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i) |
--- |
| 27019 |
/// For the reciprocal sqrt, we need to find the zero of the function: |
--- |
27019 |
/// For the reciprocal sqrt, we need to find the zero of the function: |
--- |
| 27020 |
/// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)] |
--- |
27020 |
/// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)] |
--- |
| 27021 |
/// => |
--- |
27021 |
/// => |
--- |
| 27022 |
/// X_{i+1} = X_i (1.5 - A X_i^2 / 2) |
--- |
27022 |
/// X_{i+1} = X_i (1.5 - A X_i^2 / 2) |
--- |
| 27023 |
/// As a result, we precompute A/2 prior to the iteration loop. |
--- |
27023 |
/// As a result, we precompute A/2 prior to the iteration loop. |
--- |
| 27024 |
SDValue DAGCombiner::buildSqrtNROneConst(SDValue Arg, SDValue Est, |
0 |
27024 |
SDValue DAGCombiner::buildSqrtNROneConst(SDValue Arg, SDValue Est, |
0 |
| 27025 |
unsigned Iterations, |
--- |
27025 |
unsigned Iterations, |
--- |
| 27026 |
SDNodeFlags Flags, bool Reciprocal) { |
--- |
27026 |
SDNodeFlags Flags, bool Reciprocal) { |
--- |
| 27027 |
EVT VT = Arg.getValueType(); |
0 |
27027 |
EVT VT = Arg.getValueType(); |
0 |
| 27028 |
SDLoc DL(Arg); |
0 |
27028 |
SDLoc DL(Arg); |
0 |
| 27029 |
SDValue ThreeHalves = DAG.getConstantFP(1.5, DL, VT); |
0 |
27029 |
SDValue ThreeHalves = DAG.getConstantFP(1.5, DL, VT); |
0 |
| 27030 |
|
--- |
27030 |
|
--- |
| 27031 |
// We now need 0.5 * Arg which we can write as (1.5 * Arg - Arg) so that |
--- |
27031 |
// We now need 0.5 * Arg which we can write as (1.5 * Arg - Arg) so that |
--- |
| 27032 |
// this entire sequence requires only one FP constant. |
--- |
27032 |
// this entire sequence requires only one FP constant. |
--- |
| 27033 |
SDValue HalfArg = DAG.getNode(ISD::FMUL, DL, VT, ThreeHalves, Arg, Flags); |
0 |
27033 |
SDValue HalfArg = DAG.getNode(ISD::FMUL, DL, VT, ThreeHalves, Arg, Flags); |
0 |
| 27034 |
HalfArg = DAG.getNode(ISD::FSUB, DL, VT, HalfArg, Arg, Flags); |
0 |
27034 |
HalfArg = DAG.getNode(ISD::FSUB, DL, VT, HalfArg, Arg, Flags); |
0 |
| 27035 |
|
--- |
27035 |
|
--- |
| 27036 |
// Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est) |
--- |
27036 |
// Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est) |
--- |
| 27037 |
for (unsigned i = 0; i < Iterations; ++i) { |
0 |
27037 |
for (unsigned i = 0; i < Iterations; ++i) { |
0 |
| 27038 |
SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, Est, Flags); |
0 |
27038 |
SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, Est, Flags); |
0 |
| 27039 |
NewEst = DAG.getNode(ISD::FMUL, DL, VT, HalfArg, NewEst, Flags); |
0 |
27039 |
NewEst = DAG.getNode(ISD::FMUL, DL, VT, HalfArg, NewEst, Flags); |
0 |
| 27040 |
NewEst = DAG.getNode(ISD::FSUB, DL, VT, ThreeHalves, NewEst, Flags); |
0 |
27040 |
NewEst = DAG.getNode(ISD::FSUB, DL, VT, ThreeHalves, NewEst, Flags); |
0 |
| 27041 |
Est = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst, Flags); |
0 |
27041 |
Est = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst, Flags); |
0 |
| 27042 |
} |
--- |
27042 |
} |
--- |
| 27043 |
|
--- |
27043 |
|
--- |
| 27044 |
// If non-reciprocal square root is requested, multiply the result by Arg. |
--- |
27044 |
// If non-reciprocal square root is requested, multiply the result by Arg. |
--- |
| 27045 |
if (!Reciprocal) |
0 |
27045 |
if (!Reciprocal) |
0 |
| 27046 |
Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Arg, Flags); |
0 |
27046 |
Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Arg, Flags); |
0 |
| 27047 |
|
--- |
27047 |
|
--- |
| 27048 |
return Est; |
0 |
27048 |
return Est; |
0 |
| 27049 |
} |
0 |
27049 |
} |
0 |
| 27050 |
|
--- |
27050 |
|
--- |
| 27051 |
/// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i) |
--- |
27051 |
/// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i) |
--- |
| 27052 |
/// For the reciprocal sqrt, we need to find the zero of the function: |
--- |
27052 |
/// For the reciprocal sqrt, we need to find the zero of the function: |
--- |
| 27053 |
/// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)] |
--- |
27053 |
/// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)] |
--- |
| 27054 |
/// => |
--- |
27054 |
/// => |
--- |
| 27055 |
/// X_{i+1} = (-0.5 * X_i) * (A * X_i * X_i + (-3.0)) |
--- |
27055 |
/// X_{i+1} = (-0.5 * X_i) * (A * X_i * X_i + (-3.0)) |
--- |
| 27056 |
SDValue DAGCombiner::buildSqrtNRTwoConst(SDValue Arg, SDValue Est, |
0 |
27056 |
SDValue DAGCombiner::buildSqrtNRTwoConst(SDValue Arg, SDValue Est, |
0 |
| 27057 |
unsigned Iterations, |
--- |
27057 |
unsigned Iterations, |
--- |
| 27058 |
SDNodeFlags Flags, bool Reciprocal) { |
--- |
27058 |
SDNodeFlags Flags, bool Reciprocal) { |
--- |
| 27059 |
EVT VT = Arg.getValueType(); |
0 |
27059 |
EVT VT = Arg.getValueType(); |
0 |
| 27060 |
SDLoc DL(Arg); |
0 |
27060 |
SDLoc DL(Arg); |
0 |
| 27061 |
SDValue MinusThree = DAG.getConstantFP(-3.0, DL, VT); |
0 |
27061 |
SDValue MinusThree = DAG.getConstantFP(-3.0, DL, VT); |
0 |
| 27062 |
SDValue MinusHalf = DAG.getConstantFP(-0.5, DL, VT); |
0 |
27062 |
SDValue MinusHalf = DAG.getConstantFP(-0.5, DL, VT); |
0 |
| 27063 |
|
--- |
27063 |
|
--- |
| 27064 |
// This routine must enter the loop below to work correctly |
--- |
27064 |
// This routine must enter the loop below to work correctly |
--- |
| 27065 |
// when (Reciprocal == false). |
--- |
27065 |
// when (Reciprocal == false). |
--- |
| 27066 |
assert(Iterations > 0); |
0 |
27066 |
assert(Iterations > 0); |
0 |
| 27067 |
|
--- |
27067 |
|
--- |
| 27068 |
// Newton iterations for reciprocal square root: |
--- |
27068 |
// Newton iterations for reciprocal square root: |
--- |
| 27069 |
// E = (E * -0.5) * ((A * E) * E + -3.0) |
--- |
27069 |
// E = (E * -0.5) * ((A * E) * E + -3.0) |
--- |
| 27070 |
for (unsigned i = 0; i < Iterations; ++i) { |
0 |
27070 |
for (unsigned i = 0; i < Iterations; ++i) { |
0 |
| 27071 |
SDValue AE = DAG.getNode(ISD::FMUL, DL, VT, Arg, Est, Flags); |
0 |
27071 |
SDValue AE = DAG.getNode(ISD::FMUL, DL, VT, Arg, Est, Flags); |
0 |
| 27072 |
SDValue AEE = DAG.getNode(ISD::FMUL, DL, VT, AE, Est, Flags); |
0 |
27072 |
SDValue AEE = DAG.getNode(ISD::FMUL, DL, VT, AE, Est, Flags); |
0 |
| 27073 |
SDValue RHS = DAG.getNode(ISD::FADD, DL, VT, AEE, MinusThree, Flags); |
0 |
27073 |
SDValue RHS = DAG.getNode(ISD::FADD, DL, VT, AEE, MinusThree, Flags); |
0 |
| 27074 |
|
--- |
27074 |
|
--- |
| 27075 |
// When calculating a square root at the last iteration build: |
--- |
27075 |
// When calculating a square root at the last iteration build: |
--- |
| 27076 |
// S = ((A * E) * -0.5) * ((A * E) * E + -3.0) |
--- |
27076 |
// S = ((A * E) * -0.5) * ((A * E) * E + -3.0) |
--- |
| 27077 |
// (notice a common subexpression) |
--- |
27077 |
// (notice a common subexpression) |
--- |
| 27078 |
SDValue LHS; |
0 |
27078 |
SDValue LHS; |
0 |
| 27079 |
if (Reciprocal || (i + 1) < Iterations) { |
0 |
27079 |
if (Reciprocal || (i + 1) < Iterations) { |
0 |
| 27080 |
// RSQRT: LHS = (E * -0.5) |
--- |
27080 |
// RSQRT: LHS = (E * -0.5) |
--- |
| 27081 |
LHS = DAG.getNode(ISD::FMUL, DL, VT, Est, MinusHalf, Flags); |
0 |
27081 |
LHS = DAG.getNode(ISD::FMUL, DL, VT, Est, MinusHalf, Flags); |
0 |
| 27082 |
} else { |
--- |
27082 |
} else { |
--- |
| 27083 |
// SQRT: LHS = (A * E) * -0.5 |
--- |
27083 |
// SQRT: LHS = (A * E) * -0.5 |
--- |
| 27084 |
LHS = DAG.getNode(ISD::FMUL, DL, VT, AE, MinusHalf, Flags); |
0 |
27084 |
LHS = DAG.getNode(ISD::FMUL, DL, VT, AE, MinusHalf, Flags); |
0 |
| 27085 |
} |
--- |
27085 |
} |
--- |
| 27086 |
|
--- |
27086 |
|
--- |
| 27087 |
Est = DAG.getNode(ISD::FMUL, DL, VT, LHS, RHS, Flags); |
0 |
27087 |
Est = DAG.getNode(ISD::FMUL, DL, VT, LHS, RHS, Flags); |
0 |
| 27088 |
} |
--- |
27088 |
} |
--- |
| 27089 |
|
--- |
27089 |
|
--- |
| 27090 |
return Est; |
0 |
27090 |
return Est; |
0 |
| 27091 |
} |
0 |
27091 |
} |
0 |
| 27092 |
|
--- |
27092 |
|
--- |
| 27093 |
/// Build code to calculate either rsqrt(Op) or sqrt(Op). In the latter case |
--- |
27093 |
/// Build code to calculate either rsqrt(Op) or sqrt(Op). In the latter case |
--- |
| 27094 |
/// Op*rsqrt(Op) is actually computed, so additional postprocessing is needed if |
--- |
27094 |
/// Op*rsqrt(Op) is actually computed, so additional postprocessing is needed if |
--- |
| 27095 |
/// Op can be zero. |
--- |
27095 |
/// Op can be zero. |
--- |
| 27096 |
SDValue DAGCombiner::buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, |
0 |
27096 |
SDValue DAGCombiner::buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, |
0 |
| 27097 |
bool Reciprocal) { |
--- |
27097 |
bool Reciprocal) { |
--- |
| 27098 |
if (LegalDAG) |
0 |
27098 |
if (LegalDAG) |
0 |
| 27099 |
return SDValue(); |
0 |
27099 |
return SDValue(); |
0 |
| 27100 |
|
--- |
27100 |
|
--- |
| 27101 |
// TODO: Handle extended types? |
--- |
27101 |
// TODO: Handle extended types? |
--- |
| 27102 |
EVT VT = Op.getValueType(); |
0 |
27102 |
EVT VT = Op.getValueType(); |
0 |
| 27103 |
if (VT.getScalarType() != MVT::f16 && VT.getScalarType() != MVT::f32 && |
0 |
27103 |
if (VT.getScalarType() != MVT::f16 && VT.getScalarType() != MVT::f32 && |
0 |
| 27104 |
VT.getScalarType() != MVT::f64) |
0 |
27104 |
VT.getScalarType() != MVT::f64) |
0 |
| 27105 |
return SDValue(); |
0 |
27105 |
return SDValue(); |
0 |
| 27106 |
|
--- |
27106 |
|
--- |
| 27107 |
// If estimates are explicitly disabled for this function, we're done. |
--- |
27107 |
// If estimates are explicitly disabled for this function, we're done. |
--- |
| 27108 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
27108 |
MachineFunction &MF = DAG.getMachineFunction(); |
0 |
| 27109 |
int Enabled = TLI.getRecipEstimateSqrtEnabled(VT, MF); |
0 |
27109 |
int Enabled = TLI.getRecipEstimateSqrtEnabled(VT, MF); |
0 |
| 27110 |
if (Enabled == TLI.ReciprocalEstimate::Disabled) |
0 |
27110 |
if (Enabled == TLI.ReciprocalEstimate::Disabled) |
0 |
| 27111 |
return SDValue(); |
0 |
27111 |
return SDValue(); |
0 |
| 27112 |
|
--- |
27112 |
|
--- |
| 27113 |
// Estimates may be explicitly enabled for this type with a custom number of |
--- |
27113 |
// Estimates may be explicitly enabled for this type with a custom number of |
--- |
| 27114 |
// refinement steps. |
--- |
27114 |
// refinement steps. |
--- |
| 27115 |
int Iterations = TLI.getSqrtRefinementSteps(VT, MF); |
0 |
27115 |
int Iterations = TLI.getSqrtRefinementSteps(VT, MF); |
0 |
| 27116 |
|
--- |
27116 |
|
--- |
| 27117 |
bool UseOneConstNR = false; |
0 |
27117 |
bool UseOneConstNR = false; |
0 |
| 27118 |
if (SDValue Est = |
0 |
27118 |
if (SDValue Est = |
0 |
| 27119 |
TLI.getSqrtEstimate(Op, DAG, Enabled, Iterations, UseOneConstNR, |
0 |
27119 |
TLI.getSqrtEstimate(Op, DAG, Enabled, Iterations, UseOneConstNR, |
0 |
| 27120 |
Reciprocal)) { |
0 |
27120 |
Reciprocal)) { |
0 |
| 27121 |
AddToWorklist(Est.getNode()); |
0 |
27121 |
AddToWorklist(Est.getNode()); |
0 |
| 27122 |
|
--- |
27122 |
|
--- |
| 27123 |
if (Iterations > 0) |
0 |
27123 |
if (Iterations > 0) |
0 |
| 27124 |
Est = UseOneConstNR |
0 |
27124 |
Est = UseOneConstNR |
0 |
| 27125 |
? buildSqrtNROneConst(Op, Est, Iterations, Flags, Reciprocal) |
0 |
27125 |
? buildSqrtNROneConst(Op, Est, Iterations, Flags, Reciprocal) |
0 |
| 27126 |
: buildSqrtNRTwoConst(Op, Est, Iterations, Flags, Reciprocal); |
0 |
27126 |
: buildSqrtNRTwoConst(Op, Est, Iterations, Flags, Reciprocal); |
0 |
| 27127 |
if (!Reciprocal) { |
0 |
27127 |
if (!Reciprocal) { |
0 |
| 27128 |
SDLoc DL(Op); |
0 |
27128 |
SDLoc DL(Op); |
0 |
| 27129 |
// Try the target specific test first. |
--- |
27129 |
// Try the target specific test first. |
--- |
| 27130 |
SDValue Test = TLI.getSqrtInputTest(Op, DAG, DAG.getDenormalMode(VT)); |
0 |
27130 |
SDValue Test = TLI.getSqrtInputTest(Op, DAG, DAG.getDenormalMode(VT)); |
0 |
| 27131 |
|
--- |
27131 |
|
--- |
| 27132 |
// The estimate is now completely wrong if the input was exactly 0.0 or |
--- |
27132 |
// The estimate is now completely wrong if the input was exactly 0.0 or |
--- |
| 27133 |
// possibly a denormal. Force the answer to 0.0 or value provided by |
--- |
27133 |
// possibly a denormal. Force the answer to 0.0 or value provided by |
--- |
| 27134 |
// target for those cases. |
--- |
27134 |
// target for those cases. |
--- |
| 27135 |
Est = DAG.getNode( |
0 |
27135 |
Est = DAG.getNode( |
0 |
| 27136 |
Test.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT, |
0 |
27136 |
Test.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT, |
0 |
| 27137 |
Test, TLI.getSqrtResultForDenormInput(Op, DAG), Est); |
0 |
27137 |
Test, TLI.getSqrtResultForDenormInput(Op, DAG), Est); |
0 |
| 27138 |
} |
0 |
27138 |
} |
0 |
| 27139 |
return Est; |
0 |
27139 |
return Est; |
0 |
| 27140 |
} |
--- |
27140 |
} |
--- |
| 27141 |
|
--- |
27141 |
|
--- |
| 27142 |
return SDValue(); |
0 |
27142 |
return SDValue(); |
0 |
| 27143 |
} |
--- |
27143 |
} |
--- |
| 27144 |
|
--- |
27144 |
|
--- |
| 27145 |
SDValue DAGCombiner::buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags) { |
0 |
27145 |
SDValue DAGCombiner::buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags) { |
0 |
| 27146 |
return buildSqrtEstimateImpl(Op, Flags, true); |
0 |
27146 |
return buildSqrtEstimateImpl(Op, Flags, true); |
0 |
| 27147 |
} |
--- |
27147 |
} |
--- |
| 27148 |
|
--- |
27148 |
|
--- |
| 27149 |
SDValue DAGCombiner::buildSqrtEstimate(SDValue Op, SDNodeFlags Flags) { |
0 |
27149 |
SDValue DAGCombiner::buildSqrtEstimate(SDValue Op, SDNodeFlags Flags) { |
0 |
| 27150 |
return buildSqrtEstimateImpl(Op, Flags, false); |
0 |
27150 |
return buildSqrtEstimateImpl(Op, Flags, false); |
0 |
| 27151 |
} |
--- |
27151 |
} |
--- |
| 27152 |
|
--- |
27152 |
|
--- |
| 27153 |
/// Return true if there is any possibility that the two addresses overlap. |
--- |
27153 |
/// Return true if there is any possibility that the two addresses overlap. |
--- |
| 27154 |
bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const { |
0 |
27154 |
bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const { |
0 |
| 27155 |
|
--- |
27155 |
|
--- |
| 27156 |
struct MemUseCharacteristics { |
--- |
27156 |
struct MemUseCharacteristics { |
--- |
| 27157 |
bool IsVolatile; |
--- |
27157 |
bool IsVolatile; |
--- |
| 27158 |
bool IsAtomic; |
--- |
27158 |
bool IsAtomic; |
--- |
| 27159 |
SDValue BasePtr; |
--- |
27159 |
SDValue BasePtr; |
--- |
| 27160 |
int64_t Offset; |
--- |
27160 |
int64_t Offset; |
--- |
| 27161 |
std::optional NumBytes; |
--- |
27161 |
std::optional NumBytes; |
--- |
| 27162 |
MachineMemOperand *MMO; |
--- |
27162 |
MachineMemOperand *MMO; |
--- |
| 27163 |
}; |
--- |
27163 |
}; |
--- |
| 27164 |
|
--- |
27164 |
|
--- |
| 27165 |
auto getCharacteristics = [](SDNode *N) -> MemUseCharacteristics { |
0 |
27165 |
auto getCharacteristics = [](SDNode *N) -> MemUseCharacteristics { |
0 |
| 27166 |
if (const auto *LSN = dyn_cast(N)) { |
0 |
27166 |
if (const auto *LSN = dyn_cast(N)) { |
0 |
| 27167 |
int64_t Offset = 0; |
0 |
27167 |
int64_t Offset = 0; |
0 |
| 27168 |
if (auto *C = dyn_cast(LSN->getOffset())) |
0 |
27168 |
if (auto *C = dyn_cast(LSN->getOffset())) |
0 |
| 27169 |
Offset = (LSN->getAddressingMode() == ISD::PRE_INC) |
0 |
27169 |
Offset = (LSN->getAddressingMode() == ISD::PRE_INC) |
0 |
| 27170 |
? C->getSExtValue() |
0 |
27170 |
? C->getSExtValue() |
0 |
| 27171 |
: (LSN->getAddressingMode() == ISD::PRE_DEC) |
0 |
27171 |
: (LSN->getAddressingMode() == ISD::PRE_DEC) |
0 |
| 27172 |
? -1 * C->getSExtValue() |
0 |
27172 |
? -1 * C->getSExtValue() |
0 |
| 27173 |
: 0; |
--- |
27173 |
: 0; |
--- |
| 27174 |
uint64_t Size = |
--- |
27174 |
uint64_t Size = |
--- |
| 27175 |
MemoryLocation::getSizeOrUnknown(LSN->getMemoryVT().getStoreSize()); |
0 |
27175 |
MemoryLocation::getSizeOrUnknown(LSN->getMemoryVT().getStoreSize()); |
0 |
| 27176 |
return {LSN->isVolatile(), |
0 |
27176 |
return {LSN->isVolatile(), |
0 |
| 27177 |
LSN->isAtomic(), |
0 |
27177 |
LSN->isAtomic(), |
0 |
| 27178 |
LSN->getBasePtr(), |
0 |
27178 |
LSN->getBasePtr(), |
0 |
| 27179 |
Offset /*base offset*/, |
--- |
27179 |
Offset /*base offset*/, |
--- |
| 27180 |
std::optional(Size), |
--- |
27180 |
std::optional(Size), |
--- |
| 27181 |
LSN->getMemOperand()}; |
0 |
27181 |
LSN->getMemOperand()}; |
0 |
| 27182 |
} |
--- |
27182 |
} |
--- |
| 27183 |
if (const auto *LN = cast(N)) |
0 |
27183 |
if (const auto *LN = cast(N)) |
0 |
| 27184 |
return {false /*isVolatile*/, |
--- |
27184 |
return {false /*isVolatile*/, |
--- |
| 27185 |
/*isAtomic*/ false, |
--- |
27185 |
/*isAtomic*/ false, |
--- |
| 27186 |
LN->getOperand(1), |
0 |
27186 |
LN->getOperand(1), |
0 |
| 27187 |
(LN->hasOffset()) ? LN->getOffset() : 0, |
0 |
27187 |
(LN->hasOffset()) ? LN->getOffset() : 0, |
0 |
| 27188 |
(LN->hasOffset()) ? std::optional(LN->getSize()) |
0 |
27188 |
(LN->hasOffset()) ? std::optional(LN->getSize()) |
0 |
| 27189 |
: std::optional(), |
--- |
27189 |
: std::optional(), |
--- |
| 27190 |
(MachineMemOperand *)nullptr}; |
0 |
27190 |
(MachineMemOperand *)nullptr}; |
0 |
| 27191 |
// Default. |
--- |
27191 |
// Default. |
--- |
| 27192 |
return {false /*isvolatile*/, |
--- |
27192 |
return {false /*isvolatile*/, |
--- |
| 27193 |
/*isAtomic*/ false, SDValue(), |
--- |
27193 |
/*isAtomic*/ false, SDValue(), |
--- |
| 27194 |
(int64_t)0 /*offset*/, std::optional() /*size*/, |
--- |
27194 |
(int64_t)0 /*offset*/, std::optional() /*size*/, |
--- |
| 27195 |
(MachineMemOperand *)nullptr}; |
0 |
27195 |
(MachineMemOperand *)nullptr}; |
0 |
| 27196 |
}; |
--- |
27196 |
}; |
--- |
| 27197 |
|
--- |
27197 |
|
--- |
| 27198 |
MemUseCharacteristics MUC0 = getCharacteristics(Op0), |
0 |
27198 |
MemUseCharacteristics MUC0 = getCharacteristics(Op0), |
0 |
| 27199 |
MUC1 = getCharacteristics(Op1); |
0 |
27199 |
MUC1 = getCharacteristics(Op1); |
0 |
| 27200 |
|
--- |
27200 |
|
--- |
| 27201 |
// If they are to the same address, then they must be aliases. |
--- |
27201 |
// If they are to the same address, then they must be aliases. |
--- |
| 27202 |
if (MUC0.BasePtr.getNode() && MUC0.BasePtr == MUC1.BasePtr && |
0 |
27202 |
if (MUC0.BasePtr.getNode() && MUC0.BasePtr == MUC1.BasePtr && |
0 |
| 27203 |
MUC0.Offset == MUC1.Offset) |
0 |
27203 |
MUC0.Offset == MUC1.Offset) |
0 |
| 27204 |
return true; |
0 |
27204 |
return true; |
0 |
| 27205 |
|
--- |
27205 |
|
--- |
| 27206 |
// If they are both volatile then they cannot be reordered. |
--- |
27206 |
// If they are both volatile then they cannot be reordered. |
--- |
| 27207 |
if (MUC0.IsVolatile && MUC1.IsVolatile) |
0 |
27207 |
if (MUC0.IsVolatile && MUC1.IsVolatile) |
0 |
| 27208 |
return true; |
0 |
27208 |
return true; |
0 |
| 27209 |
|
--- |
27209 |
|
--- |
| 27210 |
// Be conservative about atomics for the moment |
--- |
27210 |
// Be conservative about atomics for the moment |
--- |
| 27211 |
// TODO: This is way overconservative for unordered atomics (see D66309) |
--- |
27211 |
// TODO: This is way overconservative for unordered atomics (see D66309) |
--- |
| 27212 |
if (MUC0.IsAtomic && MUC1.IsAtomic) |
0 |
27212 |
if (MUC0.IsAtomic && MUC1.IsAtomic) |
0 |
| 27213 |
return true; |
0 |
27213 |
return true; |
0 |
| 27214 |
|
--- |
27214 |
|
--- |
| 27215 |
if (MUC0.MMO && MUC1.MMO) { |
0 |
27215 |
if (MUC0.MMO && MUC1.MMO) { |
0 |
| 27216 |
if ((MUC0.MMO->isInvariant() && MUC1.MMO->isStore()) || |
0 |
27216 |
if ((MUC0.MMO->isInvariant() && MUC1.MMO->isStore()) || |
0 |
| 27217 |
(MUC1.MMO->isInvariant() && MUC0.MMO->isStore())) |
0 |
27217 |
(MUC1.MMO->isInvariant() && MUC0.MMO->isStore())) |
0 |
| 27218 |
return false; |
0 |
27218 |
return false; |
0 |
| 27219 |
} |
--- |
27219 |
} |
--- |
| 27220 |
|
--- |
27220 |
|
--- |
| 27221 |
// Try to prove that there is aliasing, or that there is no aliasing. Either |
--- |
27221 |
// Try to prove that there is aliasing, or that there is no aliasing. Either |
--- |
| 27222 |
// way, we can return now. If nothing can be proved, proceed with more tests. |
--- |
27222 |
// way, we can return now. If nothing can be proved, proceed with more tests. |
--- |
| 27223 |
bool IsAlias; |
--- |
27223 |
bool IsAlias; |
--- |
| 27224 |
if (BaseIndexOffset::computeAliasing(Op0, MUC0.NumBytes, Op1, MUC1.NumBytes, |
0 |
27224 |
if (BaseIndexOffset::computeAliasing(Op0, MUC0.NumBytes, Op1, MUC1.NumBytes, |
0 |
| 27225 |
DAG, IsAlias)) |
0 |
27225 |
DAG, IsAlias)) |
0 |
| 27226 |
return IsAlias; |
0 |
27226 |
return IsAlias; |
0 |
| 27227 |
|
--- |
27227 |
|
--- |
| 27228 |
// The following all rely on MMO0 and MMO1 being valid. Fail conservatively if |
--- |
27228 |
// The following all rely on MMO0 and MMO1 being valid. Fail conservatively if |
--- |
| 27229 |
// either are not known. |
--- |
27229 |
// either are not known. |
--- |
| 27230 |
if (!MUC0.MMO || !MUC1.MMO) |
0 |
27230 |
if (!MUC0.MMO || !MUC1.MMO) |
0 |
| 27231 |
return true; |
0 |
27231 |
return true; |
0 |
| 27232 |
|
--- |
27232 |
|
--- |
| 27233 |
// If one operation reads from invariant memory, and the other may store, they |
--- |
27233 |
// If one operation reads from invariant memory, and the other may store, they |
--- |
| 27234 |
// cannot alias. These should really be checking the equivalent of mayWrite, |
--- |
27234 |
// cannot alias. These should really be checking the equivalent of mayWrite, |
--- |
| 27235 |
// but it only matters for memory nodes other than load /store. |
--- |
27235 |
// but it only matters for memory nodes other than load /store. |
--- |
| 27236 |
if ((MUC0.MMO->isInvariant() && MUC1.MMO->isStore()) || |
0 |
27236 |
if ((MUC0.MMO->isInvariant() && MUC1.MMO->isStore()) || |
0 |
| 27237 |
(MUC1.MMO->isInvariant() && MUC0.MMO->isStore())) |
0 |
27237 |
(MUC1.MMO->isInvariant() && MUC0.MMO->isStore())) |
0 |
| 27238 |
return false; |
0 |
27238 |
return false; |
0 |
| 27239 |
|
--- |
27239 |
|
--- |
| 27240 |
// If we know required SrcValue1 and SrcValue2 have relatively large |
--- |
27240 |
// If we know required SrcValue1 and SrcValue2 have relatively large |
--- |
| 27241 |
// alignment compared to the size and offset of the access, we may be able |
--- |
27241 |
// alignment compared to the size and offset of the access, we may be able |
--- |
| 27242 |
// to prove they do not alias. This check is conservative for now to catch |
--- |
27242 |
// to prove they do not alias. This check is conservative for now to catch |
--- |
| 27243 |
// cases created by splitting vector types, it only works when the offsets are |
--- |
27243 |
// cases created by splitting vector types, it only works when the offsets are |
--- |
| 27244 |
// multiples of the size of the data. |
--- |
27244 |
// multiples of the size of the data. |
--- |
| 27245 |
int64_t SrcValOffset0 = MUC0.MMO->getOffset(); |
0 |
27245 |
int64_t SrcValOffset0 = MUC0.MMO->getOffset(); |
0 |
| 27246 |
int64_t SrcValOffset1 = MUC1.MMO->getOffset(); |
0 |
27246 |
int64_t SrcValOffset1 = MUC1.MMO->getOffset(); |
0 |
| 27247 |
Align OrigAlignment0 = MUC0.MMO->getBaseAlign(); |
0 |
27247 |
Align OrigAlignment0 = MUC0.MMO->getBaseAlign(); |
0 |
| 27248 |
Align OrigAlignment1 = MUC1.MMO->getBaseAlign(); |
0 |
27248 |
Align OrigAlignment1 = MUC1.MMO->getBaseAlign(); |
0 |
| 27249 |
auto &Size0 = MUC0.NumBytes; |
0 |
27249 |
auto &Size0 = MUC0.NumBytes; |
0 |
| 27250 |
auto &Size1 = MUC1.NumBytes; |
0 |
27250 |
auto &Size1 = MUC1.NumBytes; |
0 |
| 27251 |
if (OrigAlignment0 == OrigAlignment1 && SrcValOffset0 != SrcValOffset1 && |
0 |
27251 |
if (OrigAlignment0 == OrigAlignment1 && SrcValOffset0 != SrcValOffset1 && |
0 |
| 27252 |
Size0.has_value() && Size1.has_value() && *Size0 == *Size1 && |
0 |
27252 |
Size0.has_value() && Size1.has_value() && *Size0 == *Size1 && |
0 |
| 27253 |
OrigAlignment0 > *Size0 && SrcValOffset0 % *Size0 == 0 && |
0 |
27253 |
OrigAlignment0 > *Size0 && SrcValOffset0 % *Size0 == 0 && |
0 |
| 27254 |
SrcValOffset1 % *Size1 == 0) { |
0 |
27254 |
SrcValOffset1 % *Size1 == 0) { |
0 |
| 27255 |
int64_t OffAlign0 = SrcValOffset0 % OrigAlignment0.value(); |
0 |
27255 |
int64_t OffAlign0 = SrcValOffset0 % OrigAlignment0.value(); |
0 |
| 27256 |
int64_t OffAlign1 = SrcValOffset1 % OrigAlignment1.value(); |
0 |
27256 |
int64_t OffAlign1 = SrcValOffset1 % OrigAlignment1.value(); |
0 |
| 27257 |
|
--- |
27257 |
|
--- |
| 27258 |
// There is no overlap between these relatively aligned accesses of |
--- |
27258 |
// There is no overlap between these relatively aligned accesses of |
--- |
| 27259 |
// similar size. Return no alias. |
--- |
27259 |
// similar size. Return no alias. |
--- |
| 27260 |
if ((OffAlign0 + *Size0) <= OffAlign1 || (OffAlign1 + *Size1) <= OffAlign0) |
0 |
27260 |
if ((OffAlign0 + *Size0) <= OffAlign1 || (OffAlign1 + *Size1) <= OffAlign0) |
0 |
| 27261 |
return false; |
0 |
27261 |
return false; |
0 |
| 27262 |
} |
--- |
27262 |
} |
--- |
| 27263 |
|
--- |
27263 |
|
--- |
| 27264 |
bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0 |
0 |
27264 |
bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0 |
0 |
| 27265 |
? CombinerGlobalAA |
0 |
27265 |
? CombinerGlobalAA |
0 |
| 27266 |
: DAG.getSubtarget().useAA(); |
0 |
27266 |
: DAG.getSubtarget().useAA(); |
0 |
| 27267 |
#ifndef NDEBUG |
--- |
27267 |
#ifndef NDEBUG |
--- |
| 27268 |
if (CombinerAAOnlyFunc.getNumOccurrences() && |
0 |
27268 |
if (CombinerAAOnlyFunc.getNumOccurrences() && |
0 |
| 27269 |
CombinerAAOnlyFunc != DAG.getMachineFunction().getName()) |
0 |
27269 |
CombinerAAOnlyFunc != DAG.getMachineFunction().getName()) |
0 |
| 27270 |
UseAA = false; |
0 |
27270 |
UseAA = false; |
0 |
| 27271 |
#endif |
--- |
27271 |
#endif |
--- |
| 27272 |
|
--- |
27272 |
|
--- |
| 27273 |
if (UseAA && AA && MUC0.MMO->getValue() && MUC1.MMO->getValue() && Size0 && |
0 |
27273 |
if (UseAA && AA && MUC0.MMO->getValue() && MUC1.MMO->getValue() && Size0 && |
0 |
| 27274 |
Size1) { |
0 |
27274 |
Size1) { |
0 |
| 27275 |
// Use alias analysis information. |
--- |
27275 |
// Use alias analysis information. |
--- |
| 27276 |
int64_t MinOffset = std::min(SrcValOffset0, SrcValOffset1); |
0 |
27276 |
int64_t MinOffset = std::min(SrcValOffset0, SrcValOffset1); |
0 |
| 27277 |
int64_t Overlap0 = *Size0 + SrcValOffset0 - MinOffset; |
0 |
27277 |
int64_t Overlap0 = *Size0 + SrcValOffset0 - MinOffset; |
0 |
| 27278 |
int64_t Overlap1 = *Size1 + SrcValOffset1 - MinOffset; |
0 |
27278 |
int64_t Overlap1 = *Size1 + SrcValOffset1 - MinOffset; |
0 |
| 27279 |
if (AA->isNoAlias( |
0 |
27279 |
if (AA->isNoAlias( |
0 |
| 27280 |
MemoryLocation(MUC0.MMO->getValue(), Overlap0, |
0 |
27280 |
MemoryLocation(MUC0.MMO->getValue(), Overlap0, |
0 |
| 27281 |
UseTBAA ? MUC0.MMO->getAAInfo() : AAMDNodes()), |
0 |
27281 |
UseTBAA ? MUC0.MMO->getAAInfo() : AAMDNodes()), |
0 |
| 27282 |
MemoryLocation(MUC1.MMO->getValue(), Overlap1, |
0 |
27282 |
MemoryLocation(MUC1.MMO->getValue(), Overlap1, |
0 |
| 27283 |
UseTBAA ? MUC1.MMO->getAAInfo() : AAMDNodes()))) |
0 |
27283 |
UseTBAA ? MUC1.MMO->getAAInfo() : AAMDNodes()))) |
0 |
| 27284 |
return false; |
0 |
27284 |
return false; |
0 |
| 27285 |
} |
--- |
27285 |
} |
--- |
| 27286 |
|
--- |
27286 |
|
--- |
| 27287 |
// Otherwise we have to assume they alias. |
--- |
27287 |
// Otherwise we have to assume they alias. |
--- |
| 27288 |
return true; |
0 |
27288 |
return true; |
0 |
| 27289 |
} |
--- |
27289 |
} |
--- |
| 27290 |
|
--- |
27290 |
|
--- |
| 27291 |
/// Walk up chain skipping non-aliasing memory nodes, |
--- |
27291 |
/// Walk up chain skipping non-aliasing memory nodes, |
--- |
| 27292 |
/// looking for aliasing nodes and adding them to the Aliases vector. |
--- |
27292 |
/// looking for aliasing nodes and adding them to the Aliases vector. |
--- |
| 27293 |
void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, |
0 |
27293 |
void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, |
0 |
| 27294 |
SmallVectorImpl &Aliases) { |
--- |
27294 |
SmallVectorImpl &Aliases) { |
--- |
| 27295 |
SmallVector Chains; // List of chains to visit. |
0 |
27295 |
SmallVector Chains; // List of chains to visit. |
0 |
| 27296 |
SmallPtrSet Visited; // Visited node set. |
0 |
27296 |
SmallPtrSet Visited; // Visited node set. |
0 |
| 27297 |
|
--- |
27297 |
|
--- |
| 27298 |
// Get alias information for node. |
--- |
27298 |
// Get alias information for node. |
--- |
| 27299 |
// TODO: relax aliasing for unordered atomics (see D66309) |
--- |
27299 |
// TODO: relax aliasing for unordered atomics (see D66309) |
--- |
| 27300 |
const bool IsLoad = isa(N) && cast(N)->isSimple(); |
0 |
27300 |
const bool IsLoad = isa(N) && cast(N)->isSimple(); |
0 |
| 27301 |
|
--- |
27301 |
|
--- |
| 27302 |
// Starting off. |
--- |
27302 |
// Starting off. |
--- |
| 27303 |
Chains.push_back(OriginalChain); |
0 |
27303 |
Chains.push_back(OriginalChain); |
0 |
| 27304 |
unsigned Depth = 0; |
0 |
27304 |
unsigned Depth = 0; |
0 |
| 27305 |
|
--- |
27305 |
|
--- |
| 27306 |
// Attempt to improve chain by a single step |
--- |
27306 |
// Attempt to improve chain by a single step |
--- |
| 27307 |
auto ImproveChain = [&](SDValue &C) -> bool { |
0 |
27307 |
auto ImproveChain = [&](SDValue &C) -> bool { |
0 |
| 27308 |
switch (C.getOpcode()) { |
0 |
27308 |
switch (C.getOpcode()) { |
0 |
| 27309 |
case ISD::EntryToken: |
0 |
27309 |
case ISD::EntryToken: |
0 |
| 27310 |
// No need to mark EntryToken. |
--- |
27310 |
// No need to mark EntryToken. |
--- |
| 27311 |
C = SDValue(); |
0 |
27311 |
C = SDValue(); |
0 |
| 27312 |
return true; |
0 |
27312 |
return true; |
0 |
| 27313 |
case ISD::LOAD: |
0 |
27313 |
case ISD::LOAD: |
0 |
| 27314 |
case ISD::STORE: { |
--- |
27314 |
case ISD::STORE: { |
--- |
| 27315 |
// Get alias information for C. |
--- |
27315 |
// Get alias information for C. |
--- |
| 27316 |
// TODO: Relax aliasing for unordered atomics (see D66309) |
--- |
27316 |
// TODO: Relax aliasing for unordered atomics (see D66309) |
--- |
| 27317 |
bool IsOpLoad = isa(C.getNode()) && |
0 |
27317 |
bool IsOpLoad = isa(C.getNode()) && |
0 |
| 27318 |
cast(C.getNode())->isSimple(); |
0 |
27318 |
cast(C.getNode())->isSimple(); |
0 |
| 27319 |
if ((IsLoad && IsOpLoad) || !mayAlias(N, C.getNode())) { |
0 |
27319 |
if ((IsLoad && IsOpLoad) || !mayAlias(N, C.getNode())) { |
0 |
| 27320 |
// Look further up the chain. |
--- |
27320 |
// Look further up the chain. |
--- |
| 27321 |
C = C.getOperand(0); |
0 |
27321 |
C = C.getOperand(0); |
0 |
| 27322 |
return true; |
0 |
27322 |
return true; |
0 |
| 27323 |
} |
--- |
27323 |
} |
--- |
| 27324 |
// Alias, so stop here. |
--- |
27324 |
// Alias, so stop here. |
--- |
| 27325 |
return false; |
0 |
27325 |
return false; |
0 |
| 27326 |
} |
--- |
27326 |
} |
--- |
| 27327 |
|
--- |
27327 |
|
--- |
| 27328 |
case ISD::CopyFromReg: |
0 |
27328 |
case ISD::CopyFromReg: |
0 |
| 27329 |
// Always forward past past CopyFromReg. |
--- |
27329 |
// Always forward past past CopyFromReg. |
--- |
| 27330 |
C = C.getOperand(0); |
0 |
27330 |
C = C.getOperand(0); |
0 |
| 27331 |
return true; |
0 |
27331 |
return true; |
0 |
| 27332 |
|
--- |
27332 |
|
--- |
| 27333 |
case ISD::LIFETIME_START: |
0 |
27333 |
case ISD::LIFETIME_START: |
0 |
| 27334 |
case ISD::LIFETIME_END: { |
--- |
27334 |
case ISD::LIFETIME_END: { |
--- |
| 27335 |
// We can forward past any lifetime start/end that can be proven not to |
--- |
27335 |
// We can forward past any lifetime start/end that can be proven not to |
--- |
| 27336 |
// alias the memory access. |
--- |
27336 |
// alias the memory access. |
--- |
| 27337 |
if (!mayAlias(N, C.getNode())) { |
0 |
27337 |
if (!mayAlias(N, C.getNode())) { |
0 |
| 27338 |
// Look further up the chain. |
--- |
27338 |
// Look further up the chain. |
--- |
| 27339 |
C = C.getOperand(0); |
0 |
27339 |
C = C.getOperand(0); |
0 |
| 27340 |
return true; |
0 |
27340 |
return true; |
0 |
| 27341 |
} |
--- |
27341 |
} |
--- |
| 27342 |
return false; |
0 |
27342 |
return false; |
0 |
| 27343 |
} |
--- |
27343 |
} |
--- |
| 27344 |
default: |
0 |
27344 |
default: |
0 |
| 27345 |
return false; |
0 |
27345 |
return false; |
0 |
| 27346 |
} |
--- |
27346 |
} |
--- |
| 27347 |
}; |
0 |
27347 |
}; |
0 |
| 27348 |
|
--- |
27348 |
|
--- |
| 27349 |
// Look at each chain and determine if it is an alias. If so, add it to the |
--- |
27349 |
// Look at each chain and determine if it is an alias. If so, add it to the |
--- |
| 27350 |
// aliases list. If not, then continue up the chain looking for the next |
--- |
27350 |
// aliases list. If not, then continue up the chain looking for the next |
--- |
| 27351 |
// candidate. |
--- |
27351 |
// candidate. |
--- |
| 27352 |
while (!Chains.empty()) { |
0 |
27352 |
while (!Chains.empty()) { |
0 |
| 27353 |
SDValue Chain = Chains.pop_back_val(); |
0 |
27353 |
SDValue Chain = Chains.pop_back_val(); |
0 |
| 27354 |
|
--- |
27354 |
|
--- |
| 27355 |
// Don't bother if we've seen Chain before. |
--- |
27355 |
// Don't bother if we've seen Chain before. |
--- |
| 27356 |
if (!Visited.insert(Chain.getNode()).second) |
0 |
27356 |
if (!Visited.insert(Chain.getNode()).second) |
0 |
| 27357 |
continue; |
0 |
27357 |
continue; |
0 |
| 27358 |
|
--- |
27358 |
|
--- |
| 27359 |
// For TokenFactor nodes, look at each operand and only continue up the |
--- |
27359 |
// For TokenFactor nodes, look at each operand and only continue up the |
--- |
| 27360 |
// chain until we reach the depth limit. |
--- |
27360 |
// chain until we reach the depth limit. |
--- |
| 27361 |
// |
--- |
27361 |
// |
--- |
| 27362 |
// FIXME: The depth check could be made to return the last non-aliasing |
--- |
27362 |
// FIXME: The depth check could be made to return the last non-aliasing |
--- |
| 27363 |
// chain we found before we hit a tokenfactor rather than the original |
--- |
27363 |
// chain we found before we hit a tokenfactor rather than the original |
--- |
| 27364 |
// chain. |
--- |
27364 |
// chain. |
--- |
| 27365 |
if (Depth > TLI.getGatherAllAliasesMaxDepth()) { |
0 |
27365 |
if (Depth > TLI.getGatherAllAliasesMaxDepth()) { |
0 |
| 27366 |
Aliases.clear(); |
0 |
27366 |
Aliases.clear(); |
0 |
| 27367 |
Aliases.push_back(OriginalChain); |
0 |
27367 |
Aliases.push_back(OriginalChain); |
0 |
| 27368 |
return; |
0 |
27368 |
return; |
0 |
| 27369 |
} |
--- |
27369 |
} |
--- |
| 27370 |
|
--- |
27370 |
|
--- |
| 27371 |
if (Chain.getOpcode() == ISD::TokenFactor) { |
0 |
27371 |
if (Chain.getOpcode() == ISD::TokenFactor) { |
0 |
| 27372 |
// We have to check each of the operands of the token factor for "small" |
--- |
27372 |
// We have to check each of the operands of the token factor for "small" |
--- |
| 27373 |
// token factors, so we queue them up. Adding the operands to the queue |
--- |
27373 |
// token factors, so we queue them up. Adding the operands to the queue |
--- |
| 27374 |
// (stack) in reverse order maintains the original order and increases the |
--- |
27374 |
// (stack) in reverse order maintains the original order and increases the |
--- |
| 27375 |
// likelihood that getNode will find a matching token factor (CSE.) |
--- |
27375 |
// likelihood that getNode will find a matching token factor (CSE.) |
--- |
| 27376 |
if (Chain.getNumOperands() > 16) { |
0 |
27376 |
if (Chain.getNumOperands() > 16) { |
0 |
| 27377 |
Aliases.push_back(Chain); |
0 |
27377 |
Aliases.push_back(Chain); |
0 |
| 27378 |
continue; |
0 |
27378 |
continue; |
0 |
| 27379 |
} |
--- |
27379 |
} |
--- |
| 27380 |
for (unsigned n = Chain.getNumOperands(); n;) |
0 |
27380 |
for (unsigned n = Chain.getNumOperands(); n;) |
0 |
| 27381 |
Chains.push_back(Chain.getOperand(--n)); |
0 |
27381 |
Chains.push_back(Chain.getOperand(--n)); |
0 |
| 27382 |
++Depth; |
0 |
27382 |
++Depth; |
0 |
| 27383 |
continue; |
0 |
27383 |
continue; |
0 |
| 27384 |
} |
0 |
27384 |
} |
0 |
| 27385 |
// Everything else |
--- |
27385 |
// Everything else |
--- |
| 27386 |
if (ImproveChain(Chain)) { |
0 |
27386 |
if (ImproveChain(Chain)) { |
0 |
| 27387 |
// Updated Chain Found, Consider new chain if one exists. |
--- |
27387 |
// Updated Chain Found, Consider new chain if one exists. |
--- |
| 27388 |
if (Chain.getNode()) |
0 |
27388 |
if (Chain.getNode()) |
0 |
| 27389 |
Chains.push_back(Chain); |
0 |
27389 |
Chains.push_back(Chain); |
0 |
| 27390 |
++Depth; |
0 |
27390 |
++Depth; |
0 |
| 27391 |
continue; |
0 |
27391 |
continue; |
0 |
| 27392 |
} |
--- |
27392 |
} |
--- |
| 27393 |
// No Improved Chain Possible, treat as Alias. |
--- |
27393 |
// No Improved Chain Possible, treat as Alias. |
--- |
| 27394 |
Aliases.push_back(Chain); |
0 |
27394 |
Aliases.push_back(Chain); |
0 |
| 27395 |
} |
--- |
27395 |
} |
--- |
| 27396 |
} |
0 |
27396 |
} |
0 |
| 27397 |
|
--- |
27397 |
|
--- |
| 27398 |
/// Walk up chain skipping non-aliasing memory nodes, looking for a better chain |
--- |
27398 |
/// Walk up chain skipping non-aliasing memory nodes, looking for a better chain |
--- |
| 27399 |
/// (aliasing node.) |
--- |
27399 |
/// (aliasing node.) |
--- |
| 27400 |
SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { |
12 |
27400 |
SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { |
12 |
| 27401 |
if (OptLevel == CodeGenOpt::None) |
12 |
27401 |
if (OptLevel == CodeGenOpt::None) |
12 |
| 27402 |
return OldChain; |
12 |
27402 |
return OldChain; |
12 |
| 27403 |
|
--- |
27403 |
|
--- |
| 27404 |
// Ops for replacing token factor. |
--- |
27404 |
// Ops for replacing token factor. |
--- |
| 27405 |
SmallVector Aliases; |
0 |
27405 |
SmallVector Aliases; |
0 |
| 27406 |
|
--- |
27406 |
|
--- |
| 27407 |
// Accumulate all the aliases to this node. |
--- |
27407 |
// Accumulate all the aliases to this node. |
--- |
| 27408 |
GatherAllAliases(N, OldChain, Aliases); |
0 |
27408 |
GatherAllAliases(N, OldChain, Aliases); |
0 |
| 27409 |
|
--- |
27409 |
|
--- |
| 27410 |
// If no operands then chain to entry token. |
--- |
27410 |
// If no operands then chain to entry token. |
--- |
| 27411 |
if (Aliases.size() == 0) |
0 |
27411 |
if (Aliases.size() == 0) |
0 |
| 27412 |
return DAG.getEntryNode(); |
0 |
27412 |
return DAG.getEntryNode(); |
0 |
| 27413 |
|
--- |
27413 |
|
--- |
| 27414 |
// If a single operand then chain to it. We don't need to revisit it. |
--- |
27414 |
// If a single operand then chain to it. We don't need to revisit it. |
--- |
| 27415 |
if (Aliases.size() == 1) |
0 |
27415 |
if (Aliases.size() == 1) |
0 |
| 27416 |
return Aliases[0]; |
0 |
27416 |
return Aliases[0]; |
0 |
| 27417 |
|
--- |
27417 |
|
--- |
| 27418 |
// Construct a custom tailored token factor. |
--- |
27418 |
// Construct a custom tailored token factor. |
--- |
| 27419 |
return DAG.getTokenFactor(SDLoc(N), Aliases); |
0 |
27419 |
return DAG.getTokenFactor(SDLoc(N), Aliases); |
0 |
| 27420 |
} |
0 |
27420 |
} |
0 |
| 27421 |
|
--- |
27421 |
|
--- |
| 27422 |
// This function tries to collect a bunch of potentially interesting |
--- |
27422 |
// This function tries to collect a bunch of potentially interesting |
--- |
| 27423 |
// nodes to improve the chains of, all at once. This might seem |
--- |
27423 |
// nodes to improve the chains of, all at once. This might seem |
--- |
| 27424 |
// redundant, as this function gets called when visiting every store |
--- |
27424 |
// redundant, as this function gets called when visiting every store |
--- |
| 27425 |
// node, so why not let the work be done on each store as it's visited? |
--- |
27425 |
// node, so why not let the work be done on each store as it's visited? |
--- |
| 27426 |
// |
--- |
27426 |
// |
--- |
| 27427 |
// I believe this is mainly important because mergeConsecutiveStores |
--- |
27427 |
// I believe this is mainly important because mergeConsecutiveStores |
--- |
| 27428 |
// is unable to deal with merging stores of different sizes, so unless |
--- |
27428 |
// is unable to deal with merging stores of different sizes, so unless |
--- |
| 27429 |
// we improve the chains of all the potential candidates up-front |
--- |
27429 |
// we improve the chains of all the potential candidates up-front |
--- |
| 27430 |
// before running mergeConsecutiveStores, it might only see some of |
--- |
27430 |
// before running mergeConsecutiveStores, it might only see some of |
--- |
| 27431 |
// the nodes that will eventually be candidates, and then not be able |
--- |
27431 |
// the nodes that will eventually be candidates, and then not be able |
--- |
| 27432 |
// to go from a partially-merged state to the desired final |
--- |
27432 |
// to go from a partially-merged state to the desired final |
--- |
| 27433 |
// fully-merged state. |
--- |
27433 |
// fully-merged state. |
--- |
| 27434 |
|
--- |
27434 |
|
--- |
| 27435 |
bool DAGCombiner::parallelizeChainedStores(StoreSDNode *St) { |
0 |
27435 |
bool DAGCombiner::parallelizeChainedStores(StoreSDNode *St) { |
0 |
| 27436 |
SmallVector ChainedStores; |
0 |
27436 |
SmallVector ChainedStores; |
0 |
| 27437 |
StoreSDNode *STChain = St; |
0 |
27437 |
StoreSDNode *STChain = St; |
0 |
| 27438 |
// Intervals records which offsets from BaseIndex have been covered. In |
--- |
27438 |
// Intervals records which offsets from BaseIndex have been covered. In |
--- |
| 27439 |
// the common case, every store writes to the immediately previous address |
--- |
27439 |
// the common case, every store writes to the immediately previous address |
--- |
| 27440 |
// space and thus merged with the previous interval at insertion time. |
--- |
27440 |
// space and thus merged with the previous interval at insertion time. |
--- |
| 27441 |
|
--- |
27441 |
|
--- |
| 27442 |
using IMap = llvm::IntervalMap
| --- |
27442 |
using IMap = llvm::IntervalMap
| --- |
| |
| 27443 |
IntervalMapHalfOpenInfo>; |
--- |
27443 |
IntervalMapHalfOpenInfo>; |
--- |
| 27444 |
IMap::Allocator A; |
0 |
27444 |
IMap::Allocator A; |
0 |
| 27445 |
IMap Intervals(A); |
0 |
27445 |
IMap Intervals(A); |
0 |
| 27446 |
|
--- |
27446 |
|
--- |
| 27447 |
// This holds the base pointer, index, and the offset in bytes from the base |
--- |
27447 |
// This holds the base pointer, index, and the offset in bytes from the base |
--- |
| 27448 |
// pointer. |
--- |
27448 |
// pointer. |
--- |
| 27449 |
const BaseIndexOffset BasePtr = BaseIndexOffset::match(St, DAG); |
0 |
27449 |
const BaseIndexOffset BasePtr = BaseIndexOffset::match(St, DAG); |
0 |
| 27450 |
|
--- |
27450 |
|
--- |
| 27451 |
// We must have a base and an offset. |
--- |
27451 |
// We must have a base and an offset. |
--- |
| 27452 |
if (!BasePtr.getBase().getNode()) |
0 |
27452 |
if (!BasePtr.getBase().getNode()) |
0 |
| 27453 |
return false; |
0 |
27453 |
return false; |
0 |
| 27454 |
|
--- |
27454 |
|
--- |
| 27455 |
// Do not handle stores to undef base pointers. |
--- |
27455 |
// Do not handle stores to undef base pointers. |
--- |
| 27456 |
if (BasePtr.getBase().isUndef()) |
0 |
27456 |
if (BasePtr.getBase().isUndef()) |
0 |
| 27457 |
return false; |
0 |
27457 |
return false; |
0 |
| 27458 |
|
--- |
27458 |
|
--- |
| 27459 |
// Do not handle stores to opaque types |
--- |
27459 |
// Do not handle stores to opaque types |
--- |
| 27460 |
if (St->getMemoryVT().isZeroSized()) |
0 |
27460 |
if (St->getMemoryVT().isZeroSized()) |
0 |
| 27461 |
return false; |
0 |
27461 |
return false; |
0 |
| 27462 |
|
--- |
27462 |
|
--- |
| 27463 |
// BaseIndexOffset assumes that offsets are fixed-size, which |
--- |
27463 |
// BaseIndexOffset assumes that offsets are fixed-size, which |
--- |
| 27464 |
// is not valid for scalable vectors where the offsets are |
--- |
27464 |
// is not valid for scalable vectors where the offsets are |
--- |
| 27465 |
// scaled by `vscale`, so bail out early. |
--- |
27465 |
// scaled by `vscale`, so bail out early. |
--- |
| 27466 |
if (St->getMemoryVT().isScalableVT()) |
0 |
27466 |
if (St->getMemoryVT().isScalableVT()) |
0 |
| 27467 |
return false; |
0 |
27467 |
return false; |
0 |
| 27468 |
|
--- |
27468 |
|
--- |
| 27469 |
// Add ST's interval. |
--- |
27469 |
// Add ST's interval. |
--- |
| 27470 |
Intervals.insert(0, (St->getMemoryVT().getSizeInBits() + 7) / 8, |
0 |
27470 |
Intervals.insert(0, (St->getMemoryVT().getSizeInBits() + 7) / 8, |
0 |
| 27471 |
std::monostate{}); |
--- |
27471 |
std::monostate{}); |
--- |
| 27472 |
|
--- |
27472 |
|
--- |
| 27473 |
while (StoreSDNode *Chain = dyn_cast(STChain->getChain())) { |
0 |
27473 |
while (StoreSDNode *Chain = dyn_cast(STChain->getChain())) { |
0 |
| 27474 |
if (Chain->getMemoryVT().isScalableVector()) |
0 |
27474 |
if (Chain->getMemoryVT().isScalableVector()) |
0 |
| 27475 |
return false; |
0 |
27475 |
return false; |
0 |
| 27476 |
|
--- |
27476 |
|
--- |
| 27477 |
// If the chain has more than one use, then we can't reorder the mem ops. |
--- |
27477 |
// If the chain has more than one use, then we can't reorder the mem ops. |
--- |
| 27478 |
if (!SDValue(Chain, 0)->hasOneUse()) |
0 |
27478 |
if (!SDValue(Chain, 0)->hasOneUse()) |
0 |
| 27479 |
break; |
0 |
27479 |
break; |
0 |
| 27480 |
// TODO: Relax for unordered atomics (see D66309) |
--- |
27480 |
// TODO: Relax for unordered atomics (see D66309) |
--- |
| 27481 |
if (!Chain->isSimple() || Chain->isIndexed()) |
0 |
27481 |
if (!Chain->isSimple() || Chain->isIndexed()) |
0 |
| 27482 |
break; |
0 |
27482 |
break; |
0 |
| 27483 |
|
--- |
27483 |
|
--- |
| 27484 |
// Find the base pointer and offset for this memory node. |
--- |
27484 |
// Find the base pointer and offset for this memory node. |
--- |
| 27485 |
const BaseIndexOffset Ptr = BaseIndexOffset::match(Chain, DAG); |
0 |
27485 |
const BaseIndexOffset Ptr = BaseIndexOffset::match(Chain, DAG); |
0 |
| 27486 |
// Check that the base pointer is the same as the original one. |
--- |
27486 |
// Check that the base pointer is the same as the original one. |
--- |
| 27487 |
int64_t Offset; |
--- |
27487 |
int64_t Offset; |
--- |
| 27488 |
if (!BasePtr.equalBaseIndex(Ptr, DAG, Offset)) |
0 |
27488 |
if (!BasePtr.equalBaseIndex(Ptr, DAG, Offset)) |
0 |
| 27489 |
break; |
0 |
27489 |
break; |
0 |
| 27490 |
int64_t Length = (Chain->getMemoryVT().getSizeInBits() + 7) / 8; |
0 |
27490 |
int64_t Length = (Chain->getMemoryVT().getSizeInBits() + 7) / 8; |
0 |
| 27491 |
// Make sure we don't overlap with other intervals by checking the ones to |
--- |
27491 |
// Make sure we don't overlap with other intervals by checking the ones to |
--- |
| 27492 |
// the left or right before inserting. |
--- |
27492 |
// the left or right before inserting. |
--- |
| 27493 |
auto I = Intervals.find(Offset); |
0 |
27493 |
auto I = Intervals.find(Offset); |
0 |
| 27494 |
// If there's a next interval, we should end before it. |
--- |
27494 |
// If there's a next interval, we should end before it. |
--- |
| 27495 |
if (I != Intervals.end() && I.start() < (Offset + Length)) |
0 |
27495 |
if (I != Intervals.end() && I.start() < (Offset + Length)) |
0 |
| 27496 |
break; |
0 |
27496 |
break; |
0 |
| 27497 |
// If there's a previous interval, we should start after it. |
--- |
27497 |
// If there's a previous interval, we should start after it. |
--- |
| 27498 |
if (I != Intervals.begin() && (--I).stop() <= Offset) |
0 |
27498 |
if (I != Intervals.begin() && (--I).stop() <= Offset) |
0 |
| 27499 |
break; |
0 |
27499 |
break; |
0 |
| 27500 |
Intervals.insert(Offset, Offset + Length, std::monostate{}); |
0 |
27500 |
Intervals.insert(Offset, Offset + Length, std::monostate{}); |
0 |
| 27501 |
|
--- |
27501 |
|
--- |
| 27502 |
ChainedStores.push_back(Chain); |
0 |
27502 |
ChainedStores.push_back(Chain); |
0 |
| 27503 |
STChain = Chain; |
0 |
27503 |
STChain = Chain; |
0 |
| 27504 |
} |
0 |
27504 |
} |
0 |
| 27505 |
|
--- |
27505 |
|
--- |
| 27506 |
// If we didn't find a chained store, exit. |
--- |
27506 |
// If we didn't find a chained store, exit. |
--- |
| 27507 |
if (ChainedStores.size() == 0) |
0 |
27507 |
if (ChainedStores.size() == 0) |
0 |
| 27508 |
return false; |
0 |
27508 |
return false; |
0 |
| 27509 |
|
--- |
27509 |
|
--- |
| 27510 |
// Improve all chained stores (St and ChainedStores members) starting from |
--- |
27510 |
// Improve all chained stores (St and ChainedStores members) starting from |
--- |
| 27511 |
// where the store chain ended and return single TokenFactor. |
--- |
27511 |
// where the store chain ended and return single TokenFactor. |
--- |
| 27512 |
SDValue NewChain = STChain->getChain(); |
0 |
27512 |
SDValue NewChain = STChain->getChain(); |
0 |
| 27513 |
SmallVector TFOps; |
0 |
27513 |
SmallVector TFOps; |
0 |
| 27514 |
for (unsigned I = ChainedStores.size(); I;) { |
0 |
27514 |
for (unsigned I = ChainedStores.size(); I;) { |
0 |
| 27515 |
StoreSDNode *S = ChainedStores[--I]; |
0 |
27515 |
StoreSDNode *S = ChainedStores[--I]; |
0 |
| 27516 |
SDValue BetterChain = FindBetterChain(S, NewChain); |
0 |
27516 |
SDValue BetterChain = FindBetterChain(S, NewChain); |
0 |
| 27517 |
S = cast(DAG.UpdateNodeOperands( |
0 |
27517 |
S = cast(DAG.UpdateNodeOperands( |
0 |
| 27518 |
S, BetterChain, S->getOperand(1), S->getOperand(2), S->getOperand(3))); |
0 |
27518 |
S, BetterChain, S->getOperand(1), S->getOperand(2), S->getOperand(3))); |
0 |
| 27519 |
TFOps.push_back(SDValue(S, 0)); |
0 |
27519 |
TFOps.push_back(SDValue(S, 0)); |
0 |
| 27520 |
ChainedStores[I] = S; |
0 |
27520 |
ChainedStores[I] = S; |
0 |
| 27521 |
} |
--- |
27521 |
} |
--- |
| 27522 |
|
--- |
27522 |
|
--- |
| 27523 |
// Improve St's chain. Use a new node to avoid creating a loop from CombineTo. |
--- |
27523 |
// Improve St's chain. Use a new node to avoid creating a loop from CombineTo. |
--- |
| 27524 |
SDValue BetterChain = FindBetterChain(St, NewChain); |
0 |
27524 |
SDValue BetterChain = FindBetterChain(St, NewChain); |
0 |
| 27525 |
SDValue NewST; |
0 |
27525 |
SDValue NewST; |
0 |
| 27526 |
if (St->isTruncatingStore()) |
0 |
27526 |
if (St->isTruncatingStore()) |
0 |
| 27527 |
NewST = DAG.getTruncStore(BetterChain, SDLoc(St), St->getValue(), |
0 |
27527 |
NewST = DAG.getTruncStore(BetterChain, SDLoc(St), St->getValue(), |
0 |
| 27528 |
St->getBasePtr(), St->getMemoryVT(), |
0 |
27528 |
St->getBasePtr(), St->getMemoryVT(), |
0 |
| 27529 |
St->getMemOperand()); |
--- |
27529 |
St->getMemOperand()); |
--- |
| 27530 |
else |
--- |
27530 |
else |
--- |
| 27531 |
NewST = DAG.getStore(BetterChain, SDLoc(St), St->getValue(), |
0 |
27531 |
NewST = DAG.getStore(BetterChain, SDLoc(St), St->getValue(), |
0 |
| 27532 |
St->getBasePtr(), St->getMemOperand()); |
0 |
27532 |
St->getBasePtr(), St->getMemOperand()); |
0 |
| 27533 |
|
--- |
27533 |
|
--- |
| 27534 |
TFOps.push_back(NewST); |
0 |
27534 |
TFOps.push_back(NewST); |
0 |
| 27535 |
|
--- |
27535 |
|
--- |
| 27536 |
// If we improved every element of TFOps, then we've lost the dependence on |
--- |
27536 |
// If we improved every element of TFOps, then we've lost the dependence on |
--- |
| 27537 |
// NewChain to successors of St and we need to add it back to TFOps. Do so at |
--- |
27537 |
// NewChain to successors of St and we need to add it back to TFOps. Do so at |
--- |
| 27538 |
// the beginning to keep relative order consistent with FindBetterChains. |
--- |
27538 |
// the beginning to keep relative order consistent with FindBetterChains. |
--- |
| 27539 |
auto hasImprovedChain = [&](SDValue ST) -> bool { |
0 |
27539 |
auto hasImprovedChain = [&](SDValue ST) -> bool { |
0 |
| 27540 |
return ST->getOperand(0) != NewChain; |
0 |
27540 |
return ST->getOperand(0) != NewChain; |
0 |
| 27541 |
}; |
0 |
27541 |
}; |
0 |
| 27542 |
bool AddNewChain = llvm::all_of(TFOps, hasImprovedChain); |
0 |
27542 |
bool AddNewChain = llvm::all_of(TFOps, hasImprovedChain); |
0 |
| 27543 |
if (AddNewChain) |
0 |
27543 |
if (AddNewChain) |
0 |
| 27544 |
TFOps.insert(TFOps.begin(), NewChain); |
0 |
27544 |
TFOps.insert(TFOps.begin(), NewChain); |
0 |
| 27545 |
|
--- |
27545 |
|
--- |
| 27546 |
SDValue TF = DAG.getTokenFactor(SDLoc(STChain), TFOps); |
0 |
27546 |
SDValue TF = DAG.getTokenFactor(SDLoc(STChain), TFOps); |
0 |
| 27547 |
CombineTo(St, TF); |
0 |
27547 |
CombineTo(St, TF); |
0 |
| 27548 |
|
--- |
27548 |
|
--- |
| 27549 |
// Add TF and its operands to the worklist. |
--- |
27549 |
// Add TF and its operands to the worklist. |
--- |
| 27550 |
AddToWorklist(TF.getNode()); |
0 |
27550 |
AddToWorklist(TF.getNode()); |
0 |
| 27551 |
for (const SDValue &Op : TF->ops()) |
0 |
27551 |
for (const SDValue &Op : TF->ops()) |
0 |
| 27552 |
AddToWorklist(Op.getNode()); |
0 |
27552 |
AddToWorklist(Op.getNode()); |
0 |
| 27553 |
AddToWorklist(STChain); |
0 |
27553 |
AddToWorklist(STChain); |
0 |
| 27554 |
return true; |
0 |
27554 |
return true; |
0 |
| 27555 |
} |
0 |
27555 |
} |
0 |
| 27556 |
|
--- |
27556 |
|
--- |
| 27557 |
bool DAGCombiner::findBetterNeighborChains(StoreSDNode *St) { |
10 |
27557 |
bool DAGCombiner::findBetterNeighborChains(StoreSDNode *St) { |
10 |
| 27558 |
if (OptLevel == CodeGenOpt::None) |
10 |
27558 |
if (OptLevel == CodeGenOpt::None) |
10 |
| 27559 |
return false; |
10 |
27559 |
return false; |
10 |
| 27560 |
|
--- |
27560 |
|
--- |
| 27561 |
const BaseIndexOffset BasePtr = BaseIndexOffset::match(St, DAG); |
0 |
27561 |
const BaseIndexOffset BasePtr = BaseIndexOffset::match(St, DAG); |
0 |
| 27562 |
|
--- |
27562 |
|
--- |
| 27563 |
// We must have a base and an offset. |
--- |
27563 |
// We must have a base and an offset. |
--- |
| 27564 |
if (!BasePtr.getBase().getNode()) |
0 |
27564 |
if (!BasePtr.getBase().getNode()) |
0 |
| 27565 |
return false; |
0 |
27565 |
return false; |
0 |
| 27566 |
|
--- |
27566 |
|
--- |
| 27567 |
// Do not handle stores to undef base pointers. |
--- |
27567 |
// Do not handle stores to undef base pointers. |
--- |
| 27568 |
if (BasePtr.getBase().isUndef()) |
0 |
27568 |
if (BasePtr.getBase().isUndef()) |
0 |
| 27569 |
return false; |
0 |
27569 |
return false; |
0 |
| 27570 |
|
--- |
27570 |
|
--- |
| 27571 |
// Directly improve a chain of disjoint stores starting at St. |
--- |
27571 |
// Directly improve a chain of disjoint stores starting at St. |
--- |
| 27572 |
if (parallelizeChainedStores(St)) |
0 |
27572 |
if (parallelizeChainedStores(St)) |
0 |
| 27573 |
return true; |
0 |
27573 |
return true; |
0 |
| 27574 |
|
--- |
27574 |
|
--- |
| 27575 |
// Improve St's Chain.. |
--- |
27575 |
// Improve St's Chain.. |
--- |
| 27576 |
SDValue BetterChain = FindBetterChain(St, St->getChain()); |
0 |
27576 |
SDValue BetterChain = FindBetterChain(St, St->getChain()); |
0 |
| 27577 |
if (St->getChain() != BetterChain) { |
0 |
27577 |
if (St->getChain() != BetterChain) { |
0 |
| 27578 |
replaceStoreChain(St, BetterChain); |
0 |
27578 |
replaceStoreChain(St, BetterChain); |
0 |
| 27579 |
return true; |
0 |
27579 |
return true; |
0 |
| 27580 |
} |
--- |
27580 |
} |
--- |
| 27581 |
return false; |
0 |
27581 |
return false; |
0 |
| 27582 |
} |
--- |
27582 |
} |
--- |
| 27583 |
|
--- |
27583 |
|
--- |
| 27584 |
/// This is the entry point for the file. |
--- |
27584 |
/// This is the entry point for the file. |
--- |
| 27585 |
void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis *AA, |
9 |
27585 |
void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis *AA, |
9 |
| 27586 |
CodeGenOpt::Level OptLevel) { |
--- |
27586 |
CodeGenOpt::Level OptLevel) { |
--- |
| 27587 |
/// This is the main entry point to this class. |
--- |
27587 |
/// This is the main entry point to this class. |
--- |
| 27588 |
DAGCombiner(*this, AA, OptLevel).Run(Level); |
9 |
27588 |
DAGCombiner(*this, AA, OptLevel).Run(Level); |
9 |
| 27589 |
} |
9 |
27589 |
} |
9 |
| 27590 |
|
--- |
27590 |
|
--- |